config.ini revision 5516
1[root] 2type=Root 3children=system 4dummy=0 5 6[system] 7type=System 8children=cpu membus physmem 9mem_mode=atomic 10physmem=system.physmem 11 12[system.cpu] 13type=DerivO3CPU 14children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload 15BTBEntries=4096 16BTBTagSize=16 17LFSTSize=1024 18LQEntries=32 19RASSize=16 20SQEntries=32 21SSITSize=1024 22activity=0 23backComSize=5 24cachePorts=200 25choiceCtrBits=2 26choicePredictorSize=8192 27clock=500 28commitToDecodeDelay=1 29commitToFetchDelay=1 30commitToIEWDelay=1 31commitToRenameDelay=1 32commitWidth=8 33cpu_id=0 34decodeToFetchDelay=1 35decodeToRenameDelay=1 36decodeWidth=8 37defer_registration=false 38dispatchWidth=8 39dtb=system.cpu.dtb 40fetchToDecodeDelay=1 41fetchTrapLatency=1 42fetchWidth=8 43forwardComSize=5 44fuPool=system.cpu.fuPool 45function_trace=false 46function_trace_start=0 47globalCtrBits=2 48globalHistoryBits=13 49globalPredictorSize=8192 50iewToCommitDelay=1 51iewToDecodeDelay=1 52iewToFetchDelay=1 53iewToRenameDelay=1 54instShiftAmt=2 55issueToExecuteDelay=1 56issueWidth=8 57itb=system.cpu.itb 58localCtrBits=2 59localHistoryBits=11 60localHistoryTableSize=2048 61localPredictorSize=2048 62max_insts_all_threads=0 63max_insts_any_thread=0 64max_loads_all_threads=0 65max_loads_any_thread=0 66numIQEntries=64 67numPhysFloatRegs=256 68numPhysIntRegs=256 69numROBEntries=192 70numRobs=1 71numThreads=1 72phase=0 73predType=tournament 74progress_interval=0 75renameToDecodeDelay=1 76renameToFetchDelay=1 77renameToIEWDelay=2 78renameToROBDelay=1 79renameWidth=8 80smtCommitPolicy=RoundRobin 81smtFetchPolicy=SingleThread 82smtIQPolicy=Partitioned 83smtIQThreshold=100 84smtLSQPolicy=Partitioned 85smtLSQThreshold=100 86smtNumFetchingThreads=1 87smtROBPolicy=Partitioned 88smtROBThreshold=100 89squashWidth=8 90system=system 91tracer=system.cpu.tracer 92trapLatency=13 93wbDepth=1 94wbWidth=8 95workload=system.cpu.workload 96dcache_port=system.cpu.dcache.cpu_side 97icache_port=system.cpu.icache.cpu_side 98 99[system.cpu.dcache] 100type=BaseCache 101addr_range=0:18446744073709551615 102assoc=2 103block_size=64 104cpu_side_filter_ranges= 105hash_delay=1 106latency=1000 107lifo=false 108max_miss_count=0 109mem_side_filter_ranges= 110mshrs=10 111prefetch_access=false 112prefetch_cache_check_push=true 113prefetch_data_accesses_only=false 114prefetch_degree=1 115prefetch_latency=10000 116prefetch_miss=false 117prefetch_past_page=false 118prefetch_policy=none 119prefetch_serial_squash=false 120prefetch_use_cpu_id=true 121prefetcher_size=100 122prioritizeRequests=false 123repl=Null 124size=262144 125split=false 126split_size=0 127subblock_size=0 128tgts_per_mshr=20 129trace_addr=0 130two_queue=false 131write_buffers=8 132cpu_side=system.cpu.dcache_port 133mem_side=system.cpu.toL2Bus.port[1] 134 135[system.cpu.dtb] 136type=AlphaDTB 137size=64 138 139[system.cpu.fuPool] 140type=FUPool 141children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 142FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 143 144[system.cpu.fuPool.FUList0] 145type=FUDesc 146children=opList 147count=6 148opList=system.cpu.fuPool.FUList0.opList 149 150[system.cpu.fuPool.FUList0.opList] 151type=OpDesc 152issueLat=1 153opClass=IntAlu 154opLat=1 155 156[system.cpu.fuPool.FUList1] 157type=FUDesc 158children=opList0 opList1 159count=2 160opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 161 162[system.cpu.fuPool.FUList1.opList0] 163type=OpDesc 164issueLat=1 165opClass=IntMult 166opLat=3 167 168[system.cpu.fuPool.FUList1.opList1] 169type=OpDesc 170issueLat=19 171opClass=IntDiv 172opLat=20 173 174[system.cpu.fuPool.FUList2] 175type=FUDesc 176children=opList0 opList1 opList2 177count=4 178opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 179 180[system.cpu.fuPool.FUList2.opList0] 181type=OpDesc 182issueLat=1 183opClass=FloatAdd 184opLat=2 185 186[system.cpu.fuPool.FUList2.opList1] 187type=OpDesc 188issueLat=1 189opClass=FloatCmp 190opLat=2 191 192[system.cpu.fuPool.FUList2.opList2] 193type=OpDesc 194issueLat=1 195opClass=FloatCvt 196opLat=2 197 198[system.cpu.fuPool.FUList3] 199type=FUDesc 200children=opList0 opList1 opList2 201count=2 202opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 203 204[system.cpu.fuPool.FUList3.opList0] 205type=OpDesc 206issueLat=1 207opClass=FloatMult 208opLat=4 209 210[system.cpu.fuPool.FUList3.opList1] 211type=OpDesc 212issueLat=12 213opClass=FloatDiv 214opLat=12 215 216[system.cpu.fuPool.FUList3.opList2] 217type=OpDesc 218issueLat=24 219opClass=FloatSqrt 220opLat=24 221 222[system.cpu.fuPool.FUList4] 223type=FUDesc 224children=opList 225count=0 226opList=system.cpu.fuPool.FUList4.opList 227 228[system.cpu.fuPool.FUList4.opList] 229type=OpDesc 230issueLat=1 231opClass=MemRead 232opLat=1 233 234[system.cpu.fuPool.FUList5] 235type=FUDesc 236children=opList 237count=0 238opList=system.cpu.fuPool.FUList5.opList 239 240[system.cpu.fuPool.FUList5.opList] 241type=OpDesc 242issueLat=1 243opClass=MemWrite 244opLat=1 245 246[system.cpu.fuPool.FUList6] 247type=FUDesc 248children=opList0 opList1 249count=4 250opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 251 252[system.cpu.fuPool.FUList6.opList0] 253type=OpDesc 254issueLat=1 255opClass=MemRead 256opLat=1 257 258[system.cpu.fuPool.FUList6.opList1] 259type=OpDesc 260issueLat=1 261opClass=MemWrite 262opLat=1 263 264[system.cpu.fuPool.FUList7] 265type=FUDesc 266children=opList 267count=1 268opList=system.cpu.fuPool.FUList7.opList 269 270[system.cpu.fuPool.FUList7.opList] 271type=OpDesc 272issueLat=3 273opClass=IprAccess 274opLat=3 275 276[system.cpu.icache] 277type=BaseCache 278addr_range=0:18446744073709551615 279assoc=2 280block_size=64 281cpu_side_filter_ranges= 282hash_delay=1 283latency=1000 284lifo=false 285max_miss_count=0 286mem_side_filter_ranges= 287mshrs=10 288prefetch_access=false 289prefetch_cache_check_push=true 290prefetch_data_accesses_only=false 291prefetch_degree=1 292prefetch_latency=10000 293prefetch_miss=false 294prefetch_past_page=false 295prefetch_policy=none 296prefetch_serial_squash=false 297prefetch_use_cpu_id=true 298prefetcher_size=100 299prioritizeRequests=false 300repl=Null 301size=131072 302split=false 303split_size=0 304subblock_size=0 305tgts_per_mshr=20 306trace_addr=0 307two_queue=false 308write_buffers=8 309cpu_side=system.cpu.icache_port 310mem_side=system.cpu.toL2Bus.port[0] 311 312[system.cpu.itb] 313type=AlphaITB 314size=48 315 316[system.cpu.l2cache] 317type=BaseCache 318addr_range=0:18446744073709551615 319assoc=2 320block_size=64 321cpu_side_filter_ranges= 322hash_delay=1 323latency=1000 324lifo=false 325max_miss_count=0 326mem_side_filter_ranges= 327mshrs=10 328prefetch_access=false 329prefetch_cache_check_push=true 330prefetch_data_accesses_only=false 331prefetch_degree=1 332prefetch_latency=10000 333prefetch_miss=false 334prefetch_past_page=false 335prefetch_policy=none 336prefetch_serial_squash=false 337prefetch_use_cpu_id=true 338prefetcher_size=100 339prioritizeRequests=false 340repl=Null 341size=2097152 342split=false 343split_size=0 344subblock_size=0 345tgts_per_mshr=5 346trace_addr=0 347two_queue=false 348write_buffers=8 349cpu_side=system.cpu.toL2Bus.port[2] 350mem_side=system.membus.port[1] 351 352[system.cpu.toL2Bus] 353type=Bus 354block_size=64 355bus_id=0 356clock=1000 357header_cycles=1 358responder_set=false 359width=64 360port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side 361 362[system.cpu.tracer] 363type=ExeTracer 364 365[system.cpu.workload] 366type=LiveProcess 367cmd=hello 368cwd= 369egid=100 370env= 371errout=cerr 372euid=100 373executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello 374gid=100 375input=cin 376max_stack_size=67108864 377output=cout 378pid=100 379ppid=99 380simpoint=0 381system=system 382uid=100 383 384[system.membus] 385type=Bus 386block_size=64 387bus_id=0 388clock=1000 389header_cycles=1 390responder_set=false 391width=64 392port=system.physmem.port[0] system.cpu.l2cache.mem_side 393 394[system.physmem] 395type=PhysicalMemory 396file= 397latency=1 398latency_var=0 399null=false 400range=0:134217727 401zero=false 402port=system.membus.port[0] 403 404