stats.txt revision 11606
13691SN/A 23691SN/A---------- Begin Simulation Statistics ---------- 39449SAli.Saidi@ARM.comsim_seconds 0.200409 # Number of seconds simulated 410409Sandreas.hansson@arm.comsim_ticks 200409271000 # Number of ticks simulated 510409Sandreas.hansson@arm.comfinal_tick 4321213476000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68721SN/Asim_freq 1000000000000 # Frequency of simulated ticks 711606Sandreas.sandberg@arm.comhost_inst_rate 11448115 # Simulator instruction rate (inst/s) 811606Sandreas.sandberg@arm.comhost_op_rate 11448111 # Simulator op (including micro ops) rate (op/s) 911606Sandreas.sandberg@arm.comhost_tick_rate 4380279881 # Simulator tick rate (ticks/s) 1011606Sandreas.sandberg@arm.comhost_mem_usage 499724 # Number of bytes of host memory used 1111606Sandreas.sandberg@arm.comhost_seconds 45.75 # Real time elapsed on the host 1210409Sandreas.hansson@arm.comsim_insts 523780905 # Number of instructions simulated 1310409Sandreas.hansson@arm.comsim_ops 523780905 # Number of ops (including micro ops) simulated 1410778Snilay@cs.wisc.edudrivesys.voltage_domain.voltage 1 # Voltage in Volts 1510778Snilay@cs.wisc.edudrivesys.clk_domain.clock 1000 # Clock period in ticks 1611530Sandreas.sandberg@arm.comdrivesys.physmem.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 1710778Snilay@cs.wisc.edudrivesys.physmem.bytes_read::cpu.inst 76205572 # Number of bytes read from this memory 1810778Snilay@cs.wisc.edudrivesys.physmem.bytes_read::cpu.data 26284292 # Number of bytes read from this memory 1910778Snilay@cs.wisc.edudrivesys.physmem.bytes_read::tsunami.ethernet 57260550 # Number of bytes read from this memory 2010778Snilay@cs.wisc.edudrivesys.physmem.bytes_read::total 159750414 # Number of bytes read from this memory 2110778Snilay@cs.wisc.edudrivesys.physmem.bytes_inst_read::cpu.inst 76205572 # Number of instructions bytes read from this memory 2210778Snilay@cs.wisc.edudrivesys.physmem.bytes_inst_read::total 76205572 # Number of instructions bytes read from this memory 2310778Snilay@cs.wisc.edudrivesys.physmem.bytes_written::cpu.data 14619632 # Number of bytes written to this memory 2410778Snilay@cs.wisc.edudrivesys.physmem.bytes_written::tsunami.ethernet 1064 # Number of bytes written to this memory 2510778Snilay@cs.wisc.edudrivesys.physmem.bytes_written::total 14620696 # Number of bytes written to this memory 2610778Snilay@cs.wisc.edudrivesys.physmem.num_reads::cpu.inst 19051393 # Number of read requests responded to by this memory 2710778Snilay@cs.wisc.edudrivesys.physmem.num_reads::cpu.data 3647049 # Number of read requests responded to by this memory 2810778Snilay@cs.wisc.edudrivesys.physmem.num_reads::tsunami.ethernet 2385839 # Number of read requests responded to by this memory 2910778Snilay@cs.wisc.edudrivesys.physmem.num_reads::total 25084281 # Number of read requests responded to by this memory 3010778Snilay@cs.wisc.edudrivesys.physmem.num_writes::cpu.data 2024776 # Number of write requests responded to by this memory 3110778Snilay@cs.wisc.edudrivesys.physmem.num_writes::tsunami.ethernet 37 # Number of write requests responded to by this memory 3210778Snilay@cs.wisc.edudrivesys.physmem.num_writes::total 2024813 # Number of write requests responded to by this memory 3310778Snilay@cs.wisc.edudrivesys.physmem.bw_read::cpu.inst 380249734 # Total read bandwidth from this memory (bytes/s) 3410778Snilay@cs.wisc.edudrivesys.physmem.bw_read::cpu.data 131153074 # Total read bandwidth from this memory (bytes/s) 3510778Snilay@cs.wisc.edudrivesys.physmem.bw_read::tsunami.ethernet 285718069 # Total read bandwidth from this memory (bytes/s) 3610778Snilay@cs.wisc.edudrivesys.physmem.bw_read::total 797120878 # Total read bandwidth from this memory (bytes/s) 3710778Snilay@cs.wisc.edudrivesys.physmem.bw_inst_read::cpu.inst 380249734 # Instruction read bandwidth from this memory (bytes/s) 3810778Snilay@cs.wisc.edudrivesys.physmem.bw_inst_read::total 380249734 # Instruction read bandwidth from this memory (bytes/s) 3910778Snilay@cs.wisc.edudrivesys.physmem.bw_write::cpu.data 72948881 # Write bandwidth from this memory (bytes/s) 4010778Snilay@cs.wisc.edudrivesys.physmem.bw_write::tsunami.ethernet 5309 # Write bandwidth from this memory (bytes/s) 4110778Snilay@cs.wisc.edudrivesys.physmem.bw_write::total 72954190 # Write bandwidth from this memory (bytes/s) 4210778Snilay@cs.wisc.edudrivesys.physmem.bw_total::cpu.inst 380249734 # Total bandwidth to/from this memory (bytes/s) 4310778Snilay@cs.wisc.edudrivesys.physmem.bw_total::cpu.data 204101955 # Total bandwidth to/from this memory (bytes/s) 4410778Snilay@cs.wisc.edudrivesys.physmem.bw_total::tsunami.ethernet 285723379 # Total bandwidth to/from this memory (bytes/s) 4510778Snilay@cs.wisc.edudrivesys.physmem.bw_total::total 870075068 # Total bandwidth to/from this memory (bytes/s) 4611530Sandreas.sandberg@arm.comdrivesys.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 4711530Sandreas.sandberg@arm.comdrivesys.bridge.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 4810778Snilay@cs.wisc.edudrivesys.cpu.clk_domain.clock 250 # Clock period in ticks 4910778Snilay@cs.wisc.edudrivesys.cpu.dtb.fetch_hits 0 # ITB hits 5010778Snilay@cs.wisc.edudrivesys.cpu.dtb.fetch_misses 0 # ITB misses 5110778Snilay@cs.wisc.edudrivesys.cpu.dtb.fetch_acv 0 # ITB acv 5210778Snilay@cs.wisc.edudrivesys.cpu.dtb.fetch_accesses 0 # ITB accesses 5310778Snilay@cs.wisc.edudrivesys.cpu.dtb.read_hits 3725273 # DTB read hits 5410778Snilay@cs.wisc.edudrivesys.cpu.dtb.read_misses 487 # DTB read misses 5510778Snilay@cs.wisc.edudrivesys.cpu.dtb.read_acv 30 # DTB read access violations 5610778Snilay@cs.wisc.edudrivesys.cpu.dtb.read_accesses 267991 # DTB read accesses 5710778Snilay@cs.wisc.edudrivesys.cpu.dtb.write_hits 2084079 # DTB write hits 5810778Snilay@cs.wisc.edudrivesys.cpu.dtb.write_misses 82 # DTB write misses 5910778Snilay@cs.wisc.edudrivesys.cpu.dtb.write_acv 10 # DTB write access violations 6010778Snilay@cs.wisc.edudrivesys.cpu.dtb.write_accesses 133239 # DTB write accesses 6110778Snilay@cs.wisc.edudrivesys.cpu.dtb.data_hits 5809352 # DTB hits 6210778Snilay@cs.wisc.edudrivesys.cpu.dtb.data_misses 569 # DTB misses 6310778Snilay@cs.wisc.edudrivesys.cpu.dtb.data_acv 40 # DTB access violations 6410778Snilay@cs.wisc.edudrivesys.cpu.dtb.data_accesses 401230 # DTB accesses 6510778Snilay@cs.wisc.edudrivesys.cpu.itb.fetch_hits 4197628 # ITB hits 6610778Snilay@cs.wisc.edudrivesys.cpu.itb.fetch_misses 194 # ITB misses 6710778Snilay@cs.wisc.edudrivesys.cpu.itb.fetch_acv 22 # ITB acv 6810778Snilay@cs.wisc.edudrivesys.cpu.itb.fetch_accesses 4197822 # ITB accesses 6910778Snilay@cs.wisc.edudrivesys.cpu.itb.read_hits 0 # DTB read hits 7010778Snilay@cs.wisc.edudrivesys.cpu.itb.read_misses 0 # DTB read misses 7110778Snilay@cs.wisc.edudrivesys.cpu.itb.read_acv 0 # DTB read access violations 7210778Snilay@cs.wisc.edudrivesys.cpu.itb.read_accesses 0 # DTB read accesses 7310778Snilay@cs.wisc.edudrivesys.cpu.itb.write_hits 0 # DTB write hits 7410778Snilay@cs.wisc.edudrivesys.cpu.itb.write_misses 0 # DTB write misses 7510778Snilay@cs.wisc.edudrivesys.cpu.itb.write_acv 0 # DTB write access violations 7610778Snilay@cs.wisc.edudrivesys.cpu.itb.write_accesses 0 # DTB write accesses 7710778Snilay@cs.wisc.edudrivesys.cpu.itb.data_hits 0 # DTB hits 7810778Snilay@cs.wisc.edudrivesys.cpu.itb.data_misses 0 # DTB misses 7910778Snilay@cs.wisc.edudrivesys.cpu.itb.data_acv 0 # DTB access violations 8010778Snilay@cs.wisc.edudrivesys.cpu.itb.data_accesses 0 # DTB accesses 8111530Sandreas.sandberg@arm.comdrivesys.cpu.numPwrStateTransitions 39752 # Number of power state transitions 8211530Sandreas.sandberg@arm.comdrivesys.cpu.pwrStateClkGateDist::samples 19877 # Distribution of time spent in the clock gated state 8311530Sandreas.sandberg@arm.comdrivesys.cpu.pwrStateClkGateDist::mean 9843365.409770 # Distribution of time spent in the clock gated state 8411530Sandreas.sandberg@arm.comdrivesys.cpu.pwrStateClkGateDist::stdev 830979.613808 # Distribution of time spent in the clock gated state 8511530Sandreas.sandberg@arm.comdrivesys.cpu.pwrStateClkGateDist::1000-5e+10 19877 100.00% 100.00% # Distribution of time spent in the clock gated state 8611530Sandreas.sandberg@arm.comdrivesys.cpu.pwrStateClkGateDist::min_value 25500 # Distribution of time spent in the clock gated state 8711530Sandreas.sandberg@arm.comdrivesys.cpu.pwrStateClkGateDist::max_value 9947500 # Distribution of time spent in the clock gated state 8811530Sandreas.sandberg@arm.comdrivesys.cpu.pwrStateClkGateDist::total 19877 # Distribution of time spent in the clock gated state 8911530Sandreas.sandberg@arm.comdrivesys.cpu.pwrStateResidencyTicks::ON 4757933250 # Cumulative time (in ticks) in various power states 9011530Sandreas.sandberg@arm.comdrivesys.cpu.pwrStateResidencyTicks::CLK_GATED 195656574250 # Cumulative time (in ticks) in various power states 9110778Snilay@cs.wisc.edudrivesys.cpu.numCycles 801651324 # number of cpu cycles simulated 9210778Snilay@cs.wisc.edudrivesys.cpu.numWorkItemsStarted 0 # number of work items this cpu started 9310778Snilay@cs.wisc.edudrivesys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 9410778Snilay@cs.wisc.edudrivesys.cpu.kern.inst.arm 0 # number of arm instructions executed 9510778Snilay@cs.wisc.edudrivesys.cpu.kern.inst.quiesce 19876 # number of quiesce instructions executed 9610778Snilay@cs.wisc.edudrivesys.cpu.kern.inst.hwrei 143591 # number of hwrei instructions executed 9710778Snilay@cs.wisc.edudrivesys.cpu.kern.ipl_count::0 60359 42.42% 42.42% # number of times we switched to this ipl 9810778Snilay@cs.wisc.edudrivesys.cpu.kern.ipl_count::21 19727 13.86% 56.28% # number of times we switched to this ipl 9910778Snilay@cs.wisc.edudrivesys.cpu.kern.ipl_count::22 205 0.14% 56.42% # number of times we switched to this ipl 10010778Snilay@cs.wisc.edudrivesys.cpu.kern.ipl_count::31 62011 43.58% 100.00% # number of times we switched to this ipl 10110778Snilay@cs.wisc.edudrivesys.cpu.kern.ipl_count::total 142302 # number of times we switched to this ipl 10210778Snilay@cs.wisc.edudrivesys.cpu.kern.ipl_good::0 60359 42.91% 42.91% # number of times we switched to this ipl from a different ipl 10310778Snilay@cs.wisc.edudrivesys.cpu.kern.ipl_good::21 19727 14.03% 56.94% # number of times we switched to this ipl from a different ipl 10410778Snilay@cs.wisc.edudrivesys.cpu.kern.ipl_good::22 205 0.15% 57.09% # number of times we switched to this ipl from a different ipl 10510778Snilay@cs.wisc.edudrivesys.cpu.kern.ipl_good::31 60360 42.91% 100.00% # number of times we switched to this ipl from a different ipl 10610778Snilay@cs.wisc.edudrivesys.cpu.kern.ipl_good::total 140651 # number of times we switched to this ipl from a different ipl 10710778Snilay@cs.wisc.edudrivesys.cpu.kern.ipl_ticks::0 197399332500 98.50% 98.50% # number of cycles we spent at this ipl 10810778Snilay@cs.wisc.edudrivesys.cpu.kern.ipl_ticks::21 798910750 0.40% 98.90% # number of cycles we spent at this ipl 10910778Snilay@cs.wisc.edudrivesys.cpu.kern.ipl_ticks::22 4407500 0.00% 98.90% # number of cycles we spent at this ipl 11010778Snilay@cs.wisc.edudrivesys.cpu.kern.ipl_ticks::31 2205211250 1.10% 100.00% # number of cycles we spent at this ipl 11110778Snilay@cs.wisc.edudrivesys.cpu.kern.ipl_ticks::total 200407862000 # number of cycles we spent at this ipl 11210778Snilay@cs.wisc.edudrivesys.cpu.kern.ipl_used::0 1 # fraction of swpipl calls that actually changed the ipl 11310778Snilay@cs.wisc.edudrivesys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 11410778Snilay@cs.wisc.edudrivesys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 11510778Snilay@cs.wisc.edudrivesys.cpu.kern.ipl_used::31 0.973376 # fraction of swpipl calls that actually changed the ipl 11610778Snilay@cs.wisc.edudrivesys.cpu.kern.ipl_used::total 0.988398 # fraction of swpipl calls that actually changed the ipl 11710778Snilay@cs.wisc.edudrivesys.cpu.kern.syscall::2 1 4.55% 4.55% # number of syscalls executed 11810778Snilay@cs.wisc.edudrivesys.cpu.kern.syscall::6 3 13.64% 18.18% # number of syscalls executed 11910778Snilay@cs.wisc.edudrivesys.cpu.kern.syscall::17 2 9.09% 27.27% # number of syscalls executed 12010778Snilay@cs.wisc.edudrivesys.cpu.kern.syscall::97 1 4.55% 31.82% # number of syscalls executed 12110778Snilay@cs.wisc.edudrivesys.cpu.kern.syscall::99 2 9.09% 40.91% # number of syscalls executed 12210778Snilay@cs.wisc.edudrivesys.cpu.kern.syscall::101 2 9.09% 50.00% # number of syscalls executed 12310778Snilay@cs.wisc.edudrivesys.cpu.kern.syscall::102 3 13.64% 63.64% # number of syscalls executed 12410778Snilay@cs.wisc.edudrivesys.cpu.kern.syscall::104 1 4.55% 68.18% # number of syscalls executed 12510778Snilay@cs.wisc.edudrivesys.cpu.kern.syscall::105 3 13.64% 81.82% # number of syscalls executed 12610778Snilay@cs.wisc.edudrivesys.cpu.kern.syscall::106 1 4.55% 86.36% # number of syscalls executed 12710778Snilay@cs.wisc.edudrivesys.cpu.kern.syscall::118 2 9.09% 95.45% # number of syscalls executed 12810778Snilay@cs.wisc.edudrivesys.cpu.kern.syscall::150 1 4.55% 100.00% # number of syscalls executed 12910778Snilay@cs.wisc.edudrivesys.cpu.kern.syscall::total 22 # number of syscalls executed 13010778Snilay@cs.wisc.edudrivesys.cpu.kern.callpal::swpctx 72 0.06% 0.06% # number of callpals executed 13110778Snilay@cs.wisc.edudrivesys.cpu.kern.callpal::tbi 5 0.00% 0.06% # number of callpals executed 13210778Snilay@cs.wisc.edudrivesys.cpu.kern.callpal::swpipl 102333 83.31% 83.37% # number of callpals executed 13310778Snilay@cs.wisc.edudrivesys.cpu.kern.callpal::rdps 354 0.29% 83.66% # number of callpals executed 13410778Snilay@cs.wisc.edudrivesys.cpu.kern.callpal::rdusp 1 0.00% 83.66% # number of callpals executed 13510778Snilay@cs.wisc.edudrivesys.cpu.kern.callpal::rti 20038 16.31% 99.97% # number of callpals executed 13610778Snilay@cs.wisc.edudrivesys.cpu.kern.callpal::callsys 25 0.02% 99.99% # number of callpals executed 13710778Snilay@cs.wisc.edudrivesys.cpu.kern.callpal::imb 7 0.01% 100.00% # number of callpals executed 13810778Snilay@cs.wisc.edudrivesys.cpu.kern.callpal::total 122835 # number of callpals executed 13910778Snilay@cs.wisc.edudrivesys.cpu.kern.mode_switch::kernel 214 # number of protection mode switches 14010778Snilay@cs.wisc.edudrivesys.cpu.kern.mode_switch::user 140 # number of protection mode switches 14110778Snilay@cs.wisc.edudrivesys.cpu.kern.mode_switch::idle 19896 # number of protection mode switches 14210778Snilay@cs.wisc.edudrivesys.cpu.kern.mode_good::kernel 144 14310778Snilay@cs.wisc.edudrivesys.cpu.kern.mode_good::user 140 14410778Snilay@cs.wisc.edudrivesys.cpu.kern.mode_good::idle 4 14510778Snilay@cs.wisc.edudrivesys.cpu.kern.mode_switch_good::kernel 0.672897 # fraction of useful protection mode switches 14610778Snilay@cs.wisc.edudrivesys.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 14710778Snilay@cs.wisc.edudrivesys.cpu.kern.mode_switch_good::idle 0.000201 # fraction of useful protection mode switches 14810778Snilay@cs.wisc.edudrivesys.cpu.kern.mode_switch_good::total 0.014222 # fraction of useful protection mode switches 14910778Snilay@cs.wisc.edudrivesys.cpu.kern.mode_ticks::kernel 78134250 2.63% 2.63% # number of ticks spent at the given mode 15010778Snilay@cs.wisc.edudrivesys.cpu.kern.mode_ticks::user 319668250 10.78% 13.41% # number of ticks spent at the given mode 15110778Snilay@cs.wisc.edudrivesys.cpu.kern.mode_ticks::idle 2567942000 86.59% 100.00% # number of ticks spent at the given mode 15210778Snilay@cs.wisc.edudrivesys.cpu.kern.swap_context 72 # number of times the context was actually changed 15311245Sandreas.sandberg@arm.comdrivesys.cpu.committedInsts 19050784 # Number of instructions committed 15411245Sandreas.sandberg@arm.comdrivesys.cpu.committedOps 19050784 # Number of ops (including micro ops) committed 15511245Sandreas.sandberg@arm.comdrivesys.cpu.num_int_alu_accesses 17740632 # Number of integer alu accesses 15611245Sandreas.sandberg@arm.comdrivesys.cpu.num_fp_alu_accesses 1412 # Number of float alu accesses 15711245Sandreas.sandberg@arm.comdrivesys.cpu.num_func_calls 1265024 # number of times a function call or return occured 15811245Sandreas.sandberg@arm.comdrivesys.cpu.num_conditional_control_insts 1264985 # number of instructions that are conditional controls 15911245Sandreas.sandberg@arm.comdrivesys.cpu.num_int_insts 17740632 # number of integer instructions 16011245Sandreas.sandberg@arm.comdrivesys.cpu.num_fp_insts 1412 # number of float instructions 16111245Sandreas.sandberg@arm.comdrivesys.cpu.num_int_register_reads 23072330 # number of times the integer registers were read 16211245Sandreas.sandberg@arm.comdrivesys.cpu.num_int_register_writes 13981107 # number of times the integer registers were written 16311245Sandreas.sandberg@arm.comdrivesys.cpu.num_fp_register_reads 760 # number of times the floating registers were read 16411245Sandreas.sandberg@arm.comdrivesys.cpu.num_fp_register_writes 766 # number of times the floating registers were written 16511245Sandreas.sandberg@arm.comdrivesys.cpu.num_mem_refs 5830788 # number of memory refs 16611245Sandreas.sandberg@arm.comdrivesys.cpu.num_load_insts 3746196 # Number of load instructions 16711245Sandreas.sandberg@arm.comdrivesys.cpu.num_store_insts 2084592 # Number of store instructions 16811245Sandreas.sandberg@arm.comdrivesys.cpu.num_idle_cycles 782619252.927065 # Number of idle cycles 16911245Sandreas.sandberg@arm.comdrivesys.cpu.num_busy_cycles 19032071.072935 # Number of busy cycles 17011245Sandreas.sandberg@arm.comdrivesys.cpu.not_idle_fraction 0.023741 # Percentage of non-idle cycles 17111245Sandreas.sandberg@arm.comdrivesys.cpu.idle_fraction 0.976259 # Percentage of idle cycles 17211245Sandreas.sandberg@arm.comdrivesys.cpu.Branches 2793313 # Number of branches fetched 17311245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::No_OpClass 623554 3.27% 3.27% # Class of executed instruction 17411245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::IntAlu 11538627 60.57% 63.84% # Class of executed instruction 17511245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::IntMult 20663 0.11% 63.95% # Class of executed instruction 17611245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::IntDiv 0 0.00% 63.95% # Class of executed instruction 17711245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::FloatAdd 141 0.00% 63.95% # Class of executed instruction 17811245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::FloatCmp 0 0.00% 63.95% # Class of executed instruction 17911245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::FloatCvt 0 0.00% 63.95% # Class of executed instruction 18011245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::FloatMult 0 0.00% 63.95% # Class of executed instruction 18111245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::FloatDiv 23 0.00% 63.95% # Class of executed instruction 18211245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::FloatSqrt 0 0.00% 63.95% # Class of executed instruction 18311245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::SimdAdd 0 0.00% 63.95% # Class of executed instruction 18411245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::SimdAddAcc 0 0.00% 63.95% # Class of executed instruction 18511245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::SimdAlu 0 0.00% 63.95% # Class of executed instruction 18611245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::SimdCmp 0 0.00% 63.95% # Class of executed instruction 18711245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::SimdCvt 0 0.00% 63.95% # Class of executed instruction 18811245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::SimdMisc 0 0.00% 63.95% # Class of executed instruction 18911245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::SimdMult 0 0.00% 63.95% # Class of executed instruction 19011245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::SimdMultAcc 0 0.00% 63.95% # Class of executed instruction 19111245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::SimdShift 0 0.00% 63.95% # Class of executed instruction 19211245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::SimdShiftAcc 0 0.00% 63.95% # Class of executed instruction 19311245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::SimdSqrt 0 0.00% 63.95% # Class of executed instruction 19411245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::SimdFloatAdd 0 0.00% 63.95% # Class of executed instruction 19511245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::SimdFloatAlu 0 0.00% 63.95% # Class of executed instruction 19611245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::SimdFloatCmp 0 0.00% 63.95% # Class of executed instruction 19711245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::SimdFloatCvt 0 0.00% 63.95% # Class of executed instruction 19811245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::SimdFloatDiv 0 0.00% 63.95% # Class of executed instruction 19911245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::SimdFloatMisc 0 0.00% 63.95% # Class of executed instruction 20011245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::SimdFloatMult 0 0.00% 63.95% # Class of executed instruction 20111245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.95% # Class of executed instruction 20211245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::SimdFloatSqrt 0 0.00% 63.95% # Class of executed instruction 20311245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::MemRead 4026028 21.13% 85.08% # Class of executed instruction 20411245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::MemWrite 2085021 10.94% 96.02% # Class of executed instruction 20511245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::IprAccess 757336 3.98% 100.00% # Class of executed instruction 20611245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 20711245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::total 19051393 # Class of executed instruction 20810778Snilay@cs.wisc.edudrivesys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 20910778Snilay@cs.wisc.edudrivesys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 21010778Snilay@cs.wisc.edudrivesys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 21110778Snilay@cs.wisc.edudrivesys.disk0.dma_write_full_pages 0 # Number of full page size DMA writes. 21210778Snilay@cs.wisc.edudrivesys.disk0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 21310778Snilay@cs.wisc.edudrivesys.disk0.dma_write_txs 0 # Number of DMA write transactions. 21410778Snilay@cs.wisc.edudrivesys.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 21510778Snilay@cs.wisc.edudrivesys.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 21610778Snilay@cs.wisc.edudrivesys.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 21710778Snilay@cs.wisc.edudrivesys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes. 21810778Snilay@cs.wisc.edudrivesys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 21910778Snilay@cs.wisc.edudrivesys.disk2.dma_write_txs 0 # Number of DMA write transactions. 22011530Sandreas.sandberg@arm.comdrivesys.iobridge.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 22111530Sandreas.sandberg@arm.comdrivesys.iobus.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 22210778Snilay@cs.wisc.edudrivesys.iobus.trans_dist::ReadReq 2484469 # Transaction distribution 22310778Snilay@cs.wisc.edudrivesys.iobus.trans_dist::ReadResp 2484469 # Transaction distribution 22410778Snilay@cs.wisc.edudrivesys.iobus.trans_dist::WriteReq 39723 # Transaction distribution 22510778Snilay@cs.wisc.edudrivesys.iobus.trans_dist::WriteResp 39723 # Transaction distribution 22610778Snilay@cs.wisc.edudrivesys.iobus.pkt_count_drivesys.bridge.master::drivesys.tsunami.cchip.pio 197670 # Packet count per connected master and slave (bytes) 22710778Snilay@cs.wisc.edudrivesys.iobus.pkt_count_drivesys.bridge.master::drivesys.tsunami.ethernet.pio 78962 # Packet count per connected master and slave (bytes) 22810778Snilay@cs.wisc.edudrivesys.iobus.pkt_count_drivesys.bridge.master::total 276632 # Packet count per connected master and slave (bytes) 22910778Snilay@cs.wisc.edudrivesys.iobus.pkt_count_drivesys.tsunami.ethernet.dma::drivesys.iobridge.slave 4771752 # Packet count per connected master and slave (bytes) 23010778Snilay@cs.wisc.edudrivesys.iobus.pkt_count_drivesys.tsunami.ethernet.dma::total 4771752 # Packet count per connected master and slave (bytes) 23110778Snilay@cs.wisc.edudrivesys.iobus.pkt_count::total 5048384 # Packet count per connected master and slave (bytes) 23210778Snilay@cs.wisc.edudrivesys.iobus.pkt_size_drivesys.bridge.master::drivesys.tsunami.cchip.pio 790680 # Cumulative packet size per connected master and slave (bytes) 23310778Snilay@cs.wisc.edudrivesys.iobus.pkt_size_drivesys.bridge.master::drivesys.tsunami.ethernet.pio 157924 # Cumulative packet size per connected master and slave (bytes) 23410778Snilay@cs.wisc.edudrivesys.iobus.pkt_size_drivesys.bridge.master::total 948604 # Cumulative packet size per connected master and slave (bytes) 23510778Snilay@cs.wisc.edudrivesys.iobus.pkt_size_drivesys.tsunami.ethernet.dma::drivesys.iobridge.slave 57261614 # Cumulative packet size per connected master and slave (bytes) 23610778Snilay@cs.wisc.edudrivesys.iobus.pkt_size_drivesys.tsunami.ethernet.dma::total 57261614 # Cumulative packet size per connected master and slave (bytes) 23710778Snilay@cs.wisc.edudrivesys.iobus.pkt_size::total 58210218 # Cumulative packet size per connected master and slave (bytes) 23811606Sandreas.sandberg@arm.comdrivesys.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. 23911606Sandreas.sandberg@arm.comdrivesys.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 24011606Sandreas.sandberg@arm.comdrivesys.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 24111606Sandreas.sandberg@arm.comdrivesys.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 24211606Sandreas.sandberg@arm.comdrivesys.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 24311606Sandreas.sandberg@arm.comdrivesys.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 24411530Sandreas.sandberg@arm.comdrivesys.membus.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 24510778Snilay@cs.wisc.edudrivesys.membus.trans_dist::ReadReq 25081955 # Transaction distribution 24610778Snilay@cs.wisc.edudrivesys.membus.trans_dist::ReadResp 25182911 # Transaction distribution 24710778Snilay@cs.wisc.edudrivesys.membus.trans_dist::WriteReq 1963575 # Transaction distribution 24810778Snilay@cs.wisc.edudrivesys.membus.trans_dist::WriteResp 1963575 # Transaction distribution 24910778Snilay@cs.wisc.edudrivesys.membus.trans_dist::LoadLockedReq 100956 # Transaction distribution 25010778Snilay@cs.wisc.edudrivesys.membus.trans_dist::StoreCondReq 100924 # Transaction distribution 25110778Snilay@cs.wisc.edudrivesys.membus.trans_dist::StoreCondResp 100924 # Transaction distribution 25210778Snilay@cs.wisc.edudrivesys.membus.pkt_count_drivesys.cpu.icache_port::drivesys.physmem.port 38102786 # Packet count per connected master and slave (bytes) 25310778Snilay@cs.wisc.edudrivesys.membus.pkt_count_drivesys.cpu.icache_port::total 38102786 # Packet count per connected master and slave (bytes) 25410778Snilay@cs.wisc.edudrivesys.membus.pkt_count_drivesys.cpu.dcache_port::drivesys.bridge.slave 276632 # Packet count per connected master and slave (bytes) 25510778Snilay@cs.wisc.edudrivesys.membus.pkt_count_drivesys.cpu.dcache_port::drivesys.physmem.port 11343650 # Packet count per connected master and slave (bytes) 25610778Snilay@cs.wisc.edudrivesys.membus.pkt_count_drivesys.cpu.dcache_port::total 11620282 # Packet count per connected master and slave (bytes) 25710778Snilay@cs.wisc.edudrivesys.membus.pkt_count_drivesys.iobridge.master::drivesys.physmem.port 4771752 # Packet count per connected master and slave (bytes) 25810778Snilay@cs.wisc.edudrivesys.membus.pkt_count_drivesys.iobridge.master::total 4771752 # Packet count per connected master and slave (bytes) 25910778Snilay@cs.wisc.edudrivesys.membus.pkt_count::total 54494820 # Packet count per connected master and slave (bytes) 26010778Snilay@cs.wisc.edudrivesys.membus.pkt_size_drivesys.cpu.icache_port::drivesys.physmem.port 76205572 # Cumulative packet size per connected master and slave (bytes) 26110778Snilay@cs.wisc.edudrivesys.membus.pkt_size_drivesys.cpu.icache_port::total 76205572 # Cumulative packet size per connected master and slave (bytes) 26210778Snilay@cs.wisc.edudrivesys.membus.pkt_size_drivesys.cpu.dcache_port::drivesys.bridge.slave 948604 # Cumulative packet size per connected master and slave (bytes) 26310778Snilay@cs.wisc.edudrivesys.membus.pkt_size_drivesys.cpu.dcache_port::drivesys.physmem.port 40903924 # Cumulative packet size per connected master and slave (bytes) 26410778Snilay@cs.wisc.edudrivesys.membus.pkt_size_drivesys.cpu.dcache_port::total 41852528 # Cumulative packet size per connected master and slave (bytes) 26510778Snilay@cs.wisc.edudrivesys.membus.pkt_size_drivesys.iobridge.master::drivesys.physmem.port 57261614 # Cumulative packet size per connected master and slave (bytes) 26610778Snilay@cs.wisc.edudrivesys.membus.pkt_size_drivesys.iobridge.master::total 57261614 # Cumulative packet size per connected master and slave (bytes) 26710778Snilay@cs.wisc.edudrivesys.membus.pkt_size::total 175319714 # Cumulative packet size per connected master and slave (bytes) 26810778Snilay@cs.wisc.edudrivesys.membus.snoops 0 # Total snoops (count) 26911570SCurtis.Dunham@arm.comdrivesys.membus.snoopTraffic 0 # Total snoop traffic (bytes) 27010827Sandreas.hansson@arm.comdrivesys.membus.snoop_fanout::samples 27247410 # Request fanout histogram 27111606Sandreas.sandberg@arm.comdrivesys.membus.snoop_fanout::mean 0 # Request fanout histogram 27211606Sandreas.sandberg@arm.comdrivesys.membus.snoop_fanout::stdev 0 # Request fanout histogram 27310778Snilay@cs.wisc.edudrivesys.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 27411606Sandreas.sandberg@arm.comdrivesys.membus.snoop_fanout::0 27247410 100.00% 100.00% # Request fanout histogram 27511606Sandreas.sandberg@arm.comdrivesys.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 27610778Snilay@cs.wisc.edudrivesys.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 27710778Snilay@cs.wisc.edudrivesys.membus.snoop_fanout::min_value 0 # Request fanout histogram 27811606Sandreas.sandberg@arm.comdrivesys.membus.snoop_fanout::max_value 0 # Request fanout histogram 27910827Sandreas.hansson@arm.comdrivesys.membus.snoop_fanout::total 27247410 # Request fanout histogram 28011530Sandreas.sandberg@arm.comdrivesys.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 28111530Sandreas.sandberg@arm.comdrivesys.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 28211530Sandreas.sandberg@arm.comdrivesys.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 28310778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.clk_domain.clock 2000 # Clock period in ticks 28411530Sandreas.sandberg@arm.comdrivesys.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 28511530Sandreas.sandberg@arm.comdrivesys.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 28610778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.txBytes 798 # Bytes Transmitted 28710778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.rxBytes 960 # Bytes Received 28810778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.txPackets 5 # Number of Packets Transmitted 28910778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.rxPackets 8 # Number of Packets Received 29010778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.txIpChecksums 2 # Number of tx IP Checksums done by device 29110778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.rxIpChecksums 8 # Number of rx IP Checksums done by device 29210778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.txTcpChecksums 2 # Number of tx TCP Checksums done by device 29310778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.rxTcpChecksums 8 # Number of rx TCP Checksums done by device 29410778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 29510778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.rxUdpChecksums 0 # Number of rx UDP Checksums done by device 29610778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.descDMAReads 2385810 # Number of descriptors the device read w/ DMA 29710778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.descDMAWrites 13 # Number of descriptors the device wrote w/ DMA 29810778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.descDmaReadBytes 57259440 # number of descriptor bytes read w/ DMA 29910778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.descDmaWriteBytes 104 # number of descriptor bytes write w/ DMA 30010778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.totBandwidth 70176 # Total Bandwidth (bits/s) 30110778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.totPackets 13 # Total Packets 30210778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.totBytes 1758 # Total Bytes 30310778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.totPPS 65 # Total Tranmission Rate (packets/s) 30410778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.txBandwidth 31855 # Transmit Bandwidth (bits/s) 30510778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.rxBandwidth 38322 # Receive Bandwidth (bits/s) 30610778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.txPPS 25 # Packet Tranmission Rate (packets/s) 30710778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.rxPPS 40 # Packet Reception Rate (packets/s) 30810778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 30910778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 31010778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 31110778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 31210778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 31310778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 31410778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 31510778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 31610778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 31710778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.postedRxDesc 8 # number of RxDesc interrupts posted to CPU 31810778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 31910778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.totalRxDesc 8 # total number of RxDesc written to ISR 32010778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 32110778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 32210778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 32310778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.postedTxIdle 19726 # number of TxIdle interrupts posted to CPU 32410778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post 32510778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.totalTxIdle 2385810 # total number of TxIdle written to ISR 32610778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 32710778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 32810778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 32910778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 33010778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 33110778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 33210778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post 33310778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.postedInterrupts 2385831 # number of posts to CPU 33410778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.droppedPackets 0 # number of packets dropped 33511530Sandreas.sandberg@arm.comdrivesys.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 33611530Sandreas.sandberg@arm.comdrivesys.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 33711530Sandreas.sandberg@arm.comdrivesys.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 33811530Sandreas.sandberg@arm.comdrivesys.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 33911530Sandreas.sandberg@arm.comdrivesys.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 34011530Sandreas.sandberg@arm.comdrivesys.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 34111530Sandreas.sandberg@arm.comdrivesys.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 34211530Sandreas.sandberg@arm.comdrivesys.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 34311530Sandreas.sandberg@arm.comdrivesys.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 34411530Sandreas.sandberg@arm.comdrivesys.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 34511530Sandreas.sandberg@arm.comdrivesys.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 34611530Sandreas.sandberg@arm.comdrivesys.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 34711530Sandreas.sandberg@arm.comdrivesys.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 34811530Sandreas.sandberg@arm.comdrivesys.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 34911530Sandreas.sandberg@arm.comdrivesys.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 35011530Sandreas.sandberg@arm.comdrivesys.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 35111530Sandreas.sandberg@arm.comdrivesys.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 35211530Sandreas.sandberg@arm.comdrivesys.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 35311530Sandreas.sandberg@arm.comdrivesys.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 35411530Sandreas.sandberg@arm.comdrivesys.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 35511530Sandreas.sandberg@arm.comdrivesys.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 35611530Sandreas.sandberg@arm.comdrivesys.tsunami.io.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 35711530Sandreas.sandberg@arm.comdrivesys.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 35810036SAli.Saidi@ARM.comtestsys.voltage_domain.voltage 1 # Voltage in Volts 35910036SAli.Saidi@ARM.comtestsys.clk_domain.clock 1000 # Clock period in ticks 36011530Sandreas.sandberg@arm.comtestsys.physmem.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 36110409Sandreas.hansson@arm.comtestsys.physmem.bytes_read::cpu.inst 81044080 # Number of bytes read from this memory 36210409Sandreas.hansson@arm.comtestsys.physmem.bytes_read::cpu.data 27825116 # Number of bytes read from this memory 3639729Sandreas.hansson@arm.comtestsys.physmem.bytes_read::tsunami.ethernet 57260496 # Number of bytes read from this memory 36410409Sandreas.hansson@arm.comtestsys.physmem.bytes_read::total 166129692 # Number of bytes read from this memory 36510409Sandreas.hansson@arm.comtestsys.physmem.bytes_inst_read::cpu.inst 81044080 # Number of instructions bytes read from this memory 36610409Sandreas.hansson@arm.comtestsys.physmem.bytes_inst_read::total 81044080 # Number of instructions bytes read from this memory 36710409Sandreas.hansson@arm.comtestsys.physmem.bytes_written::cpu.data 16605404 # Number of bytes written to this memory 3689055Ssaidi@eecs.umich.edutestsys.physmem.bytes_written::tsunami.ethernet 902 # Number of bytes written to this memory 36910409Sandreas.hansson@arm.comtestsys.physmem.bytes_written::total 16606306 # Number of bytes written to this memory 37010409Sandreas.hansson@arm.comtestsys.physmem.num_reads::cpu.inst 20261020 # Number of read requests responded to by this memory 37110409Sandreas.hansson@arm.comtestsys.physmem.num_reads::cpu.data 3842409 # Number of read requests responded to by this memory 3729729Sandreas.hansson@arm.comtestsys.physmem.num_reads::tsunami.ethernet 2385836 # Number of read requests responded to by this memory 37310409Sandreas.hansson@arm.comtestsys.physmem.num_reads::total 26489265 # Number of read requests responded to by this memory 37410409Sandreas.hansson@arm.comtestsys.physmem.num_writes::cpu.data 2258228 # Number of write requests responded to by this memory 3759055Ssaidi@eecs.umich.edutestsys.physmem.num_writes::tsunami.ethernet 31 # Number of write requests responded to by this memory 37610409Sandreas.hansson@arm.comtestsys.physmem.num_writes::total 2258259 # Number of write requests responded to by this memory 37710409Sandreas.hansson@arm.comtestsys.physmem.bw_read::cpu.inst 404392869 # Total read bandwidth from this memory (bytes/s) 37810409Sandreas.hansson@arm.comtestsys.physmem.bw_read::cpu.data 138841461 # Total read bandwidth from this memory (bytes/s) 37910409Sandreas.hansson@arm.comtestsys.physmem.bw_read::tsunami.ethernet 285717800 # Total read bandwidth from this memory (bytes/s) 38010409Sandreas.hansson@arm.comtestsys.physmem.bw_read::total 828952130 # Total read bandwidth from this memory (bytes/s) 38110409Sandreas.hansson@arm.comtestsys.physmem.bw_inst_read::cpu.inst 404392869 # Instruction read bandwidth from this memory (bytes/s) 38210409Sandreas.hansson@arm.comtestsys.physmem.bw_inst_read::total 404392869 # Instruction read bandwidth from this memory (bytes/s) 38310409Sandreas.hansson@arm.comtestsys.physmem.bw_write::cpu.data 82857464 # Write bandwidth from this memory (bytes/s) 3849247Sandreas.hansson@arm.comtestsys.physmem.bw_write::tsunami.ethernet 4501 # Write bandwidth from this memory (bytes/s) 38510409Sandreas.hansson@arm.comtestsys.physmem.bw_write::total 82861965 # Write bandwidth from this memory (bytes/s) 38610409Sandreas.hansson@arm.comtestsys.physmem.bw_total::cpu.inst 404392869 # Total bandwidth to/from this memory (bytes/s) 38710409Sandreas.hansson@arm.comtestsys.physmem.bw_total::cpu.data 221698925 # Total bandwidth to/from this memory (bytes/s) 38810409Sandreas.hansson@arm.comtestsys.physmem.bw_total::tsunami.ethernet 285722301 # Total bandwidth to/from this memory (bytes/s) 38910409Sandreas.hansson@arm.comtestsys.physmem.bw_total::total 911814095 # Total bandwidth to/from this memory (bytes/s) 39011530Sandreas.sandberg@arm.comtestsys.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 39111530Sandreas.sandberg@arm.comtestsys.bridge.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 39210036SAli.Saidi@ARM.comtestsys.cpu.clk_domain.clock 500 # Clock period in ticks 3938721SN/Atestsys.cpu.dtb.fetch_hits 0 # ITB hits 3948721SN/Atestsys.cpu.dtb.fetch_misses 0 # ITB misses 3958721SN/Atestsys.cpu.dtb.fetch_acv 0 # ITB acv 3968721SN/Atestsys.cpu.dtb.fetch_accesses 0 # ITB accesses 39710409Sandreas.hansson@arm.comtestsys.cpu.dtb.read_hits 3916768 # DTB read hits 3988721SN/Atestsys.cpu.dtb.read_misses 3287 # DTB read misses 3998721SN/Atestsys.cpu.dtb.read_acv 80 # DTB read access violations 4008721SN/Atestsys.cpu.dtb.read_accesses 225414 # DTB read accesses 40110409Sandreas.hansson@arm.comtestsys.cpu.dtb.write_hits 2316721 # DTB write hits 4028721SN/Atestsys.cpu.dtb.write_misses 528 # DTB write misses 4038721SN/Atestsys.cpu.dtb.write_acv 81 # DTB write access violations 4048721SN/Atestsys.cpu.dtb.write_accesses 109988 # DTB write accesses 40510409Sandreas.hansson@arm.comtestsys.cpu.dtb.data_hits 6233489 # DTB hits 4066024SN/Atestsys.cpu.dtb.data_misses 3815 # DTB misses 4078721SN/Atestsys.cpu.dtb.data_acv 161 # DTB access violations 4088721SN/Atestsys.cpu.dtb.data_accesses 335402 # DTB accesses 40910409Sandreas.hansson@arm.comtestsys.cpu.itb.fetch_hits 4052237 # ITB hits 4108721SN/Atestsys.cpu.itb.fetch_misses 1497 # ITB misses 4118721SN/Atestsys.cpu.itb.fetch_acv 69 # ITB acv 41210409Sandreas.hansson@arm.comtestsys.cpu.itb.fetch_accesses 4053734 # ITB accesses 4138721SN/Atestsys.cpu.itb.read_hits 0 # DTB read hits 4148721SN/Atestsys.cpu.itb.read_misses 0 # DTB read misses 4158721SN/Atestsys.cpu.itb.read_acv 0 # DTB read access violations 4168721SN/Atestsys.cpu.itb.read_accesses 0 # DTB read accesses 4178721SN/Atestsys.cpu.itb.write_hits 0 # DTB write hits 4188721SN/Atestsys.cpu.itb.write_misses 0 # DTB write misses 4198721SN/Atestsys.cpu.itb.write_acv 0 # DTB write access violations 4208721SN/Atestsys.cpu.itb.write_accesses 0 # DTB write accesses 4216024SN/Atestsys.cpu.itb.data_hits 0 # DTB hits 4226024SN/Atestsys.cpu.itb.data_misses 0 # DTB misses 4238721SN/Atestsys.cpu.itb.data_acv 0 # DTB access violations 4248721SN/Atestsys.cpu.itb.data_accesses 0 # DTB accesses 42511530Sandreas.sandberg@arm.comtestsys.cpu.numPwrStateTransitions 39159 # Number of power state transitions 42611530Sandreas.sandberg@arm.comtestsys.cpu.pwrStateClkGateDist::samples 19580 # Distribution of time spent in the clock gated state 42711530Sandreas.sandberg@arm.comtestsys.cpu.pwrStateClkGateDist::mean 9718476.378958 # Distribution of time spent in the clock gated state 42811530Sandreas.sandberg@arm.comtestsys.cpu.pwrStateClkGateDist::stdev 783559.874332 # Distribution of time spent in the clock gated state 42911530Sandreas.sandberg@arm.comtestsys.cpu.pwrStateClkGateDist::1000-5e+10 19580 100.00% 100.00% # Distribution of time spent in the clock gated state 43011530Sandreas.sandberg@arm.comtestsys.cpu.pwrStateClkGateDist::min_value 105000 # Distribution of time spent in the clock gated state 43111530Sandreas.sandberg@arm.comtestsys.cpu.pwrStateClkGateDist::max_value 9815000 # Distribution of time spent in the clock gated state 43211530Sandreas.sandberg@arm.comtestsys.cpu.pwrStateClkGateDist::total 19580 # Distribution of time spent in the clock gated state 43311530Sandreas.sandberg@arm.comtestsys.cpu.pwrStateResidencyTicks::ON 11102310500 # Cumulative time (in ticks) in various power states 43411530Sandreas.sandberg@arm.comtestsys.cpu.pwrStateResidencyTicks::CLK_GATED 190287767500 # Cumulative time (in ticks) in various power states 43510409Sandreas.hansson@arm.comtestsys.cpu.numCycles 400825859 # number of cpu cycles simulated 4368721SN/Atestsys.cpu.numWorkItemsStarted 0 # number of work items this cpu started 4378721SN/Atestsys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 4383691SN/Atestsys.cpu.kern.inst.arm 0 # number of arm instructions executed 4399729Sandreas.hansson@arm.comtestsys.cpu.kern.inst.quiesce 19580 # number of quiesce instructions executed 44010409Sandreas.hansson@arm.comtestsys.cpu.kern.inst.hwrei 153669 # number of hwrei instructions executed 4419729Sandreas.hansson@arm.comtestsys.cpu.kern.ipl_count::0 62779 42.67% 42.67% # number of times we switched to this ipl 4429729Sandreas.hansson@arm.comtestsys.cpu.kern.ipl_count::21 19625 13.34% 56.01% # number of times we switched to this ipl 4439449SAli.Saidi@ARM.comtestsys.cpu.kern.ipl_count::22 205 0.14% 56.15% # number of times we switched to this ipl 44410409Sandreas.hansson@arm.comtestsys.cpu.kern.ipl_count::31 64511 43.85% 100.00% # number of times we switched to this ipl 44510409Sandreas.hansson@arm.comtestsys.cpu.kern.ipl_count::total 147120 # number of times we switched to this ipl 4469729Sandreas.hansson@arm.comtestsys.cpu.kern.ipl_good::0 62773 43.18% 43.18% # number of times we switched to this ipl from a different ipl 4479729Sandreas.hansson@arm.comtestsys.cpu.kern.ipl_good::21 19625 13.50% 56.67% # number of times we switched to this ipl from a different ipl 4489729Sandreas.hansson@arm.comtestsys.cpu.kern.ipl_good::22 205 0.14% 56.82% # number of times we switched to this ipl from a different ipl 4499729Sandreas.hansson@arm.comtestsys.cpu.kern.ipl_good::31 62785 43.18% 100.00% # number of times we switched to this ipl from a different ipl 4509729Sandreas.hansson@arm.comtestsys.cpu.kern.ipl_good::total 145388 # number of times we switched to this ipl from a different ipl 45110409Sandreas.hansson@arm.comtestsys.cpu.kern.ipl_ticks::0 194347611000 96.98% 96.98% # number of cycles we spent at this ipl 4529729Sandreas.hansson@arm.comtestsys.cpu.kern.ipl_ticks::21 1588986000 0.79% 97.77% # number of cycles we spent at this ipl 4539449SAli.Saidi@ARM.comtestsys.cpu.kern.ipl_ticks::22 8815000 0.00% 97.78% # number of cycles we spent at this ipl 45410409Sandreas.hansson@arm.comtestsys.cpu.kern.ipl_ticks::31 4457946500 2.22% 100.00% # number of cycles we spent at this ipl 45510409Sandreas.hansson@arm.comtestsys.cpu.kern.ipl_ticks::total 200403358500 # number of cycles we spent at this ipl 4569449SAli.Saidi@ARM.comtestsys.cpu.kern.ipl_used::0 0.999904 # fraction of swpipl calls that actually changed the ipl 4576127SN/Atestsys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 4586127SN/Atestsys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 45910409Sandreas.hansson@arm.comtestsys.cpu.kern.ipl_used::31 0.973245 # fraction of swpipl calls that actually changed the ipl 46010409Sandreas.hansson@arm.comtestsys.cpu.kern.ipl_used::total 0.988227 # fraction of swpipl calls that actually changed the ipl 4616291SN/Atestsys.cpu.kern.syscall::2 3 3.61% 3.61% # number of syscalls executed 4626291SN/Atestsys.cpu.kern.syscall::3 7 8.43% 12.05% # number of syscalls executed 4636291SN/Atestsys.cpu.kern.syscall::4 1 1.20% 13.25% # number of syscalls executed 4646291SN/Atestsys.cpu.kern.syscall::6 7 8.43% 21.69% # number of syscalls executed 4656291SN/Atestsys.cpu.kern.syscall::17 7 8.43% 30.12% # number of syscalls executed 4666291SN/Atestsys.cpu.kern.syscall::19 2 2.41% 32.53% # number of syscalls executed 4676291SN/Atestsys.cpu.kern.syscall::20 1 1.20% 33.73% # number of syscalls executed 4686291SN/Atestsys.cpu.kern.syscall::33 3 3.61% 37.35% # number of syscalls executed 4696291SN/Atestsys.cpu.kern.syscall::45 10 12.05% 49.40% # number of syscalls executed 4706291SN/Atestsys.cpu.kern.syscall::48 5 6.02% 55.42% # number of syscalls executed 4716291SN/Atestsys.cpu.kern.syscall::54 1 1.20% 56.63% # number of syscalls executed 4726291SN/Atestsys.cpu.kern.syscall::59 3 3.61% 60.24% # number of syscalls executed 4736291SN/Atestsys.cpu.kern.syscall::71 15 18.07% 78.31% # number of syscalls executed 4746291SN/Atestsys.cpu.kern.syscall::74 4 4.82% 83.13% # number of syscalls executed 4756291SN/Atestsys.cpu.kern.syscall::97 2 2.41% 85.54% # number of syscalls executed 4766291SN/Atestsys.cpu.kern.syscall::98 2 2.41% 87.95% # number of syscalls executed 4776291SN/Atestsys.cpu.kern.syscall::101 2 2.41% 90.36% # number of syscalls executed 4786291SN/Atestsys.cpu.kern.syscall::102 2 2.41% 92.77% # number of syscalls executed 4796291SN/Atestsys.cpu.kern.syscall::104 1 1.20% 93.98% # number of syscalls executed 4806291SN/Atestsys.cpu.kern.syscall::105 3 3.61% 97.59% # number of syscalls executed 4816291SN/Atestsys.cpu.kern.syscall::118 2 2.41% 100.00% # number of syscalls executed 4826127SN/Atestsys.cpu.kern.syscall::total 83 # number of syscalls executed 4839729Sandreas.hansson@arm.comtestsys.cpu.kern.callpal::swpctx 438 0.34% 0.34% # number of callpals executed 4849449SAli.Saidi@ARM.comtestsys.cpu.kern.callpal::tbi 20 0.02% 0.36% # number of callpals executed 48510409Sandreas.hansson@arm.comtestsys.cpu.kern.callpal::swpipl 106832 83.26% 83.62% # number of callpals executed 4869449SAli.Saidi@ARM.comtestsys.cpu.kern.callpal::rdps 359 0.28% 83.90% # number of callpals executed 4879449SAli.Saidi@ARM.comtestsys.cpu.kern.callpal::wrusp 3 0.00% 83.90% # number of callpals executed 4889490Sandreas.hansson@arm.comtestsys.cpu.kern.callpal::rdusp 3 0.00% 83.90% # number of callpals executed 4899490Sandreas.hansson@arm.comtestsys.cpu.kern.callpal::rti 20470 15.95% 99.86% # number of callpals executed 4909449SAli.Saidi@ARM.comtestsys.cpu.kern.callpal::callsys 140 0.11% 99.97% # number of callpals executed 4919449SAli.Saidi@ARM.comtestsys.cpu.kern.callpal::imb 44 0.03% 100.00% # number of callpals executed 49210409Sandreas.hansson@arm.comtestsys.cpu.kern.callpal::total 128309 # number of callpals executed 4939729Sandreas.hansson@arm.comtestsys.cpu.kern.mode_switch::kernel 1280 # number of protection mode switches 49410409Sandreas.hansson@arm.comtestsys.cpu.kern.mode_switch::user 706 # number of protection mode switches 4959729Sandreas.hansson@arm.comtestsys.cpu.kern.mode_switch::idle 19629 # number of protection mode switches 49610409Sandreas.hansson@arm.comtestsys.cpu.kern.mode_good::kernel 711 49710409Sandreas.hansson@arm.comtestsys.cpu.kern.mode_good::user 706 4989729Sandreas.hansson@arm.comtestsys.cpu.kern.mode_good::idle 5 49910409Sandreas.hansson@arm.comtestsys.cpu.kern.mode_switch_good::kernel 0.555469 # fraction of useful protection mode switches 5008721SN/Atestsys.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 5019729Sandreas.hansson@arm.comtestsys.cpu.kern.mode_switch_good::idle 0.000255 # fraction of useful protection mode switches 50210409Sandreas.hansson@arm.comtestsys.cpu.kern.mode_switch_good::total 0.065788 # fraction of useful protection mode switches 50310409Sandreas.hansson@arm.comtestsys.cpu.kern.mode_ticks::kernel 994253000 59.96% 59.96% # number of ticks spent at the given mode 50410409Sandreas.hansson@arm.comtestsys.cpu.kern.mode_ticks::user 533088000 32.15% 92.11% # number of ticks spent at the given mode 50510409Sandreas.hansson@arm.comtestsys.cpu.kern.mode_ticks::idle 130749000 7.89% 100.00% # number of ticks spent at the given mode 5069729Sandreas.hansson@arm.comtestsys.cpu.kern.swap_context 438 # number of times the context was actually changed 50711245Sandreas.sandberg@arm.comtestsys.cpu.committedInsts 20257044 # Number of instructions committed 50811245Sandreas.sandberg@arm.comtestsys.cpu.committedOps 20257044 # Number of ops (including micro ops) committed 50911245Sandreas.sandberg@arm.comtestsys.cpu.num_int_alu_accesses 18836392 # Number of integer alu accesses 51011245Sandreas.sandberg@arm.comtestsys.cpu.num_fp_alu_accesses 17380 # Number of float alu accesses 51111245Sandreas.sandberg@arm.comtestsys.cpu.num_func_calls 1221158 # number of times a function call or return occured 51211245Sandreas.sandberg@arm.comtestsys.cpu.num_conditional_control_insts 1442105 # number of instructions that are conditional controls 51311245Sandreas.sandberg@arm.comtestsys.cpu.num_int_insts 18836392 # number of integer instructions 51411245Sandreas.sandberg@arm.comtestsys.cpu.num_fp_insts 17380 # number of float instructions 51511245Sandreas.sandberg@arm.comtestsys.cpu.num_int_register_reads 24786330 # number of times the integer registers were read 51611245Sandreas.sandberg@arm.comtestsys.cpu.num_int_register_writes 14693469 # number of times the integer registers were written 51711245Sandreas.sandberg@arm.comtestsys.cpu.num_fp_register_reads 11166 # number of times the floating registers were read 51811245Sandreas.sandberg@arm.comtestsys.cpu.num_fp_register_writes 10823 # number of times the floating registers were written 51911245Sandreas.sandberg@arm.comtestsys.cpu.num_mem_refs 6262732 # number of memory refs 52011245Sandreas.sandberg@arm.comtestsys.cpu.num_load_insts 3943883 # Number of load instructions 52111245Sandreas.sandberg@arm.comtestsys.cpu.num_store_insts 2318849 # Number of store instructions 52211245Sandreas.sandberg@arm.comtestsys.cpu.num_idle_cycles 380582482.461103 # Number of idle cycles 52311245Sandreas.sandberg@arm.comtestsys.cpu.num_busy_cycles 20243376.538897 # Number of busy cycles 52411245Sandreas.sandberg@arm.comtestsys.cpu.not_idle_fraction 0.050504 # Percentage of non-idle cycles 52511245Sandreas.sandberg@arm.comtestsys.cpu.idle_fraction 0.949496 # Percentage of idle cycles 52611245Sandreas.sandberg@arm.comtestsys.cpu.Branches 2929782 # Number of branches fetched 52711245Sandreas.sandberg@arm.comtestsys.cpu.op_class::No_OpClass 712785 3.52% 3.52% # Class of executed instruction 52811245Sandreas.sandberg@arm.comtestsys.cpu.op_class::IntAlu 12147004 59.95% 63.47% # Class of executed instruction 52911245Sandreas.sandberg@arm.comtestsys.cpu.op_class::IntMult 21654 0.11% 63.58% # Class of executed instruction 53011245Sandreas.sandberg@arm.comtestsys.cpu.op_class::IntDiv 0 0.00% 63.58% # Class of executed instruction 53111245Sandreas.sandberg@arm.comtestsys.cpu.op_class::FloatAdd 4655 0.02% 63.60% # Class of executed instruction 53211245Sandreas.sandberg@arm.comtestsys.cpu.op_class::FloatCmp 1 0.00% 63.60% # Class of executed instruction 53311245Sandreas.sandberg@arm.comtestsys.cpu.op_class::FloatCvt 0 0.00% 63.60% # Class of executed instruction 53411245Sandreas.sandberg@arm.comtestsys.cpu.op_class::FloatMult 0 0.00% 63.60% # Class of executed instruction 53511245Sandreas.sandberg@arm.comtestsys.cpu.op_class::FloatDiv 922 0.00% 63.60% # Class of executed instruction 53611245Sandreas.sandberg@arm.comtestsys.cpu.op_class::FloatSqrt 0 0.00% 63.60% # Class of executed instruction 53711245Sandreas.sandberg@arm.comtestsys.cpu.op_class::SimdAdd 0 0.00% 63.60% # Class of executed instruction 53811245Sandreas.sandberg@arm.comtestsys.cpu.op_class::SimdAddAcc 0 0.00% 63.60% # Class of executed instruction 53911245Sandreas.sandberg@arm.comtestsys.cpu.op_class::SimdAlu 0 0.00% 63.60% # Class of executed instruction 54011245Sandreas.sandberg@arm.comtestsys.cpu.op_class::SimdCmp 0 0.00% 63.60% # Class of executed instruction 54111245Sandreas.sandberg@arm.comtestsys.cpu.op_class::SimdCvt 0 0.00% 63.60% # Class of executed instruction 54211245Sandreas.sandberg@arm.comtestsys.cpu.op_class::SimdMisc 0 0.00% 63.60% # Class of executed instruction 54311245Sandreas.sandberg@arm.comtestsys.cpu.op_class::SimdMult 0 0.00% 63.60% # Class of executed instruction 54411245Sandreas.sandberg@arm.comtestsys.cpu.op_class::SimdMultAcc 0 0.00% 63.60% # Class of executed instruction 54511245Sandreas.sandberg@arm.comtestsys.cpu.op_class::SimdShift 0 0.00% 63.60% # Class of executed instruction 54611245Sandreas.sandberg@arm.comtestsys.cpu.op_class::SimdShiftAcc 0 0.00% 63.60% # Class of executed instruction 54711245Sandreas.sandberg@arm.comtestsys.cpu.op_class::SimdSqrt 0 0.00% 63.60% # Class of executed instruction 54811245Sandreas.sandberg@arm.comtestsys.cpu.op_class::SimdFloatAdd 0 0.00% 63.60% # Class of executed instruction 54911245Sandreas.sandberg@arm.comtestsys.cpu.op_class::SimdFloatAlu 0 0.00% 63.60% # Class of executed instruction 55011245Sandreas.sandberg@arm.comtestsys.cpu.op_class::SimdFloatCmp 0 0.00% 63.60% # Class of executed instruction 55111245Sandreas.sandberg@arm.comtestsys.cpu.op_class::SimdFloatCvt 0 0.00% 63.60% # Class of executed instruction 55211245Sandreas.sandberg@arm.comtestsys.cpu.op_class::SimdFloatDiv 0 0.00% 63.60% # Class of executed instruction 55311245Sandreas.sandberg@arm.comtestsys.cpu.op_class::SimdFloatMisc 0 0.00% 63.60% # Class of executed instruction 55411245Sandreas.sandberg@arm.comtestsys.cpu.op_class::SimdFloatMult 0 0.00% 63.60% # Class of executed instruction 55511245Sandreas.sandberg@arm.comtestsys.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.60% # Class of executed instruction 55611245Sandreas.sandberg@arm.comtestsys.cpu.op_class::SimdFloatSqrt 0 0.00% 63.60% # Class of executed instruction 55711245Sandreas.sandberg@arm.comtestsys.cpu.op_class::MemRead 4230485 20.88% 84.48% # Class of executed instruction 55811245Sandreas.sandberg@arm.comtestsys.cpu.op_class::MemWrite 2319388 11.45% 95.93% # Class of executed instruction 55911245Sandreas.sandberg@arm.comtestsys.cpu.op_class::IprAccess 824126 4.07% 100.00% # Class of executed instruction 56011245Sandreas.sandberg@arm.comtestsys.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 56111245Sandreas.sandberg@arm.comtestsys.cpu.op_class::total 20261020 # Class of executed instruction 56210778Snilay@cs.wisc.edutestsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 56310778Snilay@cs.wisc.edutestsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 56410778Snilay@cs.wisc.edutestsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 56510778Snilay@cs.wisc.edutestsys.disk0.dma_write_full_pages 0 # Number of full page size DMA writes. 56610778Snilay@cs.wisc.edutestsys.disk0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 56710778Snilay@cs.wisc.edutestsys.disk0.dma_write_txs 0 # Number of DMA write transactions. 56810778Snilay@cs.wisc.edutestsys.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 56910778Snilay@cs.wisc.edutestsys.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 57010778Snilay@cs.wisc.edutestsys.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 57110778Snilay@cs.wisc.edutestsys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes. 57210778Snilay@cs.wisc.edutestsys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 57310778Snilay@cs.wisc.edutestsys.disk2.dma_write_txs 0 # Number of DMA write transactions. 57411530Sandreas.sandberg@arm.comtestsys.iobridge.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 57511530Sandreas.sandberg@arm.comtestsys.iobus.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 57610778Snilay@cs.wisc.edutestsys.iobus.trans_dist::ReadReq 2483943 # Transaction distribution 57710778Snilay@cs.wisc.edutestsys.iobus.trans_dist::ReadResp 2483943 # Transaction distribution 57810778Snilay@cs.wisc.edutestsys.iobus.trans_dist::WriteReq 39573 # Transaction distribution 57910778Snilay@cs.wisc.edutestsys.iobus.trans_dist::WriteResp 39573 # Transaction distribution 58010778Snilay@cs.wisc.edutestsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.cchip.pio 196204 # Packet count per connected master and slave (bytes) 58110778Snilay@cs.wisc.edutestsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.io.pio 336 # Packet count per connected master and slave (bytes) 58210778Snilay@cs.wisc.edutestsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.uart.pio 428 # Packet count per connected master and slave (bytes) 58310778Snilay@cs.wisc.edutestsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.ethernet.pio 78330 # Packet count per connected master and slave (bytes) 58410778Snilay@cs.wisc.edutestsys.iobus.pkt_count_testsys.bridge.master::total 275298 # Packet count per connected master and slave (bytes) 58510778Snilay@cs.wisc.edutestsys.iobus.pkt_count_testsys.tsunami.ethernet.dma::testsys.iobridge.slave 4771734 # Packet count per connected master and slave (bytes) 58610778Snilay@cs.wisc.edutestsys.iobus.pkt_count_testsys.tsunami.ethernet.dma::total 4771734 # Packet count per connected master and slave (bytes) 58710778Snilay@cs.wisc.edutestsys.iobus.pkt_count::total 5047032 # Packet count per connected master and slave (bytes) 58810778Snilay@cs.wisc.edutestsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.cchip.pio 784816 # Cumulative packet size per connected master and slave (bytes) 58910778Snilay@cs.wisc.edutestsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.io.pio 462 # Cumulative packet size per connected master and slave (bytes) 59010778Snilay@cs.wisc.edutestsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.uart.pio 214 # Cumulative packet size per connected master and slave (bytes) 59110778Snilay@cs.wisc.edutestsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.ethernet.pio 156660 # Cumulative packet size per connected master and slave (bytes) 59210778Snilay@cs.wisc.edutestsys.iobus.pkt_size_testsys.bridge.master::total 942152 # Cumulative packet size per connected master and slave (bytes) 59310778Snilay@cs.wisc.edutestsys.iobus.pkt_size_testsys.tsunami.ethernet.dma::testsys.iobridge.slave 57261398 # Cumulative packet size per connected master and slave (bytes) 59410778Snilay@cs.wisc.edutestsys.iobus.pkt_size_testsys.tsunami.ethernet.dma::total 57261398 # Cumulative packet size per connected master and slave (bytes) 59510778Snilay@cs.wisc.edutestsys.iobus.pkt_size::total 58203550 # Cumulative packet size per connected master and slave (bytes) 59611606Sandreas.sandberg@arm.comtestsys.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. 59711606Sandreas.sandberg@arm.comtestsys.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 59811606Sandreas.sandberg@arm.comtestsys.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 59911606Sandreas.sandberg@arm.comtestsys.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 60011606Sandreas.sandberg@arm.comtestsys.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 60111606Sandreas.sandberg@arm.comtestsys.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 60211530Sandreas.sandberg@arm.comtestsys.membus.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 60310778Snilay@cs.wisc.edutestsys.membus.trans_dist::ReadReq 26478762 # Transaction distribution 60410778Snilay@cs.wisc.edutestsys.membus.trans_dist::ReadResp 26587372 # Transaction distribution 60510778Snilay@cs.wisc.edutestsys.membus.trans_dist::WriteReq 2189273 # Transaction distribution 60610778Snilay@cs.wisc.edutestsys.membus.trans_dist::WriteResp 2189273 # Transaction distribution 60710778Snilay@cs.wisc.edutestsys.membus.trans_dist::LoadLockedReq 108610 # Transaction distribution 60810778Snilay@cs.wisc.edutestsys.membus.trans_dist::StoreCondReq 108528 # Transaction distribution 60910778Snilay@cs.wisc.edutestsys.membus.trans_dist::StoreCondResp 108528 # Transaction distribution 61010778Snilay@cs.wisc.edutestsys.membus.pkt_count_testsys.cpu.icache_port::testsys.physmem.port 40522040 # Packet count per connected master and slave (bytes) 61110778Snilay@cs.wisc.edutestsys.membus.pkt_count_testsys.cpu.icache_port::total 40522040 # Packet count per connected master and slave (bytes) 61210778Snilay@cs.wisc.edutestsys.membus.pkt_count_testsys.cpu.dcache_port::testsys.bridge.slave 275298 # Packet count per connected master and slave (bytes) 61310778Snilay@cs.wisc.edutestsys.membus.pkt_count_testsys.cpu.dcache_port::testsys.physmem.port 12201274 # Packet count per connected master and slave (bytes) 61410778Snilay@cs.wisc.edutestsys.membus.pkt_count_testsys.cpu.dcache_port::total 12476572 # Packet count per connected master and slave (bytes) 61510778Snilay@cs.wisc.edutestsys.membus.pkt_count_testsys.iobridge.master::testsys.physmem.port 4771734 # Packet count per connected master and slave (bytes) 61610778Snilay@cs.wisc.edutestsys.membus.pkt_count_testsys.iobridge.master::total 4771734 # Packet count per connected master and slave (bytes) 61710778Snilay@cs.wisc.edutestsys.membus.pkt_count::total 57770346 # Packet count per connected master and slave (bytes) 61810778Snilay@cs.wisc.edutestsys.membus.pkt_size_testsys.cpu.icache_port::testsys.physmem.port 81044080 # Cumulative packet size per connected master and slave (bytes) 61910778Snilay@cs.wisc.edutestsys.membus.pkt_size_testsys.cpu.icache_port::total 81044080 # Cumulative packet size per connected master and slave (bytes) 62010778Snilay@cs.wisc.edutestsys.membus.pkt_size_testsys.cpu.dcache_port::testsys.bridge.slave 942152 # Cumulative packet size per connected master and slave (bytes) 62110778Snilay@cs.wisc.edutestsys.membus.pkt_size_testsys.cpu.dcache_port::testsys.physmem.port 44430520 # Cumulative packet size per connected master and slave (bytes) 62210778Snilay@cs.wisc.edutestsys.membus.pkt_size_testsys.cpu.dcache_port::total 45372672 # Cumulative packet size per connected master and slave (bytes) 62310778Snilay@cs.wisc.edutestsys.membus.pkt_size_testsys.iobridge.master::testsys.physmem.port 57261398 # Cumulative packet size per connected master and slave (bytes) 62410778Snilay@cs.wisc.edutestsys.membus.pkt_size_testsys.iobridge.master::total 57261398 # Cumulative packet size per connected master and slave (bytes) 62510778Snilay@cs.wisc.edutestsys.membus.pkt_size::total 183678150 # Cumulative packet size per connected master and slave (bytes) 62610778Snilay@cs.wisc.edutestsys.membus.snoops 0 # Total snoops (count) 62711570SCurtis.Dunham@arm.comtestsys.membus.snoopTraffic 0 # Total snoop traffic (bytes) 62810827Sandreas.hansson@arm.comtestsys.membus.snoop_fanout::samples 28885173 # Request fanout histogram 62911606Sandreas.sandberg@arm.comtestsys.membus.snoop_fanout::mean 0 # Request fanout histogram 63011606Sandreas.sandberg@arm.comtestsys.membus.snoop_fanout::stdev 0 # Request fanout histogram 63110778Snilay@cs.wisc.edutestsys.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 63211606Sandreas.sandberg@arm.comtestsys.membus.snoop_fanout::0 28885173 100.00% 100.00% # Request fanout histogram 63311606Sandreas.sandberg@arm.comtestsys.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 63410778Snilay@cs.wisc.edutestsys.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 63510778Snilay@cs.wisc.edutestsys.membus.snoop_fanout::min_value 0 # Request fanout histogram 63611606Sandreas.sandberg@arm.comtestsys.membus.snoop_fanout::max_value 0 # Request fanout histogram 63710827Sandreas.hansson@arm.comtestsys.membus.snoop_fanout::total 28885173 # Request fanout histogram 63811530Sandreas.sandberg@arm.comtestsys.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 63911530Sandreas.sandberg@arm.comtestsys.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 64011530Sandreas.sandberg@arm.comtestsys.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 64110036SAli.Saidi@ARM.comtestsys.tsunami.ethernet.clk_domain.clock 2000 # Clock period in ticks 64211530Sandreas.sandberg@arm.comtestsys.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 64311530Sandreas.sandberg@arm.comtestsys.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 6448721SN/Atestsys.tsunami.ethernet.txBytes 960 # Bytes Transmitted 6458721SN/Atestsys.tsunami.ethernet.rxBytes 798 # Bytes Received 6468721SN/Atestsys.tsunami.ethernet.txPackets 8 # Number of Packets Transmitted 6478721SN/Atestsys.tsunami.ethernet.rxPackets 5 # Number of Packets Received 6488721SN/Atestsys.tsunami.ethernet.txIpChecksums 2 # Number of tx IP Checksums done by device 6498721SN/Atestsys.tsunami.ethernet.rxIpChecksums 5 # Number of rx IP Checksums done by device 6508721SN/Atestsys.tsunami.ethernet.txTcpChecksums 2 # Number of tx TCP Checksums done by device 6518721SN/Atestsys.tsunami.ethernet.rxTcpChecksums 5 # Number of rx TCP Checksums done by device 6528721SN/Atestsys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 6538721SN/Atestsys.tsunami.ethernet.rxUdpChecksums 0 # Number of rx UDP Checksums done by device 6549729Sandreas.hansson@arm.comtestsys.tsunami.ethernet.descDMAReads 2385801 # Number of descriptors the device read w/ DMA 6553691SN/Atestsys.tsunami.ethernet.descDMAWrites 13 # Number of descriptors the device wrote w/ DMA 6569729Sandreas.hansson@arm.comtestsys.tsunami.ethernet.descDmaReadBytes 57259224 # number of descriptor bytes read w/ DMA 6573691SN/Atestsys.tsunami.ethernet.descDmaWriteBytes 104 # number of descriptor bytes write w/ DMA 6589449SAli.Saidi@ARM.comtestsys.tsunami.ethernet.totBandwidth 70176 # Total Bandwidth (bits/s) 6598721SN/Atestsys.tsunami.ethernet.totPackets 13 # Total Packets 6603691SN/Atestsys.tsunami.ethernet.totBytes 1758 # Total Bytes 6617461SN/Atestsys.tsunami.ethernet.totPPS 65 # Total Tranmission Rate (packets/s) 6629449SAli.Saidi@ARM.comtestsys.tsunami.ethernet.txBandwidth 38322 # Transmit Bandwidth (bits/s) 6639449SAli.Saidi@ARM.comtestsys.tsunami.ethernet.rxBandwidth 31855 # Receive Bandwidth (bits/s) 6648721SN/Atestsys.tsunami.ethernet.txPPS 40 # Packet Tranmission Rate (packets/s) 6658721SN/Atestsys.tsunami.ethernet.rxPPS 25 # Packet Reception Rate (packets/s) 6668721SN/Atestsys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 6678721SN/Atestsys.tsunami.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 6688721SN/Atestsys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 6698721SN/Atestsys.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 6708721SN/Atestsys.tsunami.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 6718721SN/Atestsys.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 6728721SN/Atestsys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 6738721SN/Atestsys.tsunami.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 6748721SN/Atestsys.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 6759247Sandreas.hansson@arm.comtestsys.tsunami.ethernet.postedRxDesc 5 # number of RxDesc interrupts posted to CPU 6768721SN/Atestsys.tsunami.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 6773691SN/Atestsys.tsunami.ethernet.totalRxDesc 5 # total number of RxDesc written to ISR 6788721SN/Atestsys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 6798721SN/Atestsys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 6808721SN/Atestsys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 6819490Sandreas.hansson@arm.comtestsys.tsunami.ethernet.postedTxIdle 19571 # number of TxIdle interrupts posted to CPU 6829247Sandreas.hansson@arm.comtestsys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post 6839729Sandreas.hansson@arm.comtestsys.tsunami.ethernet.totalTxIdle 2385801 # total number of TxIdle written to ISR 6848721SN/Atestsys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 6858721SN/Atestsys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 6868721SN/Atestsys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 6878721SN/Atestsys.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 6888721SN/Atestsys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 6893691SN/Atestsys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 6908721SN/Atestsys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post 6919729Sandreas.hansson@arm.comtestsys.tsunami.ethernet.postedInterrupts 2385819 # number of posts to CPU 6928721SN/Atestsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped 69311530Sandreas.sandberg@arm.comtestsys.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 69411530Sandreas.sandberg@arm.comtestsys.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 69511530Sandreas.sandberg@arm.comtestsys.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 69611530Sandreas.sandberg@arm.comtestsys.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 69711530Sandreas.sandberg@arm.comtestsys.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 69811530Sandreas.sandberg@arm.comtestsys.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 69911530Sandreas.sandberg@arm.comtestsys.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 70011530Sandreas.sandberg@arm.comtestsys.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 70111530Sandreas.sandberg@arm.comtestsys.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 70211530Sandreas.sandberg@arm.comtestsys.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 70311530Sandreas.sandberg@arm.comtestsys.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 70411530Sandreas.sandberg@arm.comtestsys.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 70511530Sandreas.sandberg@arm.comtestsys.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 70611530Sandreas.sandberg@arm.comtestsys.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 70711530Sandreas.sandberg@arm.comtestsys.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 70811530Sandreas.sandberg@arm.comtestsys.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 70911530Sandreas.sandberg@arm.comtestsys.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 71011530Sandreas.sandberg@arm.comtestsys.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 71111530Sandreas.sandberg@arm.comtestsys.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 71211530Sandreas.sandberg@arm.comtestsys.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 71311530Sandreas.sandberg@arm.comtestsys.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 71411530Sandreas.sandberg@arm.comtestsys.tsunami.io.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 71511530Sandreas.sandberg@arm.comtestsys.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states 71610778Snilay@cs.wisc.edu 71710778Snilay@cs.wisc.edu---------- End Simulation Statistics ---------- 71810778Snilay@cs.wisc.edu 71910778Snilay@cs.wisc.edu---------- Begin Simulation Statistics ---------- 72010778Snilay@cs.wisc.edusim_seconds 0.000407 # Number of seconds simulated 72110778Snilay@cs.wisc.edusim_ticks 407341500 # Number of ticks simulated 72210778Snilay@cs.wisc.edufinal_tick 4321620817500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 72310778Snilay@cs.wisc.edusim_freq 1000000000000 # Frequency of simulated ticks 72411606Sandreas.sandberg@arm.comhost_inst_rate 5887840528 # Simulator instruction rate (inst/s) 72511606Sandreas.sandberg@arm.comhost_op_rate 5886957075 # Simulator op (including micro ops) rate (op/s) 72611606Sandreas.sandberg@arm.comhost_tick_rate 4576964640 # Simulator tick rate (ticks/s) 72711606Sandreas.sandberg@arm.comhost_mem_usage 499724 # Number of bytes of host memory used 72811606Sandreas.sandberg@arm.comhost_seconds 0.09 # Real time elapsed on the host 72910778Snilay@cs.wisc.edusim_insts 523853183 # Number of instructions simulated 73010778Snilay@cs.wisc.edusim_ops 523853183 # Number of ops (including micro ops) simulated 73110036SAli.Saidi@ARM.comdrivesys.voltage_domain.voltage 1 # Voltage in Volts 73210036SAli.Saidi@ARM.comdrivesys.clk_domain.clock 1000 # Clock period in ticks 73311530Sandreas.sandberg@arm.comdrivesys.physmem.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 73410778Snilay@cs.wisc.edudrivesys.physmem.bytes_read::cpu.inst 144608 # Number of bytes read from this memory 73510778Snilay@cs.wisc.edudrivesys.physmem.bytes_read::cpu.data 49952 # Number of bytes read from this memory 73610778Snilay@cs.wisc.edudrivesys.physmem.bytes_read::tsunami.ethernet 116400 # Number of bytes read from this memory 73710778Snilay@cs.wisc.edudrivesys.physmem.bytes_read::total 310960 # Number of bytes read from this memory 73810778Snilay@cs.wisc.edudrivesys.physmem.bytes_inst_read::cpu.inst 144608 # Number of instructions bytes read from this memory 73910778Snilay@cs.wisc.edudrivesys.physmem.bytes_inst_read::total 144608 # Number of instructions bytes read from this memory 74010778Snilay@cs.wisc.edudrivesys.physmem.bytes_written::cpu.data 27688 # Number of bytes written to this memory 74110778Snilay@cs.wisc.edudrivesys.physmem.bytes_written::total 27688 # Number of bytes written to this memory 74210778Snilay@cs.wisc.edudrivesys.physmem.num_reads::cpu.inst 36152 # Number of read requests responded to by this memory 74310778Snilay@cs.wisc.edudrivesys.physmem.num_reads::cpu.data 6909 # Number of read requests responded to by this memory 74410778Snilay@cs.wisc.edudrivesys.physmem.num_reads::tsunami.ethernet 4850 # Number of read requests responded to by this memory 74510778Snilay@cs.wisc.edudrivesys.physmem.num_reads::total 47911 # Number of read requests responded to by this memory 74610778Snilay@cs.wisc.edudrivesys.physmem.num_writes::cpu.data 3812 # Number of write requests responded to by this memory 74710778Snilay@cs.wisc.edudrivesys.physmem.num_writes::total 3812 # Number of write requests responded to by this memory 74810778Snilay@cs.wisc.edudrivesys.physmem.bw_read::cpu.inst 355004339 # Total read bandwidth from this memory (bytes/s) 74910778Snilay@cs.wisc.edudrivesys.physmem.bw_read::cpu.data 122629293 # Total read bandwidth from this memory (bytes/s) 75010778Snilay@cs.wisc.edudrivesys.physmem.bw_read::tsunami.ethernet 285755318 # Total read bandwidth from this memory (bytes/s) 75110778Snilay@cs.wisc.edudrivesys.physmem.bw_read::total 763388950 # Total read bandwidth from this memory (bytes/s) 75210778Snilay@cs.wisc.edudrivesys.physmem.bw_inst_read::cpu.inst 355004339 # Instruction read bandwidth from this memory (bytes/s) 75310778Snilay@cs.wisc.edudrivesys.physmem.bw_inst_read::total 355004339 # Instruction read bandwidth from this memory (bytes/s) 75410778Snilay@cs.wisc.edudrivesys.physmem.bw_write::cpu.data 67972451 # Write bandwidth from this memory (bytes/s) 75510778Snilay@cs.wisc.edudrivesys.physmem.bw_write::total 67972451 # Write bandwidth from this memory (bytes/s) 75610778Snilay@cs.wisc.edudrivesys.physmem.bw_total::cpu.inst 355004339 # Total bandwidth to/from this memory (bytes/s) 75710778Snilay@cs.wisc.edudrivesys.physmem.bw_total::cpu.data 190601743 # Total bandwidth to/from this memory (bytes/s) 75810778Snilay@cs.wisc.edudrivesys.physmem.bw_total::tsunami.ethernet 285755318 # Total bandwidth to/from this memory (bytes/s) 75910778Snilay@cs.wisc.edudrivesys.physmem.bw_total::total 831361401 # Total bandwidth to/from this memory (bytes/s) 76011530Sandreas.sandberg@arm.comdrivesys.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 76111530Sandreas.sandberg@arm.comdrivesys.bridge.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 76210778Snilay@cs.wisc.edudrivesys.cpu.clk_domain.clock 250 # Clock period in ticks 76310778Snilay@cs.wisc.edudrivesys.cpu.dtb.fetch_hits 0 # ITB hits 76410778Snilay@cs.wisc.edudrivesys.cpu.dtb.fetch_misses 0 # ITB misses 76510778Snilay@cs.wisc.edudrivesys.cpu.dtb.fetch_acv 0 # ITB acv 76610778Snilay@cs.wisc.edudrivesys.cpu.dtb.fetch_accesses 0 # ITB accesses 76710778Snilay@cs.wisc.edudrivesys.cpu.dtb.read_hits 7069 # DTB read hits 76810778Snilay@cs.wisc.edudrivesys.cpu.dtb.read_misses 0 # DTB read misses 76910778Snilay@cs.wisc.edudrivesys.cpu.dtb.read_acv 0 # DTB read access violations 77010778Snilay@cs.wisc.edudrivesys.cpu.dtb.read_accesses 0 # DTB read accesses 77110778Snilay@cs.wisc.edudrivesys.cpu.dtb.write_hits 3933 # DTB write hits 77210778Snilay@cs.wisc.edudrivesys.cpu.dtb.write_misses 0 # DTB write misses 77310778Snilay@cs.wisc.edudrivesys.cpu.dtb.write_acv 0 # DTB write access violations 77410778Snilay@cs.wisc.edudrivesys.cpu.dtb.write_accesses 0 # DTB write accesses 77510778Snilay@cs.wisc.edudrivesys.cpu.dtb.data_hits 11002 # DTB hits 77610778Snilay@cs.wisc.edudrivesys.cpu.dtb.data_misses 0 # DTB misses 77710778Snilay@cs.wisc.edudrivesys.cpu.dtb.data_acv 0 # DTB access violations 77810778Snilay@cs.wisc.edudrivesys.cpu.dtb.data_accesses 0 # DTB accesses 77910778Snilay@cs.wisc.edudrivesys.cpu.itb.fetch_hits 5992 # ITB hits 78010778Snilay@cs.wisc.edudrivesys.cpu.itb.fetch_misses 0 # ITB misses 78110778Snilay@cs.wisc.edudrivesys.cpu.itb.fetch_acv 0 # ITB acv 78210778Snilay@cs.wisc.edudrivesys.cpu.itb.fetch_accesses 5992 # ITB accesses 78310778Snilay@cs.wisc.edudrivesys.cpu.itb.read_hits 0 # DTB read hits 78410778Snilay@cs.wisc.edudrivesys.cpu.itb.read_misses 0 # DTB read misses 78510778Snilay@cs.wisc.edudrivesys.cpu.itb.read_acv 0 # DTB read access violations 78610778Snilay@cs.wisc.edudrivesys.cpu.itb.read_accesses 0 # DTB read accesses 78710778Snilay@cs.wisc.edudrivesys.cpu.itb.write_hits 0 # DTB write hits 78810778Snilay@cs.wisc.edudrivesys.cpu.itb.write_misses 0 # DTB write misses 78910778Snilay@cs.wisc.edudrivesys.cpu.itb.write_acv 0 # DTB write access violations 79010778Snilay@cs.wisc.edudrivesys.cpu.itb.write_accesses 0 # DTB write accesses 79110778Snilay@cs.wisc.edudrivesys.cpu.itb.data_hits 0 # DTB hits 79210778Snilay@cs.wisc.edudrivesys.cpu.itb.data_misses 0 # DTB misses 79310778Snilay@cs.wisc.edudrivesys.cpu.itb.data_acv 0 # DTB access violations 79410778Snilay@cs.wisc.edudrivesys.cpu.itb.data_accesses 0 # DTB accesses 79511530Sandreas.sandberg@arm.comdrivesys.cpu.numPwrStateTransitions 82 # Number of power state transitions 79611530Sandreas.sandberg@arm.comdrivesys.cpu.pwrStateClkGateDist::samples 42 # Distribution of time spent in the clock gated state 79711530Sandreas.sandberg@arm.comdrivesys.cpu.pwrStateClkGateDist::mean 9483660.714286 # Distribution of time spent in the clock gated state 79811530Sandreas.sandberg@arm.comdrivesys.cpu.pwrStateClkGateDist::stdev 1743513.957554 # Distribution of time spent in the clock gated state 79911530Sandreas.sandberg@arm.comdrivesys.cpu.pwrStateClkGateDist::1000-5e+10 42 100.00% 100.00% # Distribution of time spent in the clock gated state 80011530Sandreas.sandberg@arm.comdrivesys.cpu.pwrStateClkGateDist::min_value 920000 # Distribution of time spent in the clock gated state 80111530Sandreas.sandberg@arm.comdrivesys.cpu.pwrStateClkGateDist::max_value 9947500 # Distribution of time spent in the clock gated state 80211530Sandreas.sandberg@arm.comdrivesys.cpu.pwrStateClkGateDist::total 42 # Distribution of time spent in the clock gated state 80311530Sandreas.sandberg@arm.comdrivesys.cpu.pwrStateResidencyTicks::ON 9027750 # Cumulative time (in ticks) in various power states 80411530Sandreas.sandberg@arm.comdrivesys.cpu.pwrStateResidencyTicks::CLK_GATED 398313750 # Cumulative time (in ticks) in various power states 80510778Snilay@cs.wisc.edudrivesys.cpu.numCycles 1626281 # number of cpu cycles simulated 80610778Snilay@cs.wisc.edudrivesys.cpu.numWorkItemsStarted 0 # number of work items this cpu started 80710778Snilay@cs.wisc.edudrivesys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 80811245Sandreas.sandberg@arm.comdrivesys.cpu.kern.inst.arm 0 # number of arm instructions executed 80911245Sandreas.sandberg@arm.comdrivesys.cpu.kern.inst.quiesce 41 # number of quiesce instructions executed 81011245Sandreas.sandberg@arm.comdrivesys.cpu.kern.inst.hwrei 295 # number of hwrei instructions executed 81111245Sandreas.sandberg@arm.comdrivesys.cpu.kern.ipl_count::0 123 41.84% 41.84% # number of times we switched to this ipl 81211245Sandreas.sandberg@arm.comdrivesys.cpu.kern.ipl_count::21 40 13.61% 55.44% # number of times we switched to this ipl 81311245Sandreas.sandberg@arm.comdrivesys.cpu.kern.ipl_count::22 1 0.34% 55.78% # number of times we switched to this ipl 81411245Sandreas.sandberg@arm.comdrivesys.cpu.kern.ipl_count::31 130 44.22% 100.00% # number of times we switched to this ipl 81511245Sandreas.sandberg@arm.comdrivesys.cpu.kern.ipl_count::total 294 # number of times we switched to this ipl 81611245Sandreas.sandberg@arm.comdrivesys.cpu.kern.ipl_good::0 123 42.86% 42.86% # number of times we switched to this ipl from a different ipl 81711245Sandreas.sandberg@arm.comdrivesys.cpu.kern.ipl_good::21 40 13.94% 56.79% # number of times we switched to this ipl from a different ipl 81811245Sandreas.sandberg@arm.comdrivesys.cpu.kern.ipl_good::22 1 0.35% 57.14% # number of times we switched to this ipl from a different ipl 81911245Sandreas.sandberg@arm.comdrivesys.cpu.kern.ipl_good::31 123 42.86% 100.00% # number of times we switched to this ipl from a different ipl 82011245Sandreas.sandberg@arm.comdrivesys.cpu.kern.ipl_good::total 287 # number of times we switched to this ipl from a different ipl 82111245Sandreas.sandberg@arm.comdrivesys.cpu.kern.ipl_ticks::0 400289000 98.46% 98.46% # number of cycles we spent at this ipl 82211245Sandreas.sandberg@arm.comdrivesys.cpu.kern.ipl_ticks::21 1620000 0.40% 98.86% # number of cycles we spent at this ipl 82311245Sandreas.sandberg@arm.comdrivesys.cpu.kern.ipl_ticks::22 21500 0.01% 98.86% # number of cycles we spent at this ipl 82411245Sandreas.sandberg@arm.comdrivesys.cpu.kern.ipl_ticks::31 4629500 1.14% 100.00% # number of cycles we spent at this ipl 82511245Sandreas.sandberg@arm.comdrivesys.cpu.kern.ipl_ticks::total 406560000 # number of cycles we spent at this ipl 82611245Sandreas.sandberg@arm.comdrivesys.cpu.kern.ipl_used::0 1 # fraction of swpipl calls that actually changed the ipl 82711245Sandreas.sandberg@arm.comdrivesys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 82811245Sandreas.sandberg@arm.comdrivesys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 82911245Sandreas.sandberg@arm.comdrivesys.cpu.kern.ipl_used::31 0.946154 # fraction of swpipl calls that actually changed the ipl 83011245Sandreas.sandberg@arm.comdrivesys.cpu.kern.ipl_used::total 0.976190 # fraction of swpipl calls that actually changed the ipl 83111245Sandreas.sandberg@arm.comdrivesys.cpu.kern.callpal::swpipl 212 83.46% 83.46% # number of callpals executed 83211245Sandreas.sandberg@arm.comdrivesys.cpu.kern.callpal::rdps 1 0.39% 83.86% # number of callpals executed 83311245Sandreas.sandberg@arm.comdrivesys.cpu.kern.callpal::rti 41 16.14% 100.00% # number of callpals executed 83411245Sandreas.sandberg@arm.comdrivesys.cpu.kern.callpal::total 254 # number of callpals executed 83511245Sandreas.sandberg@arm.comdrivesys.cpu.kern.mode_switch::kernel 0 # number of protection mode switches 83611245Sandreas.sandberg@arm.comdrivesys.cpu.kern.mode_switch::user 0 # number of protection mode switches 83711245Sandreas.sandberg@arm.comdrivesys.cpu.kern.mode_switch::idle 41 # number of protection mode switches 83811245Sandreas.sandberg@arm.comdrivesys.cpu.kern.mode_good::kernel 0 83911245Sandreas.sandberg@arm.comdrivesys.cpu.kern.mode_good::user 0 84011245Sandreas.sandberg@arm.comdrivesys.cpu.kern.mode_good::idle 0 84111245Sandreas.sandberg@arm.comdrivesys.cpu.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches 84211245Sandreas.sandberg@arm.comdrivesys.cpu.kern.mode_switch_good::user nan # fraction of useful protection mode switches 84311245Sandreas.sandberg@arm.comdrivesys.cpu.kern.mode_switch_good::idle 0 # fraction of useful protection mode switches 84411245Sandreas.sandberg@arm.comdrivesys.cpu.kern.mode_switch_good::total 0 # fraction of useful protection mode switches 84511245Sandreas.sandberg@arm.comdrivesys.cpu.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode 84611245Sandreas.sandberg@arm.comdrivesys.cpu.kern.mode_ticks::user 0 # number of ticks spent at the given mode 84711245Sandreas.sandberg@arm.comdrivesys.cpu.kern.mode_ticks::idle 0 # number of ticks spent at the given mode 84811245Sandreas.sandberg@arm.comdrivesys.cpu.kern.swap_context 0 # number of times the context was actually changed 84910778Snilay@cs.wisc.edudrivesys.cpu.committedInsts 36152 # Number of instructions committed 85010778Snilay@cs.wisc.edudrivesys.cpu.committedOps 36152 # Number of ops (including micro ops) committed 85110778Snilay@cs.wisc.edudrivesys.cpu.num_int_alu_accesses 33516 # Number of integer alu accesses 85210778Snilay@cs.wisc.edudrivesys.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 85310778Snilay@cs.wisc.edudrivesys.cpu.num_func_calls 2388 # number of times a function call or return occured 85410778Snilay@cs.wisc.edudrivesys.cpu.num_conditional_control_insts 2347 # number of instructions that are conditional controls 85510778Snilay@cs.wisc.edudrivesys.cpu.num_int_insts 33516 # number of integer instructions 85610778Snilay@cs.wisc.edudrivesys.cpu.num_fp_insts 0 # number of float instructions 85710778Snilay@cs.wisc.edudrivesys.cpu.num_int_register_reads 43772 # number of times the integer registers were read 85810778Snilay@cs.wisc.edudrivesys.cpu.num_int_register_writes 26499 # number of times the integer registers were written 85910778Snilay@cs.wisc.edudrivesys.cpu.num_fp_register_reads 0 # number of times the floating registers were read 86010778Snilay@cs.wisc.edudrivesys.cpu.num_fp_register_writes 0 # number of times the floating registers were written 86110778Snilay@cs.wisc.edudrivesys.cpu.num_mem_refs 11043 # number of memory refs 86210778Snilay@cs.wisc.edudrivesys.cpu.num_load_insts 7109 # Number of load instructions 86310778Snilay@cs.wisc.edudrivesys.cpu.num_store_insts 3934 # Number of store instructions 86410778Snilay@cs.wisc.edudrivesys.cpu.num_idle_cycles 1590238.371734 # Number of idle cycles 86510778Snilay@cs.wisc.edudrivesys.cpu.num_busy_cycles 36042.628266 # Number of busy cycles 86610778Snilay@cs.wisc.edudrivesys.cpu.not_idle_fraction 0.022163 # Percentage of non-idle cycles 86710778Snilay@cs.wisc.edudrivesys.cpu.idle_fraction 0.977837 # Percentage of idle cycles 86810778Snilay@cs.wisc.edudrivesys.cpu.Branches 5243 # Number of branches fetched 86910778Snilay@cs.wisc.edudrivesys.cpu.op_class::No_OpClass 1262 3.49% 3.49% # Class of executed instruction 87010778Snilay@cs.wisc.edudrivesys.cpu.op_class::IntAlu 21687 59.99% 63.48% # Class of executed instruction 87110778Snilay@cs.wisc.edudrivesys.cpu.op_class::IntMult 44 0.12% 63.60% # Class of executed instruction 87210778Snilay@cs.wisc.edudrivesys.cpu.op_class::IntDiv 0 0.00% 63.60% # Class of executed instruction 87310778Snilay@cs.wisc.edudrivesys.cpu.op_class::FloatAdd 0 0.00% 63.60% # Class of executed instruction 87410778Snilay@cs.wisc.edudrivesys.cpu.op_class::FloatCmp 0 0.00% 63.60% # Class of executed instruction 87510778Snilay@cs.wisc.edudrivesys.cpu.op_class::FloatCvt 0 0.00% 63.60% # Class of executed instruction 87610778Snilay@cs.wisc.edudrivesys.cpu.op_class::FloatMult 0 0.00% 63.60% # Class of executed instruction 87710778Snilay@cs.wisc.edudrivesys.cpu.op_class::FloatDiv 0 0.00% 63.60% # Class of executed instruction 87810778Snilay@cs.wisc.edudrivesys.cpu.op_class::FloatSqrt 0 0.00% 63.60% # Class of executed instruction 87910778Snilay@cs.wisc.edudrivesys.cpu.op_class::SimdAdd 0 0.00% 63.60% # Class of executed instruction 88010778Snilay@cs.wisc.edudrivesys.cpu.op_class::SimdAddAcc 0 0.00% 63.60% # Class of executed instruction 88110778Snilay@cs.wisc.edudrivesys.cpu.op_class::SimdAlu 0 0.00% 63.60% # Class of executed instruction 88210778Snilay@cs.wisc.edudrivesys.cpu.op_class::SimdCmp 0 0.00% 63.60% # Class of executed instruction 88310778Snilay@cs.wisc.edudrivesys.cpu.op_class::SimdCvt 0 0.00% 63.60% # Class of executed instruction 88410778Snilay@cs.wisc.edudrivesys.cpu.op_class::SimdMisc 0 0.00% 63.60% # Class of executed instruction 88510778Snilay@cs.wisc.edudrivesys.cpu.op_class::SimdMult 0 0.00% 63.60% # Class of executed instruction 88610778Snilay@cs.wisc.edudrivesys.cpu.op_class::SimdMultAcc 0 0.00% 63.60% # Class of executed instruction 88710778Snilay@cs.wisc.edudrivesys.cpu.op_class::SimdShift 0 0.00% 63.60% # Class of executed instruction 88810778Snilay@cs.wisc.edudrivesys.cpu.op_class::SimdShiftAcc 0 0.00% 63.60% # Class of executed instruction 88910778Snilay@cs.wisc.edudrivesys.cpu.op_class::SimdSqrt 0 0.00% 63.60% # Class of executed instruction 89010778Snilay@cs.wisc.edudrivesys.cpu.op_class::SimdFloatAdd 0 0.00% 63.60% # Class of executed instruction 89110778Snilay@cs.wisc.edudrivesys.cpu.op_class::SimdFloatAlu 0 0.00% 63.60% # Class of executed instruction 89210778Snilay@cs.wisc.edudrivesys.cpu.op_class::SimdFloatCmp 0 0.00% 63.60% # Class of executed instruction 89310778Snilay@cs.wisc.edudrivesys.cpu.op_class::SimdFloatCvt 0 0.00% 63.60% # Class of executed instruction 89410778Snilay@cs.wisc.edudrivesys.cpu.op_class::SimdFloatDiv 0 0.00% 63.60% # Class of executed instruction 89510778Snilay@cs.wisc.edudrivesys.cpu.op_class::SimdFloatMisc 0 0.00% 63.60% # Class of executed instruction 89610778Snilay@cs.wisc.edudrivesys.cpu.op_class::SimdFloatMult 0 0.00% 63.60% # Class of executed instruction 89710778Snilay@cs.wisc.edudrivesys.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.60% # Class of executed instruction 89810778Snilay@cs.wisc.edudrivesys.cpu.op_class::SimdFloatSqrt 0 0.00% 63.60% # Class of executed instruction 89910778Snilay@cs.wisc.edudrivesys.cpu.op_class::MemRead 7678 21.24% 84.84% # Class of executed instruction 90010778Snilay@cs.wisc.edudrivesys.cpu.op_class::MemWrite 3936 10.89% 95.73% # Class of executed instruction 90110778Snilay@cs.wisc.edudrivesys.cpu.op_class::IprAccess 1545 4.27% 100.00% # Class of executed instruction 90210778Snilay@cs.wisc.edudrivesys.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 90310778Snilay@cs.wisc.edudrivesys.cpu.op_class::total 36152 # Class of executed instruction 9048721SN/Adrivesys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 9058721SN/Adrivesys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 9068721SN/Adrivesys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 9078721SN/Adrivesys.disk0.dma_write_full_pages 0 # Number of full page size DMA writes. 9088721SN/Adrivesys.disk0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 9098721SN/Adrivesys.disk0.dma_write_txs 0 # Number of DMA write transactions. 9108721SN/Adrivesys.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 9118721SN/Adrivesys.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 9128721SN/Adrivesys.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 9138721SN/Adrivesys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes. 9148721SN/Adrivesys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 9158721SN/Adrivesys.disk2.dma_write_txs 0 # Number of DMA write transactions. 91611530Sandreas.sandberg@arm.comdrivesys.iobridge.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 91711530Sandreas.sandberg@arm.comdrivesys.iobus.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 91810778Snilay@cs.wisc.edudrivesys.iobus.trans_dist::ReadReq 5050 # Transaction distribution 91910778Snilay@cs.wisc.edudrivesys.iobus.trans_dist::ReadResp 5050 # Transaction distribution 92010778Snilay@cs.wisc.edudrivesys.iobus.trans_dist::WriteReq 81 # Transaction distribution 92110778Snilay@cs.wisc.edudrivesys.iobus.trans_dist::WriteResp 81 # Transaction distribution 92210778Snilay@cs.wisc.edudrivesys.iobus.pkt_count_drivesys.bridge.master::drivesys.tsunami.cchip.pio 402 # Packet count per connected master and slave (bytes) 92310778Snilay@cs.wisc.edudrivesys.iobus.pkt_count_drivesys.bridge.master::drivesys.tsunami.ethernet.pio 160 # Packet count per connected master and slave (bytes) 92410778Snilay@cs.wisc.edudrivesys.iobus.pkt_count_drivesys.bridge.master::total 562 # Packet count per connected master and slave (bytes) 92510778Snilay@cs.wisc.edudrivesys.iobus.pkt_count_drivesys.tsunami.ethernet.dma::drivesys.iobridge.slave 9700 # Packet count per connected master and slave (bytes) 92610778Snilay@cs.wisc.edudrivesys.iobus.pkt_count_drivesys.tsunami.ethernet.dma::total 9700 # Packet count per connected master and slave (bytes) 92710778Snilay@cs.wisc.edudrivesys.iobus.pkt_count::total 10262 # Packet count per connected master and slave (bytes) 92810778Snilay@cs.wisc.edudrivesys.iobus.pkt_size_drivesys.bridge.master::drivesys.tsunami.cchip.pio 1608 # Cumulative packet size per connected master and slave (bytes) 92910778Snilay@cs.wisc.edudrivesys.iobus.pkt_size_drivesys.bridge.master::drivesys.tsunami.ethernet.pio 320 # Cumulative packet size per connected master and slave (bytes) 93010778Snilay@cs.wisc.edudrivesys.iobus.pkt_size_drivesys.bridge.master::total 1928 # Cumulative packet size per connected master and slave (bytes) 93110778Snilay@cs.wisc.edudrivesys.iobus.pkt_size_drivesys.tsunami.ethernet.dma::drivesys.iobridge.slave 116400 # Cumulative packet size per connected master and slave (bytes) 93210778Snilay@cs.wisc.edudrivesys.iobus.pkt_size_drivesys.tsunami.ethernet.dma::total 116400 # Cumulative packet size per connected master and slave (bytes) 93310778Snilay@cs.wisc.edudrivesys.iobus.pkt_size::total 118328 # Cumulative packet size per connected master and slave (bytes) 93411606Sandreas.sandberg@arm.comdrivesys.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. 93511606Sandreas.sandberg@arm.comdrivesys.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 93611606Sandreas.sandberg@arm.comdrivesys.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 93711606Sandreas.sandberg@arm.comdrivesys.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 93811606Sandreas.sandberg@arm.comdrivesys.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 93911606Sandreas.sandberg@arm.comdrivesys.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 94011530Sandreas.sandberg@arm.comdrivesys.membus.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 94110778Snilay@cs.wisc.edudrivesys.membus.trans_dist::ReadReq 47907 # Transaction distribution 94210778Snilay@cs.wisc.edudrivesys.membus.trans_dist::ReadResp 48111 # Transaction distribution 94310778Snilay@cs.wisc.edudrivesys.membus.trans_dist::WriteReq 3689 # Transaction distribution 94410778Snilay@cs.wisc.edudrivesys.membus.trans_dist::WriteResp 3689 # Transaction distribution 94510778Snilay@cs.wisc.edudrivesys.membus.trans_dist::LoadLockedReq 204 # Transaction distribution 94610778Snilay@cs.wisc.edudrivesys.membus.trans_dist::StoreCondReq 204 # Transaction distribution 94710778Snilay@cs.wisc.edudrivesys.membus.trans_dist::StoreCondResp 204 # Transaction distribution 94810778Snilay@cs.wisc.edudrivesys.membus.pkt_count_drivesys.cpu.icache_port::drivesys.physmem.port 72304 # Packet count per connected master and slave (bytes) 94910778Snilay@cs.wisc.edudrivesys.membus.pkt_count_drivesys.cpu.icache_port::total 72304 # Packet count per connected master and slave (bytes) 95010778Snilay@cs.wisc.edudrivesys.membus.pkt_count_drivesys.cpu.dcache_port::drivesys.bridge.slave 562 # Packet count per connected master and slave (bytes) 95110778Snilay@cs.wisc.edudrivesys.membus.pkt_count_drivesys.cpu.dcache_port::drivesys.physmem.port 21442 # Packet count per connected master and slave (bytes) 95210778Snilay@cs.wisc.edudrivesys.membus.pkt_count_drivesys.cpu.dcache_port::total 22004 # Packet count per connected master and slave (bytes) 95310778Snilay@cs.wisc.edudrivesys.membus.pkt_count_drivesys.iobridge.master::drivesys.physmem.port 9700 # Packet count per connected master and slave (bytes) 95410778Snilay@cs.wisc.edudrivesys.membus.pkt_count_drivesys.iobridge.master::total 9700 # Packet count per connected master and slave (bytes) 95510778Snilay@cs.wisc.edudrivesys.membus.pkt_count::total 104008 # Packet count per connected master and slave (bytes) 95610778Snilay@cs.wisc.edudrivesys.membus.pkt_size_drivesys.cpu.icache_port::drivesys.physmem.port 144608 # Cumulative packet size per connected master and slave (bytes) 95710778Snilay@cs.wisc.edudrivesys.membus.pkt_size_drivesys.cpu.icache_port::total 144608 # Cumulative packet size per connected master and slave (bytes) 95810778Snilay@cs.wisc.edudrivesys.membus.pkt_size_drivesys.cpu.dcache_port::drivesys.bridge.slave 1928 # Cumulative packet size per connected master and slave (bytes) 95910778Snilay@cs.wisc.edudrivesys.membus.pkt_size_drivesys.cpu.dcache_port::drivesys.physmem.port 77640 # Cumulative packet size per connected master and slave (bytes) 96010778Snilay@cs.wisc.edudrivesys.membus.pkt_size_drivesys.cpu.dcache_port::total 79568 # Cumulative packet size per connected master and slave (bytes) 96110778Snilay@cs.wisc.edudrivesys.membus.pkt_size_drivesys.iobridge.master::drivesys.physmem.port 116400 # Cumulative packet size per connected master and slave (bytes) 96210778Snilay@cs.wisc.edudrivesys.membus.pkt_size_drivesys.iobridge.master::total 116400 # Cumulative packet size per connected master and slave (bytes) 96310778Snilay@cs.wisc.edudrivesys.membus.pkt_size::total 340576 # Cumulative packet size per connected master and slave (bytes) 96410778Snilay@cs.wisc.edudrivesys.membus.snoops 0 # Total snoops (count) 96511570SCurtis.Dunham@arm.comdrivesys.membus.snoopTraffic 0 # Total snoop traffic (bytes) 96610827Sandreas.hansson@arm.comdrivesys.membus.snoop_fanout::samples 52004 # Request fanout histogram 96711606Sandreas.sandberg@arm.comdrivesys.membus.snoop_fanout::mean 0 # Request fanout histogram 96811606Sandreas.sandberg@arm.comdrivesys.membus.snoop_fanout::stdev 0 # Request fanout histogram 96910778Snilay@cs.wisc.edudrivesys.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 97011606Sandreas.sandberg@arm.comdrivesys.membus.snoop_fanout::0 52004 100.00% 100.00% # Request fanout histogram 97111606Sandreas.sandberg@arm.comdrivesys.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 97210778Snilay@cs.wisc.edudrivesys.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 97310778Snilay@cs.wisc.edudrivesys.membus.snoop_fanout::min_value 0 # Request fanout histogram 97411606Sandreas.sandberg@arm.comdrivesys.membus.snoop_fanout::max_value 0 # Request fanout histogram 97510827Sandreas.hansson@arm.comdrivesys.membus.snoop_fanout::total 52004 # Request fanout histogram 97611530Sandreas.sandberg@arm.comdrivesys.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 97711530Sandreas.sandberg@arm.comdrivesys.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 97811530Sandreas.sandberg@arm.comdrivesys.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 97910036SAli.Saidi@ARM.comdrivesys.tsunami.ethernet.clk_domain.clock 2000 # Clock period in ticks 98011530Sandreas.sandberg@arm.comdrivesys.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 98111530Sandreas.sandberg@arm.comdrivesys.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 98210778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.descDMAReads 4850 # Number of descriptors the device read w/ DMA 98310778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 98410778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.descDmaReadBytes 116400 # number of descriptor bytes read w/ DMA 98510778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 9868721SN/Adrivesys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 9878721SN/Adrivesys.tsunami.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 9888721SN/Adrivesys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 9898721SN/Adrivesys.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 9908721SN/Adrivesys.tsunami.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 9918721SN/Adrivesys.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 9928721SN/Adrivesys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 9938721SN/Adrivesys.tsunami.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 9948721SN/Adrivesys.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 99510778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 9969449SAli.Saidi@ARM.comdrivesys.tsunami.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 99710778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 9988721SN/Adrivesys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 9998721SN/Adrivesys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 10008721SN/Adrivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 100110778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.postedTxIdle 40 # number of TxIdle interrupts posted to CPU 10029449SAli.Saidi@ARM.comdrivesys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post 100310778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.totalTxIdle 4850 # total number of TxIdle written to ISR 10048721SN/Adrivesys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 10058721SN/Adrivesys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 10068721SN/Adrivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 10078721SN/Adrivesys.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 10088721SN/Adrivesys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 10098721SN/Adrivesys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 10108721SN/Adrivesys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post 101110778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.postedInterrupts 4850 # number of posts to CPU 10128721SN/Adrivesys.tsunami.ethernet.droppedPackets 0 # number of packets dropped 101311530Sandreas.sandberg@arm.comdrivesys.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 101411530Sandreas.sandberg@arm.comdrivesys.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 101511530Sandreas.sandberg@arm.comdrivesys.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 101611530Sandreas.sandberg@arm.comdrivesys.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 101711530Sandreas.sandberg@arm.comdrivesys.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 101811530Sandreas.sandberg@arm.comdrivesys.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 101911530Sandreas.sandberg@arm.comdrivesys.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 102011530Sandreas.sandberg@arm.comdrivesys.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 102111530Sandreas.sandberg@arm.comdrivesys.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 102211530Sandreas.sandberg@arm.comdrivesys.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 102311530Sandreas.sandberg@arm.comdrivesys.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 102411530Sandreas.sandberg@arm.comdrivesys.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 102511530Sandreas.sandberg@arm.comdrivesys.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 102611530Sandreas.sandberg@arm.comdrivesys.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 102711530Sandreas.sandberg@arm.comdrivesys.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 102811530Sandreas.sandberg@arm.comdrivesys.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 102911530Sandreas.sandberg@arm.comdrivesys.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 103011530Sandreas.sandberg@arm.comdrivesys.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 103111530Sandreas.sandberg@arm.comdrivesys.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 103211530Sandreas.sandberg@arm.comdrivesys.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 103311530Sandreas.sandberg@arm.comdrivesys.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 103411530Sandreas.sandberg@arm.comdrivesys.tsunami.io.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 103511530Sandreas.sandberg@arm.comdrivesys.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 103610036SAli.Saidi@ARM.comtestsys.voltage_domain.voltage 1 # Voltage in Volts 103710036SAli.Saidi@ARM.comtestsys.clk_domain.clock 1000 # Clock period in ticks 103811530Sandreas.sandberg@arm.comtestsys.physmem.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 10399729Sandreas.hansson@arm.comtestsys.physmem.bytes_read::cpu.inst 144504 # Number of bytes read from this memory 10409729Sandreas.hansson@arm.comtestsys.physmem.bytes_read::cpu.data 49936 # Number of bytes read from this memory 10419729Sandreas.hansson@arm.comtestsys.physmem.bytes_read::tsunami.ethernet 116376 # Number of bytes read from this memory 10429729Sandreas.hansson@arm.comtestsys.physmem.bytes_read::total 310816 # Number of bytes read from this memory 10439729Sandreas.hansson@arm.comtestsys.physmem.bytes_inst_read::cpu.inst 144504 # Number of instructions bytes read from this memory 10449729Sandreas.hansson@arm.comtestsys.physmem.bytes_inst_read::total 144504 # Number of instructions bytes read from this memory 10459729Sandreas.hansson@arm.comtestsys.physmem.bytes_written::cpu.data 27704 # Number of bytes written to this memory 10469729Sandreas.hansson@arm.comtestsys.physmem.bytes_written::total 27704 # Number of bytes written to this memory 10479729Sandreas.hansson@arm.comtestsys.physmem.num_reads::cpu.inst 36126 # Number of read requests responded to by this memory 10489729Sandreas.hansson@arm.comtestsys.physmem.num_reads::cpu.data 6905 # Number of read requests responded to by this memory 10499729Sandreas.hansson@arm.comtestsys.physmem.num_reads::tsunami.ethernet 4849 # Number of read requests responded to by this memory 10509729Sandreas.hansson@arm.comtestsys.physmem.num_reads::total 47880 # Number of read requests responded to by this memory 10519729Sandreas.hansson@arm.comtestsys.physmem.num_writes::cpu.data 3814 # Number of write requests responded to by this memory 10529729Sandreas.hansson@arm.comtestsys.physmem.num_writes::total 3814 # Number of write requests responded to by this memory 10539729Sandreas.hansson@arm.comtestsys.physmem.bw_read::cpu.inst 354749025 # Total read bandwidth from this memory (bytes/s) 10549729Sandreas.hansson@arm.comtestsys.physmem.bw_read::cpu.data 122590014 # Total read bandwidth from this memory (bytes/s) 10559729Sandreas.hansson@arm.comtestsys.physmem.bw_read::tsunami.ethernet 285696400 # Total read bandwidth from this memory (bytes/s) 10569729Sandreas.hansson@arm.comtestsys.physmem.bw_read::total 763035438 # Total read bandwidth from this memory (bytes/s) 10579729Sandreas.hansson@arm.comtestsys.physmem.bw_inst_read::cpu.inst 354749025 # Instruction read bandwidth from this memory (bytes/s) 10589729Sandreas.hansson@arm.comtestsys.physmem.bw_inst_read::total 354749025 # Instruction read bandwidth from this memory (bytes/s) 10599729Sandreas.hansson@arm.comtestsys.physmem.bw_write::cpu.data 68011730 # Write bandwidth from this memory (bytes/s) 10609729Sandreas.hansson@arm.comtestsys.physmem.bw_write::total 68011730 # Write bandwidth from this memory (bytes/s) 10619729Sandreas.hansson@arm.comtestsys.physmem.bw_total::cpu.inst 354749025 # Total bandwidth to/from this memory (bytes/s) 10629729Sandreas.hansson@arm.comtestsys.physmem.bw_total::cpu.data 190601743 # Total bandwidth to/from this memory (bytes/s) 10639729Sandreas.hansson@arm.comtestsys.physmem.bw_total::tsunami.ethernet 285696400 # Total bandwidth to/from this memory (bytes/s) 10649729Sandreas.hansson@arm.comtestsys.physmem.bw_total::total 831047168 # Total bandwidth to/from this memory (bytes/s) 106511530Sandreas.sandberg@arm.comtestsys.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 106611530Sandreas.sandberg@arm.comtestsys.bridge.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 106710036SAli.Saidi@ARM.comtestsys.cpu.clk_domain.clock 500 # Clock period in ticks 10688721SN/Atestsys.cpu.dtb.fetch_hits 0 # ITB hits 10698721SN/Atestsys.cpu.dtb.fetch_misses 0 # ITB misses 10708721SN/Atestsys.cpu.dtb.fetch_acv 0 # ITB acv 10718721SN/Atestsys.cpu.dtb.fetch_accesses 0 # ITB accesses 10729729Sandreas.hansson@arm.comtestsys.cpu.dtb.read_hits 7065 # DTB read hits 10738721SN/Atestsys.cpu.dtb.read_misses 0 # DTB read misses 10748721SN/Atestsys.cpu.dtb.read_acv 0 # DTB read access violations 10758721SN/Atestsys.cpu.dtb.read_accesses 0 # DTB read accesses 10769729Sandreas.hansson@arm.comtestsys.cpu.dtb.write_hits 3935 # DTB write hits 10778721SN/Atestsys.cpu.dtb.write_misses 0 # DTB write misses 10788721SN/Atestsys.cpu.dtb.write_acv 0 # DTB write access violations 10798721SN/Atestsys.cpu.dtb.write_accesses 0 # DTB write accesses 10809729Sandreas.hansson@arm.comtestsys.cpu.dtb.data_hits 11000 # DTB hits 10818721SN/Atestsys.cpu.dtb.data_misses 0 # DTB misses 10828721SN/Atestsys.cpu.dtb.data_acv 0 # DTB access violations 10838721SN/Atestsys.cpu.dtb.data_accesses 0 # DTB accesses 10849729Sandreas.hansson@arm.comtestsys.cpu.itb.fetch_hits 5992 # ITB hits 10858721SN/Atestsys.cpu.itb.fetch_misses 0 # ITB misses 10868721SN/Atestsys.cpu.itb.fetch_acv 0 # ITB acv 10879729Sandreas.hansson@arm.comtestsys.cpu.itb.fetch_accesses 5992 # ITB accesses 10888721SN/Atestsys.cpu.itb.read_hits 0 # DTB read hits 10898721SN/Atestsys.cpu.itb.read_misses 0 # DTB read misses 10908721SN/Atestsys.cpu.itb.read_acv 0 # DTB read access violations 10918721SN/Atestsys.cpu.itb.read_accesses 0 # DTB read accesses 10928721SN/Atestsys.cpu.itb.write_hits 0 # DTB write hits 10938721SN/Atestsys.cpu.itb.write_misses 0 # DTB write misses 10948721SN/Atestsys.cpu.itb.write_acv 0 # DTB write access violations 10958721SN/Atestsys.cpu.itb.write_accesses 0 # DTB write accesses 10968721SN/Atestsys.cpu.itb.data_hits 0 # DTB hits 10978721SN/Atestsys.cpu.itb.data_misses 0 # DTB misses 10988721SN/Atestsys.cpu.itb.data_acv 0 # DTB access violations 10998721SN/Atestsys.cpu.itb.data_accesses 0 # DTB accesses 110011530Sandreas.sandberg@arm.comtestsys.cpu.numPwrStateTransitions 80 # Number of power state transitions 110111530Sandreas.sandberg@arm.comtestsys.cpu.pwrStateClkGateDist::samples 41 # Distribution of time spent in the clock gated state 110211530Sandreas.sandberg@arm.comtestsys.cpu.pwrStateClkGateDist::mean 9495085.365854 # Distribution of time spent in the clock gated state 110311530Sandreas.sandberg@arm.comtestsys.cpu.pwrStateClkGateDist::stdev 1417220.659876 # Distribution of time spent in the clock gated state 110411530Sandreas.sandberg@arm.comtestsys.cpu.pwrStateClkGateDist::1000-5e+10 41 100.00% 100.00% # Distribution of time spent in the clock gated state 110511530Sandreas.sandberg@arm.comtestsys.cpu.pwrStateClkGateDist::min_value 2964500 # Distribution of time spent in the clock gated state 110611530Sandreas.sandberg@arm.comtestsys.cpu.pwrStateClkGateDist::max_value 9815000 # Distribution of time spent in the clock gated state 110711530Sandreas.sandberg@arm.comtestsys.cpu.pwrStateClkGateDist::total 41 # Distribution of time spent in the clock gated state 110811530Sandreas.sandberg@arm.comtestsys.cpu.pwrStateResidencyTicks::ON 18043000 # Cumulative time (in ticks) in various power states 110911530Sandreas.sandberg@arm.comtestsys.cpu.pwrStateResidencyTicks::CLK_GATED 389298500 # Cumulative time (in ticks) in various power states 111010409Sandreas.hansson@arm.comtestsys.cpu.numCycles 821056 # number of cpu cycles simulated 11118721SN/Atestsys.cpu.numWorkItemsStarted 0 # number of work items this cpu started 11128721SN/Atestsys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 111311245Sandreas.sandberg@arm.comtestsys.cpu.kern.inst.arm 0 # number of arm instructions executed 111411245Sandreas.sandberg@arm.comtestsys.cpu.kern.inst.quiesce 40 # number of quiesce instructions executed 111511245Sandreas.sandberg@arm.comtestsys.cpu.kern.inst.hwrei 295 # number of hwrei instructions executed 111611245Sandreas.sandberg@arm.comtestsys.cpu.kern.ipl_count::0 123 41.84% 41.84% # number of times we switched to this ipl 111711245Sandreas.sandberg@arm.comtestsys.cpu.kern.ipl_count::21 40 13.61% 55.44% # number of times we switched to this ipl 111811245Sandreas.sandberg@arm.comtestsys.cpu.kern.ipl_count::22 1 0.34% 55.78% # number of times we switched to this ipl 111911245Sandreas.sandberg@arm.comtestsys.cpu.kern.ipl_count::31 130 44.22% 100.00% # number of times we switched to this ipl 112011245Sandreas.sandberg@arm.comtestsys.cpu.kern.ipl_count::total 294 # number of times we switched to this ipl 112111245Sandreas.sandberg@arm.comtestsys.cpu.kern.ipl_good::0 123 42.86% 42.86% # number of times we switched to this ipl from a different ipl 112211245Sandreas.sandberg@arm.comtestsys.cpu.kern.ipl_good::21 40 13.94% 56.79% # number of times we switched to this ipl from a different ipl 112311245Sandreas.sandberg@arm.comtestsys.cpu.kern.ipl_good::22 1 0.35% 57.14% # number of times we switched to this ipl from a different ipl 112411245Sandreas.sandberg@arm.comtestsys.cpu.kern.ipl_good::31 123 42.86% 100.00% # number of times we switched to this ipl from a different ipl 112511245Sandreas.sandberg@arm.comtestsys.cpu.kern.ipl_good::total 287 # number of times we switched to this ipl from a different ipl 112611245Sandreas.sandberg@arm.comtestsys.cpu.kern.ipl_ticks::0 397967000 96.95% 96.95% # number of cycles we spent at this ipl 112711245Sandreas.sandberg@arm.comtestsys.cpu.kern.ipl_ticks::21 3240000 0.79% 97.73% # number of cycles we spent at this ipl 112811245Sandreas.sandberg@arm.comtestsys.cpu.kern.ipl_ticks::22 43000 0.01% 97.74% # number of cycles we spent at this ipl 112911245Sandreas.sandberg@arm.comtestsys.cpu.kern.ipl_ticks::31 9258000 2.26% 100.00% # number of cycles we spent at this ipl 113011245Sandreas.sandberg@arm.comtestsys.cpu.kern.ipl_ticks::total 410508000 # number of cycles we spent at this ipl 113111245Sandreas.sandberg@arm.comtestsys.cpu.kern.ipl_used::0 1 # fraction of swpipl calls that actually changed the ipl 113211245Sandreas.sandberg@arm.comtestsys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 113311245Sandreas.sandberg@arm.comtestsys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 113411245Sandreas.sandberg@arm.comtestsys.cpu.kern.ipl_used::31 0.946154 # fraction of swpipl calls that actually changed the ipl 113511245Sandreas.sandberg@arm.comtestsys.cpu.kern.ipl_used::total 0.976190 # fraction of swpipl calls that actually changed the ipl 113611245Sandreas.sandberg@arm.comtestsys.cpu.kern.callpal::swpipl 212 83.46% 83.46% # number of callpals executed 113711245Sandreas.sandberg@arm.comtestsys.cpu.kern.callpal::rdps 1 0.39% 83.86% # number of callpals executed 113811245Sandreas.sandberg@arm.comtestsys.cpu.kern.callpal::rti 41 16.14% 100.00% # number of callpals executed 113911245Sandreas.sandberg@arm.comtestsys.cpu.kern.callpal::total 254 # number of callpals executed 114011245Sandreas.sandberg@arm.comtestsys.cpu.kern.mode_switch::kernel 0 # number of protection mode switches 114111245Sandreas.sandberg@arm.comtestsys.cpu.kern.mode_switch::user 0 # number of protection mode switches 114211245Sandreas.sandberg@arm.comtestsys.cpu.kern.mode_switch::idle 41 # number of protection mode switches 114311245Sandreas.sandberg@arm.comtestsys.cpu.kern.mode_good::kernel 0 114411245Sandreas.sandberg@arm.comtestsys.cpu.kern.mode_good::user 0 114511245Sandreas.sandberg@arm.comtestsys.cpu.kern.mode_good::idle 0 114611245Sandreas.sandberg@arm.comtestsys.cpu.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches 114711245Sandreas.sandberg@arm.comtestsys.cpu.kern.mode_switch_good::user nan # fraction of useful protection mode switches 114811245Sandreas.sandberg@arm.comtestsys.cpu.kern.mode_switch_good::idle 0 # fraction of useful protection mode switches 114911245Sandreas.sandberg@arm.comtestsys.cpu.kern.mode_switch_good::total 0 # fraction of useful protection mode switches 115011245Sandreas.sandberg@arm.comtestsys.cpu.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode 115111245Sandreas.sandberg@arm.comtestsys.cpu.kern.mode_ticks::user 0 # number of ticks spent at the given mode 115211245Sandreas.sandberg@arm.comtestsys.cpu.kern.mode_ticks::idle 0 # number of ticks spent at the given mode 115311245Sandreas.sandberg@arm.comtestsys.cpu.kern.swap_context 0 # number of times the context was actually changed 11549729Sandreas.hansson@arm.comtestsys.cpu.committedInsts 36126 # Number of instructions committed 11559729Sandreas.hansson@arm.comtestsys.cpu.committedOps 36126 # Number of ops (including micro ops) committed 11569729Sandreas.hansson@arm.comtestsys.cpu.num_int_alu_accesses 33492 # Number of integer alu accesses 11578721SN/Atestsys.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 11589729Sandreas.hansson@arm.comtestsys.cpu.num_func_calls 2384 # number of times a function call or return occured 11599729Sandreas.hansson@arm.comtestsys.cpu.num_conditional_control_insts 2346 # number of instructions that are conditional controls 11609729Sandreas.hansson@arm.comtestsys.cpu.num_int_insts 33492 # number of integer instructions 11618721SN/Atestsys.cpu.num_fp_insts 0 # number of float instructions 11629729Sandreas.hansson@arm.comtestsys.cpu.num_int_register_reads 43747 # number of times the integer registers were read 11639729Sandreas.hansson@arm.comtestsys.cpu.num_int_register_writes 26476 # number of times the integer registers were written 11648721SN/Atestsys.cpu.num_fp_register_reads 0 # number of times the floating registers were read 11658721SN/Atestsys.cpu.num_fp_register_writes 0 # number of times the floating registers were written 11669729Sandreas.hansson@arm.comtestsys.cpu.num_mem_refs 11041 # number of memory refs 11679729Sandreas.hansson@arm.comtestsys.cpu.num_load_insts 7105 # Number of load instructions 11689729Sandreas.hansson@arm.comtestsys.cpu.num_store_insts 3936 # Number of store instructions 116910409Sandreas.hansson@arm.comtestsys.cpu.num_idle_cycles 784687.711054 # Number of idle cycles 117010409Sandreas.hansson@arm.comtestsys.cpu.num_busy_cycles 36368.288946 # Number of busy cycles 117110409Sandreas.hansson@arm.comtestsys.cpu.not_idle_fraction 0.044295 # Percentage of non-idle cycles 117210409Sandreas.hansson@arm.comtestsys.cpu.idle_fraction 0.955705 # Percentage of idle cycles 117310063Snilay@cs.wisc.edutestsys.cpu.Branches 5238 # Number of branches fetched 117410220Sandreas.hansson@arm.comtestsys.cpu.op_class::No_OpClass 1261 3.49% 3.49% # Class of executed instruction 117510220Sandreas.hansson@arm.comtestsys.cpu.op_class::IntAlu 21664 59.97% 63.46% # Class of executed instruction 117610220Sandreas.hansson@arm.comtestsys.cpu.op_class::IntMult 44 0.12% 63.58% # Class of executed instruction 117710220Sandreas.hansson@arm.comtestsys.cpu.op_class::IntDiv 0 0.00% 63.58% # Class of executed instruction 117810220Sandreas.hansson@arm.comtestsys.cpu.op_class::FloatAdd 0 0.00% 63.58% # Class of executed instruction 117910220Sandreas.hansson@arm.comtestsys.cpu.op_class::FloatCmp 0 0.00% 63.58% # Class of executed instruction 118010220Sandreas.hansson@arm.comtestsys.cpu.op_class::FloatCvt 0 0.00% 63.58% # Class of executed instruction 118110220Sandreas.hansson@arm.comtestsys.cpu.op_class::FloatMult 0 0.00% 63.58% # Class of executed instruction 118210220Sandreas.hansson@arm.comtestsys.cpu.op_class::FloatDiv 0 0.00% 63.58% # Class of executed instruction 118310220Sandreas.hansson@arm.comtestsys.cpu.op_class::FloatSqrt 0 0.00% 63.58% # Class of executed instruction 118410220Sandreas.hansson@arm.comtestsys.cpu.op_class::SimdAdd 0 0.00% 63.58% # Class of executed instruction 118510220Sandreas.hansson@arm.comtestsys.cpu.op_class::SimdAddAcc 0 0.00% 63.58% # Class of executed instruction 118610220Sandreas.hansson@arm.comtestsys.cpu.op_class::SimdAlu 0 0.00% 63.58% # Class of executed instruction 118710220Sandreas.hansson@arm.comtestsys.cpu.op_class::SimdCmp 0 0.00% 63.58% # Class of executed instruction 118810220Sandreas.hansson@arm.comtestsys.cpu.op_class::SimdCvt 0 0.00% 63.58% # Class of executed instruction 118910220Sandreas.hansson@arm.comtestsys.cpu.op_class::SimdMisc 0 0.00% 63.58% # Class of executed instruction 119010220Sandreas.hansson@arm.comtestsys.cpu.op_class::SimdMult 0 0.00% 63.58% # Class of executed instruction 119110220Sandreas.hansson@arm.comtestsys.cpu.op_class::SimdMultAcc 0 0.00% 63.58% # Class of executed instruction 119210220Sandreas.hansson@arm.comtestsys.cpu.op_class::SimdShift 0 0.00% 63.58% # Class of executed instruction 119310220Sandreas.hansson@arm.comtestsys.cpu.op_class::SimdShiftAcc 0 0.00% 63.58% # Class of executed instruction 119410220Sandreas.hansson@arm.comtestsys.cpu.op_class::SimdSqrt 0 0.00% 63.58% # Class of executed instruction 119510220Sandreas.hansson@arm.comtestsys.cpu.op_class::SimdFloatAdd 0 0.00% 63.58% # Class of executed instruction 119610220Sandreas.hansson@arm.comtestsys.cpu.op_class::SimdFloatAlu 0 0.00% 63.58% # Class of executed instruction 119710220Sandreas.hansson@arm.comtestsys.cpu.op_class::SimdFloatCmp 0 0.00% 63.58% # Class of executed instruction 119810220Sandreas.hansson@arm.comtestsys.cpu.op_class::SimdFloatCvt 0 0.00% 63.58% # Class of executed instruction 119910220Sandreas.hansson@arm.comtestsys.cpu.op_class::SimdFloatDiv 0 0.00% 63.58% # Class of executed instruction 120010220Sandreas.hansson@arm.comtestsys.cpu.op_class::SimdFloatMisc 0 0.00% 63.58% # Class of executed instruction 120110220Sandreas.hansson@arm.comtestsys.cpu.op_class::SimdFloatMult 0 0.00% 63.58% # Class of executed instruction 120210220Sandreas.hansson@arm.comtestsys.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.58% # Class of executed instruction 120310220Sandreas.hansson@arm.comtestsys.cpu.op_class::SimdFloatSqrt 0 0.00% 63.58% # Class of executed instruction 120410220Sandreas.hansson@arm.comtestsys.cpu.op_class::MemRead 7674 21.24% 84.82% # Class of executed instruction 120510220Sandreas.hansson@arm.comtestsys.cpu.op_class::MemWrite 3938 10.90% 95.72% # Class of executed instruction 120610220Sandreas.hansson@arm.comtestsys.cpu.op_class::IprAccess 1545 4.28% 100.00% # Class of executed instruction 120710220Sandreas.hansson@arm.comtestsys.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 120810220Sandreas.hansson@arm.comtestsys.cpu.op_class::total 36126 # Class of executed instruction 120910778Snilay@cs.wisc.edutestsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 121010778Snilay@cs.wisc.edutestsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 121110778Snilay@cs.wisc.edutestsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 121210778Snilay@cs.wisc.edutestsys.disk0.dma_write_full_pages 0 # Number of full page size DMA writes. 121310778Snilay@cs.wisc.edutestsys.disk0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 121410778Snilay@cs.wisc.edutestsys.disk0.dma_write_txs 0 # Number of DMA write transactions. 121510778Snilay@cs.wisc.edutestsys.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 121610778Snilay@cs.wisc.edutestsys.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 121710778Snilay@cs.wisc.edutestsys.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 121810778Snilay@cs.wisc.edutestsys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes. 121910778Snilay@cs.wisc.edutestsys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 122010778Snilay@cs.wisc.edutestsys.disk2.dma_write_txs 0 # Number of DMA write transactions. 122111530Sandreas.sandberg@arm.comtestsys.iobridge.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 122211530Sandreas.sandberg@arm.comtestsys.iobus.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 122310778Snilay@cs.wisc.edutestsys.iobus.trans_dist::ReadReq 5049 # Transaction distribution 122410778Snilay@cs.wisc.edutestsys.iobus.trans_dist::ReadResp 5049 # Transaction distribution 122510778Snilay@cs.wisc.edutestsys.iobus.trans_dist::WriteReq 81 # Transaction distribution 122610778Snilay@cs.wisc.edutestsys.iobus.trans_dist::WriteResp 81 # Transaction distribution 122710778Snilay@cs.wisc.edutestsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.cchip.pio 402 # Packet count per connected master and slave (bytes) 122810778Snilay@cs.wisc.edutestsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.ethernet.pio 160 # Packet count per connected master and slave (bytes) 122910778Snilay@cs.wisc.edutestsys.iobus.pkt_count_testsys.bridge.master::total 562 # Packet count per connected master and slave (bytes) 123010778Snilay@cs.wisc.edutestsys.iobus.pkt_count_testsys.tsunami.ethernet.dma::testsys.iobridge.slave 9698 # Packet count per connected master and slave (bytes) 123110778Snilay@cs.wisc.edutestsys.iobus.pkt_count_testsys.tsunami.ethernet.dma::total 9698 # Packet count per connected master and slave (bytes) 123210778Snilay@cs.wisc.edutestsys.iobus.pkt_count::total 10260 # Packet count per connected master and slave (bytes) 123310778Snilay@cs.wisc.edutestsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.cchip.pio 1608 # Cumulative packet size per connected master and slave (bytes) 123410778Snilay@cs.wisc.edutestsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.ethernet.pio 320 # Cumulative packet size per connected master and slave (bytes) 123510778Snilay@cs.wisc.edutestsys.iobus.pkt_size_testsys.bridge.master::total 1928 # Cumulative packet size per connected master and slave (bytes) 123610778Snilay@cs.wisc.edutestsys.iobus.pkt_size_testsys.tsunami.ethernet.dma::testsys.iobridge.slave 116376 # Cumulative packet size per connected master and slave (bytes) 123710778Snilay@cs.wisc.edutestsys.iobus.pkt_size_testsys.tsunami.ethernet.dma::total 116376 # Cumulative packet size per connected master and slave (bytes) 123810778Snilay@cs.wisc.edutestsys.iobus.pkt_size::total 118304 # Cumulative packet size per connected master and slave (bytes) 123911606Sandreas.sandberg@arm.comtestsys.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. 124011606Sandreas.sandberg@arm.comtestsys.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 124111606Sandreas.sandberg@arm.comtestsys.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 124211606Sandreas.sandberg@arm.comtestsys.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 124311606Sandreas.sandberg@arm.comtestsys.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 124411606Sandreas.sandberg@arm.comtestsys.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 124511530Sandreas.sandberg@arm.comtestsys.membus.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 124610778Snilay@cs.wisc.edutestsys.membus.trans_dist::ReadReq 47876 # Transaction distribution 124710778Snilay@cs.wisc.edutestsys.membus.trans_dist::ReadResp 48080 # Transaction distribution 124810778Snilay@cs.wisc.edutestsys.membus.trans_dist::WriteReq 3691 # Transaction distribution 124910778Snilay@cs.wisc.edutestsys.membus.trans_dist::WriteResp 3691 # Transaction distribution 125010778Snilay@cs.wisc.edutestsys.membus.trans_dist::LoadLockedReq 204 # Transaction distribution 125110778Snilay@cs.wisc.edutestsys.membus.trans_dist::StoreCondReq 204 # Transaction distribution 125210778Snilay@cs.wisc.edutestsys.membus.trans_dist::StoreCondResp 204 # Transaction distribution 125310778Snilay@cs.wisc.edutestsys.membus.pkt_count_testsys.cpu.icache_port::testsys.physmem.port 72252 # Packet count per connected master and slave (bytes) 125410778Snilay@cs.wisc.edutestsys.membus.pkt_count_testsys.cpu.icache_port::total 72252 # Packet count per connected master and slave (bytes) 125510778Snilay@cs.wisc.edutestsys.membus.pkt_count_testsys.cpu.dcache_port::testsys.bridge.slave 562 # Packet count per connected master and slave (bytes) 125610778Snilay@cs.wisc.edutestsys.membus.pkt_count_testsys.cpu.dcache_port::testsys.physmem.port 21438 # Packet count per connected master and slave (bytes) 125710778Snilay@cs.wisc.edutestsys.membus.pkt_count_testsys.cpu.dcache_port::total 22000 # Packet count per connected master and slave (bytes) 125810778Snilay@cs.wisc.edutestsys.membus.pkt_count_testsys.iobridge.master::testsys.physmem.port 9698 # Packet count per connected master and slave (bytes) 125910778Snilay@cs.wisc.edutestsys.membus.pkt_count_testsys.iobridge.master::total 9698 # Packet count per connected master and slave (bytes) 126010778Snilay@cs.wisc.edutestsys.membus.pkt_count::total 103950 # Packet count per connected master and slave (bytes) 126110778Snilay@cs.wisc.edutestsys.membus.pkt_size_testsys.cpu.icache_port::testsys.physmem.port 144504 # Cumulative packet size per connected master and slave (bytes) 126210778Snilay@cs.wisc.edutestsys.membus.pkt_size_testsys.cpu.icache_port::total 144504 # Cumulative packet size per connected master and slave (bytes) 126310778Snilay@cs.wisc.edutestsys.membus.pkt_size_testsys.cpu.dcache_port::testsys.bridge.slave 1928 # Cumulative packet size per connected master and slave (bytes) 126410778Snilay@cs.wisc.edutestsys.membus.pkt_size_testsys.cpu.dcache_port::testsys.physmem.port 77640 # Cumulative packet size per connected master and slave (bytes) 126510778Snilay@cs.wisc.edutestsys.membus.pkt_size_testsys.cpu.dcache_port::total 79568 # Cumulative packet size per connected master and slave (bytes) 126610778Snilay@cs.wisc.edutestsys.membus.pkt_size_testsys.iobridge.master::testsys.physmem.port 116376 # Cumulative packet size per connected master and slave (bytes) 126710778Snilay@cs.wisc.edutestsys.membus.pkt_size_testsys.iobridge.master::total 116376 # Cumulative packet size per connected master and slave (bytes) 126810778Snilay@cs.wisc.edutestsys.membus.pkt_size::total 340448 # Cumulative packet size per connected master and slave (bytes) 126910778Snilay@cs.wisc.edutestsys.membus.snoops 0 # Total snoops (count) 127011570SCurtis.Dunham@arm.comtestsys.membus.snoopTraffic 0 # Total snoop traffic (bytes) 127110827Sandreas.hansson@arm.comtestsys.membus.snoop_fanout::samples 51975 # Request fanout histogram 127211606Sandreas.sandberg@arm.comtestsys.membus.snoop_fanout::mean 0 # Request fanout histogram 127311606Sandreas.sandberg@arm.comtestsys.membus.snoop_fanout::stdev 0 # Request fanout histogram 127410778Snilay@cs.wisc.edutestsys.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 127511606Sandreas.sandberg@arm.comtestsys.membus.snoop_fanout::0 51975 100.00% 100.00% # Request fanout histogram 127611606Sandreas.sandberg@arm.comtestsys.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 127710778Snilay@cs.wisc.edutestsys.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 127810778Snilay@cs.wisc.edutestsys.membus.snoop_fanout::min_value 0 # Request fanout histogram 127911606Sandreas.sandberg@arm.comtestsys.membus.snoop_fanout::max_value 0 # Request fanout histogram 128010827Sandreas.hansson@arm.comtestsys.membus.snoop_fanout::total 51975 # Request fanout histogram 128111530Sandreas.sandberg@arm.comtestsys.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 128211530Sandreas.sandberg@arm.comtestsys.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 128311530Sandreas.sandberg@arm.comtestsys.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 128410036SAli.Saidi@ARM.comtestsys.tsunami.ethernet.clk_domain.clock 2000 # Clock period in ticks 128511530Sandreas.sandberg@arm.comtestsys.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 128611530Sandreas.sandberg@arm.comtestsys.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 12879729Sandreas.hansson@arm.comtestsys.tsunami.ethernet.descDMAReads 4849 # Number of descriptors the device read w/ DMA 12888721SN/Atestsys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 12899729Sandreas.hansson@arm.comtestsys.tsunami.ethernet.descDmaReadBytes 116376 # number of descriptor bytes read w/ DMA 12908721SN/Atestsys.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 12918721SN/Atestsys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 12929449SAli.Saidi@ARM.comtestsys.tsunami.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 12938721SN/Atestsys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 12948721SN/Atestsys.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 12959449SAli.Saidi@ARM.comtestsys.tsunami.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 12968721SN/Atestsys.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 12978721SN/Atestsys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 12989449SAli.Saidi@ARM.comtestsys.tsunami.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 12998721SN/Atestsys.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 13008721SN/Atestsys.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 13019449SAli.Saidi@ARM.comtestsys.tsunami.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 13028721SN/Atestsys.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 13038721SN/Atestsys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 13049449SAli.Saidi@ARM.comtestsys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 13058721SN/Atestsys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 13069729Sandreas.hansson@arm.comtestsys.tsunami.ethernet.postedTxIdle 40 # number of TxIdle interrupts posted to CPU 13079449SAli.Saidi@ARM.comtestsys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post 13089729Sandreas.hansson@arm.comtestsys.tsunami.ethernet.totalTxIdle 4849 # total number of TxIdle written to ISR 13098721SN/Atestsys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 13109449SAli.Saidi@ARM.comtestsys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 13118721SN/Atestsys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 13128721SN/Atestsys.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 13139449SAli.Saidi@ARM.comtestsys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 13148721SN/Atestsys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 13159449SAli.Saidi@ARM.comtestsys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post 13169729Sandreas.hansson@arm.comtestsys.tsunami.ethernet.postedInterrupts 4849 # number of posts to CPU 13178721SN/Atestsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped 131811530Sandreas.sandberg@arm.comtestsys.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 131911530Sandreas.sandberg@arm.comtestsys.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 132011530Sandreas.sandberg@arm.comtestsys.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 132111530Sandreas.sandberg@arm.comtestsys.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 132211530Sandreas.sandberg@arm.comtestsys.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 132311530Sandreas.sandberg@arm.comtestsys.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 132411530Sandreas.sandberg@arm.comtestsys.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 132511530Sandreas.sandberg@arm.comtestsys.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 132611530Sandreas.sandberg@arm.comtestsys.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 132711530Sandreas.sandberg@arm.comtestsys.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 132811530Sandreas.sandberg@arm.comtestsys.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 132911530Sandreas.sandberg@arm.comtestsys.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 133011530Sandreas.sandberg@arm.comtestsys.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 133111530Sandreas.sandberg@arm.comtestsys.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 133211530Sandreas.sandberg@arm.comtestsys.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 133311530Sandreas.sandberg@arm.comtestsys.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 133411530Sandreas.sandberg@arm.comtestsys.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 133511530Sandreas.sandberg@arm.comtestsys.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 133611530Sandreas.sandberg@arm.comtestsys.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 133711530Sandreas.sandberg@arm.comtestsys.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 133811530Sandreas.sandberg@arm.comtestsys.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 133911530Sandreas.sandberg@arm.comtestsys.tsunami.io.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 134011530Sandreas.sandberg@arm.comtestsys.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states 13413691SN/A 13423691SN/A---------- End Simulation Statistics ---------- 1343