stats.txt revision 11245
13691SN/A 23691SN/A---------- Begin Simulation Statistics ---------- 39449SAli.Saidi@ARM.comsim_seconds 0.200409 # Number of seconds simulated 410409Sandreas.hansson@arm.comsim_ticks 200409271000 # Number of ticks simulated 510409Sandreas.hansson@arm.comfinal_tick 4321213476000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68721SN/Asim_freq 1000000000000 # Frequency of simulated ticks 711245Sandreas.sandberg@arm.comhost_inst_rate 12150896 # Simulator instruction rate (inst/s) 811245Sandreas.sandberg@arm.comhost_op_rate 12150892 # Simulator op (including micro ops) rate (op/s) 911245Sandreas.sandberg@arm.comhost_tick_rate 4649177813 # Simulator tick rate (ticks/s) 1011245Sandreas.sandberg@arm.comhost_mem_usage 500080 # Number of bytes of host memory used 1111245Sandreas.sandberg@arm.comhost_seconds 43.11 # Real time elapsed on the host 1210409Sandreas.hansson@arm.comsim_insts 523780905 # Number of instructions simulated 1310409Sandreas.hansson@arm.comsim_ops 523780905 # Number of ops (including micro ops) simulated 1410778Snilay@cs.wisc.edudrivesys.voltage_domain.voltage 1 # Voltage in Volts 1510778Snilay@cs.wisc.edudrivesys.clk_domain.clock 1000 # Clock period in ticks 1610778Snilay@cs.wisc.edudrivesys.physmem.bytes_read::cpu.inst 76205572 # Number of bytes read from this memory 1710778Snilay@cs.wisc.edudrivesys.physmem.bytes_read::cpu.data 26284292 # Number of bytes read from this memory 1810778Snilay@cs.wisc.edudrivesys.physmem.bytes_read::tsunami.ethernet 57260550 # Number of bytes read from this memory 1910778Snilay@cs.wisc.edudrivesys.physmem.bytes_read::total 159750414 # Number of bytes read from this memory 2010778Snilay@cs.wisc.edudrivesys.physmem.bytes_inst_read::cpu.inst 76205572 # Number of instructions bytes read from this memory 2110778Snilay@cs.wisc.edudrivesys.physmem.bytes_inst_read::total 76205572 # Number of instructions bytes read from this memory 2210778Snilay@cs.wisc.edudrivesys.physmem.bytes_written::cpu.data 14619632 # Number of bytes written to this memory 2310778Snilay@cs.wisc.edudrivesys.physmem.bytes_written::tsunami.ethernet 1064 # Number of bytes written to this memory 2410778Snilay@cs.wisc.edudrivesys.physmem.bytes_written::total 14620696 # Number of bytes written to this memory 2510778Snilay@cs.wisc.edudrivesys.physmem.num_reads::cpu.inst 19051393 # Number of read requests responded to by this memory 2610778Snilay@cs.wisc.edudrivesys.physmem.num_reads::cpu.data 3647049 # Number of read requests responded to by this memory 2710778Snilay@cs.wisc.edudrivesys.physmem.num_reads::tsunami.ethernet 2385839 # Number of read requests responded to by this memory 2810778Snilay@cs.wisc.edudrivesys.physmem.num_reads::total 25084281 # Number of read requests responded to by this memory 2910778Snilay@cs.wisc.edudrivesys.physmem.num_writes::cpu.data 2024776 # Number of write requests responded to by this memory 3010778Snilay@cs.wisc.edudrivesys.physmem.num_writes::tsunami.ethernet 37 # Number of write requests responded to by this memory 3110778Snilay@cs.wisc.edudrivesys.physmem.num_writes::total 2024813 # Number of write requests responded to by this memory 3210778Snilay@cs.wisc.edudrivesys.physmem.bw_read::cpu.inst 380249734 # Total read bandwidth from this memory (bytes/s) 3310778Snilay@cs.wisc.edudrivesys.physmem.bw_read::cpu.data 131153074 # Total read bandwidth from this memory (bytes/s) 3410778Snilay@cs.wisc.edudrivesys.physmem.bw_read::tsunami.ethernet 285718069 # Total read bandwidth from this memory (bytes/s) 3510778Snilay@cs.wisc.edudrivesys.physmem.bw_read::total 797120878 # Total read bandwidth from this memory (bytes/s) 3610778Snilay@cs.wisc.edudrivesys.physmem.bw_inst_read::cpu.inst 380249734 # Instruction read bandwidth from this memory (bytes/s) 3710778Snilay@cs.wisc.edudrivesys.physmem.bw_inst_read::total 380249734 # Instruction read bandwidth from this memory (bytes/s) 3810778Snilay@cs.wisc.edudrivesys.physmem.bw_write::cpu.data 72948881 # Write bandwidth from this memory (bytes/s) 3910778Snilay@cs.wisc.edudrivesys.physmem.bw_write::tsunami.ethernet 5309 # Write bandwidth from this memory (bytes/s) 4010778Snilay@cs.wisc.edudrivesys.physmem.bw_write::total 72954190 # Write bandwidth from this memory (bytes/s) 4110778Snilay@cs.wisc.edudrivesys.physmem.bw_total::cpu.inst 380249734 # Total bandwidth to/from this memory (bytes/s) 4210778Snilay@cs.wisc.edudrivesys.physmem.bw_total::cpu.data 204101955 # Total bandwidth to/from this memory (bytes/s) 4310778Snilay@cs.wisc.edudrivesys.physmem.bw_total::tsunami.ethernet 285723379 # Total bandwidth to/from this memory (bytes/s) 4410778Snilay@cs.wisc.edudrivesys.physmem.bw_total::total 870075068 # Total bandwidth to/from this memory (bytes/s) 4510778Snilay@cs.wisc.edudrivesys.cpu.clk_domain.clock 250 # Clock period in ticks 4610778Snilay@cs.wisc.edudrivesys.cpu.dtb.fetch_hits 0 # ITB hits 4710778Snilay@cs.wisc.edudrivesys.cpu.dtb.fetch_misses 0 # ITB misses 4810778Snilay@cs.wisc.edudrivesys.cpu.dtb.fetch_acv 0 # ITB acv 4910778Snilay@cs.wisc.edudrivesys.cpu.dtb.fetch_accesses 0 # ITB accesses 5010778Snilay@cs.wisc.edudrivesys.cpu.dtb.read_hits 3725273 # DTB read hits 5110778Snilay@cs.wisc.edudrivesys.cpu.dtb.read_misses 487 # DTB read misses 5210778Snilay@cs.wisc.edudrivesys.cpu.dtb.read_acv 30 # DTB read access violations 5310778Snilay@cs.wisc.edudrivesys.cpu.dtb.read_accesses 267991 # DTB read accesses 5410778Snilay@cs.wisc.edudrivesys.cpu.dtb.write_hits 2084079 # DTB write hits 5510778Snilay@cs.wisc.edudrivesys.cpu.dtb.write_misses 82 # DTB write misses 5610778Snilay@cs.wisc.edudrivesys.cpu.dtb.write_acv 10 # DTB write access violations 5710778Snilay@cs.wisc.edudrivesys.cpu.dtb.write_accesses 133239 # DTB write accesses 5810778Snilay@cs.wisc.edudrivesys.cpu.dtb.data_hits 5809352 # DTB hits 5910778Snilay@cs.wisc.edudrivesys.cpu.dtb.data_misses 569 # DTB misses 6010778Snilay@cs.wisc.edudrivesys.cpu.dtb.data_acv 40 # DTB access violations 6110778Snilay@cs.wisc.edudrivesys.cpu.dtb.data_accesses 401230 # DTB accesses 6210778Snilay@cs.wisc.edudrivesys.cpu.itb.fetch_hits 4197628 # ITB hits 6310778Snilay@cs.wisc.edudrivesys.cpu.itb.fetch_misses 194 # ITB misses 6410778Snilay@cs.wisc.edudrivesys.cpu.itb.fetch_acv 22 # ITB acv 6510778Snilay@cs.wisc.edudrivesys.cpu.itb.fetch_accesses 4197822 # ITB accesses 6610778Snilay@cs.wisc.edudrivesys.cpu.itb.read_hits 0 # DTB read hits 6710778Snilay@cs.wisc.edudrivesys.cpu.itb.read_misses 0 # DTB read misses 6810778Snilay@cs.wisc.edudrivesys.cpu.itb.read_acv 0 # DTB read access violations 6910778Snilay@cs.wisc.edudrivesys.cpu.itb.read_accesses 0 # DTB read accesses 7010778Snilay@cs.wisc.edudrivesys.cpu.itb.write_hits 0 # DTB write hits 7110778Snilay@cs.wisc.edudrivesys.cpu.itb.write_misses 0 # DTB write misses 7210778Snilay@cs.wisc.edudrivesys.cpu.itb.write_acv 0 # DTB write access violations 7310778Snilay@cs.wisc.edudrivesys.cpu.itb.write_accesses 0 # DTB write accesses 7410778Snilay@cs.wisc.edudrivesys.cpu.itb.data_hits 0 # DTB hits 7510778Snilay@cs.wisc.edudrivesys.cpu.itb.data_misses 0 # DTB misses 7610778Snilay@cs.wisc.edudrivesys.cpu.itb.data_acv 0 # DTB access violations 7710778Snilay@cs.wisc.edudrivesys.cpu.itb.data_accesses 0 # DTB accesses 7810778Snilay@cs.wisc.edudrivesys.cpu.numCycles 801651324 # number of cpu cycles simulated 7910778Snilay@cs.wisc.edudrivesys.cpu.numWorkItemsStarted 0 # number of work items this cpu started 8010778Snilay@cs.wisc.edudrivesys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 8110778Snilay@cs.wisc.edudrivesys.cpu.kern.inst.arm 0 # number of arm instructions executed 8210778Snilay@cs.wisc.edudrivesys.cpu.kern.inst.quiesce 19876 # number of quiesce instructions executed 8310778Snilay@cs.wisc.edudrivesys.cpu.kern.inst.hwrei 143591 # number of hwrei instructions executed 8410778Snilay@cs.wisc.edudrivesys.cpu.kern.ipl_count::0 60359 42.42% 42.42% # number of times we switched to this ipl 8510778Snilay@cs.wisc.edudrivesys.cpu.kern.ipl_count::21 19727 13.86% 56.28% # number of times we switched to this ipl 8610778Snilay@cs.wisc.edudrivesys.cpu.kern.ipl_count::22 205 0.14% 56.42% # number of times we switched to this ipl 8710778Snilay@cs.wisc.edudrivesys.cpu.kern.ipl_count::31 62011 43.58% 100.00% # number of times we switched to this ipl 8810778Snilay@cs.wisc.edudrivesys.cpu.kern.ipl_count::total 142302 # number of times we switched to this ipl 8910778Snilay@cs.wisc.edudrivesys.cpu.kern.ipl_good::0 60359 42.91% 42.91% # number of times we switched to this ipl from a different ipl 9010778Snilay@cs.wisc.edudrivesys.cpu.kern.ipl_good::21 19727 14.03% 56.94% # number of times we switched to this ipl from a different ipl 9110778Snilay@cs.wisc.edudrivesys.cpu.kern.ipl_good::22 205 0.15% 57.09% # number of times we switched to this ipl from a different ipl 9210778Snilay@cs.wisc.edudrivesys.cpu.kern.ipl_good::31 60360 42.91% 100.00% # number of times we switched to this ipl from a different ipl 9310778Snilay@cs.wisc.edudrivesys.cpu.kern.ipl_good::total 140651 # number of times we switched to this ipl from a different ipl 9410778Snilay@cs.wisc.edudrivesys.cpu.kern.ipl_ticks::0 197399332500 98.50% 98.50% # number of cycles we spent at this ipl 9510778Snilay@cs.wisc.edudrivesys.cpu.kern.ipl_ticks::21 798910750 0.40% 98.90% # number of cycles we spent at this ipl 9610778Snilay@cs.wisc.edudrivesys.cpu.kern.ipl_ticks::22 4407500 0.00% 98.90% # number of cycles we spent at this ipl 9710778Snilay@cs.wisc.edudrivesys.cpu.kern.ipl_ticks::31 2205211250 1.10% 100.00% # number of cycles we spent at this ipl 9810778Snilay@cs.wisc.edudrivesys.cpu.kern.ipl_ticks::total 200407862000 # number of cycles we spent at this ipl 9910778Snilay@cs.wisc.edudrivesys.cpu.kern.ipl_used::0 1 # fraction of swpipl calls that actually changed the ipl 10010778Snilay@cs.wisc.edudrivesys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 10110778Snilay@cs.wisc.edudrivesys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 10210778Snilay@cs.wisc.edudrivesys.cpu.kern.ipl_used::31 0.973376 # fraction of swpipl calls that actually changed the ipl 10310778Snilay@cs.wisc.edudrivesys.cpu.kern.ipl_used::total 0.988398 # fraction of swpipl calls that actually changed the ipl 10410778Snilay@cs.wisc.edudrivesys.cpu.kern.syscall::2 1 4.55% 4.55% # number of syscalls executed 10510778Snilay@cs.wisc.edudrivesys.cpu.kern.syscall::6 3 13.64% 18.18% # number of syscalls executed 10610778Snilay@cs.wisc.edudrivesys.cpu.kern.syscall::17 2 9.09% 27.27% # number of syscalls executed 10710778Snilay@cs.wisc.edudrivesys.cpu.kern.syscall::97 1 4.55% 31.82% # number of syscalls executed 10810778Snilay@cs.wisc.edudrivesys.cpu.kern.syscall::99 2 9.09% 40.91% # number of syscalls executed 10910778Snilay@cs.wisc.edudrivesys.cpu.kern.syscall::101 2 9.09% 50.00% # number of syscalls executed 11010778Snilay@cs.wisc.edudrivesys.cpu.kern.syscall::102 3 13.64% 63.64% # number of syscalls executed 11110778Snilay@cs.wisc.edudrivesys.cpu.kern.syscall::104 1 4.55% 68.18% # number of syscalls executed 11210778Snilay@cs.wisc.edudrivesys.cpu.kern.syscall::105 3 13.64% 81.82% # number of syscalls executed 11310778Snilay@cs.wisc.edudrivesys.cpu.kern.syscall::106 1 4.55% 86.36% # number of syscalls executed 11410778Snilay@cs.wisc.edudrivesys.cpu.kern.syscall::118 2 9.09% 95.45% # number of syscalls executed 11510778Snilay@cs.wisc.edudrivesys.cpu.kern.syscall::150 1 4.55% 100.00% # number of syscalls executed 11610778Snilay@cs.wisc.edudrivesys.cpu.kern.syscall::total 22 # number of syscalls executed 11710778Snilay@cs.wisc.edudrivesys.cpu.kern.callpal::swpctx 72 0.06% 0.06% # number of callpals executed 11810778Snilay@cs.wisc.edudrivesys.cpu.kern.callpal::tbi 5 0.00% 0.06% # number of callpals executed 11910778Snilay@cs.wisc.edudrivesys.cpu.kern.callpal::swpipl 102333 83.31% 83.37% # number of callpals executed 12010778Snilay@cs.wisc.edudrivesys.cpu.kern.callpal::rdps 354 0.29% 83.66% # number of callpals executed 12110778Snilay@cs.wisc.edudrivesys.cpu.kern.callpal::rdusp 1 0.00% 83.66% # number of callpals executed 12210778Snilay@cs.wisc.edudrivesys.cpu.kern.callpal::rti 20038 16.31% 99.97% # number of callpals executed 12310778Snilay@cs.wisc.edudrivesys.cpu.kern.callpal::callsys 25 0.02% 99.99% # number of callpals executed 12410778Snilay@cs.wisc.edudrivesys.cpu.kern.callpal::imb 7 0.01% 100.00% # number of callpals executed 12510778Snilay@cs.wisc.edudrivesys.cpu.kern.callpal::total 122835 # number of callpals executed 12610778Snilay@cs.wisc.edudrivesys.cpu.kern.mode_switch::kernel 214 # number of protection mode switches 12710778Snilay@cs.wisc.edudrivesys.cpu.kern.mode_switch::user 140 # number of protection mode switches 12810778Snilay@cs.wisc.edudrivesys.cpu.kern.mode_switch::idle 19896 # number of protection mode switches 12910778Snilay@cs.wisc.edudrivesys.cpu.kern.mode_good::kernel 144 13010778Snilay@cs.wisc.edudrivesys.cpu.kern.mode_good::user 140 13110778Snilay@cs.wisc.edudrivesys.cpu.kern.mode_good::idle 4 13210778Snilay@cs.wisc.edudrivesys.cpu.kern.mode_switch_good::kernel 0.672897 # fraction of useful protection mode switches 13310778Snilay@cs.wisc.edudrivesys.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 13410778Snilay@cs.wisc.edudrivesys.cpu.kern.mode_switch_good::idle 0.000201 # fraction of useful protection mode switches 13510778Snilay@cs.wisc.edudrivesys.cpu.kern.mode_switch_good::total 0.014222 # fraction of useful protection mode switches 13610778Snilay@cs.wisc.edudrivesys.cpu.kern.mode_ticks::kernel 78134250 2.63% 2.63% # number of ticks spent at the given mode 13710778Snilay@cs.wisc.edudrivesys.cpu.kern.mode_ticks::user 319668250 10.78% 13.41% # number of ticks spent at the given mode 13810778Snilay@cs.wisc.edudrivesys.cpu.kern.mode_ticks::idle 2567942000 86.59% 100.00% # number of ticks spent at the given mode 13910778Snilay@cs.wisc.edudrivesys.cpu.kern.swap_context 72 # number of times the context was actually changed 14011245Sandreas.sandberg@arm.comdrivesys.cpu.committedInsts 19050784 # Number of instructions committed 14111245Sandreas.sandberg@arm.comdrivesys.cpu.committedOps 19050784 # Number of ops (including micro ops) committed 14211245Sandreas.sandberg@arm.comdrivesys.cpu.num_int_alu_accesses 17740632 # Number of integer alu accesses 14311245Sandreas.sandberg@arm.comdrivesys.cpu.num_fp_alu_accesses 1412 # Number of float alu accesses 14411245Sandreas.sandberg@arm.comdrivesys.cpu.num_func_calls 1265024 # number of times a function call or return occured 14511245Sandreas.sandberg@arm.comdrivesys.cpu.num_conditional_control_insts 1264985 # number of instructions that are conditional controls 14611245Sandreas.sandberg@arm.comdrivesys.cpu.num_int_insts 17740632 # number of integer instructions 14711245Sandreas.sandberg@arm.comdrivesys.cpu.num_fp_insts 1412 # number of float instructions 14811245Sandreas.sandberg@arm.comdrivesys.cpu.num_int_register_reads 23072330 # number of times the integer registers were read 14911245Sandreas.sandberg@arm.comdrivesys.cpu.num_int_register_writes 13981107 # number of times the integer registers were written 15011245Sandreas.sandberg@arm.comdrivesys.cpu.num_fp_register_reads 760 # number of times the floating registers were read 15111245Sandreas.sandberg@arm.comdrivesys.cpu.num_fp_register_writes 766 # number of times the floating registers were written 15211245Sandreas.sandberg@arm.comdrivesys.cpu.num_mem_refs 5830788 # number of memory refs 15311245Sandreas.sandberg@arm.comdrivesys.cpu.num_load_insts 3746196 # Number of load instructions 15411245Sandreas.sandberg@arm.comdrivesys.cpu.num_store_insts 2084592 # Number of store instructions 15511245Sandreas.sandberg@arm.comdrivesys.cpu.num_idle_cycles 782619252.927065 # Number of idle cycles 15611245Sandreas.sandberg@arm.comdrivesys.cpu.num_busy_cycles 19032071.072935 # Number of busy cycles 15711245Sandreas.sandberg@arm.comdrivesys.cpu.not_idle_fraction 0.023741 # Percentage of non-idle cycles 15811245Sandreas.sandberg@arm.comdrivesys.cpu.idle_fraction 0.976259 # Percentage of idle cycles 15911245Sandreas.sandberg@arm.comdrivesys.cpu.Branches 2793313 # Number of branches fetched 16011245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::No_OpClass 623554 3.27% 3.27% # Class of executed instruction 16111245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::IntAlu 11538627 60.57% 63.84% # Class of executed instruction 16211245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::IntMult 20663 0.11% 63.95% # Class of executed instruction 16311245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::IntDiv 0 0.00% 63.95% # Class of executed instruction 16411245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::FloatAdd 141 0.00% 63.95% # Class of executed instruction 16511245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::FloatCmp 0 0.00% 63.95% # Class of executed instruction 16611245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::FloatCvt 0 0.00% 63.95% # Class of executed instruction 16711245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::FloatMult 0 0.00% 63.95% # Class of executed instruction 16811245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::FloatDiv 23 0.00% 63.95% # Class of executed instruction 16911245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::FloatSqrt 0 0.00% 63.95% # Class of executed instruction 17011245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::SimdAdd 0 0.00% 63.95% # Class of executed instruction 17111245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::SimdAddAcc 0 0.00% 63.95% # Class of executed instruction 17211245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::SimdAlu 0 0.00% 63.95% # Class of executed instruction 17311245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::SimdCmp 0 0.00% 63.95% # Class of executed instruction 17411245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::SimdCvt 0 0.00% 63.95% # Class of executed instruction 17511245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::SimdMisc 0 0.00% 63.95% # Class of executed instruction 17611245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::SimdMult 0 0.00% 63.95% # Class of executed instruction 17711245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::SimdMultAcc 0 0.00% 63.95% # Class of executed instruction 17811245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::SimdShift 0 0.00% 63.95% # Class of executed instruction 17911245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::SimdShiftAcc 0 0.00% 63.95% # Class of executed instruction 18011245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::SimdSqrt 0 0.00% 63.95% # Class of executed instruction 18111245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::SimdFloatAdd 0 0.00% 63.95% # Class of executed instruction 18211245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::SimdFloatAlu 0 0.00% 63.95% # Class of executed instruction 18311245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::SimdFloatCmp 0 0.00% 63.95% # Class of executed instruction 18411245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::SimdFloatCvt 0 0.00% 63.95% # Class of executed instruction 18511245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::SimdFloatDiv 0 0.00% 63.95% # Class of executed instruction 18611245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::SimdFloatMisc 0 0.00% 63.95% # Class of executed instruction 18711245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::SimdFloatMult 0 0.00% 63.95% # Class of executed instruction 18811245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.95% # Class of executed instruction 18911245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::SimdFloatSqrt 0 0.00% 63.95% # Class of executed instruction 19011245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::MemRead 4026028 21.13% 85.08% # Class of executed instruction 19111245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::MemWrite 2085021 10.94% 96.02% # Class of executed instruction 19211245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::IprAccess 757336 3.98% 100.00% # Class of executed instruction 19311245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 19411245Sandreas.sandberg@arm.comdrivesys.cpu.op_class::total 19051393 # Class of executed instruction 19510778Snilay@cs.wisc.edudrivesys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 19610778Snilay@cs.wisc.edudrivesys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 19710778Snilay@cs.wisc.edudrivesys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 19810778Snilay@cs.wisc.edudrivesys.disk0.dma_write_full_pages 0 # Number of full page size DMA writes. 19910778Snilay@cs.wisc.edudrivesys.disk0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 20010778Snilay@cs.wisc.edudrivesys.disk0.dma_write_txs 0 # Number of DMA write transactions. 20110778Snilay@cs.wisc.edudrivesys.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 20210778Snilay@cs.wisc.edudrivesys.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 20310778Snilay@cs.wisc.edudrivesys.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 20410778Snilay@cs.wisc.edudrivesys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes. 20510778Snilay@cs.wisc.edudrivesys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 20610778Snilay@cs.wisc.edudrivesys.disk2.dma_write_txs 0 # Number of DMA write transactions. 20710778Snilay@cs.wisc.edudrivesys.iobus.trans_dist::ReadReq 2484469 # Transaction distribution 20810778Snilay@cs.wisc.edudrivesys.iobus.trans_dist::ReadResp 2484469 # Transaction distribution 20910778Snilay@cs.wisc.edudrivesys.iobus.trans_dist::WriteReq 39723 # Transaction distribution 21010778Snilay@cs.wisc.edudrivesys.iobus.trans_dist::WriteResp 39723 # Transaction distribution 21110778Snilay@cs.wisc.edudrivesys.iobus.pkt_count_drivesys.bridge.master::drivesys.tsunami.cchip.pio 197670 # Packet count per connected master and slave (bytes) 21210778Snilay@cs.wisc.edudrivesys.iobus.pkt_count_drivesys.bridge.master::drivesys.tsunami.ethernet.pio 78962 # Packet count per connected master and slave (bytes) 21310778Snilay@cs.wisc.edudrivesys.iobus.pkt_count_drivesys.bridge.master::total 276632 # Packet count per connected master and slave (bytes) 21410778Snilay@cs.wisc.edudrivesys.iobus.pkt_count_drivesys.tsunami.ethernet.dma::drivesys.iobridge.slave 4771752 # Packet count per connected master and slave (bytes) 21510778Snilay@cs.wisc.edudrivesys.iobus.pkt_count_drivesys.tsunami.ethernet.dma::total 4771752 # Packet count per connected master and slave (bytes) 21610778Snilay@cs.wisc.edudrivesys.iobus.pkt_count::total 5048384 # Packet count per connected master and slave (bytes) 21710778Snilay@cs.wisc.edudrivesys.iobus.pkt_size_drivesys.bridge.master::drivesys.tsunami.cchip.pio 790680 # Cumulative packet size per connected master and slave (bytes) 21810778Snilay@cs.wisc.edudrivesys.iobus.pkt_size_drivesys.bridge.master::drivesys.tsunami.ethernet.pio 157924 # Cumulative packet size per connected master and slave (bytes) 21910778Snilay@cs.wisc.edudrivesys.iobus.pkt_size_drivesys.bridge.master::total 948604 # Cumulative packet size per connected master and slave (bytes) 22010778Snilay@cs.wisc.edudrivesys.iobus.pkt_size_drivesys.tsunami.ethernet.dma::drivesys.iobridge.slave 57261614 # Cumulative packet size per connected master and slave (bytes) 22110778Snilay@cs.wisc.edudrivesys.iobus.pkt_size_drivesys.tsunami.ethernet.dma::total 57261614 # Cumulative packet size per connected master and slave (bytes) 22210778Snilay@cs.wisc.edudrivesys.iobus.pkt_size::total 58210218 # Cumulative packet size per connected master and slave (bytes) 22310778Snilay@cs.wisc.edudrivesys.membus.trans_dist::ReadReq 25081955 # Transaction distribution 22410778Snilay@cs.wisc.edudrivesys.membus.trans_dist::ReadResp 25182911 # Transaction distribution 22510778Snilay@cs.wisc.edudrivesys.membus.trans_dist::WriteReq 1963575 # Transaction distribution 22610778Snilay@cs.wisc.edudrivesys.membus.trans_dist::WriteResp 1963575 # Transaction distribution 22710778Snilay@cs.wisc.edudrivesys.membus.trans_dist::LoadLockedReq 100956 # Transaction distribution 22810778Snilay@cs.wisc.edudrivesys.membus.trans_dist::StoreCondReq 100924 # Transaction distribution 22910778Snilay@cs.wisc.edudrivesys.membus.trans_dist::StoreCondResp 100924 # Transaction distribution 23010778Snilay@cs.wisc.edudrivesys.membus.pkt_count_drivesys.cpu.icache_port::drivesys.physmem.port 38102786 # Packet count per connected master and slave (bytes) 23110778Snilay@cs.wisc.edudrivesys.membus.pkt_count_drivesys.cpu.icache_port::total 38102786 # Packet count per connected master and slave (bytes) 23210778Snilay@cs.wisc.edudrivesys.membus.pkt_count_drivesys.cpu.dcache_port::drivesys.bridge.slave 276632 # Packet count per connected master and slave (bytes) 23310778Snilay@cs.wisc.edudrivesys.membus.pkt_count_drivesys.cpu.dcache_port::drivesys.physmem.port 11343650 # Packet count per connected master and slave (bytes) 23410778Snilay@cs.wisc.edudrivesys.membus.pkt_count_drivesys.cpu.dcache_port::total 11620282 # Packet count per connected master and slave (bytes) 23510778Snilay@cs.wisc.edudrivesys.membus.pkt_count_drivesys.iobridge.master::drivesys.physmem.port 4771752 # Packet count per connected master and slave (bytes) 23610778Snilay@cs.wisc.edudrivesys.membus.pkt_count_drivesys.iobridge.master::total 4771752 # Packet count per connected master and slave (bytes) 23710778Snilay@cs.wisc.edudrivesys.membus.pkt_count::total 54494820 # Packet count per connected master and slave (bytes) 23810778Snilay@cs.wisc.edudrivesys.membus.pkt_size_drivesys.cpu.icache_port::drivesys.physmem.port 76205572 # Cumulative packet size per connected master and slave (bytes) 23910778Snilay@cs.wisc.edudrivesys.membus.pkt_size_drivesys.cpu.icache_port::total 76205572 # Cumulative packet size per connected master and slave (bytes) 24010778Snilay@cs.wisc.edudrivesys.membus.pkt_size_drivesys.cpu.dcache_port::drivesys.bridge.slave 948604 # Cumulative packet size per connected master and slave (bytes) 24110778Snilay@cs.wisc.edudrivesys.membus.pkt_size_drivesys.cpu.dcache_port::drivesys.physmem.port 40903924 # Cumulative packet size per connected master and slave (bytes) 24210778Snilay@cs.wisc.edudrivesys.membus.pkt_size_drivesys.cpu.dcache_port::total 41852528 # Cumulative packet size per connected master and slave (bytes) 24310778Snilay@cs.wisc.edudrivesys.membus.pkt_size_drivesys.iobridge.master::drivesys.physmem.port 57261614 # Cumulative packet size per connected master and slave (bytes) 24410778Snilay@cs.wisc.edudrivesys.membus.pkt_size_drivesys.iobridge.master::total 57261614 # Cumulative packet size per connected master and slave (bytes) 24510778Snilay@cs.wisc.edudrivesys.membus.pkt_size::total 175319714 # Cumulative packet size per connected master and slave (bytes) 24610778Snilay@cs.wisc.edudrivesys.membus.snoops 0 # Total snoops (count) 24710827Sandreas.hansson@arm.comdrivesys.membus.snoop_fanout::samples 27247410 # Request fanout histogram 24810827Sandreas.hansson@arm.comdrivesys.membus.snoop_fanout::mean 0.786764 # Request fanout histogram 24910827Sandreas.hansson@arm.comdrivesys.membus.snoop_fanout::stdev 0.409593 # Request fanout histogram 25010778Snilay@cs.wisc.edudrivesys.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 25110827Sandreas.hansson@arm.comdrivesys.membus.snoop_fanout::0 5810141 21.32% 21.32% # Request fanout histogram 25210827Sandreas.hansson@arm.comdrivesys.membus.snoop_fanout::1 21437269 78.68% 100.00% # Request fanout histogram 25310778Snilay@cs.wisc.edudrivesys.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 25410778Snilay@cs.wisc.edudrivesys.membus.snoop_fanout::min_value 0 # Request fanout histogram 25510778Snilay@cs.wisc.edudrivesys.membus.snoop_fanout::max_value 1 # Request fanout histogram 25610827Sandreas.hansson@arm.comdrivesys.membus.snoop_fanout::total 27247410 # Request fanout histogram 25710778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.clk_domain.clock 2000 # Clock period in ticks 25810778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.txBytes 798 # Bytes Transmitted 25910778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.rxBytes 960 # Bytes Received 26010778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.txPackets 5 # Number of Packets Transmitted 26110778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.rxPackets 8 # Number of Packets Received 26210778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.txIpChecksums 2 # Number of tx IP Checksums done by device 26310778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.rxIpChecksums 8 # Number of rx IP Checksums done by device 26410778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.txTcpChecksums 2 # Number of tx TCP Checksums done by device 26510778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.rxTcpChecksums 8 # Number of rx TCP Checksums done by device 26610778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 26710778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.rxUdpChecksums 0 # Number of rx UDP Checksums done by device 26810778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.descDMAReads 2385810 # Number of descriptors the device read w/ DMA 26910778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.descDMAWrites 13 # Number of descriptors the device wrote w/ DMA 27010778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.descDmaReadBytes 57259440 # number of descriptor bytes read w/ DMA 27110778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.descDmaWriteBytes 104 # number of descriptor bytes write w/ DMA 27210778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.totBandwidth 70176 # Total Bandwidth (bits/s) 27310778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.totPackets 13 # Total Packets 27410778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.totBytes 1758 # Total Bytes 27510778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.totPPS 65 # Total Tranmission Rate (packets/s) 27610778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.txBandwidth 31855 # Transmit Bandwidth (bits/s) 27710778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.rxBandwidth 38322 # Receive Bandwidth (bits/s) 27810778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.txPPS 25 # Packet Tranmission Rate (packets/s) 27910778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.rxPPS 40 # Packet Reception Rate (packets/s) 28010778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 28110778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 28210778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 28310778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 28410778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 28510778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 28610778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 28710778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 28810778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 28910778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.postedRxDesc 8 # number of RxDesc interrupts posted to CPU 29010778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 29110778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.totalRxDesc 8 # total number of RxDesc written to ISR 29210778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 29310778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 29410778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 29510778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.postedTxIdle 19726 # number of TxIdle interrupts posted to CPU 29610778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post 29710778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.totalTxIdle 2385810 # total number of TxIdle written to ISR 29810778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 29910778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 30010778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 30110778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 30210778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 30310778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 30410778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post 30510778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.postedInterrupts 2385831 # number of posts to CPU 30610778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.droppedPackets 0 # number of packets dropped 30710036SAli.Saidi@ARM.comtestsys.voltage_domain.voltage 1 # Voltage in Volts 30810036SAli.Saidi@ARM.comtestsys.clk_domain.clock 1000 # Clock period in ticks 30910409Sandreas.hansson@arm.comtestsys.physmem.bytes_read::cpu.inst 81044080 # Number of bytes read from this memory 31010409Sandreas.hansson@arm.comtestsys.physmem.bytes_read::cpu.data 27825116 # Number of bytes read from this memory 3119729Sandreas.hansson@arm.comtestsys.physmem.bytes_read::tsunami.ethernet 57260496 # Number of bytes read from this memory 31210409Sandreas.hansson@arm.comtestsys.physmem.bytes_read::total 166129692 # Number of bytes read from this memory 31310409Sandreas.hansson@arm.comtestsys.physmem.bytes_inst_read::cpu.inst 81044080 # Number of instructions bytes read from this memory 31410409Sandreas.hansson@arm.comtestsys.physmem.bytes_inst_read::total 81044080 # Number of instructions bytes read from this memory 31510409Sandreas.hansson@arm.comtestsys.physmem.bytes_written::cpu.data 16605404 # Number of bytes written to this memory 3169055Ssaidi@eecs.umich.edutestsys.physmem.bytes_written::tsunami.ethernet 902 # Number of bytes written to this memory 31710409Sandreas.hansson@arm.comtestsys.physmem.bytes_written::total 16606306 # Number of bytes written to this memory 31810409Sandreas.hansson@arm.comtestsys.physmem.num_reads::cpu.inst 20261020 # Number of read requests responded to by this memory 31910409Sandreas.hansson@arm.comtestsys.physmem.num_reads::cpu.data 3842409 # Number of read requests responded to by this memory 3209729Sandreas.hansson@arm.comtestsys.physmem.num_reads::tsunami.ethernet 2385836 # Number of read requests responded to by this memory 32110409Sandreas.hansson@arm.comtestsys.physmem.num_reads::total 26489265 # Number of read requests responded to by this memory 32210409Sandreas.hansson@arm.comtestsys.physmem.num_writes::cpu.data 2258228 # Number of write requests responded to by this memory 3239055Ssaidi@eecs.umich.edutestsys.physmem.num_writes::tsunami.ethernet 31 # Number of write requests responded to by this memory 32410409Sandreas.hansson@arm.comtestsys.physmem.num_writes::total 2258259 # Number of write requests responded to by this memory 32510409Sandreas.hansson@arm.comtestsys.physmem.bw_read::cpu.inst 404392869 # Total read bandwidth from this memory (bytes/s) 32610409Sandreas.hansson@arm.comtestsys.physmem.bw_read::cpu.data 138841461 # Total read bandwidth from this memory (bytes/s) 32710409Sandreas.hansson@arm.comtestsys.physmem.bw_read::tsunami.ethernet 285717800 # Total read bandwidth from this memory (bytes/s) 32810409Sandreas.hansson@arm.comtestsys.physmem.bw_read::total 828952130 # Total read bandwidth from this memory (bytes/s) 32910409Sandreas.hansson@arm.comtestsys.physmem.bw_inst_read::cpu.inst 404392869 # Instruction read bandwidth from this memory (bytes/s) 33010409Sandreas.hansson@arm.comtestsys.physmem.bw_inst_read::total 404392869 # Instruction read bandwidth from this memory (bytes/s) 33110409Sandreas.hansson@arm.comtestsys.physmem.bw_write::cpu.data 82857464 # Write bandwidth from this memory (bytes/s) 3329247Sandreas.hansson@arm.comtestsys.physmem.bw_write::tsunami.ethernet 4501 # Write bandwidth from this memory (bytes/s) 33310409Sandreas.hansson@arm.comtestsys.physmem.bw_write::total 82861965 # Write bandwidth from this memory (bytes/s) 33410409Sandreas.hansson@arm.comtestsys.physmem.bw_total::cpu.inst 404392869 # Total bandwidth to/from this memory (bytes/s) 33510409Sandreas.hansson@arm.comtestsys.physmem.bw_total::cpu.data 221698925 # Total bandwidth to/from this memory (bytes/s) 33610409Sandreas.hansson@arm.comtestsys.physmem.bw_total::tsunami.ethernet 285722301 # Total bandwidth to/from this memory (bytes/s) 33710409Sandreas.hansson@arm.comtestsys.physmem.bw_total::total 911814095 # Total bandwidth to/from this memory (bytes/s) 33810036SAli.Saidi@ARM.comtestsys.cpu.clk_domain.clock 500 # Clock period in ticks 3398721SN/Atestsys.cpu.dtb.fetch_hits 0 # ITB hits 3408721SN/Atestsys.cpu.dtb.fetch_misses 0 # ITB misses 3418721SN/Atestsys.cpu.dtb.fetch_acv 0 # ITB acv 3428721SN/Atestsys.cpu.dtb.fetch_accesses 0 # ITB accesses 34310409Sandreas.hansson@arm.comtestsys.cpu.dtb.read_hits 3916768 # DTB read hits 3448721SN/Atestsys.cpu.dtb.read_misses 3287 # DTB read misses 3458721SN/Atestsys.cpu.dtb.read_acv 80 # DTB read access violations 3468721SN/Atestsys.cpu.dtb.read_accesses 225414 # DTB read accesses 34710409Sandreas.hansson@arm.comtestsys.cpu.dtb.write_hits 2316721 # DTB write hits 3488721SN/Atestsys.cpu.dtb.write_misses 528 # DTB write misses 3498721SN/Atestsys.cpu.dtb.write_acv 81 # DTB write access violations 3508721SN/Atestsys.cpu.dtb.write_accesses 109988 # DTB write accesses 35110409Sandreas.hansson@arm.comtestsys.cpu.dtb.data_hits 6233489 # DTB hits 3526024SN/Atestsys.cpu.dtb.data_misses 3815 # DTB misses 3538721SN/Atestsys.cpu.dtb.data_acv 161 # DTB access violations 3548721SN/Atestsys.cpu.dtb.data_accesses 335402 # DTB accesses 35510409Sandreas.hansson@arm.comtestsys.cpu.itb.fetch_hits 4052237 # ITB hits 3568721SN/Atestsys.cpu.itb.fetch_misses 1497 # ITB misses 3578721SN/Atestsys.cpu.itb.fetch_acv 69 # ITB acv 35810409Sandreas.hansson@arm.comtestsys.cpu.itb.fetch_accesses 4053734 # ITB accesses 3598721SN/Atestsys.cpu.itb.read_hits 0 # DTB read hits 3608721SN/Atestsys.cpu.itb.read_misses 0 # DTB read misses 3618721SN/Atestsys.cpu.itb.read_acv 0 # DTB read access violations 3628721SN/Atestsys.cpu.itb.read_accesses 0 # DTB read accesses 3638721SN/Atestsys.cpu.itb.write_hits 0 # DTB write hits 3648721SN/Atestsys.cpu.itb.write_misses 0 # DTB write misses 3658721SN/Atestsys.cpu.itb.write_acv 0 # DTB write access violations 3668721SN/Atestsys.cpu.itb.write_accesses 0 # DTB write accesses 3676024SN/Atestsys.cpu.itb.data_hits 0 # DTB hits 3686024SN/Atestsys.cpu.itb.data_misses 0 # DTB misses 3698721SN/Atestsys.cpu.itb.data_acv 0 # DTB access violations 3708721SN/Atestsys.cpu.itb.data_accesses 0 # DTB accesses 37110409Sandreas.hansson@arm.comtestsys.cpu.numCycles 400825859 # number of cpu cycles simulated 3728721SN/Atestsys.cpu.numWorkItemsStarted 0 # number of work items this cpu started 3738721SN/Atestsys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 3743691SN/Atestsys.cpu.kern.inst.arm 0 # number of arm instructions executed 3759729Sandreas.hansson@arm.comtestsys.cpu.kern.inst.quiesce 19580 # number of quiesce instructions executed 37610409Sandreas.hansson@arm.comtestsys.cpu.kern.inst.hwrei 153669 # number of hwrei instructions executed 3779729Sandreas.hansson@arm.comtestsys.cpu.kern.ipl_count::0 62779 42.67% 42.67% # number of times we switched to this ipl 3789729Sandreas.hansson@arm.comtestsys.cpu.kern.ipl_count::21 19625 13.34% 56.01% # number of times we switched to this ipl 3799449SAli.Saidi@ARM.comtestsys.cpu.kern.ipl_count::22 205 0.14% 56.15% # number of times we switched to this ipl 38010409Sandreas.hansson@arm.comtestsys.cpu.kern.ipl_count::31 64511 43.85% 100.00% # number of times we switched to this ipl 38110409Sandreas.hansson@arm.comtestsys.cpu.kern.ipl_count::total 147120 # number of times we switched to this ipl 3829729Sandreas.hansson@arm.comtestsys.cpu.kern.ipl_good::0 62773 43.18% 43.18% # number of times we switched to this ipl from a different ipl 3839729Sandreas.hansson@arm.comtestsys.cpu.kern.ipl_good::21 19625 13.50% 56.67% # number of times we switched to this ipl from a different ipl 3849729Sandreas.hansson@arm.comtestsys.cpu.kern.ipl_good::22 205 0.14% 56.82% # number of times we switched to this ipl from a different ipl 3859729Sandreas.hansson@arm.comtestsys.cpu.kern.ipl_good::31 62785 43.18% 100.00% # number of times we switched to this ipl from a different ipl 3869729Sandreas.hansson@arm.comtestsys.cpu.kern.ipl_good::total 145388 # number of times we switched to this ipl from a different ipl 38710409Sandreas.hansson@arm.comtestsys.cpu.kern.ipl_ticks::0 194347611000 96.98% 96.98% # number of cycles we spent at this ipl 3889729Sandreas.hansson@arm.comtestsys.cpu.kern.ipl_ticks::21 1588986000 0.79% 97.77% # number of cycles we spent at this ipl 3899449SAli.Saidi@ARM.comtestsys.cpu.kern.ipl_ticks::22 8815000 0.00% 97.78% # number of cycles we spent at this ipl 39010409Sandreas.hansson@arm.comtestsys.cpu.kern.ipl_ticks::31 4457946500 2.22% 100.00% # number of cycles we spent at this ipl 39110409Sandreas.hansson@arm.comtestsys.cpu.kern.ipl_ticks::total 200403358500 # number of cycles we spent at this ipl 3929449SAli.Saidi@ARM.comtestsys.cpu.kern.ipl_used::0 0.999904 # fraction of swpipl calls that actually changed the ipl 3936127SN/Atestsys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 3946127SN/Atestsys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 39510409Sandreas.hansson@arm.comtestsys.cpu.kern.ipl_used::31 0.973245 # fraction of swpipl calls that actually changed the ipl 39610409Sandreas.hansson@arm.comtestsys.cpu.kern.ipl_used::total 0.988227 # fraction of swpipl calls that actually changed the ipl 3976291SN/Atestsys.cpu.kern.syscall::2 3 3.61% 3.61% # number of syscalls executed 3986291SN/Atestsys.cpu.kern.syscall::3 7 8.43% 12.05% # number of syscalls executed 3996291SN/Atestsys.cpu.kern.syscall::4 1 1.20% 13.25% # number of syscalls executed 4006291SN/Atestsys.cpu.kern.syscall::6 7 8.43% 21.69% # number of syscalls executed 4016291SN/Atestsys.cpu.kern.syscall::17 7 8.43% 30.12% # number of syscalls executed 4026291SN/Atestsys.cpu.kern.syscall::19 2 2.41% 32.53% # number of syscalls executed 4036291SN/Atestsys.cpu.kern.syscall::20 1 1.20% 33.73% # number of syscalls executed 4046291SN/Atestsys.cpu.kern.syscall::33 3 3.61% 37.35% # number of syscalls executed 4056291SN/Atestsys.cpu.kern.syscall::45 10 12.05% 49.40% # number of syscalls executed 4066291SN/Atestsys.cpu.kern.syscall::48 5 6.02% 55.42% # number of syscalls executed 4076291SN/Atestsys.cpu.kern.syscall::54 1 1.20% 56.63% # number of syscalls executed 4086291SN/Atestsys.cpu.kern.syscall::59 3 3.61% 60.24% # number of syscalls executed 4096291SN/Atestsys.cpu.kern.syscall::71 15 18.07% 78.31% # number of syscalls executed 4106291SN/Atestsys.cpu.kern.syscall::74 4 4.82% 83.13% # number of syscalls executed 4116291SN/Atestsys.cpu.kern.syscall::97 2 2.41% 85.54% # number of syscalls executed 4126291SN/Atestsys.cpu.kern.syscall::98 2 2.41% 87.95% # number of syscalls executed 4136291SN/Atestsys.cpu.kern.syscall::101 2 2.41% 90.36% # number of syscalls executed 4146291SN/Atestsys.cpu.kern.syscall::102 2 2.41% 92.77% # number of syscalls executed 4156291SN/Atestsys.cpu.kern.syscall::104 1 1.20% 93.98% # number of syscalls executed 4166291SN/Atestsys.cpu.kern.syscall::105 3 3.61% 97.59% # number of syscalls executed 4176291SN/Atestsys.cpu.kern.syscall::118 2 2.41% 100.00% # number of syscalls executed 4186127SN/Atestsys.cpu.kern.syscall::total 83 # number of syscalls executed 4199729Sandreas.hansson@arm.comtestsys.cpu.kern.callpal::swpctx 438 0.34% 0.34% # number of callpals executed 4209449SAli.Saidi@ARM.comtestsys.cpu.kern.callpal::tbi 20 0.02% 0.36% # number of callpals executed 42110409Sandreas.hansson@arm.comtestsys.cpu.kern.callpal::swpipl 106832 83.26% 83.62% # number of callpals executed 4229449SAli.Saidi@ARM.comtestsys.cpu.kern.callpal::rdps 359 0.28% 83.90% # number of callpals executed 4239449SAli.Saidi@ARM.comtestsys.cpu.kern.callpal::wrusp 3 0.00% 83.90% # number of callpals executed 4249490Sandreas.hansson@arm.comtestsys.cpu.kern.callpal::rdusp 3 0.00% 83.90% # number of callpals executed 4259490Sandreas.hansson@arm.comtestsys.cpu.kern.callpal::rti 20470 15.95% 99.86% # number of callpals executed 4269449SAli.Saidi@ARM.comtestsys.cpu.kern.callpal::callsys 140 0.11% 99.97% # number of callpals executed 4279449SAli.Saidi@ARM.comtestsys.cpu.kern.callpal::imb 44 0.03% 100.00% # number of callpals executed 42810409Sandreas.hansson@arm.comtestsys.cpu.kern.callpal::total 128309 # number of callpals executed 4299729Sandreas.hansson@arm.comtestsys.cpu.kern.mode_switch::kernel 1280 # number of protection mode switches 43010409Sandreas.hansson@arm.comtestsys.cpu.kern.mode_switch::user 706 # number of protection mode switches 4319729Sandreas.hansson@arm.comtestsys.cpu.kern.mode_switch::idle 19629 # number of protection mode switches 43210409Sandreas.hansson@arm.comtestsys.cpu.kern.mode_good::kernel 711 43310409Sandreas.hansson@arm.comtestsys.cpu.kern.mode_good::user 706 4349729Sandreas.hansson@arm.comtestsys.cpu.kern.mode_good::idle 5 43510409Sandreas.hansson@arm.comtestsys.cpu.kern.mode_switch_good::kernel 0.555469 # fraction of useful protection mode switches 4368721SN/Atestsys.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 4379729Sandreas.hansson@arm.comtestsys.cpu.kern.mode_switch_good::idle 0.000255 # fraction of useful protection mode switches 43810409Sandreas.hansson@arm.comtestsys.cpu.kern.mode_switch_good::total 0.065788 # fraction of useful protection mode switches 43910409Sandreas.hansson@arm.comtestsys.cpu.kern.mode_ticks::kernel 994253000 59.96% 59.96% # number of ticks spent at the given mode 44010409Sandreas.hansson@arm.comtestsys.cpu.kern.mode_ticks::user 533088000 32.15% 92.11% # number of ticks spent at the given mode 44110409Sandreas.hansson@arm.comtestsys.cpu.kern.mode_ticks::idle 130749000 7.89% 100.00% # number of ticks spent at the given mode 4429729Sandreas.hansson@arm.comtestsys.cpu.kern.swap_context 438 # number of times the context was actually changed 44311245Sandreas.sandberg@arm.comtestsys.cpu.committedInsts 20257044 # Number of instructions committed 44411245Sandreas.sandberg@arm.comtestsys.cpu.committedOps 20257044 # Number of ops (including micro ops) committed 44511245Sandreas.sandberg@arm.comtestsys.cpu.num_int_alu_accesses 18836392 # Number of integer alu accesses 44611245Sandreas.sandberg@arm.comtestsys.cpu.num_fp_alu_accesses 17380 # Number of float alu accesses 44711245Sandreas.sandberg@arm.comtestsys.cpu.num_func_calls 1221158 # number of times a function call or return occured 44811245Sandreas.sandberg@arm.comtestsys.cpu.num_conditional_control_insts 1442105 # number of instructions that are conditional controls 44911245Sandreas.sandberg@arm.comtestsys.cpu.num_int_insts 18836392 # number of integer instructions 45011245Sandreas.sandberg@arm.comtestsys.cpu.num_fp_insts 17380 # number of float instructions 45111245Sandreas.sandberg@arm.comtestsys.cpu.num_int_register_reads 24786330 # number of times the integer registers were read 45211245Sandreas.sandberg@arm.comtestsys.cpu.num_int_register_writes 14693469 # number of times the integer registers were written 45311245Sandreas.sandberg@arm.comtestsys.cpu.num_fp_register_reads 11166 # number of times the floating registers were read 45411245Sandreas.sandberg@arm.comtestsys.cpu.num_fp_register_writes 10823 # number of times the floating registers were written 45511245Sandreas.sandberg@arm.comtestsys.cpu.num_mem_refs 6262732 # number of memory refs 45611245Sandreas.sandberg@arm.comtestsys.cpu.num_load_insts 3943883 # Number of load instructions 45711245Sandreas.sandberg@arm.comtestsys.cpu.num_store_insts 2318849 # Number of store instructions 45811245Sandreas.sandberg@arm.comtestsys.cpu.num_idle_cycles 380582482.461103 # Number of idle cycles 45911245Sandreas.sandberg@arm.comtestsys.cpu.num_busy_cycles 20243376.538897 # Number of busy cycles 46011245Sandreas.sandberg@arm.comtestsys.cpu.not_idle_fraction 0.050504 # Percentage of non-idle cycles 46111245Sandreas.sandberg@arm.comtestsys.cpu.idle_fraction 0.949496 # Percentage of idle cycles 46211245Sandreas.sandberg@arm.comtestsys.cpu.Branches 2929782 # Number of branches fetched 46311245Sandreas.sandberg@arm.comtestsys.cpu.op_class::No_OpClass 712785 3.52% 3.52% # Class of executed instruction 46411245Sandreas.sandberg@arm.comtestsys.cpu.op_class::IntAlu 12147004 59.95% 63.47% # Class of executed instruction 46511245Sandreas.sandberg@arm.comtestsys.cpu.op_class::IntMult 21654 0.11% 63.58% # Class of executed instruction 46611245Sandreas.sandberg@arm.comtestsys.cpu.op_class::IntDiv 0 0.00% 63.58% # Class of executed instruction 46711245Sandreas.sandberg@arm.comtestsys.cpu.op_class::FloatAdd 4655 0.02% 63.60% # Class of executed instruction 46811245Sandreas.sandberg@arm.comtestsys.cpu.op_class::FloatCmp 1 0.00% 63.60% # Class of executed instruction 46911245Sandreas.sandberg@arm.comtestsys.cpu.op_class::FloatCvt 0 0.00% 63.60% # Class of executed instruction 47011245Sandreas.sandberg@arm.comtestsys.cpu.op_class::FloatMult 0 0.00% 63.60% # Class of executed instruction 47111245Sandreas.sandberg@arm.comtestsys.cpu.op_class::FloatDiv 922 0.00% 63.60% # Class of executed instruction 47211245Sandreas.sandberg@arm.comtestsys.cpu.op_class::FloatSqrt 0 0.00% 63.60% # Class of executed instruction 47311245Sandreas.sandberg@arm.comtestsys.cpu.op_class::SimdAdd 0 0.00% 63.60% # Class of executed instruction 47411245Sandreas.sandberg@arm.comtestsys.cpu.op_class::SimdAddAcc 0 0.00% 63.60% # Class of executed instruction 47511245Sandreas.sandberg@arm.comtestsys.cpu.op_class::SimdAlu 0 0.00% 63.60% # Class of executed instruction 47611245Sandreas.sandberg@arm.comtestsys.cpu.op_class::SimdCmp 0 0.00% 63.60% # Class of executed instruction 47711245Sandreas.sandberg@arm.comtestsys.cpu.op_class::SimdCvt 0 0.00% 63.60% # Class of executed instruction 47811245Sandreas.sandberg@arm.comtestsys.cpu.op_class::SimdMisc 0 0.00% 63.60% # Class of executed instruction 47911245Sandreas.sandberg@arm.comtestsys.cpu.op_class::SimdMult 0 0.00% 63.60% # Class of executed instruction 48011245Sandreas.sandberg@arm.comtestsys.cpu.op_class::SimdMultAcc 0 0.00% 63.60% # Class of executed instruction 48111245Sandreas.sandberg@arm.comtestsys.cpu.op_class::SimdShift 0 0.00% 63.60% # Class of executed instruction 48211245Sandreas.sandberg@arm.comtestsys.cpu.op_class::SimdShiftAcc 0 0.00% 63.60% # Class of executed instruction 48311245Sandreas.sandberg@arm.comtestsys.cpu.op_class::SimdSqrt 0 0.00% 63.60% # Class of executed instruction 48411245Sandreas.sandberg@arm.comtestsys.cpu.op_class::SimdFloatAdd 0 0.00% 63.60% # Class of executed instruction 48511245Sandreas.sandberg@arm.comtestsys.cpu.op_class::SimdFloatAlu 0 0.00% 63.60% # Class of executed instruction 48611245Sandreas.sandberg@arm.comtestsys.cpu.op_class::SimdFloatCmp 0 0.00% 63.60% # Class of executed instruction 48711245Sandreas.sandberg@arm.comtestsys.cpu.op_class::SimdFloatCvt 0 0.00% 63.60% # Class of executed instruction 48811245Sandreas.sandberg@arm.comtestsys.cpu.op_class::SimdFloatDiv 0 0.00% 63.60% # Class of executed instruction 48911245Sandreas.sandberg@arm.comtestsys.cpu.op_class::SimdFloatMisc 0 0.00% 63.60% # Class of executed instruction 49011245Sandreas.sandberg@arm.comtestsys.cpu.op_class::SimdFloatMult 0 0.00% 63.60% # Class of executed instruction 49111245Sandreas.sandberg@arm.comtestsys.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.60% # Class of executed instruction 49211245Sandreas.sandberg@arm.comtestsys.cpu.op_class::SimdFloatSqrt 0 0.00% 63.60% # Class of executed instruction 49311245Sandreas.sandberg@arm.comtestsys.cpu.op_class::MemRead 4230485 20.88% 84.48% # Class of executed instruction 49411245Sandreas.sandberg@arm.comtestsys.cpu.op_class::MemWrite 2319388 11.45% 95.93% # Class of executed instruction 49511245Sandreas.sandberg@arm.comtestsys.cpu.op_class::IprAccess 824126 4.07% 100.00% # Class of executed instruction 49611245Sandreas.sandberg@arm.comtestsys.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 49711245Sandreas.sandberg@arm.comtestsys.cpu.op_class::total 20261020 # Class of executed instruction 49810778Snilay@cs.wisc.edutestsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 49910778Snilay@cs.wisc.edutestsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 50010778Snilay@cs.wisc.edutestsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 50110778Snilay@cs.wisc.edutestsys.disk0.dma_write_full_pages 0 # Number of full page size DMA writes. 50210778Snilay@cs.wisc.edutestsys.disk0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 50310778Snilay@cs.wisc.edutestsys.disk0.dma_write_txs 0 # Number of DMA write transactions. 50410778Snilay@cs.wisc.edutestsys.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 50510778Snilay@cs.wisc.edutestsys.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 50610778Snilay@cs.wisc.edutestsys.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 50710778Snilay@cs.wisc.edutestsys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes. 50810778Snilay@cs.wisc.edutestsys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 50910778Snilay@cs.wisc.edutestsys.disk2.dma_write_txs 0 # Number of DMA write transactions. 51010778Snilay@cs.wisc.edutestsys.iobus.trans_dist::ReadReq 2483943 # Transaction distribution 51110778Snilay@cs.wisc.edutestsys.iobus.trans_dist::ReadResp 2483943 # Transaction distribution 51210778Snilay@cs.wisc.edutestsys.iobus.trans_dist::WriteReq 39573 # Transaction distribution 51310778Snilay@cs.wisc.edutestsys.iobus.trans_dist::WriteResp 39573 # Transaction distribution 51410778Snilay@cs.wisc.edutestsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.cchip.pio 196204 # Packet count per connected master and slave (bytes) 51510778Snilay@cs.wisc.edutestsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.io.pio 336 # Packet count per connected master and slave (bytes) 51610778Snilay@cs.wisc.edutestsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.uart.pio 428 # Packet count per connected master and slave (bytes) 51710778Snilay@cs.wisc.edutestsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.ethernet.pio 78330 # Packet count per connected master and slave (bytes) 51810778Snilay@cs.wisc.edutestsys.iobus.pkt_count_testsys.bridge.master::total 275298 # Packet count per connected master and slave (bytes) 51910778Snilay@cs.wisc.edutestsys.iobus.pkt_count_testsys.tsunami.ethernet.dma::testsys.iobridge.slave 4771734 # Packet count per connected master and slave (bytes) 52010778Snilay@cs.wisc.edutestsys.iobus.pkt_count_testsys.tsunami.ethernet.dma::total 4771734 # Packet count per connected master and slave (bytes) 52110778Snilay@cs.wisc.edutestsys.iobus.pkt_count::total 5047032 # Packet count per connected master and slave (bytes) 52210778Snilay@cs.wisc.edutestsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.cchip.pio 784816 # Cumulative packet size per connected master and slave (bytes) 52310778Snilay@cs.wisc.edutestsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.io.pio 462 # Cumulative packet size per connected master and slave (bytes) 52410778Snilay@cs.wisc.edutestsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.uart.pio 214 # Cumulative packet size per connected master and slave (bytes) 52510778Snilay@cs.wisc.edutestsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.ethernet.pio 156660 # Cumulative packet size per connected master and slave (bytes) 52610778Snilay@cs.wisc.edutestsys.iobus.pkt_size_testsys.bridge.master::total 942152 # Cumulative packet size per connected master and slave (bytes) 52710778Snilay@cs.wisc.edutestsys.iobus.pkt_size_testsys.tsunami.ethernet.dma::testsys.iobridge.slave 57261398 # Cumulative packet size per connected master and slave (bytes) 52810778Snilay@cs.wisc.edutestsys.iobus.pkt_size_testsys.tsunami.ethernet.dma::total 57261398 # Cumulative packet size per connected master and slave (bytes) 52910778Snilay@cs.wisc.edutestsys.iobus.pkt_size::total 58203550 # Cumulative packet size per connected master and slave (bytes) 53010778Snilay@cs.wisc.edutestsys.membus.trans_dist::ReadReq 26478762 # Transaction distribution 53110778Snilay@cs.wisc.edutestsys.membus.trans_dist::ReadResp 26587372 # Transaction distribution 53210778Snilay@cs.wisc.edutestsys.membus.trans_dist::WriteReq 2189273 # Transaction distribution 53310778Snilay@cs.wisc.edutestsys.membus.trans_dist::WriteResp 2189273 # Transaction distribution 53410778Snilay@cs.wisc.edutestsys.membus.trans_dist::LoadLockedReq 108610 # Transaction distribution 53510778Snilay@cs.wisc.edutestsys.membus.trans_dist::StoreCondReq 108528 # Transaction distribution 53610778Snilay@cs.wisc.edutestsys.membus.trans_dist::StoreCondResp 108528 # Transaction distribution 53710778Snilay@cs.wisc.edutestsys.membus.pkt_count_testsys.cpu.icache_port::testsys.physmem.port 40522040 # Packet count per connected master and slave (bytes) 53810778Snilay@cs.wisc.edutestsys.membus.pkt_count_testsys.cpu.icache_port::total 40522040 # Packet count per connected master and slave (bytes) 53910778Snilay@cs.wisc.edutestsys.membus.pkt_count_testsys.cpu.dcache_port::testsys.bridge.slave 275298 # Packet count per connected master and slave (bytes) 54010778Snilay@cs.wisc.edutestsys.membus.pkt_count_testsys.cpu.dcache_port::testsys.physmem.port 12201274 # Packet count per connected master and slave (bytes) 54110778Snilay@cs.wisc.edutestsys.membus.pkt_count_testsys.cpu.dcache_port::total 12476572 # Packet count per connected master and slave (bytes) 54210778Snilay@cs.wisc.edutestsys.membus.pkt_count_testsys.iobridge.master::testsys.physmem.port 4771734 # Packet count per connected master and slave (bytes) 54310778Snilay@cs.wisc.edutestsys.membus.pkt_count_testsys.iobridge.master::total 4771734 # Packet count per connected master and slave (bytes) 54410778Snilay@cs.wisc.edutestsys.membus.pkt_count::total 57770346 # Packet count per connected master and slave (bytes) 54510778Snilay@cs.wisc.edutestsys.membus.pkt_size_testsys.cpu.icache_port::testsys.physmem.port 81044080 # Cumulative packet size per connected master and slave (bytes) 54610778Snilay@cs.wisc.edutestsys.membus.pkt_size_testsys.cpu.icache_port::total 81044080 # Cumulative packet size per connected master and slave (bytes) 54710778Snilay@cs.wisc.edutestsys.membus.pkt_size_testsys.cpu.dcache_port::testsys.bridge.slave 942152 # Cumulative packet size per connected master and slave (bytes) 54810778Snilay@cs.wisc.edutestsys.membus.pkt_size_testsys.cpu.dcache_port::testsys.physmem.port 44430520 # Cumulative packet size per connected master and slave (bytes) 54910778Snilay@cs.wisc.edutestsys.membus.pkt_size_testsys.cpu.dcache_port::total 45372672 # Cumulative packet size per connected master and slave (bytes) 55010778Snilay@cs.wisc.edutestsys.membus.pkt_size_testsys.iobridge.master::testsys.physmem.port 57261398 # Cumulative packet size per connected master and slave (bytes) 55110778Snilay@cs.wisc.edutestsys.membus.pkt_size_testsys.iobridge.master::total 57261398 # Cumulative packet size per connected master and slave (bytes) 55210778Snilay@cs.wisc.edutestsys.membus.pkt_size::total 183678150 # Cumulative packet size per connected master and slave (bytes) 55310778Snilay@cs.wisc.edutestsys.membus.snoops 0 # Total snoops (count) 55410827Sandreas.hansson@arm.comtestsys.membus.snoop_fanout::samples 28885173 # Request fanout histogram 55510827Sandreas.hansson@arm.comtestsys.membus.snoop_fanout::mean 0.784032 # Request fanout histogram 55610827Sandreas.hansson@arm.comtestsys.membus.snoop_fanout::stdev 0.411493 # Request fanout histogram 55710778Snilay@cs.wisc.edutestsys.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 55810827Sandreas.hansson@arm.comtestsys.membus.snoop_fanout::0 6238286 21.60% 21.60% # Request fanout histogram 55910827Sandreas.hansson@arm.comtestsys.membus.snoop_fanout::1 22646887 78.40% 100.00% # Request fanout histogram 56010778Snilay@cs.wisc.edutestsys.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 56110778Snilay@cs.wisc.edutestsys.membus.snoop_fanout::min_value 0 # Request fanout histogram 56210778Snilay@cs.wisc.edutestsys.membus.snoop_fanout::max_value 1 # Request fanout histogram 56310827Sandreas.hansson@arm.comtestsys.membus.snoop_fanout::total 28885173 # Request fanout histogram 56410036SAli.Saidi@ARM.comtestsys.tsunami.ethernet.clk_domain.clock 2000 # Clock period in ticks 5658721SN/Atestsys.tsunami.ethernet.txBytes 960 # Bytes Transmitted 5668721SN/Atestsys.tsunami.ethernet.rxBytes 798 # Bytes Received 5678721SN/Atestsys.tsunami.ethernet.txPackets 8 # Number of Packets Transmitted 5688721SN/Atestsys.tsunami.ethernet.rxPackets 5 # Number of Packets Received 5698721SN/Atestsys.tsunami.ethernet.txIpChecksums 2 # Number of tx IP Checksums done by device 5708721SN/Atestsys.tsunami.ethernet.rxIpChecksums 5 # Number of rx IP Checksums done by device 5718721SN/Atestsys.tsunami.ethernet.txTcpChecksums 2 # Number of tx TCP Checksums done by device 5728721SN/Atestsys.tsunami.ethernet.rxTcpChecksums 5 # Number of rx TCP Checksums done by device 5738721SN/Atestsys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 5748721SN/Atestsys.tsunami.ethernet.rxUdpChecksums 0 # Number of rx UDP Checksums done by device 5759729Sandreas.hansson@arm.comtestsys.tsunami.ethernet.descDMAReads 2385801 # Number of descriptors the device read w/ DMA 5763691SN/Atestsys.tsunami.ethernet.descDMAWrites 13 # Number of descriptors the device wrote w/ DMA 5779729Sandreas.hansson@arm.comtestsys.tsunami.ethernet.descDmaReadBytes 57259224 # number of descriptor bytes read w/ DMA 5783691SN/Atestsys.tsunami.ethernet.descDmaWriteBytes 104 # number of descriptor bytes write w/ DMA 5799449SAli.Saidi@ARM.comtestsys.tsunami.ethernet.totBandwidth 70176 # Total Bandwidth (bits/s) 5808721SN/Atestsys.tsunami.ethernet.totPackets 13 # Total Packets 5813691SN/Atestsys.tsunami.ethernet.totBytes 1758 # Total Bytes 5827461SN/Atestsys.tsunami.ethernet.totPPS 65 # Total Tranmission Rate (packets/s) 5839449SAli.Saidi@ARM.comtestsys.tsunami.ethernet.txBandwidth 38322 # Transmit Bandwidth (bits/s) 5849449SAli.Saidi@ARM.comtestsys.tsunami.ethernet.rxBandwidth 31855 # Receive Bandwidth (bits/s) 5858721SN/Atestsys.tsunami.ethernet.txPPS 40 # Packet Tranmission Rate (packets/s) 5868721SN/Atestsys.tsunami.ethernet.rxPPS 25 # Packet Reception Rate (packets/s) 5878721SN/Atestsys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 5888721SN/Atestsys.tsunami.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 5898721SN/Atestsys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 5908721SN/Atestsys.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 5918721SN/Atestsys.tsunami.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 5928721SN/Atestsys.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 5938721SN/Atestsys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 5948721SN/Atestsys.tsunami.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 5958721SN/Atestsys.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 5969247Sandreas.hansson@arm.comtestsys.tsunami.ethernet.postedRxDesc 5 # number of RxDesc interrupts posted to CPU 5978721SN/Atestsys.tsunami.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 5983691SN/Atestsys.tsunami.ethernet.totalRxDesc 5 # total number of RxDesc written to ISR 5998721SN/Atestsys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 6008721SN/Atestsys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 6018721SN/Atestsys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 6029490Sandreas.hansson@arm.comtestsys.tsunami.ethernet.postedTxIdle 19571 # number of TxIdle interrupts posted to CPU 6039247Sandreas.hansson@arm.comtestsys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post 6049729Sandreas.hansson@arm.comtestsys.tsunami.ethernet.totalTxIdle 2385801 # total number of TxIdle written to ISR 6058721SN/Atestsys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 6068721SN/Atestsys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 6078721SN/Atestsys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 6088721SN/Atestsys.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 6098721SN/Atestsys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 6103691SN/Atestsys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 6118721SN/Atestsys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post 6129729Sandreas.hansson@arm.comtestsys.tsunami.ethernet.postedInterrupts 2385819 # number of posts to CPU 6138721SN/Atestsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped 61410778Snilay@cs.wisc.edu 61510778Snilay@cs.wisc.edu---------- End Simulation Statistics ---------- 61610778Snilay@cs.wisc.edu 61710778Snilay@cs.wisc.edu---------- Begin Simulation Statistics ---------- 61810778Snilay@cs.wisc.edusim_seconds 0.000407 # Number of seconds simulated 61910778Snilay@cs.wisc.edusim_ticks 407341500 # Number of ticks simulated 62010778Snilay@cs.wisc.edufinal_tick 4321620817500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 62110778Snilay@cs.wisc.edusim_freq 1000000000000 # Frequency of simulated ticks 62211245Sandreas.sandberg@arm.comhost_inst_rate 5761027657 # Simulator instruction rate (inst/s) 62311245Sandreas.sandberg@arm.comhost_op_rate 5760057644 # Simulator op (including micro ops) rate (op/s) 62411245Sandreas.sandberg@arm.comhost_tick_rate 4478236963 # Simulator tick rate (ticks/s) 62511245Sandreas.sandberg@arm.comhost_mem_usage 500080 # Number of bytes of host memory used 62611245Sandreas.sandberg@arm.comhost_seconds 0.09 # Real time elapsed on the host 62710778Snilay@cs.wisc.edusim_insts 523853183 # Number of instructions simulated 62810778Snilay@cs.wisc.edusim_ops 523853183 # Number of ops (including micro ops) simulated 62910036SAli.Saidi@ARM.comdrivesys.voltage_domain.voltage 1 # Voltage in Volts 63010036SAli.Saidi@ARM.comdrivesys.clk_domain.clock 1000 # Clock period in ticks 63110778Snilay@cs.wisc.edudrivesys.physmem.bytes_read::cpu.inst 144608 # Number of bytes read from this memory 63210778Snilay@cs.wisc.edudrivesys.physmem.bytes_read::cpu.data 49952 # Number of bytes read from this memory 63310778Snilay@cs.wisc.edudrivesys.physmem.bytes_read::tsunami.ethernet 116400 # Number of bytes read from this memory 63410778Snilay@cs.wisc.edudrivesys.physmem.bytes_read::total 310960 # Number of bytes read from this memory 63510778Snilay@cs.wisc.edudrivesys.physmem.bytes_inst_read::cpu.inst 144608 # Number of instructions bytes read from this memory 63610778Snilay@cs.wisc.edudrivesys.physmem.bytes_inst_read::total 144608 # Number of instructions bytes read from this memory 63710778Snilay@cs.wisc.edudrivesys.physmem.bytes_written::cpu.data 27688 # Number of bytes written to this memory 63810778Snilay@cs.wisc.edudrivesys.physmem.bytes_written::total 27688 # Number of bytes written to this memory 63910778Snilay@cs.wisc.edudrivesys.physmem.num_reads::cpu.inst 36152 # Number of read requests responded to by this memory 64010778Snilay@cs.wisc.edudrivesys.physmem.num_reads::cpu.data 6909 # Number of read requests responded to by this memory 64110778Snilay@cs.wisc.edudrivesys.physmem.num_reads::tsunami.ethernet 4850 # Number of read requests responded to by this memory 64210778Snilay@cs.wisc.edudrivesys.physmem.num_reads::total 47911 # Number of read requests responded to by this memory 64310778Snilay@cs.wisc.edudrivesys.physmem.num_writes::cpu.data 3812 # Number of write requests responded to by this memory 64410778Snilay@cs.wisc.edudrivesys.physmem.num_writes::total 3812 # Number of write requests responded to by this memory 64510778Snilay@cs.wisc.edudrivesys.physmem.bw_read::cpu.inst 355004339 # Total read bandwidth from this memory (bytes/s) 64610778Snilay@cs.wisc.edudrivesys.physmem.bw_read::cpu.data 122629293 # Total read bandwidth from this memory (bytes/s) 64710778Snilay@cs.wisc.edudrivesys.physmem.bw_read::tsunami.ethernet 285755318 # Total read bandwidth from this memory (bytes/s) 64810778Snilay@cs.wisc.edudrivesys.physmem.bw_read::total 763388950 # Total read bandwidth from this memory (bytes/s) 64910778Snilay@cs.wisc.edudrivesys.physmem.bw_inst_read::cpu.inst 355004339 # Instruction read bandwidth from this memory (bytes/s) 65010778Snilay@cs.wisc.edudrivesys.physmem.bw_inst_read::total 355004339 # Instruction read bandwidth from this memory (bytes/s) 65110778Snilay@cs.wisc.edudrivesys.physmem.bw_write::cpu.data 67972451 # Write bandwidth from this memory (bytes/s) 65210778Snilay@cs.wisc.edudrivesys.physmem.bw_write::total 67972451 # Write bandwidth from this memory (bytes/s) 65310778Snilay@cs.wisc.edudrivesys.physmem.bw_total::cpu.inst 355004339 # Total bandwidth to/from this memory (bytes/s) 65410778Snilay@cs.wisc.edudrivesys.physmem.bw_total::cpu.data 190601743 # Total bandwidth to/from this memory (bytes/s) 65510778Snilay@cs.wisc.edudrivesys.physmem.bw_total::tsunami.ethernet 285755318 # Total bandwidth to/from this memory (bytes/s) 65610778Snilay@cs.wisc.edudrivesys.physmem.bw_total::total 831361401 # Total bandwidth to/from this memory (bytes/s) 65710778Snilay@cs.wisc.edudrivesys.cpu.clk_domain.clock 250 # Clock period in ticks 65810778Snilay@cs.wisc.edudrivesys.cpu.dtb.fetch_hits 0 # ITB hits 65910778Snilay@cs.wisc.edudrivesys.cpu.dtb.fetch_misses 0 # ITB misses 66010778Snilay@cs.wisc.edudrivesys.cpu.dtb.fetch_acv 0 # ITB acv 66110778Snilay@cs.wisc.edudrivesys.cpu.dtb.fetch_accesses 0 # ITB accesses 66210778Snilay@cs.wisc.edudrivesys.cpu.dtb.read_hits 7069 # DTB read hits 66310778Snilay@cs.wisc.edudrivesys.cpu.dtb.read_misses 0 # DTB read misses 66410778Snilay@cs.wisc.edudrivesys.cpu.dtb.read_acv 0 # DTB read access violations 66510778Snilay@cs.wisc.edudrivesys.cpu.dtb.read_accesses 0 # DTB read accesses 66610778Snilay@cs.wisc.edudrivesys.cpu.dtb.write_hits 3933 # DTB write hits 66710778Snilay@cs.wisc.edudrivesys.cpu.dtb.write_misses 0 # DTB write misses 66810778Snilay@cs.wisc.edudrivesys.cpu.dtb.write_acv 0 # DTB write access violations 66910778Snilay@cs.wisc.edudrivesys.cpu.dtb.write_accesses 0 # DTB write accesses 67010778Snilay@cs.wisc.edudrivesys.cpu.dtb.data_hits 11002 # DTB hits 67110778Snilay@cs.wisc.edudrivesys.cpu.dtb.data_misses 0 # DTB misses 67210778Snilay@cs.wisc.edudrivesys.cpu.dtb.data_acv 0 # DTB access violations 67310778Snilay@cs.wisc.edudrivesys.cpu.dtb.data_accesses 0 # DTB accesses 67410778Snilay@cs.wisc.edudrivesys.cpu.itb.fetch_hits 5992 # ITB hits 67510778Snilay@cs.wisc.edudrivesys.cpu.itb.fetch_misses 0 # ITB misses 67610778Snilay@cs.wisc.edudrivesys.cpu.itb.fetch_acv 0 # ITB acv 67710778Snilay@cs.wisc.edudrivesys.cpu.itb.fetch_accesses 5992 # ITB accesses 67810778Snilay@cs.wisc.edudrivesys.cpu.itb.read_hits 0 # DTB read hits 67910778Snilay@cs.wisc.edudrivesys.cpu.itb.read_misses 0 # DTB read misses 68010778Snilay@cs.wisc.edudrivesys.cpu.itb.read_acv 0 # DTB read access violations 68110778Snilay@cs.wisc.edudrivesys.cpu.itb.read_accesses 0 # DTB read accesses 68210778Snilay@cs.wisc.edudrivesys.cpu.itb.write_hits 0 # DTB write hits 68310778Snilay@cs.wisc.edudrivesys.cpu.itb.write_misses 0 # DTB write misses 68410778Snilay@cs.wisc.edudrivesys.cpu.itb.write_acv 0 # DTB write access violations 68510778Snilay@cs.wisc.edudrivesys.cpu.itb.write_accesses 0 # DTB write accesses 68610778Snilay@cs.wisc.edudrivesys.cpu.itb.data_hits 0 # DTB hits 68710778Snilay@cs.wisc.edudrivesys.cpu.itb.data_misses 0 # DTB misses 68810778Snilay@cs.wisc.edudrivesys.cpu.itb.data_acv 0 # DTB access violations 68910778Snilay@cs.wisc.edudrivesys.cpu.itb.data_accesses 0 # DTB accesses 69010778Snilay@cs.wisc.edudrivesys.cpu.numCycles 1626281 # number of cpu cycles simulated 69110778Snilay@cs.wisc.edudrivesys.cpu.numWorkItemsStarted 0 # number of work items this cpu started 69210778Snilay@cs.wisc.edudrivesys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 69311245Sandreas.sandberg@arm.comdrivesys.cpu.kern.inst.arm 0 # number of arm instructions executed 69411245Sandreas.sandberg@arm.comdrivesys.cpu.kern.inst.quiesce 41 # number of quiesce instructions executed 69511245Sandreas.sandberg@arm.comdrivesys.cpu.kern.inst.hwrei 295 # number of hwrei instructions executed 69611245Sandreas.sandberg@arm.comdrivesys.cpu.kern.ipl_count::0 123 41.84% 41.84% # number of times we switched to this ipl 69711245Sandreas.sandberg@arm.comdrivesys.cpu.kern.ipl_count::21 40 13.61% 55.44% # number of times we switched to this ipl 69811245Sandreas.sandberg@arm.comdrivesys.cpu.kern.ipl_count::22 1 0.34% 55.78% # number of times we switched to this ipl 69911245Sandreas.sandberg@arm.comdrivesys.cpu.kern.ipl_count::31 130 44.22% 100.00% # number of times we switched to this ipl 70011245Sandreas.sandberg@arm.comdrivesys.cpu.kern.ipl_count::total 294 # number of times we switched to this ipl 70111245Sandreas.sandberg@arm.comdrivesys.cpu.kern.ipl_good::0 123 42.86% 42.86% # number of times we switched to this ipl from a different ipl 70211245Sandreas.sandberg@arm.comdrivesys.cpu.kern.ipl_good::21 40 13.94% 56.79% # number of times we switched to this ipl from a different ipl 70311245Sandreas.sandberg@arm.comdrivesys.cpu.kern.ipl_good::22 1 0.35% 57.14% # number of times we switched to this ipl from a different ipl 70411245Sandreas.sandberg@arm.comdrivesys.cpu.kern.ipl_good::31 123 42.86% 100.00% # number of times we switched to this ipl from a different ipl 70511245Sandreas.sandberg@arm.comdrivesys.cpu.kern.ipl_good::total 287 # number of times we switched to this ipl from a different ipl 70611245Sandreas.sandberg@arm.comdrivesys.cpu.kern.ipl_ticks::0 400289000 98.46% 98.46% # number of cycles we spent at this ipl 70711245Sandreas.sandberg@arm.comdrivesys.cpu.kern.ipl_ticks::21 1620000 0.40% 98.86% # number of cycles we spent at this ipl 70811245Sandreas.sandberg@arm.comdrivesys.cpu.kern.ipl_ticks::22 21500 0.01% 98.86% # number of cycles we spent at this ipl 70911245Sandreas.sandberg@arm.comdrivesys.cpu.kern.ipl_ticks::31 4629500 1.14% 100.00% # number of cycles we spent at this ipl 71011245Sandreas.sandberg@arm.comdrivesys.cpu.kern.ipl_ticks::total 406560000 # number of cycles we spent at this ipl 71111245Sandreas.sandberg@arm.comdrivesys.cpu.kern.ipl_used::0 1 # fraction of swpipl calls that actually changed the ipl 71211245Sandreas.sandberg@arm.comdrivesys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 71311245Sandreas.sandberg@arm.comdrivesys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 71411245Sandreas.sandberg@arm.comdrivesys.cpu.kern.ipl_used::31 0.946154 # fraction of swpipl calls that actually changed the ipl 71511245Sandreas.sandberg@arm.comdrivesys.cpu.kern.ipl_used::total 0.976190 # fraction of swpipl calls that actually changed the ipl 71611245Sandreas.sandberg@arm.comdrivesys.cpu.kern.callpal::swpipl 212 83.46% 83.46% # number of callpals executed 71711245Sandreas.sandberg@arm.comdrivesys.cpu.kern.callpal::rdps 1 0.39% 83.86% # number of callpals executed 71811245Sandreas.sandberg@arm.comdrivesys.cpu.kern.callpal::rti 41 16.14% 100.00% # number of callpals executed 71911245Sandreas.sandberg@arm.comdrivesys.cpu.kern.callpal::total 254 # number of callpals executed 72011245Sandreas.sandberg@arm.comdrivesys.cpu.kern.mode_switch::kernel 0 # number of protection mode switches 72111245Sandreas.sandberg@arm.comdrivesys.cpu.kern.mode_switch::user 0 # number of protection mode switches 72211245Sandreas.sandberg@arm.comdrivesys.cpu.kern.mode_switch::idle 41 # number of protection mode switches 72311245Sandreas.sandberg@arm.comdrivesys.cpu.kern.mode_good::kernel 0 72411245Sandreas.sandberg@arm.comdrivesys.cpu.kern.mode_good::user 0 72511245Sandreas.sandberg@arm.comdrivesys.cpu.kern.mode_good::idle 0 72611245Sandreas.sandberg@arm.comdrivesys.cpu.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches 72711245Sandreas.sandberg@arm.comdrivesys.cpu.kern.mode_switch_good::user nan # fraction of useful protection mode switches 72811245Sandreas.sandberg@arm.comdrivesys.cpu.kern.mode_switch_good::idle 0 # fraction of useful protection mode switches 72911245Sandreas.sandberg@arm.comdrivesys.cpu.kern.mode_switch_good::total 0 # fraction of useful protection mode switches 73011245Sandreas.sandberg@arm.comdrivesys.cpu.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode 73111245Sandreas.sandberg@arm.comdrivesys.cpu.kern.mode_ticks::user 0 # number of ticks spent at the given mode 73211245Sandreas.sandberg@arm.comdrivesys.cpu.kern.mode_ticks::idle 0 # number of ticks spent at the given mode 73311245Sandreas.sandberg@arm.comdrivesys.cpu.kern.swap_context 0 # number of times the context was actually changed 73410778Snilay@cs.wisc.edudrivesys.cpu.committedInsts 36152 # Number of instructions committed 73510778Snilay@cs.wisc.edudrivesys.cpu.committedOps 36152 # Number of ops (including micro ops) committed 73610778Snilay@cs.wisc.edudrivesys.cpu.num_int_alu_accesses 33516 # Number of integer alu accesses 73710778Snilay@cs.wisc.edudrivesys.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 73810778Snilay@cs.wisc.edudrivesys.cpu.num_func_calls 2388 # number of times a function call or return occured 73910778Snilay@cs.wisc.edudrivesys.cpu.num_conditional_control_insts 2347 # number of instructions that are conditional controls 74010778Snilay@cs.wisc.edudrivesys.cpu.num_int_insts 33516 # number of integer instructions 74110778Snilay@cs.wisc.edudrivesys.cpu.num_fp_insts 0 # number of float instructions 74210778Snilay@cs.wisc.edudrivesys.cpu.num_int_register_reads 43772 # number of times the integer registers were read 74310778Snilay@cs.wisc.edudrivesys.cpu.num_int_register_writes 26499 # number of times the integer registers were written 74410778Snilay@cs.wisc.edudrivesys.cpu.num_fp_register_reads 0 # number of times the floating registers were read 74510778Snilay@cs.wisc.edudrivesys.cpu.num_fp_register_writes 0 # number of times the floating registers were written 74610778Snilay@cs.wisc.edudrivesys.cpu.num_mem_refs 11043 # number of memory refs 74710778Snilay@cs.wisc.edudrivesys.cpu.num_load_insts 7109 # Number of load instructions 74810778Snilay@cs.wisc.edudrivesys.cpu.num_store_insts 3934 # Number of store instructions 74910778Snilay@cs.wisc.edudrivesys.cpu.num_idle_cycles 1590238.371734 # Number of idle cycles 75010778Snilay@cs.wisc.edudrivesys.cpu.num_busy_cycles 36042.628266 # Number of busy cycles 75110778Snilay@cs.wisc.edudrivesys.cpu.not_idle_fraction 0.022163 # Percentage of non-idle cycles 75210778Snilay@cs.wisc.edudrivesys.cpu.idle_fraction 0.977837 # Percentage of idle cycles 75310778Snilay@cs.wisc.edudrivesys.cpu.Branches 5243 # Number of branches fetched 75410778Snilay@cs.wisc.edudrivesys.cpu.op_class::No_OpClass 1262 3.49% 3.49% # Class of executed instruction 75510778Snilay@cs.wisc.edudrivesys.cpu.op_class::IntAlu 21687 59.99% 63.48% # Class of executed instruction 75610778Snilay@cs.wisc.edudrivesys.cpu.op_class::IntMult 44 0.12% 63.60% # Class of executed instruction 75710778Snilay@cs.wisc.edudrivesys.cpu.op_class::IntDiv 0 0.00% 63.60% # Class of executed instruction 75810778Snilay@cs.wisc.edudrivesys.cpu.op_class::FloatAdd 0 0.00% 63.60% # Class of executed instruction 75910778Snilay@cs.wisc.edudrivesys.cpu.op_class::FloatCmp 0 0.00% 63.60% # Class of executed instruction 76010778Snilay@cs.wisc.edudrivesys.cpu.op_class::FloatCvt 0 0.00% 63.60% # Class of executed instruction 76110778Snilay@cs.wisc.edudrivesys.cpu.op_class::FloatMult 0 0.00% 63.60% # Class of executed instruction 76210778Snilay@cs.wisc.edudrivesys.cpu.op_class::FloatDiv 0 0.00% 63.60% # Class of executed instruction 76310778Snilay@cs.wisc.edudrivesys.cpu.op_class::FloatSqrt 0 0.00% 63.60% # Class of executed instruction 76410778Snilay@cs.wisc.edudrivesys.cpu.op_class::SimdAdd 0 0.00% 63.60% # Class of executed instruction 76510778Snilay@cs.wisc.edudrivesys.cpu.op_class::SimdAddAcc 0 0.00% 63.60% # Class of executed instruction 76610778Snilay@cs.wisc.edudrivesys.cpu.op_class::SimdAlu 0 0.00% 63.60% # Class of executed instruction 76710778Snilay@cs.wisc.edudrivesys.cpu.op_class::SimdCmp 0 0.00% 63.60% # Class of executed instruction 76810778Snilay@cs.wisc.edudrivesys.cpu.op_class::SimdCvt 0 0.00% 63.60% # Class of executed instruction 76910778Snilay@cs.wisc.edudrivesys.cpu.op_class::SimdMisc 0 0.00% 63.60% # Class of executed instruction 77010778Snilay@cs.wisc.edudrivesys.cpu.op_class::SimdMult 0 0.00% 63.60% # Class of executed instruction 77110778Snilay@cs.wisc.edudrivesys.cpu.op_class::SimdMultAcc 0 0.00% 63.60% # Class of executed instruction 77210778Snilay@cs.wisc.edudrivesys.cpu.op_class::SimdShift 0 0.00% 63.60% # Class of executed instruction 77310778Snilay@cs.wisc.edudrivesys.cpu.op_class::SimdShiftAcc 0 0.00% 63.60% # Class of executed instruction 77410778Snilay@cs.wisc.edudrivesys.cpu.op_class::SimdSqrt 0 0.00% 63.60% # Class of executed instruction 77510778Snilay@cs.wisc.edudrivesys.cpu.op_class::SimdFloatAdd 0 0.00% 63.60% # Class of executed instruction 77610778Snilay@cs.wisc.edudrivesys.cpu.op_class::SimdFloatAlu 0 0.00% 63.60% # Class of executed instruction 77710778Snilay@cs.wisc.edudrivesys.cpu.op_class::SimdFloatCmp 0 0.00% 63.60% # Class of executed instruction 77810778Snilay@cs.wisc.edudrivesys.cpu.op_class::SimdFloatCvt 0 0.00% 63.60% # Class of executed instruction 77910778Snilay@cs.wisc.edudrivesys.cpu.op_class::SimdFloatDiv 0 0.00% 63.60% # Class of executed instruction 78010778Snilay@cs.wisc.edudrivesys.cpu.op_class::SimdFloatMisc 0 0.00% 63.60% # Class of executed instruction 78110778Snilay@cs.wisc.edudrivesys.cpu.op_class::SimdFloatMult 0 0.00% 63.60% # Class of executed instruction 78210778Snilay@cs.wisc.edudrivesys.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.60% # Class of executed instruction 78310778Snilay@cs.wisc.edudrivesys.cpu.op_class::SimdFloatSqrt 0 0.00% 63.60% # Class of executed instruction 78410778Snilay@cs.wisc.edudrivesys.cpu.op_class::MemRead 7678 21.24% 84.84% # Class of executed instruction 78510778Snilay@cs.wisc.edudrivesys.cpu.op_class::MemWrite 3936 10.89% 95.73% # Class of executed instruction 78610778Snilay@cs.wisc.edudrivesys.cpu.op_class::IprAccess 1545 4.27% 100.00% # Class of executed instruction 78710778Snilay@cs.wisc.edudrivesys.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 78810778Snilay@cs.wisc.edudrivesys.cpu.op_class::total 36152 # Class of executed instruction 7898721SN/Adrivesys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 7908721SN/Adrivesys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 7918721SN/Adrivesys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 7928721SN/Adrivesys.disk0.dma_write_full_pages 0 # Number of full page size DMA writes. 7938721SN/Adrivesys.disk0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 7948721SN/Adrivesys.disk0.dma_write_txs 0 # Number of DMA write transactions. 7958721SN/Adrivesys.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 7968721SN/Adrivesys.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 7978721SN/Adrivesys.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 7988721SN/Adrivesys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes. 7998721SN/Adrivesys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 8008721SN/Adrivesys.disk2.dma_write_txs 0 # Number of DMA write transactions. 80110778Snilay@cs.wisc.edudrivesys.iobus.trans_dist::ReadReq 5050 # Transaction distribution 80210778Snilay@cs.wisc.edudrivesys.iobus.trans_dist::ReadResp 5050 # Transaction distribution 80310778Snilay@cs.wisc.edudrivesys.iobus.trans_dist::WriteReq 81 # Transaction distribution 80410778Snilay@cs.wisc.edudrivesys.iobus.trans_dist::WriteResp 81 # Transaction distribution 80510778Snilay@cs.wisc.edudrivesys.iobus.pkt_count_drivesys.bridge.master::drivesys.tsunami.cchip.pio 402 # Packet count per connected master and slave (bytes) 80610778Snilay@cs.wisc.edudrivesys.iobus.pkt_count_drivesys.bridge.master::drivesys.tsunami.ethernet.pio 160 # Packet count per connected master and slave (bytes) 80710778Snilay@cs.wisc.edudrivesys.iobus.pkt_count_drivesys.bridge.master::total 562 # Packet count per connected master and slave (bytes) 80810778Snilay@cs.wisc.edudrivesys.iobus.pkt_count_drivesys.tsunami.ethernet.dma::drivesys.iobridge.slave 9700 # Packet count per connected master and slave (bytes) 80910778Snilay@cs.wisc.edudrivesys.iobus.pkt_count_drivesys.tsunami.ethernet.dma::total 9700 # Packet count per connected master and slave (bytes) 81010778Snilay@cs.wisc.edudrivesys.iobus.pkt_count::total 10262 # Packet count per connected master and slave (bytes) 81110778Snilay@cs.wisc.edudrivesys.iobus.pkt_size_drivesys.bridge.master::drivesys.tsunami.cchip.pio 1608 # Cumulative packet size per connected master and slave (bytes) 81210778Snilay@cs.wisc.edudrivesys.iobus.pkt_size_drivesys.bridge.master::drivesys.tsunami.ethernet.pio 320 # Cumulative packet size per connected master and slave (bytes) 81310778Snilay@cs.wisc.edudrivesys.iobus.pkt_size_drivesys.bridge.master::total 1928 # Cumulative packet size per connected master and slave (bytes) 81410778Snilay@cs.wisc.edudrivesys.iobus.pkt_size_drivesys.tsunami.ethernet.dma::drivesys.iobridge.slave 116400 # Cumulative packet size per connected master and slave (bytes) 81510778Snilay@cs.wisc.edudrivesys.iobus.pkt_size_drivesys.tsunami.ethernet.dma::total 116400 # Cumulative packet size per connected master and slave (bytes) 81610778Snilay@cs.wisc.edudrivesys.iobus.pkt_size::total 118328 # Cumulative packet size per connected master and slave (bytes) 81710778Snilay@cs.wisc.edudrivesys.membus.trans_dist::ReadReq 47907 # Transaction distribution 81810778Snilay@cs.wisc.edudrivesys.membus.trans_dist::ReadResp 48111 # Transaction distribution 81910778Snilay@cs.wisc.edudrivesys.membus.trans_dist::WriteReq 3689 # Transaction distribution 82010778Snilay@cs.wisc.edudrivesys.membus.trans_dist::WriteResp 3689 # Transaction distribution 82110778Snilay@cs.wisc.edudrivesys.membus.trans_dist::LoadLockedReq 204 # Transaction distribution 82210778Snilay@cs.wisc.edudrivesys.membus.trans_dist::StoreCondReq 204 # Transaction distribution 82310778Snilay@cs.wisc.edudrivesys.membus.trans_dist::StoreCondResp 204 # Transaction distribution 82410778Snilay@cs.wisc.edudrivesys.membus.pkt_count_drivesys.cpu.icache_port::drivesys.physmem.port 72304 # Packet count per connected master and slave (bytes) 82510778Snilay@cs.wisc.edudrivesys.membus.pkt_count_drivesys.cpu.icache_port::total 72304 # Packet count per connected master and slave (bytes) 82610778Snilay@cs.wisc.edudrivesys.membus.pkt_count_drivesys.cpu.dcache_port::drivesys.bridge.slave 562 # Packet count per connected master and slave (bytes) 82710778Snilay@cs.wisc.edudrivesys.membus.pkt_count_drivesys.cpu.dcache_port::drivesys.physmem.port 21442 # Packet count per connected master and slave (bytes) 82810778Snilay@cs.wisc.edudrivesys.membus.pkt_count_drivesys.cpu.dcache_port::total 22004 # Packet count per connected master and slave (bytes) 82910778Snilay@cs.wisc.edudrivesys.membus.pkt_count_drivesys.iobridge.master::drivesys.physmem.port 9700 # Packet count per connected master and slave (bytes) 83010778Snilay@cs.wisc.edudrivesys.membus.pkt_count_drivesys.iobridge.master::total 9700 # Packet count per connected master and slave (bytes) 83110778Snilay@cs.wisc.edudrivesys.membus.pkt_count::total 104008 # Packet count per connected master and slave (bytes) 83210778Snilay@cs.wisc.edudrivesys.membus.pkt_size_drivesys.cpu.icache_port::drivesys.physmem.port 144608 # Cumulative packet size per connected master and slave (bytes) 83310778Snilay@cs.wisc.edudrivesys.membus.pkt_size_drivesys.cpu.icache_port::total 144608 # Cumulative packet size per connected master and slave (bytes) 83410778Snilay@cs.wisc.edudrivesys.membus.pkt_size_drivesys.cpu.dcache_port::drivesys.bridge.slave 1928 # Cumulative packet size per connected master and slave (bytes) 83510778Snilay@cs.wisc.edudrivesys.membus.pkt_size_drivesys.cpu.dcache_port::drivesys.physmem.port 77640 # Cumulative packet size per connected master and slave (bytes) 83610778Snilay@cs.wisc.edudrivesys.membus.pkt_size_drivesys.cpu.dcache_port::total 79568 # Cumulative packet size per connected master and slave (bytes) 83710778Snilay@cs.wisc.edudrivesys.membus.pkt_size_drivesys.iobridge.master::drivesys.physmem.port 116400 # Cumulative packet size per connected master and slave (bytes) 83810778Snilay@cs.wisc.edudrivesys.membus.pkt_size_drivesys.iobridge.master::total 116400 # Cumulative packet size per connected master and slave (bytes) 83910778Snilay@cs.wisc.edudrivesys.membus.pkt_size::total 340576 # Cumulative packet size per connected master and slave (bytes) 84010778Snilay@cs.wisc.edudrivesys.membus.snoops 0 # Total snoops (count) 84110827Sandreas.hansson@arm.comdrivesys.membus.snoop_fanout::samples 52004 # Request fanout histogram 84210827Sandreas.hansson@arm.comdrivesys.membus.snoop_fanout::mean 0.788439 # Request fanout histogram 84310827Sandreas.hansson@arm.comdrivesys.membus.snoop_fanout::stdev 0.408419 # Request fanout histogram 84410778Snilay@cs.wisc.edudrivesys.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 84510827Sandreas.hansson@arm.comdrivesys.membus.snoop_fanout::0 11002 21.16% 21.16% # Request fanout histogram 84610827Sandreas.hansson@arm.comdrivesys.membus.snoop_fanout::1 41002 78.84% 100.00% # Request fanout histogram 84710778Snilay@cs.wisc.edudrivesys.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 84810778Snilay@cs.wisc.edudrivesys.membus.snoop_fanout::min_value 0 # Request fanout histogram 84910778Snilay@cs.wisc.edudrivesys.membus.snoop_fanout::max_value 1 # Request fanout histogram 85010827Sandreas.hansson@arm.comdrivesys.membus.snoop_fanout::total 52004 # Request fanout histogram 85110036SAli.Saidi@ARM.comdrivesys.tsunami.ethernet.clk_domain.clock 2000 # Clock period in ticks 85210778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.descDMAReads 4850 # Number of descriptors the device read w/ DMA 85310778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 85410778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.descDmaReadBytes 116400 # number of descriptor bytes read w/ DMA 85510778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 8568721SN/Adrivesys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 8578721SN/Adrivesys.tsunami.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 8588721SN/Adrivesys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 8598721SN/Adrivesys.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 8608721SN/Adrivesys.tsunami.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 8618721SN/Adrivesys.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 8628721SN/Adrivesys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 8638721SN/Adrivesys.tsunami.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 8648721SN/Adrivesys.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 86510778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 8669449SAli.Saidi@ARM.comdrivesys.tsunami.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 86710778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 8688721SN/Adrivesys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 8698721SN/Adrivesys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 8708721SN/Adrivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 87110778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.postedTxIdle 40 # number of TxIdle interrupts posted to CPU 8729449SAli.Saidi@ARM.comdrivesys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post 87310778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.totalTxIdle 4850 # total number of TxIdle written to ISR 8748721SN/Adrivesys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 8758721SN/Adrivesys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 8768721SN/Adrivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 8778721SN/Adrivesys.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 8788721SN/Adrivesys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 8798721SN/Adrivesys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 8808721SN/Adrivesys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post 88110778Snilay@cs.wisc.edudrivesys.tsunami.ethernet.postedInterrupts 4850 # number of posts to CPU 8828721SN/Adrivesys.tsunami.ethernet.droppedPackets 0 # number of packets dropped 88310036SAli.Saidi@ARM.comtestsys.voltage_domain.voltage 1 # Voltage in Volts 88410036SAli.Saidi@ARM.comtestsys.clk_domain.clock 1000 # Clock period in ticks 8859729Sandreas.hansson@arm.comtestsys.physmem.bytes_read::cpu.inst 144504 # Number of bytes read from this memory 8869729Sandreas.hansson@arm.comtestsys.physmem.bytes_read::cpu.data 49936 # Number of bytes read from this memory 8879729Sandreas.hansson@arm.comtestsys.physmem.bytes_read::tsunami.ethernet 116376 # Number of bytes read from this memory 8889729Sandreas.hansson@arm.comtestsys.physmem.bytes_read::total 310816 # Number of bytes read from this memory 8899729Sandreas.hansson@arm.comtestsys.physmem.bytes_inst_read::cpu.inst 144504 # Number of instructions bytes read from this memory 8909729Sandreas.hansson@arm.comtestsys.physmem.bytes_inst_read::total 144504 # Number of instructions bytes read from this memory 8919729Sandreas.hansson@arm.comtestsys.physmem.bytes_written::cpu.data 27704 # Number of bytes written to this memory 8929729Sandreas.hansson@arm.comtestsys.physmem.bytes_written::total 27704 # Number of bytes written to this memory 8939729Sandreas.hansson@arm.comtestsys.physmem.num_reads::cpu.inst 36126 # Number of read requests responded to by this memory 8949729Sandreas.hansson@arm.comtestsys.physmem.num_reads::cpu.data 6905 # Number of read requests responded to by this memory 8959729Sandreas.hansson@arm.comtestsys.physmem.num_reads::tsunami.ethernet 4849 # Number of read requests responded to by this memory 8969729Sandreas.hansson@arm.comtestsys.physmem.num_reads::total 47880 # Number of read requests responded to by this memory 8979729Sandreas.hansson@arm.comtestsys.physmem.num_writes::cpu.data 3814 # Number of write requests responded to by this memory 8989729Sandreas.hansson@arm.comtestsys.physmem.num_writes::total 3814 # Number of write requests responded to by this memory 8999729Sandreas.hansson@arm.comtestsys.physmem.bw_read::cpu.inst 354749025 # Total read bandwidth from this memory (bytes/s) 9009729Sandreas.hansson@arm.comtestsys.physmem.bw_read::cpu.data 122590014 # Total read bandwidth from this memory (bytes/s) 9019729Sandreas.hansson@arm.comtestsys.physmem.bw_read::tsunami.ethernet 285696400 # Total read bandwidth from this memory (bytes/s) 9029729Sandreas.hansson@arm.comtestsys.physmem.bw_read::total 763035438 # Total read bandwidth from this memory (bytes/s) 9039729Sandreas.hansson@arm.comtestsys.physmem.bw_inst_read::cpu.inst 354749025 # Instruction read bandwidth from this memory (bytes/s) 9049729Sandreas.hansson@arm.comtestsys.physmem.bw_inst_read::total 354749025 # Instruction read bandwidth from this memory (bytes/s) 9059729Sandreas.hansson@arm.comtestsys.physmem.bw_write::cpu.data 68011730 # Write bandwidth from this memory (bytes/s) 9069729Sandreas.hansson@arm.comtestsys.physmem.bw_write::total 68011730 # Write bandwidth from this memory (bytes/s) 9079729Sandreas.hansson@arm.comtestsys.physmem.bw_total::cpu.inst 354749025 # Total bandwidth to/from this memory (bytes/s) 9089729Sandreas.hansson@arm.comtestsys.physmem.bw_total::cpu.data 190601743 # Total bandwidth to/from this memory (bytes/s) 9099729Sandreas.hansson@arm.comtestsys.physmem.bw_total::tsunami.ethernet 285696400 # Total bandwidth to/from this memory (bytes/s) 9109729Sandreas.hansson@arm.comtestsys.physmem.bw_total::total 831047168 # Total bandwidth to/from this memory (bytes/s) 91110036SAli.Saidi@ARM.comtestsys.cpu.clk_domain.clock 500 # Clock period in ticks 9128721SN/Atestsys.cpu.dtb.fetch_hits 0 # ITB hits 9138721SN/Atestsys.cpu.dtb.fetch_misses 0 # ITB misses 9148721SN/Atestsys.cpu.dtb.fetch_acv 0 # ITB acv 9158721SN/Atestsys.cpu.dtb.fetch_accesses 0 # ITB accesses 9169729Sandreas.hansson@arm.comtestsys.cpu.dtb.read_hits 7065 # DTB read hits 9178721SN/Atestsys.cpu.dtb.read_misses 0 # DTB read misses 9188721SN/Atestsys.cpu.dtb.read_acv 0 # DTB read access violations 9198721SN/Atestsys.cpu.dtb.read_accesses 0 # DTB read accesses 9209729Sandreas.hansson@arm.comtestsys.cpu.dtb.write_hits 3935 # DTB write hits 9218721SN/Atestsys.cpu.dtb.write_misses 0 # DTB write misses 9228721SN/Atestsys.cpu.dtb.write_acv 0 # DTB write access violations 9238721SN/Atestsys.cpu.dtb.write_accesses 0 # DTB write accesses 9249729Sandreas.hansson@arm.comtestsys.cpu.dtb.data_hits 11000 # DTB hits 9258721SN/Atestsys.cpu.dtb.data_misses 0 # DTB misses 9268721SN/Atestsys.cpu.dtb.data_acv 0 # DTB access violations 9278721SN/Atestsys.cpu.dtb.data_accesses 0 # DTB accesses 9289729Sandreas.hansson@arm.comtestsys.cpu.itb.fetch_hits 5992 # ITB hits 9298721SN/Atestsys.cpu.itb.fetch_misses 0 # ITB misses 9308721SN/Atestsys.cpu.itb.fetch_acv 0 # ITB acv 9319729Sandreas.hansson@arm.comtestsys.cpu.itb.fetch_accesses 5992 # ITB accesses 9328721SN/Atestsys.cpu.itb.read_hits 0 # DTB read hits 9338721SN/Atestsys.cpu.itb.read_misses 0 # DTB read misses 9348721SN/Atestsys.cpu.itb.read_acv 0 # DTB read access violations 9358721SN/Atestsys.cpu.itb.read_accesses 0 # DTB read accesses 9368721SN/Atestsys.cpu.itb.write_hits 0 # DTB write hits 9378721SN/Atestsys.cpu.itb.write_misses 0 # DTB write misses 9388721SN/Atestsys.cpu.itb.write_acv 0 # DTB write access violations 9398721SN/Atestsys.cpu.itb.write_accesses 0 # DTB write accesses 9408721SN/Atestsys.cpu.itb.data_hits 0 # DTB hits 9418721SN/Atestsys.cpu.itb.data_misses 0 # DTB misses 9428721SN/Atestsys.cpu.itb.data_acv 0 # DTB access violations 9438721SN/Atestsys.cpu.itb.data_accesses 0 # DTB accesses 94410409Sandreas.hansson@arm.comtestsys.cpu.numCycles 821056 # number of cpu cycles simulated 9458721SN/Atestsys.cpu.numWorkItemsStarted 0 # number of work items this cpu started 9468721SN/Atestsys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 94711245Sandreas.sandberg@arm.comtestsys.cpu.kern.inst.arm 0 # number of arm instructions executed 94811245Sandreas.sandberg@arm.comtestsys.cpu.kern.inst.quiesce 40 # number of quiesce instructions executed 94911245Sandreas.sandberg@arm.comtestsys.cpu.kern.inst.hwrei 295 # number of hwrei instructions executed 95011245Sandreas.sandberg@arm.comtestsys.cpu.kern.ipl_count::0 123 41.84% 41.84% # number of times we switched to this ipl 95111245Sandreas.sandberg@arm.comtestsys.cpu.kern.ipl_count::21 40 13.61% 55.44% # number of times we switched to this ipl 95211245Sandreas.sandberg@arm.comtestsys.cpu.kern.ipl_count::22 1 0.34% 55.78% # number of times we switched to this ipl 95311245Sandreas.sandberg@arm.comtestsys.cpu.kern.ipl_count::31 130 44.22% 100.00% # number of times we switched to this ipl 95411245Sandreas.sandberg@arm.comtestsys.cpu.kern.ipl_count::total 294 # number of times we switched to this ipl 95511245Sandreas.sandberg@arm.comtestsys.cpu.kern.ipl_good::0 123 42.86% 42.86% # number of times we switched to this ipl from a different ipl 95611245Sandreas.sandberg@arm.comtestsys.cpu.kern.ipl_good::21 40 13.94% 56.79% # number of times we switched to this ipl from a different ipl 95711245Sandreas.sandberg@arm.comtestsys.cpu.kern.ipl_good::22 1 0.35% 57.14% # number of times we switched to this ipl from a different ipl 95811245Sandreas.sandberg@arm.comtestsys.cpu.kern.ipl_good::31 123 42.86% 100.00% # number of times we switched to this ipl from a different ipl 95911245Sandreas.sandberg@arm.comtestsys.cpu.kern.ipl_good::total 287 # number of times we switched to this ipl from a different ipl 96011245Sandreas.sandberg@arm.comtestsys.cpu.kern.ipl_ticks::0 397967000 96.95% 96.95% # number of cycles we spent at this ipl 96111245Sandreas.sandberg@arm.comtestsys.cpu.kern.ipl_ticks::21 3240000 0.79% 97.73% # number of cycles we spent at this ipl 96211245Sandreas.sandberg@arm.comtestsys.cpu.kern.ipl_ticks::22 43000 0.01% 97.74% # number of cycles we spent at this ipl 96311245Sandreas.sandberg@arm.comtestsys.cpu.kern.ipl_ticks::31 9258000 2.26% 100.00% # number of cycles we spent at this ipl 96411245Sandreas.sandberg@arm.comtestsys.cpu.kern.ipl_ticks::total 410508000 # number of cycles we spent at this ipl 96511245Sandreas.sandberg@arm.comtestsys.cpu.kern.ipl_used::0 1 # fraction of swpipl calls that actually changed the ipl 96611245Sandreas.sandberg@arm.comtestsys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 96711245Sandreas.sandberg@arm.comtestsys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 96811245Sandreas.sandberg@arm.comtestsys.cpu.kern.ipl_used::31 0.946154 # fraction of swpipl calls that actually changed the ipl 96911245Sandreas.sandberg@arm.comtestsys.cpu.kern.ipl_used::total 0.976190 # fraction of swpipl calls that actually changed the ipl 97011245Sandreas.sandberg@arm.comtestsys.cpu.kern.callpal::swpipl 212 83.46% 83.46% # number of callpals executed 97111245Sandreas.sandberg@arm.comtestsys.cpu.kern.callpal::rdps 1 0.39% 83.86% # number of callpals executed 97211245Sandreas.sandberg@arm.comtestsys.cpu.kern.callpal::rti 41 16.14% 100.00% # number of callpals executed 97311245Sandreas.sandberg@arm.comtestsys.cpu.kern.callpal::total 254 # number of callpals executed 97411245Sandreas.sandberg@arm.comtestsys.cpu.kern.mode_switch::kernel 0 # number of protection mode switches 97511245Sandreas.sandberg@arm.comtestsys.cpu.kern.mode_switch::user 0 # number of protection mode switches 97611245Sandreas.sandberg@arm.comtestsys.cpu.kern.mode_switch::idle 41 # number of protection mode switches 97711245Sandreas.sandberg@arm.comtestsys.cpu.kern.mode_good::kernel 0 97811245Sandreas.sandberg@arm.comtestsys.cpu.kern.mode_good::user 0 97911245Sandreas.sandberg@arm.comtestsys.cpu.kern.mode_good::idle 0 98011245Sandreas.sandberg@arm.comtestsys.cpu.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches 98111245Sandreas.sandberg@arm.comtestsys.cpu.kern.mode_switch_good::user nan # fraction of useful protection mode switches 98211245Sandreas.sandberg@arm.comtestsys.cpu.kern.mode_switch_good::idle 0 # fraction of useful protection mode switches 98311245Sandreas.sandberg@arm.comtestsys.cpu.kern.mode_switch_good::total 0 # fraction of useful protection mode switches 98411245Sandreas.sandberg@arm.comtestsys.cpu.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode 98511245Sandreas.sandberg@arm.comtestsys.cpu.kern.mode_ticks::user 0 # number of ticks spent at the given mode 98611245Sandreas.sandberg@arm.comtestsys.cpu.kern.mode_ticks::idle 0 # number of ticks spent at the given mode 98711245Sandreas.sandberg@arm.comtestsys.cpu.kern.swap_context 0 # number of times the context was actually changed 9889729Sandreas.hansson@arm.comtestsys.cpu.committedInsts 36126 # Number of instructions committed 9899729Sandreas.hansson@arm.comtestsys.cpu.committedOps 36126 # Number of ops (including micro ops) committed 9909729Sandreas.hansson@arm.comtestsys.cpu.num_int_alu_accesses 33492 # Number of integer alu accesses 9918721SN/Atestsys.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 9929729Sandreas.hansson@arm.comtestsys.cpu.num_func_calls 2384 # number of times a function call or return occured 9939729Sandreas.hansson@arm.comtestsys.cpu.num_conditional_control_insts 2346 # number of instructions that are conditional controls 9949729Sandreas.hansson@arm.comtestsys.cpu.num_int_insts 33492 # number of integer instructions 9958721SN/Atestsys.cpu.num_fp_insts 0 # number of float instructions 9969729Sandreas.hansson@arm.comtestsys.cpu.num_int_register_reads 43747 # number of times the integer registers were read 9979729Sandreas.hansson@arm.comtestsys.cpu.num_int_register_writes 26476 # number of times the integer registers were written 9988721SN/Atestsys.cpu.num_fp_register_reads 0 # number of times the floating registers were read 9998721SN/Atestsys.cpu.num_fp_register_writes 0 # number of times the floating registers were written 10009729Sandreas.hansson@arm.comtestsys.cpu.num_mem_refs 11041 # number of memory refs 10019729Sandreas.hansson@arm.comtestsys.cpu.num_load_insts 7105 # Number of load instructions 10029729Sandreas.hansson@arm.comtestsys.cpu.num_store_insts 3936 # Number of store instructions 100310409Sandreas.hansson@arm.comtestsys.cpu.num_idle_cycles 784687.711054 # Number of idle cycles 100410409Sandreas.hansson@arm.comtestsys.cpu.num_busy_cycles 36368.288946 # Number of busy cycles 100510409Sandreas.hansson@arm.comtestsys.cpu.not_idle_fraction 0.044295 # Percentage of non-idle cycles 100610409Sandreas.hansson@arm.comtestsys.cpu.idle_fraction 0.955705 # Percentage of idle cycles 100710063Snilay@cs.wisc.edutestsys.cpu.Branches 5238 # Number of branches fetched 100810220Sandreas.hansson@arm.comtestsys.cpu.op_class::No_OpClass 1261 3.49% 3.49% # Class of executed instruction 100910220Sandreas.hansson@arm.comtestsys.cpu.op_class::IntAlu 21664 59.97% 63.46% # Class of executed instruction 101010220Sandreas.hansson@arm.comtestsys.cpu.op_class::IntMult 44 0.12% 63.58% # Class of executed instruction 101110220Sandreas.hansson@arm.comtestsys.cpu.op_class::IntDiv 0 0.00% 63.58% # Class of executed instruction 101210220Sandreas.hansson@arm.comtestsys.cpu.op_class::FloatAdd 0 0.00% 63.58% # Class of executed instruction 101310220Sandreas.hansson@arm.comtestsys.cpu.op_class::FloatCmp 0 0.00% 63.58% # Class of executed instruction 101410220Sandreas.hansson@arm.comtestsys.cpu.op_class::FloatCvt 0 0.00% 63.58% # Class of executed instruction 101510220Sandreas.hansson@arm.comtestsys.cpu.op_class::FloatMult 0 0.00% 63.58% # Class of executed instruction 101610220Sandreas.hansson@arm.comtestsys.cpu.op_class::FloatDiv 0 0.00% 63.58% # Class of executed instruction 101710220Sandreas.hansson@arm.comtestsys.cpu.op_class::FloatSqrt 0 0.00% 63.58% # Class of executed instruction 101810220Sandreas.hansson@arm.comtestsys.cpu.op_class::SimdAdd 0 0.00% 63.58% # Class of executed instruction 101910220Sandreas.hansson@arm.comtestsys.cpu.op_class::SimdAddAcc 0 0.00% 63.58% # Class of executed instruction 102010220Sandreas.hansson@arm.comtestsys.cpu.op_class::SimdAlu 0 0.00% 63.58% # Class of executed instruction 102110220Sandreas.hansson@arm.comtestsys.cpu.op_class::SimdCmp 0 0.00% 63.58% # Class of executed instruction 102210220Sandreas.hansson@arm.comtestsys.cpu.op_class::SimdCvt 0 0.00% 63.58% # Class of executed instruction 102310220Sandreas.hansson@arm.comtestsys.cpu.op_class::SimdMisc 0 0.00% 63.58% # Class of executed instruction 102410220Sandreas.hansson@arm.comtestsys.cpu.op_class::SimdMult 0 0.00% 63.58% # Class of executed instruction 102510220Sandreas.hansson@arm.comtestsys.cpu.op_class::SimdMultAcc 0 0.00% 63.58% # Class of executed instruction 102610220Sandreas.hansson@arm.comtestsys.cpu.op_class::SimdShift 0 0.00% 63.58% # Class of executed instruction 102710220Sandreas.hansson@arm.comtestsys.cpu.op_class::SimdShiftAcc 0 0.00% 63.58% # Class of executed instruction 102810220Sandreas.hansson@arm.comtestsys.cpu.op_class::SimdSqrt 0 0.00% 63.58% # Class of executed instruction 102910220Sandreas.hansson@arm.comtestsys.cpu.op_class::SimdFloatAdd 0 0.00% 63.58% # Class of executed instruction 103010220Sandreas.hansson@arm.comtestsys.cpu.op_class::SimdFloatAlu 0 0.00% 63.58% # Class of executed instruction 103110220Sandreas.hansson@arm.comtestsys.cpu.op_class::SimdFloatCmp 0 0.00% 63.58% # Class of executed instruction 103210220Sandreas.hansson@arm.comtestsys.cpu.op_class::SimdFloatCvt 0 0.00% 63.58% # Class of executed instruction 103310220Sandreas.hansson@arm.comtestsys.cpu.op_class::SimdFloatDiv 0 0.00% 63.58% # Class of executed instruction 103410220Sandreas.hansson@arm.comtestsys.cpu.op_class::SimdFloatMisc 0 0.00% 63.58% # Class of executed instruction 103510220Sandreas.hansson@arm.comtestsys.cpu.op_class::SimdFloatMult 0 0.00% 63.58% # Class of executed instruction 103610220Sandreas.hansson@arm.comtestsys.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.58% # Class of executed instruction 103710220Sandreas.hansson@arm.comtestsys.cpu.op_class::SimdFloatSqrt 0 0.00% 63.58% # Class of executed instruction 103810220Sandreas.hansson@arm.comtestsys.cpu.op_class::MemRead 7674 21.24% 84.82% # Class of executed instruction 103910220Sandreas.hansson@arm.comtestsys.cpu.op_class::MemWrite 3938 10.90% 95.72% # Class of executed instruction 104010220Sandreas.hansson@arm.comtestsys.cpu.op_class::IprAccess 1545 4.28% 100.00% # Class of executed instruction 104110220Sandreas.hansson@arm.comtestsys.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 104210220Sandreas.hansson@arm.comtestsys.cpu.op_class::total 36126 # Class of executed instruction 104310778Snilay@cs.wisc.edutestsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 104410778Snilay@cs.wisc.edutestsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 104510778Snilay@cs.wisc.edutestsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 104610778Snilay@cs.wisc.edutestsys.disk0.dma_write_full_pages 0 # Number of full page size DMA writes. 104710778Snilay@cs.wisc.edutestsys.disk0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 104810778Snilay@cs.wisc.edutestsys.disk0.dma_write_txs 0 # Number of DMA write transactions. 104910778Snilay@cs.wisc.edutestsys.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 105010778Snilay@cs.wisc.edutestsys.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 105110778Snilay@cs.wisc.edutestsys.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 105210778Snilay@cs.wisc.edutestsys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes. 105310778Snilay@cs.wisc.edutestsys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 105410778Snilay@cs.wisc.edutestsys.disk2.dma_write_txs 0 # Number of DMA write transactions. 105510778Snilay@cs.wisc.edutestsys.iobus.trans_dist::ReadReq 5049 # Transaction distribution 105610778Snilay@cs.wisc.edutestsys.iobus.trans_dist::ReadResp 5049 # Transaction distribution 105710778Snilay@cs.wisc.edutestsys.iobus.trans_dist::WriteReq 81 # Transaction distribution 105810778Snilay@cs.wisc.edutestsys.iobus.trans_dist::WriteResp 81 # Transaction distribution 105910778Snilay@cs.wisc.edutestsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.cchip.pio 402 # Packet count per connected master and slave (bytes) 106010778Snilay@cs.wisc.edutestsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.ethernet.pio 160 # Packet count per connected master and slave (bytes) 106110778Snilay@cs.wisc.edutestsys.iobus.pkt_count_testsys.bridge.master::total 562 # Packet count per connected master and slave (bytes) 106210778Snilay@cs.wisc.edutestsys.iobus.pkt_count_testsys.tsunami.ethernet.dma::testsys.iobridge.slave 9698 # Packet count per connected master and slave (bytes) 106310778Snilay@cs.wisc.edutestsys.iobus.pkt_count_testsys.tsunami.ethernet.dma::total 9698 # Packet count per connected master and slave (bytes) 106410778Snilay@cs.wisc.edutestsys.iobus.pkt_count::total 10260 # Packet count per connected master and slave (bytes) 106510778Snilay@cs.wisc.edutestsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.cchip.pio 1608 # Cumulative packet size per connected master and slave (bytes) 106610778Snilay@cs.wisc.edutestsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.ethernet.pio 320 # Cumulative packet size per connected master and slave (bytes) 106710778Snilay@cs.wisc.edutestsys.iobus.pkt_size_testsys.bridge.master::total 1928 # Cumulative packet size per connected master and slave (bytes) 106810778Snilay@cs.wisc.edutestsys.iobus.pkt_size_testsys.tsunami.ethernet.dma::testsys.iobridge.slave 116376 # Cumulative packet size per connected master and slave (bytes) 106910778Snilay@cs.wisc.edutestsys.iobus.pkt_size_testsys.tsunami.ethernet.dma::total 116376 # Cumulative packet size per connected master and slave (bytes) 107010778Snilay@cs.wisc.edutestsys.iobus.pkt_size::total 118304 # Cumulative packet size per connected master and slave (bytes) 107110778Snilay@cs.wisc.edutestsys.membus.trans_dist::ReadReq 47876 # Transaction distribution 107210778Snilay@cs.wisc.edutestsys.membus.trans_dist::ReadResp 48080 # Transaction distribution 107310778Snilay@cs.wisc.edutestsys.membus.trans_dist::WriteReq 3691 # Transaction distribution 107410778Snilay@cs.wisc.edutestsys.membus.trans_dist::WriteResp 3691 # Transaction distribution 107510778Snilay@cs.wisc.edutestsys.membus.trans_dist::LoadLockedReq 204 # Transaction distribution 107610778Snilay@cs.wisc.edutestsys.membus.trans_dist::StoreCondReq 204 # Transaction distribution 107710778Snilay@cs.wisc.edutestsys.membus.trans_dist::StoreCondResp 204 # Transaction distribution 107810778Snilay@cs.wisc.edutestsys.membus.pkt_count_testsys.cpu.icache_port::testsys.physmem.port 72252 # Packet count per connected master and slave (bytes) 107910778Snilay@cs.wisc.edutestsys.membus.pkt_count_testsys.cpu.icache_port::total 72252 # Packet count per connected master and slave (bytes) 108010778Snilay@cs.wisc.edutestsys.membus.pkt_count_testsys.cpu.dcache_port::testsys.bridge.slave 562 # Packet count per connected master and slave (bytes) 108110778Snilay@cs.wisc.edutestsys.membus.pkt_count_testsys.cpu.dcache_port::testsys.physmem.port 21438 # Packet count per connected master and slave (bytes) 108210778Snilay@cs.wisc.edutestsys.membus.pkt_count_testsys.cpu.dcache_port::total 22000 # Packet count per connected master and slave (bytes) 108310778Snilay@cs.wisc.edutestsys.membus.pkt_count_testsys.iobridge.master::testsys.physmem.port 9698 # Packet count per connected master and slave (bytes) 108410778Snilay@cs.wisc.edutestsys.membus.pkt_count_testsys.iobridge.master::total 9698 # Packet count per connected master and slave (bytes) 108510778Snilay@cs.wisc.edutestsys.membus.pkt_count::total 103950 # Packet count per connected master and slave (bytes) 108610778Snilay@cs.wisc.edutestsys.membus.pkt_size_testsys.cpu.icache_port::testsys.physmem.port 144504 # Cumulative packet size per connected master and slave (bytes) 108710778Snilay@cs.wisc.edutestsys.membus.pkt_size_testsys.cpu.icache_port::total 144504 # Cumulative packet size per connected master and slave (bytes) 108810778Snilay@cs.wisc.edutestsys.membus.pkt_size_testsys.cpu.dcache_port::testsys.bridge.slave 1928 # Cumulative packet size per connected master and slave (bytes) 108910778Snilay@cs.wisc.edutestsys.membus.pkt_size_testsys.cpu.dcache_port::testsys.physmem.port 77640 # Cumulative packet size per connected master and slave (bytes) 109010778Snilay@cs.wisc.edutestsys.membus.pkt_size_testsys.cpu.dcache_port::total 79568 # Cumulative packet size per connected master and slave (bytes) 109110778Snilay@cs.wisc.edutestsys.membus.pkt_size_testsys.iobridge.master::testsys.physmem.port 116376 # Cumulative packet size per connected master and slave (bytes) 109210778Snilay@cs.wisc.edutestsys.membus.pkt_size_testsys.iobridge.master::total 116376 # Cumulative packet size per connected master and slave (bytes) 109310778Snilay@cs.wisc.edutestsys.membus.pkt_size::total 340448 # Cumulative packet size per connected master and slave (bytes) 109410778Snilay@cs.wisc.edutestsys.membus.snoops 0 # Total snoops (count) 109510827Sandreas.hansson@arm.comtestsys.membus.snoop_fanout::samples 51975 # Request fanout histogram 109610827Sandreas.hansson@arm.comtestsys.membus.snoop_fanout::mean 0.788360 # Request fanout histogram 109710827Sandreas.hansson@arm.comtestsys.membus.snoop_fanout::stdev 0.408475 # Request fanout histogram 109810778Snilay@cs.wisc.edutestsys.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 109910827Sandreas.hansson@arm.comtestsys.membus.snoop_fanout::0 11000 21.16% 21.16% # Request fanout histogram 110010827Sandreas.hansson@arm.comtestsys.membus.snoop_fanout::1 40975 78.84% 100.00% # Request fanout histogram 110110778Snilay@cs.wisc.edutestsys.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 110210778Snilay@cs.wisc.edutestsys.membus.snoop_fanout::min_value 0 # Request fanout histogram 110310778Snilay@cs.wisc.edutestsys.membus.snoop_fanout::max_value 1 # Request fanout histogram 110410827Sandreas.hansson@arm.comtestsys.membus.snoop_fanout::total 51975 # Request fanout histogram 110510036SAli.Saidi@ARM.comtestsys.tsunami.ethernet.clk_domain.clock 2000 # Clock period in ticks 11069729Sandreas.hansson@arm.comtestsys.tsunami.ethernet.descDMAReads 4849 # Number of descriptors the device read w/ DMA 11078721SN/Atestsys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 11089729Sandreas.hansson@arm.comtestsys.tsunami.ethernet.descDmaReadBytes 116376 # number of descriptor bytes read w/ DMA 11098721SN/Atestsys.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 11108721SN/Atestsys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 11119449SAli.Saidi@ARM.comtestsys.tsunami.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 11128721SN/Atestsys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 11138721SN/Atestsys.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 11149449SAli.Saidi@ARM.comtestsys.tsunami.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 11158721SN/Atestsys.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 11168721SN/Atestsys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 11179449SAli.Saidi@ARM.comtestsys.tsunami.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 11188721SN/Atestsys.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 11198721SN/Atestsys.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 11209449SAli.Saidi@ARM.comtestsys.tsunami.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 11218721SN/Atestsys.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 11228721SN/Atestsys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 11239449SAli.Saidi@ARM.comtestsys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 11248721SN/Atestsys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 11259729Sandreas.hansson@arm.comtestsys.tsunami.ethernet.postedTxIdle 40 # number of TxIdle interrupts posted to CPU 11269449SAli.Saidi@ARM.comtestsys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post 11279729Sandreas.hansson@arm.comtestsys.tsunami.ethernet.totalTxIdle 4849 # total number of TxIdle written to ISR 11288721SN/Atestsys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 11299449SAli.Saidi@ARM.comtestsys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 11308721SN/Atestsys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 11318721SN/Atestsys.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 11329449SAli.Saidi@ARM.comtestsys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 11338721SN/Atestsys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 11349449SAli.Saidi@ARM.comtestsys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post 11359729Sandreas.hansson@arm.comtestsys.tsunami.ethernet.postedInterrupts 4849 # number of posts to CPU 11368721SN/Atestsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped 11373691SN/A 11383691SN/A---------- End Simulation Statistics ---------- 1139