stats.txt revision 9314:63e7cfff4188
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.191113 # Number of seconds simulated 4sim_ticks 5191112864000 # Number of ticks simulated 5final_tick 5191112864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1106680 # Simulator instruction rate (inst/s) 8host_op_rate 2133324 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 44796411922 # Simulator tick rate (ticks/s) 10host_mem_usage 384016 # Number of bytes of host memory used 11host_seconds 115.88 # Real time elapsed on the host 12sim_insts 128244614 # Number of instructions simulated 13sim_ops 247214600 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::pc.south_bridge.ide 2852352 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu.inst 825984 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 9026368 # Number of bytes read from this memory 18system.physmem.bytes_read::total 12705024 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 825984 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 825984 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 8129280 # Number of bytes written to this memory 22system.physmem.bytes_written::total 8129280 # Number of bytes written to this memory 23system.physmem.num_reads::pc.south_bridge.ide 44568 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.inst 12906 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.data 141037 # Number of read requests responded to by this memory 27system.physmem.num_reads::total 198516 # Number of read requests responded to by this memory 28system.physmem.num_writes::writebacks 127020 # Number of write requests responded to by this memory 29system.physmem.num_writes::total 127020 # Number of write requests responded to by this memory 30system.physmem.bw_read::pc.south_bridge.ide 549468 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.inst 159115 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::cpu.data 1738812 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::total 2447457 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::cpu.inst 159115 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_inst_read::total 159115 # Instruction read bandwidth from this memory (bytes/s) 37system.physmem.bw_write::writebacks 1565999 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_write::total 1565999 # Write bandwidth from this memory (bytes/s) 39system.physmem.bw_total::writebacks 1565999 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::pc.south_bridge.ide 549468 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::cpu.inst 159115 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::cpu.data 1738812 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.bw_total::total 4013456 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.readReqs 198516 # Total number of read requests seen 46system.physmem.writeReqs 127020 # Total number of write requests seen 47system.physmem.cpureqs 331314 # Reqs generatd by CPU via cache - shady 48system.physmem.bytesRead 12705024 # Total number of bytes read from memory 49system.physmem.bytesWritten 8129280 # Total number of bytes written to memory 50system.physmem.bytesConsumedRd 12705024 # bytesRead derated as per pkt->getSize() 51system.physmem.bytesConsumedWr 8129280 # bytesWritten derated as per pkt->getSize() 52system.physmem.servicedByWrQ 88 # Number of read reqs serviced by write Q 53system.physmem.neitherReadNorWrite 1599 # Reqs where no action is needed 54system.physmem.perBankRdReqs::0 12028 # Track reads on a per bank basis 55system.physmem.perBankRdReqs::1 12411 # Track reads on a per bank basis 56system.physmem.perBankRdReqs::2 11776 # Track reads on a per bank basis 57system.physmem.perBankRdReqs::3 12503 # Track reads on a per bank basis 58system.physmem.perBankRdReqs::4 12483 # Track reads on a per bank basis 59system.physmem.perBankRdReqs::5 12755 # Track reads on a per bank basis 60system.physmem.perBankRdReqs::6 12240 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::7 12788 # Track reads on a per bank basis 62system.physmem.perBankRdReqs::8 12663 # Track reads on a per bank basis 63system.physmem.perBankRdReqs::9 12687 # Track reads on a per bank basis 64system.physmem.perBankRdReqs::10 12141 # Track reads on a per bank basis 65system.physmem.perBankRdReqs::11 12548 # Track reads on a per bank basis 66system.physmem.perBankRdReqs::12 12236 # Track reads on a per bank basis 67system.physmem.perBankRdReqs::13 12474 # Track reads on a per bank basis 68system.physmem.perBankRdReqs::14 11907 # Track reads on a per bank basis 69system.physmem.perBankRdReqs::15 12788 # Track reads on a per bank basis 70system.physmem.perBankWrReqs::0 7431 # Track writes on a per bank basis 71system.physmem.perBankWrReqs::1 7966 # Track writes on a per bank basis 72system.physmem.perBankWrReqs::2 7373 # Track writes on a per bank basis 73system.physmem.perBankWrReqs::3 8083 # Track writes on a per bank basis 74system.physmem.perBankWrReqs::4 7981 # Track writes on a per bank basis 75system.physmem.perBankWrReqs::5 8219 # Track writes on a per bank basis 76system.physmem.perBankWrReqs::6 7719 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::7 8332 # Track writes on a per bank basis 78system.physmem.perBankWrReqs::8 8225 # Track writes on a per bank basis 79system.physmem.perBankWrReqs::9 8161 # Track writes on a per bank basis 80system.physmem.perBankWrReqs::10 7712 # Track writes on a per bank basis 81system.physmem.perBankWrReqs::11 8125 # Track writes on a per bank basis 82system.physmem.perBankWrReqs::12 7893 # Track writes on a per bank basis 83system.physmem.perBankWrReqs::13 7991 # Track writes on a per bank basis 84system.physmem.perBankWrReqs::14 7528 # Track writes on a per bank basis 85system.physmem.perBankWrReqs::15 8281 # Track writes on a per bank basis 86system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 87system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 88system.physmem.totGap 5191112800500 # Total gap between requests 89system.physmem.readPktSize::0 0 # Categorize read packet sizes 90system.physmem.readPktSize::1 0 # Categorize read packet sizes 91system.physmem.readPktSize::2 0 # Categorize read packet sizes 92system.physmem.readPktSize::3 0 # Categorize read packet sizes 93system.physmem.readPktSize::4 0 # Categorize read packet sizes 94system.physmem.readPktSize::5 0 # Categorize read packet sizes 95system.physmem.readPktSize::6 198516 # Categorize read packet sizes 96system.physmem.readPktSize::7 0 # Categorize read packet sizes 97system.physmem.readPktSize::8 0 # Categorize read packet sizes 98system.physmem.writePktSize::0 0 # categorize write packet sizes 99system.physmem.writePktSize::1 0 # categorize write packet sizes 100system.physmem.writePktSize::2 0 # categorize write packet sizes 101system.physmem.writePktSize::3 0 # categorize write packet sizes 102system.physmem.writePktSize::4 0 # categorize write packet sizes 103system.physmem.writePktSize::5 0 # categorize write packet sizes 104system.physmem.writePktSize::6 127020 # categorize write packet sizes 105system.physmem.writePktSize::7 0 # categorize write packet sizes 106system.physmem.writePktSize::8 0 # categorize write packet sizes 107system.physmem.neitherpktsize::0 0 # categorize neither packet sizes 108system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 109system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 110system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 111system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 112system.physmem.neitherpktsize::5 0 # categorize neither packet sizes 113system.physmem.neitherpktsize::6 1599 # categorize neither packet sizes 114system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 115system.physmem.neitherpktsize::8 0 # categorize neither packet sizes 116system.physmem.rdQLenPdf::0 158090 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::1 11440 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::2 7599 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::3 2597 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::4 3245 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::5 2511 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::6 1497 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::7 1744 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::8 1556 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::9 1514 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::10 1392 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::11 1291 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::12 1281 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::13 1081 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::14 569 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::15 355 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::16 264 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::17 183 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::18 118 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::19 88 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see 149system.physmem.wrQLenPdf::0 4625 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::1 5391 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::2 5480 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::3 5504 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::4 5511 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::5 5517 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::6 5522 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::7 5522 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::8 5523 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::9 5523 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::10 5523 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::11 5523 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::12 5523 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::13 5523 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::14 5522 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::15 5522 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::16 5522 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::17 5522 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::18 5522 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::19 5522 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::20 5522 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::21 5522 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::22 5522 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::23 898 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::24 132 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::25 43 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::26 19 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::27 12 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::28 6 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 182system.physmem.totQLat 2876233269 # Total cycles spent in queuing delays 183system.physmem.totMemAccLat 6438459269 # Sum of mem lat for all requests 184system.physmem.totBusLat 793712000 # Total cycles spent in databus access 185system.physmem.totBankLat 2768514000 # Total cycles spent in bank access 186system.physmem.avgQLat 14495.10 # Average queueing delay per request 187system.physmem.avgBankLat 13952.23 # Average bank access latency per request 188system.physmem.avgBusLat 4000.00 # Average bus latency per request 189system.physmem.avgMemAccLat 32447.33 # Average memory access latency 190system.physmem.avgRdBW 2.45 # Average achieved read bandwidth in MB/s 191system.physmem.avgWrBW 1.57 # Average achieved write bandwidth in MB/s 192system.physmem.avgConsumedRdBW 2.45 # Average consumed read bandwidth in MB/s 193system.physmem.avgConsumedWrBW 1.57 # Average consumed write bandwidth in MB/s 194system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 195system.physmem.busUtil 0.03 # Data bus utilization in percentage 196system.physmem.avgRdQLen 0.00 # Average read queue length over time 197system.physmem.avgWrQLen 9.06 # Average write queue length over time 198system.physmem.readRowHits 179831 # Number of row buffer hits during reads 199system.physmem.writeRowHits 78085 # Number of row buffer hits during writes 200system.physmem.readRowHitRate 90.63 # Row buffer hit rate for reads 201system.physmem.writeRowHitRate 61.47 # Row buffer hit rate for writes 202system.physmem.avgGap 15946355.55 # Average gap between requests 203system.iocache.replacements 47506 # number of replacements 204system.iocache.tagsinuse 0.117830 # Cycle average of tags in use 205system.iocache.total_refs 0 # Total number of references to valid blocks. 206system.iocache.sampled_refs 47522 # Sample count of references to valid blocks. 207system.iocache.avg_refs 0 # Average number of references to valid blocks. 208system.iocache.warmup_cycle 5044498925000 # Cycle when the warmup percentage was hit. 209system.iocache.occ_blocks::pc.south_bridge.ide 0.117830 # Average occupied blocks per requestor 210system.iocache.occ_percent::pc.south_bridge.ide 0.007364 # Average percentage of cache occupancy 211system.iocache.occ_percent::total 0.007364 # Average percentage of cache occupancy 212system.iocache.ReadReq_misses::pc.south_bridge.ide 841 # number of ReadReq misses 213system.iocache.ReadReq_misses::total 841 # number of ReadReq misses 214system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses 215system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses 216system.iocache.demand_misses::pc.south_bridge.ide 47561 # number of demand (read+write) misses 217system.iocache.demand_misses::total 47561 # number of demand (read+write) misses 218system.iocache.overall_misses::pc.south_bridge.ide 47561 # number of overall misses 219system.iocache.overall_misses::total 47561 # number of overall misses 220system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 133668932 # number of ReadReq miss cycles 221system.iocache.ReadReq_miss_latency::total 133668932 # number of ReadReq miss cycles 222system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 9598301160 # number of WriteReq miss cycles 223system.iocache.WriteReq_miss_latency::total 9598301160 # number of WriteReq miss cycles 224system.iocache.demand_miss_latency::pc.south_bridge.ide 9731970092 # number of demand (read+write) miss cycles 225system.iocache.demand_miss_latency::total 9731970092 # number of demand (read+write) miss cycles 226system.iocache.overall_miss_latency::pc.south_bridge.ide 9731970092 # number of overall miss cycles 227system.iocache.overall_miss_latency::total 9731970092 # number of overall miss cycles 228system.iocache.ReadReq_accesses::pc.south_bridge.ide 841 # number of ReadReq accesses(hits+misses) 229system.iocache.ReadReq_accesses::total 841 # number of ReadReq accesses(hits+misses) 230system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) 231system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) 232system.iocache.demand_accesses::pc.south_bridge.ide 47561 # number of demand (read+write) accesses 233system.iocache.demand_accesses::total 47561 # number of demand (read+write) accesses 234system.iocache.overall_accesses::pc.south_bridge.ide 47561 # number of overall (read+write) accesses 235system.iocache.overall_accesses::total 47561 # number of overall (read+write) accesses 236system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 237system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 238system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses 239system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 240system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 241system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 242system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 243system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 244system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 158940.466112 # average ReadReq miss latency 245system.iocache.ReadReq_avg_miss_latency::total 158940.466112 # average ReadReq miss latency 246system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 205443.089897 # average WriteReq miss latency 247system.iocache.WriteReq_avg_miss_latency::total 205443.089897 # average WriteReq miss latency 248system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 204620.804693 # average overall miss latency 249system.iocache.demand_avg_miss_latency::total 204620.804693 # average overall miss latency 250system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 204620.804693 # average overall miss latency 251system.iocache.overall_avg_miss_latency::total 204620.804693 # average overall miss latency 252system.iocache.blocked_cycles::no_mshrs 78425 # number of cycles access was blocked 253system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 254system.iocache.blocked::no_mshrs 10368 # number of cycles access was blocked 255system.iocache.blocked::no_targets 0 # number of cycles access was blocked 256system.iocache.avg_blocked_cycles::no_mshrs 7.564140 # average number of cycles each access was blocked 257system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 258system.iocache.fast_writes 0 # number of fast writes performed 259system.iocache.cache_copies 0 # number of cache copies performed 260system.iocache.writebacks::writebacks 46667 # number of writebacks 261system.iocache.writebacks::total 46667 # number of writebacks 262system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 841 # number of ReadReq MSHR misses 263system.iocache.ReadReq_mshr_misses::total 841 # number of ReadReq MSHR misses 264system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses 265system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses 266system.iocache.demand_mshr_misses::pc.south_bridge.ide 47561 # number of demand (read+write) MSHR misses 267system.iocache.demand_mshr_misses::total 47561 # number of demand (read+write) MSHR misses 268system.iocache.overall_mshr_misses::pc.south_bridge.ide 47561 # number of overall MSHR misses 269system.iocache.overall_mshr_misses::total 47561 # number of overall MSHR misses 270system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 89906992 # number of ReadReq MSHR miss cycles 271system.iocache.ReadReq_mshr_miss_latency::total 89906992 # number of ReadReq MSHR miss cycles 272system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7166703132 # number of WriteReq MSHR miss cycles 273system.iocache.WriteReq_mshr_miss_latency::total 7166703132 # number of WriteReq MSHR miss cycles 274system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7256610124 # number of demand (read+write) MSHR miss cycles 275system.iocache.demand_mshr_miss_latency::total 7256610124 # number of demand (read+write) MSHR miss cycles 276system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7256610124 # number of overall MSHR miss cycles 277system.iocache.overall_mshr_miss_latency::total 7256610124 # number of overall MSHR miss cycles 278system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 279system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 280system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses 281system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 282system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 283system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 284system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 285system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 286system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 106904.865636 # average ReadReq mshr miss latency 287system.iocache.ReadReq_avg_mshr_miss_latency::total 106904.865636 # average ReadReq mshr miss latency 288system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 153396.899229 # average WriteReq mshr miss latency 289system.iocache.WriteReq_avg_mshr_miss_latency::total 153396.899229 # average WriteReq mshr miss latency 290system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 152574.801287 # average overall mshr miss latency 291system.iocache.demand_avg_mshr_miss_latency::total 152574.801287 # average overall mshr miss latency 292system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 152574.801287 # average overall mshr miss latency 293system.iocache.overall_avg_mshr_miss_latency::total 152574.801287 # average overall mshr miss latency 294system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 295system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 296system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 297system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). 298system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 299system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 300system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 301system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 302system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 303system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 304system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 305system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 306system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 307system.cpu.numCycles 10382225728 # number of cpu cycles simulated 308system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 309system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 310system.cpu.committedInsts 128244614 # Number of instructions committed 311system.cpu.committedOps 247214600 # Number of ops (including micro ops) committed 312system.cpu.num_int_alu_accesses 231949861 # Number of integer alu accesses 313system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 314system.cpu.num_func_calls 0 # number of times a function call or return occured 315system.cpu.num_conditional_control_insts 23149723 # number of instructions that are conditional controls 316system.cpu.num_int_insts 231949861 # number of integer instructions 317system.cpu.num_fp_insts 0 # number of float instructions 318system.cpu.num_int_register_reads 566905512 # number of times the integer registers were read 319system.cpu.num_int_register_writes 293156466 # number of times the integer registers were written 320system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 321system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 322system.cpu.num_mem_refs 22227093 # number of memory refs 323system.cpu.num_load_insts 13866667 # Number of load instructions 324system.cpu.num_store_insts 8360426 # Number of store instructions 325system.cpu.num_idle_cycles 9781583060.998116 # Number of idle cycles 326system.cpu.num_busy_cycles 600642667.001884 # Number of busy cycles 327system.cpu.not_idle_fraction 0.057853 # Percentage of non-idle cycles 328system.cpu.idle_fraction 0.942147 # Percentage of idle cycles 329system.cpu.kern.inst.arm 0 # number of arm instructions executed 330system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 331system.cpu.icache.replacements 790930 # number of replacements 332system.cpu.icache.tagsinuse 510.376048 # Cycle average of tags in use 333system.cpu.icache.total_refs 144455339 # Total number of references to valid blocks. 334system.cpu.icache.sampled_refs 791442 # Sample count of references to valid blocks. 335system.cpu.icache.avg_refs 182.521700 # Average number of references to valid blocks. 336system.cpu.icache.warmup_cycle 159759301000 # Cycle when the warmup percentage was hit. 337system.cpu.icache.occ_blocks::cpu.inst 510.376048 # Average occupied blocks per requestor 338system.cpu.icache.occ_percent::cpu.inst 0.996828 # Average percentage of cache occupancy 339system.cpu.icache.occ_percent::total 0.996828 # Average percentage of cache occupancy 340system.cpu.icache.ReadReq_hits::cpu.inst 144455339 # number of ReadReq hits 341system.cpu.icache.ReadReq_hits::total 144455339 # number of ReadReq hits 342system.cpu.icache.demand_hits::cpu.inst 144455339 # number of demand (read+write) hits 343system.cpu.icache.demand_hits::total 144455339 # number of demand (read+write) hits 344system.cpu.icache.overall_hits::cpu.inst 144455339 # number of overall hits 345system.cpu.icache.overall_hits::total 144455339 # number of overall hits 346system.cpu.icache.ReadReq_misses::cpu.inst 791449 # number of ReadReq misses 347system.cpu.icache.ReadReq_misses::total 791449 # number of ReadReq misses 348system.cpu.icache.demand_misses::cpu.inst 791449 # number of demand (read+write) misses 349system.cpu.icache.demand_misses::total 791449 # number of demand (read+write) misses 350system.cpu.icache.overall_misses::cpu.inst 791449 # number of overall misses 351system.cpu.icache.overall_misses::total 791449 # number of overall misses 352system.cpu.icache.ReadReq_miss_latency::cpu.inst 10871281000 # number of ReadReq miss cycles 353system.cpu.icache.ReadReq_miss_latency::total 10871281000 # number of ReadReq miss cycles 354system.cpu.icache.demand_miss_latency::cpu.inst 10871281000 # number of demand (read+write) miss cycles 355system.cpu.icache.demand_miss_latency::total 10871281000 # number of demand (read+write) miss cycles 356system.cpu.icache.overall_miss_latency::cpu.inst 10871281000 # number of overall miss cycles 357system.cpu.icache.overall_miss_latency::total 10871281000 # number of overall miss cycles 358system.cpu.icache.ReadReq_accesses::cpu.inst 145246788 # number of ReadReq accesses(hits+misses) 359system.cpu.icache.ReadReq_accesses::total 145246788 # number of ReadReq accesses(hits+misses) 360system.cpu.icache.demand_accesses::cpu.inst 145246788 # number of demand (read+write) accesses 361system.cpu.icache.demand_accesses::total 145246788 # number of demand (read+write) accesses 362system.cpu.icache.overall_accesses::cpu.inst 145246788 # number of overall (read+write) accesses 363system.cpu.icache.overall_accesses::total 145246788 # number of overall (read+write) accesses 364system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005449 # miss rate for ReadReq accesses 365system.cpu.icache.ReadReq_miss_rate::total 0.005449 # miss rate for ReadReq accesses 366system.cpu.icache.demand_miss_rate::cpu.inst 0.005449 # miss rate for demand accesses 367system.cpu.icache.demand_miss_rate::total 0.005449 # miss rate for demand accesses 368system.cpu.icache.overall_miss_rate::cpu.inst 0.005449 # miss rate for overall accesses 369system.cpu.icache.overall_miss_rate::total 0.005449 # miss rate for overall accesses 370system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13735.921076 # average ReadReq miss latency 371system.cpu.icache.ReadReq_avg_miss_latency::total 13735.921076 # average ReadReq miss latency 372system.cpu.icache.demand_avg_miss_latency::cpu.inst 13735.921076 # average overall miss latency 373system.cpu.icache.demand_avg_miss_latency::total 13735.921076 # average overall miss latency 374system.cpu.icache.overall_avg_miss_latency::cpu.inst 13735.921076 # average overall miss latency 375system.cpu.icache.overall_avg_miss_latency::total 13735.921076 # average overall miss latency 376system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 377system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 378system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 379system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 380system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 381system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 382system.cpu.icache.fast_writes 0 # number of fast writes performed 383system.cpu.icache.cache_copies 0 # number of cache copies performed 384system.cpu.icache.ReadReq_mshr_misses::cpu.inst 791449 # number of ReadReq MSHR misses 385system.cpu.icache.ReadReq_mshr_misses::total 791449 # number of ReadReq MSHR misses 386system.cpu.icache.demand_mshr_misses::cpu.inst 791449 # number of demand (read+write) MSHR misses 387system.cpu.icache.demand_mshr_misses::total 791449 # number of demand (read+write) MSHR misses 388system.cpu.icache.overall_mshr_misses::cpu.inst 791449 # number of overall MSHR misses 389system.cpu.icache.overall_mshr_misses::total 791449 # number of overall MSHR misses 390system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9288383000 # number of ReadReq MSHR miss cycles 391system.cpu.icache.ReadReq_mshr_miss_latency::total 9288383000 # number of ReadReq MSHR miss cycles 392system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9288383000 # number of demand (read+write) MSHR miss cycles 393system.cpu.icache.demand_mshr_miss_latency::total 9288383000 # number of demand (read+write) MSHR miss cycles 394system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9288383000 # number of overall MSHR miss cycles 395system.cpu.icache.overall_mshr_miss_latency::total 9288383000 # number of overall MSHR miss cycles 396system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005449 # mshr miss rate for ReadReq accesses 397system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005449 # mshr miss rate for ReadReq accesses 398system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005449 # mshr miss rate for demand accesses 399system.cpu.icache.demand_mshr_miss_rate::total 0.005449 # mshr miss rate for demand accesses 400system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005449 # mshr miss rate for overall accesses 401system.cpu.icache.overall_mshr_miss_rate::total 0.005449 # mshr miss rate for overall accesses 402system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11735.921076 # average ReadReq mshr miss latency 403system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11735.921076 # average ReadReq mshr miss latency 404system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11735.921076 # average overall mshr miss latency 405system.cpu.icache.demand_avg_mshr_miss_latency::total 11735.921076 # average overall mshr miss latency 406system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11735.921076 # average overall mshr miss latency 407system.cpu.icache.overall_avg_mshr_miss_latency::total 11735.921076 # average overall mshr miss latency 408system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 409system.cpu.itb_walker_cache.replacements 3663 # number of replacements 410system.cpu.itb_walker_cache.tagsinuse 3.069768 # Cycle average of tags in use 411system.cpu.itb_walker_cache.total_refs 7696 # Total number of references to valid blocks. 412system.cpu.itb_walker_cache.sampled_refs 3675 # Sample count of references to valid blocks. 413system.cpu.itb_walker_cache.avg_refs 2.094150 # Average number of references to valid blocks. 414system.cpu.itb_walker_cache.warmup_cycle 5164936292000 # Cycle when the warmup percentage was hit. 415system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.069768 # Average occupied blocks per requestor 416system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.191861 # Average percentage of cache occupancy 417system.cpu.itb_walker_cache.occ_percent::total 0.191861 # Average percentage of cache occupancy 418system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7696 # number of ReadReq hits 419system.cpu.itb_walker_cache.ReadReq_hits::total 7696 # number of ReadReq hits 420system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 421system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits 422system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7698 # number of demand (read+write) hits 423system.cpu.itb_walker_cache.demand_hits::total 7698 # number of demand (read+write) hits 424system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7698 # number of overall hits 425system.cpu.itb_walker_cache.overall_hits::total 7698 # number of overall hits 426system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4528 # number of ReadReq misses 427system.cpu.itb_walker_cache.ReadReq_misses::total 4528 # number of ReadReq misses 428system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4528 # number of demand (read+write) misses 429system.cpu.itb_walker_cache.demand_misses::total 4528 # number of demand (read+write) misses 430system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4528 # number of overall misses 431system.cpu.itb_walker_cache.overall_misses::total 4528 # number of overall misses 432system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 46136000 # number of ReadReq miss cycles 433system.cpu.itb_walker_cache.ReadReq_miss_latency::total 46136000 # number of ReadReq miss cycles 434system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 46136000 # number of demand (read+write) miss cycles 435system.cpu.itb_walker_cache.demand_miss_latency::total 46136000 # number of demand (read+write) miss cycles 436system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 46136000 # number of overall miss cycles 437system.cpu.itb_walker_cache.overall_miss_latency::total 46136000 # number of overall miss cycles 438system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12224 # number of ReadReq accesses(hits+misses) 439system.cpu.itb_walker_cache.ReadReq_accesses::total 12224 # number of ReadReq accesses(hits+misses) 440system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 441system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) 442system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12226 # number of demand (read+write) accesses 443system.cpu.itb_walker_cache.demand_accesses::total 12226 # number of demand (read+write) accesses 444system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12226 # number of overall (read+write) accesses 445system.cpu.itb_walker_cache.overall_accesses::total 12226 # number of overall (read+write) accesses 446system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.370419 # miss rate for ReadReq accesses 447system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.370419 # miss rate for ReadReq accesses 448system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.370358 # miss rate for demand accesses 449system.cpu.itb_walker_cache.demand_miss_rate::total 0.370358 # miss rate for demand accesses 450system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.370358 # miss rate for overall accesses 451system.cpu.itb_walker_cache.overall_miss_rate::total 0.370358 # miss rate for overall accesses 452system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10189.045936 # average ReadReq miss latency 453system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10189.045936 # average ReadReq miss latency 454system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10189.045936 # average overall miss latency 455system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10189.045936 # average overall miss latency 456system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10189.045936 # average overall miss latency 457system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10189.045936 # average overall miss latency 458system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 459system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 460system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 461system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 462system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 463system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 464system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 465system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed 466system.cpu.itb_walker_cache.writebacks::writebacks 884 # number of writebacks 467system.cpu.itb_walker_cache.writebacks::total 884 # number of writebacks 468system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4528 # number of ReadReq MSHR misses 469system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4528 # number of ReadReq MSHR misses 470system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4528 # number of demand (read+write) MSHR misses 471system.cpu.itb_walker_cache.demand_mshr_misses::total 4528 # number of demand (read+write) MSHR misses 472system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4528 # number of overall MSHR misses 473system.cpu.itb_walker_cache.overall_mshr_misses::total 4528 # number of overall MSHR misses 474system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 37080000 # number of ReadReq MSHR miss cycles 475system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 37080000 # number of ReadReq MSHR miss cycles 476system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 37080000 # number of demand (read+write) MSHR miss cycles 477system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 37080000 # number of demand (read+write) MSHR miss cycles 478system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 37080000 # number of overall MSHR miss cycles 479system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 37080000 # number of overall MSHR miss cycles 480system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.370419 # mshr miss rate for ReadReq accesses 481system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.370419 # mshr miss rate for ReadReq accesses 482system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.370358 # mshr miss rate for demand accesses 483system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.370358 # mshr miss rate for demand accesses 484system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.370358 # mshr miss rate for overall accesses 485system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.370358 # mshr miss rate for overall accesses 486system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8189.045936 # average ReadReq mshr miss latency 487system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8189.045936 # average ReadReq mshr miss latency 488system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8189.045936 # average overall mshr miss latency 489system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8189.045936 # average overall mshr miss latency 490system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8189.045936 # average overall mshr miss latency 491system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8189.045936 # average overall mshr miss latency 492system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 493system.cpu.dtb_walker_cache.replacements 8012 # number of replacements 494system.cpu.dtb_walker_cache.tagsinuse 5.053256 # Cycle average of tags in use 495system.cpu.dtb_walker_cache.total_refs 13052 # Total number of references to valid blocks. 496system.cpu.dtb_walker_cache.sampled_refs 8025 # Sample count of references to valid blocks. 497system.cpu.dtb_walker_cache.avg_refs 1.626417 # Average number of references to valid blocks. 498system.cpu.dtb_walker_cache.warmup_cycle 5162707625000 # Cycle when the warmup percentage was hit. 499system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.053256 # Average occupied blocks per requestor 500system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.315829 # Average percentage of cache occupancy 501system.cpu.dtb_walker_cache.occ_percent::total 0.315829 # Average percentage of cache occupancy 502system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13068 # number of ReadReq hits 503system.cpu.dtb_walker_cache.ReadReq_hits::total 13068 # number of ReadReq hits 504system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13068 # number of demand (read+write) hits 505system.cpu.dtb_walker_cache.demand_hits::total 13068 # number of demand (read+write) hits 506system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13068 # number of overall hits 507system.cpu.dtb_walker_cache.overall_hits::total 13068 # number of overall hits 508system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 9194 # number of ReadReq misses 509system.cpu.dtb_walker_cache.ReadReq_misses::total 9194 # number of ReadReq misses 510system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 9194 # number of demand (read+write) misses 511system.cpu.dtb_walker_cache.demand_misses::total 9194 # number of demand (read+write) misses 512system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 9194 # number of overall misses 513system.cpu.dtb_walker_cache.overall_misses::total 9194 # number of overall misses 514system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 98984000 # number of ReadReq miss cycles 515system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 98984000 # number of ReadReq miss cycles 516system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 98984000 # number of demand (read+write) miss cycles 517system.cpu.dtb_walker_cache.demand_miss_latency::total 98984000 # number of demand (read+write) miss cycles 518system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 98984000 # number of overall miss cycles 519system.cpu.dtb_walker_cache.overall_miss_latency::total 98984000 # number of overall miss cycles 520system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22262 # number of ReadReq accesses(hits+misses) 521system.cpu.dtb_walker_cache.ReadReq_accesses::total 22262 # number of ReadReq accesses(hits+misses) 522system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22262 # number of demand (read+write) accesses 523system.cpu.dtb_walker_cache.demand_accesses::total 22262 # number of demand (read+write) accesses 524system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22262 # number of overall (read+write) accesses 525system.cpu.dtb_walker_cache.overall_accesses::total 22262 # number of overall (read+write) accesses 526system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.412991 # miss rate for ReadReq accesses 527system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.412991 # miss rate for ReadReq accesses 528system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.412991 # miss rate for demand accesses 529system.cpu.dtb_walker_cache.demand_miss_rate::total 0.412991 # miss rate for demand accesses 530system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.412991 # miss rate for overall accesses 531system.cpu.dtb_walker_cache.overall_miss_rate::total 0.412991 # miss rate for overall accesses 532system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10766.151838 # average ReadReq miss latency 533system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10766.151838 # average ReadReq miss latency 534system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10766.151838 # average overall miss latency 535system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10766.151838 # average overall miss latency 536system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10766.151838 # average overall miss latency 537system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10766.151838 # average overall miss latency 538system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 539system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 540system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 541system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 542system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 543system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 544system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 545system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed 546system.cpu.dtb_walker_cache.writebacks::writebacks 3347 # number of writebacks 547system.cpu.dtb_walker_cache.writebacks::total 3347 # number of writebacks 548system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 9194 # number of ReadReq MSHR misses 549system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 9194 # number of ReadReq MSHR misses 550system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 9194 # number of demand (read+write) MSHR misses 551system.cpu.dtb_walker_cache.demand_mshr_misses::total 9194 # number of demand (read+write) MSHR misses 552system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 9194 # number of overall MSHR misses 553system.cpu.dtb_walker_cache.overall_mshr_misses::total 9194 # number of overall MSHR misses 554system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 80596000 # number of ReadReq MSHR miss cycles 555system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 80596000 # number of ReadReq MSHR miss cycles 556system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 80596000 # number of demand (read+write) MSHR miss cycles 557system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 80596000 # number of demand (read+write) MSHR miss cycles 558system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 80596000 # number of overall MSHR miss cycles 559system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 80596000 # number of overall MSHR miss cycles 560system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.412991 # mshr miss rate for ReadReq accesses 561system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.412991 # mshr miss rate for ReadReq accesses 562system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.412991 # mshr miss rate for demand accesses 563system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.412991 # mshr miss rate for demand accesses 564system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.412991 # mshr miss rate for overall accesses 565system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.412991 # mshr miss rate for overall accesses 566system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8766.151838 # average ReadReq mshr miss latency 567system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8766.151838 # average ReadReq mshr miss latency 568system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8766.151838 # average overall mshr miss latency 569system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8766.151838 # average overall mshr miss latency 570system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8766.151838 # average overall mshr miss latency 571system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8766.151838 # average overall mshr miss latency 572system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 573system.cpu.dcache.replacements 1620901 # number of replacements 574system.cpu.dcache.tagsinuse 511.997778 # Cycle average of tags in use 575system.cpu.dcache.total_refs 20018688 # Total number of references to valid blocks. 576system.cpu.dcache.sampled_refs 1621413 # Sample count of references to valid blocks. 577system.cpu.dcache.avg_refs 12.346446 # Average number of references to valid blocks. 578system.cpu.dcache.warmup_cycle 38749000 # Cycle when the warmup percentage was hit. 579system.cpu.dcache.occ_blocks::cpu.data 511.997778 # Average occupied blocks per requestor 580system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy 581system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy 582system.cpu.dcache.ReadReq_hits::cpu.data 11981580 # number of ReadReq hits 583system.cpu.dcache.ReadReq_hits::total 11981580 # number of ReadReq hits 584system.cpu.dcache.WriteReq_hits::cpu.data 8034926 # number of WriteReq hits 585system.cpu.dcache.WriteReq_hits::total 8034926 # number of WriteReq hits 586system.cpu.dcache.demand_hits::cpu.data 20016506 # number of demand (read+write) hits 587system.cpu.dcache.demand_hits::total 20016506 # number of demand (read+write) hits 588system.cpu.dcache.overall_hits::cpu.data 20016506 # number of overall hits 589system.cpu.dcache.overall_hits::total 20016506 # number of overall hits 590system.cpu.dcache.ReadReq_misses::cpu.data 1308145 # number of ReadReq misses 591system.cpu.dcache.ReadReq_misses::total 1308145 # number of ReadReq misses 592system.cpu.dcache.WriteReq_misses::cpu.data 315486 # number of WriteReq misses 593system.cpu.dcache.WriteReq_misses::total 315486 # number of WriteReq misses 594system.cpu.dcache.demand_misses::cpu.data 1623631 # number of demand (read+write) misses 595system.cpu.dcache.demand_misses::total 1623631 # number of demand (read+write) misses 596system.cpu.dcache.overall_misses::cpu.data 1623631 # number of overall misses 597system.cpu.dcache.overall_misses::total 1623631 # number of overall misses 598system.cpu.dcache.ReadReq_miss_latency::cpu.data 18313644000 # number of ReadReq miss cycles 599system.cpu.dcache.ReadReq_miss_latency::total 18313644000 # number of ReadReq miss cycles 600system.cpu.dcache.WriteReq_miss_latency::cpu.data 8702717500 # number of WriteReq miss cycles 601system.cpu.dcache.WriteReq_miss_latency::total 8702717500 # number of WriteReq miss cycles 602system.cpu.dcache.demand_miss_latency::cpu.data 27016361500 # number of demand (read+write) miss cycles 603system.cpu.dcache.demand_miss_latency::total 27016361500 # number of demand (read+write) miss cycles 604system.cpu.dcache.overall_miss_latency::cpu.data 27016361500 # number of overall miss cycles 605system.cpu.dcache.overall_miss_latency::total 27016361500 # number of overall miss cycles 606system.cpu.dcache.ReadReq_accesses::cpu.data 13289725 # number of ReadReq accesses(hits+misses) 607system.cpu.dcache.ReadReq_accesses::total 13289725 # number of ReadReq accesses(hits+misses) 608system.cpu.dcache.WriteReq_accesses::cpu.data 8350412 # number of WriteReq accesses(hits+misses) 609system.cpu.dcache.WriteReq_accesses::total 8350412 # number of WriteReq accesses(hits+misses) 610system.cpu.dcache.demand_accesses::cpu.data 21640137 # number of demand (read+write) accesses 611system.cpu.dcache.demand_accesses::total 21640137 # number of demand (read+write) accesses 612system.cpu.dcache.overall_accesses::cpu.data 21640137 # number of overall (read+write) accesses 613system.cpu.dcache.overall_accesses::total 21640137 # number of overall (read+write) accesses 614system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098433 # miss rate for ReadReq accesses 615system.cpu.dcache.ReadReq_miss_rate::total 0.098433 # miss rate for ReadReq accesses 616system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037781 # miss rate for WriteReq accesses 617system.cpu.dcache.WriteReq_miss_rate::total 0.037781 # miss rate for WriteReq accesses 618system.cpu.dcache.demand_miss_rate::cpu.data 0.075029 # miss rate for demand accesses 619system.cpu.dcache.demand_miss_rate::total 0.075029 # miss rate for demand accesses 620system.cpu.dcache.overall_miss_rate::cpu.data 0.075029 # miss rate for overall accesses 621system.cpu.dcache.overall_miss_rate::total 0.075029 # miss rate for overall accesses 622system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13999.704926 # average ReadReq miss latency 623system.cpu.dcache.ReadReq_avg_miss_latency::total 13999.704926 # average ReadReq miss latency 624system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27585.114712 # average WriteReq miss latency 625system.cpu.dcache.WriteReq_avg_miss_latency::total 27585.114712 # average WriteReq miss latency 626system.cpu.dcache.demand_avg_miss_latency::cpu.data 16639.471345 # average overall miss latency 627system.cpu.dcache.demand_avg_miss_latency::total 16639.471345 # average overall miss latency 628system.cpu.dcache.overall_avg_miss_latency::cpu.data 16639.471345 # average overall miss latency 629system.cpu.dcache.overall_avg_miss_latency::total 16639.471345 # average overall miss latency 630system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 631system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 632system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 633system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 634system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 635system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 636system.cpu.dcache.fast_writes 0 # number of fast writes performed 637system.cpu.dcache.cache_copies 0 # number of cache copies performed 638system.cpu.dcache.writebacks::writebacks 1538028 # number of writebacks 639system.cpu.dcache.writebacks::total 1538028 # number of writebacks 640system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1308145 # number of ReadReq MSHR misses 641system.cpu.dcache.ReadReq_mshr_misses::total 1308145 # number of ReadReq MSHR misses 642system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315486 # number of WriteReq MSHR misses 643system.cpu.dcache.WriteReq_mshr_misses::total 315486 # number of WriteReq MSHR misses 644system.cpu.dcache.demand_mshr_misses::cpu.data 1623631 # number of demand (read+write) MSHR misses 645system.cpu.dcache.demand_mshr_misses::total 1623631 # number of demand (read+write) MSHR misses 646system.cpu.dcache.overall_mshr_misses::cpu.data 1623631 # number of overall MSHR misses 647system.cpu.dcache.overall_mshr_misses::total 1623631 # number of overall MSHR misses 648system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15697354000 # number of ReadReq MSHR miss cycles 649system.cpu.dcache.ReadReq_mshr_miss_latency::total 15697354000 # number of ReadReq MSHR miss cycles 650system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8071745500 # number of WriteReq MSHR miss cycles 651system.cpu.dcache.WriteReq_mshr_miss_latency::total 8071745500 # number of WriteReq MSHR miss cycles 652system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23769099500 # number of demand (read+write) MSHR miss cycles 653system.cpu.dcache.demand_mshr_miss_latency::total 23769099500 # number of demand (read+write) MSHR miss cycles 654system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23769099500 # number of overall MSHR miss cycles 655system.cpu.dcache.overall_mshr_miss_latency::total 23769099500 # number of overall MSHR miss cycles 656system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94147176000 # number of ReadReq MSHR uncacheable cycles 657system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94147176000 # number of ReadReq MSHR uncacheable cycles 658system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2469978500 # number of WriteReq MSHR uncacheable cycles 659system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2469978500 # number of WriteReq MSHR uncacheable cycles 660system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96617154500 # number of overall MSHR uncacheable cycles 661system.cpu.dcache.overall_mshr_uncacheable_latency::total 96617154500 # number of overall MSHR uncacheable cycles 662system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098433 # mshr miss rate for ReadReq accesses 663system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098433 # mshr miss rate for ReadReq accesses 664system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037781 # mshr miss rate for WriteReq accesses 665system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037781 # mshr miss rate for WriteReq accesses 666system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.075029 # mshr miss rate for demand accesses 667system.cpu.dcache.demand_mshr_miss_rate::total 0.075029 # mshr miss rate for demand accesses 668system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.075029 # mshr miss rate for overall accesses 669system.cpu.dcache.overall_mshr_miss_rate::total 0.075029 # mshr miss rate for overall accesses 670system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11999.704926 # average ReadReq mshr miss latency 671system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11999.704926 # average ReadReq mshr miss latency 672system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25585.114712 # average WriteReq mshr miss latency 673system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25585.114712 # average WriteReq mshr miss latency 674system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14639.471345 # average overall mshr miss latency 675system.cpu.dcache.demand_avg_mshr_miss_latency::total 14639.471345 # average overall mshr miss latency 676system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14639.471345 # average overall mshr miss latency 677system.cpu.dcache.overall_avg_mshr_miss_latency::total 14639.471345 # average overall mshr miss latency 678system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 679system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 680system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 681system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 682system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 683system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 684system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 685system.cpu.l2cache.replacements 87015 # number of replacements 686system.cpu.l2cache.tagsinuse 64709.520704 # Cycle average of tags in use 687system.cpu.l2cache.total_refs 3488531 # Total number of references to valid blocks. 688system.cpu.l2cache.sampled_refs 151765 # Sample count of references to valid blocks. 689system.cpu.l2cache.avg_refs 22.986400 # Average number of references to valid blocks. 690system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 691system.cpu.l2cache.occ_blocks::writebacks 50328.696692 # Average occupied blocks per requestor 692system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.140121 # Average occupied blocks per requestor 693system.cpu.l2cache.occ_blocks::cpu.inst 3391.684309 # Average occupied blocks per requestor 694system.cpu.l2cache.occ_blocks::cpu.data 10988.999582 # Average occupied blocks per requestor 695system.cpu.l2cache.occ_percent::writebacks 0.767955 # Average percentage of cache occupancy 696system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy 697system.cpu.l2cache.occ_percent::cpu.inst 0.051753 # Average percentage of cache occupancy 698system.cpu.l2cache.occ_percent::cpu.data 0.167679 # Average percentage of cache occupancy 699system.cpu.l2cache.occ_percent::total 0.987389 # Average percentage of cache occupancy 700system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6912 # number of ReadReq hits 701system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3076 # number of ReadReq hits 702system.cpu.l2cache.ReadReq_hits::cpu.inst 778529 # number of ReadReq hits 703system.cpu.l2cache.ReadReq_hits::cpu.data 1278877 # number of ReadReq hits 704system.cpu.l2cache.ReadReq_hits::total 2067394 # number of ReadReq hits 705system.cpu.l2cache.Writeback_hits::writebacks 1542259 # number of Writeback hits 706system.cpu.l2cache.Writeback_hits::total 1542259 # number of Writeback hits 707system.cpu.l2cache.UpgradeReq_hits::cpu.data 324 # number of UpgradeReq hits 708system.cpu.l2cache.UpgradeReq_hits::total 324 # number of UpgradeReq hits 709system.cpu.l2cache.ReadExReq_hits::cpu.data 199770 # number of ReadExReq hits 710system.cpu.l2cache.ReadExReq_hits::total 199770 # number of ReadExReq hits 711system.cpu.l2cache.demand_hits::cpu.dtb.walker 6912 # number of demand (read+write) hits 712system.cpu.l2cache.demand_hits::cpu.itb.walker 3076 # number of demand (read+write) hits 713system.cpu.l2cache.demand_hits::cpu.inst 778529 # number of demand (read+write) hits 714system.cpu.l2cache.demand_hits::cpu.data 1478647 # number of demand (read+write) hits 715system.cpu.l2cache.demand_hits::total 2267164 # number of demand (read+write) hits 716system.cpu.l2cache.overall_hits::cpu.dtb.walker 6912 # number of overall hits 717system.cpu.l2cache.overall_hits::cpu.itb.walker 3076 # number of overall hits 718system.cpu.l2cache.overall_hits::cpu.inst 778529 # number of overall hits 719system.cpu.l2cache.overall_hits::cpu.data 1478647 # number of overall hits 720system.cpu.l2cache.overall_hits::total 2267164 # number of overall hits 721system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses 722system.cpu.l2cache.ReadReq_misses::cpu.inst 12907 # number of ReadReq misses 723system.cpu.l2cache.ReadReq_misses::cpu.data 28433 # number of ReadReq misses 724system.cpu.l2cache.ReadReq_misses::total 41345 # number of ReadReq misses 725system.cpu.l2cache.UpgradeReq_misses::cpu.data 1340 # number of UpgradeReq misses 726system.cpu.l2cache.UpgradeReq_misses::total 1340 # number of UpgradeReq misses 727system.cpu.l2cache.ReadExReq_misses::cpu.data 113530 # number of ReadExReq misses 728system.cpu.l2cache.ReadExReq_misses::total 113530 # number of ReadExReq misses 729system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses 730system.cpu.l2cache.demand_misses::cpu.inst 12907 # number of demand (read+write) misses 731system.cpu.l2cache.demand_misses::cpu.data 141963 # number of demand (read+write) misses 732system.cpu.l2cache.demand_misses::total 154875 # number of demand (read+write) misses 733system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses 734system.cpu.l2cache.overall_misses::cpu.inst 12907 # number of overall misses 735system.cpu.l2cache.overall_misses::cpu.data 141963 # number of overall misses 736system.cpu.l2cache.overall_misses::total 154875 # number of overall misses 737system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 345000 # number of ReadReq miss cycles 738system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 711631000 # number of ReadReq miss cycles 739system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1599602500 # number of ReadReq miss cycles 740system.cpu.l2cache.ReadReq_miss_latency::total 2311578500 # number of ReadReq miss cycles 741system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 16623000 # number of UpgradeReq miss cycles 742system.cpu.l2cache.UpgradeReq_miss_latency::total 16623000 # number of UpgradeReq miss cycles 743system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5723743500 # number of ReadExReq miss cycles 744system.cpu.l2cache.ReadExReq_miss_latency::total 5723743500 # number of ReadExReq miss cycles 745system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 345000 # number of demand (read+write) miss cycles 746system.cpu.l2cache.demand_miss_latency::cpu.inst 711631000 # number of demand (read+write) miss cycles 747system.cpu.l2cache.demand_miss_latency::cpu.data 7323346000 # number of demand (read+write) miss cycles 748system.cpu.l2cache.demand_miss_latency::total 8035322000 # number of demand (read+write) miss cycles 749system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 345000 # number of overall miss cycles 750system.cpu.l2cache.overall_miss_latency::cpu.inst 711631000 # number of overall miss cycles 751system.cpu.l2cache.overall_miss_latency::cpu.data 7323346000 # number of overall miss cycles 752system.cpu.l2cache.overall_miss_latency::total 8035322000 # number of overall miss cycles 753system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6912 # number of ReadReq accesses(hits+misses) 754system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3081 # number of ReadReq accesses(hits+misses) 755system.cpu.l2cache.ReadReq_accesses::cpu.inst 791436 # number of ReadReq accesses(hits+misses) 756system.cpu.l2cache.ReadReq_accesses::cpu.data 1307310 # number of ReadReq accesses(hits+misses) 757system.cpu.l2cache.ReadReq_accesses::total 2108739 # number of ReadReq accesses(hits+misses) 758system.cpu.l2cache.Writeback_accesses::writebacks 1542259 # number of Writeback accesses(hits+misses) 759system.cpu.l2cache.Writeback_accesses::total 1542259 # number of Writeback accesses(hits+misses) 760system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1664 # number of UpgradeReq accesses(hits+misses) 761system.cpu.l2cache.UpgradeReq_accesses::total 1664 # number of UpgradeReq accesses(hits+misses) 762system.cpu.l2cache.ReadExReq_accesses::cpu.data 313300 # number of ReadExReq accesses(hits+misses) 763system.cpu.l2cache.ReadExReq_accesses::total 313300 # number of ReadExReq accesses(hits+misses) 764system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6912 # number of demand (read+write) accesses 765system.cpu.l2cache.demand_accesses::cpu.itb.walker 3081 # number of demand (read+write) accesses 766system.cpu.l2cache.demand_accesses::cpu.inst 791436 # number of demand (read+write) accesses 767system.cpu.l2cache.demand_accesses::cpu.data 1620610 # number of demand (read+write) accesses 768system.cpu.l2cache.demand_accesses::total 2422039 # number of demand (read+write) accesses 769system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6912 # number of overall (read+write) accesses 770system.cpu.l2cache.overall_accesses::cpu.itb.walker 3081 # number of overall (read+write) accesses 771system.cpu.l2cache.overall_accesses::cpu.inst 791436 # number of overall (read+write) accesses 772system.cpu.l2cache.overall_accesses::cpu.data 1620610 # number of overall (read+write) accesses 773system.cpu.l2cache.overall_accesses::total 2422039 # number of overall (read+write) accesses 774system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001623 # miss rate for ReadReq accesses 775system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016308 # miss rate for ReadReq accesses 776system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021749 # miss rate for ReadReq accesses 777system.cpu.l2cache.ReadReq_miss_rate::total 0.019607 # miss rate for ReadReq accesses 778system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.805288 # miss rate for UpgradeReq accesses 779system.cpu.l2cache.UpgradeReq_miss_rate::total 0.805288 # miss rate for UpgradeReq accesses 780system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.362368 # miss rate for ReadExReq accesses 781system.cpu.l2cache.ReadExReq_miss_rate::total 0.362368 # miss rate for ReadExReq accesses 782system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001623 # miss rate for demand accesses 783system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016308 # miss rate for demand accesses 784system.cpu.l2cache.demand_miss_rate::cpu.data 0.087598 # miss rate for demand accesses 785system.cpu.l2cache.demand_miss_rate::total 0.063944 # miss rate for demand accesses 786system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001623 # miss rate for overall accesses 787system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016308 # miss rate for overall accesses 788system.cpu.l2cache.overall_miss_rate::cpu.data 0.087598 # miss rate for overall accesses 789system.cpu.l2cache.overall_miss_rate::total 0.063944 # miss rate for overall accesses 790system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 69000 # average ReadReq miss latency 791system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 55135.275432 # average ReadReq miss latency 792system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56258.660711 # average ReadReq miss latency 793system.cpu.l2cache.ReadReq_avg_miss_latency::total 55909.505382 # average ReadReq miss latency 794system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12405.223881 # average UpgradeReq miss latency 795system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12405.223881 # average UpgradeReq miss latency 796system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50416.132300 # average ReadExReq miss latency 797system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50416.132300 # average ReadExReq miss latency 798system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 69000 # average overall miss latency 799system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 55135.275432 # average overall miss latency 800system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51586.300656 # average overall miss latency 801system.cpu.l2cache.demand_avg_miss_latency::total 51882.627926 # average overall miss latency 802system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 69000 # average overall miss latency 803system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 55135.275432 # average overall miss latency 804system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51586.300656 # average overall miss latency 805system.cpu.l2cache.overall_avg_miss_latency::total 51882.627926 # average overall miss latency 806system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 807system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 808system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 809system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 810system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 811system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 812system.cpu.l2cache.fast_writes 0 # number of fast writes performed 813system.cpu.l2cache.cache_copies 0 # number of cache copies performed 814system.cpu.l2cache.writebacks::writebacks 80353 # number of writebacks 815system.cpu.l2cache.writebacks::total 80353 # number of writebacks 816system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses 817system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12907 # number of ReadReq MSHR misses 818system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28433 # number of ReadReq MSHR misses 819system.cpu.l2cache.ReadReq_mshr_misses::total 41345 # number of ReadReq MSHR misses 820system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1340 # number of UpgradeReq MSHR misses 821system.cpu.l2cache.UpgradeReq_mshr_misses::total 1340 # number of UpgradeReq MSHR misses 822system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 113530 # number of ReadExReq MSHR misses 823system.cpu.l2cache.ReadExReq_mshr_misses::total 113530 # number of ReadExReq MSHR misses 824system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses 825system.cpu.l2cache.demand_mshr_misses::cpu.inst 12907 # number of demand (read+write) MSHR misses 826system.cpu.l2cache.demand_mshr_misses::cpu.data 141963 # number of demand (read+write) MSHR misses 827system.cpu.l2cache.demand_mshr_misses::total 154875 # number of demand (read+write) MSHR misses 828system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses 829system.cpu.l2cache.overall_mshr_misses::cpu.inst 12907 # number of overall MSHR misses 830system.cpu.l2cache.overall_mshr_misses::cpu.data 141963 # number of overall MSHR misses 831system.cpu.l2cache.overall_mshr_misses::total 154875 # number of overall MSHR misses 832system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 280010 # number of ReadReq MSHR miss cycles 833system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 544173395 # number of ReadReq MSHR miss cycles 834system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1230984255 # number of ReadReq MSHR miss cycles 835system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1775437660 # number of ReadReq MSHR miss cycles 836system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14316322 # number of UpgradeReq MSHR miss cycles 837system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14316322 # number of UpgradeReq MSHR miss cycles 838system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4249333352 # number of ReadExReq MSHR miss cycles 839system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4249333352 # number of ReadExReq MSHR miss cycles 840system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 280010 # number of demand (read+write) MSHR miss cycles 841system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 544173395 # number of demand (read+write) MSHR miss cycles 842system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5480317607 # number of demand (read+write) MSHR miss cycles 843system.cpu.l2cache.demand_mshr_miss_latency::total 6024771012 # number of demand (read+write) MSHR miss cycles 844system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 280010 # number of overall MSHR miss cycles 845system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 544173395 # number of overall MSHR miss cycles 846system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5480317607 # number of overall MSHR miss cycles 847system.cpu.l2cache.overall_mshr_miss_latency::total 6024771012 # number of overall MSHR miss cycles 848system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86592298500 # number of ReadReq MSHR uncacheable cycles 849system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86592298500 # number of ReadReq MSHR uncacheable cycles 850system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2307004500 # number of WriteReq MSHR uncacheable cycles 851system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2307004500 # number of WriteReq MSHR uncacheable cycles 852system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 88899303000 # number of overall MSHR uncacheable cycles 853system.cpu.l2cache.overall_mshr_uncacheable_latency::total 88899303000 # number of overall MSHR uncacheable cycles 854system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001623 # mshr miss rate for ReadReq accesses 855system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016308 # mshr miss rate for ReadReq accesses 856system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021749 # mshr miss rate for ReadReq accesses 857system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019607 # mshr miss rate for ReadReq accesses 858system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.805288 # mshr miss rate for UpgradeReq accesses 859system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.805288 # mshr miss rate for UpgradeReq accesses 860system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.362368 # mshr miss rate for ReadExReq accesses 861system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.362368 # mshr miss rate for ReadExReq accesses 862system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001623 # mshr miss rate for demand accesses 863system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016308 # mshr miss rate for demand accesses 864system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087598 # mshr miss rate for demand accesses 865system.cpu.l2cache.demand_mshr_miss_rate::total 0.063944 # mshr miss rate for demand accesses 866system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001623 # mshr miss rate for overall accesses 867system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016308 # mshr miss rate for overall accesses 868system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087598 # mshr miss rate for overall accesses 869system.cpu.l2cache.overall_mshr_miss_rate::total 0.063944 # mshr miss rate for overall accesses 870system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 56002 # average ReadReq mshr miss latency 871system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42161.105989 # average ReadReq mshr miss latency 872system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43294.209369 # average ReadReq mshr miss latency 873system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42942.016205 # average ReadReq mshr miss latency 874system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10683.822388 # average UpgradeReq mshr miss latency 875system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10683.822388 # average UpgradeReq mshr miss latency 876system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37429.167198 # average ReadExReq mshr miss latency 877system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37429.167198 # average ReadExReq mshr miss latency 878system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 56002 # average overall mshr miss latency 879system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42161.105989 # average overall mshr miss latency 880system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38603.844713 # average overall mshr miss latency 881system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38900.862063 # average overall mshr miss latency 882system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 56002 # average overall mshr miss latency 883system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42161.105989 # average overall mshr miss latency 884system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38603.844713 # average overall mshr miss latency 885system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38900.862063 # average overall mshr miss latency 886system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 887system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 888system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 889system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 890system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 891system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 892system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 893 894---------- End Simulation Statistics ---------- 895