stats.txt revision 9285:9901180cd573
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.187896 # Number of seconds simulated 4sim_ticks 5187896410000 # Number of ticks simulated 5final_tick 5187896410000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 834857 # Simulator instruction rate (inst/s) 8host_op_rate 1609393 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 33766110220 # Simulator tick rate (ticks/s) 10host_mem_usage 354356 # Number of bytes of host memory used 11host_seconds 153.64 # Real time elapsed on the host 12sim_insts 128269216 # Number of instructions simulated 13sim_ops 247270559 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::pc.south_bridge.ide 2867328 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu.inst 826944 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8996288 # Number of bytes read from this memory 18system.physmem.bytes_read::total 12690880 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 826944 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 826944 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 8107200 # Number of bytes written to this memory 22system.physmem.bytes_written::total 8107200 # Number of bytes written to this memory 23system.physmem.num_reads::pc.south_bridge.ide 44802 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.inst 12921 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.data 140567 # Number of read requests responded to by this memory 27system.physmem.num_reads::total 198295 # Number of read requests responded to by this memory 28system.physmem.num_writes::writebacks 126675 # Number of write requests responded to by this memory 29system.physmem.num_writes::total 126675 # Number of write requests responded to by this memory 30system.physmem.bw_read::pc.south_bridge.ide 552696 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.inst 159399 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::cpu.data 1734092 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::total 2446248 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::cpu.inst 159399 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_inst_read::total 159399 # Instruction read bandwidth from this memory (bytes/s) 37system.physmem.bw_write::writebacks 1562714 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_write::total 1562714 # Write bandwidth from this memory (bytes/s) 39system.physmem.bw_total::writebacks 1562714 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::pc.south_bridge.ide 552696 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::cpu.inst 159399 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::cpu.data 1734092 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.bw_total::total 4008962 # Total bandwidth to/from this memory (bytes/s) 45system.iocache.replacements 47503 # number of replacements 46system.iocache.tagsinuse 0.106662 # Cycle average of tags in use 47system.iocache.total_refs 0 # Total number of references to valid blocks. 48system.iocache.sampled_refs 47519 # Sample count of references to valid blocks. 49system.iocache.avg_refs 0 # Average number of references to valid blocks. 50system.iocache.warmup_cycle 5044925516000 # Cycle when the warmup percentage was hit. 51system.iocache.occ_blocks::pc.south_bridge.ide 0.106662 # Average occupied blocks per requestor 52system.iocache.occ_percent::pc.south_bridge.ide 0.006666 # Average percentage of cache occupancy 53system.iocache.occ_percent::total 0.006666 # Average percentage of cache occupancy 54system.iocache.ReadReq_misses::pc.south_bridge.ide 838 # number of ReadReq misses 55system.iocache.ReadReq_misses::total 838 # number of ReadReq misses 56system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses 57system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses 58system.iocache.demand_misses::pc.south_bridge.ide 47558 # number of demand (read+write) misses 59system.iocache.demand_misses::total 47558 # number of demand (read+write) misses 60system.iocache.overall_misses::pc.south_bridge.ide 47558 # number of overall misses 61system.iocache.overall_misses::total 47558 # number of overall misses 62system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 130045932 # number of ReadReq miss cycles 63system.iocache.ReadReq_miss_latency::total 130045932 # number of ReadReq miss cycles 64system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10696163160 # number of WriteReq miss cycles 65system.iocache.WriteReq_miss_latency::total 10696163160 # number of WriteReq miss cycles 66system.iocache.demand_miss_latency::pc.south_bridge.ide 10826209092 # number of demand (read+write) miss cycles 67system.iocache.demand_miss_latency::total 10826209092 # number of demand (read+write) miss cycles 68system.iocache.overall_miss_latency::pc.south_bridge.ide 10826209092 # number of overall miss cycles 69system.iocache.overall_miss_latency::total 10826209092 # number of overall miss cycles 70system.iocache.ReadReq_accesses::pc.south_bridge.ide 838 # number of ReadReq accesses(hits+misses) 71system.iocache.ReadReq_accesses::total 838 # number of ReadReq accesses(hits+misses) 72system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) 73system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) 74system.iocache.demand_accesses::pc.south_bridge.ide 47558 # number of demand (read+write) accesses 75system.iocache.demand_accesses::total 47558 # number of demand (read+write) accesses 76system.iocache.overall_accesses::pc.south_bridge.ide 47558 # number of overall (read+write) accesses 77system.iocache.overall_accesses::total 47558 # number of overall (read+write) accesses 78system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 79system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 80system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses 81system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 82system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 83system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 84system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 85system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 86system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 155186.076372 # average ReadReq miss latency 87system.iocache.ReadReq_avg_miss_latency::total 155186.076372 # average ReadReq miss latency 88system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 228941.848459 # average WriteReq miss latency 89system.iocache.WriteReq_avg_miss_latency::total 228941.848459 # average WriteReq miss latency 90system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 227642.228269 # average overall miss latency 91system.iocache.demand_avg_miss_latency::total 227642.228269 # average overall miss latency 92system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 227642.228269 # average overall miss latency 93system.iocache.overall_avg_miss_latency::total 227642.228269 # average overall miss latency 94system.iocache.blocked_cycles::no_mshrs 90077012 # number of cycles access was blocked 95system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 96system.iocache.blocked::no_mshrs 11025 # number of cycles access was blocked 97system.iocache.blocked::no_targets 0 # number of cycles access was blocked 98system.iocache.avg_blocked_cycles::no_mshrs 8170.250522 # average number of cycles each access was blocked 99system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 100system.iocache.fast_writes 0 # number of fast writes performed 101system.iocache.cache_copies 0 # number of cache copies performed 102system.iocache.writebacks::writebacks 46667 # number of writebacks 103system.iocache.writebacks::total 46667 # number of writebacks 104system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 838 # number of ReadReq MSHR misses 105system.iocache.ReadReq_mshr_misses::total 838 # number of ReadReq MSHR misses 106system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses 107system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses 108system.iocache.demand_mshr_misses::pc.south_bridge.ide 47558 # number of demand (read+write) MSHR misses 109system.iocache.demand_mshr_misses::total 47558 # number of demand (read+write) MSHR misses 110system.iocache.overall_mshr_misses::pc.south_bridge.ide 47558 # number of overall MSHR misses 111system.iocache.overall_mshr_misses::total 47558 # number of overall MSHR misses 112system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 86439000 # number of ReadReq MSHR miss cycles 113system.iocache.ReadReq_mshr_miss_latency::total 86439000 # number of ReadReq MSHR miss cycles 114system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8266468944 # number of WriteReq MSHR miss cycles 115system.iocache.WriteReq_mshr_miss_latency::total 8266468944 # number of WriteReq MSHR miss cycles 116system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8352907944 # number of demand (read+write) MSHR miss cycles 117system.iocache.demand_mshr_miss_latency::total 8352907944 # number of demand (read+write) MSHR miss cycles 118system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8352907944 # number of overall MSHR miss cycles 119system.iocache.overall_mshr_miss_latency::total 8352907944 # number of overall MSHR miss cycles 120system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 121system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 122system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses 123system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 124system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 125system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 126system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 127system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 128system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 103149.164678 # average ReadReq mshr miss latency 129system.iocache.ReadReq_avg_mshr_miss_latency::total 103149.164678 # average ReadReq mshr miss latency 130system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 176936.407192 # average WriteReq mshr miss latency 131system.iocache.WriteReq_avg_mshr_miss_latency::total 176936.407192 # average WriteReq mshr miss latency 132system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 175636.232474 # average overall mshr miss latency 133system.iocache.demand_avg_mshr_miss_latency::total 175636.232474 # average overall mshr miss latency 134system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 175636.232474 # average overall mshr miss latency 135system.iocache.overall_avg_mshr_miss_latency::total 175636.232474 # average overall mshr miss latency 136system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 137system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 138system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 139system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). 140system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 141system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 142system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 143system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 144system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 145system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 146system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 147system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 148system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 149system.cpu.numCycles 10375792820 # number of cpu cycles simulated 150system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 151system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 152system.cpu.committedInsts 128269216 # Number of instructions committed 153system.cpu.committedOps 247270559 # Number of ops (including micro ops) committed 154system.cpu.num_int_alu_accesses 232005526 # Number of integer alu accesses 155system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 156system.cpu.num_func_calls 0 # number of times a function call or return occured 157system.cpu.num_conditional_control_insts 23152914 # number of instructions that are conditional controls 158system.cpu.num_int_insts 232005526 # number of integer instructions 159system.cpu.num_fp_insts 0 # number of float instructions 160system.cpu.num_int_register_reads 567048885 # number of times the integer registers were read 161system.cpu.num_int_register_writes 293217624 # number of times the integer registers were written 162system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 163system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 164system.cpu.num_mem_refs 22238817 # number of memory refs 165system.cpu.num_load_insts 13875768 # Number of load instructions 166system.cpu.num_store_insts 8363049 # Number of store instructions 167system.cpu.num_idle_cycles 9774979498.742117 # Number of idle cycles 168system.cpu.num_busy_cycles 600813321.257884 # Number of busy cycles 169system.cpu.not_idle_fraction 0.057905 # Percentage of non-idle cycles 170system.cpu.idle_fraction 0.942095 # Percentage of idle cycles 171system.cpu.kern.inst.arm 0 # number of arm instructions executed 172system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 173system.cpu.icache.replacements 793131 # number of replacements 174system.cpu.icache.tagsinuse 510.350730 # Cycle average of tags in use 175system.cpu.icache.total_refs 144484487 # Total number of references to valid blocks. 176system.cpu.icache.sampled_refs 793643 # Sample count of references to valid blocks. 177system.cpu.icache.avg_refs 182.052241 # Average number of references to valid blocks. 178system.cpu.icache.warmup_cycle 160314386000 # Cycle when the warmup percentage was hit. 179system.cpu.icache.occ_blocks::cpu.inst 510.350730 # Average occupied blocks per requestor 180system.cpu.icache.occ_percent::cpu.inst 0.996779 # Average percentage of cache occupancy 181system.cpu.icache.occ_percent::total 0.996779 # Average percentage of cache occupancy 182system.cpu.icache.ReadReq_hits::cpu.inst 144484487 # number of ReadReq hits 183system.cpu.icache.ReadReq_hits::total 144484487 # number of ReadReq hits 184system.cpu.icache.demand_hits::cpu.inst 144484487 # number of demand (read+write) hits 185system.cpu.icache.demand_hits::total 144484487 # number of demand (read+write) hits 186system.cpu.icache.overall_hits::cpu.inst 144484487 # number of overall hits 187system.cpu.icache.overall_hits::total 144484487 # number of overall hits 188system.cpu.icache.ReadReq_misses::cpu.inst 793650 # number of ReadReq misses 189system.cpu.icache.ReadReq_misses::total 793650 # number of ReadReq misses 190system.cpu.icache.demand_misses::cpu.inst 793650 # number of demand (read+write) misses 191system.cpu.icache.demand_misses::total 793650 # number of demand (read+write) misses 192system.cpu.icache.overall_misses::cpu.inst 793650 # number of overall misses 193system.cpu.icache.overall_misses::total 793650 # number of overall misses 194system.cpu.icache.ReadReq_miss_latency::cpu.inst 10860662000 # number of ReadReq miss cycles 195system.cpu.icache.ReadReq_miss_latency::total 10860662000 # number of ReadReq miss cycles 196system.cpu.icache.demand_miss_latency::cpu.inst 10860662000 # number of demand (read+write) miss cycles 197system.cpu.icache.demand_miss_latency::total 10860662000 # number of demand (read+write) miss cycles 198system.cpu.icache.overall_miss_latency::cpu.inst 10860662000 # number of overall miss cycles 199system.cpu.icache.overall_miss_latency::total 10860662000 # number of overall miss cycles 200system.cpu.icache.ReadReq_accesses::cpu.inst 145278137 # number of ReadReq accesses(hits+misses) 201system.cpu.icache.ReadReq_accesses::total 145278137 # number of ReadReq accesses(hits+misses) 202system.cpu.icache.demand_accesses::cpu.inst 145278137 # number of demand (read+write) accesses 203system.cpu.icache.demand_accesses::total 145278137 # number of demand (read+write) accesses 204system.cpu.icache.overall_accesses::cpu.inst 145278137 # number of overall (read+write) accesses 205system.cpu.icache.overall_accesses::total 145278137 # number of overall (read+write) accesses 206system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005463 # miss rate for ReadReq accesses 207system.cpu.icache.ReadReq_miss_rate::total 0.005463 # miss rate for ReadReq accesses 208system.cpu.icache.demand_miss_rate::cpu.inst 0.005463 # miss rate for demand accesses 209system.cpu.icache.demand_miss_rate::total 0.005463 # miss rate for demand accesses 210system.cpu.icache.overall_miss_rate::cpu.inst 0.005463 # miss rate for overall accesses 211system.cpu.icache.overall_miss_rate::total 0.005463 # miss rate for overall accesses 212system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13684.447804 # average ReadReq miss latency 213system.cpu.icache.ReadReq_avg_miss_latency::total 13684.447804 # average ReadReq miss latency 214system.cpu.icache.demand_avg_miss_latency::cpu.inst 13684.447804 # average overall miss latency 215system.cpu.icache.demand_avg_miss_latency::total 13684.447804 # average overall miss latency 216system.cpu.icache.overall_avg_miss_latency::cpu.inst 13684.447804 # average overall miss latency 217system.cpu.icache.overall_avg_miss_latency::total 13684.447804 # average overall miss latency 218system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 219system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 220system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 221system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 222system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 223system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 224system.cpu.icache.fast_writes 0 # number of fast writes performed 225system.cpu.icache.cache_copies 0 # number of cache copies performed 226system.cpu.icache.ReadReq_mshr_misses::cpu.inst 793650 # number of ReadReq MSHR misses 227system.cpu.icache.ReadReq_mshr_misses::total 793650 # number of ReadReq MSHR misses 228system.cpu.icache.demand_mshr_misses::cpu.inst 793650 # number of demand (read+write) MSHR misses 229system.cpu.icache.demand_mshr_misses::total 793650 # number of demand (read+write) MSHR misses 230system.cpu.icache.overall_mshr_misses::cpu.inst 793650 # number of overall MSHR misses 231system.cpu.icache.overall_mshr_misses::total 793650 # number of overall MSHR misses 232system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9273362000 # number of ReadReq MSHR miss cycles 233system.cpu.icache.ReadReq_mshr_miss_latency::total 9273362000 # number of ReadReq MSHR miss cycles 234system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9273362000 # number of demand (read+write) MSHR miss cycles 235system.cpu.icache.demand_mshr_miss_latency::total 9273362000 # number of demand (read+write) MSHR miss cycles 236system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9273362000 # number of overall MSHR miss cycles 237system.cpu.icache.overall_mshr_miss_latency::total 9273362000 # number of overall MSHR miss cycles 238system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005463 # mshr miss rate for ReadReq accesses 239system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005463 # mshr miss rate for ReadReq accesses 240system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005463 # mshr miss rate for demand accesses 241system.cpu.icache.demand_mshr_miss_rate::total 0.005463 # mshr miss rate for demand accesses 242system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005463 # mshr miss rate for overall accesses 243system.cpu.icache.overall_mshr_miss_rate::total 0.005463 # mshr miss rate for overall accesses 244system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11684.447804 # average ReadReq mshr miss latency 245system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11684.447804 # average ReadReq mshr miss latency 246system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11684.447804 # average overall mshr miss latency 247system.cpu.icache.demand_avg_mshr_miss_latency::total 11684.447804 # average overall mshr miss latency 248system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11684.447804 # average overall mshr miss latency 249system.cpu.icache.overall_avg_mshr_miss_latency::total 11684.447804 # average overall mshr miss latency 250system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 251system.cpu.itb_walker_cache.replacements 3599 # number of replacements 252system.cpu.itb_walker_cache.tagsinuse 3.063919 # Cycle average of tags in use 253system.cpu.itb_walker_cache.total_refs 7874 # Total number of references to valid blocks. 254system.cpu.itb_walker_cache.sampled_refs 3610 # Sample count of references to valid blocks. 255system.cpu.itb_walker_cache.avg_refs 2.181163 # Average number of references to valid blocks. 256system.cpu.itb_walker_cache.warmup_cycle 5162043257000 # Cycle when the warmup percentage was hit. 257system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.063919 # Average occupied blocks per requestor 258system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.191495 # Average percentage of cache occupancy 259system.cpu.itb_walker_cache.occ_percent::total 0.191495 # Average percentage of cache occupancy 260system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7876 # number of ReadReq hits 261system.cpu.itb_walker_cache.ReadReq_hits::total 7876 # number of ReadReq hits 262system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 263system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits 264system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7878 # number of demand (read+write) hits 265system.cpu.itb_walker_cache.demand_hits::total 7878 # number of demand (read+write) hits 266system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7878 # number of overall hits 267system.cpu.itb_walker_cache.overall_hits::total 7878 # number of overall hits 268system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4455 # number of ReadReq misses 269system.cpu.itb_walker_cache.ReadReq_misses::total 4455 # number of ReadReq misses 270system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4455 # number of demand (read+write) misses 271system.cpu.itb_walker_cache.demand_misses::total 4455 # number of demand (read+write) misses 272system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4455 # number of overall misses 273system.cpu.itb_walker_cache.overall_misses::total 4455 # number of overall misses 274system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 43455000 # number of ReadReq miss cycles 275system.cpu.itb_walker_cache.ReadReq_miss_latency::total 43455000 # number of ReadReq miss cycles 276system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 43455000 # number of demand (read+write) miss cycles 277system.cpu.itb_walker_cache.demand_miss_latency::total 43455000 # number of demand (read+write) miss cycles 278system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 43455000 # number of overall miss cycles 279system.cpu.itb_walker_cache.overall_miss_latency::total 43455000 # number of overall miss cycles 280system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12331 # number of ReadReq accesses(hits+misses) 281system.cpu.itb_walker_cache.ReadReq_accesses::total 12331 # number of ReadReq accesses(hits+misses) 282system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 283system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) 284system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12333 # number of demand (read+write) accesses 285system.cpu.itb_walker_cache.demand_accesses::total 12333 # number of demand (read+write) accesses 286system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12333 # number of overall (read+write) accesses 287system.cpu.itb_walker_cache.overall_accesses::total 12333 # number of overall (read+write) accesses 288system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.361285 # miss rate for ReadReq accesses 289system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.361285 # miss rate for ReadReq accesses 290system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.361226 # miss rate for demand accesses 291system.cpu.itb_walker_cache.demand_miss_rate::total 0.361226 # miss rate for demand accesses 292system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.361226 # miss rate for overall accesses 293system.cpu.itb_walker_cache.overall_miss_rate::total 0.361226 # miss rate for overall accesses 294system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9754.208754 # average ReadReq miss latency 295system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9754.208754 # average ReadReq miss latency 296system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9754.208754 # average overall miss latency 297system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9754.208754 # average overall miss latency 298system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9754.208754 # average overall miss latency 299system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9754.208754 # average overall miss latency 300system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 301system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 302system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 303system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 304system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 305system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 306system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 307system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed 308system.cpu.itb_walker_cache.writebacks::writebacks 700 # number of writebacks 309system.cpu.itb_walker_cache.writebacks::total 700 # number of writebacks 310system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4455 # number of ReadReq MSHR misses 311system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4455 # number of ReadReq MSHR misses 312system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4455 # number of demand (read+write) MSHR misses 313system.cpu.itb_walker_cache.demand_mshr_misses::total 4455 # number of demand (read+write) MSHR misses 314system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4455 # number of overall MSHR misses 315system.cpu.itb_walker_cache.overall_mshr_misses::total 4455 # number of overall MSHR misses 316system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 34545000 # number of ReadReq MSHR miss cycles 317system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 34545000 # number of ReadReq MSHR miss cycles 318system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 34545000 # number of demand (read+write) MSHR miss cycles 319system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 34545000 # number of demand (read+write) MSHR miss cycles 320system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 34545000 # number of overall MSHR miss cycles 321system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 34545000 # number of overall MSHR miss cycles 322system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.361285 # mshr miss rate for ReadReq accesses 323system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.361285 # mshr miss rate for ReadReq accesses 324system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.361226 # mshr miss rate for demand accesses 325system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.361226 # mshr miss rate for demand accesses 326system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.361226 # mshr miss rate for overall accesses 327system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.361226 # mshr miss rate for overall accesses 328system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 7754.208754 # average ReadReq mshr miss latency 329system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 7754.208754 # average ReadReq mshr miss latency 330system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 7754.208754 # average overall mshr miss latency 331system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7754.208754 # average overall mshr miss latency 332system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7754.208754 # average overall mshr miss latency 333system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7754.208754 # average overall mshr miss latency 334system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 335system.cpu.dtb_walker_cache.replacements 7423 # number of replacements 336system.cpu.dtb_walker_cache.tagsinuse 5.046109 # Cycle average of tags in use 337system.cpu.dtb_walker_cache.total_refs 13594 # Total number of references to valid blocks. 338system.cpu.dtb_walker_cache.sampled_refs 7438 # Sample count of references to valid blocks. 339system.cpu.dtb_walker_cache.avg_refs 1.827642 # Average number of references to valid blocks. 340system.cpu.dtb_walker_cache.warmup_cycle 5159593477000 # Cycle when the warmup percentage was hit. 341system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.046109 # Average occupied blocks per requestor 342system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.315382 # Average percentage of cache occupancy 343system.cpu.dtb_walker_cache.occ_percent::total 0.315382 # Average percentage of cache occupancy 344system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13598 # number of ReadReq hits 345system.cpu.dtb_walker_cache.ReadReq_hits::total 13598 # number of ReadReq hits 346system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13598 # number of demand (read+write) hits 347system.cpu.dtb_walker_cache.demand_hits::total 13598 # number of demand (read+write) hits 348system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13598 # number of overall hits 349system.cpu.dtb_walker_cache.overall_hits::total 13598 # number of overall hits 350system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8635 # number of ReadReq misses 351system.cpu.dtb_walker_cache.ReadReq_misses::total 8635 # number of ReadReq misses 352system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8635 # number of demand (read+write) misses 353system.cpu.dtb_walker_cache.demand_misses::total 8635 # number of demand (read+write) misses 354system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8635 # number of overall misses 355system.cpu.dtb_walker_cache.overall_misses::total 8635 # number of overall misses 356system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 91582000 # number of ReadReq miss cycles 357system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 91582000 # number of ReadReq miss cycles 358system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 91582000 # number of demand (read+write) miss cycles 359system.cpu.dtb_walker_cache.demand_miss_latency::total 91582000 # number of demand (read+write) miss cycles 360system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 91582000 # number of overall miss cycles 361system.cpu.dtb_walker_cache.overall_miss_latency::total 91582000 # number of overall miss cycles 362system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22233 # number of ReadReq accesses(hits+misses) 363system.cpu.dtb_walker_cache.ReadReq_accesses::total 22233 # number of ReadReq accesses(hits+misses) 364system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22233 # number of demand (read+write) accesses 365system.cpu.dtb_walker_cache.demand_accesses::total 22233 # number of demand (read+write) accesses 366system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22233 # number of overall (read+write) accesses 367system.cpu.dtb_walker_cache.overall_accesses::total 22233 # number of overall (read+write) accesses 368system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.388387 # miss rate for ReadReq accesses 369system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.388387 # miss rate for ReadReq accesses 370system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.388387 # miss rate for demand accesses 371system.cpu.dtb_walker_cache.demand_miss_rate::total 0.388387 # miss rate for demand accesses 372system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.388387 # miss rate for overall accesses 373system.cpu.dtb_walker_cache.overall_miss_rate::total 0.388387 # miss rate for overall accesses 374system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10605.906196 # average ReadReq miss latency 375system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10605.906196 # average ReadReq miss latency 376system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10605.906196 # average overall miss latency 377system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10605.906196 # average overall miss latency 378system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10605.906196 # average overall miss latency 379system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10605.906196 # average overall miss latency 380system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 381system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 382system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 383system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 384system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 385system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 386system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 387system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed 388system.cpu.dtb_walker_cache.writebacks::writebacks 2904 # number of writebacks 389system.cpu.dtb_walker_cache.writebacks::total 2904 # number of writebacks 390system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8635 # number of ReadReq MSHR misses 391system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8635 # number of ReadReq MSHR misses 392system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8635 # number of demand (read+write) MSHR misses 393system.cpu.dtb_walker_cache.demand_mshr_misses::total 8635 # number of demand (read+write) MSHR misses 394system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8635 # number of overall MSHR misses 395system.cpu.dtb_walker_cache.overall_mshr_misses::total 8635 # number of overall MSHR misses 396system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 74312000 # number of ReadReq MSHR miss cycles 397system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 74312000 # number of ReadReq MSHR miss cycles 398system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 74312000 # number of demand (read+write) MSHR miss cycles 399system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 74312000 # number of demand (read+write) MSHR miss cycles 400system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 74312000 # number of overall MSHR miss cycles 401system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 74312000 # number of overall MSHR miss cycles 402system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.388387 # mshr miss rate for ReadReq accesses 403system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.388387 # mshr miss rate for ReadReq accesses 404system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.388387 # mshr miss rate for demand accesses 405system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.388387 # mshr miss rate for demand accesses 406system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.388387 # mshr miss rate for overall accesses 407system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.388387 # mshr miss rate for overall accesses 408system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8605.906196 # average ReadReq mshr miss latency 409system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8605.906196 # average ReadReq mshr miss latency 410system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8605.906196 # average overall mshr miss latency 411system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8605.906196 # average overall mshr miss latency 412system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8605.906196 # average overall mshr miss latency 413system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8605.906196 # average overall mshr miss latency 414system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 415system.cpu.dcache.replacements 1618325 # number of replacements 416system.cpu.dcache.tagsinuse 511.997377 # Cycle average of tags in use 417system.cpu.dcache.total_refs 20032981 # Total number of references to valid blocks. 418system.cpu.dcache.sampled_refs 1618837 # Sample count of references to valid blocks. 419system.cpu.dcache.avg_refs 12.374922 # Average number of references to valid blocks. 420system.cpu.dcache.warmup_cycle 43788000 # Cycle when the warmup percentage was hit. 421system.cpu.dcache.occ_blocks::cpu.data 511.997377 # Average occupied blocks per requestor 422system.cpu.dcache.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy 423system.cpu.dcache.occ_percent::total 0.999995 # Average percentage of cache occupancy 424system.cpu.dcache.ReadReq_hits::cpu.data 11992560 # number of ReadReq hits 425system.cpu.dcache.ReadReq_hits::total 11992560 # number of ReadReq hits 426system.cpu.dcache.WriteReq_hits::cpu.data 8038236 # number of WriteReq hits 427system.cpu.dcache.WriteReq_hits::total 8038236 # number of WriteReq hits 428system.cpu.dcache.demand_hits::cpu.data 20030796 # number of demand (read+write) hits 429system.cpu.dcache.demand_hits::total 20030796 # number of demand (read+write) hits 430system.cpu.dcache.overall_hits::cpu.data 20030796 # number of overall hits 431system.cpu.dcache.overall_hits::total 20030796 # number of overall hits 432system.cpu.dcache.ReadReq_misses::cpu.data 1306270 # number of ReadReq misses 433system.cpu.dcache.ReadReq_misses::total 1306270 # number of ReadReq misses 434system.cpu.dcache.WriteReq_misses::cpu.data 314797 # number of WriteReq misses 435system.cpu.dcache.WriteReq_misses::total 314797 # number of WriteReq misses 436system.cpu.dcache.demand_misses::cpu.data 1621067 # number of demand (read+write) misses 437system.cpu.dcache.demand_misses::total 1621067 # number of demand (read+write) misses 438system.cpu.dcache.overall_misses::cpu.data 1621067 # number of overall misses 439system.cpu.dcache.overall_misses::total 1621067 # number of overall misses 440system.cpu.dcache.ReadReq_miss_latency::cpu.data 18175236500 # number of ReadReq miss cycles 441system.cpu.dcache.ReadReq_miss_latency::total 18175236500 # number of ReadReq miss cycles 442system.cpu.dcache.WriteReq_miss_latency::cpu.data 8903442500 # number of WriteReq miss cycles 443system.cpu.dcache.WriteReq_miss_latency::total 8903442500 # number of WriteReq miss cycles 444system.cpu.dcache.demand_miss_latency::cpu.data 27078679000 # number of demand (read+write) miss cycles 445system.cpu.dcache.demand_miss_latency::total 27078679000 # number of demand (read+write) miss cycles 446system.cpu.dcache.overall_miss_latency::cpu.data 27078679000 # number of overall miss cycles 447system.cpu.dcache.overall_miss_latency::total 27078679000 # number of overall miss cycles 448system.cpu.dcache.ReadReq_accesses::cpu.data 13298830 # number of ReadReq accesses(hits+misses) 449system.cpu.dcache.ReadReq_accesses::total 13298830 # number of ReadReq accesses(hits+misses) 450system.cpu.dcache.WriteReq_accesses::cpu.data 8353033 # number of WriteReq accesses(hits+misses) 451system.cpu.dcache.WriteReq_accesses::total 8353033 # number of WriteReq accesses(hits+misses) 452system.cpu.dcache.demand_accesses::cpu.data 21651863 # number of demand (read+write) accesses 453system.cpu.dcache.demand_accesses::total 21651863 # number of demand (read+write) accesses 454system.cpu.dcache.overall_accesses::cpu.data 21651863 # number of overall (read+write) accesses 455system.cpu.dcache.overall_accesses::total 21651863 # number of overall (read+write) accesses 456system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098224 # miss rate for ReadReq accesses 457system.cpu.dcache.ReadReq_miss_rate::total 0.098224 # miss rate for ReadReq accesses 458system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037687 # miss rate for WriteReq accesses 459system.cpu.dcache.WriteReq_miss_rate::total 0.037687 # miss rate for WriteReq accesses 460system.cpu.dcache.demand_miss_rate::cpu.data 0.074870 # miss rate for demand accesses 461system.cpu.dcache.demand_miss_rate::total 0.074870 # miss rate for demand accesses 462system.cpu.dcache.overall_miss_rate::cpu.data 0.074870 # miss rate for overall accesses 463system.cpu.dcache.overall_miss_rate::total 0.074870 # miss rate for overall accesses 464system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13913.843616 # average ReadReq miss latency 465system.cpu.dcache.ReadReq_avg_miss_latency::total 13913.843616 # average ReadReq miss latency 466system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28283.123727 # average WriteReq miss latency 467system.cpu.dcache.WriteReq_avg_miss_latency::total 28283.123727 # average WriteReq miss latency 468system.cpu.dcache.demand_avg_miss_latency::cpu.data 16704.231842 # average overall miss latency 469system.cpu.dcache.demand_avg_miss_latency::total 16704.231842 # average overall miss latency 470system.cpu.dcache.overall_avg_miss_latency::cpu.data 16704.231842 # average overall miss latency 471system.cpu.dcache.overall_avg_miss_latency::total 16704.231842 # average overall miss latency 472system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 473system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 474system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 475system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 476system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 477system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 478system.cpu.dcache.fast_writes 0 # number of fast writes performed 479system.cpu.dcache.cache_copies 0 # number of cache copies performed 480system.cpu.dcache.writebacks::writebacks 1535863 # number of writebacks 481system.cpu.dcache.writebacks::total 1535863 # number of writebacks 482system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1306270 # number of ReadReq MSHR misses 483system.cpu.dcache.ReadReq_mshr_misses::total 1306270 # number of ReadReq MSHR misses 484system.cpu.dcache.WriteReq_mshr_misses::cpu.data 314797 # number of WriteReq MSHR misses 485system.cpu.dcache.WriteReq_mshr_misses::total 314797 # number of WriteReq MSHR misses 486system.cpu.dcache.demand_mshr_misses::cpu.data 1621067 # number of demand (read+write) MSHR misses 487system.cpu.dcache.demand_mshr_misses::total 1621067 # number of demand (read+write) MSHR misses 488system.cpu.dcache.overall_mshr_misses::cpu.data 1621067 # number of overall MSHR misses 489system.cpu.dcache.overall_mshr_misses::total 1621067 # number of overall MSHR misses 490system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15562696500 # number of ReadReq MSHR miss cycles 491system.cpu.dcache.ReadReq_mshr_miss_latency::total 15562696500 # number of ReadReq MSHR miss cycles 492system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8273848500 # number of WriteReq MSHR miss cycles 493system.cpu.dcache.WriteReq_mshr_miss_latency::total 8273848500 # number of WriteReq MSHR miss cycles 494system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23836545000 # number of demand (read+write) MSHR miss cycles 495system.cpu.dcache.demand_mshr_miss_latency::total 23836545000 # number of demand (read+write) MSHR miss cycles 496system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23836545000 # number of overall MSHR miss cycles 497system.cpu.dcache.overall_mshr_miss_latency::total 23836545000 # number of overall MSHR miss cycles 498system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94146954000 # number of ReadReq MSHR uncacheable cycles 499system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94146954000 # number of ReadReq MSHR uncacheable cycles 500system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2469435000 # number of WriteReq MSHR uncacheable cycles 501system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2469435000 # number of WriteReq MSHR uncacheable cycles 502system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96616389000 # number of overall MSHR uncacheable cycles 503system.cpu.dcache.overall_mshr_uncacheable_latency::total 96616389000 # number of overall MSHR uncacheable cycles 504system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098224 # mshr miss rate for ReadReq accesses 505system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098224 # mshr miss rate for ReadReq accesses 506system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037687 # mshr miss rate for WriteReq accesses 507system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037687 # mshr miss rate for WriteReq accesses 508system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074870 # mshr miss rate for demand accesses 509system.cpu.dcache.demand_mshr_miss_rate::total 0.074870 # mshr miss rate for demand accesses 510system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074870 # mshr miss rate for overall accesses 511system.cpu.dcache.overall_mshr_miss_rate::total 0.074870 # mshr miss rate for overall accesses 512system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11913.843616 # average ReadReq mshr miss latency 513system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11913.843616 # average ReadReq mshr miss latency 514system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26283.123727 # average WriteReq mshr miss latency 515system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26283.123727 # average WriteReq mshr miss latency 516system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14704.231842 # average overall mshr miss latency 517system.cpu.dcache.demand_avg_mshr_miss_latency::total 14704.231842 # average overall mshr miss latency 518system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14704.231842 # average overall mshr miss latency 519system.cpu.dcache.overall_avg_mshr_miss_latency::total 14704.231842 # average overall mshr miss latency 520system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 521system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 522system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 523system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 524system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 525system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 526system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 527system.cpu.l2cache.replacements 86829 # number of replacements 528system.cpu.l2cache.tagsinuse 64762.717222 # Cycle average of tags in use 529system.cpu.l2cache.total_refs 3488042 # Total number of references to valid blocks. 530system.cpu.l2cache.sampled_refs 151520 # Sample count of references to valid blocks. 531system.cpu.l2cache.avg_refs 23.020341 # Average number of references to valid blocks. 532system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 533system.cpu.l2cache.occ_blocks::writebacks 50387.154618 # Average occupied blocks per requestor 534system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.140509 # Average occupied blocks per requestor 535system.cpu.l2cache.occ_blocks::cpu.inst 3354.597125 # Average occupied blocks per requestor 536system.cpu.l2cache.occ_blocks::cpu.data 11020.824971 # Average occupied blocks per requestor 537system.cpu.l2cache.occ_percent::writebacks 0.768847 # Average percentage of cache occupancy 538system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy 539system.cpu.l2cache.occ_percent::cpu.inst 0.051187 # Average percentage of cache occupancy 540system.cpu.l2cache.occ_percent::cpu.data 0.168164 # Average percentage of cache occupancy 541system.cpu.l2cache.occ_percent::total 0.988201 # Average percentage of cache occupancy 542system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6338 # number of ReadReq hits 543system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2820 # number of ReadReq hits 544system.cpu.l2cache.ReadReq_hits::cpu.inst 780715 # number of ReadReq hits 545system.cpu.l2cache.ReadReq_hits::cpu.data 1277261 # number of ReadReq hits 546system.cpu.l2cache.ReadReq_hits::total 2067134 # number of ReadReq hits 547system.cpu.l2cache.Writeback_hits::writebacks 1539467 # number of Writeback hits 548system.cpu.l2cache.Writeback_hits::total 1539467 # number of Writeback hits 549system.cpu.l2cache.UpgradeReq_hits::cpu.data 313 # number of UpgradeReq hits 550system.cpu.l2cache.UpgradeReq_hits::total 313 # number of UpgradeReq hits 551system.cpu.l2cache.ReadExReq_hits::cpu.data 199347 # number of ReadExReq hits 552system.cpu.l2cache.ReadExReq_hits::total 199347 # number of ReadExReq hits 553system.cpu.l2cache.demand_hits::cpu.dtb.walker 6338 # number of demand (read+write) hits 554system.cpu.l2cache.demand_hits::cpu.itb.walker 2820 # number of demand (read+write) hits 555system.cpu.l2cache.demand_hits::cpu.inst 780715 # number of demand (read+write) hits 556system.cpu.l2cache.demand_hits::cpu.data 1476608 # number of demand (read+write) hits 557system.cpu.l2cache.demand_hits::total 2266481 # number of demand (read+write) hits 558system.cpu.l2cache.overall_hits::cpu.dtb.walker 6338 # number of overall hits 559system.cpu.l2cache.overall_hits::cpu.itb.walker 2820 # number of overall hits 560system.cpu.l2cache.overall_hits::cpu.inst 780715 # number of overall hits 561system.cpu.l2cache.overall_hits::cpu.data 1476608 # number of overall hits 562system.cpu.l2cache.overall_hits::total 2266481 # number of overall hits 563system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses 564system.cpu.l2cache.ReadReq_misses::cpu.inst 12922 # number of ReadReq misses 565system.cpu.l2cache.ReadReq_misses::cpu.data 28238 # number of ReadReq misses 566system.cpu.l2cache.ReadReq_misses::total 41165 # number of ReadReq misses 567system.cpu.l2cache.UpgradeReq_misses::cpu.data 1345 # number of UpgradeReq misses 568system.cpu.l2cache.UpgradeReq_misses::total 1345 # number of UpgradeReq misses 569system.cpu.l2cache.ReadExReq_misses::cpu.data 113260 # number of ReadExReq misses 570system.cpu.l2cache.ReadExReq_misses::total 113260 # number of ReadExReq misses 571system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses 572system.cpu.l2cache.demand_misses::cpu.inst 12922 # number of demand (read+write) misses 573system.cpu.l2cache.demand_misses::cpu.data 141498 # number of demand (read+write) misses 574system.cpu.l2cache.demand_misses::total 154425 # number of demand (read+write) misses 575system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses 576system.cpu.l2cache.overall_misses::cpu.inst 12922 # number of overall misses 577system.cpu.l2cache.overall_misses::cpu.data 141498 # number of overall misses 578system.cpu.l2cache.overall_misses::total 154425 # number of overall misses 579system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 260000 # number of ReadReq miss cycles 580system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 672549000 # number of ReadReq miss cycles 581system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1483044000 # number of ReadReq miss cycles 582system.cpu.l2cache.ReadReq_miss_latency::total 2155853000 # number of ReadReq miss cycles 583system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 33608000 # number of UpgradeReq miss cycles 584system.cpu.l2cache.UpgradeReq_miss_latency::total 33608000 # number of UpgradeReq miss cycles 585system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5892280500 # number of ReadExReq miss cycles 586system.cpu.l2cache.ReadExReq_miss_latency::total 5892280500 # number of ReadExReq miss cycles 587system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 260000 # number of demand (read+write) miss cycles 588system.cpu.l2cache.demand_miss_latency::cpu.inst 672549000 # number of demand (read+write) miss cycles 589system.cpu.l2cache.demand_miss_latency::cpu.data 7375324500 # number of demand (read+write) miss cycles 590system.cpu.l2cache.demand_miss_latency::total 8048133500 # number of demand (read+write) miss cycles 591system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 260000 # number of overall miss cycles 592system.cpu.l2cache.overall_miss_latency::cpu.inst 672549000 # number of overall miss cycles 593system.cpu.l2cache.overall_miss_latency::cpu.data 7375324500 # number of overall miss cycles 594system.cpu.l2cache.overall_miss_latency::total 8048133500 # number of overall miss cycles 595system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6338 # number of ReadReq accesses(hits+misses) 596system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2825 # number of ReadReq accesses(hits+misses) 597system.cpu.l2cache.ReadReq_accesses::cpu.inst 793637 # number of ReadReq accesses(hits+misses) 598system.cpu.l2cache.ReadReq_accesses::cpu.data 1305499 # number of ReadReq accesses(hits+misses) 599system.cpu.l2cache.ReadReq_accesses::total 2108299 # number of ReadReq accesses(hits+misses) 600system.cpu.l2cache.Writeback_accesses::writebacks 1539467 # number of Writeback accesses(hits+misses) 601system.cpu.l2cache.Writeback_accesses::total 1539467 # number of Writeback accesses(hits+misses) 602system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1658 # number of UpgradeReq accesses(hits+misses) 603system.cpu.l2cache.UpgradeReq_accesses::total 1658 # number of UpgradeReq accesses(hits+misses) 604system.cpu.l2cache.ReadExReq_accesses::cpu.data 312607 # number of ReadExReq accesses(hits+misses) 605system.cpu.l2cache.ReadExReq_accesses::total 312607 # number of ReadExReq accesses(hits+misses) 606system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6338 # number of demand (read+write) accesses 607system.cpu.l2cache.demand_accesses::cpu.itb.walker 2825 # number of demand (read+write) accesses 608system.cpu.l2cache.demand_accesses::cpu.inst 793637 # number of demand (read+write) accesses 609system.cpu.l2cache.demand_accesses::cpu.data 1618106 # number of demand (read+write) accesses 610system.cpu.l2cache.demand_accesses::total 2420906 # number of demand (read+write) accesses 611system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6338 # number of overall (read+write) accesses 612system.cpu.l2cache.overall_accesses::cpu.itb.walker 2825 # number of overall (read+write) accesses 613system.cpu.l2cache.overall_accesses::cpu.inst 793637 # number of overall (read+write) accesses 614system.cpu.l2cache.overall_accesses::cpu.data 1618106 # number of overall (read+write) accesses 615system.cpu.l2cache.overall_accesses::total 2420906 # number of overall (read+write) accesses 616system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001770 # miss rate for ReadReq accesses 617system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016282 # miss rate for ReadReq accesses 618system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021630 # miss rate for ReadReq accesses 619system.cpu.l2cache.ReadReq_miss_rate::total 0.019525 # miss rate for ReadReq accesses 620system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.811218 # miss rate for UpgradeReq accesses 621system.cpu.l2cache.UpgradeReq_miss_rate::total 0.811218 # miss rate for UpgradeReq accesses 622system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.362308 # miss rate for ReadExReq accesses 623system.cpu.l2cache.ReadExReq_miss_rate::total 0.362308 # miss rate for ReadExReq accesses 624system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001770 # miss rate for demand accesses 625system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016282 # miss rate for demand accesses 626system.cpu.l2cache.demand_miss_rate::cpu.data 0.087447 # miss rate for demand accesses 627system.cpu.l2cache.demand_miss_rate::total 0.063788 # miss rate for demand accesses 628system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001770 # miss rate for overall accesses 629system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016282 # miss rate for overall accesses 630system.cpu.l2cache.overall_miss_rate::cpu.data 0.087447 # miss rate for overall accesses 631system.cpu.l2cache.overall_miss_rate::total 0.063788 # miss rate for overall accesses 632system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency 633system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52046.819378 # average ReadReq miss latency 634system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52519.441887 # average ReadReq miss latency 635system.cpu.l2cache.ReadReq_avg_miss_latency::total 52371.019070 # average ReadReq miss latency 636system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 24987.360595 # average UpgradeReq miss latency 637system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 24987.360595 # average UpgradeReq miss latency 638system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52024.373124 # average ReadExReq miss latency 639system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52024.373124 # average ReadExReq miss latency 640system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency 641system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52046.819378 # average overall miss latency 642system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52123.171352 # average overall miss latency 643system.cpu.l2cache.demand_avg_miss_latency::total 52116.778371 # average overall miss latency 644system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency 645system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52046.819378 # average overall miss latency 646system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52123.171352 # average overall miss latency 647system.cpu.l2cache.overall_avg_miss_latency::total 52116.778371 # average overall miss latency 648system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 649system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 650system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 651system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 652system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 653system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 654system.cpu.l2cache.fast_writes 0 # number of fast writes performed 655system.cpu.l2cache.cache_copies 0 # number of cache copies performed 656system.cpu.l2cache.writebacks::writebacks 80008 # number of writebacks 657system.cpu.l2cache.writebacks::total 80008 # number of writebacks 658system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses 659system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12922 # number of ReadReq MSHR misses 660system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28238 # number of ReadReq MSHR misses 661system.cpu.l2cache.ReadReq_mshr_misses::total 41165 # number of ReadReq MSHR misses 662system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1345 # number of UpgradeReq MSHR misses 663system.cpu.l2cache.UpgradeReq_mshr_misses::total 1345 # number of UpgradeReq MSHR misses 664system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 113260 # number of ReadExReq MSHR misses 665system.cpu.l2cache.ReadExReq_mshr_misses::total 113260 # number of ReadExReq MSHR misses 666system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses 667system.cpu.l2cache.demand_mshr_misses::cpu.inst 12922 # number of demand (read+write) MSHR misses 668system.cpu.l2cache.demand_mshr_misses::cpu.data 141498 # number of demand (read+write) MSHR misses 669system.cpu.l2cache.demand_mshr_misses::total 154425 # number of demand (read+write) MSHR misses 670system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses 671system.cpu.l2cache.overall_mshr_misses::cpu.inst 12922 # number of overall MSHR misses 672system.cpu.l2cache.overall_mshr_misses::cpu.data 141498 # number of overall MSHR misses 673system.cpu.l2cache.overall_mshr_misses::total 154425 # number of overall MSHR misses 674system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 200000 # number of ReadReq MSHR miss cycles 675system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 517329000 # number of ReadReq MSHR miss cycles 676system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1144074500 # number of ReadReq MSHR miss cycles 677system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1661603500 # number of ReadReq MSHR miss cycles 678system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 54186500 # number of UpgradeReq MSHR miss cycles 679system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 54186500 # number of UpgradeReq MSHR miss cycles 680system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4533030500 # number of ReadExReq MSHR miss cycles 681system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4533030500 # number of ReadExReq MSHR miss cycles 682system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 200000 # number of demand (read+write) MSHR miss cycles 683system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 517329000 # number of demand (read+write) MSHR miss cycles 684system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5677105000 # number of demand (read+write) MSHR miss cycles 685system.cpu.l2cache.demand_mshr_miss_latency::total 6194634000 # number of demand (read+write) MSHR miss cycles 686system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 200000 # number of overall MSHR miss cycles 687system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 517329000 # number of overall MSHR miss cycles 688system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5677105000 # number of overall MSHR miss cycles 689system.cpu.l2cache.overall_mshr_miss_latency::total 6194634000 # number of overall MSHR miss cycles 690system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86587561000 # number of ReadReq MSHR uncacheable cycles 691system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86587561000 # number of ReadReq MSHR uncacheable cycles 692system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2305699000 # number of WriteReq MSHR uncacheable cycles 693system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2305699000 # number of WriteReq MSHR uncacheable cycles 694system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 88893260000 # number of overall MSHR uncacheable cycles 695system.cpu.l2cache.overall_mshr_uncacheable_latency::total 88893260000 # number of overall MSHR uncacheable cycles 696system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001770 # mshr miss rate for ReadReq accesses 697system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016282 # mshr miss rate for ReadReq accesses 698system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021630 # mshr miss rate for ReadReq accesses 699system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019525 # mshr miss rate for ReadReq accesses 700system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.811218 # mshr miss rate for UpgradeReq accesses 701system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.811218 # mshr miss rate for UpgradeReq accesses 702system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.362308 # mshr miss rate for ReadExReq accesses 703system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.362308 # mshr miss rate for ReadExReq accesses 704system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001770 # mshr miss rate for demand accesses 705system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016282 # mshr miss rate for demand accesses 706system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087447 # mshr miss rate for demand accesses 707system.cpu.l2cache.demand_mshr_miss_rate::total 0.063788 # mshr miss rate for demand accesses 708system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001770 # mshr miss rate for overall accesses 709system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016282 # mshr miss rate for overall accesses 710system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087447 # mshr miss rate for overall accesses 711system.cpu.l2cache.overall_mshr_miss_rate::total 0.063788 # mshr miss rate for overall accesses 712system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency 713system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40034.746943 # average ReadReq mshr miss latency 714system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40515.422480 # average ReadReq mshr miss latency 715system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40364.472246 # average ReadReq mshr miss latency 716system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40287.360595 # average UpgradeReq mshr miss latency 717system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40287.360595 # average UpgradeReq mshr miss latency 718system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40023.225322 # average ReadExReq mshr miss latency 719system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40023.225322 # average ReadExReq mshr miss latency 720system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency 721system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40034.746943 # average overall mshr miss latency 722system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40121.450480 # average overall mshr miss latency 723system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40114.191355 # average overall mshr miss latency 724system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency 725system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40034.746943 # average overall mshr miss latency 726system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40121.450480 # average overall mshr miss latency 727system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40114.191355 # average overall mshr miss latency 728system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 729system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 730system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 731system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 732system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 733system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 734system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 735 736---------- End Simulation Statistics ---------- 737