stats.txt revision 10892:bd37e25fb3b7
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.184733 # Number of seconds simulated 4sim_ticks 5184732721500 # Number of ticks simulated 5final_tick 5184732721500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 808289 # Simulator instruction rate (inst/s) 8host_op_rate 1558079 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 32570584041 # Simulator tick rate (ticks/s) 10host_mem_usage 654268 # Number of bytes of host memory used 11host_seconds 159.18 # Real time elapsed on the host 12sim_insts 128667033 # Number of instructions simulated 13sim_ops 248022101 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.inst 825344 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 9044928 # Number of bytes read from this memory 19system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory 20system.physmem.bytes_read::total 9898944 # Number of bytes read from this memory 21system.physmem.bytes_inst_read::cpu.inst 825344 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 825344 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 8133056 # Number of bytes written to this memory 24system.physmem.bytes_written::total 8133056 # Number of bytes written to this memory 25system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.inst 12896 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.data 141327 # Number of read requests responded to by this memory 28system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory 29system.physmem.num_reads::total 154671 # Number of read requests responded to by this memory 30system.physmem.num_writes::writebacks 127079 # Number of write requests responded to by this memory 31system.physmem.num_writes::total 127079 # Number of write requests responded to by this memory 32system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::cpu.inst 159187 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::cpu.data 1744531 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::pc.south_bridge.ide 5468 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::total 1909249 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_inst_read::cpu.inst 159187 # Instruction read bandwidth from this memory (bytes/s) 38system.physmem.bw_inst_read::total 159187 # Instruction read bandwidth from this memory (bytes/s) 39system.physmem.bw_write::writebacks 1568655 # Write bandwidth from this memory (bytes/s) 40system.physmem.bw_write::total 1568655 # Write bandwidth from this memory (bytes/s) 41system.physmem.bw_total::writebacks 1568655 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::cpu.inst 159187 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.bw_total::cpu.data 1744531 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::pc.south_bridge.ide 5468 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::total 3477903 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.readReqs 154671 # Number of read requests accepted 48system.physmem.writeReqs 127079 # Number of write requests accepted 49system.physmem.readBursts 154671 # Number of DRAM read bursts, including those serviced by the write queue 50system.physmem.writeBursts 127079 # Number of DRAM write bursts, including those merged in the write queue 51system.physmem.bytesReadDRAM 9888768 # Total number of bytes read from DRAM 52system.physmem.bytesReadWrQ 10176 # Total number of bytes read from write queue 53system.physmem.bytesWritten 8131392 # Total number of bytes written to DRAM 54system.physmem.bytesReadSys 9898944 # Total read bytes from the system interface side 55system.physmem.bytesWrittenSys 8133056 # Total written bytes from the system interface side 56system.physmem.servicedByWrQ 159 # Number of DRAM read bursts serviced by the write queue 57system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 58system.physmem.neitherReadNorWriteReqs 48348 # Number of requests that are neither read nor write 59system.physmem.perBankRdBursts::0 9772 # Per bank write bursts 60system.physmem.perBankRdBursts::1 9412 # Per bank write bursts 61system.physmem.perBankRdBursts::2 9829 # Per bank write bursts 62system.physmem.perBankRdBursts::3 9622 # Per bank write bursts 63system.physmem.perBankRdBursts::4 9563 # Per bank write bursts 64system.physmem.perBankRdBursts::5 9355 # Per bank write bursts 65system.physmem.perBankRdBursts::6 9720 # Per bank write bursts 66system.physmem.perBankRdBursts::7 9664 # Per bank write bursts 67system.physmem.perBankRdBursts::8 9219 # Per bank write bursts 68system.physmem.perBankRdBursts::9 9313 # Per bank write bursts 69system.physmem.perBankRdBursts::10 9431 # Per bank write bursts 70system.physmem.perBankRdBursts::11 9415 # Per bank write bursts 71system.physmem.perBankRdBursts::12 9985 # Per bank write bursts 72system.physmem.perBankRdBursts::13 10194 # Per bank write bursts 73system.physmem.perBankRdBursts::14 10163 # Per bank write bursts 74system.physmem.perBankRdBursts::15 9855 # Per bank write bursts 75system.physmem.perBankWrBursts::0 8316 # Per bank write bursts 76system.physmem.perBankWrBursts::1 7960 # Per bank write bursts 77system.physmem.perBankWrBursts::2 8144 # Per bank write bursts 78system.physmem.perBankWrBursts::3 8236 # Per bank write bursts 79system.physmem.perBankWrBursts::4 8504 # Per bank write bursts 80system.physmem.perBankWrBursts::5 7731 # Per bank write bursts 81system.physmem.perBankWrBursts::6 7974 # Per bank write bursts 82system.physmem.perBankWrBursts::7 7835 # Per bank write bursts 83system.physmem.perBankWrBursts::8 7118 # Per bank write bursts 84system.physmem.perBankWrBursts::9 7555 # Per bank write bursts 85system.physmem.perBankWrBursts::10 7609 # Per bank write bursts 86system.physmem.perBankWrBursts::11 7637 # Per bank write bursts 87system.physmem.perBankWrBursts::12 8092 # Per bank write bursts 88system.physmem.perBankWrBursts::13 8095 # Per bank write bursts 89system.physmem.perBankWrBursts::14 8240 # Per bank write bursts 90system.physmem.perBankWrBursts::15 8007 # Per bank write bursts 91system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 92system.physmem.numWrRetry 3 # Number of times write queue was full causing retry 93system.physmem.totGap 5184732588500 # Total gap between requests 94system.physmem.readPktSize::0 0 # Read request sizes (log2) 95system.physmem.readPktSize::1 0 # Read request sizes (log2) 96system.physmem.readPktSize::2 0 # Read request sizes (log2) 97system.physmem.readPktSize::3 0 # Read request sizes (log2) 98system.physmem.readPktSize::4 0 # Read request sizes (log2) 99system.physmem.readPktSize::5 0 # Read request sizes (log2) 100system.physmem.readPktSize::6 154671 # Read request sizes (log2) 101system.physmem.writePktSize::0 0 # Write request sizes (log2) 102system.physmem.writePktSize::1 0 # Write request sizes (log2) 103system.physmem.writePktSize::2 0 # Write request sizes (log2) 104system.physmem.writePktSize::3 0 # Write request sizes (log2) 105system.physmem.writePktSize::4 0 # Write request sizes (log2) 106system.physmem.writePktSize::5 0 # Write request sizes (log2) 107system.physmem.writePktSize::6 127079 # Write request sizes (log2) 108system.physmem.rdQLenPdf::0 151205 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::1 2887 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::3 48 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::4 40 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::5 33 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::6 31 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::7 35 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::9 30 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::12 25 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::13 25 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 140system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::15 2360 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::16 2863 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::17 6760 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::18 6764 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::19 6407 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::20 6343 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::21 6364 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::22 8198 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::23 8634 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::24 10421 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::25 9012 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::26 8283 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::27 7047 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::28 7628 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::29 7472 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::30 6195 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::31 6206 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::32 6107 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::33 234 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::34 187 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::35 258 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::36 145 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::37 184 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::38 176 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::39 206 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::40 206 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::41 193 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::42 126 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::43 134 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::44 112 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::45 157 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::46 188 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::47 176 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::48 142 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::49 163 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::50 117 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::51 136 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::52 145 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::53 114 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::54 95 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::55 132 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::56 82 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::57 57 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::58 36 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::59 28 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::60 39 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::61 16 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::62 8 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::63 8 # What write queue length does an incoming req see 204system.physmem.bytesPerActivate::samples 55882 # Bytes accessed per row activation 205system.physmem.bytesPerActivate::mean 322.466912 # Bytes accessed per row activation 206system.physmem.bytesPerActivate::gmean 190.971568 # Bytes accessed per row activation 207system.physmem.bytesPerActivate::stdev 335.231986 # Bytes accessed per row activation 208system.physmem.bytesPerActivate::0-127 19566 35.01% 35.01% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::128-255 13855 24.79% 59.81% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::256-383 5752 10.29% 70.10% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::384-511 3280 5.87% 75.97% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::512-639 2436 4.36% 80.33% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::640-767 1597 2.86% 83.19% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::768-895 1106 1.98% 85.17% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::896-1023 958 1.71% 86.88% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::1024-1151 7332 13.12% 100.00% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::total 55882 # Bytes accessed per row activation 218system.physmem.rdPerTurnAround::samples 5902 # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::mean 26.177906 # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::stdev 623.301246 # Reads before turning the bus around for writes 221system.physmem.rdPerTurnAround::0-2047 5901 99.98% 99.98% # Reads before turning the bus around for writes 222system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes 223system.physmem.rdPerTurnAround::total 5902 # Reads before turning the bus around for writes 224system.physmem.wrPerTurnAround::samples 5902 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::mean 21.527109 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::gmean 19.363013 # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::stdev 14.814592 # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::16-19 4841 82.02% 82.02% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::20-23 49 0.83% 82.85% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::24-27 261 4.42% 87.28% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::28-31 70 1.19% 88.46% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::32-35 69 1.17% 89.63% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::36-39 251 4.25% 93.88% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::40-43 22 0.37% 94.26% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::44-47 13 0.22% 94.48% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::48-51 15 0.25% 94.73% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::52-55 5 0.08% 94.82% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::56-59 7 0.12% 94.93% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::60-63 5 0.08% 95.02% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::64-67 235 3.98% 99.00% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::68-71 3 0.05% 99.05% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::72-75 5 0.08% 99.14% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::76-79 8 0.14% 99.27% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::80-83 1 0.02% 99.29% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::92-95 2 0.03% 99.32% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::100-103 2 0.03% 99.36% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::124-127 1 0.02% 99.37% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::128-131 27 0.46% 99.83% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::148-151 2 0.03% 99.86% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::152-155 1 0.02% 99.88% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::160-163 1 0.02% 99.90% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::164-167 3 0.05% 99.95% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::176-179 1 0.02% 99.97% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::200-203 1 0.02% 99.98% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::204-207 1 0.02% 100.00% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::total 5902 # Writes before turning the bus around for reads 257system.physmem.totQLat 1454171981 # Total ticks spent queuing 258system.physmem.totMemAccLat 4351271981 # Total ticks spent from burst creation until serviced by the DRAM 259system.physmem.totBusLat 772560000 # Total ticks spent in databus transfers 260system.physmem.avgQLat 9411.39 # Average queueing delay per DRAM burst 261system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 262system.physmem.avgMemAccLat 28161.39 # Average memory access latency per DRAM burst 263system.physmem.avgRdBW 1.91 # Average DRAM read bandwidth in MiByte/s 264system.physmem.avgWrBW 1.57 # Average achieved write bandwidth in MiByte/s 265system.physmem.avgRdBWSys 1.91 # Average system read bandwidth in MiByte/s 266system.physmem.avgWrBWSys 1.57 # Average system write bandwidth in MiByte/s 267system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 268system.physmem.busUtil 0.03 # Data bus utilization in percentage 269system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 270system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 271system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 272system.physmem.avgWrQLen 24.52 # Average write queue length when enqueuing 273system.physmem.readRowHits 126926 # Number of row buffer hits during reads 274system.physmem.writeRowHits 98756 # Number of row buffer hits during writes 275system.physmem.readRowHitRate 82.15 # Row buffer hit rate for reads 276system.physmem.writeRowHitRate 77.71 # Row buffer hit rate for writes 277system.physmem.avgGap 18401890.29 # Average gap between requests 278system.physmem.pageHitRate 80.15 # Row buffer hit rate, read and write combined 279system.physmem_0.actEnergy 207522000 # Energy for activate commands per rank (pJ) 280system.physmem_0.preEnergy 113231250 # Energy for precharge commands per rank (pJ) 281system.physmem_0.readEnergy 600100800 # Energy for read commands per rank (pJ) 282system.physmem_0.writeEnergy 419256000 # Energy for write commands per rank (pJ) 283system.physmem_0.refreshEnergy 338641458480 # Energy for refresh commands per rank (pJ) 284system.physmem_0.actBackEnergy 134001495225 # Energy for active background per rank (pJ) 285system.physmem_0.preBackEnergy 2993293881750 # Energy for precharge background per rank (pJ) 286system.physmem_0.totalEnergy 3467276945505 # Total energy per rank (pJ) 287system.physmem_0.averagePower 668.747605 # Core power per rank (mW) 288system.physmem_0.memoryStateTime::IDLE 4979520185732 # Time in different power states 289system.physmem_0.memoryStateTime::REF 173129580000 # Time in different power states 290system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 291system.physmem_0.memoryStateTime::ACT 32082834268 # Time in different power states 292system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 293system.physmem_1.actEnergy 214945920 # Energy for activate commands per rank (pJ) 294system.physmem_1.preEnergy 117282000 # Energy for precharge commands per rank (pJ) 295system.physmem_1.readEnergy 605085000 # Energy for read commands per rank (pJ) 296system.physmem_1.writeEnergy 404047440 # Energy for write commands per rank (pJ) 297system.physmem_1.refreshEnergy 338641458480 # Energy for refresh commands per rank (pJ) 298system.physmem_1.actBackEnergy 134530881300 # Energy for active background per rank (pJ) 299system.physmem_1.preBackEnergy 2992829508000 # Energy for precharge background per rank (pJ) 300system.physmem_1.totalEnergy 3467343208140 # Total energy per rank (pJ) 301system.physmem_1.averagePower 668.760386 # Core power per rank (mW) 302system.physmem_1.memoryStateTime::IDLE 4978746411720 # Time in different power states 303system.physmem_1.memoryStateTime::REF 173129580000 # Time in different power states 304system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 305system.physmem_1.memoryStateTime::ACT 32855777030 # Time in different power states 306system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 307system.cpu_clk_domain.clock 500 # Clock period in ticks 308system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 309system.cpu.numCycles 10369465443 # number of cpu cycles simulated 310system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 311system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 312system.cpu.committedInsts 128667033 # Number of instructions committed 313system.cpu.committedOps 248022101 # Number of ops (including micro ops) committed 314system.cpu.num_int_alu_accesses 232599125 # Number of integer alu accesses 315system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses 316system.cpu.num_func_calls 2317363 # number of times a function call or return occured 317system.cpu.num_conditional_control_insts 23194478 # number of instructions that are conditional controls 318system.cpu.num_int_insts 232599125 # number of integer instructions 319system.cpu.num_fp_insts 48 # number of float instructions 320system.cpu.num_int_register_reads 435753384 # number of times the integer registers were read 321system.cpu.num_int_register_writes 198362025 # number of times the integer registers were written 322system.cpu.num_fp_register_reads 48 # number of times the floating registers were read 323system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 324system.cpu.num_cc_register_reads 133133176 # number of times the CC registers were read 325system.cpu.num_cc_register_writes 95670461 # number of times the CC registers were written 326system.cpu.num_mem_refs 22356642 # number of memory refs 327system.cpu.num_load_insts 13946240 # Number of load instructions 328system.cpu.num_store_insts 8410402 # Number of store instructions 329system.cpu.num_idle_cycles 9769457503.998116 # Number of idle cycles 330system.cpu.num_busy_cycles 600007939.001884 # Number of busy cycles 331system.cpu.not_idle_fraction 0.057863 # Percentage of non-idle cycles 332system.cpu.idle_fraction 0.942137 # Percentage of idle cycles 333system.cpu.Branches 26370667 # Number of branches fetched 334system.cpu.op_class::No_OpClass 172538 0.07% 0.07% # Class of executed instruction 335system.cpu.op_class::IntAlu 225235379 90.81% 90.88% # Class of executed instruction 336system.cpu.op_class::IntMult 140393 0.06% 90.94% # Class of executed instruction 337system.cpu.op_class::IntDiv 123647 0.05% 90.99% # Class of executed instruction 338system.cpu.op_class::FloatAdd 0 0.00% 90.99% # Class of executed instruction 339system.cpu.op_class::FloatCmp 0 0.00% 90.99% # Class of executed instruction 340system.cpu.op_class::FloatCvt 16 0.00% 90.99% # Class of executed instruction 341system.cpu.op_class::FloatMult 0 0.00% 90.99% # Class of executed instruction 342system.cpu.op_class::FloatDiv 0 0.00% 90.99% # Class of executed instruction 343system.cpu.op_class::FloatSqrt 0 0.00% 90.99% # Class of executed instruction 344system.cpu.op_class::SimdAdd 0 0.00% 90.99% # Class of executed instruction 345system.cpu.op_class::SimdAddAcc 0 0.00% 90.99% # Class of executed instruction 346system.cpu.op_class::SimdAlu 0 0.00% 90.99% # Class of executed instruction 347system.cpu.op_class::SimdCmp 0 0.00% 90.99% # Class of executed instruction 348system.cpu.op_class::SimdCvt 0 0.00% 90.99% # Class of executed instruction 349system.cpu.op_class::SimdMisc 0 0.00% 90.99% # Class of executed instruction 350system.cpu.op_class::SimdMult 0 0.00% 90.99% # Class of executed instruction 351system.cpu.op_class::SimdMultAcc 0 0.00% 90.99% # Class of executed instruction 352system.cpu.op_class::SimdShift 0 0.00% 90.99% # Class of executed instruction 353system.cpu.op_class::SimdShiftAcc 0 0.00% 90.99% # Class of executed instruction 354system.cpu.op_class::SimdSqrt 0 0.00% 90.99% # Class of executed instruction 355system.cpu.op_class::SimdFloatAdd 0 0.00% 90.99% # Class of executed instruction 356system.cpu.op_class::SimdFloatAlu 0 0.00% 90.99% # Class of executed instruction 357system.cpu.op_class::SimdFloatCmp 0 0.00% 90.99% # Class of executed instruction 358system.cpu.op_class::SimdFloatCvt 0 0.00% 90.99% # Class of executed instruction 359system.cpu.op_class::SimdFloatDiv 0 0.00% 90.99% # Class of executed instruction 360system.cpu.op_class::SimdFloatMisc 0 0.00% 90.99% # Class of executed instruction 361system.cpu.op_class::SimdFloatMult 0 0.00% 90.99% # Class of executed instruction 362system.cpu.op_class::SimdFloatMultAcc 0 0.00% 90.99% # Class of executed instruction 363system.cpu.op_class::SimdFloatSqrt 0 0.00% 90.99% # Class of executed instruction 364system.cpu.op_class::MemRead 13941273 5.62% 96.61% # Class of executed instruction 365system.cpu.op_class::MemWrite 8410402 3.39% 100.00% # Class of executed instruction 366system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 367system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 368system.cpu.op_class::total 248023648 # Class of executed instruction 369system.cpu.kern.inst.arm 0 # number of arm instructions executed 370system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 371system.cpu.dcache.tags.replacements 1621027 # number of replacements 372system.cpu.dcache.tags.tagsinuse 511.996962 # Cycle average of tags in use 373system.cpu.dcache.tags.total_refs 20151381 # Total number of references to valid blocks. 374system.cpu.dcache.tags.sampled_refs 1621539 # Sample count of references to valid blocks. 375system.cpu.dcache.tags.avg_refs 12.427318 # Average number of references to valid blocks. 376system.cpu.dcache.tags.warmup_cycle 54359500 # Cycle when the warmup percentage was hit. 377system.cpu.dcache.tags.occ_blocks::cpu.data 511.996962 # Average occupied blocks per requestor 378system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy 379system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy 380system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 381system.cpu.dcache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id 382system.cpu.dcache.tags.age_task_id_blocks_1024::1 326 # Occupied blocks per task id 383system.cpu.dcache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id 384system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 385system.cpu.dcache.tags.tag_accesses 88751069 # Number of tag accesses 386system.cpu.dcache.tags.data_accesses 88751069 # Number of data accesses 387system.cpu.dcache.ReadReq_hits::cpu.data 12012436 # number of ReadReq hits 388system.cpu.dcache.ReadReq_hits::total 12012436 # number of ReadReq hits 389system.cpu.dcache.WriteReq_hits::cpu.data 8077606 # number of WriteReq hits 390system.cpu.dcache.WriteReq_hits::total 8077606 # number of WriteReq hits 391system.cpu.dcache.SoftPFReq_hits::cpu.data 59170 # number of SoftPFReq hits 392system.cpu.dcache.SoftPFReq_hits::total 59170 # number of SoftPFReq hits 393system.cpu.dcache.demand_hits::cpu.data 20090042 # number of demand (read+write) hits 394system.cpu.dcache.demand_hits::total 20090042 # number of demand (read+write) hits 395system.cpu.dcache.overall_hits::cpu.data 20149212 # number of overall hits 396system.cpu.dcache.overall_hits::total 20149212 # number of overall hits 397system.cpu.dcache.ReadReq_misses::cpu.data 905821 # number of ReadReq misses 398system.cpu.dcache.ReadReq_misses::total 905821 # number of ReadReq misses 399system.cpu.dcache.WriteReq_misses::cpu.data 324802 # number of WriteReq misses 400system.cpu.dcache.WriteReq_misses::total 324802 # number of WriteReq misses 401system.cpu.dcache.SoftPFReq_misses::cpu.data 402538 # number of SoftPFReq misses 402system.cpu.dcache.SoftPFReq_misses::total 402538 # number of SoftPFReq misses 403system.cpu.dcache.demand_misses::cpu.data 1230623 # number of demand (read+write) misses 404system.cpu.dcache.demand_misses::total 1230623 # number of demand (read+write) misses 405system.cpu.dcache.overall_misses::cpu.data 1633161 # number of overall misses 406system.cpu.dcache.overall_misses::total 1633161 # number of overall misses 407system.cpu.dcache.ReadReq_miss_latency::cpu.data 12812474000 # number of ReadReq miss cycles 408system.cpu.dcache.ReadReq_miss_latency::total 12812474000 # number of ReadReq miss cycles 409system.cpu.dcache.WriteReq_miss_latency::cpu.data 12127378479 # number of WriteReq miss cycles 410system.cpu.dcache.WriteReq_miss_latency::total 12127378479 # number of WriteReq miss cycles 411system.cpu.dcache.demand_miss_latency::cpu.data 24939852479 # number of demand (read+write) miss cycles 412system.cpu.dcache.demand_miss_latency::total 24939852479 # number of demand (read+write) miss cycles 413system.cpu.dcache.overall_miss_latency::cpu.data 24939852479 # number of overall miss cycles 414system.cpu.dcache.overall_miss_latency::total 24939852479 # number of overall miss cycles 415system.cpu.dcache.ReadReq_accesses::cpu.data 12918257 # number of ReadReq accesses(hits+misses) 416system.cpu.dcache.ReadReq_accesses::total 12918257 # number of ReadReq accesses(hits+misses) 417system.cpu.dcache.WriteReq_accesses::cpu.data 8402408 # number of WriteReq accesses(hits+misses) 418system.cpu.dcache.WriteReq_accesses::total 8402408 # number of WriteReq accesses(hits+misses) 419system.cpu.dcache.SoftPFReq_accesses::cpu.data 461708 # number of SoftPFReq accesses(hits+misses) 420system.cpu.dcache.SoftPFReq_accesses::total 461708 # number of SoftPFReq accesses(hits+misses) 421system.cpu.dcache.demand_accesses::cpu.data 21320665 # number of demand (read+write) accesses 422system.cpu.dcache.demand_accesses::total 21320665 # number of demand (read+write) accesses 423system.cpu.dcache.overall_accesses::cpu.data 21782373 # number of overall (read+write) accesses 424system.cpu.dcache.overall_accesses::total 21782373 # number of overall (read+write) accesses 425system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070119 # miss rate for ReadReq accesses 426system.cpu.dcache.ReadReq_miss_rate::total 0.070119 # miss rate for ReadReq accesses 427system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038656 # miss rate for WriteReq accesses 428system.cpu.dcache.WriteReq_miss_rate::total 0.038656 # miss rate for WriteReq accesses 429system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.871845 # miss rate for SoftPFReq accesses 430system.cpu.dcache.SoftPFReq_miss_rate::total 0.871845 # miss rate for SoftPFReq accesses 431system.cpu.dcache.demand_miss_rate::cpu.data 0.057720 # miss rate for demand accesses 432system.cpu.dcache.demand_miss_rate::total 0.057720 # miss rate for demand accesses 433system.cpu.dcache.overall_miss_rate::cpu.data 0.074976 # miss rate for overall accesses 434system.cpu.dcache.overall_miss_rate::total 0.074976 # miss rate for overall accesses 435system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14144.598105 # average ReadReq miss latency 436system.cpu.dcache.ReadReq_avg_miss_latency::total 14144.598105 # average ReadReq miss latency 437system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37337.758016 # average WriteReq miss latency 438system.cpu.dcache.WriteReq_avg_miss_latency::total 37337.758016 # average WriteReq miss latency 439system.cpu.dcache.demand_avg_miss_latency::cpu.data 20266.037998 # average overall miss latency 440system.cpu.dcache.demand_avg_miss_latency::total 20266.037998 # average overall miss latency 441system.cpu.dcache.overall_avg_miss_latency::cpu.data 15270.908673 # average overall miss latency 442system.cpu.dcache.overall_avg_miss_latency::total 15270.908673 # average overall miss latency 443system.cpu.dcache.blocked_cycles::no_mshrs 5798 # number of cycles access was blocked 444system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 445system.cpu.dcache.blocked::no_mshrs 72 # number of cycles access was blocked 446system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 447system.cpu.dcache.avg_blocked_cycles::no_mshrs 80.527778 # average number of cycles each access was blocked 448system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 449system.cpu.dcache.fast_writes 0 # number of fast writes performed 450system.cpu.dcache.cache_copies 0 # number of cache copies performed 451system.cpu.dcache.writebacks::writebacks 1537873 # number of writebacks 452system.cpu.dcache.writebacks::total 1537873 # number of writebacks 453system.cpu.dcache.ReadReq_mshr_hits::cpu.data 288 # number of ReadReq MSHR hits 454system.cpu.dcache.ReadReq_mshr_hits::total 288 # number of ReadReq MSHR hits 455system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9093 # number of WriteReq MSHR hits 456system.cpu.dcache.WriteReq_mshr_hits::total 9093 # number of WriteReq MSHR hits 457system.cpu.dcache.demand_mshr_hits::cpu.data 9381 # number of demand (read+write) MSHR hits 458system.cpu.dcache.demand_mshr_hits::total 9381 # number of demand (read+write) MSHR hits 459system.cpu.dcache.overall_mshr_hits::cpu.data 9381 # number of overall MSHR hits 460system.cpu.dcache.overall_mshr_hits::total 9381 # number of overall MSHR hits 461system.cpu.dcache.ReadReq_mshr_misses::cpu.data 905533 # number of ReadReq MSHR misses 462system.cpu.dcache.ReadReq_mshr_misses::total 905533 # number of ReadReq MSHR misses 463system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315709 # number of WriteReq MSHR misses 464system.cpu.dcache.WriteReq_mshr_misses::total 315709 # number of WriteReq MSHR misses 465system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402504 # number of SoftPFReq MSHR misses 466system.cpu.dcache.SoftPFReq_mshr_misses::total 402504 # number of SoftPFReq MSHR misses 467system.cpu.dcache.demand_mshr_misses::cpu.data 1221242 # number of demand (read+write) MSHR misses 468system.cpu.dcache.demand_mshr_misses::total 1221242 # number of demand (read+write) MSHR misses 469system.cpu.dcache.overall_mshr_misses::cpu.data 1623746 # number of overall MSHR misses 470system.cpu.dcache.overall_mshr_misses::total 1623746 # number of overall MSHR misses 471system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 572954 # number of ReadReq MSHR uncacheable 472system.cpu.dcache.ReadReq_mshr_uncacheable::total 572954 # number of ReadReq MSHR uncacheable 473system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 13916 # number of WriteReq MSHR uncacheable 474system.cpu.dcache.WriteReq_mshr_uncacheable::total 13916 # number of WriteReq MSHR uncacheable 475system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 586870 # number of overall MSHR uncacheable misses 476system.cpu.dcache.overall_mshr_uncacheable_misses::total 586870 # number of overall MSHR uncacheable misses 477system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11904745500 # number of ReadReq MSHR miss cycles 478system.cpu.dcache.ReadReq_mshr_miss_latency::total 11904745500 # number of ReadReq MSHR miss cycles 479system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11312729479 # number of WriteReq MSHR miss cycles 480system.cpu.dcache.WriteReq_mshr_miss_latency::total 11312729479 # number of WriteReq MSHR miss cycles 481system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5814985000 # number of SoftPFReq MSHR miss cycles 482system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5814985000 # number of SoftPFReq MSHR miss cycles 483system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23217474979 # number of demand (read+write) MSHR miss cycles 484system.cpu.dcache.demand_mshr_miss_latency::total 23217474979 # number of demand (read+write) MSHR miss cycles 485system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29032459979 # number of overall MSHR miss cycles 486system.cpu.dcache.overall_mshr_miss_latency::total 29032459979 # number of overall MSHR miss cycles 487system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94684333500 # number of ReadReq MSHR uncacheable cycles 488system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94684333500 # number of ReadReq MSHR uncacheable cycles 489system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2622247500 # number of WriteReq MSHR uncacheable cycles 490system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2622247500 # number of WriteReq MSHR uncacheable cycles 491system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 97306581000 # number of overall MSHR uncacheable cycles 492system.cpu.dcache.overall_mshr_uncacheable_latency::total 97306581000 # number of overall MSHR uncacheable cycles 493system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070097 # mshr miss rate for ReadReq accesses 494system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070097 # mshr miss rate for ReadReq accesses 495system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037574 # mshr miss rate for WriteReq accesses 496system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037574 # mshr miss rate for WriteReq accesses 497system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.871772 # mshr miss rate for SoftPFReq accesses 498system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.871772 # mshr miss rate for SoftPFReq accesses 499system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057280 # mshr miss rate for demand accesses 500system.cpu.dcache.demand_mshr_miss_rate::total 0.057280 # mshr miss rate for demand accesses 501system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074544 # mshr miss rate for overall accesses 502system.cpu.dcache.overall_mshr_miss_rate::total 0.074544 # mshr miss rate for overall accesses 503system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13146.672181 # average ReadReq mshr miss latency 504system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13146.672181 # average ReadReq mshr miss latency 505system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35832.774736 # average WriteReq mshr miss latency 506system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35832.774736 # average WriteReq mshr miss latency 507system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14447.024129 # average SoftPFReq mshr miss latency 508system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14447.024129 # average SoftPFReq mshr miss latency 509system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19011.363005 # average overall mshr miss latency 510system.cpu.dcache.demand_avg_mshr_miss_latency::total 19011.363005 # average overall mshr miss latency 511system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17879.927020 # average overall mshr miss latency 512system.cpu.dcache.overall_avg_mshr_miss_latency::total 17879.927020 # average overall mshr miss latency 513system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 165256.431581 # average ReadReq mshr uncacheable latency 514system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 165256.431581 # average ReadReq mshr uncacheable latency 515system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188433.996838 # average WriteReq mshr uncacheable latency 516system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 188433.996838 # average WriteReq mshr uncacheable latency 517system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 165806.023480 # average overall mshr uncacheable latency 518system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 165806.023480 # average overall mshr uncacheable latency 519system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 520system.cpu.dtb_walker_cache.tags.replacements 7782 # number of replacements 521system.cpu.dtb_walker_cache.tags.tagsinuse 5.044171 # Cycle average of tags in use 522system.cpu.dtb_walker_cache.tags.total_refs 13071 # Total number of references to valid blocks. 523system.cpu.dtb_walker_cache.tags.sampled_refs 7797 # Sample count of references to valid blocks. 524system.cpu.dtb_walker_cache.tags.avg_refs 1.676414 # Average number of references to valid blocks. 525system.cpu.dtb_walker_cache.tags.warmup_cycle 5158049844500 # Cycle when the warmup percentage was hit. 526system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.044171 # Average occupied blocks per requestor 527system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.315261 # Average percentage of cache occupancy 528system.cpu.dtb_walker_cache.tags.occ_percent::total 0.315261 # Average percentage of cache occupancy 529system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id 530system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id 531system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id 532system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id 533system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 534system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id 535system.cpu.dtb_walker_cache.tags.tag_accesses 53116 # Number of tag accesses 536system.cpu.dtb_walker_cache.tags.data_accesses 53116 # Number of data accesses 537system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13073 # number of ReadReq hits 538system.cpu.dtb_walker_cache.ReadReq_hits::total 13073 # number of ReadReq hits 539system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13073 # number of demand (read+write) hits 540system.cpu.dtb_walker_cache.demand_hits::total 13073 # number of demand (read+write) hits 541system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13073 # number of overall hits 542system.cpu.dtb_walker_cache.overall_hits::total 13073 # number of overall hits 543system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8990 # number of ReadReq misses 544system.cpu.dtb_walker_cache.ReadReq_misses::total 8990 # number of ReadReq misses 545system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8990 # number of demand (read+write) misses 546system.cpu.dtb_walker_cache.demand_misses::total 8990 # number of demand (read+write) misses 547system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8990 # number of overall misses 548system.cpu.dtb_walker_cache.overall_misses::total 8990 # number of overall misses 549system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 97324000 # number of ReadReq miss cycles 550system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 97324000 # number of ReadReq miss cycles 551system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 97324000 # number of demand (read+write) miss cycles 552system.cpu.dtb_walker_cache.demand_miss_latency::total 97324000 # number of demand (read+write) miss cycles 553system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 97324000 # number of overall miss cycles 554system.cpu.dtb_walker_cache.overall_miss_latency::total 97324000 # number of overall miss cycles 555system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22063 # number of ReadReq accesses(hits+misses) 556system.cpu.dtb_walker_cache.ReadReq_accesses::total 22063 # number of ReadReq accesses(hits+misses) 557system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22063 # number of demand (read+write) accesses 558system.cpu.dtb_walker_cache.demand_accesses::total 22063 # number of demand (read+write) accesses 559system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22063 # number of overall (read+write) accesses 560system.cpu.dtb_walker_cache.overall_accesses::total 22063 # number of overall (read+write) accesses 561system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.407470 # miss rate for ReadReq accesses 562system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.407470 # miss rate for ReadReq accesses 563system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.407470 # miss rate for demand accesses 564system.cpu.dtb_walker_cache.demand_miss_rate::total 0.407470 # miss rate for demand accesses 565system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.407470 # miss rate for overall accesses 566system.cpu.dtb_walker_cache.overall_miss_rate::total 0.407470 # miss rate for overall accesses 567system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10825.806452 # average ReadReq miss latency 568system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10825.806452 # average ReadReq miss latency 569system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10825.806452 # average overall miss latency 570system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10825.806452 # average overall miss latency 571system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10825.806452 # average overall miss latency 572system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10825.806452 # average overall miss latency 573system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 574system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 575system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 576system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 577system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 578system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 579system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 580system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed 581system.cpu.dtb_walker_cache.writebacks::writebacks 3106 # number of writebacks 582system.cpu.dtb_walker_cache.writebacks::total 3106 # number of writebacks 583system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8990 # number of ReadReq MSHR misses 584system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8990 # number of ReadReq MSHR misses 585system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8990 # number of demand (read+write) MSHR misses 586system.cpu.dtb_walker_cache.demand_mshr_misses::total 8990 # number of demand (read+write) MSHR misses 587system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8990 # number of overall MSHR misses 588system.cpu.dtb_walker_cache.overall_mshr_misses::total 8990 # number of overall MSHR misses 589system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 88334000 # number of ReadReq MSHR miss cycles 590system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 88334000 # number of ReadReq MSHR miss cycles 591system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 88334000 # number of demand (read+write) MSHR miss cycles 592system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 88334000 # number of demand (read+write) MSHR miss cycles 593system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 88334000 # number of overall MSHR miss cycles 594system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 88334000 # number of overall MSHR miss cycles 595system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.407470 # mshr miss rate for ReadReq accesses 596system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.407470 # mshr miss rate for ReadReq accesses 597system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.407470 # mshr miss rate for demand accesses 598system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.407470 # mshr miss rate for demand accesses 599system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.407470 # mshr miss rate for overall accesses 600system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.407470 # mshr miss rate for overall accesses 601system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 9825.806452 # average ReadReq mshr miss latency 602system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9825.806452 # average ReadReq mshr miss latency 603system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 9825.806452 # average overall mshr miss latency 604system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 9825.806452 # average overall mshr miss latency 605system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 9825.806452 # average overall mshr miss latency 606system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 9825.806452 # average overall mshr miss latency 607system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 608system.cpu.icache.tags.replacements 792637 # number of replacements 609system.cpu.icache.tags.tagsinuse 510.330403 # Cycle average of tags in use 610system.cpu.icache.tags.total_refs 144952019 # Total number of references to valid blocks. 611system.cpu.icache.tags.sampled_refs 793149 # Sample count of references to valid blocks. 612system.cpu.icache.tags.avg_refs 182.755093 # Average number of references to valid blocks. 613system.cpu.icache.tags.warmup_cycle 161555480500 # Cycle when the warmup percentage was hit. 614system.cpu.icache.tags.occ_blocks::cpu.inst 510.330403 # Average occupied blocks per requestor 615system.cpu.icache.tags.occ_percent::cpu.inst 0.996739 # Average percentage of cache occupancy 616system.cpu.icache.tags.occ_percent::total 0.996739 # Average percentage of cache occupancy 617system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 618system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id 619system.cpu.icache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id 620system.cpu.icache.tags.age_task_id_blocks_1024::2 289 # Occupied blocks per task id 621system.cpu.icache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id 622system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 623system.cpu.icache.tags.tag_accesses 146538331 # Number of tag accesses 624system.cpu.icache.tags.data_accesses 146538331 # Number of data accesses 625system.cpu.icache.ReadReq_hits::cpu.inst 144952019 # number of ReadReq hits 626system.cpu.icache.ReadReq_hits::total 144952019 # number of ReadReq hits 627system.cpu.icache.demand_hits::cpu.inst 144952019 # number of demand (read+write) hits 628system.cpu.icache.demand_hits::total 144952019 # number of demand (read+write) hits 629system.cpu.icache.overall_hits::cpu.inst 144952019 # number of overall hits 630system.cpu.icache.overall_hits::total 144952019 # number of overall hits 631system.cpu.icache.ReadReq_misses::cpu.inst 793156 # number of ReadReq misses 632system.cpu.icache.ReadReq_misses::total 793156 # number of ReadReq misses 633system.cpu.icache.demand_misses::cpu.inst 793156 # number of demand (read+write) misses 634system.cpu.icache.demand_misses::total 793156 # number of demand (read+write) misses 635system.cpu.icache.overall_misses::cpu.inst 793156 # number of overall misses 636system.cpu.icache.overall_misses::total 793156 # number of overall misses 637system.cpu.icache.ReadReq_miss_latency::cpu.inst 11221653000 # number of ReadReq miss cycles 638system.cpu.icache.ReadReq_miss_latency::total 11221653000 # number of ReadReq miss cycles 639system.cpu.icache.demand_miss_latency::cpu.inst 11221653000 # number of demand (read+write) miss cycles 640system.cpu.icache.demand_miss_latency::total 11221653000 # number of demand (read+write) miss cycles 641system.cpu.icache.overall_miss_latency::cpu.inst 11221653000 # number of overall miss cycles 642system.cpu.icache.overall_miss_latency::total 11221653000 # number of overall miss cycles 643system.cpu.icache.ReadReq_accesses::cpu.inst 145745175 # number of ReadReq accesses(hits+misses) 644system.cpu.icache.ReadReq_accesses::total 145745175 # number of ReadReq accesses(hits+misses) 645system.cpu.icache.demand_accesses::cpu.inst 145745175 # number of demand (read+write) accesses 646system.cpu.icache.demand_accesses::total 145745175 # number of demand (read+write) accesses 647system.cpu.icache.overall_accesses::cpu.inst 145745175 # number of overall (read+write) accesses 648system.cpu.icache.overall_accesses::total 145745175 # number of overall (read+write) accesses 649system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005442 # miss rate for ReadReq accesses 650system.cpu.icache.ReadReq_miss_rate::total 0.005442 # miss rate for ReadReq accesses 651system.cpu.icache.demand_miss_rate::cpu.inst 0.005442 # miss rate for demand accesses 652system.cpu.icache.demand_miss_rate::total 0.005442 # miss rate for demand accesses 653system.cpu.icache.overall_miss_rate::cpu.inst 0.005442 # miss rate for overall accesses 654system.cpu.icache.overall_miss_rate::total 0.005442 # miss rate for overall accesses 655system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14148.103274 # average ReadReq miss latency 656system.cpu.icache.ReadReq_avg_miss_latency::total 14148.103274 # average ReadReq miss latency 657system.cpu.icache.demand_avg_miss_latency::cpu.inst 14148.103274 # average overall miss latency 658system.cpu.icache.demand_avg_miss_latency::total 14148.103274 # average overall miss latency 659system.cpu.icache.overall_avg_miss_latency::cpu.inst 14148.103274 # average overall miss latency 660system.cpu.icache.overall_avg_miss_latency::total 14148.103274 # average overall miss latency 661system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 662system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 663system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 664system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 665system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 666system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 667system.cpu.icache.fast_writes 0 # number of fast writes performed 668system.cpu.icache.cache_copies 0 # number of cache copies performed 669system.cpu.icache.ReadReq_mshr_misses::cpu.inst 793156 # number of ReadReq MSHR misses 670system.cpu.icache.ReadReq_mshr_misses::total 793156 # number of ReadReq MSHR misses 671system.cpu.icache.demand_mshr_misses::cpu.inst 793156 # number of demand (read+write) MSHR misses 672system.cpu.icache.demand_mshr_misses::total 793156 # number of demand (read+write) MSHR misses 673system.cpu.icache.overall_mshr_misses::cpu.inst 793156 # number of overall MSHR misses 674system.cpu.icache.overall_mshr_misses::total 793156 # number of overall MSHR misses 675system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10428497000 # number of ReadReq MSHR miss cycles 676system.cpu.icache.ReadReq_mshr_miss_latency::total 10428497000 # number of ReadReq MSHR miss cycles 677system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10428497000 # number of demand (read+write) MSHR miss cycles 678system.cpu.icache.demand_mshr_miss_latency::total 10428497000 # number of demand (read+write) MSHR miss cycles 679system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10428497000 # number of overall MSHR miss cycles 680system.cpu.icache.overall_mshr_miss_latency::total 10428497000 # number of overall MSHR miss cycles 681system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005442 # mshr miss rate for ReadReq accesses 682system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005442 # mshr miss rate for ReadReq accesses 683system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005442 # mshr miss rate for demand accesses 684system.cpu.icache.demand_mshr_miss_rate::total 0.005442 # mshr miss rate for demand accesses 685system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005442 # mshr miss rate for overall accesses 686system.cpu.icache.overall_mshr_miss_rate::total 0.005442 # mshr miss rate for overall accesses 687system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13148.103274 # average ReadReq mshr miss latency 688system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13148.103274 # average ReadReq mshr miss latency 689system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13148.103274 # average overall mshr miss latency 690system.cpu.icache.demand_avg_mshr_miss_latency::total 13148.103274 # average overall mshr miss latency 691system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13148.103274 # average overall mshr miss latency 692system.cpu.icache.overall_avg_mshr_miss_latency::total 13148.103274 # average overall mshr miss latency 693system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 694system.cpu.itb_walker_cache.tags.replacements 3538 # number of replacements 695system.cpu.itb_walker_cache.tags.tagsinuse 3.060279 # Cycle average of tags in use 696system.cpu.itb_walker_cache.tags.total_refs 7930 # Total number of references to valid blocks. 697system.cpu.itb_walker_cache.tags.sampled_refs 3549 # Sample count of references to valid blocks. 698system.cpu.itb_walker_cache.tags.avg_refs 2.234432 # Average number of references to valid blocks. 699system.cpu.itb_walker_cache.tags.warmup_cycle 5161245744500 # Cycle when the warmup percentage was hit. 700system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.060279 # Average occupied blocks per requestor 701system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191267 # Average percentage of cache occupancy 702system.cpu.itb_walker_cache.tags.occ_percent::total 0.191267 # Average percentage of cache occupancy 703system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 11 # Occupied blocks per task id 704system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id 705system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id 706system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id 707system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 708system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.687500 # Percentage of cache occupancy per task id 709system.cpu.itb_walker_cache.tags.tag_accesses 29062 # Number of tag accesses 710system.cpu.itb_walker_cache.tags.data_accesses 29062 # Number of data accesses 711system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7929 # number of ReadReq hits 712system.cpu.itb_walker_cache.ReadReq_hits::total 7929 # number of ReadReq hits 713system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 714system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits 715system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7931 # number of demand (read+write) hits 716system.cpu.itb_walker_cache.demand_hits::total 7931 # number of demand (read+write) hits 717system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7931 # number of overall hits 718system.cpu.itb_walker_cache.overall_hits::total 7931 # number of overall hits 719system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4400 # number of ReadReq misses 720system.cpu.itb_walker_cache.ReadReq_misses::total 4400 # number of ReadReq misses 721system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4400 # number of demand (read+write) misses 722system.cpu.itb_walker_cache.demand_misses::total 4400 # number of demand (read+write) misses 723system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4400 # number of overall misses 724system.cpu.itb_walker_cache.overall_misses::total 4400 # number of overall misses 725system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 45407000 # number of ReadReq miss cycles 726system.cpu.itb_walker_cache.ReadReq_miss_latency::total 45407000 # number of ReadReq miss cycles 727system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 45407000 # number of demand (read+write) miss cycles 728system.cpu.itb_walker_cache.demand_miss_latency::total 45407000 # number of demand (read+write) miss cycles 729system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 45407000 # number of overall miss cycles 730system.cpu.itb_walker_cache.overall_miss_latency::total 45407000 # number of overall miss cycles 731system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12329 # number of ReadReq accesses(hits+misses) 732system.cpu.itb_walker_cache.ReadReq_accesses::total 12329 # number of ReadReq accesses(hits+misses) 733system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 734system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) 735system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12331 # number of demand (read+write) accesses 736system.cpu.itb_walker_cache.demand_accesses::total 12331 # number of demand (read+write) accesses 737system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12331 # number of overall (read+write) accesses 738system.cpu.itb_walker_cache.overall_accesses::total 12331 # number of overall (read+write) accesses 739system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.356882 # miss rate for ReadReq accesses 740system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.356882 # miss rate for ReadReq accesses 741system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.356824 # miss rate for demand accesses 742system.cpu.itb_walker_cache.demand_miss_rate::total 0.356824 # miss rate for demand accesses 743system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.356824 # miss rate for overall accesses 744system.cpu.itb_walker_cache.overall_miss_rate::total 0.356824 # miss rate for overall accesses 745system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10319.772727 # average ReadReq miss latency 746system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10319.772727 # average ReadReq miss latency 747system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10319.772727 # average overall miss latency 748system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10319.772727 # average overall miss latency 749system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10319.772727 # average overall miss latency 750system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10319.772727 # average overall miss latency 751system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 752system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 753system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 754system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 755system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 756system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 757system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 758system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed 759system.cpu.itb_walker_cache.writebacks::writebacks 796 # number of writebacks 760system.cpu.itb_walker_cache.writebacks::total 796 # number of writebacks 761system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4400 # number of ReadReq MSHR misses 762system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4400 # number of ReadReq MSHR misses 763system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4400 # number of demand (read+write) MSHR misses 764system.cpu.itb_walker_cache.demand_mshr_misses::total 4400 # number of demand (read+write) MSHR misses 765system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4400 # number of overall MSHR misses 766system.cpu.itb_walker_cache.overall_mshr_misses::total 4400 # number of overall MSHR misses 767system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 41007000 # number of ReadReq MSHR miss cycles 768system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 41007000 # number of ReadReq MSHR miss cycles 769system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 41007000 # number of demand (read+write) MSHR miss cycles 770system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 41007000 # number of demand (read+write) MSHR miss cycles 771system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 41007000 # number of overall MSHR miss cycles 772system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 41007000 # number of overall MSHR miss cycles 773system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.356882 # mshr miss rate for ReadReq accesses 774system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.356882 # mshr miss rate for ReadReq accesses 775system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.356824 # mshr miss rate for demand accesses 776system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.356824 # mshr miss rate for demand accesses 777system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.356824 # mshr miss rate for overall accesses 778system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.356824 # mshr miss rate for overall accesses 779system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9319.772727 # average ReadReq mshr miss latency 780system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9319.772727 # average ReadReq mshr miss latency 781system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9319.772727 # average overall mshr miss latency 782system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9319.772727 # average overall mshr miss latency 783system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9319.772727 # average overall mshr miss latency 784system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9319.772727 # average overall mshr miss latency 785system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 786system.cpu.l2cache.tags.replacements 87263 # number of replacements 787system.cpu.l2cache.tags.tagsinuse 64757.225173 # Cycle average of tags in use 788system.cpu.l2cache.tags.total_refs 4369524 # Total number of references to valid blocks. 789system.cpu.l2cache.tags.sampled_refs 151965 # Sample count of references to valid blocks. 790system.cpu.l2cache.tags.avg_refs 28.753489 # Average number of references to valid blocks. 791system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 792system.cpu.l2cache.tags.occ_blocks::writebacks 50419.617435 # Average occupied blocks per requestor 793system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.145028 # Average occupied blocks per requestor 794system.cpu.l2cache.tags.occ_blocks::cpu.inst 3328.329800 # Average occupied blocks per requestor 795system.cpu.l2cache.tags.occ_blocks::cpu.data 11009.132909 # Average occupied blocks per requestor 796system.cpu.l2cache.tags.occ_percent::writebacks 0.769342 # Average percentage of cache occupancy 797system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy 798system.cpu.l2cache.tags.occ_percent::cpu.inst 0.050786 # Average percentage of cache occupancy 799system.cpu.l2cache.tags.occ_percent::cpu.data 0.167986 # Average percentage of cache occupancy 800system.cpu.l2cache.tags.occ_percent::total 0.988117 # Average percentage of cache occupancy 801system.cpu.l2cache.tags.occ_task_id_blocks::1024 64702 # Occupied blocks per task id 802system.cpu.l2cache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id 803system.cpu.l2cache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id 804system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2890 # Occupied blocks per task id 805system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5302 # Occupied blocks per task id 806system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56392 # Occupied blocks per task id 807system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987274 # Percentage of cache occupancy per task id 808system.cpu.l2cache.tags.tag_accesses 39224493 # Number of tag accesses 809system.cpu.l2cache.tags.data_accesses 39224493 # Number of data accesses 810system.cpu.l2cache.Writeback_hits::writebacks 1541775 # number of Writeback hits 811system.cpu.l2cache.Writeback_hits::total 1541775 # number of Writeback hits 812system.cpu.l2cache.UpgradeReq_hits::cpu.data 307 # number of UpgradeReq hits 813system.cpu.l2cache.UpgradeReq_hits::total 307 # number of UpgradeReq hits 814system.cpu.l2cache.ReadExReq_hits::cpu.data 199754 # number of ReadExReq hits 815system.cpu.l2cache.ReadExReq_hits::total 199754 # number of ReadExReq hits 816system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 780246 # number of ReadCleanReq hits 817system.cpu.l2cache.ReadCleanReq_hits::total 780246 # number of ReadCleanReq hits 818system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker 6724 # number of ReadSharedReq hits 819system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker 3018 # number of ReadSharedReq hits 820system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1278797 # number of ReadSharedReq hits 821system.cpu.l2cache.ReadSharedReq_hits::total 1288539 # number of ReadSharedReq hits 822system.cpu.l2cache.demand_hits::cpu.dtb.walker 6724 # number of demand (read+write) hits 823system.cpu.l2cache.demand_hits::cpu.itb.walker 3018 # number of demand (read+write) hits 824system.cpu.l2cache.demand_hits::cpu.inst 780246 # number of demand (read+write) hits 825system.cpu.l2cache.demand_hits::cpu.data 1478551 # number of demand (read+write) hits 826system.cpu.l2cache.demand_hits::total 2268539 # number of demand (read+write) hits 827system.cpu.l2cache.overall_hits::cpu.dtb.walker 6724 # number of overall hits 828system.cpu.l2cache.overall_hits::cpu.itb.walker 3018 # number of overall hits 829system.cpu.l2cache.overall_hits::cpu.inst 780246 # number of overall hits 830system.cpu.l2cache.overall_hits::cpu.data 1478551 # number of overall hits 831system.cpu.l2cache.overall_hits::total 2268539 # number of overall hits 832system.cpu.l2cache.UpgradeReq_misses::cpu.data 1367 # number of UpgradeReq misses 833system.cpu.l2cache.UpgradeReq_misses::total 1367 # number of UpgradeReq misses 834system.cpu.l2cache.ReadExReq_misses::cpu.data 113781 # number of ReadExReq misses 835system.cpu.l2cache.ReadExReq_misses::total 113781 # number of ReadExReq misses 836system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 12897 # number of ReadCleanReq misses 837system.cpu.l2cache.ReadCleanReq_misses::total 12897 # number of ReadCleanReq misses 838system.cpu.l2cache.ReadSharedReq_misses::cpu.itb.walker 5 # number of ReadSharedReq misses 839system.cpu.l2cache.ReadSharedReq_misses::cpu.data 28476 # number of ReadSharedReq misses 840system.cpu.l2cache.ReadSharedReq_misses::total 28481 # number of ReadSharedReq misses 841system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses 842system.cpu.l2cache.demand_misses::cpu.inst 12897 # number of demand (read+write) misses 843system.cpu.l2cache.demand_misses::cpu.data 142257 # number of demand (read+write) misses 844system.cpu.l2cache.demand_misses::total 155159 # number of demand (read+write) misses 845system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses 846system.cpu.l2cache.overall_misses::cpu.inst 12897 # number of overall misses 847system.cpu.l2cache.overall_misses::cpu.data 142257 # number of overall misses 848system.cpu.l2cache.overall_misses::total 155159 # number of overall misses 849system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 21508500 # number of UpgradeReq miss cycles 850system.cpu.l2cache.UpgradeReq_miss_latency::total 21508500 # number of UpgradeReq miss cycles 851system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8694302000 # number of ReadExReq miss cycles 852system.cpu.l2cache.ReadExReq_miss_latency::total 8694302000 # number of ReadExReq miss cycles 853system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1043096500 # number of ReadCleanReq miss cycles 854system.cpu.l2cache.ReadCleanReq_miss_latency::total 1043096500 # number of ReadCleanReq miss cycles 855system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.itb.walker 401500 # number of ReadSharedReq miss cycles 856system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2328492500 # number of ReadSharedReq miss cycles 857system.cpu.l2cache.ReadSharedReq_miss_latency::total 2328894000 # number of ReadSharedReq miss cycles 858system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 401500 # number of demand (read+write) miss cycles 859system.cpu.l2cache.demand_miss_latency::cpu.inst 1043096500 # number of demand (read+write) miss cycles 860system.cpu.l2cache.demand_miss_latency::cpu.data 11022794500 # number of demand (read+write) miss cycles 861system.cpu.l2cache.demand_miss_latency::total 12066292500 # number of demand (read+write) miss cycles 862system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 401500 # number of overall miss cycles 863system.cpu.l2cache.overall_miss_latency::cpu.inst 1043096500 # number of overall miss cycles 864system.cpu.l2cache.overall_miss_latency::cpu.data 11022794500 # number of overall miss cycles 865system.cpu.l2cache.overall_miss_latency::total 12066292500 # number of overall miss cycles 866system.cpu.l2cache.Writeback_accesses::writebacks 1541775 # number of Writeback accesses(hits+misses) 867system.cpu.l2cache.Writeback_accesses::total 1541775 # number of Writeback accesses(hits+misses) 868system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1674 # number of UpgradeReq accesses(hits+misses) 869system.cpu.l2cache.UpgradeReq_accesses::total 1674 # number of UpgradeReq accesses(hits+misses) 870system.cpu.l2cache.ReadExReq_accesses::cpu.data 313535 # number of ReadExReq accesses(hits+misses) 871system.cpu.l2cache.ReadExReq_accesses::total 313535 # number of ReadExReq accesses(hits+misses) 872system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 793143 # number of ReadCleanReq accesses(hits+misses) 873system.cpu.l2cache.ReadCleanReq_accesses::total 793143 # number of ReadCleanReq accesses(hits+misses) 874system.cpu.l2cache.ReadSharedReq_accesses::cpu.dtb.walker 6724 # number of ReadSharedReq accesses(hits+misses) 875system.cpu.l2cache.ReadSharedReq_accesses::cpu.itb.walker 3023 # number of ReadSharedReq accesses(hits+misses) 876system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1307273 # number of ReadSharedReq accesses(hits+misses) 877system.cpu.l2cache.ReadSharedReq_accesses::total 1317020 # number of ReadSharedReq accesses(hits+misses) 878system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6724 # number of demand (read+write) accesses 879system.cpu.l2cache.demand_accesses::cpu.itb.walker 3023 # number of demand (read+write) accesses 880system.cpu.l2cache.demand_accesses::cpu.inst 793143 # number of demand (read+write) accesses 881system.cpu.l2cache.demand_accesses::cpu.data 1620808 # number of demand (read+write) accesses 882system.cpu.l2cache.demand_accesses::total 2423698 # number of demand (read+write) accesses 883system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6724 # number of overall (read+write) accesses 884system.cpu.l2cache.overall_accesses::cpu.itb.walker 3023 # number of overall (read+write) accesses 885system.cpu.l2cache.overall_accesses::cpu.inst 793143 # number of overall (read+write) accesses 886system.cpu.l2cache.overall_accesses::cpu.data 1620808 # number of overall (read+write) accesses 887system.cpu.l2cache.overall_accesses::total 2423698 # number of overall (read+write) accesses 888system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.816607 # miss rate for UpgradeReq accesses 889system.cpu.l2cache.UpgradeReq_miss_rate::total 0.816607 # miss rate for UpgradeReq accesses 890system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.362897 # miss rate for ReadExReq accesses 891system.cpu.l2cache.ReadExReq_miss_rate::total 0.362897 # miss rate for ReadExReq accesses 892system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.016261 # miss rate for ReadCleanReq accesses 893system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.016261 # miss rate for ReadCleanReq accesses 894system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.itb.walker 0.001654 # miss rate for ReadSharedReq accesses 895system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.021783 # miss rate for ReadSharedReq accesses 896system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.021625 # miss rate for ReadSharedReq accesses 897system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001654 # miss rate for demand accesses 898system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016261 # miss rate for demand accesses 899system.cpu.l2cache.demand_miss_rate::cpu.data 0.087769 # miss rate for demand accesses 900system.cpu.l2cache.demand_miss_rate::total 0.064017 # miss rate for demand accesses 901system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001654 # miss rate for overall accesses 902system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016261 # miss rate for overall accesses 903system.cpu.l2cache.overall_miss_rate::cpu.data 0.087769 # miss rate for overall accesses 904system.cpu.l2cache.overall_miss_rate::total 0.064017 # miss rate for overall accesses 905system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15734.089247 # average UpgradeReq miss latency 906system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15734.089247 # average UpgradeReq miss latency 907system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76412.599643 # average ReadExReq miss latency 908system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76412.599643 # average ReadExReq miss latency 909system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80879.002869 # average ReadCleanReq miss latency 910system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80879.002869 # average ReadCleanReq miss latency 911system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.itb.walker 80300 # average ReadSharedReq miss latency 912system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81770.350471 # average ReadSharedReq miss latency 913system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81770.092342 # average ReadSharedReq miss latency 914system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 80300 # average overall miss latency 915system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80879.002869 # average overall miss latency 916system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77485.076306 # average overall miss latency 917system.cpu.l2cache.demand_avg_miss_latency::total 77767.274215 # average overall miss latency 918system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 80300 # average overall miss latency 919system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80879.002869 # average overall miss latency 920system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77485.076306 # average overall miss latency 921system.cpu.l2cache.overall_avg_miss_latency::total 77767.274215 # average overall miss latency 922system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 923system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 924system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 925system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 926system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 927system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 928system.cpu.l2cache.fast_writes 0 # number of fast writes performed 929system.cpu.l2cache.cache_copies 0 # number of cache copies performed 930system.cpu.l2cache.writebacks::writebacks 80412 # number of writebacks 931system.cpu.l2cache.writebacks::total 80412 # number of writebacks 932system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 30 # number of CleanEvict MSHR misses 933system.cpu.l2cache.CleanEvict_mshr_misses::total 30 # number of CleanEvict MSHR misses 934system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1367 # number of UpgradeReq MSHR misses 935system.cpu.l2cache.UpgradeReq_mshr_misses::total 1367 # number of UpgradeReq MSHR misses 936system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 113781 # number of ReadExReq MSHR misses 937system.cpu.l2cache.ReadExReq_mshr_misses::total 113781 # number of ReadExReq MSHR misses 938system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 12897 # number of ReadCleanReq MSHR misses 939system.cpu.l2cache.ReadCleanReq_mshr_misses::total 12897 # number of ReadCleanReq MSHR misses 940system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.itb.walker 5 # number of ReadSharedReq MSHR misses 941system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 28476 # number of ReadSharedReq MSHR misses 942system.cpu.l2cache.ReadSharedReq_mshr_misses::total 28481 # number of ReadSharedReq MSHR misses 943system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses 944system.cpu.l2cache.demand_mshr_misses::cpu.inst 12897 # number of demand (read+write) MSHR misses 945system.cpu.l2cache.demand_mshr_misses::cpu.data 142257 # number of demand (read+write) MSHR misses 946system.cpu.l2cache.demand_mshr_misses::total 155159 # number of demand (read+write) MSHR misses 947system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses 948system.cpu.l2cache.overall_mshr_misses::cpu.inst 12897 # number of overall MSHR misses 949system.cpu.l2cache.overall_mshr_misses::cpu.data 142257 # number of overall MSHR misses 950system.cpu.l2cache.overall_mshr_misses::total 155159 # number of overall MSHR misses 951system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 572954 # number of ReadReq MSHR uncacheable 952system.cpu.l2cache.ReadReq_mshr_uncacheable::total 572954 # number of ReadReq MSHR uncacheable 953system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 13916 # number of WriteReq MSHR uncacheable 954system.cpu.l2cache.WriteReq_mshr_uncacheable::total 13916 # number of WriteReq MSHR uncacheable 955system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 586870 # number of overall MSHR uncacheable misses 956system.cpu.l2cache.overall_mshr_uncacheable_misses::total 586870 # number of overall MSHR uncacheable misses 957system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29036000 # number of UpgradeReq MSHR miss cycles 958system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29036000 # number of UpgradeReq MSHR miss cycles 959system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7556492000 # number of ReadExReq MSHR miss cycles 960system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7556492000 # number of ReadExReq MSHR miss cycles 961system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 914126500 # number of ReadCleanReq MSHR miss cycles 962system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 914126500 # number of ReadCleanReq MSHR miss cycles 963system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.itb.walker 351500 # number of ReadSharedReq MSHR miss cycles 964system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2043732500 # number of ReadSharedReq MSHR miss cycles 965system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2044084000 # number of ReadSharedReq MSHR miss cycles 966system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 351500 # number of demand (read+write) MSHR miss cycles 967system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 914126500 # number of demand (read+write) MSHR miss cycles 968system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9600224500 # number of demand (read+write) MSHR miss cycles 969system.cpu.l2cache.demand_mshr_miss_latency::total 10514702500 # number of demand (read+write) MSHR miss cycles 970system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 351500 # number of overall MSHR miss cycles 971system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 914126500 # number of overall MSHR miss cycles 972system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9600224500 # number of overall MSHR miss cycles 973system.cpu.l2cache.overall_mshr_miss_latency::total 10514702500 # number of overall MSHR miss cycles 974system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 87522404500 # number of ReadReq MSHR uncacheable cycles 975system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 87522404500 # number of ReadReq MSHR uncacheable cycles 976system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2462213500 # number of WriteReq MSHR uncacheable cycles 977system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2462213500 # number of WriteReq MSHR uncacheable cycles 978system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 89984618000 # number of overall MSHR uncacheable cycles 979system.cpu.l2cache.overall_mshr_uncacheable_latency::total 89984618000 # number of overall MSHR uncacheable cycles 980system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 981system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 982system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.816607 # mshr miss rate for UpgradeReq accesses 983system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.816607 # mshr miss rate for UpgradeReq accesses 984system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.362897 # mshr miss rate for ReadExReq accesses 985system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.362897 # mshr miss rate for ReadExReq accesses 986system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.016261 # mshr miss rate for ReadCleanReq accesses 987system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.016261 # mshr miss rate for ReadCleanReq accesses 988system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker 0.001654 # mshr miss rate for ReadSharedReq accesses 989system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.021783 # mshr miss rate for ReadSharedReq accesses 990system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.021625 # mshr miss rate for ReadSharedReq accesses 991system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001654 # mshr miss rate for demand accesses 992system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016261 # mshr miss rate for demand accesses 993system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087769 # mshr miss rate for demand accesses 994system.cpu.l2cache.demand_mshr_miss_rate::total 0.064017 # mshr miss rate for demand accesses 995system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001654 # mshr miss rate for overall accesses 996system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016261 # mshr miss rate for overall accesses 997system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087769 # mshr miss rate for overall accesses 998system.cpu.l2cache.overall_mshr_miss_rate::total 0.064017 # mshr miss rate for overall accesses 999system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 21240.673007 # average UpgradeReq mshr miss latency 1000system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21240.673007 # average UpgradeReq mshr miss latency 1001system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66412.599643 # average ReadExReq mshr miss latency 1002system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66412.599643 # average ReadExReq mshr miss latency 1003system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70879.002869 # average ReadCleanReq mshr miss latency 1004system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70879.002869 # average ReadCleanReq mshr miss latency 1005system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker 70300 # average ReadSharedReq mshr miss latency 1006system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71770.350471 # average ReadSharedReq mshr miss latency 1007system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71770.092342 # average ReadSharedReq mshr miss latency 1008system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 70300 # average overall mshr miss latency 1009system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70879.002869 # average overall mshr miss latency 1010system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67485.076306 # average overall mshr miss latency 1011system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67767.274215 # average overall mshr miss latency 1012system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 70300 # average overall mshr miss latency 1013system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70879.002869 # average overall mshr miss latency 1014system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67485.076306 # average overall mshr miss latency 1015system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67767.274215 # average overall mshr miss latency 1016system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 152756.424600 # average ReadReq mshr uncacheable latency 1017system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 152756.424600 # average ReadReq mshr uncacheable latency 1018system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 176933.996838 # average WriteReq mshr uncacheable latency 1019system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 176933.996838 # average WriteReq mshr uncacheable latency 1020system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 153329.728901 # average overall mshr uncacheable latency 1021system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 153329.728901 # average overall mshr uncacheable latency 1022system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1023system.cpu.toL2Bus.trans_dist::ReadReq 572954 # Transaction distribution 1024system.cpu.toL2Bus.trans_dist::ReadResp 2687857 # Transaction distribution 1025system.cpu.toL2Bus.trans_dist::WriteReq 13916 # Transaction distribution 1026system.cpu.toL2Bus.trans_dist::WriteResp 13916 # Transaction distribution 1027system.cpu.toL2Bus.trans_dist::Writeback 1668857 # Transaction distribution 1028system.cpu.toL2Bus.trans_dist::CleanEvict 884964 # Transaction distribution 1029system.cpu.toL2Bus.trans_dist::UpgradeReq 2182 # Transaction distribution 1030system.cpu.toL2Bus.trans_dist::UpgradeResp 2182 # Transaction distribution 1031system.cpu.toL2Bus.trans_dist::ReadExReq 313540 # Transaction distribution 1032system.cpu.toL2Bus.trans_dist::ReadExResp 313540 # Transaction distribution 1033system.cpu.toL2Bus.trans_dist::ReadCleanReq 793156 # Transaction distribution 1034system.cpu.toL2Bus.trans_dist::ReadSharedReq 1322272 # Transaction distribution 1035system.cpu.toL2Bus.trans_dist::MessageReq 1652 # Transaction distribution 1036system.cpu.toL2Bus.trans_dist::InvalidateReq 46720 # Transaction distribution 1037system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2378925 # Packet count per connected master and slave (bytes) 1038system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6040657 # Packet count per connected master and slave (bytes) 1039system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 8974 # Packet count per connected master and slave (bytes) 1040system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 20226 # Packet count per connected master and slave (bytes) 1041system.cpu.toL2Bus.pkt_count::total 8448782 # Packet count per connected master and slave (bytes) 1042system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50761152 # Cumulative packet size per connected master and slave (bytes) 1043system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 203819691 # Cumulative packet size per connected master and slave (bytes) 1044system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 244416 # Cumulative packet size per connected master and slave (bytes) 1045system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 629120 # Cumulative packet size per connected master and slave (bytes) 1046system.cpu.toL2Bus.pkt_size::total 255454379 # Cumulative packet size per connected master and slave (bytes) 1047system.cpu.toL2Bus.snoops 189246 # Total snoops (count) 1048system.cpu.toL2Bus.snoop_fanout::samples 5626152 # Request fanout histogram 1049system.cpu.toL2Bus.snoop_fanout::mean 3.032703 # Request fanout histogram 1050system.cpu.toL2Bus.snoop_fanout::stdev 0.177859 # Request fanout histogram 1051system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1052system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1053system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1054system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1055system.cpu.toL2Bus.snoop_fanout::3 5442159 96.73% 96.73% # Request fanout histogram 1056system.cpu.toL2Bus.snoop_fanout::4 183993 3.27% 100.00% # Request fanout histogram 1057system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1058system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 1059system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram 1060system.cpu.toL2Bus.snoop_fanout::total 5626152 # Request fanout histogram 1061system.cpu.toL2Bus.reqLayer0.occupancy 4269812500 # Layer occupancy (ticks) 1062system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1063system.cpu.toL2Bus.snoopLayer0.occupancy 480000 # Layer occupancy (ticks) 1064system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1065system.cpu.toL2Bus.respLayer0.occupancy 1189734000 # Layer occupancy (ticks) 1066system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1067system.cpu.toL2Bus.respLayer1.occupancy 3013374987 # Layer occupancy (ticks) 1068system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1069system.cpu.toL2Bus.respLayer2.occupancy 6600000 # Layer occupancy (ticks) 1070system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1071system.cpu.toL2Bus.respLayer3.occupancy 13485000 # Layer occupancy (ticks) 1072system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1073system.iobus.trans_dist::ReadReq 226549 # Transaction distribution 1074system.iobus.trans_dist::ReadResp 226549 # Transaction distribution 1075system.iobus.trans_dist::WriteReq 57726 # Transaction distribution 1076system.iobus.trans_dist::WriteResp 57726 # Transaction distribution 1077system.iobus.trans_dist::MessageReq 1652 # Transaction distribution 1078system.iobus.trans_dist::MessageResp 1652 # Transaction distribution 1079system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) 1080system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) 1081system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes) 1082system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) 1083system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) 1084system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) 1085system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) 1086system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) 1087system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 429188 # Packet count per connected master and slave (bytes) 1088system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) 1089system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes) 1090system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) 1091system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27824 # Packet count per connected master and slave (bytes) 1092system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) 1093system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) 1094system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) 1095system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) 1096system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) 1097system.iobus.pkt_count_system.bridge.master::total 473420 # Packet count per connected master and slave (bytes) 1098system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95130 # Packet count per connected master and slave (bytes) 1099system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95130 # Packet count per connected master and slave (bytes) 1100system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3304 # Packet count per connected master and slave (bytes) 1101system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3304 # Packet count per connected master and slave (bytes) 1102system.iobus.pkt_count::total 571854 # Packet count per connected master and slave (bytes) 1103system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) 1104system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) 1105system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) 1106system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) 1107system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) 1108system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) 1109system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) 1110system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) 1111system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 214594 # Cumulative packet size per connected master and slave (bytes) 1112system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) 1113system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes) 1114system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) 1115system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13912 # Cumulative packet size per connected master and slave (bytes) 1116system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) 1117system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) 1118system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) 1119system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) 1120system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) 1121system.iobus.pkt_size_system.bridge.master::total 242990 # Cumulative packet size per connected master and slave (bytes) 1122system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027304 # Cumulative packet size per connected master and slave (bytes) 1123system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027304 # Cumulative packet size per connected master and slave (bytes) 1124system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6608 # Cumulative packet size per connected master and slave (bytes) 1125system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6608 # Cumulative packet size per connected master and slave (bytes) 1126system.iobus.pkt_size::total 3276902 # Cumulative packet size per connected master and slave (bytes) 1127system.iobus.reqLayer0.occupancy 3939784 # Layer occupancy (ticks) 1128system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1129system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) 1130system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1131system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) 1132system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1133system.iobus.reqLayer3.occupancy 8813000 # Layer occupancy (ticks) 1134system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1135system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) 1136system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 1137system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks) 1138system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) 1139system.iobus.reqLayer6.occupancy 77000 # Layer occupancy (ticks) 1140system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1141system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks) 1142system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 1143system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks) 1144system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 1145system.iobus.reqLayer9.occupancy 214595000 # Layer occupancy (ticks) 1146system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) 1147system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks) 1148system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1149system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks) 1150system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) 1151system.iobus.reqLayer13.occupancy 2000 # Layer occupancy (ticks) 1152system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1153system.iobus.reqLayer14.occupancy 20815000 # Layer occupancy (ticks) 1154system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1155system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) 1156system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1157system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) 1158system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1159system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks) 1160system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1161system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) 1162system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 1163system.iobus.reqLayer19.occupancy 242362178 # Layer occupancy (ticks) 1164system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 1165system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks) 1166system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 1167system.iobus.respLayer0.occupancy 462414000 # Layer occupancy (ticks) 1168system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1169system.iobus.respLayer1.occupancy 50042000 # Layer occupancy (ticks) 1170system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 1171system.iobus.respLayer2.occupancy 1652000 # Layer occupancy (ticks) 1172system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) 1173system.iocache.tags.replacements 47510 # number of replacements 1174system.iocache.tags.tagsinuse 0.095938 # Cycle average of tags in use 1175system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1176system.iocache.tags.sampled_refs 47526 # Sample count of references to valid blocks. 1177system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1178system.iocache.tags.warmup_cycle 5046145075000 # Cycle when the warmup percentage was hit. 1179system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.095938 # Average occupied blocks per requestor 1180system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005996 # Average percentage of cache occupancy 1181system.iocache.tags.occ_percent::total 0.005996 # Average percentage of cache occupancy 1182system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1183system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 1184system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1185system.iocache.tags.tag_accesses 428085 # Number of tag accesses 1186system.iocache.tags.data_accesses 428085 # Number of data accesses 1187system.iocache.ReadReq_misses::pc.south_bridge.ide 845 # number of ReadReq misses 1188system.iocache.ReadReq_misses::total 845 # number of ReadReq misses 1189system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses 1190system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses 1191system.iocache.demand_misses::pc.south_bridge.ide 845 # number of demand (read+write) misses 1192system.iocache.demand_misses::total 845 # number of demand (read+write) misses 1193system.iocache.overall_misses::pc.south_bridge.ide 845 # number of overall misses 1194system.iocache.overall_misses::total 845 # number of overall misses 1195system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 134017694 # number of ReadReq miss cycles 1196system.iocache.ReadReq_miss_latency::total 134017694 # number of ReadReq miss cycles 1197system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 5509470484 # number of WriteLineReq miss cycles 1198system.iocache.WriteLineReq_miss_latency::total 5509470484 # number of WriteLineReq miss cycles 1199system.iocache.demand_miss_latency::pc.south_bridge.ide 134017694 # number of demand (read+write) miss cycles 1200system.iocache.demand_miss_latency::total 134017694 # number of demand (read+write) miss cycles 1201system.iocache.overall_miss_latency::pc.south_bridge.ide 134017694 # number of overall miss cycles 1202system.iocache.overall_miss_latency::total 134017694 # number of overall miss cycles 1203system.iocache.ReadReq_accesses::pc.south_bridge.ide 845 # number of ReadReq accesses(hits+misses) 1204system.iocache.ReadReq_accesses::total 845 # number of ReadReq accesses(hits+misses) 1205system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses) 1206system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses) 1207system.iocache.demand_accesses::pc.south_bridge.ide 845 # number of demand (read+write) accesses 1208system.iocache.demand_accesses::total 845 # number of demand (read+write) accesses 1209system.iocache.overall_accesses::pc.south_bridge.ide 845 # number of overall (read+write) accesses 1210system.iocache.overall_accesses::total 845 # number of overall (read+write) accesses 1211system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 1212system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1213system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses 1214system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1215system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 1216system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1217system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 1218system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1219system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 158600.821302 # average ReadReq miss latency 1220system.iocache.ReadReq_avg_miss_latency::total 158600.821302 # average ReadReq miss latency 1221system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 117925.310017 # average WriteLineReq miss latency 1222system.iocache.WriteLineReq_avg_miss_latency::total 117925.310017 # average WriteLineReq miss latency 1223system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 158600.821302 # average overall miss latency 1224system.iocache.demand_avg_miss_latency::total 158600.821302 # average overall miss latency 1225system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 158600.821302 # average overall miss latency 1226system.iocache.overall_avg_miss_latency::total 158600.821302 # average overall miss latency 1227system.iocache.blocked_cycles::no_mshrs 341 # number of cycles access was blocked 1228system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1229system.iocache.blocked::no_mshrs 28 # number of cycles access was blocked 1230system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1231system.iocache.avg_blocked_cycles::no_mshrs 12.178571 # average number of cycles each access was blocked 1232system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1233system.iocache.fast_writes 0 # number of fast writes performed 1234system.iocache.cache_copies 0 # number of cache copies performed 1235system.iocache.writebacks::writebacks 46667 # number of writebacks 1236system.iocache.writebacks::total 46667 # number of writebacks 1237system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 845 # number of ReadReq MSHR misses 1238system.iocache.ReadReq_mshr_misses::total 845 # number of ReadReq MSHR misses 1239system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteLineReq MSHR misses 1240system.iocache.WriteLineReq_mshr_misses::total 46720 # number of WriteLineReq MSHR misses 1241system.iocache.demand_mshr_misses::pc.south_bridge.ide 845 # number of demand (read+write) MSHR misses 1242system.iocache.demand_mshr_misses::total 845 # number of demand (read+write) MSHR misses 1243system.iocache.overall_mshr_misses::pc.south_bridge.ide 845 # number of overall MSHR misses 1244system.iocache.overall_mshr_misses::total 845 # number of overall MSHR misses 1245system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 91767694 # number of ReadReq MSHR miss cycles 1246system.iocache.ReadReq_mshr_miss_latency::total 91767694 # number of ReadReq MSHR miss cycles 1247system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3173470484 # number of WriteLineReq MSHR miss cycles 1248system.iocache.WriteLineReq_mshr_miss_latency::total 3173470484 # number of WriteLineReq MSHR miss cycles 1249system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 91767694 # number of demand (read+write) MSHR miss cycles 1250system.iocache.demand_mshr_miss_latency::total 91767694 # number of demand (read+write) MSHR miss cycles 1251system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 91767694 # number of overall MSHR miss cycles 1252system.iocache.overall_mshr_miss_latency::total 91767694 # number of overall MSHR miss cycles 1253system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 1254system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1255system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteLineReq accesses 1256system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1257system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 1258system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1259system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 1260system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1261system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 108600.821302 # average ReadReq mshr miss latency 1262system.iocache.ReadReq_avg_mshr_miss_latency::total 108600.821302 # average ReadReq mshr miss latency 1263system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 67925.310017 # average WriteLineReq mshr miss latency 1264system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67925.310017 # average WriteLineReq mshr miss latency 1265system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 108600.821302 # average overall mshr miss latency 1266system.iocache.demand_avg_mshr_miss_latency::total 108600.821302 # average overall mshr miss latency 1267system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 108600.821302 # average overall mshr miss latency 1268system.iocache.overall_avg_mshr_miss_latency::total 108600.821302 # average overall mshr miss latency 1269system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1270system.membus.trans_dist::ReadReq 572954 # Transaction distribution 1271system.membus.trans_dist::ReadResp 615177 # Transaction distribution 1272system.membus.trans_dist::WriteReq 13916 # Transaction distribution 1273system.membus.trans_dist::WriteResp 13916 # Transaction distribution 1274system.membus.trans_dist::Writeback 127079 # Transaction distribution 1275system.membus.trans_dist::CleanEvict 7222 # Transaction distribution 1276system.membus.trans_dist::UpgradeReq 2154 # Transaction distribution 1277system.membus.trans_dist::UpgradeResp 1646 # Transaction distribution 1278system.membus.trans_dist::ReadExReq 113502 # Transaction distribution 1279system.membus.trans_dist::ReadExResp 113502 # Transaction distribution 1280system.membus.trans_dist::ReadSharedReq 42223 # Transaction distribution 1281system.membus.trans_dist::MessageReq 1652 # Transaction distribution 1282system.membus.trans_dist::MessageResp 1652 # Transaction distribution 1283system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution 1284system.membus.trans_dist::InvalidateResp 46720 # Transaction distribution 1285system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3304 # Packet count per connected master and slave (bytes) 1286system.membus.pkt_count_system.apicbridge.master::total 3304 # Packet count per connected master and slave (bytes) 1287system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 473420 # Packet count per connected master and slave (bytes) 1288system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 700320 # Packet count per connected master and slave (bytes) 1289system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 400152 # Packet count per connected master and slave (bytes) 1290system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1573892 # Packet count per connected master and slave (bytes) 1291system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141767 # Packet count per connected master and slave (bytes) 1292system.membus.pkt_count_system.iocache.mem_side::total 141767 # Packet count per connected master and slave (bytes) 1293system.membus.pkt_count::total 1718963 # Packet count per connected master and slave (bytes) 1294system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6608 # Cumulative packet size per connected master and slave (bytes) 1295system.membus.pkt_size_system.apicbridge.master::total 6608 # Cumulative packet size per connected master and slave (bytes) 1296system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 242990 # Cumulative packet size per connected master and slave (bytes) 1297system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1400637 # Cumulative packet size per connected master and slave (bytes) 1298system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15016960 # Cumulative packet size per connected master and slave (bytes) 1299system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16660587 # Cumulative packet size per connected master and slave (bytes) 1300system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3015040 # Cumulative packet size per connected master and slave (bytes) 1301system.membus.pkt_size_system.iocache.mem_side::total 3015040 # Cumulative packet size per connected master and slave (bytes) 1302system.membus.pkt_size::total 19682235 # Cumulative packet size per connected master and slave (bytes) 1303system.membus.snoops 1580 # Total snoops (count) 1304system.membus.snoop_fanout::samples 927896 # Request fanout histogram 1305system.membus.snoop_fanout::mean 1.001780 # Request fanout histogram 1306system.membus.snoop_fanout::stdev 0.042157 # Request fanout histogram 1307system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1308system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1309system.membus.snoop_fanout::1 926244 99.82% 99.82% # Request fanout histogram 1310system.membus.snoop_fanout::2 1652 0.18% 100.00% # Request fanout histogram 1311system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1312system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1313system.membus.snoop_fanout::max_value 2 # Request fanout histogram 1314system.membus.snoop_fanout::total 927896 # Request fanout histogram 1315system.membus.reqLayer0.occupancy 359896000 # Layer occupancy (ticks) 1316system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1317system.membus.reqLayer1.occupancy 527973000 # Layer occupancy (ticks) 1318system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1319system.membus.reqLayer2.occupancy 3304000 # Layer occupancy (ticks) 1320system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1321system.membus.reqLayer3.occupancy 848970266 # Layer occupancy (ticks) 1322system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) 1323system.membus.respLayer0.occupancy 1652000 # Layer occupancy (ticks) 1324system.membus.respLayer0.utilization 0.0 # Layer utilization (%) 1325system.membus.respLayer2.occupancy 2157850870 # Layer occupancy (ticks) 1326system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1327system.membus.respLayer4.occupancy 85904679 # Layer occupancy (ticks) 1328system.membus.respLayer4.utilization 0.0 # Layer utilization (%) 1329system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1330system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 1331system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). 1332system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 1333system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 1334system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 1335system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1336system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1337system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1338system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 1339system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 1340system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 1341 1342---------- End Simulation Statistics ---------- 1343