stats.txt revision 8802:ef66a9083bc4
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.112043 # Number of seconds simulated 4sim_ticks 5112043255000 # Number of ticks simulated 5final_tick 5112043255000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 2850135 # Simulator instruction rate (inst/s) 8host_tick_rate 35611898535 # Simulator tick rate (ticks/s) 9host_mem_usage 353172 # Number of bytes of host memory used 10host_seconds 143.55 # Real time elapsed on the host 11sim_insts 409133277 # Number of instructions simulated 12system.physmem.bytes_read 15568704 # Number of bytes read from this memory 13system.physmem.bytes_inst_read 972736 # Number of instructions bytes read from this memory 14system.physmem.bytes_written 12232896 # Number of bytes written to this memory 15system.physmem.num_reads 243261 # Number of read requests responded to by this memory 16system.physmem.num_writes 191139 # Number of write requests responded to by this memory 17system.physmem.num_other 0 # Number of other requests responded to by this memory 18system.physmem.bw_read 3045495 # Total read bandwidth from this memory (bytes/s) 19system.physmem.bw_inst_read 190283 # Instruction read bandwidth from this memory (bytes/s) 20system.physmem.bw_write 2392956 # Write bandwidth from this memory (bytes/s) 21system.physmem.bw_total 5438452 # Total bandwidth to/from this memory (bytes/s) 22system.l2c.replacements 164044 # number of replacements 23system.l2c.tagsinuse 36842.944085 # Cycle average of tags in use 24system.l2c.total_refs 3332458 # Total number of references to valid blocks. 25system.l2c.sampled_refs 196390 # Sample count of references to valid blocks. 26system.l2c.avg_refs 16.968573 # Average number of references to valid blocks. 27system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 28system.l2c.occ_blocks::0 9701.563280 # Average occupied blocks per context 29system.l2c.occ_blocks::1 27141.380805 # Average occupied blocks per context 30system.l2c.occ_percent::0 0.148034 # Average percentage of cache occupancy 31system.l2c.occ_percent::1 0.414145 # Average percentage of cache occupancy 32system.l2c.ReadReq_hits::0 2042917 # number of ReadReq hits 33system.l2c.ReadReq_hits::1 9538 # number of ReadReq hits 34system.l2c.ReadReq_hits::total 2052455 # number of ReadReq hits 35system.l2c.Writeback_hits::0 1529403 # number of Writeback hits 36system.l2c.Writeback_hits::total 1529403 # number of Writeback hits 37system.l2c.UpgradeReq_hits::0 31 # number of UpgradeReq hits 38system.l2c.UpgradeReq_hits::total 31 # number of UpgradeReq hits 39system.l2c.ReadExReq_hits::0 168948 # number of ReadExReq hits 40system.l2c.ReadExReq_hits::total 168948 # number of ReadExReq hits 41system.l2c.demand_hits::0 2211865 # number of demand (read+write) hits 42system.l2c.demand_hits::1 9538 # number of demand (read+write) hits 43system.l2c.demand_hits::total 2221403 # number of demand (read+write) hits 44system.l2c.overall_hits::0 2211865 # number of overall hits 45system.l2c.overall_hits::1 9538 # number of overall hits 46system.l2c.overall_hits::total 2221403 # number of overall hits 47system.l2c.ReadReq_misses::0 55972 # number of ReadReq misses 48system.l2c.ReadReq_misses::1 27 # number of ReadReq misses 49system.l2c.ReadReq_misses::total 55999 # number of ReadReq misses 50system.l2c.UpgradeReq_misses::0 1792 # number of UpgradeReq misses 51system.l2c.UpgradeReq_misses::total 1792 # number of UpgradeReq misses 52system.l2c.ReadExReq_misses::0 144639 # number of ReadExReq misses 53system.l2c.ReadExReq_misses::total 144639 # number of ReadExReq misses 54system.l2c.demand_misses::0 200611 # number of demand (read+write) misses 55system.l2c.demand_misses::1 27 # number of demand (read+write) misses 56system.l2c.demand_misses::total 200638 # number of demand (read+write) misses 57system.l2c.overall_misses::0 200611 # number of overall misses 58system.l2c.overall_misses::1 27 # number of overall misses 59system.l2c.overall_misses::total 200638 # number of overall misses 60system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles 61system.l2c.overall_miss_latency 0 # number of overall miss cycles 62system.l2c.ReadReq_accesses::0 2098889 # number of ReadReq accesses(hits+misses) 63system.l2c.ReadReq_accesses::1 9565 # number of ReadReq accesses(hits+misses) 64system.l2c.ReadReq_accesses::total 2108454 # number of ReadReq accesses(hits+misses) 65system.l2c.Writeback_accesses::0 1529403 # number of Writeback accesses(hits+misses) 66system.l2c.Writeback_accesses::total 1529403 # number of Writeback accesses(hits+misses) 67system.l2c.UpgradeReq_accesses::0 1823 # number of UpgradeReq accesses(hits+misses) 68system.l2c.UpgradeReq_accesses::total 1823 # number of UpgradeReq accesses(hits+misses) 69system.l2c.ReadExReq_accesses::0 313587 # number of ReadExReq accesses(hits+misses) 70system.l2c.ReadExReq_accesses::total 313587 # number of ReadExReq accesses(hits+misses) 71system.l2c.demand_accesses::0 2412476 # number of demand (read+write) accesses 72system.l2c.demand_accesses::1 9565 # number of demand (read+write) accesses 73system.l2c.demand_accesses::total 2422041 # number of demand (read+write) accesses 74system.l2c.overall_accesses::0 2412476 # number of overall (read+write) accesses 75system.l2c.overall_accesses::1 9565 # number of overall (read+write) accesses 76system.l2c.overall_accesses::total 2422041 # number of overall (read+write) accesses 77system.l2c.ReadReq_miss_rate::0 0.026667 # miss rate for ReadReq accesses 78system.l2c.ReadReq_miss_rate::1 0.002823 # miss rate for ReadReq accesses 79system.l2c.ReadReq_miss_rate::total 0.029490 # miss rate for ReadReq accesses 80system.l2c.UpgradeReq_miss_rate::0 0.982995 # miss rate for UpgradeReq accesses 81system.l2c.ReadExReq_miss_rate::0 0.461240 # miss rate for ReadExReq accesses 82system.l2c.demand_miss_rate::0 0.083156 # miss rate for demand accesses 83system.l2c.demand_miss_rate::1 0.002823 # miss rate for demand accesses 84system.l2c.demand_miss_rate::total 0.085978 # miss rate for demand accesses 85system.l2c.overall_miss_rate::0 0.083156 # miss rate for overall accesses 86system.l2c.overall_miss_rate::1 0.002823 # miss rate for overall accesses 87system.l2c.overall_miss_rate::total 0.085978 # miss rate for overall accesses 88system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency 89system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency 90system.l2c.demand_avg_miss_latency::total 0 # average overall miss latency 91system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency 92system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency 93system.l2c.overall_avg_miss_latency::total 0 # average overall miss latency 94system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 95system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 96system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 97system.l2c.blocked::no_targets 0 # number of cycles access was blocked 98system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 99system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 100system.l2c.fast_writes 0 # number of fast writes performed 101system.l2c.cache_copies 0 # number of cache copies performed 102system.l2c.writebacks 144472 # number of writebacks 103system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 104system.l2c.overall_mshr_hits 0 # number of overall MSHR hits 105system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 106system.l2c.overall_mshr_misses 0 # number of overall MSHR misses 107system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 108system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 109system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 110system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 111system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses 112system.l2c.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses 113system.l2c.demand_mshr_miss_rate::total 0 # mshr miss rate for demand accesses 114system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses 115system.l2c.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses 116system.l2c.overall_mshr_miss_rate::total 0 # mshr miss rate for overall accesses 117system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 118system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 119system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 120system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated 121system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 122system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 123system.iocache.replacements 47570 # number of replacements 124system.iocache.tagsinuse 0.042409 # Cycle average of tags in use 125system.iocache.total_refs 0 # Total number of references to valid blocks. 126system.iocache.sampled_refs 47586 # Sample count of references to valid blocks. 127system.iocache.avg_refs 0 # Average number of references to valid blocks. 128system.iocache.warmup_cycle 4994776740009 # Cycle when the warmup percentage was hit. 129system.iocache.occ_blocks::1 0.042409 # Average occupied blocks per context 130system.iocache.occ_percent::1 0.002651 # Average percentage of cache occupancy 131system.iocache.demand_hits::0 0 # number of demand (read+write) hits 132system.iocache.demand_hits::1 0 # number of demand (read+write) hits 133system.iocache.demand_hits::total 0 # number of demand (read+write) hits 134system.iocache.overall_hits::0 0 # number of overall hits 135system.iocache.overall_hits::1 0 # number of overall hits 136system.iocache.overall_hits::total 0 # number of overall hits 137system.iocache.ReadReq_misses::1 905 # number of ReadReq misses 138system.iocache.ReadReq_misses::total 905 # number of ReadReq misses 139system.iocache.WriteReq_misses::1 46720 # number of WriteReq misses 140system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses 141system.iocache.demand_misses::0 0 # number of demand (read+write) misses 142system.iocache.demand_misses::1 47625 # number of demand (read+write) misses 143system.iocache.demand_misses::total 47625 # number of demand (read+write) misses 144system.iocache.overall_misses::0 0 # number of overall misses 145system.iocache.overall_misses::1 47625 # number of overall misses 146system.iocache.overall_misses::total 47625 # number of overall misses 147system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles 148system.iocache.overall_miss_latency 0 # number of overall miss cycles 149system.iocache.ReadReq_accesses::1 905 # number of ReadReq accesses(hits+misses) 150system.iocache.ReadReq_accesses::total 905 # number of ReadReq accesses(hits+misses) 151system.iocache.WriteReq_accesses::1 46720 # number of WriteReq accesses(hits+misses) 152system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) 153system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses 154system.iocache.demand_accesses::1 47625 # number of demand (read+write) accesses 155system.iocache.demand_accesses::total 47625 # number of demand (read+write) accesses 156system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses 157system.iocache.overall_accesses::1 47625 # number of overall (read+write) accesses 158system.iocache.overall_accesses::total 47625 # number of overall (read+write) accesses 159system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses 160system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses 161system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses 162system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses 163system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses 164system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses 165system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses 166system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses 167system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency 168system.iocache.demand_avg_miss_latency::1 0 # average overall miss latency 169system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency 170system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency 171system.iocache.overall_avg_miss_latency::1 0 # average overall miss latency 172system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency 173system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 174system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 175system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 176system.iocache.blocked::no_targets 0 # number of cycles access was blocked 177system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 178system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 179system.iocache.fast_writes 0 # number of fast writes performed 180system.iocache.cache_copies 0 # number of cache copies performed 181system.iocache.writebacks 46667 # number of writebacks 182system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 183system.iocache.overall_mshr_hits 0 # number of overall MSHR hits 184system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 185system.iocache.overall_mshr_misses 0 # number of overall MSHR misses 186system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 187system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 188system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 189system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 190system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses 191system.iocache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses 192system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses 193system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses 194system.iocache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses 195system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses 196system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 197system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 198system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 199system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated 200system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 201system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 202system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 203system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 204system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). 205system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 206system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 207system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 208system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 209system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 210system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 211system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 212system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 213system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 214system.cpu.numCycles 10224086531 # number of cpu cycles simulated 215system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 216system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 217system.cpu.num_insts 409133277 # Number of instructions executed 218system.cpu.num_int_alu_accesses 374297244 # Number of integer alu accesses 219system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 220system.cpu.num_func_calls 0 # number of times a function call or return occured 221system.cpu.num_conditional_control_insts 39954968 # number of instructions that are conditional controls 222system.cpu.num_int_insts 374297244 # number of integer instructions 223system.cpu.num_fp_insts 0 # number of float instructions 224system.cpu.num_int_register_reads 801267455 # number of times the integer registers were read 225system.cpu.num_int_register_writes 401624559 # number of times the integer registers were written 226system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 227system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 228system.cpu.num_mem_refs 35626519 # number of memory refs 229system.cpu.num_load_insts 27217784 # Number of load instructions 230system.cpu.num_store_insts 8408735 # Number of store instructions 231system.cpu.num_idle_cycles 9770605338.086651 # Number of idle cycles 232system.cpu.num_busy_cycles 453481192.913350 # Number of busy cycles 233system.cpu.not_idle_fraction 0.044354 # Percentage of non-idle cycles 234system.cpu.idle_fraction 0.955646 # Percentage of idle cycles 235system.cpu.kern.inst.arm 0 # number of arm instructions executed 236system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 237system.cpu.icache.replacements 790795 # number of replacements 238system.cpu.icache.tagsinuse 510.627676 # Cycle average of tags in use 239system.cpu.icache.total_refs 243365777 # Total number of references to valid blocks. 240system.cpu.icache.sampled_refs 791307 # Sample count of references to valid blocks. 241system.cpu.icache.avg_refs 307.549127 # Average number of references to valid blocks. 242system.cpu.icache.warmup_cycle 148763105500 # Cycle when the warmup percentage was hit. 243system.cpu.icache.occ_blocks::0 510.627676 # Average occupied blocks per context 244system.cpu.icache.occ_percent::0 0.997320 # Average percentage of cache occupancy 245system.cpu.icache.ReadReq_hits::0 243365777 # number of ReadReq hits 246system.cpu.icache.ReadReq_hits::total 243365777 # number of ReadReq hits 247system.cpu.icache.demand_hits::0 243365777 # number of demand (read+write) hits 248system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits 249system.cpu.icache.demand_hits::total 243365777 # number of demand (read+write) hits 250system.cpu.icache.overall_hits::0 243365777 # number of overall hits 251system.cpu.icache.overall_hits::1 0 # number of overall hits 252system.cpu.icache.overall_hits::total 243365777 # number of overall hits 253system.cpu.icache.ReadReq_misses::0 791314 # number of ReadReq misses 254system.cpu.icache.ReadReq_misses::total 791314 # number of ReadReq misses 255system.cpu.icache.demand_misses::0 791314 # number of demand (read+write) misses 256system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses 257system.cpu.icache.demand_misses::total 791314 # number of demand (read+write) misses 258system.cpu.icache.overall_misses::0 791314 # number of overall misses 259system.cpu.icache.overall_misses::1 0 # number of overall misses 260system.cpu.icache.overall_misses::total 791314 # number of overall misses 261system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles 262system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles 263system.cpu.icache.ReadReq_accesses::0 244157091 # number of ReadReq accesses(hits+misses) 264system.cpu.icache.ReadReq_accesses::total 244157091 # number of ReadReq accesses(hits+misses) 265system.cpu.icache.demand_accesses::0 244157091 # number of demand (read+write) accesses 266system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses 267system.cpu.icache.demand_accesses::total 244157091 # number of demand (read+write) accesses 268system.cpu.icache.overall_accesses::0 244157091 # number of overall (read+write) accesses 269system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses 270system.cpu.icache.overall_accesses::total 244157091 # number of overall (read+write) accesses 271system.cpu.icache.ReadReq_miss_rate::0 0.003241 # miss rate for ReadReq accesses 272system.cpu.icache.demand_miss_rate::0 0.003241 # miss rate for demand accesses 273system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses 274system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses 275system.cpu.icache.overall_miss_rate::0 0.003241 # miss rate for overall accesses 276system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses 277system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses 278system.cpu.icache.demand_avg_miss_latency::0 0 # average overall miss latency 279system.cpu.icache.demand_avg_miss_latency::1 no_value # average overall miss latency 280system.cpu.icache.demand_avg_miss_latency::total no_value # average overall miss latency 281system.cpu.icache.overall_avg_miss_latency::0 0 # average overall miss latency 282system.cpu.icache.overall_avg_miss_latency::1 no_value # average overall miss latency 283system.cpu.icache.overall_avg_miss_latency::total no_value # average overall miss latency 284system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 285system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 286system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 287system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 288system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 289system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 290system.cpu.icache.fast_writes 0 # number of fast writes performed 291system.cpu.icache.cache_copies 0 # number of cache copies performed 292system.cpu.icache.writebacks 809 # number of writebacks 293system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 294system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits 295system.cpu.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 296system.cpu.icache.overall_mshr_misses 0 # number of overall MSHR misses 297system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 298system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 299system.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 300system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 301system.cpu.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses 302system.cpu.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses 303system.cpu.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses 304system.cpu.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses 305system.cpu.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses 306system.cpu.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses 307system.cpu.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 308system.cpu.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 309system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 310system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated 311system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 312system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 313system.cpu.itb_walker_cache.replacements 3435 # number of replacements 314system.cpu.itb_walker_cache.tagsinuse 3.021701 # Cycle average of tags in use 315system.cpu.itb_walker_cache.total_refs 7940 # Total number of references to valid blocks. 316system.cpu.itb_walker_cache.sampled_refs 3444 # Sample count of references to valid blocks. 317system.cpu.itb_walker_cache.avg_refs 2.305459 # Average number of references to valid blocks. 318system.cpu.itb_walker_cache.warmup_cycle 5105275407500 # Cycle when the warmup percentage was hit. 319system.cpu.itb_walker_cache.occ_blocks::1 3.021701 # Average occupied blocks per context 320system.cpu.itb_walker_cache.occ_percent::1 0.188856 # Average percentage of cache occupancy 321system.cpu.itb_walker_cache.ReadReq_hits::1 7947 # number of ReadReq hits 322system.cpu.itb_walker_cache.ReadReq_hits::total 7947 # number of ReadReq hits 323system.cpu.itb_walker_cache.WriteReq_hits::1 2 # number of WriteReq hits 324system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits 325system.cpu.itb_walker_cache.demand_hits::0 0 # number of demand (read+write) hits 326system.cpu.itb_walker_cache.demand_hits::1 7949 # number of demand (read+write) hits 327system.cpu.itb_walker_cache.demand_hits::total 7949 # number of demand (read+write) hits 328system.cpu.itb_walker_cache.overall_hits::0 0 # number of overall hits 329system.cpu.itb_walker_cache.overall_hits::1 7949 # number of overall hits 330system.cpu.itb_walker_cache.overall_hits::total 7949 # number of overall hits 331system.cpu.itb_walker_cache.ReadReq_misses::1 4278 # number of ReadReq misses 332system.cpu.itb_walker_cache.ReadReq_misses::total 4278 # number of ReadReq misses 333system.cpu.itb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses 334system.cpu.itb_walker_cache.demand_misses::1 4278 # number of demand (read+write) misses 335system.cpu.itb_walker_cache.demand_misses::total 4278 # number of demand (read+write) misses 336system.cpu.itb_walker_cache.overall_misses::0 0 # number of overall misses 337system.cpu.itb_walker_cache.overall_misses::1 4278 # number of overall misses 338system.cpu.itb_walker_cache.overall_misses::total 4278 # number of overall misses 339system.cpu.itb_walker_cache.demand_miss_latency 0 # number of demand (read+write) miss cycles 340system.cpu.itb_walker_cache.overall_miss_latency 0 # number of overall miss cycles 341system.cpu.itb_walker_cache.ReadReq_accesses::1 12225 # number of ReadReq accesses(hits+misses) 342system.cpu.itb_walker_cache.ReadReq_accesses::total 12225 # number of ReadReq accesses(hits+misses) 343system.cpu.itb_walker_cache.WriteReq_accesses::1 2 # number of WriteReq accesses(hits+misses) 344system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) 345system.cpu.itb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses 346system.cpu.itb_walker_cache.demand_accesses::1 12227 # number of demand (read+write) accesses 347system.cpu.itb_walker_cache.demand_accesses::total 12227 # number of demand (read+write) accesses 348system.cpu.itb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses 349system.cpu.itb_walker_cache.overall_accesses::1 12227 # number of overall (read+write) accesses 350system.cpu.itb_walker_cache.overall_accesses::total 12227 # number of overall (read+write) accesses 351system.cpu.itb_walker_cache.ReadReq_miss_rate::1 0.349939 # miss rate for ReadReq accesses 352system.cpu.itb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses 353system.cpu.itb_walker_cache.demand_miss_rate::1 0.349881 # miss rate for demand accesses 354system.cpu.itb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses 355system.cpu.itb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses 356system.cpu.itb_walker_cache.overall_miss_rate::1 0.349881 # miss rate for overall accesses 357system.cpu.itb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses 358system.cpu.itb_walker_cache.demand_avg_miss_latency::0 no_value # average overall miss latency 359system.cpu.itb_walker_cache.demand_avg_miss_latency::1 0 # average overall miss latency 360system.cpu.itb_walker_cache.demand_avg_miss_latency::total no_value # average overall miss latency 361system.cpu.itb_walker_cache.overall_avg_miss_latency::0 no_value # average overall miss latency 362system.cpu.itb_walker_cache.overall_avg_miss_latency::1 0 # average overall miss latency 363system.cpu.itb_walker_cache.overall_avg_miss_latency::total no_value # average overall miss latency 364system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 365system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 366system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 367system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 368system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 369system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 370system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 371system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed 372system.cpu.itb_walker_cache.writebacks 518 # number of writebacks 373system.cpu.itb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 374system.cpu.itb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits 375system.cpu.itb_walker_cache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 376system.cpu.itb_walker_cache.overall_mshr_misses 0 # number of overall MSHR misses 377system.cpu.itb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 378system.cpu.itb_walker_cache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 379system.cpu.itb_walker_cache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 380system.cpu.itb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 381system.cpu.itb_walker_cache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses 382system.cpu.itb_walker_cache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses 383system.cpu.itb_walker_cache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses 384system.cpu.itb_walker_cache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses 385system.cpu.itb_walker_cache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses 386system.cpu.itb_walker_cache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses 387system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 388system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 389system.cpu.itb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 390system.cpu.itb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated 391system.cpu.itb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 392system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 393system.cpu.dtb_walker_cache.replacements 7755 # number of replacements 394system.cpu.dtb_walker_cache.tagsinuse 5.010998 # Cycle average of tags in use 395system.cpu.dtb_walker_cache.total_refs 12854 # Total number of references to valid blocks. 396system.cpu.dtb_walker_cache.sampled_refs 7767 # Sample count of references to valid blocks. 397system.cpu.dtb_walker_cache.avg_refs 1.654950 # Average number of references to valid blocks. 398system.cpu.dtb_walker_cache.warmup_cycle 5101232849000 # Cycle when the warmup percentage was hit. 399system.cpu.dtb_walker_cache.occ_blocks::1 5.010998 # Average occupied blocks per context 400system.cpu.dtb_walker_cache.occ_percent::1 0.313187 # Average percentage of cache occupancy 401system.cpu.dtb_walker_cache.ReadReq_hits::1 12875 # number of ReadReq hits 402system.cpu.dtb_walker_cache.ReadReq_hits::total 12875 # number of ReadReq hits 403system.cpu.dtb_walker_cache.demand_hits::0 0 # number of demand (read+write) hits 404system.cpu.dtb_walker_cache.demand_hits::1 12875 # number of demand (read+write) hits 405system.cpu.dtb_walker_cache.demand_hits::total 12875 # number of demand (read+write) hits 406system.cpu.dtb_walker_cache.overall_hits::0 0 # number of overall hits 407system.cpu.dtb_walker_cache.overall_hits::1 12875 # number of overall hits 408system.cpu.dtb_walker_cache.overall_hits::total 12875 # number of overall hits 409system.cpu.dtb_walker_cache.ReadReq_misses::1 8933 # number of ReadReq misses 410system.cpu.dtb_walker_cache.ReadReq_misses::total 8933 # number of ReadReq misses 411system.cpu.dtb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses 412system.cpu.dtb_walker_cache.demand_misses::1 8933 # number of demand (read+write) misses 413system.cpu.dtb_walker_cache.demand_misses::total 8933 # number of demand (read+write) misses 414system.cpu.dtb_walker_cache.overall_misses::0 0 # number of overall misses 415system.cpu.dtb_walker_cache.overall_misses::1 8933 # number of overall misses 416system.cpu.dtb_walker_cache.overall_misses::total 8933 # number of overall misses 417system.cpu.dtb_walker_cache.demand_miss_latency 0 # number of demand (read+write) miss cycles 418system.cpu.dtb_walker_cache.overall_miss_latency 0 # number of overall miss cycles 419system.cpu.dtb_walker_cache.ReadReq_accesses::1 21808 # number of ReadReq accesses(hits+misses) 420system.cpu.dtb_walker_cache.ReadReq_accesses::total 21808 # number of ReadReq accesses(hits+misses) 421system.cpu.dtb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses 422system.cpu.dtb_walker_cache.demand_accesses::1 21808 # number of demand (read+write) accesses 423system.cpu.dtb_walker_cache.demand_accesses::total 21808 # number of demand (read+write) accesses 424system.cpu.dtb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses 425system.cpu.dtb_walker_cache.overall_accesses::1 21808 # number of overall (read+write) accesses 426system.cpu.dtb_walker_cache.overall_accesses::total 21808 # number of overall (read+write) accesses 427system.cpu.dtb_walker_cache.ReadReq_miss_rate::1 0.409620 # miss rate for ReadReq accesses 428system.cpu.dtb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses 429system.cpu.dtb_walker_cache.demand_miss_rate::1 0.409620 # miss rate for demand accesses 430system.cpu.dtb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses 431system.cpu.dtb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses 432system.cpu.dtb_walker_cache.overall_miss_rate::1 0.409620 # miss rate for overall accesses 433system.cpu.dtb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses 434system.cpu.dtb_walker_cache.demand_avg_miss_latency::0 no_value # average overall miss latency 435system.cpu.dtb_walker_cache.demand_avg_miss_latency::1 0 # average overall miss latency 436system.cpu.dtb_walker_cache.demand_avg_miss_latency::total no_value # average overall miss latency 437system.cpu.dtb_walker_cache.overall_avg_miss_latency::0 no_value # average overall miss latency 438system.cpu.dtb_walker_cache.overall_avg_miss_latency::1 0 # average overall miss latency 439system.cpu.dtb_walker_cache.overall_avg_miss_latency::total no_value # average overall miss latency 440system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 441system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 442system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 443system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 444system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 445system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 446system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 447system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed 448system.cpu.dtb_walker_cache.writebacks 2517 # number of writebacks 449system.cpu.dtb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 450system.cpu.dtb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits 451system.cpu.dtb_walker_cache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 452system.cpu.dtb_walker_cache.overall_mshr_misses 0 # number of overall MSHR misses 453system.cpu.dtb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 454system.cpu.dtb_walker_cache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 455system.cpu.dtb_walker_cache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 456system.cpu.dtb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 457system.cpu.dtb_walker_cache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses 458system.cpu.dtb_walker_cache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses 459system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses 460system.cpu.dtb_walker_cache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses 461system.cpu.dtb_walker_cache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses 462system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses 463system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 464system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 465system.cpu.dtb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 466system.cpu.dtb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated 467system.cpu.dtb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 468system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 469system.cpu.dcache.replacements 1621277 # number of replacements 470system.cpu.dcache.tagsinuse 511.999417 # Cycle average of tags in use 471system.cpu.dcache.total_refs 20142220 # Total number of references to valid blocks. 472system.cpu.dcache.sampled_refs 1621789 # Sample count of references to valid blocks. 473system.cpu.dcache.avg_refs 12.419754 # Average number of references to valid blocks. 474system.cpu.dcache.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. 475system.cpu.dcache.occ_blocks::0 511.999417 # Average occupied blocks per context 476system.cpu.dcache.occ_percent::0 0.999999 # Average percentage of cache occupancy 477system.cpu.dcache.ReadReq_hits::0 12057024 # number of ReadReq hits 478system.cpu.dcache.ReadReq_hits::total 12057024 # number of ReadReq hits 479system.cpu.dcache.WriteReq_hits::0 8082938 # number of WriteReq hits 480system.cpu.dcache.WriteReq_hits::total 8082938 # number of WriteReq hits 481system.cpu.dcache.demand_hits::0 20139962 # number of demand (read+write) hits 482system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits 483system.cpu.dcache.demand_hits::total 20139962 # number of demand (read+write) hits 484system.cpu.dcache.overall_hits::0 20139962 # number of overall hits 485system.cpu.dcache.overall_hits::1 0 # number of overall hits 486system.cpu.dcache.overall_hits::total 20139962 # number of overall hits 487system.cpu.dcache.ReadReq_misses::0 1308207 # number of ReadReq misses 488system.cpu.dcache.ReadReq_misses::total 1308207 # number of ReadReq misses 489system.cpu.dcache.WriteReq_misses::0 315850 # number of WriteReq misses 490system.cpu.dcache.WriteReq_misses::total 315850 # number of WriteReq misses 491system.cpu.dcache.demand_misses::0 1624057 # number of demand (read+write) misses 492system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses 493system.cpu.dcache.demand_misses::total 1624057 # number of demand (read+write) misses 494system.cpu.dcache.overall_misses::0 1624057 # number of overall misses 495system.cpu.dcache.overall_misses::1 0 # number of overall misses 496system.cpu.dcache.overall_misses::total 1624057 # number of overall misses 497system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles 498system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles 499system.cpu.dcache.ReadReq_accesses::0 13365231 # number of ReadReq accesses(hits+misses) 500system.cpu.dcache.ReadReq_accesses::total 13365231 # number of ReadReq accesses(hits+misses) 501system.cpu.dcache.WriteReq_accesses::0 8398788 # number of WriteReq accesses(hits+misses) 502system.cpu.dcache.WriteReq_accesses::total 8398788 # number of WriteReq accesses(hits+misses) 503system.cpu.dcache.demand_accesses::0 21764019 # number of demand (read+write) accesses 504system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses 505system.cpu.dcache.demand_accesses::total 21764019 # number of demand (read+write) accesses 506system.cpu.dcache.overall_accesses::0 21764019 # number of overall (read+write) accesses 507system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses 508system.cpu.dcache.overall_accesses::total 21764019 # number of overall (read+write) accesses 509system.cpu.dcache.ReadReq_miss_rate::0 0.097881 # miss rate for ReadReq accesses 510system.cpu.dcache.WriteReq_miss_rate::0 0.037607 # miss rate for WriteReq accesses 511system.cpu.dcache.demand_miss_rate::0 0.074621 # miss rate for demand accesses 512system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses 513system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses 514system.cpu.dcache.overall_miss_rate::0 0.074621 # miss rate for overall accesses 515system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses 516system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses 517system.cpu.dcache.demand_avg_miss_latency::0 0 # average overall miss latency 518system.cpu.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency 519system.cpu.dcache.demand_avg_miss_latency::total no_value # average overall miss latency 520system.cpu.dcache.overall_avg_miss_latency::0 0 # average overall miss latency 521system.cpu.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency 522system.cpu.dcache.overall_avg_miss_latency::total no_value # average overall miss latency 523system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 524system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 525system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 526system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 527system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 528system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 529system.cpu.dcache.fast_writes 0 # number of fast writes performed 530system.cpu.dcache.cache_copies 0 # number of cache copies performed 531system.cpu.dcache.writebacks 1525559 # number of writebacks 532system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 533system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits 534system.cpu.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 535system.cpu.dcache.overall_mshr_misses 0 # number of overall MSHR misses 536system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 537system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 538system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 539system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 540system.cpu.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses 541system.cpu.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses 542system.cpu.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses 543system.cpu.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses 544system.cpu.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses 545system.cpu.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses 546system.cpu.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 547system.cpu.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 548system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 549system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 550system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 551system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 552 553---------- End Simulation Statistics ---------- 554