stats.txt revision 9729:e2fafd224f43
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.615622 # Number of seconds simulated 4sim_ticks 2615622384000 # Number of ticks simulated 5final_tick 2615622384000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 264818 # Simulator instruction rate (inst/s) 8host_op_rate 336993 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 11506330329 # Simulator tick rate (ticks/s) 10host_mem_usage 396436 # Number of bytes of host memory used 11host_seconds 227.32 # Real time elapsed on the host 12sim_insts 60198587 # Number of instructions simulated 13sim_ops 76605405 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.inst 704800 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 9093200 # Number of bytes read from this memory 19system.physmem.bytes_read::total 132481840 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 704800 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 704800 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 3709760 # Number of bytes written to this memory 23system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory 24system.physmem.bytes_written::total 6725832 # Number of bytes written to this memory 25system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.inst 17215 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.data 142115 # Number of read requests responded to by this memory 30system.physmem.num_reads::total 15494761 # Number of read requests responded to by this memory 31system.physmem.num_writes::writebacks 57965 # Number of write requests responded to by this memory 32system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory 33system.physmem.num_writes::total 811983 # Number of write requests responded to by this memory 34system.physmem.bw_read::realview.clcd 46904092 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::cpu.dtb.walker 122 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.itb.walker 49 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.inst 269458 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.data 3476496 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::total 50650216 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu.inst 269458 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 269458 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 1418309 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::cpu.data 1153099 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_write::total 2571408 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_total::writebacks 1418309 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::realview.clcd 46904092 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.dtb.walker 122 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.inst 269458 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.data 4629595 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::total 53221624 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.readReqs 15494761 # Total number of read requests seen 53system.physmem.writeReqs 811983 # Total number of write requests seen 54system.physmem.cpureqs 215166 # Reqs generatd by CPU via cache - shady 55system.physmem.bytesRead 991664704 # Total number of bytes read from memory 56system.physmem.bytesWritten 51966912 # Total number of bytes written to memory 57system.physmem.bytesConsumedRd 132481840 # bytesRead derated as per pkt->getSize() 58system.physmem.bytesConsumedWr 6725832 # bytesWritten derated as per pkt->getSize() 59system.physmem.servicedByWrQ 301 # Number of read reqs serviced by write Q 60system.physmem.neitherReadNorWrite 4516 # Reqs where no action is needed 61system.physmem.perBankRdReqs::0 968108 # Track reads on a per bank basis 62system.physmem.perBankRdReqs::1 967904 # Track reads on a per bank basis 63system.physmem.perBankRdReqs::2 967765 # Track reads on a per bank basis 64system.physmem.perBankRdReqs::3 967946 # Track reads on a per bank basis 65system.physmem.perBankRdReqs::4 974722 # Track reads on a per bank basis 66system.physmem.perBankRdReqs::5 968494 # Track reads on a per bank basis 67system.physmem.perBankRdReqs::6 967971 # Track reads on a per bank basis 68system.physmem.perBankRdReqs::7 967832 # Track reads on a per bank basis 69system.physmem.perBankRdReqs::8 968523 # Track reads on a per bank basis 70system.physmem.perBankRdReqs::9 968301 # Track reads on a per bank basis 71system.physmem.perBankRdReqs::10 967958 # Track reads on a per bank basis 72system.physmem.perBankRdReqs::11 967809 # Track reads on a per bank basis 73system.physmem.perBankRdReqs::12 967930 # Track reads on a per bank basis 74system.physmem.perBankRdReqs::13 967629 # Track reads on a per bank basis 75system.physmem.perBankRdReqs::14 967885 # Track reads on a per bank basis 76system.physmem.perBankRdReqs::15 967683 # Track reads on a per bank basis 77system.physmem.perBankWrReqs::0 49152 # Track writes on a per bank basis 78system.physmem.perBankWrReqs::1 49010 # Track writes on a per bank basis 79system.physmem.perBankWrReqs::2 50853 # Track writes on a per bank basis 80system.physmem.perBankWrReqs::3 50913 # Track writes on a per bank basis 81system.physmem.perBankWrReqs::4 51127 # Track writes on a per bank basis 82system.physmem.perBankWrReqs::5 51430 # Track writes on a per bank basis 83system.physmem.perBankWrReqs::6 51157 # Track writes on a per bank basis 84system.physmem.perBankWrReqs::7 51246 # Track writes on a per bank basis 85system.physmem.perBankWrReqs::8 51368 # Track writes on a per bank basis 86system.physmem.perBankWrReqs::9 51158 # Track writes on a per bank basis 87system.physmem.perBankWrReqs::10 50878 # Track writes on a per bank basis 88system.physmem.perBankWrReqs::11 50797 # Track writes on a per bank basis 89system.physmem.perBankWrReqs::12 50871 # Track writes on a per bank basis 90system.physmem.perBankWrReqs::13 50522 # Track writes on a per bank basis 91system.physmem.perBankWrReqs::14 50825 # Track writes on a per bank basis 92system.physmem.perBankWrReqs::15 50676 # Track writes on a per bank basis 93system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 94system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 95system.physmem.totGap 2615618000000 # Total gap between requests 96system.physmem.readPktSize::0 0 # Categorize read packet sizes 97system.physmem.readPktSize::1 0 # Categorize read packet sizes 98system.physmem.readPktSize::2 6652 # Categorize read packet sizes 99system.physmem.readPktSize::3 15335424 # Categorize read packet sizes 100system.physmem.readPktSize::4 0 # Categorize read packet sizes 101system.physmem.readPktSize::5 0 # Categorize read packet sizes 102system.physmem.readPktSize::6 152685 # Categorize read packet sizes 103system.physmem.writePktSize::0 0 # Categorize write packet sizes 104system.physmem.writePktSize::1 0 # Categorize write packet sizes 105system.physmem.writePktSize::2 754018 # Categorize write packet sizes 106system.physmem.writePktSize::3 0 # Categorize write packet sizes 107system.physmem.writePktSize::4 0 # Categorize write packet sizes 108system.physmem.writePktSize::5 0 # Categorize write packet sizes 109system.physmem.writePktSize::6 57965 # Categorize write packet sizes 110system.physmem.rdQLenPdf::0 1126555 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::1 973164 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::2 1018253 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::3 3775658 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::4 2831038 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::5 2826406 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::6 2774250 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::7 21901 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::8 19136 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::9 31670 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::10 43534 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::11 30921 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::12 5697 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::13 5598 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::14 5455 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::15 5184 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::16 40 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 142system.physmem.wrQLenPdf::0 35284 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::1 35302 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::2 35303 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::3 35304 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::4 35304 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::5 35304 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::6 35304 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::7 35304 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::8 35304 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::9 35304 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::10 35304 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::11 35304 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::12 35304 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::13 35304 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::14 35303 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::15 35303 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::16 35303 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::17 35303 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::18 35303 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::19 35303 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::20 35303 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::21 35303 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::22 35303 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::23 20 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 174system.physmem.bytesPerActivate::samples 38567 # Bytes accessed per row activation 175system.physmem.bytesPerActivate::mean 27059.676926 # Bytes accessed per row activation 176system.physmem.bytesPerActivate::gmean 2495.376643 # Bytes accessed per row activation 177system.physmem.bytesPerActivate::stdev 33105.439598 # Bytes accessed per row activation 178system.physmem.bytesPerActivate::64-127 5489 14.23% 14.23% # Bytes accessed per row activation 179system.physmem.bytesPerActivate::128-191 3331 8.64% 22.87% # Bytes accessed per row activation 180system.physmem.bytesPerActivate::192-255 2176 5.64% 28.51% # Bytes accessed per row activation 181system.physmem.bytesPerActivate::256-319 1697 4.40% 32.91% # Bytes accessed per row activation 182system.physmem.bytesPerActivate::320-383 1162 3.01% 35.92% # Bytes accessed per row activation 183system.physmem.bytesPerActivate::384-447 1046 2.71% 38.64% # Bytes accessed per row activation 184system.physmem.bytesPerActivate::448-511 828 2.15% 40.78% # Bytes accessed per row activation 185system.physmem.bytesPerActivate::512-575 748 1.94% 42.72% # Bytes accessed per row activation 186system.physmem.bytesPerActivate::576-639 582 1.51% 44.23% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::640-703 509 1.32% 45.55% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::704-767 411 1.07% 46.62% # Bytes accessed per row activation 189system.physmem.bytesPerActivate::768-831 479 1.24% 47.86% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::832-895 285 0.74% 48.60% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::896-959 248 0.64% 49.24% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::960-1023 187 0.48% 49.73% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::1024-1087 239 0.62% 50.35% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::1088-1151 141 0.37% 50.71% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::1152-1215 137 0.36% 51.07% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::1216-1279 106 0.27% 51.34% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::1280-1343 105 0.27% 51.61% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::1344-1407 92 0.24% 51.85% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::1408-1471 151 0.39% 52.24% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::1472-1535 970 2.52% 54.76% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1536-1599 203 0.53% 55.29% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1600-1663 135 0.35% 55.64% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::1664-1727 110 0.29% 55.92% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::1728-1791 91 0.24% 56.16% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::1792-1855 77 0.20% 56.36% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::1856-1919 66 0.17% 56.53% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::1920-1983 47 0.12% 56.65% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1984-2047 51 0.13% 56.78% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::2048-2111 64 0.17% 56.95% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::2112-2175 37 0.10% 57.04% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::2176-2239 25 0.06% 57.11% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::2240-2303 18 0.05% 57.16% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::2304-2367 25 0.06% 57.22% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::2368-2431 26 0.07% 57.29% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::2432-2495 13 0.03% 57.32% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::2496-2559 25 0.06% 57.39% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::2560-2623 11 0.03% 57.41% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::2624-2687 14 0.04% 57.45% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::2688-2751 8 0.02% 57.47% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::2752-2815 18 0.05% 57.52% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::2816-2879 9 0.02% 57.54% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::2880-2943 8 0.02% 57.56% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::2944-3007 14 0.04% 57.60% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::3008-3071 7 0.02% 57.62% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::3072-3135 17 0.04% 57.66% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::3136-3199 7 0.02% 57.68% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::3200-3263 8 0.02% 57.70% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::3264-3327 12 0.03% 57.73% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::3328-3391 12 0.03% 57.76% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::3392-3455 3 0.01% 57.77% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::3456-3519 9 0.02% 57.79% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::3520-3583 3 0.01% 57.80% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::3584-3647 6 0.02% 57.82% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::3648-3711 12 0.03% 57.85% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::3712-3775 9 0.02% 57.87% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::3776-3839 7 0.02% 57.89% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::3840-3903 9 0.02% 57.91% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::3904-3967 4 0.01% 57.92% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::3968-4031 6 0.02% 57.94% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::4032-4095 9 0.02% 57.96% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::4096-4159 44 0.11% 58.08% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::4160-4223 3 0.01% 58.08% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::4224-4287 2 0.01% 58.09% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::4288-4351 3 0.01% 58.10% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::4352-4415 5 0.01% 58.11% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::4416-4479 6 0.02% 58.12% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::4480-4543 2 0.01% 58.13% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::4544-4607 5 0.01% 58.14% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::4608-4671 2 0.01% 58.15% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::4672-4735 1 0.00% 58.15% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::4736-4799 1 0.00% 58.15% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::4800-4863 3 0.01% 58.16% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::4864-4927 7 0.02% 58.18% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::4992-5055 6 0.02% 58.19% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::5056-5119 1 0.00% 58.20% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::5120-5183 12 0.03% 58.23% # Bytes accessed per row activation 257system.physmem.bytesPerActivate::5184-5247 1 0.00% 58.23% # Bytes accessed per row activation 258system.physmem.bytesPerActivate::5248-5311 5 0.01% 58.24% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::5312-5375 3 0.01% 58.25% # Bytes accessed per row activation 260system.physmem.bytesPerActivate::5376-5439 5 0.01% 58.26% # Bytes accessed per row activation 261system.physmem.bytesPerActivate::5440-5503 7 0.02% 58.28% # Bytes accessed per row activation 262system.physmem.bytesPerActivate::5504-5567 2 0.01% 58.29% # Bytes accessed per row activation 263system.physmem.bytesPerActivate::5568-5631 2 0.01% 58.29% # Bytes accessed per row activation 264system.physmem.bytesPerActivate::5632-5695 2 0.01% 58.30% # Bytes accessed per row activation 265system.physmem.bytesPerActivate::5696-5759 6 0.02% 58.31% # Bytes accessed per row activation 266system.physmem.bytesPerActivate::5824-5887 3 0.01% 58.32% # Bytes accessed per row activation 267system.physmem.bytesPerActivate::5888-5951 2 0.01% 58.33% # Bytes accessed per row activation 268system.physmem.bytesPerActivate::5952-6015 3 0.01% 58.33% # Bytes accessed per row activation 269system.physmem.bytesPerActivate::6016-6079 2 0.01% 58.34% # Bytes accessed per row activation 270system.physmem.bytesPerActivate::6080-6143 2 0.01% 58.35% # Bytes accessed per row activation 271system.physmem.bytesPerActivate::6144-6207 180 0.47% 58.81% # Bytes accessed per row activation 272system.physmem.bytesPerActivate::6208-6271 1 0.00% 58.81% # Bytes accessed per row activation 273system.physmem.bytesPerActivate::6272-6335 1 0.00% 58.82% # Bytes accessed per row activation 274system.physmem.bytesPerActivate::6336-6399 3 0.01% 58.82% # Bytes accessed per row activation 275system.physmem.bytesPerActivate::6400-6463 5 0.01% 58.84% # Bytes accessed per row activation 276system.physmem.bytesPerActivate::6464-6527 2 0.01% 58.84% # Bytes accessed per row activation 277system.physmem.bytesPerActivate::6528-6591 3 0.01% 58.85% # Bytes accessed per row activation 278system.physmem.bytesPerActivate::6592-6655 1 0.00% 58.85% # Bytes accessed per row activation 279system.physmem.bytesPerActivate::6656-6719 2 0.01% 58.86% # Bytes accessed per row activation 280system.physmem.bytesPerActivate::6720-6783 1 0.00% 58.86% # Bytes accessed per row activation 281system.physmem.bytesPerActivate::6784-6847 15 0.04% 58.90% # Bytes accessed per row activation 282system.physmem.bytesPerActivate::6848-6911 3 0.01% 58.91% # Bytes accessed per row activation 283system.physmem.bytesPerActivate::6912-6975 1 0.00% 58.91% # Bytes accessed per row activation 284system.physmem.bytesPerActivate::6976-7039 2 0.01% 58.92% # Bytes accessed per row activation 285system.physmem.bytesPerActivate::7040-7103 2 0.01% 58.92% # Bytes accessed per row activation 286system.physmem.bytesPerActivate::7168-7231 4 0.01% 58.93% # Bytes accessed per row activation 287system.physmem.bytesPerActivate::7232-7295 3 0.01% 58.94% # Bytes accessed per row activation 288system.physmem.bytesPerActivate::7360-7423 1 0.00% 58.94% # Bytes accessed per row activation 289system.physmem.bytesPerActivate::7424-7487 2 0.01% 58.95% # Bytes accessed per row activation 290system.physmem.bytesPerActivate::7488-7551 3 0.01% 58.95% # Bytes accessed per row activation 291system.physmem.bytesPerActivate::7552-7615 3 0.01% 58.96% # Bytes accessed per row activation 292system.physmem.bytesPerActivate::7616-7679 3 0.01% 58.97% # Bytes accessed per row activation 293system.physmem.bytesPerActivate::7680-7743 11 0.03% 59.00% # Bytes accessed per row activation 294system.physmem.bytesPerActivate::7744-7807 3 0.01% 59.01% # Bytes accessed per row activation 295system.physmem.bytesPerActivate::7808-7871 4 0.01% 59.02% # Bytes accessed per row activation 296system.physmem.bytesPerActivate::7872-7935 4 0.01% 59.03% # Bytes accessed per row activation 297system.physmem.bytesPerActivate::7936-7999 3 0.01% 59.03% # Bytes accessed per row activation 298system.physmem.bytesPerActivate::8000-8063 1 0.00% 59.04% # Bytes accessed per row activation 299system.physmem.bytesPerActivate::8064-8127 6 0.02% 59.05% # Bytes accessed per row activation 300system.physmem.bytesPerActivate::8128-8191 4 0.01% 59.06% # Bytes accessed per row activation 301system.physmem.bytesPerActivate::8192-8255 327 0.85% 59.91% # Bytes accessed per row activation 302system.physmem.bytesPerActivate::8448-8511 5 0.01% 59.92% # Bytes accessed per row activation 303system.physmem.bytesPerActivate::8832-8895 1 0.00% 59.93% # Bytes accessed per row activation 304system.physmem.bytesPerActivate::8960-9023 1 0.00% 59.93% # Bytes accessed per row activation 305system.physmem.bytesPerActivate::9216-9279 3 0.01% 59.94% # Bytes accessed per row activation 306system.physmem.bytesPerActivate::9472-9535 2 0.01% 59.94% # Bytes accessed per row activation 307system.physmem.bytesPerActivate::9728-9791 1 0.00% 59.95% # Bytes accessed per row activation 308system.physmem.bytesPerActivate::10240-10303 18 0.05% 59.99% # Bytes accessed per row activation 309system.physmem.bytesPerActivate::10496-10559 1 0.00% 59.99% # Bytes accessed per row activation 310system.physmem.bytesPerActivate::10752-10815 1 0.00% 60.00% # Bytes accessed per row activation 311system.physmem.bytesPerActivate::11200-11263 1 0.00% 60.00% # Bytes accessed per row activation 312system.physmem.bytesPerActivate::11264-11327 2 0.01% 60.00% # Bytes accessed per row activation 313system.physmem.bytesPerActivate::11520-11583 2 0.01% 60.01% # Bytes accessed per row activation 314system.physmem.bytesPerActivate::11584-11647 1 0.00% 60.01% # Bytes accessed per row activation 315system.physmem.bytesPerActivate::11776-11839 1 0.00% 60.02% # Bytes accessed per row activation 316system.physmem.bytesPerActivate::12032-12095 1 0.00% 60.02% # Bytes accessed per row activation 317system.physmem.bytesPerActivate::12288-12351 3 0.01% 60.03% # Bytes accessed per row activation 318system.physmem.bytesPerActivate::12544-12607 1 0.00% 60.03% # Bytes accessed per row activation 319system.physmem.bytesPerActivate::13056-13119 1 0.00% 60.03% # Bytes accessed per row activation 320system.physmem.bytesPerActivate::13568-13631 1 0.00% 60.03% # Bytes accessed per row activation 321system.physmem.bytesPerActivate::14080-14143 1 0.00% 60.04% # Bytes accessed per row activation 322system.physmem.bytesPerActivate::14336-14399 2 0.01% 60.04% # Bytes accessed per row activation 323system.physmem.bytesPerActivate::14592-14655 2 0.01% 60.05% # Bytes accessed per row activation 324system.physmem.bytesPerActivate::15360-15423 3 0.01% 60.05% # Bytes accessed per row activation 325system.physmem.bytesPerActivate::15680-15743 1 0.00% 60.06% # Bytes accessed per row activation 326system.physmem.bytesPerActivate::15872-15935 1 0.00% 60.06% # Bytes accessed per row activation 327system.physmem.bytesPerActivate::16128-16191 2 0.01% 60.06% # Bytes accessed per row activation 328system.physmem.bytesPerActivate::16384-16447 1 0.00% 60.07% # Bytes accessed per row activation 329system.physmem.bytesPerActivate::17408-17471 2 0.01% 60.07% # Bytes accessed per row activation 330system.physmem.bytesPerActivate::17664-17727 1 0.00% 60.07% # Bytes accessed per row activation 331system.physmem.bytesPerActivate::17920-17983 1 0.00% 60.08% # Bytes accessed per row activation 332system.physmem.bytesPerActivate::18176-18239 1 0.00% 60.08% # Bytes accessed per row activation 333system.physmem.bytesPerActivate::18432-18495 2 0.01% 60.09% # Bytes accessed per row activation 334system.physmem.bytesPerActivate::19008-19071 1 0.00% 60.09% # Bytes accessed per row activation 335system.physmem.bytesPerActivate::19200-19263 1 0.00% 60.09% # Bytes accessed per row activation 336system.physmem.bytesPerActivate::19456-19519 3 0.01% 60.10% # Bytes accessed per row activation 337system.physmem.bytesPerActivate::19712-19775 3 0.01% 60.11% # Bytes accessed per row activation 338system.physmem.bytesPerActivate::19968-20031 1 0.00% 60.11% # Bytes accessed per row activation 339system.physmem.bytesPerActivate::20224-20287 1 0.00% 60.11% # Bytes accessed per row activation 340system.physmem.bytesPerActivate::20480-20543 2 0.01% 60.12% # Bytes accessed per row activation 341system.physmem.bytesPerActivate::20736-20799 1 0.00% 60.12% # Bytes accessed per row activation 342system.physmem.bytesPerActivate::21248-21311 1 0.00% 60.12% # Bytes accessed per row activation 343system.physmem.bytesPerActivate::21504-21567 1 0.00% 60.12% # Bytes accessed per row activation 344system.physmem.bytesPerActivate::21760-21823 2 0.01% 60.13% # Bytes accessed per row activation 345system.physmem.bytesPerActivate::22528-22591 4 0.01% 60.14% # Bytes accessed per row activation 346system.physmem.bytesPerActivate::22784-22847 1 0.00% 60.14% # Bytes accessed per row activation 347system.physmem.bytesPerActivate::23040-23103 3 0.01% 60.15% # Bytes accessed per row activation 348system.physmem.bytesPerActivate::23296-23359 1 0.00% 60.15% # Bytes accessed per row activation 349system.physmem.bytesPerActivate::23552-23615 5 0.01% 60.17% # Bytes accessed per row activation 350system.physmem.bytesPerActivate::23808-23871 1 0.00% 60.17% # Bytes accessed per row activation 351system.physmem.bytesPerActivate::24064-24127 2 0.01% 60.17% # Bytes accessed per row activation 352system.physmem.bytesPerActivate::24576-24639 1 0.00% 60.18% # Bytes accessed per row activation 353system.physmem.bytesPerActivate::24832-24895 1 0.00% 60.18% # Bytes accessed per row activation 354system.physmem.bytesPerActivate::24960-25023 1 0.00% 60.18% # Bytes accessed per row activation 355system.physmem.bytesPerActivate::25600-25663 3 0.01% 60.19% # Bytes accessed per row activation 356system.physmem.bytesPerActivate::25856-25919 2 0.01% 60.19% # Bytes accessed per row activation 357system.physmem.bytesPerActivate::26368-26431 1 0.00% 60.20% # Bytes accessed per row activation 358system.physmem.bytesPerActivate::26624-26687 4 0.01% 60.21% # Bytes accessed per row activation 359system.physmem.bytesPerActivate::26880-26943 1 0.00% 60.21% # Bytes accessed per row activation 360system.physmem.bytesPerActivate::27136-27199 1 0.00% 60.21% # Bytes accessed per row activation 361system.physmem.bytesPerActivate::27904-27967 1 0.00% 60.21% # Bytes accessed per row activation 362system.physmem.bytesPerActivate::28096-28159 1 0.00% 60.22% # Bytes accessed per row activation 363system.physmem.bytesPerActivate::28672-28735 1 0.00% 60.22% # Bytes accessed per row activation 364system.physmem.bytesPerActivate::28928-28991 1 0.00% 60.22% # Bytes accessed per row activation 365system.physmem.bytesPerActivate::29376-29439 1 0.00% 60.23% # Bytes accessed per row activation 366system.physmem.bytesPerActivate::29696-29759 6 0.02% 60.24% # Bytes accessed per row activation 367system.physmem.bytesPerActivate::29952-30015 2 0.01% 60.25% # Bytes accessed per row activation 368system.physmem.bytesPerActivate::30464-30527 3 0.01% 60.25% # Bytes accessed per row activation 369system.physmem.bytesPerActivate::30720-30783 3 0.01% 60.26% # Bytes accessed per row activation 370system.physmem.bytesPerActivate::31168-31231 1 0.00% 60.26% # Bytes accessed per row activation 371system.physmem.bytesPerActivate::31232-31295 2 0.01% 60.27% # Bytes accessed per row activation 372system.physmem.bytesPerActivate::31744-31807 5 0.01% 60.28% # Bytes accessed per row activation 373system.physmem.bytesPerActivate::32000-32063 1 0.00% 60.28% # Bytes accessed per row activation 374system.physmem.bytesPerActivate::32768-32831 2 0.01% 60.29% # Bytes accessed per row activation 375system.physmem.bytesPerActivate::33280-33343 4 0.01% 60.30% # Bytes accessed per row activation 376system.physmem.bytesPerActivate::33536-33599 56 0.15% 60.45% # Bytes accessed per row activation 377system.physmem.bytesPerActivate::33600-33663 1 0.00% 60.45% # Bytes accessed per row activation 378system.physmem.bytesPerActivate::34048-34111 1 0.00% 60.45% # Bytes accessed per row activation 379system.physmem.bytesPerActivate::34816-34879 1 0.00% 60.45% # Bytes accessed per row activation 380system.physmem.bytesPerActivate::35840-35903 1 0.00% 60.46% # Bytes accessed per row activation 381system.physmem.bytesPerActivate::37376-37439 1 0.00% 60.46% # Bytes accessed per row activation 382system.physmem.bytesPerActivate::38912-38975 1 0.00% 60.46% # Bytes accessed per row activation 383system.physmem.bytesPerActivate::39936-39999 2 0.01% 60.47% # Bytes accessed per row activation 384system.physmem.bytesPerActivate::42240-42303 1 0.00% 60.47% # Bytes accessed per row activation 385system.physmem.bytesPerActivate::42496-42559 2 0.01% 60.47% # Bytes accessed per row activation 386system.physmem.bytesPerActivate::43008-43071 1 0.00% 60.48% # Bytes accessed per row activation 387system.physmem.bytesPerActivate::43520-43583 1 0.00% 60.48% # Bytes accessed per row activation 388system.physmem.bytesPerActivate::45056-45119 1 0.00% 60.48% # Bytes accessed per row activation 389system.physmem.bytesPerActivate::45568-45631 1 0.00% 60.48% # Bytes accessed per row activation 390system.physmem.bytesPerActivate::46080-46143 1 0.00% 60.49% # Bytes accessed per row activation 391system.physmem.bytesPerActivate::47360-47423 1 0.00% 60.49% # Bytes accessed per row activation 392system.physmem.bytesPerActivate::48128-48191 1 0.00% 60.49% # Bytes accessed per row activation 393system.physmem.bytesPerActivate::49152-49215 2 0.01% 60.50% # Bytes accessed per row activation 394system.physmem.bytesPerActivate::49664-49727 2 0.01% 60.50% # Bytes accessed per row activation 395system.physmem.bytesPerActivate::50176-50239 1 0.00% 60.51% # Bytes accessed per row activation 396system.physmem.bytesPerActivate::51200-51263 1 0.00% 60.51% # Bytes accessed per row activation 397system.physmem.bytesPerActivate::52480-52543 1 0.00% 60.51% # Bytes accessed per row activation 398system.physmem.bytesPerActivate::52992-53055 1 0.00% 60.51% # Bytes accessed per row activation 399system.physmem.bytesPerActivate::56320-56383 3 0.01% 60.52% # Bytes accessed per row activation 400system.physmem.bytesPerActivate::57088-57151 1 0.00% 60.52% # Bytes accessed per row activation 401system.physmem.bytesPerActivate::59392-59455 1 0.00% 60.53% # Bytes accessed per row activation 402system.physmem.bytesPerActivate::60416-60479 2 0.01% 60.53% # Bytes accessed per row activation 403system.physmem.bytesPerActivate::61440-61503 1 0.00% 60.53% # Bytes accessed per row activation 404system.physmem.bytesPerActivate::63488-63551 2 0.01% 60.54% # Bytes accessed per row activation 405system.physmem.bytesPerActivate::63808-63871 1 0.00% 60.54% # Bytes accessed per row activation 406system.physmem.bytesPerActivate::64512-64575 1 0.00% 60.54% # Bytes accessed per row activation 407system.physmem.bytesPerActivate::65024-65087 19 0.05% 60.59% # Bytes accessed per row activation 408system.physmem.bytesPerActivate::65088-65151 6 0.02% 60.61% # Bytes accessed per row activation 409system.physmem.bytesPerActivate::65152-65215 2 0.01% 60.61% # Bytes accessed per row activation 410system.physmem.bytesPerActivate::65280-65343 6 0.02% 60.63% # Bytes accessed per row activation 411system.physmem.bytesPerActivate::65344-65407 6 0.02% 60.65% # Bytes accessed per row activation 412system.physmem.bytesPerActivate::65408-65471 14 0.04% 60.68% # Bytes accessed per row activation 413system.physmem.bytesPerActivate::65472-65535 6 0.02% 60.70% # Bytes accessed per row activation 414system.physmem.bytesPerActivate::65536-65599 14789 38.35% 99.04% # Bytes accessed per row activation 415system.physmem.bytesPerActivate::71360-71423 1 0.00% 99.05% # Bytes accessed per row activation 416system.physmem.bytesPerActivate::73984-74047 1 0.00% 99.05% # Bytes accessed per row activation 417system.physmem.bytesPerActivate::83008-83071 1 0.00% 99.05% # Bytes accessed per row activation 418system.physmem.bytesPerActivate::85504-85567 1 0.00% 99.05% # Bytes accessed per row activation 419system.physmem.bytesPerActivate::93120-93183 1 0.00% 99.06% # Bytes accessed per row activation 420system.physmem.bytesPerActivate::97152-97215 1 0.00% 99.06% # Bytes accessed per row activation 421system.physmem.bytesPerActivate::97408-97471 1 0.00% 99.06% # Bytes accessed per row activation 422system.physmem.bytesPerActivate::100672-100735 1 0.00% 99.06% # Bytes accessed per row activation 423system.physmem.bytesPerActivate::103680-103743 1 0.00% 99.07% # Bytes accessed per row activation 424system.physmem.bytesPerActivate::104768-104831 1 0.00% 99.07% # Bytes accessed per row activation 425system.physmem.bytesPerActivate::106432-106495 1 0.00% 99.07% # Bytes accessed per row activation 426system.physmem.bytesPerActivate::109760-109823 1 0.00% 99.07% # Bytes accessed per row activation 427system.physmem.bytesPerActivate::110848-110911 1 0.00% 99.08% # Bytes accessed per row activation 428system.physmem.bytesPerActivate::110912-110975 1 0.00% 99.08% # Bytes accessed per row activation 429system.physmem.bytesPerActivate::114240-114303 1 0.00% 99.08% # Bytes accessed per row activation 430system.physmem.bytesPerActivate::115328-115391 1 0.00% 99.08% # Bytes accessed per row activation 431system.physmem.bytesPerActivate::116992-117055 1 0.00% 99.09% # Bytes accessed per row activation 432system.physmem.bytesPerActivate::120320-120383 1 0.00% 99.09% # Bytes accessed per row activation 433system.physmem.bytesPerActivate::121408-121471 1 0.00% 99.09% # Bytes accessed per row activation 434system.physmem.bytesPerActivate::121472-121535 1 0.00% 99.10% # Bytes accessed per row activation 435system.physmem.bytesPerActivate::124416-124479 1 0.00% 99.10% # Bytes accessed per row activation 436system.physmem.bytesPerActivate::127552-127615 1 0.00% 99.10% # Bytes accessed per row activation 437system.physmem.bytesPerActivate::128640-128703 1 0.00% 99.10% # Bytes accessed per row activation 438system.physmem.bytesPerActivate::130176-130239 1 0.00% 99.11% # Bytes accessed per row activation 439system.physmem.bytesPerActivate::130368-130431 1 0.00% 99.11% # Bytes accessed per row activation 440system.physmem.bytesPerActivate::130432-130495 1 0.00% 99.11% # Bytes accessed per row activation 441system.physmem.bytesPerActivate::130496-130559 1 0.00% 99.11% # Bytes accessed per row activation 442system.physmem.bytesPerActivate::130624-130687 1 0.00% 99.12% # Bytes accessed per row activation 443system.physmem.bytesPerActivate::130688-130751 1 0.00% 99.12% # Bytes accessed per row activation 444system.physmem.bytesPerActivate::130880-130943 1 0.00% 99.12% # Bytes accessed per row activation 445system.physmem.bytesPerActivate::131072-131135 328 0.85% 99.97% # Bytes accessed per row activation 446system.physmem.bytesPerActivate::131200-131263 1 0.00% 99.97% # Bytes accessed per row activation 447system.physmem.bytesPerActivate::132096-132159 3 0.01% 99.98% # Bytes accessed per row activation 448system.physmem.bytesPerActivate::136576-136639 1 0.00% 99.98% # Bytes accessed per row activation 449system.physmem.bytesPerActivate::161408-161471 1 0.00% 99.99% # Bytes accessed per row activation 450system.physmem.bytesPerActivate::190336-190399 1 0.00% 99.99% # Bytes accessed per row activation 451system.physmem.bytesPerActivate::196032-196095 1 0.00% 99.99% # Bytes accessed per row activation 452system.physmem.bytesPerActivate::196608-196671 2 0.01% 100.00% # Bytes accessed per row activation 453system.physmem.bytesPerActivate::420352-420415 1 0.00% 100.00% # Bytes accessed per row activation 454system.physmem.bytesPerActivate::total 38567 # Bytes accessed per row activation 455system.physmem.totQLat 306544443250 # Total cycles spent in queuing delays 456system.physmem.totMemAccLat 400266823250 # Sum of mem lat for all requests 457system.physmem.totBusLat 77472300000 # Total cycles spent in databus access 458system.physmem.totBankLat 16250080000 # Total cycles spent in bank access 459system.physmem.avgQLat 19784.13 # Average queueing delay per request 460system.physmem.avgBankLat 1048.77 # Average bank access latency per request 461system.physmem.avgBusLat 5000.00 # Average bus latency per request 462system.physmem.avgMemAccLat 25832.90 # Average memory access latency 463system.physmem.avgRdBW 379.13 # Average achieved read bandwidth in MB/s 464system.physmem.avgWrBW 19.87 # Average achieved write bandwidth in MB/s 465system.physmem.avgConsumedRdBW 50.65 # Average consumed read bandwidth in MB/s 466system.physmem.avgConsumedWrBW 2.57 # Average consumed write bandwidth in MB/s 467system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 468system.physmem.busUtil 3.12 # Data bus utilization in percentage 469system.physmem.avgRdQLen 0.15 # Average read queue length over time 470system.physmem.avgWrQLen 10.80 # Average write queue length over time 471system.physmem.readRowHits 15469403 # Number of row buffer hits during reads 472system.physmem.writeRowHits 798459 # Number of row buffer hits during writes 473system.physmem.readRowHitRate 99.84 # Row buffer hit rate for reads 474system.physmem.writeRowHitRate 98.33 # Row buffer hit rate for writes 475system.physmem.avgGap 160401.00 # Average gap between requests 476system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory 477system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory 478system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory 479system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory 480system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory 481system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory 482system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) 483system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) 484system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) 485system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) 486system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) 487system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) 488system.membus.throughput 54138467 # Throughput (bytes/s) 489system.membus.trans_dist::ReadReq 16546589 # Transaction distribution 490system.membus.trans_dist::ReadResp 16546589 # Transaction distribution 491system.membus.trans_dist::WriteReq 763368 # Transaction distribution 492system.membus.trans_dist::WriteResp 763368 # Transaction distribution 493system.membus.trans_dist::Writeback 57965 # Transaction distribution 494system.membus.trans_dist::UpgradeReq 4516 # Transaction distribution 495system.membus.trans_dist::UpgradeResp 4516 # Transaction distribution 496system.membus.trans_dist::ReadExReq 132246 # Transaction distribution 497system.membus.trans_dist::ReadExResp 132246 # Transaction distribution 498system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382986 # Packet count per connected master and slave (bytes) 499system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) 500system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893707 # Packet count per connected master and slave (bytes) 501system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3850 # Packet count per connected master and slave (bytes) 502system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) 503system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280555 # Packet count per connected master and slave (bytes) 504system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30670848 # Packet count per connected master and slave (bytes) 505system.membus.pkt_count_system.iocache.mem_side::total 30670848 # Packet count per connected master and slave (bytes) 506system.membus.pkt_count::system.bridge.slave 2382986 # Packet count per connected master and slave (bytes) 507system.membus.pkt_count::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) 508system.membus.pkt_count::system.physmem.port 32564555 # Packet count per connected master and slave (bytes) 509system.membus.pkt_count::system.realview.gic.pio 3850 # Packet count per connected master and slave (bytes) 510system.membus.pkt_count::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) 511system.membus.pkt_count::total 34951403 # Packet count per connected master and slave (bytes) 512system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390389 # Cumulative packet size per connected master and slave (bytes) 513system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) 514system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16524280 # Cumulative packet size per connected master and slave (bytes) 515system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7700 # Cumulative packet size per connected master and slave (bytes) 516system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) 517system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18922393 # Cumulative packet size per connected master and slave (bytes) 518system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 122683392 # Cumulative packet size per connected master and slave (bytes) 519system.membus.tot_pkt_size_system.iocache.mem_side::total 122683392 # Cumulative packet size per connected master and slave (bytes) 520system.membus.tot_pkt_size::system.bridge.slave 2390389 # Cumulative packet size per connected master and slave (bytes) 521system.membus.tot_pkt_size::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) 522system.membus.tot_pkt_size::system.physmem.port 139207672 # Cumulative packet size per connected master and slave (bytes) 523system.membus.tot_pkt_size::system.realview.gic.pio 7700 # Cumulative packet size per connected master and slave (bytes) 524system.membus.tot_pkt_size::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) 525system.membus.tot_pkt_size::total 141605785 # Cumulative packet size per connected master and slave (bytes) 526system.membus.data_through_bus 141605785 # Total data (bytes) 527system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 528system.membus.reqLayer0.occupancy 1206150500 # Layer occupancy (ticks) 529system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 530system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) 531system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 532system.membus.reqLayer2.occupancy 17904777500 # Layer occupancy (ticks) 533system.membus.reqLayer2.utilization 0.7 # Layer utilization (%) 534system.membus.reqLayer3.occupancy 3613000 # Layer occupancy (ticks) 535system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) 536system.membus.reqLayer5.occupancy 1000 # Layer occupancy (ticks) 537system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 538system.membus.respLayer1.occupancy 4945376509 # Layer occupancy (ticks) 539system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 540system.membus.respLayer2.occupancy 34635651750 # Layer occupancy (ticks) 541system.membus.respLayer2.utilization 1.3 # Layer utilization (%) 542system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 543system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 544system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 545system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 546system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 547system.cf0.dma_write_txs 0 # Number of DMA write transactions. 548system.iobus.throughput 47817981 # Throughput (bytes/s) 549system.iobus.trans_dist::ReadReq 16518751 # Transaction distribution 550system.iobus.trans_dist::ReadResp 16518751 # Transaction distribution 551system.iobus.trans_dist::WriteReq 8166 # Transaction distribution 552system.iobus.trans_dist::WriteResp 8166 # Transaction distribution 553system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) 554system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7944 # Packet count per connected master and slave (bytes) 555system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 534 # Packet count per connected master and slave (bytes) 556system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes) 557system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) 558system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 559system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) 560system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) 561system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) 562system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 563system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 564system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 565system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) 566system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) 567system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 568system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) 569system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) 570system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) 571system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) 572system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) 573system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 574system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 575system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 576system.iobus.pkt_count_system.bridge.master::total 2382986 # Packet count per connected master and slave (bytes) 577system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes) 578system.iobus.pkt_count_system.realview.clcd.dma::total 30670848 # Packet count per connected master and slave (bytes) 579system.iobus.pkt_count::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) 580system.iobus.pkt_count::system.realview.realview_io.pio 7944 # Packet count per connected master and slave (bytes) 581system.iobus.pkt_count::system.realview.timer0.pio 534 # Packet count per connected master and slave (bytes) 582system.iobus.pkt_count::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes) 583system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) 584system.iobus.pkt_count::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 585system.iobus.pkt_count::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) 586system.iobus.pkt_count::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) 587system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) 588system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 589system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 590system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 591system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) 592system.iobus.pkt_count::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) 593system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 594system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) 595system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) 596system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) 597system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) 598system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) 599system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 600system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 601system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 602system.iobus.pkt_count::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes) 603system.iobus.pkt_count::total 33053834 # Packet count per connected master and slave (bytes) 604system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) 605system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15888 # Cumulative packet size per connected master and slave (bytes) 606system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1068 # Cumulative packet size per connected master and slave (bytes) 607system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes) 608system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) 609system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 610system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) 611system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) 612system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 613system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 614system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 615system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 616system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 617system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) 618system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 619system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 620system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 621system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 622system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 623system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 624system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 625system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 626system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 627system.iobus.tot_pkt_size_system.bridge.master::total 2390389 # Cumulative packet size per connected master and slave (bytes) 628system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes) 629system.iobus.tot_pkt_size_system.realview.clcd.dma::total 122683392 # Cumulative packet size per connected master and slave (bytes) 630system.iobus.tot_pkt_size::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) 631system.iobus.tot_pkt_size::system.realview.realview_io.pio 15888 # Cumulative packet size per connected master and slave (bytes) 632system.iobus.tot_pkt_size::system.realview.timer0.pio 1068 # Cumulative packet size per connected master and slave (bytes) 633system.iobus.tot_pkt_size::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes) 634system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) 635system.iobus.tot_pkt_size::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 636system.iobus.tot_pkt_size::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) 637system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) 638system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 639system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 640system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 641system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 642system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 643system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) 644system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 645system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 646system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 647system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 648system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 649system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 650system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 651system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 652system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 653system.iobus.tot_pkt_size::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes) 654system.iobus.tot_pkt_size::total 125073781 # Cumulative packet size per connected master and slave (bytes) 655system.iobus.data_through_bus 125073781 # Total data (bytes) 656system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) 657system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 658system.iobus.reqLayer1.occupancy 3977000 # Layer occupancy (ticks) 659system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 660system.iobus.reqLayer2.occupancy 534000 # Layer occupancy (ticks) 661system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 662system.iobus.reqLayer3.occupancy 527000 # Layer occupancy (ticks) 663system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 664system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) 665system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 666system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) 667system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) 668system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks) 669system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 670system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) 671system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 672system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) 673system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) 674system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 675system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 676system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) 677system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) 678system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) 679system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) 680system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 681system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 682system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) 683system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 684system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 685system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 686system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) 687system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 688system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 689system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 690system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) 691system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 692system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) 693system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 694system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) 695system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 696system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 697system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 698system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) 699system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 700system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) 701system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 702system.iobus.reqLayer25.occupancy 15335424000 # Layer occupancy (ticks) 703system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) 704system.iobus.respLayer0.occupancy 2374820000 # Layer occupancy (ticks) 705system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) 706system.iobus.respLayer1.occupancy 30670848000 # Layer occupancy (ticks) 707system.iobus.respLayer1.utilization 1.2 # Layer utilization (%) 708system.cpu.dtb.inst_hits 0 # ITB inst hits 709system.cpu.dtb.inst_misses 0 # ITB inst misses 710system.cpu.dtb.read_hits 14996055 # DTB read hits 711system.cpu.dtb.read_misses 7342 # DTB read misses 712system.cpu.dtb.write_hits 11230429 # DTB write hits 713system.cpu.dtb.write_misses 2216 # DTB write misses 714system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed 715system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 716system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 717system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 718system.cpu.dtb.flush_entries 3506 # Number of entries that have been flushed from TLB 719system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 720system.cpu.dtb.prefetch_faults 192 # Number of TLB faults due to prefetch 721system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 722system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions 723system.cpu.dtb.read_accesses 15003397 # DTB read accesses 724system.cpu.dtb.write_accesses 11232645 # DTB write accesses 725system.cpu.dtb.inst_accesses 0 # ITB inst accesses 726system.cpu.dtb.hits 26226484 # DTB hits 727system.cpu.dtb.misses 9558 # DTB misses 728system.cpu.dtb.accesses 26236042 # DTB accesses 729system.cpu.itb.inst_hits 61492425 # ITB inst hits 730system.cpu.itb.inst_misses 4471 # ITB inst misses 731system.cpu.itb.read_hits 0 # DTB read hits 732system.cpu.itb.read_misses 0 # DTB read misses 733system.cpu.itb.write_hits 0 # DTB write hits 734system.cpu.itb.write_misses 0 # DTB write misses 735system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed 736system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 737system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 738system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 739system.cpu.itb.flush_entries 2343 # Number of entries that have been flushed from TLB 740system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 741system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 742system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 743system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 744system.cpu.itb.read_accesses 0 # DTB read accesses 745system.cpu.itb.write_accesses 0 # DTB write accesses 746system.cpu.itb.inst_accesses 61496896 # ITB inst accesses 747system.cpu.itb.hits 61492425 # DTB hits 748system.cpu.itb.misses 4471 # DTB misses 749system.cpu.itb.accesses 61496896 # DTB accesses 750system.cpu.numCycles 5231244768 # number of cpu cycles simulated 751system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 752system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 753system.cpu.committedInsts 60198587 # Number of instructions committed 754system.cpu.committedOps 76605405 # Number of ops (including micro ops) committed 755system.cpu.num_int_alu_accesses 68872209 # Number of integer alu accesses 756system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses 757system.cpu.num_func_calls 2140451 # number of times a function call or return occured 758system.cpu.num_conditional_control_insts 7948368 # number of instructions that are conditional controls 759system.cpu.num_int_insts 68872209 # number of integer instructions 760system.cpu.num_fp_insts 10269 # number of float instructions 761system.cpu.num_int_register_reads 394776354 # number of times the integer registers were read 762system.cpu.num_int_register_writes 74181797 # number of times the integer registers were written 763system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read 764system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written 765system.cpu.num_mem_refs 27393915 # number of memory refs 766system.cpu.num_load_insts 15660071 # Number of load instructions 767system.cpu.num_store_insts 11733844 # Number of store instructions 768system.cpu.num_idle_cycles 4582065338.612248 # Number of idle cycles 769system.cpu.num_busy_cycles 649179429.387752 # Number of busy cycles 770system.cpu.not_idle_fraction 0.124097 # Percentage of non-idle cycles 771system.cpu.idle_fraction 0.875903 # Percentage of idle cycles 772system.cpu.kern.inst.arm 0 # number of arm instructions executed 773system.cpu.kern.inst.quiesce 83018 # number of quiesce instructions executed 774system.cpu.icache.replacements 856250 # number of replacements 775system.cpu.icache.tagsinuse 510.885364 # Cycle average of tags in use 776system.cpu.icache.total_refs 60635663 # Total number of references to valid blocks. 777system.cpu.icache.sampled_refs 856762 # Sample count of references to valid blocks. 778system.cpu.icache.avg_refs 70.773054 # Average number of references to valid blocks. 779system.cpu.icache.warmup_cycle 19768699000 # Cycle when the warmup percentage was hit. 780system.cpu.icache.occ_blocks::cpu.inst 510.885364 # Average occupied blocks per requestor 781system.cpu.icache.occ_percent::cpu.inst 0.997823 # Average percentage of cache occupancy 782system.cpu.icache.occ_percent::total 0.997823 # Average percentage of cache occupancy 783system.cpu.icache.ReadReq_hits::cpu.inst 60635663 # number of ReadReq hits 784system.cpu.icache.ReadReq_hits::total 60635663 # number of ReadReq hits 785system.cpu.icache.demand_hits::cpu.inst 60635663 # number of demand (read+write) hits 786system.cpu.icache.demand_hits::total 60635663 # number of demand (read+write) hits 787system.cpu.icache.overall_hits::cpu.inst 60635663 # number of overall hits 788system.cpu.icache.overall_hits::total 60635663 # number of overall hits 789system.cpu.icache.ReadReq_misses::cpu.inst 856762 # number of ReadReq misses 790system.cpu.icache.ReadReq_misses::total 856762 # number of ReadReq misses 791system.cpu.icache.demand_misses::cpu.inst 856762 # number of demand (read+write) misses 792system.cpu.icache.demand_misses::total 856762 # number of demand (read+write) misses 793system.cpu.icache.overall_misses::cpu.inst 856762 # number of overall misses 794system.cpu.icache.overall_misses::total 856762 # number of overall misses 795system.cpu.icache.ReadReq_miss_latency::cpu.inst 11759087500 # number of ReadReq miss cycles 796system.cpu.icache.ReadReq_miss_latency::total 11759087500 # number of ReadReq miss cycles 797system.cpu.icache.demand_miss_latency::cpu.inst 11759087500 # number of demand (read+write) miss cycles 798system.cpu.icache.demand_miss_latency::total 11759087500 # number of demand (read+write) miss cycles 799system.cpu.icache.overall_miss_latency::cpu.inst 11759087500 # number of overall miss cycles 800system.cpu.icache.overall_miss_latency::total 11759087500 # number of overall miss cycles 801system.cpu.icache.ReadReq_accesses::cpu.inst 61492425 # number of ReadReq accesses(hits+misses) 802system.cpu.icache.ReadReq_accesses::total 61492425 # number of ReadReq accesses(hits+misses) 803system.cpu.icache.demand_accesses::cpu.inst 61492425 # number of demand (read+write) accesses 804system.cpu.icache.demand_accesses::total 61492425 # number of demand (read+write) accesses 805system.cpu.icache.overall_accesses::cpu.inst 61492425 # number of overall (read+write) accesses 806system.cpu.icache.overall_accesses::total 61492425 # number of overall (read+write) accesses 807system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013933 # miss rate for ReadReq accesses 808system.cpu.icache.ReadReq_miss_rate::total 0.013933 # miss rate for ReadReq accesses 809system.cpu.icache.demand_miss_rate::cpu.inst 0.013933 # miss rate for demand accesses 810system.cpu.icache.demand_miss_rate::total 0.013933 # miss rate for demand accesses 811system.cpu.icache.overall_miss_rate::cpu.inst 0.013933 # miss rate for overall accesses 812system.cpu.icache.overall_miss_rate::total 0.013933 # miss rate for overall accesses 813system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13725.033907 # average ReadReq miss latency 814system.cpu.icache.ReadReq_avg_miss_latency::total 13725.033907 # average ReadReq miss latency 815system.cpu.icache.demand_avg_miss_latency::cpu.inst 13725.033907 # average overall miss latency 816system.cpu.icache.demand_avg_miss_latency::total 13725.033907 # average overall miss latency 817system.cpu.icache.overall_avg_miss_latency::cpu.inst 13725.033907 # average overall miss latency 818system.cpu.icache.overall_avg_miss_latency::total 13725.033907 # average overall miss latency 819system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 820system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 821system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 822system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 823system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 824system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 825system.cpu.icache.fast_writes 0 # number of fast writes performed 826system.cpu.icache.cache_copies 0 # number of cache copies performed 827system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856762 # number of ReadReq MSHR misses 828system.cpu.icache.ReadReq_mshr_misses::total 856762 # number of ReadReq MSHR misses 829system.cpu.icache.demand_mshr_misses::cpu.inst 856762 # number of demand (read+write) MSHR misses 830system.cpu.icache.demand_mshr_misses::total 856762 # number of demand (read+write) MSHR misses 831system.cpu.icache.overall_mshr_misses::cpu.inst 856762 # number of overall MSHR misses 832system.cpu.icache.overall_mshr_misses::total 856762 # number of overall MSHR misses 833system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10045563500 # number of ReadReq MSHR miss cycles 834system.cpu.icache.ReadReq_mshr_miss_latency::total 10045563500 # number of ReadReq MSHR miss cycles 835system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10045563500 # number of demand (read+write) MSHR miss cycles 836system.cpu.icache.demand_mshr_miss_latency::total 10045563500 # number of demand (read+write) MSHR miss cycles 837system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10045563500 # number of overall MSHR miss cycles 838system.cpu.icache.overall_mshr_miss_latency::total 10045563500 # number of overall MSHR miss cycles 839system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 429084500 # number of ReadReq MSHR uncacheable cycles 840system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 429084500 # number of ReadReq MSHR uncacheable cycles 841system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 429084500 # number of overall MSHR uncacheable cycles 842system.cpu.icache.overall_mshr_uncacheable_latency::total 429084500 # number of overall MSHR uncacheable cycles 843system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for ReadReq accesses 844system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013933 # mshr miss rate for ReadReq accesses 845system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for demand accesses 846system.cpu.icache.demand_mshr_miss_rate::total 0.013933 # mshr miss rate for demand accesses 847system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for overall accesses 848system.cpu.icache.overall_mshr_miss_rate::total 0.013933 # mshr miss rate for overall accesses 849system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11725.033907 # average ReadReq mshr miss latency 850system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11725.033907 # average ReadReq mshr miss latency 851system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11725.033907 # average overall mshr miss latency 852system.cpu.icache.demand_avg_mshr_miss_latency::total 11725.033907 # average overall mshr miss latency 853system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11725.033907 # average overall mshr miss latency 854system.cpu.icache.overall_avg_mshr_miss_latency::total 11725.033907 # average overall mshr miss latency 855system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 856system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 857system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 858system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 859system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 860system.cpu.l2cache.replacements 62577 # number of replacements 861system.cpu.l2cache.tagsinuse 50733.086800 # Cycle average of tags in use 862system.cpu.l2cache.total_refs 1684914 # Total number of references to valid blocks. 863system.cpu.l2cache.sampled_refs 128011 # Sample count of references to valid blocks. 864system.cpu.l2cache.avg_refs 13.162259 # Average number of references to valid blocks. 865system.cpu.l2cache.warmup_cycle 2564823166000 # Cycle when the warmup percentage was hit. 866system.cpu.l2cache.occ_blocks::writebacks 37695.331461 # Average occupied blocks per requestor 867system.cpu.l2cache.occ_blocks::cpu.dtb.walker 3.884612 # Average occupied blocks per requestor 868system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000689 # Average occupied blocks per requestor 869system.cpu.l2cache.occ_blocks::cpu.inst 6997.589035 # Average occupied blocks per requestor 870system.cpu.l2cache.occ_blocks::cpu.data 6036.281004 # Average occupied blocks per requestor 871system.cpu.l2cache.occ_percent::writebacks 0.575185 # Average percentage of cache occupancy 872system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy 873system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy 874system.cpu.l2cache.occ_percent::cpu.inst 0.106775 # Average percentage of cache occupancy 875system.cpu.l2cache.occ_percent::cpu.data 0.092106 # Average percentage of cache occupancy 876system.cpu.l2cache.occ_percent::total 0.774125 # Average percentage of cache occupancy 877system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8724 # number of ReadReq hits 878system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3533 # number of ReadReq hits 879system.cpu.l2cache.ReadReq_hits::cpu.inst 844523 # number of ReadReq hits 880system.cpu.l2cache.ReadReq_hits::cpu.data 369967 # number of ReadReq hits 881system.cpu.l2cache.ReadReq_hits::total 1226747 # number of ReadReq hits 882system.cpu.l2cache.Writeback_hits::writebacks 595512 # number of Writeback hits 883system.cpu.l2cache.Writeback_hits::total 595512 # number of Writeback hits 884system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits 885system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits 886system.cpu.l2cache.ReadExReq_hits::cpu.data 113491 # number of ReadExReq hits 887system.cpu.l2cache.ReadExReq_hits::total 113491 # number of ReadExReq hits 888system.cpu.l2cache.demand_hits::cpu.dtb.walker 8724 # number of demand (read+write) hits 889system.cpu.l2cache.demand_hits::cpu.itb.walker 3533 # number of demand (read+write) hits 890system.cpu.l2cache.demand_hits::cpu.inst 844523 # number of demand (read+write) hits 891system.cpu.l2cache.demand_hits::cpu.data 483458 # number of demand (read+write) hits 892system.cpu.l2cache.demand_hits::total 1340238 # number of demand (read+write) hits 893system.cpu.l2cache.overall_hits::cpu.dtb.walker 8724 # number of overall hits 894system.cpu.l2cache.overall_hits::cpu.itb.walker 3533 # number of overall hits 895system.cpu.l2cache.overall_hits::cpu.inst 844523 # number of overall hits 896system.cpu.l2cache.overall_hits::cpu.data 483458 # number of overall hits 897system.cpu.l2cache.overall_hits::total 1340238 # number of overall hits 898system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses 899system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses 900system.cpu.l2cache.ReadReq_misses::cpu.inst 10599 # number of ReadReq misses 901system.cpu.l2cache.ReadReq_misses::cpu.data 9833 # number of ReadReq misses 902system.cpu.l2cache.ReadReq_misses::total 20439 # number of ReadReq misses 903system.cpu.l2cache.UpgradeReq_misses::cpu.data 2885 # number of UpgradeReq misses 904system.cpu.l2cache.UpgradeReq_misses::total 2885 # number of UpgradeReq misses 905system.cpu.l2cache.ReadExReq_misses::cpu.data 133877 # number of ReadExReq misses 906system.cpu.l2cache.ReadExReq_misses::total 133877 # number of ReadExReq misses 907system.cpu.l2cache.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses 908system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses 909system.cpu.l2cache.demand_misses::cpu.inst 10599 # number of demand (read+write) misses 910system.cpu.l2cache.demand_misses::cpu.data 143710 # number of demand (read+write) misses 911system.cpu.l2cache.demand_misses::total 154316 # number of demand (read+write) misses 912system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses 913system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses 914system.cpu.l2cache.overall_misses::cpu.inst 10599 # number of overall misses 915system.cpu.l2cache.overall_misses::cpu.data 143710 # number of overall misses 916system.cpu.l2cache.overall_misses::total 154316 # number of overall misses 917system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 468000 # number of ReadReq miss cycles 918system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 122000 # number of ReadReq miss cycles 919system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 741931500 # number of ReadReq miss cycles 920system.cpu.l2cache.ReadReq_miss_latency::cpu.data 698335500 # number of ReadReq miss cycles 921system.cpu.l2cache.ReadReq_miss_latency::total 1440857000 # number of ReadReq miss cycles 922system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 460000 # number of UpgradeReq miss cycles 923system.cpu.l2cache.UpgradeReq_miss_latency::total 460000 # number of UpgradeReq miss cycles 924system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8582435500 # number of ReadExReq miss cycles 925system.cpu.l2cache.ReadExReq_miss_latency::total 8582435500 # number of ReadExReq miss cycles 926system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 468000 # number of demand (read+write) miss cycles 927system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 122000 # number of demand (read+write) miss cycles 928system.cpu.l2cache.demand_miss_latency::cpu.inst 741931500 # number of demand (read+write) miss cycles 929system.cpu.l2cache.demand_miss_latency::cpu.data 9280771000 # number of demand (read+write) miss cycles 930system.cpu.l2cache.demand_miss_latency::total 10023292500 # number of demand (read+write) miss cycles 931system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 468000 # number of overall miss cycles 932system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 122000 # number of overall miss cycles 933system.cpu.l2cache.overall_miss_latency::cpu.inst 741931500 # number of overall miss cycles 934system.cpu.l2cache.overall_miss_latency::cpu.data 9280771000 # number of overall miss cycles 935system.cpu.l2cache.overall_miss_latency::total 10023292500 # number of overall miss cycles 936system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8729 # number of ReadReq accesses(hits+misses) 937system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3535 # number of ReadReq accesses(hits+misses) 938system.cpu.l2cache.ReadReq_accesses::cpu.inst 855122 # number of ReadReq accesses(hits+misses) 939system.cpu.l2cache.ReadReq_accesses::cpu.data 379800 # number of ReadReq accesses(hits+misses) 940system.cpu.l2cache.ReadReq_accesses::total 1247186 # number of ReadReq accesses(hits+misses) 941system.cpu.l2cache.Writeback_accesses::writebacks 595512 # number of Writeback accesses(hits+misses) 942system.cpu.l2cache.Writeback_accesses::total 595512 # number of Writeback accesses(hits+misses) 943system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2911 # number of UpgradeReq accesses(hits+misses) 944system.cpu.l2cache.UpgradeReq_accesses::total 2911 # number of UpgradeReq accesses(hits+misses) 945system.cpu.l2cache.ReadExReq_accesses::cpu.data 247368 # number of ReadExReq accesses(hits+misses) 946system.cpu.l2cache.ReadExReq_accesses::total 247368 # number of ReadExReq accesses(hits+misses) 947system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8729 # number of demand (read+write) accesses 948system.cpu.l2cache.demand_accesses::cpu.itb.walker 3535 # number of demand (read+write) accesses 949system.cpu.l2cache.demand_accesses::cpu.inst 855122 # number of demand (read+write) accesses 950system.cpu.l2cache.demand_accesses::cpu.data 627168 # number of demand (read+write) accesses 951system.cpu.l2cache.demand_accesses::total 1494554 # number of demand (read+write) accesses 952system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8729 # number of overall (read+write) accesses 953system.cpu.l2cache.overall_accesses::cpu.itb.walker 3535 # number of overall (read+write) accesses 954system.cpu.l2cache.overall_accesses::cpu.inst 855122 # number of overall (read+write) accesses 955system.cpu.l2cache.overall_accesses::cpu.data 627168 # number of overall (read+write) accesses 956system.cpu.l2cache.overall_accesses::total 1494554 # number of overall (read+write) accesses 957system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000573 # miss rate for ReadReq accesses 958system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000566 # miss rate for ReadReq accesses 959system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012395 # miss rate for ReadReq accesses 960system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025890 # miss rate for ReadReq accesses 961system.cpu.l2cache.ReadReq_miss_rate::total 0.016388 # miss rate for ReadReq accesses 962system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991068 # miss rate for UpgradeReq accesses 963system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991068 # miss rate for UpgradeReq accesses 964system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541206 # miss rate for ReadExReq accesses 965system.cpu.l2cache.ReadExReq_miss_rate::total 0.541206 # miss rate for ReadExReq accesses 966system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000573 # miss rate for demand accesses 967system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000566 # miss rate for demand accesses 968system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012395 # miss rate for demand accesses 969system.cpu.l2cache.demand_miss_rate::cpu.data 0.229141 # miss rate for demand accesses 970system.cpu.l2cache.demand_miss_rate::total 0.103252 # miss rate for demand accesses 971system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000573 # miss rate for overall accesses 972system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000566 # miss rate for overall accesses 973system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012395 # miss rate for overall accesses 974system.cpu.l2cache.overall_miss_rate::cpu.data 0.229141 # miss rate for overall accesses 975system.cpu.l2cache.overall_miss_rate::total 0.103252 # miss rate for overall accesses 976system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 93600 # average ReadReq miss latency 977system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 61000 # average ReadReq miss latency 978system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70000.141523 # average ReadReq miss latency 979system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71019.576935 # average ReadReq miss latency 980system.cpu.l2cache.ReadReq_avg_miss_latency::total 70495.474338 # average ReadReq miss latency 981system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 159.445407 # average UpgradeReq miss latency 982system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 159.445407 # average UpgradeReq miss latency 983system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 64106.870486 # average ReadExReq miss latency 984system.cpu.l2cache.ReadExReq_avg_miss_latency::total 64106.870486 # average ReadExReq miss latency 985system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 93600 # average overall miss latency 986system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 61000 # average overall miss latency 987system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70000.141523 # average overall miss latency 988system.cpu.l2cache.demand_avg_miss_latency::cpu.data 64579.855264 # average overall miss latency 989system.cpu.l2cache.demand_avg_miss_latency::total 64953.034682 # average overall miss latency 990system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 93600 # average overall miss latency 991system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 61000 # average overall miss latency 992system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70000.141523 # average overall miss latency 993system.cpu.l2cache.overall_avg_miss_latency::cpu.data 64579.855264 # average overall miss latency 994system.cpu.l2cache.overall_avg_miss_latency::total 64953.034682 # average overall miss latency 995system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 996system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 997system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 998system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 999system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1000system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1001system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1002system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1003system.cpu.l2cache.writebacks::writebacks 57965 # number of writebacks 1004system.cpu.l2cache.writebacks::total 57965 # number of writebacks 1005system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 5 # number of ReadReq MSHR misses 1006system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses 1007system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10599 # number of ReadReq MSHR misses 1008system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 9833 # number of ReadReq MSHR misses 1009system.cpu.l2cache.ReadReq_mshr_misses::total 20439 # number of ReadReq MSHR misses 1010system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2885 # number of UpgradeReq MSHR misses 1011system.cpu.l2cache.UpgradeReq_mshr_misses::total 2885 # number of UpgradeReq MSHR misses 1012system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133877 # number of ReadExReq MSHR misses 1013system.cpu.l2cache.ReadExReq_mshr_misses::total 133877 # number of ReadExReq MSHR misses 1014system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 5 # number of demand (read+write) MSHR misses 1015system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses 1016system.cpu.l2cache.demand_mshr_misses::cpu.inst 10599 # number of demand (read+write) MSHR misses 1017system.cpu.l2cache.demand_mshr_misses::cpu.data 143710 # number of demand (read+write) MSHR misses 1018system.cpu.l2cache.demand_mshr_misses::total 154316 # number of demand (read+write) MSHR misses 1019system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 5 # number of overall MSHR misses 1020system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses 1021system.cpu.l2cache.overall_mshr_misses::cpu.inst 10599 # number of overall MSHR misses 1022system.cpu.l2cache.overall_mshr_misses::cpu.data 143710 # number of overall MSHR misses 1023system.cpu.l2cache.overall_mshr_misses::total 154316 # number of overall MSHR misses 1024system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 404750 # number of ReadReq MSHR miss cycles 1025system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 97500 # number of ReadReq MSHR miss cycles 1026system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 611089500 # number of ReadReq MSHR miss cycles 1027system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 576558000 # number of ReadReq MSHR miss cycles 1028system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1188149750 # number of ReadReq MSHR miss cycles 1029system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 28854885 # number of UpgradeReq MSHR miss cycles 1030system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 28854885 # number of UpgradeReq MSHR miss cycles 1031system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6940085381 # number of ReadExReq MSHR miss cycles 1032system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6940085381 # number of ReadExReq MSHR miss cycles 1033system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 404750 # number of demand (read+write) MSHR miss cycles 1034system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 97500 # number of demand (read+write) MSHR miss cycles 1035system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 611089500 # number of demand (read+write) MSHR miss cycles 1036system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7516643381 # number of demand (read+write) MSHR miss cycles 1037system.cpu.l2cache.demand_mshr_miss_latency::total 8128235131 # number of demand (read+write) MSHR miss cycles 1038system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 404750 # number of overall MSHR miss cycles 1039system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 97500 # number of overall MSHR miss cycles 1040system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 611089500 # number of overall MSHR miss cycles 1041system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7516643381 # number of overall MSHR miss cycles 1042system.cpu.l2cache.overall_mshr_miss_latency::total 8128235131 # number of overall MSHR miss cycles 1043system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 339371500 # number of ReadReq MSHR uncacheable cycles 1044system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166657063250 # number of ReadReq MSHR uncacheable cycles 1045system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166996434750 # number of ReadReq MSHR uncacheable cycles 1046system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 16701843725 # number of WriteReq MSHR uncacheable cycles 1047system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 16701843725 # number of WriteReq MSHR uncacheable cycles 1048system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 339371500 # number of overall MSHR uncacheable cycles 1049system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 183358906975 # number of overall MSHR uncacheable cycles 1050system.cpu.l2cache.overall_mshr_uncacheable_latency::total 183698278475 # number of overall MSHR uncacheable cycles 1051system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000573 # mshr miss rate for ReadReq accesses 1052system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000566 # mshr miss rate for ReadReq accesses 1053system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012395 # mshr miss rate for ReadReq accesses 1054system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025890 # mshr miss rate for ReadReq accesses 1055system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016388 # mshr miss rate for ReadReq accesses 1056system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991068 # mshr miss rate for UpgradeReq accesses 1057system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991068 # mshr miss rate for UpgradeReq accesses 1058system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541206 # mshr miss rate for ReadExReq accesses 1059system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541206 # mshr miss rate for ReadExReq accesses 1060system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000573 # mshr miss rate for demand accesses 1061system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000566 # mshr miss rate for demand accesses 1062system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012395 # mshr miss rate for demand accesses 1063system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229141 # mshr miss rate for demand accesses 1064system.cpu.l2cache.demand_mshr_miss_rate::total 0.103252 # mshr miss rate for demand accesses 1065system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000573 # mshr miss rate for overall accesses 1066system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000566 # mshr miss rate for overall accesses 1067system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012395 # mshr miss rate for overall accesses 1068system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229141 # mshr miss rate for overall accesses 1069system.cpu.l2cache.overall_mshr_miss_rate::total 0.103252 # mshr miss rate for overall accesses 1070system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 80950 # average ReadReq mshr miss latency 1071system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 48750 # average ReadReq mshr miss latency 1072system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57655.392018 # average ReadReq mshr miss latency 1073system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58635.004576 # average ReadReq mshr miss latency 1074system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58131.501052 # average ReadReq mshr miss latency 1075system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001.693241 # average UpgradeReq mshr miss latency 1076system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.693241 # average UpgradeReq mshr miss latency 1077system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 51839.265751 # average ReadExReq mshr miss latency 1078system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 51839.265751 # average ReadExReq mshr miss latency 1079system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 80950 # average overall mshr miss latency 1080system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 48750 # average overall mshr miss latency 1081system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57655.392018 # average overall mshr miss latency 1082system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52304.247311 # average overall mshr miss latency 1083system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52672.666029 # average overall mshr miss latency 1084system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 80950 # average overall mshr miss latency 1085system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 48750 # average overall mshr miss latency 1086system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57655.392018 # average overall mshr miss latency 1087system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52304.247311 # average overall mshr miss latency 1088system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52672.666029 # average overall mshr miss latency 1089system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1090system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1091system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1092system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1093system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1094system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1095system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1096system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1097system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1098system.cpu.dcache.replacements 626656 # number of replacements 1099system.cpu.dcache.tagsinuse 511.879114 # Cycle average of tags in use 1100system.cpu.dcache.total_refs 23655617 # Total number of references to valid blocks. 1101system.cpu.dcache.sampled_refs 627168 # Sample count of references to valid blocks. 1102system.cpu.dcache.avg_refs 37.718150 # Average number of references to valid blocks. 1103system.cpu.dcache.warmup_cycle 650249000 # Cycle when the warmup percentage was hit. 1104system.cpu.dcache.occ_blocks::cpu.data 511.879114 # Average occupied blocks per requestor 1105system.cpu.dcache.occ_percent::cpu.data 0.999764 # Average percentage of cache occupancy 1106system.cpu.dcache.occ_percent::total 0.999764 # Average percentage of cache occupancy 1107system.cpu.dcache.ReadReq_hits::cpu.data 13195840 # number of ReadReq hits 1108system.cpu.dcache.ReadReq_hits::total 13195840 # number of ReadReq hits 1109system.cpu.dcache.WriteReq_hits::cpu.data 9972724 # number of WriteReq hits 1110system.cpu.dcache.WriteReq_hits::total 9972724 # number of WriteReq hits 1111system.cpu.dcache.LoadLockedReq_hits::cpu.data 236345 # number of LoadLockedReq hits 1112system.cpu.dcache.LoadLockedReq_hits::total 236345 # number of LoadLockedReq hits 1113system.cpu.dcache.StoreCondReq_hits::cpu.data 247797 # number of StoreCondReq hits 1114system.cpu.dcache.StoreCondReq_hits::total 247797 # number of StoreCondReq hits 1115system.cpu.dcache.demand_hits::cpu.data 23168564 # number of demand (read+write) hits 1116system.cpu.dcache.demand_hits::total 23168564 # number of demand (read+write) hits 1117system.cpu.dcache.overall_hits::cpu.data 23168564 # number of overall hits 1118system.cpu.dcache.overall_hits::total 23168564 # number of overall hits 1119system.cpu.dcache.ReadReq_misses::cpu.data 368347 # number of ReadReq misses 1120system.cpu.dcache.ReadReq_misses::total 368347 # number of ReadReq misses 1121system.cpu.dcache.WriteReq_misses::cpu.data 250279 # number of WriteReq misses 1122system.cpu.dcache.WriteReq_misses::total 250279 # number of WriteReq misses 1123system.cpu.dcache.LoadLockedReq_misses::cpu.data 11453 # number of LoadLockedReq misses 1124system.cpu.dcache.LoadLockedReq_misses::total 11453 # number of LoadLockedReq misses 1125system.cpu.dcache.demand_misses::cpu.data 618626 # number of demand (read+write) misses 1126system.cpu.dcache.demand_misses::total 618626 # number of demand (read+write) misses 1127system.cpu.dcache.overall_misses::cpu.data 618626 # number of overall misses 1128system.cpu.dcache.overall_misses::total 618626 # number of overall misses 1129system.cpu.dcache.ReadReq_miss_latency::cpu.data 5378545500 # number of ReadReq miss cycles 1130system.cpu.dcache.ReadReq_miss_latency::total 5378545500 # number of ReadReq miss cycles 1131system.cpu.dcache.WriteReq_miss_latency::cpu.data 10531910500 # number of WriteReq miss cycles 1132system.cpu.dcache.WriteReq_miss_latency::total 10531910500 # number of WriteReq miss cycles 1133system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 158860000 # number of LoadLockedReq miss cycles 1134system.cpu.dcache.LoadLockedReq_miss_latency::total 158860000 # number of LoadLockedReq miss cycles 1135system.cpu.dcache.demand_miss_latency::cpu.data 15910456000 # number of demand (read+write) miss cycles 1136system.cpu.dcache.demand_miss_latency::total 15910456000 # number of demand (read+write) miss cycles 1137system.cpu.dcache.overall_miss_latency::cpu.data 15910456000 # number of overall miss cycles 1138system.cpu.dcache.overall_miss_latency::total 15910456000 # number of overall miss cycles 1139system.cpu.dcache.ReadReq_accesses::cpu.data 13564187 # number of ReadReq accesses(hits+misses) 1140system.cpu.dcache.ReadReq_accesses::total 13564187 # number of ReadReq accesses(hits+misses) 1141system.cpu.dcache.WriteReq_accesses::cpu.data 10223003 # number of WriteReq accesses(hits+misses) 1142system.cpu.dcache.WriteReq_accesses::total 10223003 # number of WriteReq accesses(hits+misses) 1143system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247798 # number of LoadLockedReq accesses(hits+misses) 1144system.cpu.dcache.LoadLockedReq_accesses::total 247798 # number of LoadLockedReq accesses(hits+misses) 1145system.cpu.dcache.StoreCondReq_accesses::cpu.data 247797 # number of StoreCondReq accesses(hits+misses) 1146system.cpu.dcache.StoreCondReq_accesses::total 247797 # number of StoreCondReq accesses(hits+misses) 1147system.cpu.dcache.demand_accesses::cpu.data 23787190 # number of demand (read+write) accesses 1148system.cpu.dcache.demand_accesses::total 23787190 # number of demand (read+write) accesses 1149system.cpu.dcache.overall_accesses::cpu.data 23787190 # number of overall (read+write) accesses 1150system.cpu.dcache.overall_accesses::total 23787190 # number of overall (read+write) accesses 1151system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027156 # miss rate for ReadReq accesses 1152system.cpu.dcache.ReadReq_miss_rate::total 0.027156 # miss rate for ReadReq accesses 1153system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024482 # miss rate for WriteReq accesses 1154system.cpu.dcache.WriteReq_miss_rate::total 0.024482 # miss rate for WriteReq accesses 1155system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046219 # miss rate for LoadLockedReq accesses 1156system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046219 # miss rate for LoadLockedReq accesses 1157system.cpu.dcache.demand_miss_rate::cpu.data 0.026007 # miss rate for demand accesses 1158system.cpu.dcache.demand_miss_rate::total 0.026007 # miss rate for demand accesses 1159system.cpu.dcache.overall_miss_rate::cpu.data 0.026007 # miss rate for overall accesses 1160system.cpu.dcache.overall_miss_rate::total 0.026007 # miss rate for overall accesses 1161system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14601.844185 # average ReadReq miss latency 1162system.cpu.dcache.ReadReq_avg_miss_latency::total 14601.844185 # average ReadReq miss latency 1163system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42080.679961 # average WriteReq miss latency 1164system.cpu.dcache.WriteReq_avg_miss_latency::total 42080.679961 # average WriteReq miss latency 1165system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13870.601589 # average LoadLockedReq miss latency 1166system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13870.601589 # average LoadLockedReq miss latency 1167system.cpu.dcache.demand_avg_miss_latency::cpu.data 25719.022479 # average overall miss latency 1168system.cpu.dcache.demand_avg_miss_latency::total 25719.022479 # average overall miss latency 1169system.cpu.dcache.overall_avg_miss_latency::cpu.data 25719.022479 # average overall miss latency 1170system.cpu.dcache.overall_avg_miss_latency::total 25719.022479 # average overall miss latency 1171system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1172system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1173system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1174system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 1175system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1176system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1177system.cpu.dcache.fast_writes 0 # number of fast writes performed 1178system.cpu.dcache.cache_copies 0 # number of cache copies performed 1179system.cpu.dcache.writebacks::writebacks 595512 # number of writebacks 1180system.cpu.dcache.writebacks::total 595512 # number of writebacks 1181system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368347 # number of ReadReq MSHR misses 1182system.cpu.dcache.ReadReq_mshr_misses::total 368347 # number of ReadReq MSHR misses 1183system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250279 # number of WriteReq MSHR misses 1184system.cpu.dcache.WriteReq_mshr_misses::total 250279 # number of WriteReq MSHR misses 1185system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11453 # number of LoadLockedReq MSHR misses 1186system.cpu.dcache.LoadLockedReq_mshr_misses::total 11453 # number of LoadLockedReq MSHR misses 1187system.cpu.dcache.demand_mshr_misses::cpu.data 618626 # number of demand (read+write) MSHR misses 1188system.cpu.dcache.demand_mshr_misses::total 618626 # number of demand (read+write) MSHR misses 1189system.cpu.dcache.overall_mshr_misses::cpu.data 618626 # number of overall MSHR misses 1190system.cpu.dcache.overall_mshr_misses::total 618626 # number of overall MSHR misses 1191system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4641851500 # number of ReadReq MSHR miss cycles 1192system.cpu.dcache.ReadReq_mshr_miss_latency::total 4641851500 # number of ReadReq MSHR miss cycles 1193system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10031352500 # number of WriteReq MSHR miss cycles 1194system.cpu.dcache.WriteReq_mshr_miss_latency::total 10031352500 # number of WriteReq MSHR miss cycles 1195system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 135954000 # number of LoadLockedReq MSHR miss cycles 1196system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 135954000 # number of LoadLockedReq MSHR miss cycles 1197system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14673204000 # number of demand (read+write) MSHR miss cycles 1198system.cpu.dcache.demand_mshr_miss_latency::total 14673204000 # number of demand (read+write) MSHR miss cycles 1199system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14673204000 # number of overall MSHR miss cycles 1200system.cpu.dcache.overall_mshr_miss_latency::total 14673204000 # number of overall MSHR miss cycles 1201system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182050723500 # number of ReadReq MSHR uncacheable cycles 1202system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182050723500 # number of ReadReq MSHR uncacheable cycles 1203system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26234076500 # number of WriteReq MSHR uncacheable cycles 1204system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26234076500 # number of WriteReq MSHR uncacheable cycles 1205system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208284800000 # number of overall MSHR uncacheable cycles 1206system.cpu.dcache.overall_mshr_uncacheable_latency::total 208284800000 # number of overall MSHR uncacheable cycles 1207system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027156 # mshr miss rate for ReadReq accesses 1208system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027156 # mshr miss rate for ReadReq accesses 1209system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024482 # mshr miss rate for WriteReq accesses 1210system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024482 # mshr miss rate for WriteReq accesses 1211system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046219 # mshr miss rate for LoadLockedReq accesses 1212system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046219 # mshr miss rate for LoadLockedReq accesses 1213system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026007 # mshr miss rate for demand accesses 1214system.cpu.dcache.demand_mshr_miss_rate::total 0.026007 # mshr miss rate for demand accesses 1215system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026007 # mshr miss rate for overall accesses 1216system.cpu.dcache.overall_mshr_miss_rate::total 0.026007 # mshr miss rate for overall accesses 1217system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12601.844185 # average ReadReq mshr miss latency 1218system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12601.844185 # average ReadReq mshr miss latency 1219system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40080.679961 # average WriteReq mshr miss latency 1220system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40080.679961 # average WriteReq mshr miss latency 1221system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11870.601589 # average LoadLockedReq mshr miss latency 1222system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11870.601589 # average LoadLockedReq mshr miss latency 1223system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23719.022479 # average overall mshr miss latency 1224system.cpu.dcache.demand_avg_mshr_miss_latency::total 23719.022479 # average overall mshr miss latency 1225system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23719.022479 # average overall mshr miss latency 1226system.cpu.dcache.overall_avg_mshr_miss_latency::total 23719.022479 # average overall mshr miss latency 1227system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1228system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1229system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1230system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1231system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1232system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1233system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1234system.cpu.toL2Bus.throughput 53002965 # Throughput (bytes/s) 1235system.cpu.toL2Bus.trans_dist::ReadReq 2454953 # Transaction distribution 1236system.cpu.toL2Bus.trans_dist::ReadResp 2454953 # Transaction distribution 1237system.cpu.toL2Bus.trans_dist::WriteReq 763368 # Transaction distribution 1238system.cpu.toL2Bus.trans_dist::WriteResp 763368 # Transaction distribution 1239system.cpu.toL2Bus.trans_dist::Writeback 595512 # Transaction distribution 1240system.cpu.toL2Bus.trans_dist::UpgradeReq 2911 # Transaction distribution 1241system.cpu.toL2Bus.trans_dist::UpgradeResp 2911 # Transaction distribution 1242system.cpu.toL2Bus.trans_dist::ReadExReq 247368 # Transaction distribution 1243system.cpu.toL2Bus.trans_dist::ReadExResp 247368 # Transaction distribution 1244system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1725126 # Packet count per connected master and slave (bytes) 1245system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 5750616 # Packet count per connected master and slave (bytes) 1246system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma 12461 # Packet count per connected master and slave (bytes) 1247system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma 27468 # Packet count per connected master and slave (bytes) 1248system.cpu.toL2Bus.pkt_count 7515671 # Packet count per connected master and slave (bytes) 1249system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 54754292 # Cumulative packet size per connected master and slave (bytes) 1250system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 83665829 # Cumulative packet size per connected master and slave (bytes) 1251system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma 14140 # Cumulative packet size per connected master and slave (bytes) 1252system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma 34916 # Cumulative packet size per connected master and slave (bytes) 1253system.cpu.toL2Bus.tot_pkt_size 138469177 # Cumulative packet size per connected master and slave (bytes) 1254system.cpu.toL2Bus.data_through_bus 138469177 # Total data (bytes) 1255system.cpu.toL2Bus.snoop_data_through_bus 166564 # Total snoop data (bytes) 1256system.cpu.toL2Bus.reqLayer0.occupancy 3009252000 # Layer occupancy (ticks) 1257system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1258system.cpu.toL2Bus.respLayer0.occupancy 1291764000 # Layer occupancy (ticks) 1259system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1260system.cpu.toL2Bus.respLayer1.occupancy 2507996500 # Layer occupancy (ticks) 1261system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1262system.cpu.toL2Bus.respLayer2.occupancy 8926000 # Layer occupancy (ticks) 1263system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1264system.cpu.toL2Bus.respLayer3.occupancy 18739000 # Layer occupancy (ticks) 1265system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1266system.iocache.replacements 0 # number of replacements 1267system.iocache.tagsinuse 0 # Cycle average of tags in use 1268system.iocache.total_refs 0 # Total number of references to valid blocks. 1269system.iocache.sampled_refs 0 # Sample count of references to valid blocks. 1270system.iocache.avg_refs nan # Average number of references to valid blocks. 1271system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1272system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1273system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1274system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1275system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1276system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1277system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1278system.iocache.fast_writes 0 # number of fast writes performed 1279system.iocache.cache_copies 0 # number of cache copies performed 1280system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1470128900250 # number of ReadReq MSHR uncacheable cycles 1281system.iocache.ReadReq_mshr_uncacheable_latency::total 1470128900250 # number of ReadReq MSHR uncacheable cycles 1282system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1470128900250 # number of overall MSHR uncacheable cycles 1283system.iocache.overall_mshr_uncacheable_latency::total 1470128900250 # number of overall MSHR uncacheable cycles 1284system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1285system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1286system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1287system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1288system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1289 1290---------- End Simulation Statistics ---------- 1291