stats.txt revision 9265:8fe936e937bd
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.629150 # Number of seconds simulated 4sim_ticks 2629149747000 # Number of ticks simulated 5final_tick 2629149747000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 556259 # Simulator instruction rate (inst/s) 8host_op_rate 707830 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 24290841486 # Simulator tick rate (ticks/s) 10host_mem_usage 380276 # Number of bytes of host memory used 11host_seconds 108.24 # Real time elapsed on the host 12sim_insts 60207390 # Number of instructions simulated 13sim_ops 76612873 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.dtb.walker 256 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.inst 705696 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 9115408 # Number of bytes read from this memory 19system.physmem.bytes_read::total 134077744 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 705696 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 705696 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 3736256 # Number of bytes written to this memory 23system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory 24system.physmem.bytes_written::total 6752328 # Number of bytes written to this memory 25system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.dtb.walker 4 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.inst 17229 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.data 142462 # Number of read requests responded to by this memory 30system.physmem.num_reads::total 15691729 # Number of read requests responded to by this memory 31system.physmem.num_writes::writebacks 58379 # Number of write requests responded to by this memory 32system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory 33system.physmem.num_writes::total 812397 # Number of write requests responded to by this memory 34system.physmem.bw_read::realview.clcd 47261004 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::cpu.dtb.walker 97 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.itb.walker 49 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.inst 268412 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.data 3467055 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::total 50996618 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu.inst 268412 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 268412 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 1421089 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::cpu.data 1147166 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_write::total 2568255 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_total::writebacks 1421089 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::realview.clcd 47261004 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.dtb.walker 97 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.inst 268412 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.data 4614222 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::total 53564873 # Total bandwidth to/from this memory (bytes/s) 52system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory 53system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory 54system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory 55system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory 56system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory 57system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory 58system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) 59system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) 60system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) 61system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) 62system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) 63system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) 64system.l2c.replacements 62933 # number of replacements 65system.l2c.tagsinuse 51862.510726 # Cycle average of tags in use 66system.l2c.total_refs 1683379 # Total number of references to valid blocks. 67system.l2c.sampled_refs 128318 # Sample count of references to valid blocks. 68system.l2c.avg_refs 13.118806 # Average number of references to valid blocks. 69system.l2c.warmup_cycle 2576532162000 # Cycle when the warmup percentage was hit. 70system.l2c.occ_blocks::writebacks 38450.903251 # Average occupied blocks per requestor 71system.l2c.occ_blocks::cpu.dtb.walker 2.914018 # Average occupied blocks per requestor 72system.l2c.occ_blocks::cpu.itb.walker 0.000670 # Average occupied blocks per requestor 73system.l2c.occ_blocks::cpu.inst 7005.048584 # Average occupied blocks per requestor 74system.l2c.occ_blocks::cpu.data 6403.644203 # Average occupied blocks per requestor 75system.l2c.occ_percent::writebacks 0.586714 # Average percentage of cache occupancy 76system.l2c.occ_percent::cpu.dtb.walker 0.000044 # Average percentage of cache occupancy 77system.l2c.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy 78system.l2c.occ_percent::cpu.inst 0.106889 # Average percentage of cache occupancy 79system.l2c.occ_percent::cpu.data 0.097712 # Average percentage of cache occupancy 80system.l2c.occ_percent::total 0.791359 # Average percentage of cache occupancy 81system.l2c.ReadReq_hits::cpu.dtb.walker 8836 # number of ReadReq hits 82system.l2c.ReadReq_hits::cpu.itb.walker 3549 # number of ReadReq hits 83system.l2c.ReadReq_hits::cpu.inst 844195 # number of ReadReq hits 84system.l2c.ReadReq_hits::cpu.data 370308 # number of ReadReq hits 85system.l2c.ReadReq_hits::total 1226888 # number of ReadReq hits 86system.l2c.Writeback_hits::writebacks 596416 # number of Writeback hits 87system.l2c.Writeback_hits::total 596416 # number of Writeback hits 88system.l2c.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits 89system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits 90system.l2c.ReadExReq_hits::cpu.data 113846 # number of ReadExReq hits 91system.l2c.ReadExReq_hits::total 113846 # number of ReadExReq hits 92system.l2c.demand_hits::cpu.dtb.walker 8836 # number of demand (read+write) hits 93system.l2c.demand_hits::cpu.itb.walker 3549 # number of demand (read+write) hits 94system.l2c.demand_hits::cpu.inst 844195 # number of demand (read+write) hits 95system.l2c.demand_hits::cpu.data 484154 # number of demand (read+write) hits 96system.l2c.demand_hits::total 1340734 # number of demand (read+write) hits 97system.l2c.overall_hits::cpu.dtb.walker 8836 # number of overall hits 98system.l2c.overall_hits::cpu.itb.walker 3549 # number of overall hits 99system.l2c.overall_hits::cpu.inst 844195 # number of overall hits 100system.l2c.overall_hits::cpu.data 484154 # number of overall hits 101system.l2c.overall_hits::total 1340734 # number of overall hits 102system.l2c.ReadReq_misses::cpu.dtb.walker 4 # number of ReadReq misses 103system.l2c.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses 104system.l2c.ReadReq_misses::cpu.inst 10613 # number of ReadReq misses 105system.l2c.ReadReq_misses::cpu.data 10261 # number of ReadReq misses 106system.l2c.ReadReq_misses::total 20880 # number of ReadReq misses 107system.l2c.UpgradeReq_misses::cpu.data 2845 # number of UpgradeReq misses 108system.l2c.UpgradeReq_misses::total 2845 # number of UpgradeReq misses 109system.l2c.ReadExReq_misses::cpu.data 133824 # number of ReadExReq misses 110system.l2c.ReadExReq_misses::total 133824 # number of ReadExReq misses 111system.l2c.demand_misses::cpu.dtb.walker 4 # number of demand (read+write) misses 112system.l2c.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses 113system.l2c.demand_misses::cpu.inst 10613 # number of demand (read+write) misses 114system.l2c.demand_misses::cpu.data 144085 # number of demand (read+write) misses 115system.l2c.demand_misses::total 154704 # number of demand (read+write) misses 116system.l2c.overall_misses::cpu.dtb.walker 4 # number of overall misses 117system.l2c.overall_misses::cpu.itb.walker 2 # number of overall misses 118system.l2c.overall_misses::cpu.inst 10613 # number of overall misses 119system.l2c.overall_misses::cpu.data 144085 # number of overall misses 120system.l2c.overall_misses::total 154704 # number of overall misses 121system.l2c.ReadReq_miss_latency::cpu.dtb.walker 208000 # number of ReadReq miss cycles 122system.l2c.ReadReq_miss_latency::cpu.itb.walker 104000 # number of ReadReq miss cycles 123system.l2c.ReadReq_miss_latency::cpu.inst 553137500 # number of ReadReq miss cycles 124system.l2c.ReadReq_miss_latency::cpu.data 534185000 # number of ReadReq miss cycles 125system.l2c.ReadReq_miss_latency::total 1087634500 # number of ReadReq miss cycles 126system.l2c.UpgradeReq_miss_latency::cpu.data 1040000 # number of UpgradeReq miss cycles 127system.l2c.UpgradeReq_miss_latency::total 1040000 # number of UpgradeReq miss cycles 128system.l2c.ReadExReq_miss_latency::cpu.data 6961477000 # number of ReadExReq miss cycles 129system.l2c.ReadExReq_miss_latency::total 6961477000 # number of ReadExReq miss cycles 130system.l2c.demand_miss_latency::cpu.dtb.walker 208000 # number of demand (read+write) miss cycles 131system.l2c.demand_miss_latency::cpu.itb.walker 104000 # number of demand (read+write) miss cycles 132system.l2c.demand_miss_latency::cpu.inst 553137500 # number of demand (read+write) miss cycles 133system.l2c.demand_miss_latency::cpu.data 7495662000 # number of demand (read+write) miss cycles 134system.l2c.demand_miss_latency::total 8049111500 # number of demand (read+write) miss cycles 135system.l2c.overall_miss_latency::cpu.dtb.walker 208000 # number of overall miss cycles 136system.l2c.overall_miss_latency::cpu.itb.walker 104000 # number of overall miss cycles 137system.l2c.overall_miss_latency::cpu.inst 553137500 # number of overall miss cycles 138system.l2c.overall_miss_latency::cpu.data 7495662000 # number of overall miss cycles 139system.l2c.overall_miss_latency::total 8049111500 # number of overall miss cycles 140system.l2c.ReadReq_accesses::cpu.dtb.walker 8840 # number of ReadReq accesses(hits+misses) 141system.l2c.ReadReq_accesses::cpu.itb.walker 3551 # number of ReadReq accesses(hits+misses) 142system.l2c.ReadReq_accesses::cpu.inst 854808 # number of ReadReq accesses(hits+misses) 143system.l2c.ReadReq_accesses::cpu.data 380569 # number of ReadReq accesses(hits+misses) 144system.l2c.ReadReq_accesses::total 1247768 # number of ReadReq accesses(hits+misses) 145system.l2c.Writeback_accesses::writebacks 596416 # number of Writeback accesses(hits+misses) 146system.l2c.Writeback_accesses::total 596416 # number of Writeback accesses(hits+misses) 147system.l2c.UpgradeReq_accesses::cpu.data 2871 # number of UpgradeReq accesses(hits+misses) 148system.l2c.UpgradeReq_accesses::total 2871 # number of UpgradeReq accesses(hits+misses) 149system.l2c.ReadExReq_accesses::cpu.data 247670 # number of ReadExReq accesses(hits+misses) 150system.l2c.ReadExReq_accesses::total 247670 # number of ReadExReq accesses(hits+misses) 151system.l2c.demand_accesses::cpu.dtb.walker 8840 # number of demand (read+write) accesses 152system.l2c.demand_accesses::cpu.itb.walker 3551 # number of demand (read+write) accesses 153system.l2c.demand_accesses::cpu.inst 854808 # number of demand (read+write) accesses 154system.l2c.demand_accesses::cpu.data 628239 # number of demand (read+write) accesses 155system.l2c.demand_accesses::total 1495438 # number of demand (read+write) accesses 156system.l2c.overall_accesses::cpu.dtb.walker 8840 # number of overall (read+write) accesses 157system.l2c.overall_accesses::cpu.itb.walker 3551 # number of overall (read+write) accesses 158system.l2c.overall_accesses::cpu.inst 854808 # number of overall (read+write) accesses 159system.l2c.overall_accesses::cpu.data 628239 # number of overall (read+write) accesses 160system.l2c.overall_accesses::total 1495438 # number of overall (read+write) accesses 161system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000452 # miss rate for ReadReq accesses 162system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000563 # miss rate for ReadReq accesses 163system.l2c.ReadReq_miss_rate::cpu.inst 0.012416 # miss rate for ReadReq accesses 164system.l2c.ReadReq_miss_rate::cpu.data 0.026962 # miss rate for ReadReq accesses 165system.l2c.ReadReq_miss_rate::total 0.016734 # miss rate for ReadReq accesses 166system.l2c.UpgradeReq_miss_rate::cpu.data 0.990944 # miss rate for UpgradeReq accesses 167system.l2c.UpgradeReq_miss_rate::total 0.990944 # miss rate for UpgradeReq accesses 168system.l2c.ReadExReq_miss_rate::cpu.data 0.540332 # miss rate for ReadExReq accesses 169system.l2c.ReadExReq_miss_rate::total 0.540332 # miss rate for ReadExReq accesses 170system.l2c.demand_miss_rate::cpu.dtb.walker 0.000452 # miss rate for demand accesses 171system.l2c.demand_miss_rate::cpu.itb.walker 0.000563 # miss rate for demand accesses 172system.l2c.demand_miss_rate::cpu.inst 0.012416 # miss rate for demand accesses 173system.l2c.demand_miss_rate::cpu.data 0.229347 # miss rate for demand accesses 174system.l2c.demand_miss_rate::total 0.103451 # miss rate for demand accesses 175system.l2c.overall_miss_rate::cpu.dtb.walker 0.000452 # miss rate for overall accesses 176system.l2c.overall_miss_rate::cpu.itb.walker 0.000563 # miss rate for overall accesses 177system.l2c.overall_miss_rate::cpu.inst 0.012416 # miss rate for overall accesses 178system.l2c.overall_miss_rate::cpu.data 0.229347 # miss rate for overall accesses 179system.l2c.overall_miss_rate::total 0.103451 # miss rate for overall accesses 180system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52000 # average ReadReq miss latency 181system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency 182system.l2c.ReadReq_avg_miss_latency::cpu.inst 52118.863658 # average ReadReq miss latency 183system.l2c.ReadReq_avg_miss_latency::cpu.data 52059.740766 # average ReadReq miss latency 184system.l2c.ReadReq_avg_miss_latency::total 52089.774904 # average ReadReq miss latency 185system.l2c.UpgradeReq_avg_miss_latency::cpu.data 365.553603 # average UpgradeReq miss latency 186system.l2c.UpgradeReq_avg_miss_latency::total 365.553603 # average UpgradeReq miss latency 187system.l2c.ReadExReq_avg_miss_latency::cpu.data 52019.645206 # average ReadExReq miss latency 188system.l2c.ReadExReq_avg_miss_latency::total 52019.645206 # average ReadExReq miss latency 189system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52000 # average overall miss latency 190system.l2c.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency 191system.l2c.demand_avg_miss_latency::cpu.inst 52118.863658 # average overall miss latency 192system.l2c.demand_avg_miss_latency::cpu.data 52022.500607 # average overall miss latency 193system.l2c.demand_avg_miss_latency::total 52029.110430 # average overall miss latency 194system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52000 # average overall miss latency 195system.l2c.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency 196system.l2c.overall_avg_miss_latency::cpu.inst 52118.863658 # average overall miss latency 197system.l2c.overall_avg_miss_latency::cpu.data 52022.500607 # average overall miss latency 198system.l2c.overall_avg_miss_latency::total 52029.110430 # average overall miss latency 199system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 200system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 201system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 202system.l2c.blocked::no_targets 0 # number of cycles access was blocked 203system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 204system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 205system.l2c.fast_writes 0 # number of fast writes performed 206system.l2c.cache_copies 0 # number of cache copies performed 207system.l2c.writebacks::writebacks 58379 # number of writebacks 208system.l2c.writebacks::total 58379 # number of writebacks 209system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 4 # number of ReadReq MSHR misses 210system.l2c.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses 211system.l2c.ReadReq_mshr_misses::cpu.inst 10613 # number of ReadReq MSHR misses 212system.l2c.ReadReq_mshr_misses::cpu.data 10261 # number of ReadReq MSHR misses 213system.l2c.ReadReq_mshr_misses::total 20880 # number of ReadReq MSHR misses 214system.l2c.UpgradeReq_mshr_misses::cpu.data 2845 # number of UpgradeReq MSHR misses 215system.l2c.UpgradeReq_mshr_misses::total 2845 # number of UpgradeReq MSHR misses 216system.l2c.ReadExReq_mshr_misses::cpu.data 133824 # number of ReadExReq MSHR misses 217system.l2c.ReadExReq_mshr_misses::total 133824 # number of ReadExReq MSHR misses 218system.l2c.demand_mshr_misses::cpu.dtb.walker 4 # number of demand (read+write) MSHR misses 219system.l2c.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses 220system.l2c.demand_mshr_misses::cpu.inst 10613 # number of demand (read+write) MSHR misses 221system.l2c.demand_mshr_misses::cpu.data 144085 # number of demand (read+write) MSHR misses 222system.l2c.demand_mshr_misses::total 154704 # number of demand (read+write) MSHR misses 223system.l2c.overall_mshr_misses::cpu.dtb.walker 4 # number of overall MSHR misses 224system.l2c.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses 225system.l2c.overall_mshr_misses::cpu.inst 10613 # number of overall MSHR misses 226system.l2c.overall_mshr_misses::cpu.data 144085 # number of overall MSHR misses 227system.l2c.overall_mshr_misses::total 154704 # number of overall MSHR misses 228system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 160000 # number of ReadReq MSHR miss cycles 229system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 80000 # number of ReadReq MSHR miss cycles 230system.l2c.ReadReq_mshr_miss_latency::cpu.inst 425775500 # number of ReadReq MSHR miss cycles 231system.l2c.ReadReq_mshr_miss_latency::cpu.data 411049000 # number of ReadReq MSHR miss cycles 232system.l2c.ReadReq_mshr_miss_latency::total 837064500 # number of ReadReq MSHR miss cycles 233system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 114083000 # number of UpgradeReq MSHR miss cycles 234system.l2c.UpgradeReq_mshr_miss_latency::total 114083000 # number of UpgradeReq MSHR miss cycles 235system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5355569000 # number of ReadExReq MSHR miss cycles 236system.l2c.ReadExReq_mshr_miss_latency::total 5355569000 # number of ReadExReq MSHR miss cycles 237system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 160000 # number of demand (read+write) MSHR miss cycles 238system.l2c.demand_mshr_miss_latency::cpu.itb.walker 80000 # number of demand (read+write) MSHR miss cycles 239system.l2c.demand_mshr_miss_latency::cpu.inst 425775500 # number of demand (read+write) MSHR miss cycles 240system.l2c.demand_mshr_miss_latency::cpu.data 5766618000 # number of demand (read+write) MSHR miss cycles 241system.l2c.demand_mshr_miss_latency::total 6192633500 # number of demand (read+write) MSHR miss cycles 242system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 160000 # number of overall MSHR miss cycles 243system.l2c.overall_mshr_miss_latency::cpu.itb.walker 80000 # number of overall MSHR miss cycles 244system.l2c.overall_mshr_miss_latency::cpu.inst 425775500 # number of overall MSHR miss cycles 245system.l2c.overall_mshr_miss_latency::cpu.data 5766618000 # number of overall MSHR miss cycles 246system.l2c.overall_mshr_miss_latency::total 6192633500 # number of overall MSHR miss cycles 247system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 264840000 # number of ReadReq MSHR uncacheable cycles 248system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 166753837500 # number of ReadReq MSHR uncacheable cycles 249system.l2c.ReadReq_mshr_uncacheable_latency::total 167018677500 # number of ReadReq MSHR uncacheable cycles 250system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 31852864000 # number of WriteReq MSHR uncacheable cycles 251system.l2c.WriteReq_mshr_uncacheable_latency::total 31852864000 # number of WriteReq MSHR uncacheable cycles 252system.l2c.overall_mshr_uncacheable_latency::cpu.inst 264840000 # number of overall MSHR uncacheable cycles 253system.l2c.overall_mshr_uncacheable_latency::cpu.data 198606701500 # number of overall MSHR uncacheable cycles 254system.l2c.overall_mshr_uncacheable_latency::total 198871541500 # number of overall MSHR uncacheable cycles 255system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000452 # mshr miss rate for ReadReq accesses 256system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000563 # mshr miss rate for ReadReq accesses 257system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.012416 # mshr miss rate for ReadReq accesses 258system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.026962 # mshr miss rate for ReadReq accesses 259system.l2c.ReadReq_mshr_miss_rate::total 0.016734 # mshr miss rate for ReadReq accesses 260system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.990944 # mshr miss rate for UpgradeReq accesses 261system.l2c.UpgradeReq_mshr_miss_rate::total 0.990944 # mshr miss rate for UpgradeReq accesses 262system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.540332 # mshr miss rate for ReadExReq accesses 263system.l2c.ReadExReq_mshr_miss_rate::total 0.540332 # mshr miss rate for ReadExReq accesses 264system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000452 # mshr miss rate for demand accesses 265system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000563 # mshr miss rate for demand accesses 266system.l2c.demand_mshr_miss_rate::cpu.inst 0.012416 # mshr miss rate for demand accesses 267system.l2c.demand_mshr_miss_rate::cpu.data 0.229347 # mshr miss rate for demand accesses 268system.l2c.demand_mshr_miss_rate::total 0.103451 # mshr miss rate for demand accesses 269system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000452 # mshr miss rate for overall accesses 270system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000563 # mshr miss rate for overall accesses 271system.l2c.overall_mshr_miss_rate::cpu.inst 0.012416 # mshr miss rate for overall accesses 272system.l2c.overall_mshr_miss_rate::cpu.data 0.229347 # mshr miss rate for overall accesses 273system.l2c.overall_mshr_miss_rate::total 0.103451 # mshr miss rate for overall accesses 274system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average ReadReq mshr miss latency 275system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency 276system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40118.298313 # average ReadReq mshr miss latency 277system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40059.350940 # average ReadReq mshr miss latency 278system.l2c.ReadReq_avg_mshr_miss_latency::total 40089.295977 # average ReadReq mshr miss latency 279system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40099.472759 # average UpgradeReq mshr miss latency 280system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40099.472759 # average UpgradeReq mshr miss latency 281system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40019.495756 # average ReadExReq mshr miss latency 282system.l2c.ReadExReq_avg_mshr_miss_latency::total 40019.495756 # average ReadExReq mshr miss latency 283system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency 284system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency 285system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40118.298313 # average overall mshr miss latency 286system.l2c.demand_avg_mshr_miss_latency::cpu.data 40022.334039 # average overall mshr miss latency 287system.l2c.demand_avg_mshr_miss_latency::total 40028.916512 # average overall mshr miss latency 288system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency 289system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency 290system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40118.298313 # average overall mshr miss latency 291system.l2c.overall_avg_mshr_miss_latency::cpu.data 40022.334039 # average overall mshr miss latency 292system.l2c.overall_avg_mshr_miss_latency::total 40028.916512 # average overall mshr miss latency 293system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 294system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 295system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 296system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 297system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 298system.l2c.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 299system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 300system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 301system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 302system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 303system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 304system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 305system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 306system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 307system.cf0.dma_write_txs 0 # Number of DMA write transactions. 308system.cpu.dtb.inst_hits 0 # ITB inst hits 309system.cpu.dtb.inst_misses 0 # ITB inst misses 310system.cpu.dtb.read_hits 14998169 # DTB read hits 311system.cpu.dtb.read_misses 7372 # DTB read misses 312system.cpu.dtb.write_hits 11231565 # DTB write hits 313system.cpu.dtb.write_misses 2270 # DTB write misses 314system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed 315system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 316system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 317system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 318system.cpu.dtb.flush_entries 3524 # Number of entries that have been flushed from TLB 319system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 320system.cpu.dtb.prefetch_faults 231 # Number of TLB faults due to prefetch 321system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 322system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions 323system.cpu.dtb.read_accesses 15005541 # DTB read accesses 324system.cpu.dtb.write_accesses 11233835 # DTB write accesses 325system.cpu.dtb.inst_accesses 0 # ITB inst accesses 326system.cpu.dtb.hits 26229734 # DTB hits 327system.cpu.dtb.misses 9642 # DTB misses 328system.cpu.dtb.accesses 26239376 # DTB accesses 329system.cpu.itb.inst_hits 61501359 # ITB inst hits 330system.cpu.itb.inst_misses 4471 # ITB inst misses 331system.cpu.itb.read_hits 0 # DTB read hits 332system.cpu.itb.read_misses 0 # DTB read misses 333system.cpu.itb.write_hits 0 # DTB write hits 334system.cpu.itb.write_misses 0 # DTB write misses 335system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed 336system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 337system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 338system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 339system.cpu.itb.flush_entries 2343 # Number of entries that have been flushed from TLB 340system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 341system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 342system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 343system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 344system.cpu.itb.read_accesses 0 # DTB read accesses 345system.cpu.itb.write_accesses 0 # DTB write accesses 346system.cpu.itb.inst_accesses 61505830 # ITB inst accesses 347system.cpu.itb.hits 61501359 # DTB hits 348system.cpu.itb.misses 4471 # DTB misses 349system.cpu.itb.accesses 61505830 # DTB accesses 350system.cpu.numCycles 5258299494 # number of cpu cycles simulated 351system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 352system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 353system.cpu.committedInsts 60207390 # Number of instructions committed 354system.cpu.committedOps 76612873 # Number of ops (including micro ops) committed 355system.cpu.num_int_alu_accesses 68878830 # Number of integer alu accesses 356system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses 357system.cpu.num_func_calls 2140176 # number of times a function call or return occured 358system.cpu.num_conditional_control_insts 7948958 # number of instructions that are conditional controls 359system.cpu.num_int_insts 68878830 # number of integer instructions 360system.cpu.num_fp_insts 10269 # number of float instructions 361system.cpu.num_int_register_reads 394820534 # number of times the integer registers were read 362system.cpu.num_int_register_writes 74191435 # number of times the integer registers were written 363system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read 364system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written 365system.cpu.num_mem_refs 27397151 # number of memory refs 366system.cpu.num_load_insts 15662227 # Number of load instructions 367system.cpu.num_store_insts 11734924 # Number of store instructions 368system.cpu.num_idle_cycles 4567780450.602262 # Number of idle cycles 369system.cpu.num_busy_cycles 690519043.397737 # Number of busy cycles 370system.cpu.not_idle_fraction 0.131320 # Percentage of non-idle cycles 371system.cpu.idle_fraction 0.868680 # Percentage of idle cycles 372system.cpu.kern.inst.arm 0 # number of arm instructions executed 373system.cpu.kern.inst.quiesce 83013 # number of quiesce instructions executed 374system.cpu.icache.replacements 855930 # number of replacements 375system.cpu.icache.tagsinuse 510.898307 # Cycle average of tags in use 376system.cpu.icache.total_refs 60644917 # Total number of references to valid blocks. 377system.cpu.icache.sampled_refs 856442 # Sample count of references to valid blocks. 378system.cpu.icache.avg_refs 70.810302 # Average number of references to valid blocks. 379system.cpu.icache.warmup_cycle 19819985000 # Cycle when the warmup percentage was hit. 380system.cpu.icache.occ_blocks::cpu.inst 510.898307 # Average occupied blocks per requestor 381system.cpu.icache.occ_percent::cpu.inst 0.997848 # Average percentage of cache occupancy 382system.cpu.icache.occ_percent::total 0.997848 # Average percentage of cache occupancy 383system.cpu.icache.ReadReq_hits::cpu.inst 60644917 # number of ReadReq hits 384system.cpu.icache.ReadReq_hits::total 60644917 # number of ReadReq hits 385system.cpu.icache.demand_hits::cpu.inst 60644917 # number of demand (read+write) hits 386system.cpu.icache.demand_hits::total 60644917 # number of demand (read+write) hits 387system.cpu.icache.overall_hits::cpu.inst 60644917 # number of overall hits 388system.cpu.icache.overall_hits::total 60644917 # number of overall hits 389system.cpu.icache.ReadReq_misses::cpu.inst 856442 # number of ReadReq misses 390system.cpu.icache.ReadReq_misses::total 856442 # number of ReadReq misses 391system.cpu.icache.demand_misses::cpu.inst 856442 # number of demand (read+write) misses 392system.cpu.icache.demand_misses::total 856442 # number of demand (read+write) misses 393system.cpu.icache.overall_misses::cpu.inst 856442 # number of overall misses 394system.cpu.icache.overall_misses::total 856442 # number of overall misses 395system.cpu.icache.ReadReq_miss_latency::cpu.inst 12566277500 # number of ReadReq miss cycles 396system.cpu.icache.ReadReq_miss_latency::total 12566277500 # number of ReadReq miss cycles 397system.cpu.icache.demand_miss_latency::cpu.inst 12566277500 # number of demand (read+write) miss cycles 398system.cpu.icache.demand_miss_latency::total 12566277500 # number of demand (read+write) miss cycles 399system.cpu.icache.overall_miss_latency::cpu.inst 12566277500 # number of overall miss cycles 400system.cpu.icache.overall_miss_latency::total 12566277500 # number of overall miss cycles 401system.cpu.icache.ReadReq_accesses::cpu.inst 61501359 # number of ReadReq accesses(hits+misses) 402system.cpu.icache.ReadReq_accesses::total 61501359 # number of ReadReq accesses(hits+misses) 403system.cpu.icache.demand_accesses::cpu.inst 61501359 # number of demand (read+write) accesses 404system.cpu.icache.demand_accesses::total 61501359 # number of demand (read+write) accesses 405system.cpu.icache.overall_accesses::cpu.inst 61501359 # number of overall (read+write) accesses 406system.cpu.icache.overall_accesses::total 61501359 # number of overall (read+write) accesses 407system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013926 # miss rate for ReadReq accesses 408system.cpu.icache.ReadReq_miss_rate::total 0.013926 # miss rate for ReadReq accesses 409system.cpu.icache.demand_miss_rate::cpu.inst 0.013926 # miss rate for demand accesses 410system.cpu.icache.demand_miss_rate::total 0.013926 # miss rate for demand accesses 411system.cpu.icache.overall_miss_rate::cpu.inst 0.013926 # miss rate for overall accesses 412system.cpu.icache.overall_miss_rate::total 0.013926 # miss rate for overall accesses 413system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14672.654424 # average ReadReq miss latency 414system.cpu.icache.ReadReq_avg_miss_latency::total 14672.654424 # average ReadReq miss latency 415system.cpu.icache.demand_avg_miss_latency::cpu.inst 14672.654424 # average overall miss latency 416system.cpu.icache.demand_avg_miss_latency::total 14672.654424 # average overall miss latency 417system.cpu.icache.overall_avg_miss_latency::cpu.inst 14672.654424 # average overall miss latency 418system.cpu.icache.overall_avg_miss_latency::total 14672.654424 # average overall miss latency 419system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 420system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 421system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 422system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 423system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 424system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 425system.cpu.icache.fast_writes 0 # number of fast writes performed 426system.cpu.icache.cache_copies 0 # number of cache copies performed 427system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856442 # number of ReadReq MSHR misses 428system.cpu.icache.ReadReq_mshr_misses::total 856442 # number of ReadReq MSHR misses 429system.cpu.icache.demand_mshr_misses::cpu.inst 856442 # number of demand (read+write) MSHR misses 430system.cpu.icache.demand_mshr_misses::total 856442 # number of demand (read+write) MSHR misses 431system.cpu.icache.overall_mshr_misses::cpu.inst 856442 # number of overall MSHR misses 432system.cpu.icache.overall_mshr_misses::total 856442 # number of overall MSHR misses 433system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9995044500 # number of ReadReq MSHR miss cycles 434system.cpu.icache.ReadReq_mshr_miss_latency::total 9995044500 # number of ReadReq MSHR miss cycles 435system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9995044500 # number of demand (read+write) MSHR miss cycles 436system.cpu.icache.demand_mshr_miss_latency::total 9995044500 # number of demand (read+write) MSHR miss cycles 437system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9995044500 # number of overall MSHR miss cycles 438system.cpu.icache.overall_mshr_miss_latency::total 9995044500 # number of overall MSHR miss cycles 439system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 350913000 # number of ReadReq MSHR uncacheable cycles 440system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 350913000 # number of ReadReq MSHR uncacheable cycles 441system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 350913000 # number of overall MSHR uncacheable cycles 442system.cpu.icache.overall_mshr_uncacheable_latency::total 350913000 # number of overall MSHR uncacheable cycles 443system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013926 # mshr miss rate for ReadReq accesses 444system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013926 # mshr miss rate for ReadReq accesses 445system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013926 # mshr miss rate for demand accesses 446system.cpu.icache.demand_mshr_miss_rate::total 0.013926 # mshr miss rate for demand accesses 447system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013926 # mshr miss rate for overall accesses 448system.cpu.icache.overall_mshr_miss_rate::total 0.013926 # mshr miss rate for overall accesses 449system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11670.427770 # average ReadReq mshr miss latency 450system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11670.427770 # average ReadReq mshr miss latency 451system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11670.427770 # average overall mshr miss latency 452system.cpu.icache.demand_avg_mshr_miss_latency::total 11670.427770 # average overall mshr miss latency 453system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11670.427770 # average overall mshr miss latency 454system.cpu.icache.overall_avg_mshr_miss_latency::total 11670.427770 # average overall mshr miss latency 455system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 456system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 457system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 458system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 459system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 460system.cpu.dcache.replacements 627727 # number of replacements 461system.cpu.dcache.tagsinuse 511.877273 # Cycle average of tags in use 462system.cpu.dcache.total_refs 23657788 # Total number of references to valid blocks. 463system.cpu.dcache.sampled_refs 628239 # Sample count of references to valid blocks. 464system.cpu.dcache.avg_refs 37.657306 # Average number of references to valid blocks. 465system.cpu.dcache.warmup_cycle 661351000 # Cycle when the warmup percentage was hit. 466system.cpu.dcache.occ_blocks::cpu.data 511.877273 # Average occupied blocks per requestor 467system.cpu.dcache.occ_percent::cpu.data 0.999760 # Average percentage of cache occupancy 468system.cpu.dcache.occ_percent::total 0.999760 # Average percentage of cache occupancy 469system.cpu.dcache.ReadReq_hits::cpu.data 13196825 # number of ReadReq hits 470system.cpu.dcache.ReadReq_hits::total 13196825 # number of ReadReq hits 471system.cpu.dcache.WriteReq_hits::cpu.data 9973191 # number of WriteReq hits 472system.cpu.dcache.WriteReq_hits::total 9973191 # number of WriteReq hits 473system.cpu.dcache.LoadLockedReq_hits::cpu.data 236701 # number of LoadLockedReq hits 474system.cpu.dcache.LoadLockedReq_hits::total 236701 # number of LoadLockedReq hits 475system.cpu.dcache.StoreCondReq_hits::cpu.data 248200 # number of StoreCondReq hits 476system.cpu.dcache.StoreCondReq_hits::total 248200 # number of StoreCondReq hits 477system.cpu.dcache.demand_hits::cpu.data 23170016 # number of demand (read+write) hits 478system.cpu.dcache.demand_hits::total 23170016 # number of demand (read+write) hits 479system.cpu.dcache.overall_hits::cpu.data 23170016 # number of overall hits 480system.cpu.dcache.overall_hits::total 23170016 # number of overall hits 481system.cpu.dcache.ReadReq_misses::cpu.data 369069 # number of ReadReq misses 482system.cpu.dcache.ReadReq_misses::total 369069 # number of ReadReq misses 483system.cpu.dcache.WriteReq_misses::cpu.data 250541 # number of WriteReq misses 484system.cpu.dcache.WriteReq_misses::total 250541 # number of WriteReq misses 485system.cpu.dcache.LoadLockedReq_misses::cpu.data 11500 # number of LoadLockedReq misses 486system.cpu.dcache.LoadLockedReq_misses::total 11500 # number of LoadLockedReq misses 487system.cpu.dcache.demand_misses::cpu.data 619610 # number of demand (read+write) misses 488system.cpu.dcache.demand_misses::total 619610 # number of demand (read+write) misses 489system.cpu.dcache.overall_misses::cpu.data 619610 # number of overall misses 490system.cpu.dcache.overall_misses::total 619610 # number of overall misses 491system.cpu.dcache.ReadReq_miss_latency::cpu.data 5742174000 # number of ReadReq miss cycles 492system.cpu.dcache.ReadReq_miss_latency::total 5742174000 # number of ReadReq miss cycles 493system.cpu.dcache.WriteReq_miss_latency::cpu.data 9260838000 # number of WriteReq miss cycles 494system.cpu.dcache.WriteReq_miss_latency::total 9260838000 # number of WriteReq miss cycles 495system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 170995500 # number of LoadLockedReq miss cycles 496system.cpu.dcache.LoadLockedReq_miss_latency::total 170995500 # number of LoadLockedReq miss cycles 497system.cpu.dcache.demand_miss_latency::cpu.data 15003012000 # number of demand (read+write) miss cycles 498system.cpu.dcache.demand_miss_latency::total 15003012000 # number of demand (read+write) miss cycles 499system.cpu.dcache.overall_miss_latency::cpu.data 15003012000 # number of overall miss cycles 500system.cpu.dcache.overall_miss_latency::total 15003012000 # number of overall miss cycles 501system.cpu.dcache.ReadReq_accesses::cpu.data 13565894 # number of ReadReq accesses(hits+misses) 502system.cpu.dcache.ReadReq_accesses::total 13565894 # number of ReadReq accesses(hits+misses) 503system.cpu.dcache.WriteReq_accesses::cpu.data 10223732 # number of WriteReq accesses(hits+misses) 504system.cpu.dcache.WriteReq_accesses::total 10223732 # number of WriteReq accesses(hits+misses) 505system.cpu.dcache.LoadLockedReq_accesses::cpu.data 248201 # number of LoadLockedReq accesses(hits+misses) 506system.cpu.dcache.LoadLockedReq_accesses::total 248201 # number of LoadLockedReq accesses(hits+misses) 507system.cpu.dcache.StoreCondReq_accesses::cpu.data 248200 # number of StoreCondReq accesses(hits+misses) 508system.cpu.dcache.StoreCondReq_accesses::total 248200 # number of StoreCondReq accesses(hits+misses) 509system.cpu.dcache.demand_accesses::cpu.data 23789626 # number of demand (read+write) accesses 510system.cpu.dcache.demand_accesses::total 23789626 # number of demand (read+write) accesses 511system.cpu.dcache.overall_accesses::cpu.data 23789626 # number of overall (read+write) accesses 512system.cpu.dcache.overall_accesses::total 23789626 # number of overall (read+write) accesses 513system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027206 # miss rate for ReadReq accesses 514system.cpu.dcache.ReadReq_miss_rate::total 0.027206 # miss rate for ReadReq accesses 515system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024506 # miss rate for WriteReq accesses 516system.cpu.dcache.WriteReq_miss_rate::total 0.024506 # miss rate for WriteReq accesses 517system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046333 # miss rate for LoadLockedReq accesses 518system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046333 # miss rate for LoadLockedReq accesses 519system.cpu.dcache.demand_miss_rate::cpu.data 0.026045 # miss rate for demand accesses 520system.cpu.dcache.demand_miss_rate::total 0.026045 # miss rate for demand accesses 521system.cpu.dcache.overall_miss_rate::cpu.data 0.026045 # miss rate for overall accesses 522system.cpu.dcache.overall_miss_rate::total 0.026045 # miss rate for overall accesses 523system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15558.537834 # average ReadReq miss latency 524system.cpu.dcache.ReadReq_avg_miss_latency::total 15558.537834 # average ReadReq miss latency 525system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36963.363282 # average WriteReq miss latency 526system.cpu.dcache.WriteReq_avg_miss_latency::total 36963.363282 # average WriteReq miss latency 527system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14869.173913 # average LoadLockedReq miss latency 528system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14869.173913 # average LoadLockedReq miss latency 529system.cpu.dcache.demand_avg_miss_latency::cpu.data 24213.637611 # average overall miss latency 530system.cpu.dcache.demand_avg_miss_latency::total 24213.637611 # average overall miss latency 531system.cpu.dcache.overall_avg_miss_latency::cpu.data 24213.637611 # average overall miss latency 532system.cpu.dcache.overall_avg_miss_latency::total 24213.637611 # average overall miss latency 533system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 534system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 535system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 536system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 537system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 538system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 539system.cpu.dcache.fast_writes 0 # number of fast writes performed 540system.cpu.dcache.cache_copies 0 # number of cache copies performed 541system.cpu.dcache.writebacks::writebacks 596416 # number of writebacks 542system.cpu.dcache.writebacks::total 596416 # number of writebacks 543system.cpu.dcache.ReadReq_mshr_misses::cpu.data 369069 # number of ReadReq MSHR misses 544system.cpu.dcache.ReadReq_mshr_misses::total 369069 # number of ReadReq MSHR misses 545system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250541 # number of WriteReq MSHR misses 546system.cpu.dcache.WriteReq_mshr_misses::total 250541 # number of WriteReq MSHR misses 547system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11500 # number of LoadLockedReq MSHR misses 548system.cpu.dcache.LoadLockedReq_mshr_misses::total 11500 # number of LoadLockedReq MSHR misses 549system.cpu.dcache.demand_mshr_misses::cpu.data 619610 # number of demand (read+write) MSHR misses 550system.cpu.dcache.demand_mshr_misses::total 619610 # number of demand (read+write) MSHR misses 551system.cpu.dcache.overall_mshr_misses::cpu.data 619610 # number of overall MSHR misses 552system.cpu.dcache.overall_mshr_misses::total 619610 # number of overall MSHR misses 553system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4633803000 # number of ReadReq MSHR miss cycles 554system.cpu.dcache.ReadReq_mshr_miss_latency::total 4633803000 # number of ReadReq MSHR miss cycles 555system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8509109000 # number of WriteReq MSHR miss cycles 556system.cpu.dcache.WriteReq_mshr_miss_latency::total 8509109000 # number of WriteReq MSHR miss cycles 557system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 136482000 # number of LoadLockedReq MSHR miss cycles 558system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 136482000 # number of LoadLockedReq MSHR miss cycles 559system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13142912000 # number of demand (read+write) MSHR miss cycles 560system.cpu.dcache.demand_mshr_miss_latency::total 13142912000 # number of demand (read+write) MSHR miss cycles 561system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13142912000 # number of overall MSHR miss cycles 562system.cpu.dcache.overall_mshr_miss_latency::total 13142912000 # number of overall MSHR miss cycles 563system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182150932500 # number of ReadReq MSHR uncacheable cycles 564system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182150932500 # number of ReadReq MSHR uncacheable cycles 565system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41013343500 # number of WriteReq MSHR uncacheable cycles 566system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41013343500 # number of WriteReq MSHR uncacheable cycles 567system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 223164276000 # number of overall MSHR uncacheable cycles 568system.cpu.dcache.overall_mshr_uncacheable_latency::total 223164276000 # number of overall MSHR uncacheable cycles 569system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027206 # mshr miss rate for ReadReq accesses 570system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027206 # mshr miss rate for ReadReq accesses 571system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024506 # mshr miss rate for WriteReq accesses 572system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024506 # mshr miss rate for WriteReq accesses 573system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046333 # mshr miss rate for LoadLockedReq accesses 574system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046333 # mshr miss rate for LoadLockedReq accesses 575system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026045 # mshr miss rate for demand accesses 576system.cpu.dcache.demand_mshr_miss_rate::total 0.026045 # mshr miss rate for demand accesses 577system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026045 # mshr miss rate for overall accesses 578system.cpu.dcache.overall_mshr_miss_rate::total 0.026045 # mshr miss rate for overall accesses 579system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12555.383953 # average ReadReq mshr miss latency 580system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12555.383953 # average ReadReq mshr miss latency 581system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33962.940197 # average WriteReq mshr miss latency 582system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33962.940197 # average WriteReq mshr miss latency 583system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11868 # average LoadLockedReq mshr miss latency 584system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11868 # average LoadLockedReq mshr miss latency 585system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21211.587934 # average overall mshr miss latency 586system.cpu.dcache.demand_avg_mshr_miss_latency::total 21211.587934 # average overall mshr miss latency 587system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21211.587934 # average overall mshr miss latency 588system.cpu.dcache.overall_avg_mshr_miss_latency::total 21211.587934 # average overall mshr miss latency 589system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 590system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 591system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 592system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 593system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 594system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 595system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 596system.iocache.replacements 0 # number of replacements 597system.iocache.tagsinuse 0 # Cycle average of tags in use 598system.iocache.total_refs 0 # Total number of references to valid blocks. 599system.iocache.sampled_refs 0 # Sample count of references to valid blocks. 600system.iocache.avg_refs nan # Average number of references to valid blocks. 601system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 602system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 603system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 604system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 605system.iocache.blocked::no_targets 0 # number of cycles access was blocked 606system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 607system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 608system.iocache.fast_writes 0 # number of fast writes performed 609system.iocache.cache_copies 0 # number of cache copies performed 610system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1358668189629 # number of ReadReq MSHR uncacheable cycles 611system.iocache.ReadReq_mshr_uncacheable_latency::total 1358668189629 # number of ReadReq MSHR uncacheable cycles 612system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1358668189629 # number of overall MSHR uncacheable cycles 613system.iocache.overall_mshr_uncacheable_latency::total 1358668189629 # number of overall MSHR uncacheable cycles 614system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 615system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 616system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 617system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 618system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 619 620---------- End Simulation Statistics ---------- 621