stats.txt revision 8802:ef66a9083bc4
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.591442 # Number of seconds simulated 4sim_ticks 2591441692000 # Number of ticks simulated 5final_tick 2591441692000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 852555 # Simulator instruction rate (inst/s) 8host_tick_rate 29271571690 # Simulator tick rate (ticks/s) 9host_mem_usage 379496 # Number of bytes of host memory used 10host_seconds 88.53 # Real time elapsed on the host 11sim_insts 75477515 # Number of instructions simulated 12system.nvmem.bytes_read 20 # Number of bytes read from this memory 13system.nvmem.bytes_inst_read 20 # Number of instructions bytes read from this memory 14system.nvmem.bytes_written 0 # Number of bytes written to this memory 15system.nvmem.num_reads 5 # Number of read requests responded to by this memory 16system.nvmem.num_writes 0 # Number of write requests responded to by this memory 17system.nvmem.num_other 0 # Number of other requests responded to by this memory 18system.nvmem.bw_read 8 # Total read bandwidth from this memory (bytes/s) 19system.nvmem.bw_inst_read 8 # Instruction read bandwidth from this memory (bytes/s) 20system.nvmem.bw_total 8 # Total bandwidth to/from this memory (bytes/s) 21system.physmem.bytes_read 133655408 # Number of bytes read from this memory 22system.physmem.bytes_inst_read 949920 # Number of instructions bytes read from this memory 23system.physmem.bytes_written 9634312 # Number of bytes written to this memory 24system.physmem.num_reads 15513098 # Number of read requests responded to by this memory 25system.physmem.num_writes 857428 # Number of write requests responded to by this memory 26system.physmem.num_other 0 # Number of other requests responded to by this memory 27system.physmem.bw_read 51575696 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read 366560 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_write 3717742 # Write bandwidth from this memory (bytes/s) 30system.physmem.bw_total 55293438 # Total bandwidth to/from this memory (bytes/s) 31system.l2c.replacements 117809 # number of replacements 32system.l2c.tagsinuse 24928.376904 # Cycle average of tags in use 33system.l2c.total_refs 1535240 # Total number of references to valid blocks. 34system.l2c.sampled_refs 146709 # Sample count of references to valid blocks. 35system.l2c.avg_refs 10.464525 # Average number of references to valid blocks. 36system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 37system.l2c.occ_blocks::0 10331.534348 # Average occupied blocks per context 38system.l2c.occ_blocks::1 14596.842556 # Average occupied blocks per context 39system.l2c.occ_percent::0 0.157647 # Average percentage of cache occupancy 40system.l2c.occ_percent::1 0.222730 # Average percentage of cache occupancy 41system.l2c.ReadReq_hits::0 1198360 # number of ReadReq hits 42system.l2c.ReadReq_hits::1 12495 # number of ReadReq hits 43system.l2c.ReadReq_hits::total 1210855 # number of ReadReq hits 44system.l2c.Writeback_hits::0 610049 # number of Writeback hits 45system.l2c.Writeback_hits::total 610049 # number of Writeback hits 46system.l2c.UpgradeReq_hits::0 26 # number of UpgradeReq hits 47system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits 48system.l2c.ReadExReq_hits::0 106473 # number of ReadExReq hits 49system.l2c.ReadExReq_hits::total 106473 # number of ReadExReq hits 50system.l2c.demand_hits::0 1304833 # number of demand (read+write) hits 51system.l2c.demand_hits::1 12495 # number of demand (read+write) hits 52system.l2c.demand_hits::total 1317328 # number of demand (read+write) hits 53system.l2c.overall_hits::0 1304833 # number of overall hits 54system.l2c.overall_hits::1 12495 # number of overall hits 55system.l2c.overall_hits::total 1317328 # number of overall hits 56system.l2c.ReadReq_misses::0 31685 # number of ReadReq misses 57system.l2c.ReadReq_misses::1 37 # number of ReadReq misses 58system.l2c.ReadReq_misses::total 31722 # number of ReadReq misses 59system.l2c.UpgradeReq_misses::0 2875 # number of UpgradeReq misses 60system.l2c.UpgradeReq_misses::total 2875 # number of UpgradeReq misses 61system.l2c.ReadExReq_misses::0 140928 # number of ReadExReq misses 62system.l2c.ReadExReq_misses::total 140928 # number of ReadExReq misses 63system.l2c.demand_misses::0 172613 # number of demand (read+write) misses 64system.l2c.demand_misses::1 37 # number of demand (read+write) misses 65system.l2c.demand_misses::total 172650 # number of demand (read+write) misses 66system.l2c.overall_misses::0 172613 # number of overall misses 67system.l2c.overall_misses::1 37 # number of overall misses 68system.l2c.overall_misses::total 172650 # number of overall misses 69system.l2c.ReadReq_miss_latency 1654516000 # number of ReadReq miss cycles 70system.l2c.UpgradeReq_miss_latency 1040000 # number of UpgradeReq miss cycles 71system.l2c.ReadExReq_miss_latency 7338006500 # number of ReadExReq miss cycles 72system.l2c.demand_miss_latency 8992522500 # number of demand (read+write) miss cycles 73system.l2c.overall_miss_latency 8992522500 # number of overall miss cycles 74system.l2c.ReadReq_accesses::0 1230045 # number of ReadReq accesses(hits+misses) 75system.l2c.ReadReq_accesses::1 12532 # number of ReadReq accesses(hits+misses) 76system.l2c.ReadReq_accesses::total 1242577 # number of ReadReq accesses(hits+misses) 77system.l2c.Writeback_accesses::0 610049 # number of Writeback accesses(hits+misses) 78system.l2c.Writeback_accesses::total 610049 # number of Writeback accesses(hits+misses) 79system.l2c.UpgradeReq_accesses::0 2901 # number of UpgradeReq accesses(hits+misses) 80system.l2c.UpgradeReq_accesses::total 2901 # number of UpgradeReq accesses(hits+misses) 81system.l2c.ReadExReq_accesses::0 247401 # number of ReadExReq accesses(hits+misses) 82system.l2c.ReadExReq_accesses::total 247401 # number of ReadExReq accesses(hits+misses) 83system.l2c.demand_accesses::0 1477446 # number of demand (read+write) accesses 84system.l2c.demand_accesses::1 12532 # number of demand (read+write) accesses 85system.l2c.demand_accesses::total 1489978 # number of demand (read+write) accesses 86system.l2c.overall_accesses::0 1477446 # number of overall (read+write) accesses 87system.l2c.overall_accesses::1 12532 # number of overall (read+write) accesses 88system.l2c.overall_accesses::total 1489978 # number of overall (read+write) accesses 89system.l2c.ReadReq_miss_rate::0 0.025759 # miss rate for ReadReq accesses 90system.l2c.ReadReq_miss_rate::1 0.002952 # miss rate for ReadReq accesses 91system.l2c.ReadReq_miss_rate::total 0.028712 # miss rate for ReadReq accesses 92system.l2c.UpgradeReq_miss_rate::0 0.991038 # miss rate for UpgradeReq accesses 93system.l2c.ReadExReq_miss_rate::0 0.569634 # miss rate for ReadExReq accesses 94system.l2c.demand_miss_rate::0 0.116832 # miss rate for demand accesses 95system.l2c.demand_miss_rate::1 0.002952 # miss rate for demand accesses 96system.l2c.demand_miss_rate::total 0.119784 # miss rate for demand accesses 97system.l2c.overall_miss_rate::0 0.116832 # miss rate for overall accesses 98system.l2c.overall_miss_rate::1 0.002952 # miss rate for overall accesses 99system.l2c.overall_miss_rate::total 0.119784 # miss rate for overall accesses 100system.l2c.ReadReq_avg_miss_latency::0 52217.642418 # average ReadReq miss latency 101system.l2c.ReadReq_avg_miss_latency::1 44716648.648649 # average ReadReq miss latency 102system.l2c.ReadReq_avg_miss_latency::total 44768866.291066 # average ReadReq miss latency 103system.l2c.UpgradeReq_avg_miss_latency::0 361.739130 # average UpgradeReq miss latency 104system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency 105system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency 106system.l2c.ReadExReq_avg_miss_latency::0 52069.187812 # average ReadExReq miss latency 107system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency 108system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency 109system.l2c.demand_avg_miss_latency::0 52096.438275 # average overall miss latency 110system.l2c.demand_avg_miss_latency::1 243041148.648649 # average overall miss latency 111system.l2c.demand_avg_miss_latency::total 243093245.086924 # average overall miss latency 112system.l2c.overall_avg_miss_latency::0 52096.438275 # average overall miss latency 113system.l2c.overall_avg_miss_latency::1 243041148.648649 # average overall miss latency 114system.l2c.overall_avg_miss_latency::total 243093245.086924 # average overall miss latency 115system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 116system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 117system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 118system.l2c.blocked::no_targets 0 # number of cycles access was blocked 119system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 120system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 121system.l2c.fast_writes 0 # number of fast writes performed 122system.l2c.cache_copies 0 # number of cache copies performed 123system.l2c.writebacks 103410 # number of writebacks 124system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 125system.l2c.overall_mshr_hits 0 # number of overall MSHR hits 126system.l2c.ReadReq_mshr_misses 31722 # number of ReadReq MSHR misses 127system.l2c.UpgradeReq_mshr_misses 2875 # number of UpgradeReq MSHR misses 128system.l2c.ReadExReq_mshr_misses 140928 # number of ReadExReq MSHR misses 129system.l2c.demand_mshr_misses 172650 # number of demand (read+write) MSHR misses 130system.l2c.overall_mshr_misses 172650 # number of overall MSHR misses 131system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 132system.l2c.ReadReq_mshr_miss_latency 1273844000 # number of ReadReq MSHR miss cycles 133system.l2c.UpgradeReq_mshr_miss_latency 115156000 # number of UpgradeReq MSHR miss cycles 134system.l2c.ReadExReq_mshr_miss_latency 5646870000 # number of ReadExReq MSHR miss cycles 135system.l2c.demand_mshr_miss_latency 6920714000 # number of demand (read+write) MSHR miss cycles 136system.l2c.overall_mshr_miss_latency 6920714000 # number of overall MSHR miss cycles 137system.l2c.ReadReq_mshr_uncacheable_latency 131817513000 # number of ReadReq MSHR uncacheable cycles 138system.l2c.WriteReq_mshr_uncacheable_latency 31206766500 # number of WriteReq MSHR uncacheable cycles 139system.l2c.overall_mshr_uncacheable_latency 163024279500 # number of overall MSHR uncacheable cycles 140system.l2c.ReadReq_mshr_miss_rate::0 0.025789 # mshr miss rate for ReadReq accesses 141system.l2c.ReadReq_mshr_miss_rate::1 2.531280 # mshr miss rate for ReadReq accesses 142system.l2c.ReadReq_mshr_miss_rate::total 2.557069 # mshr miss rate for ReadReq accesses 143system.l2c.UpgradeReq_mshr_miss_rate::0 0.991038 # mshr miss rate for UpgradeReq accesses 144system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses 145system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses 146system.l2c.ReadExReq_mshr_miss_rate::0 0.569634 # mshr miss rate for ReadExReq accesses 147system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses 148system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses 149system.l2c.demand_mshr_miss_rate::0 0.116857 # mshr miss rate for demand accesses 150system.l2c.demand_mshr_miss_rate::1 13.776732 # mshr miss rate for demand accesses 151system.l2c.demand_mshr_miss_rate::total 13.893589 # mshr miss rate for demand accesses 152system.l2c.overall_mshr_miss_rate::0 0.116857 # mshr miss rate for overall accesses 153system.l2c.overall_mshr_miss_rate::1 13.776732 # mshr miss rate for overall accesses 154system.l2c.overall_mshr_miss_rate::total 13.893589 # mshr miss rate for overall accesses 155system.l2c.ReadReq_avg_mshr_miss_latency 40156.484459 # average ReadReq mshr miss latency 156system.l2c.UpgradeReq_avg_mshr_miss_latency 40054.260870 # average UpgradeReq mshr miss latency 157system.l2c.ReadExReq_avg_mshr_miss_latency 40069.184264 # average ReadExReq mshr miss latency 158system.l2c.demand_avg_mshr_miss_latency 40085.224443 # average overall mshr miss latency 159system.l2c.overall_avg_mshr_miss_latency 40085.224443 # average overall mshr miss latency 160system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency 161system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency 162system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency 163system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated 164system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 165system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 166system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 167system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 168system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 169system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 170system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 171system.cf0.dma_write_txs 0 # Number of DMA write transactions. 172system.cpu.dtb.inst_hits 0 # ITB inst hits 173system.cpu.dtb.inst_misses 0 # ITB inst misses 174system.cpu.dtb.read_hits 14970647 # DTB read hits 175system.cpu.dtb.read_misses 7343 # DTB read misses 176system.cpu.dtb.write_hits 11215605 # DTB write hits 177system.cpu.dtb.write_misses 2208 # DTB write misses 178system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed 179system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 180system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 181system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 182system.cpu.dtb.flush_entries 3488 # Number of entries that have been flushed from TLB 183system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 184system.cpu.dtb.prefetch_faults 183 # Number of TLB faults due to prefetch 185system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 186system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions 187system.cpu.dtb.read_accesses 14977990 # DTB read accesses 188system.cpu.dtb.write_accesses 11217813 # DTB write accesses 189system.cpu.dtb.inst_accesses 0 # ITB inst accesses 190system.cpu.dtb.hits 26186252 # DTB hits 191system.cpu.dtb.misses 9551 # DTB misses 192system.cpu.dtb.accesses 26195803 # DTB accesses 193system.cpu.itb.inst_hits 60357722 # ITB inst hits 194system.cpu.itb.inst_misses 4471 # ITB inst misses 195system.cpu.itb.read_hits 0 # DTB read hits 196system.cpu.itb.read_misses 0 # DTB read misses 197system.cpu.itb.write_hits 0 # DTB write hits 198system.cpu.itb.write_misses 0 # DTB write misses 199system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed 200system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 201system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 202system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 203system.cpu.itb.flush_entries 2343 # Number of entries that have been flushed from TLB 204system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 205system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 206system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 207system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 208system.cpu.itb.read_accesses 0 # DTB read accesses 209system.cpu.itb.write_accesses 0 # DTB write accesses 210system.cpu.itb.inst_accesses 60362193 # ITB inst accesses 211system.cpu.itb.hits 60357722 # DTB hits 212system.cpu.itb.misses 4471 # DTB misses 213system.cpu.itb.accesses 60362193 # DTB accesses 214system.cpu.numCycles 5182883384 # number of cpu cycles simulated 215system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 216system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 217system.cpu.num_insts 75477515 # Number of instructions executed 218system.cpu.num_int_alu_accesses 68255270 # Number of integer alu accesses 219system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses 220system.cpu.num_func_calls 1975579 # number of times a function call or return occured 221system.cpu.num_conditional_control_insts 7580611 # number of instructions that are conditional controls 222system.cpu.num_int_insts 68255270 # number of integer instructions 223system.cpu.num_fp_insts 10269 # number of float instructions 224system.cpu.num_int_register_reads 390835391 # number of times the integer registers were read 225system.cpu.num_int_register_writes 72984158 # number of times the integer registers were written 226system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read 227system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written 228system.cpu.num_mem_refs 27351734 # number of memory refs 229system.cpu.num_load_insts 15632521 # Number of load instructions 230system.cpu.num_store_insts 11719213 # Number of store instructions 231system.cpu.num_idle_cycles 4574345772.482235 # Number of idle cycles 232system.cpu.num_busy_cycles 608537611.517765 # Number of busy cycles 233system.cpu.not_idle_fraction 0.117413 # Percentage of non-idle cycles 234system.cpu.idle_fraction 0.882587 # Percentage of idle cycles 235system.cpu.kern.inst.arm 0 # number of arm instructions executed 236system.cpu.kern.inst.quiesce 82953 # number of quiesce instructions executed 237system.cpu.icache.replacements 852971 # number of replacements 238system.cpu.icache.tagsinuse 510.943281 # Cycle average of tags in use 239system.cpu.icache.total_refs 59504239 # Total number of references to valid blocks. 240system.cpu.icache.sampled_refs 853483 # Sample count of references to valid blocks. 241system.cpu.icache.avg_refs 69.719302 # Average number of references to valid blocks. 242system.cpu.icache.warmup_cycle 18512998000 # Cycle when the warmup percentage was hit. 243system.cpu.icache.occ_blocks::0 510.943281 # Average occupied blocks per context 244system.cpu.icache.occ_percent::0 0.997936 # Average percentage of cache occupancy 245system.cpu.icache.ReadReq_hits::0 59504239 # number of ReadReq hits 246system.cpu.icache.ReadReq_hits::total 59504239 # number of ReadReq hits 247system.cpu.icache.demand_hits::0 59504239 # number of demand (read+write) hits 248system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits 249system.cpu.icache.demand_hits::total 59504239 # number of demand (read+write) hits 250system.cpu.icache.overall_hits::0 59504239 # number of overall hits 251system.cpu.icache.overall_hits::1 0 # number of overall hits 252system.cpu.icache.overall_hits::total 59504239 # number of overall hits 253system.cpu.icache.ReadReq_misses::0 853483 # number of ReadReq misses 254system.cpu.icache.ReadReq_misses::total 853483 # number of ReadReq misses 255system.cpu.icache.demand_misses::0 853483 # number of demand (read+write) misses 256system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses 257system.cpu.icache.demand_misses::total 853483 # number of demand (read+write) misses 258system.cpu.icache.overall_misses::0 853483 # number of overall misses 259system.cpu.icache.overall_misses::1 0 # number of overall misses 260system.cpu.icache.overall_misses::total 853483 # number of overall misses 261system.cpu.icache.ReadReq_miss_latency 12547128000 # number of ReadReq miss cycles 262system.cpu.icache.demand_miss_latency 12547128000 # number of demand (read+write) miss cycles 263system.cpu.icache.overall_miss_latency 12547128000 # number of overall miss cycles 264system.cpu.icache.ReadReq_accesses::0 60357722 # number of ReadReq accesses(hits+misses) 265system.cpu.icache.ReadReq_accesses::total 60357722 # number of ReadReq accesses(hits+misses) 266system.cpu.icache.demand_accesses::0 60357722 # number of demand (read+write) accesses 267system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses 268system.cpu.icache.demand_accesses::total 60357722 # number of demand (read+write) accesses 269system.cpu.icache.overall_accesses::0 60357722 # number of overall (read+write) accesses 270system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses 271system.cpu.icache.overall_accesses::total 60357722 # number of overall (read+write) accesses 272system.cpu.icache.ReadReq_miss_rate::0 0.014140 # miss rate for ReadReq accesses 273system.cpu.icache.demand_miss_rate::0 0.014140 # miss rate for demand accesses 274system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses 275system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses 276system.cpu.icache.overall_miss_rate::0 0.014140 # miss rate for overall accesses 277system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses 278system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses 279system.cpu.icache.ReadReq_avg_miss_latency::0 14701.087192 # average ReadReq miss latency 280system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency 281system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency 282system.cpu.icache.demand_avg_miss_latency::0 14701.087192 # average overall miss latency 283system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency 284system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency 285system.cpu.icache.overall_avg_miss_latency::0 14701.087192 # average overall miss latency 286system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency 287system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency 288system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 289system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 290system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 291system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 292system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 293system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 294system.cpu.icache.fast_writes 0 # number of fast writes performed 295system.cpu.icache.cache_copies 0 # number of cache copies performed 296system.cpu.icache.writebacks 45661 # number of writebacks 297system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 298system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits 299system.cpu.icache.ReadReq_mshr_misses 853483 # number of ReadReq MSHR misses 300system.cpu.icache.demand_mshr_misses 853483 # number of demand (read+write) MSHR misses 301system.cpu.icache.overall_mshr_misses 853483 # number of overall MSHR misses 302system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 303system.cpu.icache.ReadReq_mshr_miss_latency 9984295500 # number of ReadReq MSHR miss cycles 304system.cpu.icache.demand_mshr_miss_latency 9984295500 # number of demand (read+write) MSHR miss cycles 305system.cpu.icache.overall_mshr_miss_latency 9984295500 # number of overall MSHR miss cycles 306system.cpu.icache.ReadReq_mshr_uncacheable_latency 350913000 # number of ReadReq MSHR uncacheable cycles 307system.cpu.icache.overall_mshr_uncacheable_latency 350913000 # number of overall MSHR uncacheable cycles 308system.cpu.icache.ReadReq_mshr_miss_rate::0 0.014140 # mshr miss rate for ReadReq accesses 309system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses 310system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses 311system.cpu.icache.demand_mshr_miss_rate::0 0.014140 # mshr miss rate for demand accesses 312system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses 313system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses 314system.cpu.icache.overall_mshr_miss_rate::0 0.014140 # mshr miss rate for overall accesses 315system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses 316system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses 317system.cpu.icache.ReadReq_avg_mshr_miss_latency 11698.294518 # average ReadReq mshr miss latency 318system.cpu.icache.demand_avg_mshr_miss_latency 11698.294518 # average overall mshr miss latency 319system.cpu.icache.overall_avg_mshr_miss_latency 11698.294518 # average overall mshr miss latency 320system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency 321system.cpu.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency 322system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated 323system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 324system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 325system.cpu.dcache.replacements 626903 # number of replacements 326system.cpu.dcache.tagsinuse 511.875592 # Cycle average of tags in use 327system.cpu.dcache.total_refs 23615096 # Total number of references to valid blocks. 328system.cpu.dcache.sampled_refs 627415 # Sample count of references to valid blocks. 329system.cpu.dcache.avg_refs 37.638718 # Average number of references to valid blocks. 330system.cpu.dcache.warmup_cycle 660309000 # Cycle when the warmup percentage was hit. 331system.cpu.dcache.occ_blocks::0 511.875592 # Average occupied blocks per context 332system.cpu.dcache.occ_percent::0 0.999757 # Average percentage of cache occupancy 333system.cpu.dcache.ReadReq_hits::0 13170367 # number of ReadReq hits 334system.cpu.dcache.ReadReq_hits::total 13170367 # number of ReadReq hits 335system.cpu.dcache.WriteReq_hits::0 9958094 # number of WriteReq hits 336system.cpu.dcache.WriteReq_hits::total 9958094 # number of WriteReq hits 337system.cpu.dcache.LoadLockedReq_hits::0 236142 # number of LoadLockedReq hits 338system.cpu.dcache.LoadLockedReq_hits::total 236142 # number of LoadLockedReq hits 339system.cpu.dcache.StoreCondReq_hits::0 247592 # number of StoreCondReq hits 340system.cpu.dcache.StoreCondReq_hits::total 247592 # number of StoreCondReq hits 341system.cpu.dcache.demand_hits::0 23128461 # number of demand (read+write) hits 342system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits 343system.cpu.dcache.demand_hits::total 23128461 # number of demand (read+write) hits 344system.cpu.dcache.overall_hits::0 23128461 # number of overall hits 345system.cpu.dcache.overall_hits::1 0 # number of overall hits 346system.cpu.dcache.overall_hits::total 23128461 # number of overall hits 347system.cpu.dcache.ReadReq_misses::0 368563 # number of ReadReq misses 348system.cpu.dcache.ReadReq_misses::total 368563 # number of ReadReq misses 349system.cpu.dcache.WriteReq_misses::0 250302 # number of WriteReq misses 350system.cpu.dcache.WriteReq_misses::total 250302 # number of WriteReq misses 351system.cpu.dcache.LoadLockedReq_misses::0 11451 # number of LoadLockedReq misses 352system.cpu.dcache.LoadLockedReq_misses::total 11451 # number of LoadLockedReq misses 353system.cpu.dcache.demand_misses::0 618865 # number of demand (read+write) misses 354system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses 355system.cpu.dcache.demand_misses::total 618865 # number of demand (read+write) misses 356system.cpu.dcache.overall_misses::0 618865 # number of overall misses 357system.cpu.dcache.overall_misses::1 0 # number of overall misses 358system.cpu.dcache.overall_misses::total 618865 # number of overall misses 359system.cpu.dcache.ReadReq_miss_latency 5846897000 # number of ReadReq miss cycles 360system.cpu.dcache.WriteReq_miss_latency 9551170500 # number of WriteReq miss cycles 361system.cpu.dcache.LoadLockedReq_miss_latency 186076500 # number of LoadLockedReq miss cycles 362system.cpu.dcache.demand_miss_latency 15398067500 # number of demand (read+write) miss cycles 363system.cpu.dcache.overall_miss_latency 15398067500 # number of overall miss cycles 364system.cpu.dcache.ReadReq_accesses::0 13538930 # number of ReadReq accesses(hits+misses) 365system.cpu.dcache.ReadReq_accesses::total 13538930 # number of ReadReq accesses(hits+misses) 366system.cpu.dcache.WriteReq_accesses::0 10208396 # number of WriteReq accesses(hits+misses) 367system.cpu.dcache.WriteReq_accesses::total 10208396 # number of WriteReq accesses(hits+misses) 368system.cpu.dcache.LoadLockedReq_accesses::0 247593 # number of LoadLockedReq accesses(hits+misses) 369system.cpu.dcache.LoadLockedReq_accesses::total 247593 # number of LoadLockedReq accesses(hits+misses) 370system.cpu.dcache.StoreCondReq_accesses::0 247592 # number of StoreCondReq accesses(hits+misses) 371system.cpu.dcache.StoreCondReq_accesses::total 247592 # number of StoreCondReq accesses(hits+misses) 372system.cpu.dcache.demand_accesses::0 23747326 # number of demand (read+write) accesses 373system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses 374system.cpu.dcache.demand_accesses::total 23747326 # number of demand (read+write) accesses 375system.cpu.dcache.overall_accesses::0 23747326 # number of overall (read+write) accesses 376system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses 377system.cpu.dcache.overall_accesses::total 23747326 # number of overall (read+write) accesses 378system.cpu.dcache.ReadReq_miss_rate::0 0.027222 # miss rate for ReadReq accesses 379system.cpu.dcache.WriteReq_miss_rate::0 0.024519 # miss rate for WriteReq accesses 380system.cpu.dcache.LoadLockedReq_miss_rate::0 0.046249 # miss rate for LoadLockedReq accesses 381system.cpu.dcache.demand_miss_rate::0 0.026060 # miss rate for demand accesses 382system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses 383system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses 384system.cpu.dcache.overall_miss_rate::0 0.026060 # miss rate for overall accesses 385system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses 386system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses 387system.cpu.dcache.ReadReq_avg_miss_latency::0 15864.036813 # average ReadReq miss latency 388system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency 389system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency 390system.cpu.dcache.WriteReq_avg_miss_latency::0 38158.586428 # average WriteReq miss latency 391system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency 392system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency 393system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 16249.803511 # average LoadLockedReq miss latency 394system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency 395system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency 396system.cpu.dcache.demand_avg_miss_latency::0 24881.141283 # average overall miss latency 397system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency 398system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency 399system.cpu.dcache.overall_avg_miss_latency::0 24881.141283 # average overall miss latency 400system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency 401system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency 402system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 403system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 404system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 405system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 406system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 407system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 408system.cpu.dcache.fast_writes 0 # number of fast writes performed 409system.cpu.dcache.cache_copies 0 # number of cache copies performed 410system.cpu.dcache.writebacks 564388 # number of writebacks 411system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 412system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits 413system.cpu.dcache.ReadReq_mshr_misses 368563 # number of ReadReq MSHR misses 414system.cpu.dcache.WriteReq_mshr_misses 250302 # number of WriteReq MSHR misses 415system.cpu.dcache.LoadLockedReq_mshr_misses 11451 # number of LoadLockedReq MSHR misses 416system.cpu.dcache.demand_mshr_misses 618865 # number of demand (read+write) MSHR misses 417system.cpu.dcache.overall_mshr_misses 618865 # number of overall MSHR misses 418system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 419system.cpu.dcache.ReadReq_mshr_miss_latency 4741074500 # number of ReadReq MSHR miss cycles 420system.cpu.dcache.WriteReq_mshr_miss_latency 8800219500 # number of WriteReq MSHR miss cycles 421system.cpu.dcache.LoadLockedReq_mshr_miss_latency 151723500 # number of LoadLockedReq MSHR miss cycles 422system.cpu.dcache.demand_mshr_miss_latency 13541294000 # number of demand (read+write) MSHR miss cycles 423system.cpu.dcache.overall_mshr_miss_latency 13541294000 # number of overall MSHR miss cycles 424system.cpu.dcache.ReadReq_mshr_uncacheable_latency 146946835000 # number of ReadReq MSHR uncacheable cycles 425system.cpu.dcache.WriteReq_mshr_uncacheable_latency 40367455500 # number of WriteReq MSHR uncacheable cycles 426system.cpu.dcache.overall_mshr_uncacheable_latency 187314290500 # number of overall MSHR uncacheable cycles 427system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.027222 # mshr miss rate for ReadReq accesses 428system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses 429system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses 430system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.024519 # mshr miss rate for WriteReq accesses 431system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses 432system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses 433system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.046249 # mshr miss rate for LoadLockedReq accesses 434system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses 435system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses 436system.cpu.dcache.demand_mshr_miss_rate::0 0.026060 # mshr miss rate for demand accesses 437system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses 438system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses 439system.cpu.dcache.overall_mshr_miss_rate::0 0.026060 # mshr miss rate for overall accesses 440system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses 441system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses 442system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12863.674596 # average ReadReq mshr miss latency 443system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35158.406645 # average WriteReq mshr miss latency 444system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 13249.803511 # average LoadLockedReq mshr miss latency 445system.cpu.dcache.demand_avg_mshr_miss_latency 21880.852852 # average overall mshr miss latency 446system.cpu.dcache.overall_avg_mshr_miss_latency 21880.852852 # average overall mshr miss latency 447system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency 448system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency 449system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency 450system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 451system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 452system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 453system.iocache.replacements 0 # number of replacements 454system.iocache.tagsinuse 0 # Cycle average of tags in use 455system.iocache.total_refs 0 # Total number of references to valid blocks. 456system.iocache.sampled_refs 0 # Sample count of references to valid blocks. 457system.iocache.avg_refs no_value # Average number of references to valid blocks. 458system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 459system.iocache.demand_hits::0 0 # number of demand (read+write) hits 460system.iocache.demand_hits::1 0 # number of demand (read+write) hits 461system.iocache.demand_hits::total 0 # number of demand (read+write) hits 462system.iocache.overall_hits::0 0 # number of overall hits 463system.iocache.overall_hits::1 0 # number of overall hits 464system.iocache.overall_hits::total 0 # number of overall hits 465system.iocache.demand_misses::0 0 # number of demand (read+write) misses 466system.iocache.demand_misses::1 0 # number of demand (read+write) misses 467system.iocache.demand_misses::total 0 # number of demand (read+write) misses 468system.iocache.overall_misses::0 0 # number of overall misses 469system.iocache.overall_misses::1 0 # number of overall misses 470system.iocache.overall_misses::total 0 # number of overall misses 471system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles 472system.iocache.overall_miss_latency 0 # number of overall miss cycles 473system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses 474system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses 475system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses 476system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses 477system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses 478system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses 479system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses 480system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses 481system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses 482system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses 483system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses 484system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses 485system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency 486system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency 487system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency 488system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency 489system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency 490system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency 491system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 492system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 493system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 494system.iocache.blocked::no_targets 0 # number of cycles access was blocked 495system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 496system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 497system.iocache.fast_writes 0 # number of fast writes performed 498system.iocache.cache_copies 0 # number of cache copies performed 499system.iocache.writebacks 0 # number of writebacks 500system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 501system.iocache.overall_mshr_hits 0 # number of overall MSHR hits 502system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 503system.iocache.overall_mshr_misses 0 # number of overall MSHR misses 504system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 505system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 506system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 507system.iocache.ReadReq_mshr_uncacheable_latency 1341941439938 # number of ReadReq MSHR uncacheable cycles 508system.iocache.overall_mshr_uncacheable_latency 1341941439938 # number of overall MSHR uncacheable cycles 509system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses 510system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses 511system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses 512system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses 513system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses 514system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses 515system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 516system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 517system.iocache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency 518system.iocache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency 519system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated 520system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 521system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 522 523---------- End Simulation Statistics ---------- 524