stats.txt revision 11547:dd6dfd38b6c2
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.909587 # Number of seconds simulated 4sim_ticks 2909586837500 # Number of ticks simulated 5final_tick 2909586837500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 567099 # Simulator instruction rate (inst/s) 8host_op_rate 683745 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 14672489619 # Simulator tick rate (ticks/s) 10host_mem_usage 579808 # Number of bytes of host memory used 11host_seconds 198.30 # Real time elapsed on the host 12sim_insts 112457035 # Number of instructions simulated 13sim_ops 135588119 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 1186532 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 8901860 # Number of bytes read from this memory 21system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 22system.physmem.bytes_read::total 10089928 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu.inst 1186532 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::total 1186532 # Number of instructions bytes read from this memory 25system.physmem.bytes_written::writebacks 7512000 # Number of bytes written to this memory 26system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory 27system.physmem.bytes_written::total 7529524 # Number of bytes written to this memory 28system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.inst 26993 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.data 139611 # Number of read requests responded to by this memory 32system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 33system.physmem.num_reads::total 166628 # Number of read requests responded to by this memory 34system.physmem.num_writes::writebacks 117375 # Number of write requests responded to by this memory 35system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory 36system.physmem.num_writes::total 121756 # Number of write requests responded to by this memory 37system.physmem.bw_read::cpu.dtb.walker 154 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.itb.walker 44 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.inst 407801 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.data 3059493 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::realview.ide 330 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::total 3467822 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::cpu.inst 407801 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_inst_read::total 407801 # Instruction read bandwidth from this memory (bytes/s) 45system.physmem.bw_write::writebacks 2581810 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::cpu.data 6023 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_write::total 2587833 # Write bandwidth from this memory (bytes/s) 48system.physmem.bw_total::writebacks 2581810 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.itb.walker 44 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.inst 407801 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.data 3065516 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::realview.ide 330 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::total 6055654 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.readReqs 166628 # Number of read requests accepted 56system.physmem.writeReqs 121756 # Number of write requests accepted 57system.physmem.readBursts 166628 # Number of DRAM read bursts, including those serviced by the write queue 58system.physmem.writeBursts 121756 # Number of DRAM write bursts, including those merged in the write queue 59system.physmem.bytesReadDRAM 10657408 # Total number of bytes read from DRAM 60system.physmem.bytesReadWrQ 6784 # Total number of bytes read from write queue 61system.physmem.bytesWritten 7542016 # Total number of bytes written to DRAM 62system.physmem.bytesReadSys 10089928 # Total read bytes from the system interface side 63system.physmem.bytesWrittenSys 7529524 # Total written bytes from the system interface side 64system.physmem.servicedByWrQ 106 # Number of DRAM read bursts serviced by the write queue 65system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one 66system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 67system.physmem.perBankRdBursts::0 10077 # Per bank write bursts 68system.physmem.perBankRdBursts::1 9979 # Per bank write bursts 69system.physmem.perBankRdBursts::2 10695 # Per bank write bursts 70system.physmem.perBankRdBursts::3 10660 # Per bank write bursts 71system.physmem.perBankRdBursts::4 18797 # Per bank write bursts 72system.physmem.perBankRdBursts::5 9664 # Per bank write bursts 73system.physmem.perBankRdBursts::6 9666 # Per bank write bursts 74system.physmem.perBankRdBursts::7 10487 # Per bank write bursts 75system.physmem.perBankRdBursts::8 9276 # Per bank write bursts 76system.physmem.perBankRdBursts::9 9973 # Per bank write bursts 77system.physmem.perBankRdBursts::10 9232 # Per bank write bursts 78system.physmem.perBankRdBursts::11 8679 # Per bank write bursts 79system.physmem.perBankRdBursts::12 9822 # Per bank write bursts 80system.physmem.perBankRdBursts::13 10379 # Per bank write bursts 81system.physmem.perBankRdBursts::14 9723 # Per bank write bursts 82system.physmem.perBankRdBursts::15 9413 # Per bank write bursts 83system.physmem.perBankWrBursts::0 7393 # Per bank write bursts 84system.physmem.perBankWrBursts::1 7263 # Per bank write bursts 85system.physmem.perBankWrBursts::2 8282 # Per bank write bursts 86system.physmem.perBankWrBursts::3 8171 # Per bank write bursts 87system.physmem.perBankWrBursts::4 7489 # Per bank write bursts 88system.physmem.perBankWrBursts::5 7265 # Per bank write bursts 89system.physmem.perBankWrBursts::6 7108 # Per bank write bursts 90system.physmem.perBankWrBursts::7 7661 # Per bank write bursts 91system.physmem.perBankWrBursts::8 7080 # Per bank write bursts 92system.physmem.perBankWrBursts::9 7523 # Per bank write bursts 93system.physmem.perBankWrBursts::10 6695 # Per bank write bursts 94system.physmem.perBankWrBursts::11 6470 # Per bank write bursts 95system.physmem.perBankWrBursts::12 7533 # Per bank write bursts 96system.physmem.perBankWrBursts::13 7859 # Per bank write bursts 97system.physmem.perBankWrBursts::14 7264 # Per bank write bursts 98system.physmem.perBankWrBursts::15 6788 # Per bank write bursts 99system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 100system.physmem.numWrRetry 10 # Number of times write queue was full causing retry 101system.physmem.totGap 2909586480500 # Total gap between requests 102system.physmem.readPktSize::0 0 # Read request sizes (log2) 103system.physmem.readPktSize::1 0 # Read request sizes (log2) 104system.physmem.readPktSize::2 9558 # Read request sizes (log2) 105system.physmem.readPktSize::3 14 # Read request sizes (log2) 106system.physmem.readPktSize::4 0 # Read request sizes (log2) 107system.physmem.readPktSize::5 0 # Read request sizes (log2) 108system.physmem.readPktSize::6 157056 # Read request sizes (log2) 109system.physmem.writePktSize::0 0 # Write request sizes (log2) 110system.physmem.writePktSize::1 0 # Write request sizes (log2) 111system.physmem.writePktSize::2 4381 # Write request sizes (log2) 112system.physmem.writePktSize::3 0 # Write request sizes (log2) 113system.physmem.writePktSize::4 0 # Write request sizes (log2) 114system.physmem.writePktSize::5 0 # Write request sizes (log2) 115system.physmem.writePktSize::6 117375 # Write request sizes (log2) 116system.physmem.rdQLenPdf::0 165639 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::1 614 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::2 257 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 148system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::15 1976 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::16 3160 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::17 6995 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::18 5904 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::19 6826 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::20 6035 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::21 5867 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::22 6120 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::23 6713 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::24 6456 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::25 6988 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::26 7862 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::27 6789 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::28 7153 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::29 8357 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::30 6865 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::31 6620 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::32 6747 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::33 1220 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::34 295 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::35 224 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::36 184 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::37 197 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::38 145 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::39 143 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::40 117 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::41 172 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::42 112 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::43 94 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::44 102 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::45 117 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::46 116 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::47 91 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::48 76 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::49 89 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::50 105 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::51 69 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::52 73 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::53 84 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::54 41 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::55 66 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::56 117 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::57 80 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::58 63 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::59 47 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::60 60 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::61 56 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::62 29 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::63 36 # What write queue length does an incoming req see 212system.physmem.bytesPerActivate::samples 58742 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::mean 309.818528 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::gmean 182.858167 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::stdev 329.750191 # Bytes accessed per row activation 216system.physmem.bytesPerActivate::0-127 21399 36.43% 36.43% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::128-255 14737 25.09% 61.52% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::256-383 6061 10.32% 71.83% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::384-511 3228 5.50% 77.33% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::512-639 2535 4.32% 81.65% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::640-767 1458 2.48% 84.13% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::768-895 1057 1.80% 85.93% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::896-1023 1079 1.84% 87.76% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::1024-1151 7188 12.24% 100.00% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::total 58742 # Bytes accessed per row activation 226system.physmem.rdPerTurnAround::samples 5615 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::mean 29.654497 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::stdev 597.763680 # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::0-2047 5614 99.98% 99.98% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::total 5615 # Reads before turning the bus around for writes 232system.physmem.wrPerTurnAround::samples 5615 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::mean 20.987355 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::gmean 18.791633 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::stdev 15.100649 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::16-19 4949 88.14% 88.14% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::20-23 78 1.39% 89.53% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::24-27 32 0.57% 90.10% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::28-31 46 0.82% 90.92% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::32-35 24 0.43% 91.34% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::36-39 20 0.36% 91.70% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::40-43 46 0.82% 92.52% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::44-47 4 0.07% 92.59% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::48-51 153 2.72% 95.32% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::52-55 11 0.20% 95.51% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::56-59 7 0.12% 95.64% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::60-63 13 0.23% 95.87% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::64-67 63 1.12% 96.99% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::68-71 5 0.09% 97.08% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::72-75 5 0.09% 97.17% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::76-79 26 0.46% 97.63% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::80-83 103 1.83% 99.47% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::84-87 1 0.02% 99.48% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::88-91 2 0.04% 99.52% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::92-95 1 0.02% 99.54% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::112-115 2 0.04% 99.57% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::128-131 8 0.14% 99.72% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::132-135 1 0.02% 99.73% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::140-143 1 0.02% 99.75% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::144-147 7 0.12% 99.88% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::148-151 1 0.02% 99.89% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::160-163 4 0.07% 99.96% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::176-179 2 0.04% 100.00% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::total 5615 # Writes before turning the bus around for reads 265system.physmem.totQLat 1624800000 # Total ticks spent queuing 266system.physmem.totMemAccLat 4747087500 # Total ticks spent from burst creation until serviced by the DRAM 267system.physmem.totBusLat 832610000 # Total ticks spent in databus transfers 268system.physmem.avgQLat 9757.27 # Average queueing delay per DRAM burst 269system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 270system.physmem.avgMemAccLat 28507.27 # Average memory access latency per DRAM burst 271system.physmem.avgRdBW 3.66 # Average DRAM read bandwidth in MiByte/s 272system.physmem.avgWrBW 2.59 # Average achieved write bandwidth in MiByte/s 273system.physmem.avgRdBWSys 3.47 # Average system read bandwidth in MiByte/s 274system.physmem.avgWrBWSys 2.59 # Average system write bandwidth in MiByte/s 275system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 276system.physmem.busUtil 0.05 # Data bus utilization in percentage 277system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 278system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 279system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 280system.physmem.avgWrQLen 25.45 # Average write queue length when enqueuing 281system.physmem.readRowHits 136095 # Number of row buffer hits during reads 282system.physmem.writeRowHits 89528 # Number of row buffer hits during writes 283system.physmem.readRowHitRate 81.73 # Row buffer hit rate for reads 284system.physmem.writeRowHitRate 75.96 # Row buffer hit rate for writes 285system.physmem.avgGap 10089278.46 # Average gap between requests 286system.physmem.pageHitRate 79.34 # Row buffer hit rate, read and write combined 287system.physmem_0.actEnergy 230829480 # Energy for activate commands per rank (pJ) 288system.physmem_0.preEnergy 125948625 # Energy for precharge commands per rank (pJ) 289system.physmem_0.readEnergy 702195000 # Energy for read commands per rank (pJ) 290system.physmem_0.writeEnergy 392895360 # Energy for write commands per rank (pJ) 291system.physmem_0.refreshEnergy 190039717920 # Energy for refresh commands per rank (pJ) 292system.physmem_0.actBackEnergy 90325761075 # Energy for active background per rank (pJ) 293system.physmem_0.preBackEnergy 1666515907500 # Energy for precharge background per rank (pJ) 294system.physmem_0.totalEnergy 1948333254960 # Total energy per rank (pJ) 295system.physmem_0.averagePower 669.626580 # Core power per rank (mW) 296system.physmem_0.memoryStateTime::IDLE 2772215900000 # Time in different power states 297system.physmem_0.memoryStateTime::REF 97157320000 # Time in different power states 298system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 299system.physmem_0.memoryStateTime::ACT 40208512500 # Time in different power states 300system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 301system.physmem_1.actEnergy 213260040 # Energy for activate commands per rank (pJ) 302system.physmem_1.preEnergy 116362125 # Energy for precharge commands per rank (pJ) 303system.physmem_1.readEnergy 596668800 # Energy for read commands per rank (pJ) 304system.physmem_1.writeEnergy 370733760 # Energy for write commands per rank (pJ) 305system.physmem_1.refreshEnergy 190039717920 # Energy for refresh commands per rank (pJ) 306system.physmem_1.actBackEnergy 88049300490 # Energy for active background per rank (pJ) 307system.physmem_1.preBackEnergy 1668512802750 # Energy for precharge background per rank (pJ) 308system.physmem_1.totalEnergy 1947898845885 # Total energy per rank (pJ) 309system.physmem_1.averagePower 669.477277 # Core power per rank (mW) 310system.physmem_1.memoryStateTime::IDLE 2775567506000 # Time in different power states 311system.physmem_1.memoryStateTime::REF 97157320000 # Time in different power states 312system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 313system.physmem_1.memoryStateTime::ACT 36861863500 # Time in different power states 314system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 315system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 316system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory 317system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory 318system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory 319system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory 320system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory 321system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory 322system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s) 323system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s) 324system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s) 325system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) 326system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) 327system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) 328system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 329system.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 330system.bridge.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 331system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 332system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 333system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 334system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 335system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 336system.cf0.dma_write_txs 631 # Number of DMA write transactions. 337system.cpu_clk_domain.clock 500 # Clock period in ticks 338system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 339system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 340system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 341system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 342system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 343system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 344system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 345system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 346system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 347system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 348system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 349system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 350system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 351system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 352system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 353system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 354system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 355system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 356system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 357system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 358system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 359system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 360system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 361system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 362system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 363system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 364system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 365system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 366system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 367system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 368system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 369system.cpu.dtb.walker.walks 9546 # Table walker walks requested 370system.cpu.dtb.walker.walksShort 9546 # Table walker walks initiated with short descriptors 371system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1255 # Level at which table walker walks with short descriptors terminate 372system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8291 # Level at which table walker walks with short descriptors terminate 373system.cpu.dtb.walker.walkWaitTime::samples 9546 # Table walker wait (enqueue to first request) latency 374system.cpu.dtb.walker.walkWaitTime::0 9546 100.00% 100.00% # Table walker wait (enqueue to first request) latency 375system.cpu.dtb.walker.walkWaitTime::total 9546 # Table walker wait (enqueue to first request) latency 376system.cpu.dtb.walker.walkCompletionTime::samples 7382 # Table walker service (enqueue to completion) latency 377system.cpu.dtb.walker.walkCompletionTime::mean 13159.035492 # Table walker service (enqueue to completion) latency 378system.cpu.dtb.walker.walkCompletionTime::gmean 10920.963738 # Table walker service (enqueue to completion) latency 379system.cpu.dtb.walker.walkCompletionTime::stdev 8541.710442 # Table walker service (enqueue to completion) latency 380system.cpu.dtb.walker.walkCompletionTime::0-32767 7377 99.93% 99.93% # Table walker service (enqueue to completion) latency 381system.cpu.dtb.walker.walkCompletionTime::131072-163839 4 0.05% 99.99% # Table walker service (enqueue to completion) latency 382system.cpu.dtb.walker.walkCompletionTime::294912-327679 1 0.01% 100.00% # Table walker service (enqueue to completion) latency 383system.cpu.dtb.walker.walkCompletionTime::total 7382 # Table walker service (enqueue to completion) latency 384system.cpu.dtb.walker.walksPending::samples 1638910500 # Table walker pending requests distribution 385system.cpu.dtb.walker.walksPending::0 1638910500 100.00% 100.00% # Table walker pending requests distribution 386system.cpu.dtb.walker.walksPending::total 1638910500 # Table walker pending requests distribution 387system.cpu.dtb.walker.walkPageSizes::4K 6174 83.64% 83.64% # Table walker page sizes translated 388system.cpu.dtb.walker.walkPageSizes::1M 1208 16.36% 100.00% # Table walker page sizes translated 389system.cpu.dtb.walker.walkPageSizes::total 7382 # Table walker page sizes translated 390system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9546 # Table walker requests started/completed, data/inst 391system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 392system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9546 # Table walker requests started/completed, data/inst 393system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7382 # Table walker requests started/completed, data/inst 394system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 395system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7382 # Table walker requests started/completed, data/inst 396system.cpu.dtb.walker.walkRequestOrigin::total 16928 # Table walker requests started/completed, data/inst 397system.cpu.dtb.inst_hits 0 # ITB inst hits 398system.cpu.dtb.inst_misses 0 # ITB inst misses 399system.cpu.dtb.read_hits 24520656 # DTB read hits 400system.cpu.dtb.read_misses 8124 # DTB read misses 401system.cpu.dtb.write_hits 19606817 # DTB write hits 402system.cpu.dtb.write_misses 1422 # DTB write misses 403system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 404system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 405system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 406system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 407system.cpu.dtb.flush_entries 4208 # Number of entries that have been flushed from TLB 408system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 409system.cpu.dtb.prefetch_faults 1650 # Number of TLB faults due to prefetch 410system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 411system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions 412system.cpu.dtb.read_accesses 24528780 # DTB read accesses 413system.cpu.dtb.write_accesses 19608239 # DTB write accesses 414system.cpu.dtb.inst_accesses 0 # ITB inst accesses 415system.cpu.dtb.hits 44127473 # DTB hits 416system.cpu.dtb.misses 9546 # DTB misses 417system.cpu.dtb.accesses 44137019 # DTB accesses 418system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 419system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 420system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 421system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 422system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 423system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 424system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 425system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 426system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 427system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 428system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 429system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 430system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 431system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 432system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 433system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 434system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 435system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 436system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 437system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 438system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 439system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 440system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 441system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 442system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 443system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 444system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 445system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 446system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 447system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 448system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 449system.cpu.itb.walker.walks 4763 # Table walker walks requested 450system.cpu.itb.walker.walksShort 4763 # Table walker walks initiated with short descriptors 451system.cpu.itb.walker.walksShortTerminationLevel::Level1 310 # Level at which table walker walks with short descriptors terminate 452system.cpu.itb.walker.walksShortTerminationLevel::Level2 4453 # Level at which table walker walks with short descriptors terminate 453system.cpu.itb.walker.walkWaitTime::samples 4763 # Table walker wait (enqueue to first request) latency 454system.cpu.itb.walker.walkWaitTime::0 4763 100.00% 100.00% # Table walker wait (enqueue to first request) latency 455system.cpu.itb.walker.walkWaitTime::total 4763 # Table walker wait (enqueue to first request) latency 456system.cpu.itb.walker.walkCompletionTime::samples 3108 # Table walker service (enqueue to completion) latency 457system.cpu.itb.walker.walkCompletionTime::mean 12722.007722 # Table walker service (enqueue to completion) latency 458system.cpu.itb.walker.walkCompletionTime::gmean 10527.196882 # Table walker service (enqueue to completion) latency 459system.cpu.itb.walker.walkCompletionTime::stdev 7865.701982 # Table walker service (enqueue to completion) latency 460system.cpu.itb.walker.walkCompletionTime::0-16383 2410 77.54% 77.54% # Table walker service (enqueue to completion) latency 461system.cpu.itb.walker.walkCompletionTime::16384-32767 696 22.39% 99.94% # Table walker service (enqueue to completion) latency 462system.cpu.itb.walker.walkCompletionTime::131072-147455 2 0.06% 100.00% # Table walker service (enqueue to completion) latency 463system.cpu.itb.walker.walkCompletionTime::total 3108 # Table walker service (enqueue to completion) latency 464system.cpu.itb.walker.walksPending::samples 1638383000 # Table walker pending requests distribution 465system.cpu.itb.walker.walksPending::0 1638383000 100.00% 100.00% # Table walker pending requests distribution 466system.cpu.itb.walker.walksPending::total 1638383000 # Table walker pending requests distribution 467system.cpu.itb.walker.walkPageSizes::4K 2798 90.03% 90.03% # Table walker page sizes translated 468system.cpu.itb.walker.walkPageSizes::1M 310 9.97% 100.00% # Table walker page sizes translated 469system.cpu.itb.walker.walkPageSizes::total 3108 # Table walker page sizes translated 470system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 471system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 4763 # Table walker requests started/completed, data/inst 472system.cpu.itb.walker.walkRequestOrigin_Requested::total 4763 # Table walker requests started/completed, data/inst 473system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 474system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3108 # Table walker requests started/completed, data/inst 475system.cpu.itb.walker.walkRequestOrigin_Completed::total 3108 # Table walker requests started/completed, data/inst 476system.cpu.itb.walker.walkRequestOrigin::total 7871 # Table walker requests started/completed, data/inst 477system.cpu.itb.inst_hits 115554258 # ITB inst hits 478system.cpu.itb.inst_misses 4763 # ITB inst misses 479system.cpu.itb.read_hits 0 # DTB read hits 480system.cpu.itb.read_misses 0 # DTB read misses 481system.cpu.itb.write_hits 0 # DTB write hits 482system.cpu.itb.write_misses 0 # DTB write misses 483system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 484system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 485system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 486system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 487system.cpu.itb.flush_entries 2849 # Number of entries that have been flushed from TLB 488system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 489system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 490system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 491system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 492system.cpu.itb.read_accesses 0 # DTB read accesses 493system.cpu.itb.write_accesses 0 # DTB write accesses 494system.cpu.itb.inst_accesses 115559021 # ITB inst accesses 495system.cpu.itb.hits 115554258 # DTB hits 496system.cpu.itb.misses 4763 # DTB misses 497system.cpu.itb.accesses 115559021 # DTB accesses 498system.cpu.numPwrStateTransitions 6066 # Number of power state transitions 499system.cpu.pwrStateClkGateDist::samples 3033 # Distribution of time spent in the clock gated state 500system.cpu.pwrStateClkGateDist::mean 886754793.248599 # Distribution of time spent in the clock gated state 501system.cpu.pwrStateClkGateDist::stdev 17463725759.115368 # Distribution of time spent in the clock gated state 502system.cpu.pwrStateClkGateDist::underflows 2967 97.82% 97.82% # Distribution of time spent in the clock gated state 503system.cpu.pwrStateClkGateDist::1000-5e+10 60 1.98% 99.80% # Distribution of time spent in the clock gated state 504system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state 505system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87% # Distribution of time spent in the clock gated state 506system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90% # Distribution of time spent in the clock gated state 507system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state 508system.cpu.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state 509system.cpu.pwrStateClkGateDist::max_value 499963874372 # Distribution of time spent in the clock gated state 510system.cpu.pwrStateClkGateDist::total 3033 # Distribution of time spent in the clock gated state 511system.cpu.pwrStateResidencyTicks::ON 220059549577 # Cumulative time (in ticks) in various power states 512system.cpu.pwrStateResidencyTicks::CLK_GATED 2689527287923 # Cumulative time (in ticks) in various power states 513system.cpu.numCycles 5819173675 # number of cpu cycles simulated 514system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 515system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 516system.cpu.kern.inst.arm 0 # number of arm instructions executed 517system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed 518system.cpu.committedInsts 112457035 # Number of instructions committed 519system.cpu.committedOps 135588119 # Number of ops (including micro ops) committed 520system.cpu.num_int_alu_accesses 119893391 # Number of integer alu accesses 521system.cpu.num_fp_alu_accesses 11161 # Number of float alu accesses 522system.cpu.num_func_calls 9892146 # number of times a function call or return occured 523system.cpu.num_conditional_control_insts 15230571 # number of instructions that are conditional controls 524system.cpu.num_int_insts 119893391 # number of integer instructions 525system.cpu.num_fp_insts 11161 # number of float instructions 526system.cpu.num_int_register_reads 218036740 # number of times the integer registers were read 527system.cpu.num_int_register_writes 82646452 # number of times the integer registers were written 528system.cpu.num_fp_register_reads 8449 # number of times the floating registers were read 529system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written 530system.cpu.num_cc_register_reads 489743459 # number of times the CC registers were read 531system.cpu.num_cc_register_writes 51893999 # number of times the CC registers were written 532system.cpu.num_mem_refs 45407924 # number of memory refs 533system.cpu.num_load_insts 24843119 # Number of load instructions 534system.cpu.num_store_insts 20564805 # Number of store instructions 535system.cpu.num_idle_cycles 5379054575.844151 # Number of idle cycles 536system.cpu.num_busy_cycles 440119099.155849 # Number of busy cycles 537system.cpu.not_idle_fraction 0.075633 # Percentage of non-idle cycles 538system.cpu.idle_fraction 0.924367 # Percentage of idle cycles 539system.cpu.Branches 25916787 # Number of branches fetched 540system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction 541system.cpu.op_class::IntAlu 93175095 67.17% 67.18% # Class of executed instruction 542system.cpu.op_class::IntMult 114406 0.08% 67.26% # Class of executed instruction 543system.cpu.op_class::IntDiv 0 0.00% 67.26% # Class of executed instruction 544system.cpu.op_class::FloatAdd 0 0.00% 67.26% # Class of executed instruction 545system.cpu.op_class::FloatCmp 0 0.00% 67.26% # Class of executed instruction 546system.cpu.op_class::FloatCvt 0 0.00% 67.26% # Class of executed instruction 547system.cpu.op_class::FloatMult 0 0.00% 67.26% # Class of executed instruction 548system.cpu.op_class::FloatDiv 0 0.00% 67.26% # Class of executed instruction 549system.cpu.op_class::FloatSqrt 0 0.00% 67.26% # Class of executed instruction 550system.cpu.op_class::SimdAdd 0 0.00% 67.26% # Class of executed instruction 551system.cpu.op_class::SimdAddAcc 0 0.00% 67.26% # Class of executed instruction 552system.cpu.op_class::SimdAlu 0 0.00% 67.26% # Class of executed instruction 553system.cpu.op_class::SimdCmp 0 0.00% 67.26% # Class of executed instruction 554system.cpu.op_class::SimdCvt 0 0.00% 67.26% # Class of executed instruction 555system.cpu.op_class::SimdMisc 0 0.00% 67.26% # Class of executed instruction 556system.cpu.op_class::SimdMult 0 0.00% 67.26% # Class of executed instruction 557system.cpu.op_class::SimdMultAcc 0 0.00% 67.26% # Class of executed instruction 558system.cpu.op_class::SimdShift 0 0.00% 67.26% # Class of executed instruction 559system.cpu.op_class::SimdShiftAcc 0 0.00% 67.26% # Class of executed instruction 560system.cpu.op_class::SimdSqrt 0 0.00% 67.26% # Class of executed instruction 561system.cpu.op_class::SimdFloatAdd 0 0.00% 67.26% # Class of executed instruction 562system.cpu.op_class::SimdFloatAlu 0 0.00% 67.26% # Class of executed instruction 563system.cpu.op_class::SimdFloatCmp 0 0.00% 67.26% # Class of executed instruction 564system.cpu.op_class::SimdFloatCvt 0 0.00% 67.26% # Class of executed instruction 565system.cpu.op_class::SimdFloatDiv 0 0.00% 67.26% # Class of executed instruction 566system.cpu.op_class::SimdFloatMisc 8453 0.01% 67.26% # Class of executed instruction 567system.cpu.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction 568system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction 569system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction 570system.cpu.op_class::MemRead 24843119 17.91% 85.17% # Class of executed instruction 571system.cpu.op_class::MemWrite 20564805 14.83% 100.00% # Class of executed instruction 572system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 573system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 574system.cpu.op_class::total 138708215 # Class of executed instruction 575system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 576system.cpu.dcache.tags.replacements 819223 # number of replacements 577system.cpu.dcache.tags.tagsinuse 511.702328 # Cycle average of tags in use 578system.cpu.dcache.tags.total_refs 43236237 # Total number of references to valid blocks. 579system.cpu.dcache.tags.sampled_refs 819735 # Sample count of references to valid blocks. 580system.cpu.dcache.tags.avg_refs 52.744164 # Average number of references to valid blocks. 581system.cpu.dcache.tags.warmup_cycle 1736147500 # Cycle when the warmup percentage was hit. 582system.cpu.dcache.tags.occ_blocks::cpu.data 511.702328 # Average occupied blocks per requestor 583system.cpu.dcache.tags.occ_percent::cpu.data 0.999419 # Average percentage of cache occupancy 584system.cpu.dcache.tags.occ_percent::total 0.999419 # Average percentage of cache occupancy 585system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 586system.cpu.dcache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id 587system.cpu.dcache.tags.age_task_id_blocks_1024::1 344 # Occupied blocks per task id 588system.cpu.dcache.tags.age_task_id_blocks_1024::2 107 # Occupied blocks per task id 589system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 590system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 591system.cpu.dcache.tags.tag_accesses 177112679 # Number of tag accesses 592system.cpu.dcache.tags.data_accesses 177112679 # Number of data accesses 593system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 594system.cpu.dcache.ReadReq_hits::cpu.data 23112984 # number of ReadReq hits 595system.cpu.dcache.ReadReq_hits::total 23112984 # number of ReadReq hits 596system.cpu.dcache.WriteReq_hits::cpu.data 18824227 # number of WriteReq hits 597system.cpu.dcache.WriteReq_hits::total 18824227 # number of WriteReq hits 598system.cpu.dcache.SoftPFReq_hits::cpu.data 392786 # number of SoftPFReq hits 599system.cpu.dcache.SoftPFReq_hits::total 392786 # number of SoftPFReq hits 600system.cpu.dcache.LoadLockedReq_hits::cpu.data 443250 # number of LoadLockedReq hits 601system.cpu.dcache.LoadLockedReq_hits::total 443250 # number of LoadLockedReq hits 602system.cpu.dcache.StoreCondReq_hits::cpu.data 460223 # number of StoreCondReq hits 603system.cpu.dcache.StoreCondReq_hits::total 460223 # number of StoreCondReq hits 604system.cpu.dcache.demand_hits::cpu.data 41937211 # number of demand (read+write) hits 605system.cpu.dcache.demand_hits::total 41937211 # number of demand (read+write) hits 606system.cpu.dcache.overall_hits::cpu.data 42329997 # number of overall hits 607system.cpu.dcache.overall_hits::total 42329997 # number of overall hits 608system.cpu.dcache.ReadReq_misses::cpu.data 399912 # number of ReadReq misses 609system.cpu.dcache.ReadReq_misses::total 399912 # number of ReadReq misses 610system.cpu.dcache.WriteReq_misses::cpu.data 298709 # number of WriteReq misses 611system.cpu.dcache.WriteReq_misses::total 298709 # number of WriteReq misses 612system.cpu.dcache.SoftPFReq_misses::cpu.data 118381 # number of SoftPFReq misses 613system.cpu.dcache.SoftPFReq_misses::total 118381 # number of SoftPFReq misses 614system.cpu.dcache.LoadLockedReq_misses::cpu.data 22756 # number of LoadLockedReq misses 615system.cpu.dcache.LoadLockedReq_misses::total 22756 # number of LoadLockedReq misses 616system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses 617system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses 618system.cpu.dcache.demand_misses::cpu.data 698621 # number of demand (read+write) misses 619system.cpu.dcache.demand_misses::total 698621 # number of demand (read+write) misses 620system.cpu.dcache.overall_misses::cpu.data 817002 # number of overall misses 621system.cpu.dcache.overall_misses::total 817002 # number of overall misses 622system.cpu.dcache.ReadReq_miss_latency::cpu.data 6488404500 # number of ReadReq miss cycles 623system.cpu.dcache.ReadReq_miss_latency::total 6488404500 # number of ReadReq miss cycles 624system.cpu.dcache.WriteReq_miss_latency::cpu.data 19100944000 # number of WriteReq miss cycles 625system.cpu.dcache.WriteReq_miss_latency::total 19100944000 # number of WriteReq miss cycles 626system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 293896000 # number of LoadLockedReq miss cycles 627system.cpu.dcache.LoadLockedReq_miss_latency::total 293896000 # number of LoadLockedReq miss cycles 628system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 164000 # number of StoreCondReq miss cycles 629system.cpu.dcache.StoreCondReq_miss_latency::total 164000 # number of StoreCondReq miss cycles 630system.cpu.dcache.demand_miss_latency::cpu.data 25589348500 # number of demand (read+write) miss cycles 631system.cpu.dcache.demand_miss_latency::total 25589348500 # number of demand (read+write) miss cycles 632system.cpu.dcache.overall_miss_latency::cpu.data 25589348500 # number of overall miss cycles 633system.cpu.dcache.overall_miss_latency::total 25589348500 # number of overall miss cycles 634system.cpu.dcache.ReadReq_accesses::cpu.data 23512896 # number of ReadReq accesses(hits+misses) 635system.cpu.dcache.ReadReq_accesses::total 23512896 # number of ReadReq accesses(hits+misses) 636system.cpu.dcache.WriteReq_accesses::cpu.data 19122936 # number of WriteReq accesses(hits+misses) 637system.cpu.dcache.WriteReq_accesses::total 19122936 # number of WriteReq accesses(hits+misses) 638system.cpu.dcache.SoftPFReq_accesses::cpu.data 511167 # number of SoftPFReq accesses(hits+misses) 639system.cpu.dcache.SoftPFReq_accesses::total 511167 # number of SoftPFReq accesses(hits+misses) 640system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466006 # number of LoadLockedReq accesses(hits+misses) 641system.cpu.dcache.LoadLockedReq_accesses::total 466006 # number of LoadLockedReq accesses(hits+misses) 642system.cpu.dcache.StoreCondReq_accesses::cpu.data 460225 # number of StoreCondReq accesses(hits+misses) 643system.cpu.dcache.StoreCondReq_accesses::total 460225 # number of StoreCondReq accesses(hits+misses) 644system.cpu.dcache.demand_accesses::cpu.data 42635832 # number of demand (read+write) accesses 645system.cpu.dcache.demand_accesses::total 42635832 # number of demand (read+write) accesses 646system.cpu.dcache.overall_accesses::cpu.data 43146999 # number of overall (read+write) accesses 647system.cpu.dcache.overall_accesses::total 43146999 # number of overall (read+write) accesses 648system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017008 # miss rate for ReadReq accesses 649system.cpu.dcache.ReadReq_miss_rate::total 0.017008 # miss rate for ReadReq accesses 650system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015620 # miss rate for WriteReq accesses 651system.cpu.dcache.WriteReq_miss_rate::total 0.015620 # miss rate for WriteReq accesses 652system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.231590 # miss rate for SoftPFReq accesses 653system.cpu.dcache.SoftPFReq_miss_rate::total 0.231590 # miss rate for SoftPFReq accesses 654system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048832 # miss rate for LoadLockedReq accesses 655system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048832 # miss rate for LoadLockedReq accesses 656system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses 657system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses 658system.cpu.dcache.demand_miss_rate::cpu.data 0.016386 # miss rate for demand accesses 659system.cpu.dcache.demand_miss_rate::total 0.016386 # miss rate for demand accesses 660system.cpu.dcache.overall_miss_rate::cpu.data 0.018935 # miss rate for overall accesses 661system.cpu.dcache.overall_miss_rate::total 0.018935 # miss rate for overall accesses 662system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16224.580658 # average ReadReq miss latency 663system.cpu.dcache.ReadReq_avg_miss_latency::total 16224.580658 # average ReadReq miss latency 664system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63944.989940 # average WriteReq miss latency 665system.cpu.dcache.WriteReq_avg_miss_latency::total 63944.989940 # average WriteReq miss latency 666system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12915.099314 # average LoadLockedReq miss latency 667system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12915.099314 # average LoadLockedReq miss latency 668system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency 669system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency 670system.cpu.dcache.demand_avg_miss_latency::cpu.data 36628.370032 # average overall miss latency 671system.cpu.dcache.demand_avg_miss_latency::total 36628.370032 # average overall miss latency 672system.cpu.dcache.overall_avg_miss_latency::cpu.data 31321.035322 # average overall miss latency 673system.cpu.dcache.overall_avg_miss_latency::total 31321.035322 # average overall miss latency 674system.cpu.dcache.blocked_cycles::no_mshrs 100 # number of cycles access was blocked 675system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 676system.cpu.dcache.blocked::no_mshrs 20 # number of cycles access was blocked 677system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 678system.cpu.dcache.avg_blocked_cycles::no_mshrs 5 # average number of cycles each access was blocked 679system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 680system.cpu.dcache.writebacks::writebacks 683846 # number of writebacks 681system.cpu.dcache.writebacks::total 683846 # number of writebacks 682system.cpu.dcache.ReadReq_mshr_hits::cpu.data 929 # number of ReadReq MSHR hits 683system.cpu.dcache.ReadReq_mshr_hits::total 929 # number of ReadReq MSHR hits 684system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14246 # number of LoadLockedReq MSHR hits 685system.cpu.dcache.LoadLockedReq_mshr_hits::total 14246 # number of LoadLockedReq MSHR hits 686system.cpu.dcache.demand_mshr_hits::cpu.data 929 # number of demand (read+write) MSHR hits 687system.cpu.dcache.demand_mshr_hits::total 929 # number of demand (read+write) MSHR hits 688system.cpu.dcache.overall_mshr_hits::cpu.data 929 # number of overall MSHR hits 689system.cpu.dcache.overall_mshr_hits::total 929 # number of overall MSHR hits 690system.cpu.dcache.ReadReq_mshr_misses::cpu.data 398983 # number of ReadReq MSHR misses 691system.cpu.dcache.ReadReq_mshr_misses::total 398983 # number of ReadReq MSHR misses 692system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298709 # number of WriteReq MSHR misses 693system.cpu.dcache.WriteReq_mshr_misses::total 298709 # number of WriteReq MSHR misses 694system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 116322 # number of SoftPFReq MSHR misses 695system.cpu.dcache.SoftPFReq_mshr_misses::total 116322 # number of SoftPFReq MSHR misses 696system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8510 # number of LoadLockedReq MSHR misses 697system.cpu.dcache.LoadLockedReq_mshr_misses::total 8510 # number of LoadLockedReq MSHR misses 698system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses 699system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses 700system.cpu.dcache.demand_mshr_misses::cpu.data 697692 # number of demand (read+write) MSHR misses 701system.cpu.dcache.demand_mshr_misses::total 697692 # number of demand (read+write) MSHR misses 702system.cpu.dcache.overall_mshr_misses::cpu.data 814014 # number of overall MSHR misses 703system.cpu.dcache.overall_mshr_misses::total 814014 # number of overall MSHR misses 704system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31138 # number of ReadReq MSHR uncacheable 705system.cpu.dcache.ReadReq_mshr_uncacheable::total 31138 # number of ReadReq MSHR uncacheable 706system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27589 # number of WriteReq MSHR uncacheable 707system.cpu.dcache.WriteReq_mshr_uncacheable::total 27589 # number of WriteReq MSHR uncacheable 708system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58727 # number of overall MSHR uncacheable misses 709system.cpu.dcache.overall_mshr_uncacheable_misses::total 58727 # number of overall MSHR uncacheable misses 710system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6058749500 # number of ReadReq MSHR miss cycles 711system.cpu.dcache.ReadReq_mshr_miss_latency::total 6058749500 # number of ReadReq MSHR miss cycles 712system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 18802235000 # number of WriteReq MSHR miss cycles 713system.cpu.dcache.WriteReq_mshr_miss_latency::total 18802235000 # number of WriteReq MSHR miss cycles 714system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1616519000 # number of SoftPFReq MSHR miss cycles 715system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1616519000 # number of SoftPFReq MSHR miss cycles 716system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 115353500 # number of LoadLockedReq MSHR miss cycles 717system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 115353500 # number of LoadLockedReq MSHR miss cycles 718system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 162000 # number of StoreCondReq MSHR miss cycles 719system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 162000 # number of StoreCondReq MSHR miss cycles 720system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24860984500 # number of demand (read+write) MSHR miss cycles 721system.cpu.dcache.demand_mshr_miss_latency::total 24860984500 # number of demand (read+write) MSHR miss cycles 722system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26477503500 # number of overall MSHR miss cycles 723system.cpu.dcache.overall_mshr_miss_latency::total 26477503500 # number of overall MSHR miss cycles 724system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6278149500 # number of ReadReq MSHR uncacheable cycles 725system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6278149500 # number of ReadReq MSHR uncacheable cycles 726system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6278149500 # number of overall MSHR uncacheable cycles 727system.cpu.dcache.overall_mshr_uncacheable_latency::total 6278149500 # number of overall MSHR uncacheable cycles 728system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016969 # mshr miss rate for ReadReq accesses 729system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016969 # mshr miss rate for ReadReq accesses 730system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015620 # mshr miss rate for WriteReq accesses 731system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015620 # mshr miss rate for WriteReq accesses 732system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227562 # mshr miss rate for SoftPFReq accesses 733system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227562 # mshr miss rate for SoftPFReq accesses 734system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018262 # mshr miss rate for LoadLockedReq accesses 735system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018262 # mshr miss rate for LoadLockedReq accesses 736system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses 737system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses 738system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016364 # mshr miss rate for demand accesses 739system.cpu.dcache.demand_mshr_miss_rate::total 0.016364 # mshr miss rate for demand accesses 740system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018866 # mshr miss rate for overall accesses 741system.cpu.dcache.overall_mshr_miss_rate::total 0.018866 # mshr miss rate for overall accesses 742system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15185.482840 # average ReadReq mshr miss latency 743system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15185.482840 # average ReadReq mshr miss latency 744system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62944.989940 # average WriteReq mshr miss latency 745system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62944.989940 # average WriteReq mshr miss latency 746system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13896.932652 # average SoftPFReq mshr miss latency 747system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13896.932652 # average SoftPFReq mshr miss latency 748system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13555.052879 # average LoadLockedReq mshr miss latency 749system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13555.052879 # average LoadLockedReq mshr miss latency 750system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81000 # average StoreCondReq mshr miss latency 751system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency 752system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35633.179827 # average overall mshr miss latency 753system.cpu.dcache.demand_avg_mshr_miss_latency::total 35633.179827 # average overall mshr miss latency 754system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32527.086143 # average overall mshr miss latency 755system.cpu.dcache.overall_avg_mshr_miss_latency::total 32527.086143 # average overall mshr miss latency 756system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201623.402274 # average ReadReq mshr uncacheable latency 757system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201623.402274 # average ReadReq mshr uncacheable latency 758system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106903.970916 # average overall mshr uncacheable latency 759system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106903.970916 # average overall mshr uncacheable latency 760system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 761system.cpu.icache.tags.replacements 1695721 # number of replacements 762system.cpu.icache.tags.tagsinuse 510.436852 # Cycle average of tags in use 763system.cpu.icache.tags.total_refs 113858019 # Total number of references to valid blocks. 764system.cpu.icache.tags.sampled_refs 1696233 # Sample count of references to valid blocks. 765system.cpu.icache.tags.avg_refs 67.124044 # Average number of references to valid blocks. 766system.cpu.icache.tags.warmup_cycle 29070355500 # Cycle when the warmup percentage was hit. 767system.cpu.icache.tags.occ_blocks::cpu.inst 510.436852 # Average occupied blocks per requestor 768system.cpu.icache.tags.occ_percent::cpu.inst 0.996947 # Average percentage of cache occupancy 769system.cpu.icache.tags.occ_percent::total 0.996947 # Average percentage of cache occupancy 770system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 771system.cpu.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id 772system.cpu.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id 773system.cpu.icache.tags.age_task_id_blocks_1024::2 262 # Occupied blocks per task id 774system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id 775system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 776system.cpu.icache.tags.tag_accesses 117250497 # Number of tag accesses 777system.cpu.icache.tags.data_accesses 117250497 # Number of data accesses 778system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 779system.cpu.icache.ReadReq_hits::cpu.inst 113858019 # number of ReadReq hits 780system.cpu.icache.ReadReq_hits::total 113858019 # number of ReadReq hits 781system.cpu.icache.demand_hits::cpu.inst 113858019 # number of demand (read+write) hits 782system.cpu.icache.demand_hits::total 113858019 # number of demand (read+write) hits 783system.cpu.icache.overall_hits::cpu.inst 113858019 # number of overall hits 784system.cpu.icache.overall_hits::total 113858019 # number of overall hits 785system.cpu.icache.ReadReq_misses::cpu.inst 1696239 # number of ReadReq misses 786system.cpu.icache.ReadReq_misses::total 1696239 # number of ReadReq misses 787system.cpu.icache.demand_misses::cpu.inst 1696239 # number of demand (read+write) misses 788system.cpu.icache.demand_misses::total 1696239 # number of demand (read+write) misses 789system.cpu.icache.overall_misses::cpu.inst 1696239 # number of overall misses 790system.cpu.icache.overall_misses::total 1696239 # number of overall misses 791system.cpu.icache.ReadReq_miss_latency::cpu.inst 24272132000 # number of ReadReq miss cycles 792system.cpu.icache.ReadReq_miss_latency::total 24272132000 # number of ReadReq miss cycles 793system.cpu.icache.demand_miss_latency::cpu.inst 24272132000 # number of demand (read+write) miss cycles 794system.cpu.icache.demand_miss_latency::total 24272132000 # number of demand (read+write) miss cycles 795system.cpu.icache.overall_miss_latency::cpu.inst 24272132000 # number of overall miss cycles 796system.cpu.icache.overall_miss_latency::total 24272132000 # number of overall miss cycles 797system.cpu.icache.ReadReq_accesses::cpu.inst 115554258 # number of ReadReq accesses(hits+misses) 798system.cpu.icache.ReadReq_accesses::total 115554258 # number of ReadReq accesses(hits+misses) 799system.cpu.icache.demand_accesses::cpu.inst 115554258 # number of demand (read+write) accesses 800system.cpu.icache.demand_accesses::total 115554258 # number of demand (read+write) accesses 801system.cpu.icache.overall_accesses::cpu.inst 115554258 # number of overall (read+write) accesses 802system.cpu.icache.overall_accesses::total 115554258 # number of overall (read+write) accesses 803system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014679 # miss rate for ReadReq accesses 804system.cpu.icache.ReadReq_miss_rate::total 0.014679 # miss rate for ReadReq accesses 805system.cpu.icache.demand_miss_rate::cpu.inst 0.014679 # miss rate for demand accesses 806system.cpu.icache.demand_miss_rate::total 0.014679 # miss rate for demand accesses 807system.cpu.icache.overall_miss_rate::cpu.inst 0.014679 # miss rate for overall accesses 808system.cpu.icache.overall_miss_rate::total 0.014679 # miss rate for overall accesses 809system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14309.382109 # average ReadReq miss latency 810system.cpu.icache.ReadReq_avg_miss_latency::total 14309.382109 # average ReadReq miss latency 811system.cpu.icache.demand_avg_miss_latency::cpu.inst 14309.382109 # average overall miss latency 812system.cpu.icache.demand_avg_miss_latency::total 14309.382109 # average overall miss latency 813system.cpu.icache.overall_avg_miss_latency::cpu.inst 14309.382109 # average overall miss latency 814system.cpu.icache.overall_avg_miss_latency::total 14309.382109 # average overall miss latency 815system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 816system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 817system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 818system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 819system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 820system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 821system.cpu.icache.writebacks::writebacks 1695721 # number of writebacks 822system.cpu.icache.writebacks::total 1695721 # number of writebacks 823system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1696239 # number of ReadReq MSHR misses 824system.cpu.icache.ReadReq_mshr_misses::total 1696239 # number of ReadReq MSHR misses 825system.cpu.icache.demand_mshr_misses::cpu.inst 1696239 # number of demand (read+write) MSHR misses 826system.cpu.icache.demand_mshr_misses::total 1696239 # number of demand (read+write) MSHR misses 827system.cpu.icache.overall_mshr_misses::cpu.inst 1696239 # number of overall MSHR misses 828system.cpu.icache.overall_mshr_misses::total 1696239 # number of overall MSHR misses 829system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 9022 # number of ReadReq MSHR uncacheable 830system.cpu.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable 831system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses 832system.cpu.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses 833system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22575893000 # number of ReadReq MSHR miss cycles 834system.cpu.icache.ReadReq_mshr_miss_latency::total 22575893000 # number of ReadReq MSHR miss cycles 835system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22575893000 # number of demand (read+write) MSHR miss cycles 836system.cpu.icache.demand_mshr_miss_latency::total 22575893000 # number of demand (read+write) MSHR miss cycles 837system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22575893000 # number of overall MSHR miss cycles 838system.cpu.icache.overall_mshr_miss_latency::total 22575893000 # number of overall MSHR miss cycles 839system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1142541000 # number of ReadReq MSHR uncacheable cycles 840system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1142541000 # number of ReadReq MSHR uncacheable cycles 841system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 1142541000 # number of overall MSHR uncacheable cycles 842system.cpu.icache.overall_mshr_uncacheable_latency::total 1142541000 # number of overall MSHR uncacheable cycles 843system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014679 # mshr miss rate for ReadReq accesses 844system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014679 # mshr miss rate for ReadReq accesses 845system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014679 # mshr miss rate for demand accesses 846system.cpu.icache.demand_mshr_miss_rate::total 0.014679 # mshr miss rate for demand accesses 847system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014679 # mshr miss rate for overall accesses 848system.cpu.icache.overall_mshr_miss_rate::total 0.014679 # mshr miss rate for overall accesses 849system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13309.382109 # average ReadReq mshr miss latency 850system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13309.382109 # average ReadReq mshr miss latency 851system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13309.382109 # average overall mshr miss latency 852system.cpu.icache.demand_avg_mshr_miss_latency::total 13309.382109 # average overall mshr miss latency 853system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13309.382109 # average overall mshr miss latency 854system.cpu.icache.overall_avg_mshr_miss_latency::total 13309.382109 # average overall mshr miss latency 855system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126639.436932 # average ReadReq mshr uncacheable latency 856system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126639.436932 # average ReadReq mshr uncacheable latency 857system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126639.436932 # average overall mshr uncacheable latency 858system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126639.436932 # average overall mshr uncacheable latency 859system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 860system.cpu.l2cache.tags.replacements 87565 # number of replacements 861system.cpu.l2cache.tags.tagsinuse 64865.223598 # Cycle average of tags in use 862system.cpu.l2cache.tags.total_refs 4544536 # Total number of references to valid blocks. 863system.cpu.l2cache.tags.sampled_refs 152800 # Sample count of references to valid blocks. 864system.cpu.l2cache.tags.avg_refs 29.741728 # Average number of references to valid blocks. 865system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 866system.cpu.l2cache.tags.occ_blocks::writebacks 50196.713333 # Average occupied blocks per requestor 867system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.799338 # Average occupied blocks per requestor 868system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.012649 # Average occupied blocks per requestor 869system.cpu.l2cache.tags.occ_blocks::cpu.inst 9701.721355 # Average occupied blocks per requestor 870system.cpu.l2cache.tags.occ_blocks::cpu.data 4962.976923 # Average occupied blocks per requestor 871system.cpu.l2cache.tags.occ_percent::writebacks 0.765941 # Average percentage of cache occupancy 872system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000058 # Average percentage of cache occupancy 873system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy 874system.cpu.l2cache.tags.occ_percent::cpu.inst 0.148037 # Average percentage of cache occupancy 875system.cpu.l2cache.tags.occ_percent::cpu.data 0.075729 # Average percentage of cache occupancy 876system.cpu.l2cache.tags.occ_percent::total 0.989765 # Average percentage of cache occupancy 877system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id 878system.cpu.l2cache.tags.occ_task_id_blocks::1024 65230 # Occupied blocks per task id 879system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id 880system.cpu.l2cache.tags.age_task_id_blocks_1024::0 13 # Occupied blocks per task id 881system.cpu.l2cache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id 882system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2129 # Occupied blocks per task id 883system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6851 # Occupied blocks per task id 884system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56199 # Occupied blocks per task id 885system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id 886system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995331 # Percentage of cache occupancy per task id 887system.cpu.l2cache.tags.tag_accesses 40512344 # Number of tag accesses 888system.cpu.l2cache.tags.data_accesses 40512344 # Number of data accesses 889system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 890system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7807 # number of ReadReq hits 891system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4039 # number of ReadReq hits 892system.cpu.l2cache.ReadReq_hits::total 11846 # number of ReadReq hits 893system.cpu.l2cache.WritebackDirty_hits::writebacks 683846 # number of WritebackDirty hits 894system.cpu.l2cache.WritebackDirty_hits::total 683846 # number of WritebackDirty hits 895system.cpu.l2cache.WritebackClean_hits::writebacks 1664945 # number of WritebackClean hits 896system.cpu.l2cache.WritebackClean_hits::total 1664945 # number of WritebackClean hits 897system.cpu.l2cache.UpgradeReq_hits::cpu.data 23 # number of UpgradeReq hits 898system.cpu.l2cache.UpgradeReq_hits::total 23 # number of UpgradeReq hits 899system.cpu.l2cache.ReadExReq_hits::cpu.data 167031 # number of ReadExReq hits 900system.cpu.l2cache.ReadExReq_hits::total 167031 # number of ReadExReq hits 901system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1678228 # number of ReadCleanReq hits 902system.cpu.l2cache.ReadCleanReq_hits::total 1678228 # number of ReadCleanReq hits 903system.cpu.l2cache.ReadSharedReq_hits::cpu.data 511642 # number of ReadSharedReq hits 904system.cpu.l2cache.ReadSharedReq_hits::total 511642 # number of ReadSharedReq hits 905system.cpu.l2cache.demand_hits::cpu.dtb.walker 7807 # number of demand (read+write) hits 906system.cpu.l2cache.demand_hits::cpu.itb.walker 4039 # number of demand (read+write) hits 907system.cpu.l2cache.demand_hits::cpu.inst 1678228 # number of demand (read+write) hits 908system.cpu.l2cache.demand_hits::cpu.data 678673 # number of demand (read+write) hits 909system.cpu.l2cache.demand_hits::total 2368747 # number of demand (read+write) hits 910system.cpu.l2cache.overall_hits::cpu.dtb.walker 7807 # number of overall hits 911system.cpu.l2cache.overall_hits::cpu.itb.walker 4039 # number of overall hits 912system.cpu.l2cache.overall_hits::cpu.inst 1678228 # number of overall hits 913system.cpu.l2cache.overall_hits::cpu.data 678673 # number of overall hits 914system.cpu.l2cache.overall_hits::total 2368747 # number of overall hits 915system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses 916system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses 917system.cpu.l2cache.ReadReq_misses::total 9 # number of ReadReq misses 918system.cpu.l2cache.UpgradeReq_misses::cpu.data 2742 # number of UpgradeReq misses 919system.cpu.l2cache.UpgradeReq_misses::total 2742 # number of UpgradeReq misses 920system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses 921system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses 922system.cpu.l2cache.ReadExReq_misses::cpu.data 128913 # number of ReadExReq misses 923system.cpu.l2cache.ReadExReq_misses::total 128913 # number of ReadExReq misses 924system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 17978 # number of ReadCleanReq misses 925system.cpu.l2cache.ReadCleanReq_misses::total 17978 # number of ReadCleanReq misses 926system.cpu.l2cache.ReadSharedReq_misses::cpu.data 12173 # number of ReadSharedReq misses 927system.cpu.l2cache.ReadSharedReq_misses::total 12173 # number of ReadSharedReq misses 928system.cpu.l2cache.demand_misses::cpu.dtb.walker 7 # number of demand (read+write) misses 929system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses 930system.cpu.l2cache.demand_misses::cpu.inst 17978 # number of demand (read+write) misses 931system.cpu.l2cache.demand_misses::cpu.data 141086 # number of demand (read+write) misses 932system.cpu.l2cache.demand_misses::total 159073 # number of demand (read+write) misses 933system.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses 934system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses 935system.cpu.l2cache.overall_misses::cpu.inst 17978 # number of overall misses 936system.cpu.l2cache.overall_misses::cpu.data 141086 # number of overall misses 937system.cpu.l2cache.overall_misses::total 159073 # number of overall misses 938system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 957500 # number of ReadReq miss cycles 939system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 266000 # number of ReadReq miss cycles 940system.cpu.l2cache.ReadReq_miss_latency::total 1223500 # number of ReadReq miss cycles 941system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1793500 # number of UpgradeReq miss cycles 942system.cpu.l2cache.UpgradeReq_miss_latency::total 1793500 # number of UpgradeReq miss cycles 943system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 159000 # number of SCUpgradeReq miss cycles 944system.cpu.l2cache.SCUpgradeReq_miss_latency::total 159000 # number of SCUpgradeReq miss cycles 945system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16382558000 # number of ReadExReq miss cycles 946system.cpu.l2cache.ReadExReq_miss_latency::total 16382558000 # number of ReadExReq miss cycles 947system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2351292500 # number of ReadCleanReq miss cycles 948system.cpu.l2cache.ReadCleanReq_miss_latency::total 2351292500 # number of ReadCleanReq miss cycles 949system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1615422500 # number of ReadSharedReq miss cycles 950system.cpu.l2cache.ReadSharedReq_miss_latency::total 1615422500 # number of ReadSharedReq miss cycles 951system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 957500 # number of demand (read+write) miss cycles 952system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 266000 # number of demand (read+write) miss cycles 953system.cpu.l2cache.demand_miss_latency::cpu.inst 2351292500 # number of demand (read+write) miss cycles 954system.cpu.l2cache.demand_miss_latency::cpu.data 17997980500 # number of demand (read+write) miss cycles 955system.cpu.l2cache.demand_miss_latency::total 20350496500 # number of demand (read+write) miss cycles 956system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 957500 # number of overall miss cycles 957system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 266000 # number of overall miss cycles 958system.cpu.l2cache.overall_miss_latency::cpu.inst 2351292500 # number of overall miss cycles 959system.cpu.l2cache.overall_miss_latency::cpu.data 17997980500 # number of overall miss cycles 960system.cpu.l2cache.overall_miss_latency::total 20350496500 # number of overall miss cycles 961system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7814 # number of ReadReq accesses(hits+misses) 962system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 4041 # number of ReadReq accesses(hits+misses) 963system.cpu.l2cache.ReadReq_accesses::total 11855 # number of ReadReq accesses(hits+misses) 964system.cpu.l2cache.WritebackDirty_accesses::writebacks 683846 # number of WritebackDirty accesses(hits+misses) 965system.cpu.l2cache.WritebackDirty_accesses::total 683846 # number of WritebackDirty accesses(hits+misses) 966system.cpu.l2cache.WritebackClean_accesses::writebacks 1664945 # number of WritebackClean accesses(hits+misses) 967system.cpu.l2cache.WritebackClean_accesses::total 1664945 # number of WritebackClean accesses(hits+misses) 968system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2765 # number of UpgradeReq accesses(hits+misses) 969system.cpu.l2cache.UpgradeReq_accesses::total 2765 # number of UpgradeReq accesses(hits+misses) 970system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) 971system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) 972system.cpu.l2cache.ReadExReq_accesses::cpu.data 295944 # number of ReadExReq accesses(hits+misses) 973system.cpu.l2cache.ReadExReq_accesses::total 295944 # number of ReadExReq accesses(hits+misses) 974system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1696206 # number of ReadCleanReq accesses(hits+misses) 975system.cpu.l2cache.ReadCleanReq_accesses::total 1696206 # number of ReadCleanReq accesses(hits+misses) 976system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 523815 # number of ReadSharedReq accesses(hits+misses) 977system.cpu.l2cache.ReadSharedReq_accesses::total 523815 # number of ReadSharedReq accesses(hits+misses) 978system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7814 # number of demand (read+write) accesses 979system.cpu.l2cache.demand_accesses::cpu.itb.walker 4041 # number of demand (read+write) accesses 980system.cpu.l2cache.demand_accesses::cpu.inst 1696206 # number of demand (read+write) accesses 981system.cpu.l2cache.demand_accesses::cpu.data 819759 # number of demand (read+write) accesses 982system.cpu.l2cache.demand_accesses::total 2527820 # number of demand (read+write) accesses 983system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7814 # number of overall (read+write) accesses 984system.cpu.l2cache.overall_accesses::cpu.itb.walker 4041 # number of overall (read+write) accesses 985system.cpu.l2cache.overall_accesses::cpu.inst 1696206 # number of overall (read+write) accesses 986system.cpu.l2cache.overall_accesses::cpu.data 819759 # number of overall (read+write) accesses 987system.cpu.l2cache.overall_accesses::total 2527820 # number of overall (read+write) accesses 988system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000896 # miss rate for ReadReq accesses 989system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000495 # miss rate for ReadReq accesses 990system.cpu.l2cache.ReadReq_miss_rate::total 0.000759 # miss rate for ReadReq accesses 991system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991682 # miss rate for UpgradeReq accesses 992system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991682 # miss rate for UpgradeReq accesses 993system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 994system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 995system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.435599 # miss rate for ReadExReq accesses 996system.cpu.l2cache.ReadExReq_miss_rate::total 0.435599 # miss rate for ReadExReq accesses 997system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010599 # miss rate for ReadCleanReq accesses 998system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010599 # miss rate for ReadCleanReq accesses 999system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.023239 # miss rate for ReadSharedReq accesses 1000system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.023239 # miss rate for ReadSharedReq accesses 1001system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000896 # miss rate for demand accesses 1002system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000495 # miss rate for demand accesses 1003system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010599 # miss rate for demand accesses 1004system.cpu.l2cache.demand_miss_rate::cpu.data 0.172107 # miss rate for demand accesses 1005system.cpu.l2cache.demand_miss_rate::total 0.062929 # miss rate for demand accesses 1006system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000896 # miss rate for overall accesses 1007system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000495 # miss rate for overall accesses 1008system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010599 # miss rate for overall accesses 1009system.cpu.l2cache.overall_miss_rate::cpu.data 0.172107 # miss rate for overall accesses 1010system.cpu.l2cache.overall_miss_rate::total 0.062929 # miss rate for overall accesses 1011system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 136785.714286 # average ReadReq miss latency 1012system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 133000 # average ReadReq miss latency 1013system.cpu.l2cache.ReadReq_avg_miss_latency::total 135944.444444 # average ReadReq miss latency 1014system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 654.084610 # average UpgradeReq miss latency 1015system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 654.084610 # average UpgradeReq miss latency 1016system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 79500 # average SCUpgradeReq miss latency 1017system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency 1018system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127082.280298 # average ReadExReq miss latency 1019system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127082.280298 # average ReadExReq miss latency 1020system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130787.212148 # average ReadCleanReq miss latency 1021system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130787.212148 # average ReadCleanReq miss latency 1022system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 132705.372546 # average ReadSharedReq miss latency 1023system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 132705.372546 # average ReadSharedReq miss latency 1024system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 136785.714286 # average overall miss latency 1025system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 133000 # average overall miss latency 1026system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130787.212148 # average overall miss latency 1027system.cpu.l2cache.demand_avg_miss_latency::cpu.data 127567.444679 # average overall miss latency 1028system.cpu.l2cache.demand_avg_miss_latency::total 127931.808038 # average overall miss latency 1029system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 136785.714286 # average overall miss latency 1030system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 133000 # average overall miss latency 1031system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130787.212148 # average overall miss latency 1032system.cpu.l2cache.overall_avg_miss_latency::cpu.data 127567.444679 # average overall miss latency 1033system.cpu.l2cache.overall_avg_miss_latency::total 127931.808038 # average overall miss latency 1034system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1035system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1036system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1037system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1038system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1039system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1040system.cpu.l2cache.writebacks::writebacks 81185 # number of writebacks 1041system.cpu.l2cache.writebacks::total 81185 # number of writebacks 1042system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 7 # number of ReadReq MSHR misses 1043system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses 1044system.cpu.l2cache.ReadReq_mshr_misses::total 9 # number of ReadReq MSHR misses 1045system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2742 # number of UpgradeReq MSHR misses 1046system.cpu.l2cache.UpgradeReq_mshr_misses::total 2742 # number of UpgradeReq MSHR misses 1047system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses 1048system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses 1049system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 128913 # number of ReadExReq MSHR misses 1050system.cpu.l2cache.ReadExReq_mshr_misses::total 128913 # number of ReadExReq MSHR misses 1051system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 17978 # number of ReadCleanReq MSHR misses 1052system.cpu.l2cache.ReadCleanReq_mshr_misses::total 17978 # number of ReadCleanReq MSHR misses 1053system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 12173 # number of ReadSharedReq MSHR misses 1054system.cpu.l2cache.ReadSharedReq_mshr_misses::total 12173 # number of ReadSharedReq MSHR misses 1055system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 7 # number of demand (read+write) MSHR misses 1056system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses 1057system.cpu.l2cache.demand_mshr_misses::cpu.inst 17978 # number of demand (read+write) MSHR misses 1058system.cpu.l2cache.demand_mshr_misses::cpu.data 141086 # number of demand (read+write) MSHR misses 1059system.cpu.l2cache.demand_mshr_misses::total 159073 # number of demand (read+write) MSHR misses 1060system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 7 # number of overall MSHR misses 1061system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses 1062system.cpu.l2cache.overall_mshr_misses::cpu.inst 17978 # number of overall MSHR misses 1063system.cpu.l2cache.overall_mshr_misses::cpu.data 141086 # number of overall MSHR misses 1064system.cpu.l2cache.overall_mshr_misses::total 159073 # number of overall MSHR misses 1065system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 9022 # number of ReadReq MSHR uncacheable 1066system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31138 # number of ReadReq MSHR uncacheable 1067system.cpu.l2cache.ReadReq_mshr_uncacheable::total 40160 # number of ReadReq MSHR uncacheable 1068system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27589 # number of WriteReq MSHR uncacheable 1069system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27589 # number of WriteReq MSHR uncacheable 1070system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses 1071system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58727 # number of overall MSHR uncacheable misses 1072system.cpu.l2cache.overall_mshr_uncacheable_misses::total 67749 # number of overall MSHR uncacheable misses 1073system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 887500 # number of ReadReq MSHR miss cycles 1074system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 246000 # number of ReadReq MSHR miss cycles 1075system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1133500 # number of ReadReq MSHR miss cycles 1076system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 186544500 # number of UpgradeReq MSHR miss cycles 1077system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 186544500 # number of UpgradeReq MSHR miss cycles 1078system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 139000 # number of SCUpgradeReq MSHR miss cycles 1079system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 139000 # number of SCUpgradeReq MSHR miss cycles 1080system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 15093428000 # number of ReadExReq MSHR miss cycles 1081system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 15093428000 # number of ReadExReq MSHR miss cycles 1082system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2171512500 # number of ReadCleanReq MSHR miss cycles 1083system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2171512500 # number of ReadCleanReq MSHR miss cycles 1084system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1493692500 # number of ReadSharedReq MSHR miss cycles 1085system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1493692500 # number of ReadSharedReq MSHR miss cycles 1086system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 887500 # number of demand (read+write) MSHR miss cycles 1087system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 246000 # number of demand (read+write) MSHR miss cycles 1088system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2171512500 # number of demand (read+write) MSHR miss cycles 1089system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16587120500 # number of demand (read+write) MSHR miss cycles 1090system.cpu.l2cache.demand_mshr_miss_latency::total 18759766500 # number of demand (read+write) MSHR miss cycles 1091system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 887500 # number of overall MSHR miss cycles 1092system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 246000 # number of overall MSHR miss cycles 1093system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2171512500 # number of overall MSHR miss cycles 1094system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16587120500 # number of overall MSHR miss cycles 1095system.cpu.l2cache.overall_mshr_miss_latency::total 18759766500 # number of overall MSHR miss cycles 1096system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1029766000 # number of ReadReq MSHR uncacheable cycles 1097system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5888804000 # number of ReadReq MSHR uncacheable cycles 1098system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6918570000 # number of ReadReq MSHR uncacheable cycles 1099system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 1029766000 # number of overall MSHR uncacheable cycles 1100system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5888804000 # number of overall MSHR uncacheable cycles 1101system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6918570000 # number of overall MSHR uncacheable cycles 1102system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000896 # mshr miss rate for ReadReq accesses 1103system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000495 # mshr miss rate for ReadReq accesses 1104system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000759 # mshr miss rate for ReadReq accesses 1105system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991682 # mshr miss rate for UpgradeReq accesses 1106system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991682 # mshr miss rate for UpgradeReq accesses 1107system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses 1108system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1109system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.435599 # mshr miss rate for ReadExReq accesses 1110system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.435599 # mshr miss rate for ReadExReq accesses 1111system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010599 # mshr miss rate for ReadCleanReq accesses 1112system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010599 # mshr miss rate for ReadCleanReq accesses 1113system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.023239 # mshr miss rate for ReadSharedReq accesses 1114system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.023239 # mshr miss rate for ReadSharedReq accesses 1115system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000896 # mshr miss rate for demand accesses 1116system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000495 # mshr miss rate for demand accesses 1117system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010599 # mshr miss rate for demand accesses 1118system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172107 # mshr miss rate for demand accesses 1119system.cpu.l2cache.demand_mshr_miss_rate::total 0.062929 # mshr miss rate for demand accesses 1120system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000896 # mshr miss rate for overall accesses 1121system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000495 # mshr miss rate for overall accesses 1122system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010599 # mshr miss rate for overall accesses 1123system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172107 # mshr miss rate for overall accesses 1124system.cpu.l2cache.overall_mshr_miss_rate::total 0.062929 # mshr miss rate for overall accesses 1125system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 126785.714286 # average ReadReq mshr miss latency 1126system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 123000 # average ReadReq mshr miss latency 1127system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 125944.444444 # average ReadReq mshr miss latency 1128system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68032.275711 # average UpgradeReq mshr miss latency 1129system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68032.275711 # average UpgradeReq mshr miss latency 1130system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69500 # average SCUpgradeReq mshr miss latency 1131system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency 1132system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117082.280298 # average ReadExReq mshr miss latency 1133system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117082.280298 # average ReadExReq mshr miss latency 1134system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120787.212148 # average ReadCleanReq mshr miss latency 1135system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120787.212148 # average ReadCleanReq mshr miss latency 1136system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122705.372546 # average ReadSharedReq mshr miss latency 1137system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122705.372546 # average ReadSharedReq mshr miss latency 1138system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 126785.714286 # average overall mshr miss latency 1139system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 123000 # average overall mshr miss latency 1140system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120787.212148 # average overall mshr miss latency 1141system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 117567.444679 # average overall mshr miss latency 1142system.cpu.l2cache.demand_avg_mshr_miss_latency::total 117931.808038 # average overall mshr miss latency 1143system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 126785.714286 # average overall mshr miss latency 1144system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 123000 # average overall mshr miss latency 1145system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120787.212148 # average overall mshr miss latency 1146system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 117567.444679 # average overall mshr miss latency 1147system.cpu.l2cache.overall_avg_mshr_miss_latency::total 117931.808038 # average overall mshr miss latency 1148system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 114139.436932 # average ReadReq mshr uncacheable latency 1149system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189119.532404 # average ReadReq mshr uncacheable latency 1150system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 172275.149402 # average ReadReq mshr uncacheable latency 1151system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 114139.436932 # average overall mshr uncacheable latency 1152system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100274.217992 # average overall mshr uncacheable latency 1153system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 102120.621707 # average overall mshr uncacheable latency 1154system.cpu.toL2Bus.snoop_filter.tot_requests 5052863 # Total number of requests made to the snoop filter. 1155system.cpu.toL2Bus.snoop_filter.hit_single_requests 2536887 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1156system.cpu.toL2Bus.snoop_filter.hit_multi_requests 38132 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1157system.cpu.toL2Bus.snoop_filter.tot_snoops 581 # Total number of snoops made to the snoop filter. 1158system.cpu.toL2Bus.snoop_filter.hit_single_snoops 581 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1159system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1160system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 1161system.cpu.toL2Bus.trans_dist::ReadReq 67213 # Transaction distribution 1162system.cpu.toL2Bus.trans_dist::ReadResp 2287480 # Transaction distribution 1163system.cpu.toL2Bus.trans_dist::WriteReq 27589 # Transaction distribution 1164system.cpu.toL2Bus.trans_dist::WriteResp 27589 # Transaction distribution 1165system.cpu.toL2Bus.trans_dist::WritebackDirty 801231 # Transaction distribution 1166system.cpu.toL2Bus.trans_dist::WritebackClean 1695721 # Transaction distribution 1167system.cpu.toL2Bus.trans_dist::CleanEvict 141985 # Transaction distribution 1168system.cpu.toL2Bus.trans_dist::UpgradeReq 2765 # Transaction distribution 1169system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution 1170system.cpu.toL2Bus.trans_dist::UpgradeResp 2767 # Transaction distribution 1171system.cpu.toL2Bus.trans_dist::ReadExReq 295944 # Transaction distribution 1172system.cpu.toL2Bus.trans_dist::ReadExResp 295944 # Transaction distribution 1173system.cpu.toL2Bus.trans_dist::ReadCleanReq 1696239 # Transaction distribution 1174system.cpu.toL2Bus.trans_dist::ReadSharedReq 524043 # Transaction distribution 1175system.cpu.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution 1176system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5106210 # Packet count per connected master and slave (bytes) 1177system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2581942 # Packet count per connected master and slave (bytes) 1178system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 13257 # Packet count per connected master and slave (bytes) 1179system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 25651 # Packet count per connected master and slave (bytes) 1180system.cpu.toL2Bus.pkt_count::total 7727060 # Packet count per connected master and slave (bytes) 1181system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217119416 # Cumulative packet size per connected master and slave (bytes) 1182system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96427485 # Cumulative packet size per connected master and slave (bytes) 1183system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 16164 # Cumulative packet size per connected master and slave (bytes) 1184system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 31256 # Cumulative packet size per connected master and slave (bytes) 1185system.cpu.toL2Bus.pkt_size::total 313594321 # Cumulative packet size per connected master and slave (bytes) 1186system.cpu.toL2Bus.snoops 175889 # Total snoops (count) 1187system.cpu.toL2Bus.snoop_fanout::samples 2774012 # Request fanout histogram 1188system.cpu.toL2Bus.snoop_fanout::mean 0.020868 # Request fanout histogram 1189system.cpu.toL2Bus.snoop_fanout::stdev 0.142944 # Request fanout histogram 1190system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1191system.cpu.toL2Bus.snoop_fanout::0 2716123 97.91% 97.91% # Request fanout histogram 1192system.cpu.toL2Bus.snoop_fanout::1 57889 2.09% 100.00% # Request fanout histogram 1193system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1194system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1195system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1196system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 1197system.cpu.toL2Bus.snoop_fanout::total 2774012 # Request fanout histogram 1198system.cpu.toL2Bus.reqLayer0.occupancy 4957617000 # Layer occupancy (ticks) 1199system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 1200system.cpu.toL2Bus.snoopLayer0.occupancy 380377 # Layer occupancy (ticks) 1201system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1202system.cpu.toL2Bus.respLayer0.occupancy 2553380500 # Layer occupancy (ticks) 1203system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1204system.cpu.toL2Bus.respLayer1.occupancy 1275954500 # Layer occupancy (ticks) 1205system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1206system.cpu.toL2Bus.respLayer2.occupancy 9216000 # Layer occupancy (ticks) 1207system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1208system.cpu.toL2Bus.respLayer3.occupancy 17837000 # Layer occupancy (ticks) 1209system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1210system.iobus.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 1211system.iobus.trans_dist::ReadReq 30177 # Transaction distribution 1212system.iobus.trans_dist::ReadResp 30177 # Transaction distribution 1213system.iobus.trans_dist::WriteReq 59014 # Transaction distribution 1214system.iobus.trans_dist::WriteResp 59014 # Transaction distribution 1215system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) 1216system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) 1217system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 1218system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 1219system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 1220system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 1221system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 1222system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 1223system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1224system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1225system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1226system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 1227system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1228system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 1229system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 1230system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 1231system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 1232system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 1233system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 1234system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) 1235system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72904 # Packet count per connected master and slave (bytes) 1236system.iobus.pkt_count_system.realview.ide.dma::total 72904 # Packet count per connected master and slave (bytes) 1237system.iobus.pkt_count::total 178382 # Packet count per connected master and slave (bytes) 1238system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) 1239system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) 1240system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) 1241system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 1242system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 1243system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 1244system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 1245system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 1246system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1247system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1248system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1249system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 1250system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1251system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1252system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 1253system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 1254system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1255system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 1256system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 1257system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) 1258system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321056 # Cumulative packet size per connected master and slave (bytes) 1259system.iobus.pkt_size_system.realview.ide.dma::total 2321056 # Cumulative packet size per connected master and slave (bytes) 1260system.iobus.pkt_size::total 2480181 # Cumulative packet size per connected master and slave (bytes) 1261system.iobus.reqLayer0.occupancy 46336500 # Layer occupancy (ticks) 1262system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1263system.iobus.reqLayer1.occupancy 97000 # Layer occupancy (ticks) 1264system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1265system.iobus.reqLayer2.occupancy 338000 # Layer occupancy (ticks) 1266system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1267system.iobus.reqLayer3.occupancy 30000 # Layer occupancy (ticks) 1268system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1269system.iobus.reqLayer4.occupancy 16000 # Layer occupancy (ticks) 1270system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 1271system.iobus.reqLayer7.occupancy 94500 # Layer occupancy (ticks) 1272system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 1273system.iobus.reqLayer8.occupancy 644500 # Layer occupancy (ticks) 1274system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 1275system.iobus.reqLayer10.occupancy 21000 # Layer occupancy (ticks) 1276system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1277system.iobus.reqLayer13.occupancy 12000 # Layer occupancy (ticks) 1278system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1279system.iobus.reqLayer14.occupancy 11500 # Layer occupancy (ticks) 1280system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1281system.iobus.reqLayer15.occupancy 11500 # Layer occupancy (ticks) 1282system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1283system.iobus.reqLayer16.occupancy 52500 # Layer occupancy (ticks) 1284system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1285system.iobus.reqLayer17.occupancy 11500 # Layer occupancy (ticks) 1286system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1287system.iobus.reqLayer18.occupancy 12000 # Layer occupancy (ticks) 1288system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 1289system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) 1290system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 1291system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) 1292system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 1293system.iobus.reqLayer21.occupancy 12000 # Layer occupancy (ticks) 1294system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 1295system.iobus.reqLayer23.occupancy 6279500 # Layer occupancy (ticks) 1296system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1297system.iobus.reqLayer24.occupancy 36469500 # Layer occupancy (ticks) 1298system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1299system.iobus.reqLayer25.occupancy 187058527 # Layer occupancy (ticks) 1300system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1301system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) 1302system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1303system.iobus.respLayer3.occupancy 36728000 # Layer occupancy (ticks) 1304system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 1305system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 1306system.iocache.tags.replacements 36418 # number of replacements 1307system.iocache.tags.tagsinuse 1.084082 # Cycle average of tags in use 1308system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1309system.iocache.tags.sampled_refs 36434 # Sample count of references to valid blocks. 1310system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1311system.iocache.tags.warmup_cycle 313812610000 # Cycle when the warmup percentage was hit. 1312system.iocache.tags.occ_blocks::realview.ide 1.084082 # Average occupied blocks per requestor 1313system.iocache.tags.occ_percent::realview.ide 0.067755 # Average percentage of cache occupancy 1314system.iocache.tags.occ_percent::total 0.067755 # Average percentage of cache occupancy 1315system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1316system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1317system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1318system.iocache.tags.tag_accesses 328068 # Number of tag accesses 1319system.iocache.tags.data_accesses 328068 # Number of data accesses 1320system.iocache.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 1321system.iocache.ReadReq_misses::realview.ide 228 # number of ReadReq misses 1322system.iocache.ReadReq_misses::total 228 # number of ReadReq misses 1323system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 1324system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 1325system.iocache.demand_misses::realview.ide 36452 # number of demand (read+write) misses 1326system.iocache.demand_misses::total 36452 # number of demand (read+write) misses 1327system.iocache.overall_misses::realview.ide 36452 # number of overall misses 1328system.iocache.overall_misses::total 36452 # number of overall misses 1329system.iocache.ReadReq_miss_latency::realview.ide 28180377 # number of ReadReq miss cycles 1330system.iocache.ReadReq_miss_latency::total 28180377 # number of ReadReq miss cycles 1331system.iocache.WriteLineReq_miss_latency::realview.ide 4549133150 # number of WriteLineReq miss cycles 1332system.iocache.WriteLineReq_miss_latency::total 4549133150 # number of WriteLineReq miss cycles 1333system.iocache.demand_miss_latency::realview.ide 4577313527 # number of demand (read+write) miss cycles 1334system.iocache.demand_miss_latency::total 4577313527 # number of demand (read+write) miss cycles 1335system.iocache.overall_miss_latency::realview.ide 4577313527 # number of overall miss cycles 1336system.iocache.overall_miss_latency::total 4577313527 # number of overall miss cycles 1337system.iocache.ReadReq_accesses::realview.ide 228 # number of ReadReq accesses(hits+misses) 1338system.iocache.ReadReq_accesses::total 228 # number of ReadReq accesses(hits+misses) 1339system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 1340system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) 1341system.iocache.demand_accesses::realview.ide 36452 # number of demand (read+write) accesses 1342system.iocache.demand_accesses::total 36452 # number of demand (read+write) accesses 1343system.iocache.overall_accesses::realview.ide 36452 # number of overall (read+write) accesses 1344system.iocache.overall_accesses::total 36452 # number of overall (read+write) accesses 1345system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1346system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1347system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1348system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1349system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1350system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1351system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1352system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1353system.iocache.ReadReq_avg_miss_latency::realview.ide 123598.144737 # average ReadReq miss latency 1354system.iocache.ReadReq_avg_miss_latency::total 123598.144737 # average ReadReq miss latency 1355system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125583.401888 # average WriteLineReq miss latency 1356system.iocache.WriteLineReq_avg_miss_latency::total 125583.401888 # average WriteLineReq miss latency 1357system.iocache.demand_avg_miss_latency::realview.ide 125570.984500 # average overall miss latency 1358system.iocache.demand_avg_miss_latency::total 125570.984500 # average overall miss latency 1359system.iocache.overall_avg_miss_latency::realview.ide 125570.984500 # average overall miss latency 1360system.iocache.overall_avg_miss_latency::total 125570.984500 # average overall miss latency 1361system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1362system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1363system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1364system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1365system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1366system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1367system.iocache.writebacks::writebacks 36190 # number of writebacks 1368system.iocache.writebacks::total 36190 # number of writebacks 1369system.iocache.ReadReq_mshr_misses::realview.ide 228 # number of ReadReq MSHR misses 1370system.iocache.ReadReq_mshr_misses::total 228 # number of ReadReq MSHR misses 1371system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses 1372system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses 1373system.iocache.demand_mshr_misses::realview.ide 36452 # number of demand (read+write) MSHR misses 1374system.iocache.demand_mshr_misses::total 36452 # number of demand (read+write) MSHR misses 1375system.iocache.overall_mshr_misses::realview.ide 36452 # number of overall MSHR misses 1376system.iocache.overall_mshr_misses::total 36452 # number of overall MSHR misses 1377system.iocache.ReadReq_mshr_miss_latency::realview.ide 16780377 # number of ReadReq MSHR miss cycles 1378system.iocache.ReadReq_mshr_miss_latency::total 16780377 # number of ReadReq MSHR miss cycles 1379system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2736521626 # number of WriteLineReq MSHR miss cycles 1380system.iocache.WriteLineReq_mshr_miss_latency::total 2736521626 # number of WriteLineReq MSHR miss cycles 1381system.iocache.demand_mshr_miss_latency::realview.ide 2753302003 # number of demand (read+write) MSHR miss cycles 1382system.iocache.demand_mshr_miss_latency::total 2753302003 # number of demand (read+write) MSHR miss cycles 1383system.iocache.overall_mshr_miss_latency::realview.ide 2753302003 # number of overall MSHR miss cycles 1384system.iocache.overall_mshr_miss_latency::total 2753302003 # number of overall MSHR miss cycles 1385system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1386system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1387system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 1388system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1389system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1390system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1391system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1392system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1393system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73598.144737 # average ReadReq mshr miss latency 1394system.iocache.ReadReq_avg_mshr_miss_latency::total 73598.144737 # average ReadReq mshr miss latency 1395system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75544.435347 # average WriteLineReq mshr miss latency 1396system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75544.435347 # average WriteLineReq mshr miss latency 1397system.iocache.demand_avg_mshr_miss_latency::realview.ide 75532.261687 # average overall mshr miss latency 1398system.iocache.demand_avg_mshr_miss_latency::total 75532.261687 # average overall mshr miss latency 1399system.iocache.overall_avg_mshr_miss_latency::realview.ide 75532.261687 # average overall mshr miss latency 1400system.iocache.overall_avg_mshr_miss_latency::total 75532.261687 # average overall mshr miss latency 1401system.membus.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 1402system.membus.trans_dist::ReadReq 40160 # Transaction distribution 1403system.membus.trans_dist::ReadResp 70548 # Transaction distribution 1404system.membus.trans_dist::WriteReq 27589 # Transaction distribution 1405system.membus.trans_dist::WriteResp 27589 # Transaction distribution 1406system.membus.trans_dist::WritebackDirty 117375 # Transaction distribution 1407system.membus.trans_dist::CleanEvict 6608 # Transaction distribution 1408system.membus.trans_dist::UpgradeReq 4497 # Transaction distribution 1409system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution 1410system.membus.trans_dist::UpgradeResp 2 # Transaction distribution 1411system.membus.trans_dist::ReadExReq 127158 # Transaction distribution 1412system.membus.trans_dist::ReadExResp 127158 # Transaction distribution 1413system.membus.trans_dist::ReadSharedReq 30388 # Transaction distribution 1414system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 1415system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) 1416system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) 1417system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes) 1418system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 434329 # Packet count per connected master and slave (bytes) 1419system.membus.pkt_count_system.cpu.l2cache.mem_side::total 541921 # Packet count per connected master and slave (bytes) 1420system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72885 # Packet count per connected master and slave (bytes) 1421system.membus.pkt_count_system.iocache.mem_side::total 72885 # Packet count per connected master and slave (bytes) 1422system.membus.pkt_count::total 614806 # Packet count per connected master and slave (bytes) 1423system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) 1424system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) 1425system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes) 1426system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15302332 # Cumulative packet size per connected master and slave (bytes) 1427system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15465685 # Cumulative packet size per connected master and slave (bytes) 1428system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) 1429system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) 1430system.membus.pkt_size::total 17782805 # Cumulative packet size per connected master and slave (bytes) 1431system.membus.snoops 492 # Total snoops (count) 1432system.membus.snoop_fanout::samples 390011 # Request fanout histogram 1433system.membus.snoop_fanout::mean 1 # Request fanout histogram 1434system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1435system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1436system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1437system.membus.snoop_fanout::1 390011 100.00% 100.00% # Request fanout histogram 1438system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1439system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1440system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1441system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1442system.membus.snoop_fanout::total 390011 # Request fanout histogram 1443system.membus.reqLayer0.occupancy 90460500 # Layer occupancy (ticks) 1444system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1445system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) 1446system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1447system.membus.reqLayer2.occupancy 1730500 # Layer occupancy (ticks) 1448system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1449system.membus.reqLayer5.occupancy 823136860 # Layer occupancy (ticks) 1450system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 1451system.membus.respLayer2.occupancy 943248500 # Layer occupancy (ticks) 1452system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1453system.membus.respLayer3.occupancy 1186623 # Layer occupancy (ticks) 1454system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 1455system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 1456system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 1457system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 1458system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 1459system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 1460system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 1461system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 1462system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1463system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1464system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1465system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1466system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1467system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 1468system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 1469system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 1470system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1471system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1472system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1473system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1474system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1475system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1476system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1477system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1478system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 1479system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1480system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1481system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 1482system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1483system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1484system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 1485system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1486system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1487system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 1488system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1489system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1490system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 1491system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1492system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1493system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1494system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1495system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1496system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1497system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1498system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1499system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 1500system.realview.ethernet.droppedPackets 0 # number of packets dropped 1501system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 1502system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 1503system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 1504system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 1505system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 1506system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 1507system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 1508system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 1509system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 1510system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 1511system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 1512system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 1513system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 1514system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 1515system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 1516system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 1517system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 1518system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 1519system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 1520system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 1521system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 1522system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 1523system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 1524 1525---------- End Simulation Statistics ---------- 1526