stats.txt revision 10585:1c9d5d9417b3
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.902845 # Number of seconds simulated 4sim_ticks 2902845442000 # Number of ticks simulated 5final_tick 2902845442000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 666753 # Simulator instruction rate (inst/s) 8host_op_rate 803907 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 17201244826 # Simulator tick rate (ticks/s) 10host_mem_usage 558784 # Number of bytes of host memory used 11host_seconds 168.76 # Real time elapsed on the host 12sim_insts 112519801 # Number of instructions simulated 13sim_ops 135665611 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 1190500 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 8985828 # Number of bytes read from this memory 20system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 21system.physmem.bytes_read::total 10177864 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 1190500 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 1190500 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 7575744 # Number of bytes written to this memory 25system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory 26system.physmem.bytes_written::total 7593268 # Number of bytes written to this memory 27system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.inst 27055 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.data 140923 # Number of read requests responded to by this memory 31system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 32system.physmem.num_reads::total 168002 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 118371 # Number of write requests responded to by this memory 34system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory 35system.physmem.num_writes::total 122752 # Number of write requests responded to by this memory 36system.physmem.bw_read::cpu.dtb.walker 154 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.itb.walker 44 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.inst 410115 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.data 3095524 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::total 3506168 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 410115 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 410115 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 2609765 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::cpu.data 6037 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 2615802 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 2609765 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.itb.walker 44 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.inst 410115 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.data 3101561 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::realview.ide 331 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::total 6121970 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.readReqs 168002 # Number of read requests accepted 55system.physmem.writeReqs 158976 # Number of write requests accepted 56system.physmem.readBursts 168002 # Number of DRAM read bursts, including those serviced by the write queue 57system.physmem.writeBursts 158976 # Number of DRAM write bursts, including those merged in the write queue 58system.physmem.bytesReadDRAM 10744064 # Total number of bytes read from DRAM 59system.physmem.bytesReadWrQ 8064 # Total number of bytes read from write queue 60system.physmem.bytesWritten 9803776 # Total number of bytes written to DRAM 61system.physmem.bytesReadSys 10177864 # Total read bytes from the system interface side 62system.physmem.bytesWrittenSys 9911604 # Total written bytes from the system interface side 63system.physmem.servicedByWrQ 126 # Number of DRAM read bursts serviced by the write queue 64system.physmem.mergedWrBursts 5765 # Number of DRAM write bursts merged with an existing one 65system.physmem.neitherReadNorWriteReqs 4503 # Number of requests that are neither read nor write 66system.physmem.perBankRdBursts::0 9689 # Per bank write bursts 67system.physmem.perBankRdBursts::1 9233 # Per bank write bursts 68system.physmem.perBankRdBursts::2 10196 # Per bank write bursts 69system.physmem.perBankRdBursts::3 10261 # Per bank write bursts 70system.physmem.perBankRdBursts::4 18984 # Per bank write bursts 71system.physmem.perBankRdBursts::5 10217 # Per bank write bursts 72system.physmem.perBankRdBursts::6 10550 # Per bank write bursts 73system.physmem.perBankRdBursts::7 10349 # Per bank write bursts 74system.physmem.perBankRdBursts::8 9691 # Per bank write bursts 75system.physmem.perBankRdBursts::9 9930 # Per bank write bursts 76system.physmem.perBankRdBursts::10 9906 # Per bank write bursts 77system.physmem.perBankRdBursts::11 8846 # Per bank write bursts 78system.physmem.perBankRdBursts::12 9937 # Per bank write bursts 79system.physmem.perBankRdBursts::13 10409 # Per bank write bursts 80system.physmem.perBankRdBursts::14 9928 # Per bank write bursts 81system.physmem.perBankRdBursts::15 9750 # Per bank write bursts 82system.physmem.perBankWrBursts::0 9383 # Per bank write bursts 83system.physmem.perBankWrBursts::1 8873 # Per bank write bursts 84system.physmem.perBankWrBursts::2 10202 # Per bank write bursts 85system.physmem.perBankWrBursts::3 10003 # Per bank write bursts 86system.physmem.perBankWrBursts::4 9293 # Per bank write bursts 87system.physmem.perBankWrBursts::5 9372 # Per bank write bursts 88system.physmem.perBankWrBursts::6 9902 # Per bank write bursts 89system.physmem.perBankWrBursts::7 9747 # Per bank write bursts 90system.physmem.perBankWrBursts::8 9662 # Per bank write bursts 91system.physmem.perBankWrBursts::9 9936 # Per bank write bursts 92system.physmem.perBankWrBursts::10 9764 # Per bank write bursts 93system.physmem.perBankWrBursts::11 9057 # Per bank write bursts 94system.physmem.perBankWrBursts::12 9756 # Per bank write bursts 95system.physmem.perBankWrBursts::13 9847 # Per bank write bursts 96system.physmem.perBankWrBursts::14 9332 # Per bank write bursts 97system.physmem.perBankWrBursts::15 9055 # Per bank write bursts 98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 99system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 100system.physmem.totGap 2902845065500 # Total gap between requests 101system.physmem.readPktSize::0 0 # Read request sizes (log2) 102system.physmem.readPktSize::1 0 # Read request sizes (log2) 103system.physmem.readPktSize::2 9558 # Read request sizes (log2) 104system.physmem.readPktSize::3 14 # Read request sizes (log2) 105system.physmem.readPktSize::4 0 # Read request sizes (log2) 106system.physmem.readPktSize::5 0 # Read request sizes (log2) 107system.physmem.readPktSize::6 158430 # Read request sizes (log2) 108system.physmem.writePktSize::0 0 # Write request sizes (log2) 109system.physmem.writePktSize::1 0 # Write request sizes (log2) 110system.physmem.writePktSize::2 4381 # Write request sizes (log2) 111system.physmem.writePktSize::3 0 # Write request sizes (log2) 112system.physmem.writePktSize::4 0 # Write request sizes (log2) 113system.physmem.writePktSize::5 0 # Write request sizes (log2) 114system.physmem.writePktSize::6 154595 # Write request sizes (log2) 115system.physmem.rdQLenPdf::0 167074 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::1 546 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::2 244 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 147system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::15 2275 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::16 4010 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::17 7794 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::18 8553 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::19 8920 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::20 9728 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::21 10123 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::22 10886 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::23 10725 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::24 11224 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::25 10377 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::26 9848 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::27 8741 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::28 8288 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::29 7158 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::30 6857 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::31 6734 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::32 6646 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::33 405 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::34 375 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::35 354 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::36 282 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::37 258 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::38 268 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::39 258 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::40 239 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::41 224 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::42 214 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::43 188 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::44 176 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::45 166 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::46 149 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::47 135 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::48 130 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::49 110 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::50 96 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::51 82 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::52 62 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::53 48 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::54 34 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::55 20 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::56 14 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::57 9 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::58 8 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::59 3 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::60 1 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::61 1 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 211system.physmem.bytesPerActivate::samples 60629 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::mean 338.910027 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::gmean 195.312314 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::stdev 353.501529 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::0-127 21458 35.39% 35.39% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::128-255 14532 23.97% 59.36% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::256-383 5550 9.15% 68.52% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::384-511 3471 5.72% 74.24% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::512-639 2318 3.82% 78.06% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::640-767 1576 2.60% 80.66% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::768-895 1018 1.68% 82.34% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::896-1023 1077 1.78% 84.12% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1024-1151 9629 15.88% 100.00% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::total 60629 # Bytes accessed per row activation 225system.physmem.rdPerTurnAround::samples 6199 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::mean 27.078561 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::stdev 543.579220 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::0-2047 6197 99.97% 99.97% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::total 6199 # Reads before turning the bus around for writes 232system.physmem.wrPerTurnAround::samples 6199 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::mean 24.711082 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::gmean 20.355367 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::stdev 23.633562 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::16-23 5127 82.71% 82.71% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::24-31 245 3.95% 86.66% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::32-39 162 2.61% 89.27% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::40-47 57 0.92% 90.19% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::48-55 142 2.29% 92.48% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::56-63 31 0.50% 92.98% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::64-71 44 0.71% 93.69% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::72-79 53 0.85% 94.55% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::80-87 77 1.24% 95.79% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::88-95 20 0.32% 96.11% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::96-103 101 1.63% 97.74% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::104-111 12 0.19% 97.94% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::112-119 30 0.48% 98.42% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::120-127 13 0.21% 98.63% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::128-135 38 0.61% 99.24% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::136-143 11 0.18% 99.42% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::144-151 15 0.24% 99.66% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::152-159 2 0.03% 99.69% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::160-167 3 0.05% 99.74% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::168-175 2 0.03% 99.77% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::176-183 3 0.05% 99.82% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::192-199 2 0.03% 99.85% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::200-207 1 0.02% 99.87% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::208-215 2 0.03% 99.90% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::216-223 2 0.03% 99.94% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::224-231 3 0.05% 99.98% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::272-279 1 0.02% 100.00% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::total 6199 # Writes before turning the bus around for reads 264system.physmem.totQLat 1496514000 # Total ticks spent queuing 265system.physmem.totMemAccLat 4644189000 # Total ticks spent from burst creation until serviced by the DRAM 266system.physmem.totBusLat 839380000 # Total ticks spent in databus transfers 267system.physmem.avgQLat 8914.40 # Average queueing delay per DRAM burst 268system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 269system.physmem.avgMemAccLat 27664.40 # Average memory access latency per DRAM burst 270system.physmem.avgRdBW 3.70 # Average DRAM read bandwidth in MiByte/s 271system.physmem.avgWrBW 3.38 # Average achieved write bandwidth in MiByte/s 272system.physmem.avgRdBWSys 3.51 # Average system read bandwidth in MiByte/s 273system.physmem.avgWrBWSys 3.41 # Average system write bandwidth in MiByte/s 274system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 275system.physmem.busUtil 0.06 # Data bus utilization in percentage 276system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 277system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 278system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 279system.physmem.avgWrQLen 27.52 # Average write queue length when enqueuing 280system.physmem.readRowHits 138272 # Number of row buffer hits during reads 281system.physmem.writeRowHits 122158 # Number of row buffer hits during writes 282system.physmem.readRowHitRate 82.37 # Row buffer hit rate for reads 283system.physmem.writeRowHitRate 79.73 # Row buffer hit rate for writes 284system.physmem.avgGap 8877799.32 # Average gap between requests 285system.physmem.pageHitRate 81.11 # Row buffer hit rate, read and write combined 286system.physmem.memoryStateTime::IDLE 2755332461750 # Time in different power states 287system.physmem.memoryStateTime::REF 96932160000 # Time in different power states 288system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 289system.physmem.memoryStateTime::ACT 50580729750 # Time in different power states 290system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 291system.physmem.actEnergy::0 234216360 # Energy for activate commands per rank (pJ) 292system.physmem.actEnergy::1 224138880 # Energy for activate commands per rank (pJ) 293system.physmem.preEnergy::0 127796625 # Energy for precharge commands per rank (pJ) 294system.physmem.preEnergy::1 122298000 # Energy for precharge commands per rank (pJ) 295system.physmem.readEnergy::0 697936200 # Energy for read commands per rank (pJ) 296system.physmem.readEnergy::1 611488800 # Energy for read commands per rank (pJ) 297system.physmem.writeEnergy::0 497502000 # Energy for write commands per rank (pJ) 298system.physmem.writeEnergy::1 495130320 # Energy for write commands per rank (pJ) 299system.physmem.refreshEnergy::0 189599304960 # Energy for refresh commands per rank (pJ) 300system.physmem.refreshEnergy::1 189599304960 # Energy for refresh commands per rank (pJ) 301system.physmem.actBackEnergy::0 86744243025 # Energy for active background per rank (pJ) 302system.physmem.actBackEnergy::1 85632450615 # Energy for active background per rank (pJ) 303system.physmem.preBackEnergy::0 1665611854500 # Energy for precharge background per rank (pJ) 304system.physmem.preBackEnergy::1 1666587111000 # Energy for precharge background per rank (pJ) 305system.physmem.totalEnergy::0 1943512853670 # Total energy per rank (pJ) 306system.physmem.totalEnergy::1 1943271922575 # Total energy per rank (pJ) 307system.physmem.averagePower::0 669.521448 # Core power per rank (mW) 308system.physmem.averagePower::1 669.438449 # Core power per rank (mW) 309system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory 310system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory 311system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory 312system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory 313system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory 314system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory 315system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s) 316system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s) 317system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s) 318system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) 319system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) 320system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) 321system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 322system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 323system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 324system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 325system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 326system.cf0.dma_write_txs 631 # Number of DMA write transactions. 327system.cpu_clk_domain.clock 500 # Clock period in ticks 328system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 329system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 330system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 331system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 332system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 333system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 334system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 335system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 336system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 337system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 338system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 339system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 340system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 341system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 342system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 343system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 344system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 345system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 346system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 347system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 348system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 349system.cpu.dtb.inst_hits 0 # ITB inst hits 350system.cpu.dtb.inst_misses 0 # ITB inst misses 351system.cpu.dtb.read_hits 24536392 # DTB read hits 352system.cpu.dtb.read_misses 8144 # DTB read misses 353system.cpu.dtb.write_hits 19617454 # DTB write hits 354system.cpu.dtb.write_misses 1410 # DTB write misses 355system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 356system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 357system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 358system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 359system.cpu.dtb.flush_entries 4273 # Number of entries that have been flushed from TLB 360system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 361system.cpu.dtb.prefetch_faults 1630 # Number of TLB faults due to prefetch 362system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 363system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions 364system.cpu.dtb.read_accesses 24544536 # DTB read accesses 365system.cpu.dtb.write_accesses 19618864 # DTB write accesses 366system.cpu.dtb.inst_accesses 0 # ITB inst accesses 367system.cpu.dtb.hits 44153846 # DTB hits 368system.cpu.dtb.misses 9554 # DTB misses 369system.cpu.dtb.accesses 44163400 # DTB accesses 370system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 371system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 372system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 373system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 374system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 375system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 376system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 377system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 378system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 379system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 380system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 381system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 382system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 383system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 384system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 385system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 386system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 387system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 388system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 389system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 390system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 391system.cpu.itb.inst_hits 115618887 # ITB inst hits 392system.cpu.itb.inst_misses 4762 # ITB inst misses 393system.cpu.itb.read_hits 0 # DTB read hits 394system.cpu.itb.read_misses 0 # DTB read misses 395system.cpu.itb.write_hits 0 # DTB write hits 396system.cpu.itb.write_misses 0 # DTB write misses 397system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 398system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 399system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 400system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 401system.cpu.itb.flush_entries 2913 # Number of entries that have been flushed from TLB 402system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 403system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 404system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 405system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 406system.cpu.itb.read_accesses 0 # DTB read accesses 407system.cpu.itb.write_accesses 0 # DTB write accesses 408system.cpu.itb.inst_accesses 115623649 # ITB inst accesses 409system.cpu.itb.hits 115618887 # DTB hits 410system.cpu.itb.misses 4762 # DTB misses 411system.cpu.itb.accesses 115623649 # DTB accesses 412system.cpu.numCycles 5805690884 # number of cpu cycles simulated 413system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 414system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 415system.cpu.committedInsts 112519801 # Number of instructions committed 416system.cpu.committedOps 135665611 # Number of ops (including micro ops) committed 417system.cpu.num_int_alu_accesses 119963928 # Number of integer alu accesses 418system.cpu.num_fp_alu_accesses 11290 # Number of float alu accesses 419system.cpu.num_func_calls 9899743 # number of times a function call or return occured 420system.cpu.num_conditional_control_insts 15237612 # number of instructions that are conditional controls 421system.cpu.num_int_insts 119963928 # number of integer instructions 422system.cpu.num_fp_insts 11290 # number of float instructions 423system.cpu.num_int_register_reads 218192496 # number of times the integer registers were read 424system.cpu.num_int_register_writes 82697523 # number of times the integer registers were written 425system.cpu.num_fp_register_reads 8578 # number of times the floating registers were read 426system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written 427system.cpu.num_cc_register_reads 490031044 # number of times the CC registers were read 428system.cpu.num_cc_register_writes 51919223 # number of times the CC registers were written 429system.cpu.num_mem_refs 45435185 # number of memory refs 430system.cpu.num_load_insts 24859277 # Number of load instructions 431system.cpu.num_store_insts 20575908 # Number of store instructions 432system.cpu.num_idle_cycles 5386811452.570145 # Number of idle cycles 433system.cpu.num_busy_cycles 418879431.429856 # Number of busy cycles 434system.cpu.not_idle_fraction 0.072150 # Percentage of non-idle cycles 435system.cpu.idle_fraction 0.927850 # Percentage of idle cycles 436system.cpu.Branches 25931479 # Number of branches fetched 437system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction 438system.cpu.op_class::IntAlu 93227451 67.17% 67.17% # Class of executed instruction 439system.cpu.op_class::IntMult 114534 0.08% 67.26% # Class of executed instruction 440system.cpu.op_class::IntDiv 0 0.00% 67.26% # Class of executed instruction 441system.cpu.op_class::FloatAdd 0 0.00% 67.26% # Class of executed instruction 442system.cpu.op_class::FloatCmp 0 0.00% 67.26% # Class of executed instruction 443system.cpu.op_class::FloatCvt 0 0.00% 67.26% # Class of executed instruction 444system.cpu.op_class::FloatMult 0 0.00% 67.26% # Class of executed instruction 445system.cpu.op_class::FloatDiv 0 0.00% 67.26% # Class of executed instruction 446system.cpu.op_class::FloatSqrt 0 0.00% 67.26% # Class of executed instruction 447system.cpu.op_class::SimdAdd 0 0.00% 67.26% # Class of executed instruction 448system.cpu.op_class::SimdAddAcc 0 0.00% 67.26% # Class of executed instruction 449system.cpu.op_class::SimdAlu 0 0.00% 67.26% # Class of executed instruction 450system.cpu.op_class::SimdCmp 0 0.00% 67.26% # Class of executed instruction 451system.cpu.op_class::SimdCvt 0 0.00% 67.26% # Class of executed instruction 452system.cpu.op_class::SimdMisc 0 0.00% 67.26% # Class of executed instruction 453system.cpu.op_class::SimdMult 0 0.00% 67.26% # Class of executed instruction 454system.cpu.op_class::SimdMultAcc 0 0.00% 67.26% # Class of executed instruction 455system.cpu.op_class::SimdShift 0 0.00% 67.26% # Class of executed instruction 456system.cpu.op_class::SimdShiftAcc 0 0.00% 67.26% # Class of executed instruction 457system.cpu.op_class::SimdSqrt 0 0.00% 67.26% # Class of executed instruction 458system.cpu.op_class::SimdFloatAdd 0 0.00% 67.26% # Class of executed instruction 459system.cpu.op_class::SimdFloatAlu 0 0.00% 67.26% # Class of executed instruction 460system.cpu.op_class::SimdFloatCmp 0 0.00% 67.26% # Class of executed instruction 461system.cpu.op_class::SimdFloatCvt 0 0.00% 67.26% # Class of executed instruction 462system.cpu.op_class::SimdFloatDiv 0 0.00% 67.26% # Class of executed instruction 463system.cpu.op_class::SimdFloatMisc 8511 0.01% 67.26% # Class of executed instruction 464system.cpu.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction 465system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction 466system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction 467system.cpu.op_class::MemRead 24859277 17.91% 85.17% # Class of executed instruction 468system.cpu.op_class::MemWrite 20575908 14.83% 100.00% # Class of executed instruction 469system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 470system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 471system.cpu.op_class::total 138788018 # Class of executed instruction 472system.cpu.kern.inst.arm 0 # number of arm instructions executed 473system.cpu.kern.inst.quiesce 3037 # number of quiesce instructions executed 474system.cpu.dcache.tags.replacements 823273 # number of replacements 475system.cpu.dcache.tags.tagsinuse 511.850546 # Cycle average of tags in use 476system.cpu.dcache.tags.total_refs 43258722 # Total number of references to valid blocks. 477system.cpu.dcache.tags.sampled_refs 823785 # Sample count of references to valid blocks. 478system.cpu.dcache.tags.avg_refs 52.512151 # Average number of references to valid blocks. 479system.cpu.dcache.tags.warmup_cycle 876905250 # Cycle when the warmup percentage was hit. 480system.cpu.dcache.tags.occ_blocks::cpu.data 511.850546 # Average occupied blocks per requestor 481system.cpu.dcache.tags.occ_percent::cpu.data 0.999708 # Average percentage of cache occupancy 482system.cpu.dcache.tags.occ_percent::total 0.999708 # Average percentage of cache occupancy 483system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 484system.cpu.dcache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id 485system.cpu.dcache.tags.age_task_id_blocks_1024::1 368 # Occupied blocks per task id 486system.cpu.dcache.tags.age_task_id_blocks_1024::2 82 # Occupied blocks per task id 487system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 488system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 489system.cpu.dcache.tags.tag_accesses 177222055 # Number of tag accesses 490system.cpu.dcache.tags.data_accesses 177222055 # Number of data accesses 491system.cpu.dcache.ReadReq_hits::cpu.data 23125535 # number of ReadReq hits 492system.cpu.dcache.ReadReq_hits::total 23125535 # number of ReadReq hits 493system.cpu.dcache.WriteReq_hits::cpu.data 18834160 # number of WriteReq hits 494system.cpu.dcache.WriteReq_hits::total 18834160 # number of WriteReq hits 495system.cpu.dcache.SoftPFReq_hits::cpu.data 392158 # number of SoftPFReq hits 496system.cpu.dcache.SoftPFReq_hits::total 392158 # number of SoftPFReq hits 497system.cpu.dcache.LoadLockedReq_hits::cpu.data 443620 # number of LoadLockedReq hits 498system.cpu.dcache.LoadLockedReq_hits::total 443620 # number of LoadLockedReq hits 499system.cpu.dcache.StoreCondReq_hits::cpu.data 460509 # number of StoreCondReq hits 500system.cpu.dcache.StoreCondReq_hits::total 460509 # number of StoreCondReq hits 501system.cpu.dcache.demand_hits::cpu.data 41959695 # number of demand (read+write) hits 502system.cpu.dcache.demand_hits::total 41959695 # number of demand (read+write) hits 503system.cpu.dcache.overall_hits::cpu.data 42351853 # number of overall hits 504system.cpu.dcache.overall_hits::total 42351853 # number of overall hits 505system.cpu.dcache.ReadReq_misses::cpu.data 402606 # number of ReadReq misses 506system.cpu.dcache.ReadReq_misses::total 402606 # number of ReadReq misses 507system.cpu.dcache.WriteReq_misses::cpu.data 299098 # number of WriteReq misses 508system.cpu.dcache.WriteReq_misses::total 299098 # number of WriteReq misses 509system.cpu.dcache.SoftPFReq_misses::cpu.data 119172 # number of SoftPFReq misses 510system.cpu.dcache.SoftPFReq_misses::total 119172 # number of SoftPFReq misses 511system.cpu.dcache.LoadLockedReq_misses::cpu.data 22698 # number of LoadLockedReq misses 512system.cpu.dcache.LoadLockedReq_misses::total 22698 # number of LoadLockedReq misses 513system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses 514system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses 515system.cpu.dcache.demand_misses::cpu.data 701704 # number of demand (read+write) misses 516system.cpu.dcache.demand_misses::total 701704 # number of demand (read+write) misses 517system.cpu.dcache.overall_misses::cpu.data 820876 # number of overall misses 518system.cpu.dcache.overall_misses::total 820876 # number of overall misses 519system.cpu.dcache.ReadReq_miss_latency::cpu.data 5915644250 # number of ReadReq miss cycles 520system.cpu.dcache.ReadReq_miss_latency::total 5915644250 # number of ReadReq miss cycles 521system.cpu.dcache.WriteReq_miss_latency::cpu.data 11659723253 # number of WriteReq miss cycles 522system.cpu.dcache.WriteReq_miss_latency::total 11659723253 # number of WriteReq miss cycles 523system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 280150250 # number of LoadLockedReq miss cycles 524system.cpu.dcache.LoadLockedReq_miss_latency::total 280150250 # number of LoadLockedReq miss cycles 525system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 150000 # number of StoreCondReq miss cycles 526system.cpu.dcache.StoreCondReq_miss_latency::total 150000 # number of StoreCondReq miss cycles 527system.cpu.dcache.demand_miss_latency::cpu.data 17575367503 # number of demand (read+write) miss cycles 528system.cpu.dcache.demand_miss_latency::total 17575367503 # number of demand (read+write) miss cycles 529system.cpu.dcache.overall_miss_latency::cpu.data 17575367503 # number of overall miss cycles 530system.cpu.dcache.overall_miss_latency::total 17575367503 # number of overall miss cycles 531system.cpu.dcache.ReadReq_accesses::cpu.data 23528141 # number of ReadReq accesses(hits+misses) 532system.cpu.dcache.ReadReq_accesses::total 23528141 # number of ReadReq accesses(hits+misses) 533system.cpu.dcache.WriteReq_accesses::cpu.data 19133258 # number of WriteReq accesses(hits+misses) 534system.cpu.dcache.WriteReq_accesses::total 19133258 # number of WriteReq accesses(hits+misses) 535system.cpu.dcache.SoftPFReq_accesses::cpu.data 511330 # number of SoftPFReq accesses(hits+misses) 536system.cpu.dcache.SoftPFReq_accesses::total 511330 # number of SoftPFReq accesses(hits+misses) 537system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466318 # number of LoadLockedReq accesses(hits+misses) 538system.cpu.dcache.LoadLockedReq_accesses::total 466318 # number of LoadLockedReq accesses(hits+misses) 539system.cpu.dcache.StoreCondReq_accesses::cpu.data 460511 # number of StoreCondReq accesses(hits+misses) 540system.cpu.dcache.StoreCondReq_accesses::total 460511 # number of StoreCondReq accesses(hits+misses) 541system.cpu.dcache.demand_accesses::cpu.data 42661399 # number of demand (read+write) accesses 542system.cpu.dcache.demand_accesses::total 42661399 # number of demand (read+write) accesses 543system.cpu.dcache.overall_accesses::cpu.data 43172729 # number of overall (read+write) accesses 544system.cpu.dcache.overall_accesses::total 43172729 # number of overall (read+write) accesses 545system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017112 # miss rate for ReadReq accesses 546system.cpu.dcache.ReadReq_miss_rate::total 0.017112 # miss rate for ReadReq accesses 547system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015632 # miss rate for WriteReq accesses 548system.cpu.dcache.WriteReq_miss_rate::total 0.015632 # miss rate for WriteReq accesses 549system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.233063 # miss rate for SoftPFReq accesses 550system.cpu.dcache.SoftPFReq_miss_rate::total 0.233063 # miss rate for SoftPFReq accesses 551system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048675 # miss rate for LoadLockedReq accesses 552system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048675 # miss rate for LoadLockedReq accesses 553system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses 554system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses 555system.cpu.dcache.demand_miss_rate::cpu.data 0.016448 # miss rate for demand accesses 556system.cpu.dcache.demand_miss_rate::total 0.016448 # miss rate for demand accesses 557system.cpu.dcache.overall_miss_rate::cpu.data 0.019014 # miss rate for overall accesses 558system.cpu.dcache.overall_miss_rate::total 0.019014 # miss rate for overall accesses 559system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14693.383233 # average ReadReq miss latency 560system.cpu.dcache.ReadReq_avg_miss_latency::total 14693.383233 # average ReadReq miss latency 561system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38982.952922 # average WriteReq miss latency 562system.cpu.dcache.WriteReq_avg_miss_latency::total 38982.952922 # average WriteReq miss latency 563system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12342.508150 # average LoadLockedReq miss latency 564system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12342.508150 # average LoadLockedReq miss latency 565system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 75000 # average StoreCondReq miss latency 566system.cpu.dcache.StoreCondReq_avg_miss_latency::total 75000 # average StoreCondReq miss latency 567system.cpu.dcache.demand_avg_miss_latency::cpu.data 25046.697045 # average overall miss latency 568system.cpu.dcache.demand_avg_miss_latency::total 25046.697045 # average overall miss latency 569system.cpu.dcache.overall_avg_miss_latency::cpu.data 21410.502321 # average overall miss latency 570system.cpu.dcache.overall_avg_miss_latency::total 21410.502321 # average overall miss latency 571system.cpu.dcache.blocked_cycles::no_mshrs 58 # number of cycles access was blocked 572system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 573system.cpu.dcache.blocked::no_mshrs 33 # number of cycles access was blocked 574system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 575system.cpu.dcache.avg_blocked_cycles::no_mshrs 1.757576 # average number of cycles each access was blocked 576system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 577system.cpu.dcache.fast_writes 0 # number of fast writes performed 578system.cpu.dcache.cache_copies 0 # number of cache copies performed 579system.cpu.dcache.writebacks::writebacks 686473 # number of writebacks 580system.cpu.dcache.writebacks::total 686473 # number of writebacks 581system.cpu.dcache.ReadReq_mshr_hits::cpu.data 636 # number of ReadReq MSHR hits 582system.cpu.dcache.ReadReq_mshr_hits::total 636 # number of ReadReq MSHR hits 583system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14226 # number of LoadLockedReq MSHR hits 584system.cpu.dcache.LoadLockedReq_mshr_hits::total 14226 # number of LoadLockedReq MSHR hits 585system.cpu.dcache.demand_mshr_hits::cpu.data 636 # number of demand (read+write) MSHR hits 586system.cpu.dcache.demand_mshr_hits::total 636 # number of demand (read+write) MSHR hits 587system.cpu.dcache.overall_mshr_hits::cpu.data 636 # number of overall MSHR hits 588system.cpu.dcache.overall_mshr_hits::total 636 # number of overall MSHR hits 589system.cpu.dcache.ReadReq_mshr_misses::cpu.data 401970 # number of ReadReq MSHR misses 590system.cpu.dcache.ReadReq_mshr_misses::total 401970 # number of ReadReq MSHR misses 591system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299098 # number of WriteReq MSHR misses 592system.cpu.dcache.WriteReq_mshr_misses::total 299098 # number of WriteReq MSHR misses 593system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 117021 # number of SoftPFReq MSHR misses 594system.cpu.dcache.SoftPFReq_mshr_misses::total 117021 # number of SoftPFReq MSHR misses 595system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8472 # number of LoadLockedReq MSHR misses 596system.cpu.dcache.LoadLockedReq_mshr_misses::total 8472 # number of LoadLockedReq MSHR misses 597system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses 598system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses 599system.cpu.dcache.demand_mshr_misses::cpu.data 701068 # number of demand (read+write) MSHR misses 600system.cpu.dcache.demand_mshr_misses::total 701068 # number of demand (read+write) MSHR misses 601system.cpu.dcache.overall_mshr_misses::cpu.data 818089 # number of overall MSHR misses 602system.cpu.dcache.overall_mshr_misses::total 818089 # number of overall MSHR misses 603system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5096620250 # number of ReadReq MSHR miss cycles 604system.cpu.dcache.ReadReq_mshr_miss_latency::total 5096620250 # number of ReadReq MSHR miss cycles 605system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11004051747 # number of WriteReq MSHR miss cycles 606system.cpu.dcache.WriteReq_mshr_miss_latency::total 11004051747 # number of WriteReq MSHR miss cycles 607system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1414370750 # number of SoftPFReq MSHR miss cycles 608system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1414370750 # number of SoftPFReq MSHR miss cycles 609system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 99646250 # number of LoadLockedReq MSHR miss cycles 610system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 99646250 # number of LoadLockedReq MSHR miss cycles 611system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 146000 # number of StoreCondReq MSHR miss cycles 612system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 146000 # number of StoreCondReq MSHR miss cycles 613system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16100671997 # number of demand (read+write) MSHR miss cycles 614system.cpu.dcache.demand_mshr_miss_latency::total 16100671997 # number of demand (read+write) MSHR miss cycles 615system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17515042747 # number of overall MSHR miss cycles 616system.cpu.dcache.overall_mshr_miss_latency::total 17515042747 # number of overall MSHR miss cycles 617system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5791399500 # number of ReadReq MSHR uncacheable cycles 618system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5791399500 # number of ReadReq MSHR uncacheable cycles 619system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4429678500 # number of WriteReq MSHR uncacheable cycles 620system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4429678500 # number of WriteReq MSHR uncacheable cycles 621system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10221078000 # number of overall MSHR uncacheable cycles 622system.cpu.dcache.overall_mshr_uncacheable_latency::total 10221078000 # number of overall MSHR uncacheable cycles 623system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017085 # mshr miss rate for ReadReq accesses 624system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017085 # mshr miss rate for ReadReq accesses 625system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015632 # mshr miss rate for WriteReq accesses 626system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015632 # mshr miss rate for WriteReq accesses 627system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228856 # mshr miss rate for SoftPFReq accesses 628system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228856 # mshr miss rate for SoftPFReq accesses 629system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018168 # mshr miss rate for LoadLockedReq accesses 630system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018168 # mshr miss rate for LoadLockedReq accesses 631system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses 632system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses 633system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016433 # mshr miss rate for demand accesses 634system.cpu.dcache.demand_mshr_miss_rate::total 0.016433 # mshr miss rate for demand accesses 635system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018949 # mshr miss rate for overall accesses 636system.cpu.dcache.overall_mshr_miss_rate::total 0.018949 # mshr miss rate for overall accesses 637system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12679.106028 # average ReadReq mshr miss latency 638system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12679.106028 # average ReadReq mshr miss latency 639system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36790.790132 # average WriteReq mshr miss latency 640system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36790.790132 # average WriteReq mshr miss latency 641system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12086.469523 # average SoftPFReq mshr miss latency 642system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12086.469523 # average SoftPFReq mshr miss latency 643system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11761.833097 # average LoadLockedReq mshr miss latency 644system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11761.833097 # average LoadLockedReq mshr miss latency 645system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 73000 # average StoreCondReq mshr miss latency 646system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 73000 # average StoreCondReq mshr miss latency 647system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22965.920563 # average overall mshr miss latency 648system.cpu.dcache.demand_avg_mshr_miss_latency::total 22965.920563 # average overall mshr miss latency 649system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21409.703280 # average overall mshr miss latency 650system.cpu.dcache.overall_avg_mshr_miss_latency::total 21409.703280 # average overall mshr miss latency 651system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 652system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 653system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 654system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 655system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 656system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 657system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 658system.cpu.icache.tags.replacements 1700967 # number of replacements 659system.cpu.icache.tags.tagsinuse 510.782035 # Cycle average of tags in use 660system.cpu.icache.tags.total_refs 113917402 # Total number of references to valid blocks. 661system.cpu.icache.tags.sampled_refs 1701479 # Sample count of references to valid blocks. 662system.cpu.icache.tags.avg_refs 66.951988 # Average number of references to valid blocks. 663system.cpu.icache.tags.warmup_cycle 25181626250 # Cycle when the warmup percentage was hit. 664system.cpu.icache.tags.occ_blocks::cpu.inst 510.782035 # Average occupied blocks per requestor 665system.cpu.icache.tags.occ_percent::cpu.inst 0.997621 # Average percentage of cache occupancy 666system.cpu.icache.tags.occ_percent::total 0.997621 # Average percentage of cache occupancy 667system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 668system.cpu.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id 669system.cpu.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id 670system.cpu.icache.tags.age_task_id_blocks_1024::2 264 # Occupied blocks per task id 671system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id 672system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 673system.cpu.icache.tags.tag_accesses 117320372 # Number of tag accesses 674system.cpu.icache.tags.data_accesses 117320372 # Number of data accesses 675system.cpu.icache.ReadReq_hits::cpu.inst 113917402 # number of ReadReq hits 676system.cpu.icache.ReadReq_hits::total 113917402 # number of ReadReq hits 677system.cpu.icache.demand_hits::cpu.inst 113917402 # number of demand (read+write) hits 678system.cpu.icache.demand_hits::total 113917402 # number of demand (read+write) hits 679system.cpu.icache.overall_hits::cpu.inst 113917402 # number of overall hits 680system.cpu.icache.overall_hits::total 113917402 # number of overall hits 681system.cpu.icache.ReadReq_misses::cpu.inst 1701485 # number of ReadReq misses 682system.cpu.icache.ReadReq_misses::total 1701485 # number of ReadReq misses 683system.cpu.icache.demand_misses::cpu.inst 1701485 # number of demand (read+write) misses 684system.cpu.icache.demand_misses::total 1701485 # number of demand (read+write) misses 685system.cpu.icache.overall_misses::cpu.inst 1701485 # number of overall misses 686system.cpu.icache.overall_misses::total 1701485 # number of overall misses 687system.cpu.icache.ReadReq_miss_latency::cpu.inst 23258305750 # number of ReadReq miss cycles 688system.cpu.icache.ReadReq_miss_latency::total 23258305750 # number of ReadReq miss cycles 689system.cpu.icache.demand_miss_latency::cpu.inst 23258305750 # number of demand (read+write) miss cycles 690system.cpu.icache.demand_miss_latency::total 23258305750 # number of demand (read+write) miss cycles 691system.cpu.icache.overall_miss_latency::cpu.inst 23258305750 # number of overall miss cycles 692system.cpu.icache.overall_miss_latency::total 23258305750 # number of overall miss cycles 693system.cpu.icache.ReadReq_accesses::cpu.inst 115618887 # number of ReadReq accesses(hits+misses) 694system.cpu.icache.ReadReq_accesses::total 115618887 # number of ReadReq accesses(hits+misses) 695system.cpu.icache.demand_accesses::cpu.inst 115618887 # number of demand (read+write) accesses 696system.cpu.icache.demand_accesses::total 115618887 # number of demand (read+write) accesses 697system.cpu.icache.overall_accesses::cpu.inst 115618887 # number of overall (read+write) accesses 698system.cpu.icache.overall_accesses::total 115618887 # number of overall (read+write) accesses 699system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014716 # miss rate for ReadReq accesses 700system.cpu.icache.ReadReq_miss_rate::total 0.014716 # miss rate for ReadReq accesses 701system.cpu.icache.demand_miss_rate::cpu.inst 0.014716 # miss rate for demand accesses 702system.cpu.icache.demand_miss_rate::total 0.014716 # miss rate for demand accesses 703system.cpu.icache.overall_miss_rate::cpu.inst 0.014716 # miss rate for overall accesses 704system.cpu.icache.overall_miss_rate::total 0.014716 # miss rate for overall accesses 705system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13669.415687 # average ReadReq miss latency 706system.cpu.icache.ReadReq_avg_miss_latency::total 13669.415687 # average ReadReq miss latency 707system.cpu.icache.demand_avg_miss_latency::cpu.inst 13669.415687 # average overall miss latency 708system.cpu.icache.demand_avg_miss_latency::total 13669.415687 # average overall miss latency 709system.cpu.icache.overall_avg_miss_latency::cpu.inst 13669.415687 # average overall miss latency 710system.cpu.icache.overall_avg_miss_latency::total 13669.415687 # average overall miss latency 711system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 712system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 713system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 714system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 715system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 716system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 717system.cpu.icache.fast_writes 0 # number of fast writes performed 718system.cpu.icache.cache_copies 0 # number of cache copies performed 719system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1701485 # number of ReadReq MSHR misses 720system.cpu.icache.ReadReq_mshr_misses::total 1701485 # number of ReadReq MSHR misses 721system.cpu.icache.demand_mshr_misses::cpu.inst 1701485 # number of demand (read+write) MSHR misses 722system.cpu.icache.demand_mshr_misses::total 1701485 # number of demand (read+write) MSHR misses 723system.cpu.icache.overall_mshr_misses::cpu.inst 1701485 # number of overall MSHR misses 724system.cpu.icache.overall_mshr_misses::total 1701485 # number of overall MSHR misses 725system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19848767250 # number of ReadReq MSHR miss cycles 726system.cpu.icache.ReadReq_mshr_miss_latency::total 19848767250 # number of ReadReq MSHR miss cycles 727system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19848767250 # number of demand (read+write) MSHR miss cycles 728system.cpu.icache.demand_mshr_miss_latency::total 19848767250 # number of demand (read+write) MSHR miss cycles 729system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19848767250 # number of overall MSHR miss cycles 730system.cpu.icache.overall_mshr_miss_latency::total 19848767250 # number of overall MSHR miss cycles 731system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 597905000 # number of ReadReq MSHR uncacheable cycles 732system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 597905000 # number of ReadReq MSHR uncacheable cycles 733system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 597905000 # number of overall MSHR uncacheable cycles 734system.cpu.icache.overall_mshr_uncacheable_latency::total 597905000 # number of overall MSHR uncacheable cycles 735system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014716 # mshr miss rate for ReadReq accesses 736system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014716 # mshr miss rate for ReadReq accesses 737system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014716 # mshr miss rate for demand accesses 738system.cpu.icache.demand_mshr_miss_rate::total 0.014716 # mshr miss rate for demand accesses 739system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014716 # mshr miss rate for overall accesses 740system.cpu.icache.overall_mshr_miss_rate::total 0.014716 # mshr miss rate for overall accesses 741system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11665.555236 # average ReadReq mshr miss latency 742system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11665.555236 # average ReadReq mshr miss latency 743system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11665.555236 # average overall mshr miss latency 744system.cpu.icache.demand_avg_mshr_miss_latency::total 11665.555236 # average overall mshr miss latency 745system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11665.555236 # average overall mshr miss latency 746system.cpu.icache.overall_avg_mshr_miss_latency::total 11665.555236 # average overall mshr miss latency 747system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 748system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 749system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 750system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 751system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 752system.cpu.l2cache.tags.replacements 88871 # number of replacements 753system.cpu.l2cache.tags.tagsinuse 64932.261061 # Cycle average of tags in use 754system.cpu.l2cache.tags.total_refs 2762491 # Total number of references to valid blocks. 755system.cpu.l2cache.tags.sampled_refs 154137 # Sample count of references to valid blocks. 756system.cpu.l2cache.tags.avg_refs 17.922309 # Average number of references to valid blocks. 757system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 758system.cpu.l2cache.tags.occ_blocks::writebacks 50671.767381 # Average occupied blocks per requestor 759system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.809345 # Average occupied blocks per requestor 760system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.012229 # Average occupied blocks per requestor 761system.cpu.l2cache.tags.occ_blocks::cpu.inst 9582.569964 # Average occupied blocks per requestor 762system.cpu.l2cache.tags.occ_blocks::cpu.data 4674.102142 # Average occupied blocks per requestor 763system.cpu.l2cache.tags.occ_percent::writebacks 0.773190 # Average percentage of cache occupancy 764system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000058 # Average percentage of cache occupancy 765system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy 766system.cpu.l2cache.tags.occ_percent::cpu.inst 0.146218 # Average percentage of cache occupancy 767system.cpu.l2cache.tags.occ_percent::cpu.data 0.071321 # Average percentage of cache occupancy 768system.cpu.l2cache.tags.occ_percent::total 0.990788 # Average percentage of cache occupancy 769system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id 770system.cpu.l2cache.tags.occ_task_id_blocks::1024 65261 # Occupied blocks per task id 771system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id 772system.cpu.l2cache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id 773system.cpu.l2cache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id 774system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2127 # Occupied blocks per task id 775system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6954 # Occupied blocks per task id 776system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56136 # Occupied blocks per task id 777system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id 778system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995804 # Percentage of cache occupancy per task id 779system.cpu.l2cache.tags.tag_accesses 26255979 # Number of tag accesses 780system.cpu.l2cache.tags.data_accesses 26255979 # Number of data accesses 781system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6969 # number of ReadReq hits 782system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3658 # number of ReadReq hits 783system.cpu.l2cache.ReadReq_hits::cpu.inst 1683420 # number of ReadReq hits 784system.cpu.l2cache.ReadReq_hits::cpu.data 515272 # number of ReadReq hits 785system.cpu.l2cache.ReadReq_hits::total 2209319 # number of ReadReq hits 786system.cpu.l2cache.Writeback_hits::writebacks 686473 # number of Writeback hits 787system.cpu.l2cache.Writeback_hits::total 686473 # number of Writeback hits 788system.cpu.l2cache.UpgradeReq_hits::cpu.data 23 # number of UpgradeReq hits 789system.cpu.l2cache.UpgradeReq_hits::total 23 # number of UpgradeReq hits 790system.cpu.l2cache.ReadExReq_hits::cpu.data 166120 # number of ReadExReq hits 791system.cpu.l2cache.ReadExReq_hits::total 166120 # number of ReadExReq hits 792system.cpu.l2cache.demand_hits::cpu.dtb.walker 6969 # number of demand (read+write) hits 793system.cpu.l2cache.demand_hits::cpu.itb.walker 3658 # number of demand (read+write) hits 794system.cpu.l2cache.demand_hits::cpu.inst 1683420 # number of demand (read+write) hits 795system.cpu.l2cache.demand_hits::cpu.data 681392 # number of demand (read+write) hits 796system.cpu.l2cache.demand_hits::total 2375439 # number of demand (read+write) hits 797system.cpu.l2cache.overall_hits::cpu.dtb.walker 6969 # number of overall hits 798system.cpu.l2cache.overall_hits::cpu.itb.walker 3658 # number of overall hits 799system.cpu.l2cache.overall_hits::cpu.inst 1683420 # number of overall hits 800system.cpu.l2cache.overall_hits::cpu.data 681392 # number of overall hits 801system.cpu.l2cache.overall_hits::total 2375439 # number of overall hits 802system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses 803system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses 804system.cpu.l2cache.ReadReq_misses::cpu.inst 18040 # number of ReadReq misses 805system.cpu.l2cache.ReadReq_misses::cpu.data 12191 # number of ReadReq misses 806system.cpu.l2cache.ReadReq_misses::total 30240 # number of ReadReq misses 807system.cpu.l2cache.UpgradeReq_misses::cpu.data 2715 # number of UpgradeReq misses 808system.cpu.l2cache.UpgradeReq_misses::total 2715 # number of UpgradeReq misses 809system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses 810system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses 811system.cpu.l2cache.ReadExReq_misses::cpu.data 130240 # number of ReadExReq misses 812system.cpu.l2cache.ReadExReq_misses::total 130240 # number of ReadExReq misses 813system.cpu.l2cache.demand_misses::cpu.dtb.walker 7 # number of demand (read+write) misses 814system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses 815system.cpu.l2cache.demand_misses::cpu.inst 18040 # number of demand (read+write) misses 816system.cpu.l2cache.demand_misses::cpu.data 142431 # number of demand (read+write) misses 817system.cpu.l2cache.demand_misses::total 160480 # number of demand (read+write) misses 818system.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses 819system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses 820system.cpu.l2cache.overall_misses::cpu.inst 18040 # number of overall misses 821system.cpu.l2cache.overall_misses::cpu.data 142431 # number of overall misses 822system.cpu.l2cache.overall_misses::total 160480 # number of overall misses 823system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 553000 # number of ReadReq miss cycles 824system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 149500 # number of ReadReq miss cycles 825system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1313036750 # number of ReadReq miss cycles 826system.cpu.l2cache.ReadReq_miss_latency::cpu.data 930003750 # number of ReadReq miss cycles 827system.cpu.l2cache.ReadReq_miss_latency::total 2243743000 # number of ReadReq miss cycles 828system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 444481 # number of UpgradeReq miss cycles 829system.cpu.l2cache.UpgradeReq_miss_latency::total 444481 # number of UpgradeReq miss cycles 830system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 144000 # number of SCUpgradeReq miss cycles 831system.cpu.l2cache.SCUpgradeReq_miss_latency::total 144000 # number of SCUpgradeReq miss cycles 832system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8983070962 # number of ReadExReq miss cycles 833system.cpu.l2cache.ReadExReq_miss_latency::total 8983070962 # number of ReadExReq miss cycles 834system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 553000 # number of demand (read+write) miss cycles 835system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 149500 # number of demand (read+write) miss cycles 836system.cpu.l2cache.demand_miss_latency::cpu.inst 1313036750 # number of demand (read+write) miss cycles 837system.cpu.l2cache.demand_miss_latency::cpu.data 9913074712 # number of demand (read+write) miss cycles 838system.cpu.l2cache.demand_miss_latency::total 11226813962 # number of demand (read+write) miss cycles 839system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 553000 # number of overall miss cycles 840system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 149500 # number of overall miss cycles 841system.cpu.l2cache.overall_miss_latency::cpu.inst 1313036750 # number of overall miss cycles 842system.cpu.l2cache.overall_miss_latency::cpu.data 9913074712 # number of overall miss cycles 843system.cpu.l2cache.overall_miss_latency::total 11226813962 # number of overall miss cycles 844system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6976 # number of ReadReq accesses(hits+misses) 845system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3660 # number of ReadReq accesses(hits+misses) 846system.cpu.l2cache.ReadReq_accesses::cpu.inst 1701460 # number of ReadReq accesses(hits+misses) 847system.cpu.l2cache.ReadReq_accesses::cpu.data 527463 # number of ReadReq accesses(hits+misses) 848system.cpu.l2cache.ReadReq_accesses::total 2239559 # number of ReadReq accesses(hits+misses) 849system.cpu.l2cache.Writeback_accesses::writebacks 686473 # number of Writeback accesses(hits+misses) 850system.cpu.l2cache.Writeback_accesses::total 686473 # number of Writeback accesses(hits+misses) 851system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2738 # number of UpgradeReq accesses(hits+misses) 852system.cpu.l2cache.UpgradeReq_accesses::total 2738 # number of UpgradeReq accesses(hits+misses) 853system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) 854system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) 855system.cpu.l2cache.ReadExReq_accesses::cpu.data 296360 # number of ReadExReq accesses(hits+misses) 856system.cpu.l2cache.ReadExReq_accesses::total 296360 # number of ReadExReq accesses(hits+misses) 857system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6976 # number of demand (read+write) accesses 858system.cpu.l2cache.demand_accesses::cpu.itb.walker 3660 # number of demand (read+write) accesses 859system.cpu.l2cache.demand_accesses::cpu.inst 1701460 # number of demand (read+write) accesses 860system.cpu.l2cache.demand_accesses::cpu.data 823823 # number of demand (read+write) accesses 861system.cpu.l2cache.demand_accesses::total 2535919 # number of demand (read+write) accesses 862system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6976 # number of overall (read+write) accesses 863system.cpu.l2cache.overall_accesses::cpu.itb.walker 3660 # number of overall (read+write) accesses 864system.cpu.l2cache.overall_accesses::cpu.inst 1701460 # number of overall (read+write) accesses 865system.cpu.l2cache.overall_accesses::cpu.data 823823 # number of overall (read+write) accesses 866system.cpu.l2cache.overall_accesses::total 2535919 # number of overall (read+write) accesses 867system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001003 # miss rate for ReadReq accesses 868system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000546 # miss rate for ReadReq accesses 869system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010603 # miss rate for ReadReq accesses 870system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.023113 # miss rate for ReadReq accesses 871system.cpu.l2cache.ReadReq_miss_rate::total 0.013503 # miss rate for ReadReq accesses 872system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991600 # miss rate for UpgradeReq accesses 873system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991600 # miss rate for UpgradeReq accesses 874system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 875system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 876system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.439466 # miss rate for ReadExReq accesses 877system.cpu.l2cache.ReadExReq_miss_rate::total 0.439466 # miss rate for ReadExReq accesses 878system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001003 # miss rate for demand accesses 879system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000546 # miss rate for demand accesses 880system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010603 # miss rate for demand accesses 881system.cpu.l2cache.demand_miss_rate::cpu.data 0.172890 # miss rate for demand accesses 882system.cpu.l2cache.demand_miss_rate::total 0.063283 # miss rate for demand accesses 883system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001003 # miss rate for overall accesses 884system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000546 # miss rate for overall accesses 885system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010603 # miss rate for overall accesses 886system.cpu.l2cache.overall_miss_rate::cpu.data 0.172890 # miss rate for overall accesses 887system.cpu.l2cache.overall_miss_rate::total 0.063283 # miss rate for overall accesses 888system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 79000 # average ReadReq miss latency 889system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 74750 # average ReadReq miss latency 890system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72784.742239 # average ReadReq miss latency 891system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76286.092199 # average ReadReq miss latency 892system.cpu.l2cache.ReadReq_avg_miss_latency::total 74197.850529 # average ReadReq miss latency 893system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 163.713076 # average UpgradeReq miss latency 894system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 163.713076 # average UpgradeReq miss latency 895system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 72000 # average SCUpgradeReq miss latency 896system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 72000 # average SCUpgradeReq miss latency 897system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68973.210703 # average ReadExReq miss latency 898system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68973.210703 # average ReadExReq miss latency 899system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 79000 # average overall miss latency 900system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 74750 # average overall miss latency 901system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72784.742239 # average overall miss latency 902system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69599.137210 # average overall miss latency 903system.cpu.l2cache.demand_avg_miss_latency::total 69957.714120 # average overall miss latency 904system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 79000 # average overall miss latency 905system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 74750 # average overall miss latency 906system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72784.742239 # average overall miss latency 907system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69599.137210 # average overall miss latency 908system.cpu.l2cache.overall_avg_miss_latency::total 69957.714120 # average overall miss latency 909system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 910system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 911system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 912system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 913system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 914system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 915system.cpu.l2cache.fast_writes 0 # number of fast writes performed 916system.cpu.l2cache.cache_copies 0 # number of cache copies performed 917system.cpu.l2cache.writebacks::writebacks 82181 # number of writebacks 918system.cpu.l2cache.writebacks::total 82181 # number of writebacks 919system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 7 # number of ReadReq MSHR misses 920system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses 921system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 18040 # number of ReadReq MSHR misses 922system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 12191 # number of ReadReq MSHR misses 923system.cpu.l2cache.ReadReq_mshr_misses::total 30240 # number of ReadReq MSHR misses 924system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2715 # number of UpgradeReq MSHR misses 925system.cpu.l2cache.UpgradeReq_mshr_misses::total 2715 # number of UpgradeReq MSHR misses 926system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses 927system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses 928system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130240 # number of ReadExReq MSHR misses 929system.cpu.l2cache.ReadExReq_mshr_misses::total 130240 # number of ReadExReq MSHR misses 930system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 7 # number of demand (read+write) MSHR misses 931system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses 932system.cpu.l2cache.demand_mshr_misses::cpu.inst 18040 # number of demand (read+write) MSHR misses 933system.cpu.l2cache.demand_mshr_misses::cpu.data 142431 # number of demand (read+write) MSHR misses 934system.cpu.l2cache.demand_mshr_misses::total 160480 # number of demand (read+write) MSHR misses 935system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 7 # number of overall MSHR misses 936system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses 937system.cpu.l2cache.overall_mshr_misses::cpu.inst 18040 # number of overall MSHR misses 938system.cpu.l2cache.overall_mshr_misses::cpu.data 142431 # number of overall MSHR misses 939system.cpu.l2cache.overall_mshr_misses::total 160480 # number of overall MSHR misses 940system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 467000 # number of ReadReq MSHR miss cycles 941system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 125000 # number of ReadReq MSHR miss cycles 942system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1087188750 # number of ReadReq MSHR miss cycles 943system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 777906250 # number of ReadReq MSHR miss cycles 944system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1865687000 # number of ReadReq MSHR miss cycles 945system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 27308715 # number of UpgradeReq MSHR miss cycles 946system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27308715 # number of UpgradeReq MSHR miss cycles 947system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 120000 # number of SCUpgradeReq MSHR miss cycles 948system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 120000 # number of SCUpgradeReq MSHR miss cycles 949system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7353282038 # number of ReadExReq MSHR miss cycles 950system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7353282038 # number of ReadExReq MSHR miss cycles 951system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 467000 # number of demand (read+write) MSHR miss cycles 952system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 125000 # number of demand (read+write) MSHR miss cycles 953system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1087188750 # number of demand (read+write) MSHR miss cycles 954system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8131188288 # number of demand (read+write) MSHR miss cycles 955system.cpu.l2cache.demand_mshr_miss_latency::total 9218969038 # number of demand (read+write) MSHR miss cycles 956system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 467000 # number of overall MSHR miss cycles 957system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 125000 # number of overall MSHR miss cycles 958system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1087188750 # number of overall MSHR miss cycles 959system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8131188288 # number of overall MSHR miss cycles 960system.cpu.l2cache.overall_mshr_miss_latency::total 9218969038 # number of overall MSHR miss cycles 961system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 474215000 # number of ReadReq MSHR uncacheable cycles 962system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5385925500 # number of ReadReq MSHR uncacheable cycles 963system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5860140500 # number of ReadReq MSHR uncacheable cycles 964system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4098165500 # number of WriteReq MSHR uncacheable cycles 965system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4098165500 # number of WriteReq MSHR uncacheable cycles 966system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 474215000 # number of overall MSHR uncacheable cycles 967system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9484091000 # number of overall MSHR uncacheable cycles 968system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9958306000 # number of overall MSHR uncacheable cycles 969system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001003 # mshr miss rate for ReadReq accesses 970system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000546 # mshr miss rate for ReadReq accesses 971system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010603 # mshr miss rate for ReadReq accesses 972system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.023113 # mshr miss rate for ReadReq accesses 973system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013503 # mshr miss rate for ReadReq accesses 974system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991600 # mshr miss rate for UpgradeReq accesses 975system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991600 # mshr miss rate for UpgradeReq accesses 976system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses 977system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 978system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.439466 # mshr miss rate for ReadExReq accesses 979system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.439466 # mshr miss rate for ReadExReq accesses 980system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001003 # mshr miss rate for demand accesses 981system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000546 # mshr miss rate for demand accesses 982system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010603 # mshr miss rate for demand accesses 983system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172890 # mshr miss rate for demand accesses 984system.cpu.l2cache.demand_mshr_miss_rate::total 0.063283 # mshr miss rate for demand accesses 985system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001003 # mshr miss rate for overall accesses 986system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000546 # mshr miss rate for overall accesses 987system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010603 # mshr miss rate for overall accesses 988system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172890 # mshr miss rate for overall accesses 989system.cpu.l2cache.overall_mshr_miss_rate::total 0.063283 # mshr miss rate for overall accesses 990system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 66714.285714 # average ReadReq mshr miss latency 991system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency 992system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60265.451774 # average ReadReq mshr miss latency 993system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63809.880240 # average ReadReq mshr miss latency 994system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61695.998677 # average ReadReq mshr miss latency 995system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10058.458564 # average UpgradeReq mshr miss latency 996system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10058.458564 # average UpgradeReq mshr miss latency 997system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 60000 # average SCUpgradeReq mshr miss latency 998system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 60000 # average SCUpgradeReq mshr miss latency 999system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56459.475107 # average ReadExReq mshr miss latency 1000system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56459.475107 # average ReadExReq mshr miss latency 1001system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 66714.285714 # average overall mshr miss latency 1002system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency 1003system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60265.451774 # average overall mshr miss latency 1004system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57088.613350 # average overall mshr miss latency 1005system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57446.217834 # average overall mshr miss latency 1006system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 66714.285714 # average overall mshr miss latency 1007system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency 1008system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60265.451774 # average overall mshr miss latency 1009system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57088.613350 # average overall mshr miss latency 1010system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57446.217834 # average overall mshr miss latency 1011system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1012system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1013system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1014system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1015system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1016system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1017system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1018system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1019system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1020system.cpu.toL2Bus.trans_dist::ReadReq 2296418 # Transaction distribution 1021system.cpu.toL2Bus.trans_dist::ReadResp 2296403 # Transaction distribution 1022system.cpu.toL2Bus.trans_dist::WriteReq 27618 # Transaction distribution 1023system.cpu.toL2Bus.trans_dist::WriteResp 27618 # Transaction distribution 1024system.cpu.toL2Bus.trans_dist::Writeback 686473 # Transaction distribution 1025system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 1026system.cpu.toL2Bus.trans_dist::UpgradeReq 2738 # Transaction distribution 1027system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution 1028system.cpu.toL2Bus.trans_dist::UpgradeResp 2740 # Transaction distribution 1029system.cpu.toL2Bus.trans_dist::ReadExReq 296360 # Transaction distribution 1030system.cpu.toL2Bus.trans_dist::ReadExResp 296360 # Transaction distribution 1031system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3420989 # Packet count per connected master and slave (bytes) 1032system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2457362 # Packet count per connected master and slave (bytes) 1033system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12875 # Packet count per connected master and slave (bytes) 1034system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 24821 # Packet count per connected master and slave (bytes) 1035system.cpu.toL2Bus.pkt_count::total 5916047 # Packet count per connected master and slave (bytes) 1036system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108929528 # Cumulative packet size per connected master and slave (bytes) 1037system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96856201 # Cumulative packet size per connected master and slave (bytes) 1038system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14640 # Cumulative packet size per connected master and slave (bytes) 1039system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27904 # Cumulative packet size per connected master and slave (bytes) 1040system.cpu.toL2Bus.pkt_size::total 205828273 # Cumulative packet size per connected master and slave (bytes) 1041system.cpu.toL2Bus.snoops 53126 # Total snoops (count) 1042system.cpu.toL2Bus.snoop_fanout::samples 3278039 # Request fanout histogram 1043system.cpu.toL2Bus.snoop_fanout::mean 5.011122 # Request fanout histogram 1044system.cpu.toL2Bus.snoop_fanout::stdev 0.104872 # Request fanout histogram 1045system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1046system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1047system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1048system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1049system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1050system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 1051system.cpu.toL2Bus.snoop_fanout::5 3241581 98.89% 98.89% # Request fanout histogram 1052system.cpu.toL2Bus.snoop_fanout::6 36458 1.11% 100.00% # Request fanout histogram 1053system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1054system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1055system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 1056system.cpu.toL2Bus.snoop_fanout::total 3278039 # Request fanout histogram 1057system.cpu.toL2Bus.reqLayer0.occupancy 2354969500 # Layer occupancy (ticks) 1058system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1059system.cpu.toL2Bus.snoopLayer0.occupancy 328500 # Layer occupancy (ticks) 1060system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1061system.cpu.toL2Bus.respLayer0.occupancy 2566643750 # Layer occupancy (ticks) 1062system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1063system.cpu.toL2Bus.respLayer1.occupancy 1312602003 # Layer occupancy (ticks) 1064system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1065system.cpu.toL2Bus.respLayer2.occupancy 9215000 # Layer occupancy (ticks) 1066system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1067system.cpu.toL2Bus.respLayer3.occupancy 17845000 # Layer occupancy (ticks) 1068system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1069system.iobus.trans_dist::ReadReq 30195 # Transaction distribution 1070system.iobus.trans_dist::ReadResp 30195 # Transaction distribution 1071system.iobus.trans_dist::WriteReq 59038 # Transaction distribution 1072system.iobus.trans_dist::WriteResp 22814 # Transaction distribution 1073system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 1074system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) 1075system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) 1076system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 1077system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 1078system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 1079system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 1080system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 1081system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1082system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1083system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1084system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 1085system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1086system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 1087system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 1088system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 1089system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 1090system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 1091system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 1092system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 1093system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 1094system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 1095system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes) 1096system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes) 1097system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes) 1098system.iobus.pkt_count::total 178466 # Packet count per connected master and slave (bytes) 1099system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes) 1100system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) 1101system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 1102system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 1103system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 1104system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 1105system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 1106system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1107system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1108system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1109system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 1110system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1111system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1112system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 1113system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 1114system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1115system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 1116system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 1117system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 1118system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 1119system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 1120system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes) 1121system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) 1122system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) 1123system.iobus.pkt_size::total 2480301 # Cumulative packet size per connected master and slave (bytes) 1124system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks) 1125system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1126system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) 1127system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1128system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) 1129system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1130system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) 1131system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1132system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) 1133system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1134system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) 1135system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 1136system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) 1137system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1138system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 1139system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1140system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 1141system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1142system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 1143system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1144system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) 1145system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1146system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 1147system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1148system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) 1149system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 1150system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) 1151system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 1152system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) 1153system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 1154system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 1155system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 1156system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) 1157system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1158system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) 1159system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1160system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) 1161system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1162system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) 1163system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1164system.iobus.reqLayer27.occupancy 347056142 # Layer occupancy (ticks) 1165system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1166system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 1167system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 1168system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) 1169system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1170system.iobus.respLayer3.occupancy 36804505 # Layer occupancy (ticks) 1171system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 1172system.iocache.tags.replacements 36424 # number of replacements 1173system.iocache.tags.tagsinuse 1.134557 # Cycle average of tags in use 1174system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1175system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. 1176system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1177system.iocache.tags.warmup_cycle 298397320000 # Cycle when the warmup percentage was hit. 1178system.iocache.tags.occ_blocks::realview.ide 1.134557 # Average occupied blocks per requestor 1179system.iocache.tags.occ_percent::realview.ide 0.070910 # Average percentage of cache occupancy 1180system.iocache.tags.occ_percent::total 0.070910 # Average percentage of cache occupancy 1181system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1182system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1183system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1184system.iocache.tags.tag_accesses 328122 # Number of tag accesses 1185system.iocache.tags.data_accesses 328122 # Number of data accesses 1186system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses 1187system.iocache.ReadReq_misses::total 234 # number of ReadReq misses 1188system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses 1189system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses 1190system.iocache.demand_misses::realview.ide 234 # number of demand (read+write) misses 1191system.iocache.demand_misses::total 234 # number of demand (read+write) misses 1192system.iocache.overall_misses::realview.ide 234 # number of overall misses 1193system.iocache.overall_misses::total 234 # number of overall misses 1194system.iocache.ReadReq_miss_latency::realview.ide 28034377 # number of ReadReq miss cycles 1195system.iocache.ReadReq_miss_latency::total 28034377 # number of ReadReq miss cycles 1196system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9588161260 # number of WriteInvalidateReq miss cycles 1197system.iocache.WriteInvalidateReq_miss_latency::total 9588161260 # number of WriteInvalidateReq miss cycles 1198system.iocache.demand_miss_latency::realview.ide 28034377 # number of demand (read+write) miss cycles 1199system.iocache.demand_miss_latency::total 28034377 # number of demand (read+write) miss cycles 1200system.iocache.overall_miss_latency::realview.ide 28034377 # number of overall miss cycles 1201system.iocache.overall_miss_latency::total 28034377 # number of overall miss cycles 1202system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) 1203system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) 1204system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) 1205system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) 1206system.iocache.demand_accesses::realview.ide 234 # number of demand (read+write) accesses 1207system.iocache.demand_accesses::total 234 # number of demand (read+write) accesses 1208system.iocache.overall_accesses::realview.ide 234 # number of overall (read+write) accesses 1209system.iocache.overall_accesses::total 234 # number of overall (read+write) accesses 1210system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1211system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1212system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses 1213system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 1214system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1215system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1216system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1217system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1218system.iocache.ReadReq_avg_miss_latency::realview.ide 119805.029915 # average ReadReq miss latency 1219system.iocache.ReadReq_avg_miss_latency::total 119805.029915 # average ReadReq miss latency 1220system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 264690.847504 # average WriteInvalidateReq miss latency 1221system.iocache.WriteInvalidateReq_avg_miss_latency::total 264690.847504 # average WriteInvalidateReq miss latency 1222system.iocache.demand_avg_miss_latency::realview.ide 119805.029915 # average overall miss latency 1223system.iocache.demand_avg_miss_latency::total 119805.029915 # average overall miss latency 1224system.iocache.overall_avg_miss_latency::realview.ide 119805.029915 # average overall miss latency 1225system.iocache.overall_avg_miss_latency::total 119805.029915 # average overall miss latency 1226system.iocache.blocked_cycles::no_mshrs 55275 # number of cycles access was blocked 1227system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1228system.iocache.blocked::no_mshrs 7147 # number of cycles access was blocked 1229system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1230system.iocache.avg_blocked_cycles::no_mshrs 7.734014 # average number of cycles each access was blocked 1231system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1232system.iocache.fast_writes 0 # number of fast writes performed 1233system.iocache.cache_copies 0 # number of cache copies performed 1234system.iocache.writebacks::writebacks 36190 # number of writebacks 1235system.iocache.writebacks::total 36190 # number of writebacks 1236system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses 1237system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses 1238system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses 1239system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses 1240system.iocache.demand_mshr_misses::realview.ide 234 # number of demand (read+write) MSHR misses 1241system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses 1242system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses 1243system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses 1244system.iocache.ReadReq_mshr_miss_latency::realview.ide 15865377 # number of ReadReq MSHR miss cycles 1245system.iocache.ReadReq_mshr_miss_latency::total 15865377 # number of ReadReq MSHR miss cycles 1246system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7704503270 # number of WriteInvalidateReq MSHR miss cycles 1247system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7704503270 # number of WriteInvalidateReq MSHR miss cycles 1248system.iocache.demand_mshr_miss_latency::realview.ide 15865377 # number of demand (read+write) MSHR miss cycles 1249system.iocache.demand_mshr_miss_latency::total 15865377 # number of demand (read+write) MSHR miss cycles 1250system.iocache.overall_mshr_miss_latency::realview.ide 15865377 # number of overall MSHR miss cycles 1251system.iocache.overall_mshr_miss_latency::total 15865377 # number of overall MSHR miss cycles 1252system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1253system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1254system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses 1255system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 1256system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1257system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1258system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1259system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1260system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67800.756410 # average ReadReq mshr miss latency 1261system.iocache.ReadReq_avg_mshr_miss_latency::total 67800.756410 # average ReadReq mshr miss latency 1262system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 212690.571720 # average WriteInvalidateReq mshr miss latency 1263system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212690.571720 # average WriteInvalidateReq mshr miss latency 1264system.iocache.demand_avg_mshr_miss_latency::realview.ide 67800.756410 # average overall mshr miss latency 1265system.iocache.demand_avg_mshr_miss_latency::total 67800.756410 # average overall mshr miss latency 1266system.iocache.overall_avg_mshr_miss_latency::realview.ide 67800.756410 # average overall mshr miss latency 1267system.iocache.overall_avg_mshr_miss_latency::total 67800.756410 # average overall mshr miss latency 1268system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1269system.membus.trans_dist::ReadReq 70650 # Transaction distribution 1270system.membus.trans_dist::ReadResp 70650 # Transaction distribution 1271system.membus.trans_dist::WriteReq 27618 # Transaction distribution 1272system.membus.trans_dist::WriteResp 27618 # Transaction distribution 1273system.membus.trans_dist::Writeback 118371 # Transaction distribution 1274system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 1275system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 1276system.membus.trans_dist::UpgradeReq 4503 # Transaction distribution 1277system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution 1278system.membus.trans_dist::UpgradeResp 4505 # Transaction distribution 1279system.membus.trans_dist::ReadExReq 128452 # Transaction distribution 1280system.membus.trans_dist::ReadExResp 128452 # Transaction distribution 1281system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) 1282system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) 1283system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2122 # Packet count per connected master and slave (bytes) 1284system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 436202 # Packet count per connected master and slave (bytes) 1285system.membus.pkt_count_system.cpu.l2cache.mem_side::total 543884 # Packet count per connected master and slave (bytes) 1286system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108887 # Packet count per connected master and slave (bytes) 1287system.membus.pkt_count_system.iocache.mem_side::total 108887 # Packet count per connected master and slave (bytes) 1288system.membus.pkt_count::total 652771 # Packet count per connected master and slave (bytes) 1289system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) 1290system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) 1291system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4244 # Cumulative packet size per connected master and slave (bytes) 1292system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15454012 # Cumulative packet size per connected master and slave (bytes) 1293system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15617473 # Cumulative packet size per connected master and slave (bytes) 1294system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) 1295system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) 1296system.membus.pkt_size::total 20252929 # Cumulative packet size per connected master and slave (bytes) 1297system.membus.snoops 498 # Total snoops (count) 1298system.membus.snoop_fanout::samples 318026 # Request fanout histogram 1299system.membus.snoop_fanout::mean 1 # Request fanout histogram 1300system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1301system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1302system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1303system.membus.snoop_fanout::1 318026 100.00% 100.00% # Request fanout histogram 1304system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1305system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1306system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1307system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1308system.membus.snoop_fanout::total 318026 # Request fanout histogram 1309system.membus.reqLayer0.occupancy 86773500 # Layer occupancy (ticks) 1310system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1311system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) 1312system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1313system.membus.reqLayer2.occupancy 1756500 # Layer occupancy (ticks) 1314system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1315system.membus.reqLayer5.occupancy 1589715500 # Layer occupancy (ticks) 1316system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) 1317system.membus.respLayer2.occupancy 1594842247 # Layer occupancy (ticks) 1318system.membus.respLayer2.utilization 0.1 # Layer utilization (%) 1319system.membus.respLayer3.occupancy 38335495 # Layer occupancy (ticks) 1320system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 1321system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1322system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1323system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1324system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1325system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1326system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1327system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1328system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1329system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 1330system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1331system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1332system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 1333system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1334system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1335system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 1336system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1337system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1338system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 1339system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1340system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1341system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 1342system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1343system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1344system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1345system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1346system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1347system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1348system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1349system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1350system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 1351system.realview.ethernet.droppedPackets 0 # number of packets dropped 1352 1353---------- End Simulation Statistics ---------- 1354