stats.txt revision 10072:fa5c8a8a7bab
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.616552 # Number of seconds simulated 4sim_ticks 2616552083000 # Number of ticks simulated 5final_tick 2616552083000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 423166 # Simulator instruction rate (inst/s) 8host_op_rate 538494 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 18392483259 # Simulator tick rate (ticks/s) 10host_mem_usage 421292 # Number of bytes of host memory used 11host_seconds 142.26 # Real time elapsed on the host 12sim_insts 60200379 # Number of instructions simulated 13sim_ops 76607188 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory 17system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory 18system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory 19system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory 20system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory 21system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory 22system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) 23system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) 24system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) 25system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) 26system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) 27system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory 29system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory 30system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory 31system.physmem.bytes_read::cpu.inst 703944 # Number of bytes read from this memory 32system.physmem.bytes_read::cpu.data 9089880 # Number of bytes read from this memory 33system.physmem.bytes_read::total 132477664 # Number of bytes read from this memory 34system.physmem.bytes_inst_read::cpu.inst 703944 # Number of instructions bytes read from this memory 35system.physmem.bytes_inst_read::total 703944 # Number of instructions bytes read from this memory 36system.physmem.bytes_written::writebacks 3706304 # Number of bytes written to this memory 37system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory 38system.physmem.bytes_written::total 6722376 # Number of bytes written to this memory 39system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu.inst 17211 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu.data 142065 # Number of read requests responded to by this memory 44system.physmem.num_reads::total 15494707 # Number of read requests responded to by this memory 45system.physmem.num_writes::writebacks 57911 # Number of write requests responded to by this memory 46system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory 47system.physmem.num_writes::total 811929 # Number of write requests responded to by this memory 48system.physmem.bw_read::realview.clcd 46887426 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu.dtb.walker 122 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu.itb.walker 49 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu.inst 269035 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu.data 3473992 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::total 50630624 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_inst_read::cpu.inst 269035 # Instruction read bandwidth from this memory (bytes/s) 55system.physmem.bw_inst_read::total 269035 # Instruction read bandwidth from this memory (bytes/s) 56system.physmem.bw_write::writebacks 1416484 # Write bandwidth from this memory (bytes/s) 57system.physmem.bw_write::cpu.data 1152689 # Write bandwidth from this memory (bytes/s) 58system.physmem.bw_write::total 2569173 # Write bandwidth from this memory (bytes/s) 59system.physmem.bw_total::writebacks 1416484 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::realview.clcd 46887426 # Total bandwidth to/from this memory (bytes/s) 61system.physmem.bw_total::cpu.dtb.walker 122 # Total bandwidth to/from this memory (bytes/s) 62system.physmem.bw_total::cpu.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) 63system.physmem.bw_total::cpu.inst 269035 # Total bandwidth to/from this memory (bytes/s) 64system.physmem.bw_total::cpu.data 4626681 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::total 53199797 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.readReqs 15494707 # Number of read requests accepted 67system.physmem.writeReqs 811929 # Number of write requests accepted 68system.physmem.readBursts 15494707 # Number of DRAM read bursts, including those serviced by the write queue 69system.physmem.writeBursts 811929 # Number of DRAM write bursts, including those merged in the write queue 70system.physmem.bytesReadDRAM 991550144 # Total number of bytes read from DRAM 71system.physmem.bytesReadWrQ 111104 # Total number of bytes read from write queue 72system.physmem.bytesWritten 6844864 # Total number of bytes written to DRAM 73system.physmem.bytesReadSys 132477664 # Total read bytes from the system interface side 74system.physmem.bytesWrittenSys 6722376 # Total written bytes from the system interface side 75system.physmem.servicedByWrQ 1736 # Number of DRAM read bursts serviced by the write queue 76system.physmem.mergedWrBursts 704958 # Number of DRAM write bursts merged with an existing one 77system.physmem.neitherReadNorWriteReqs 4515 # Number of requests that are neither read nor write 78system.physmem.perBankRdBursts::0 967983 # Per bank write bursts 79system.physmem.perBankRdBursts::1 967715 # Per bank write bursts 80system.physmem.perBankRdBursts::2 967672 # Per bank write bursts 81system.physmem.perBankRdBursts::3 967769 # Per bank write bursts 82system.physmem.perBankRdBursts::4 974609 # Per bank write bursts 83system.physmem.perBankRdBursts::5 968229 # Per bank write bursts 84system.physmem.perBankRdBursts::6 967819 # Per bank write bursts 85system.physmem.perBankRdBursts::7 967736 # Per bank write bursts 86system.physmem.perBankRdBursts::8 968546 # Per bank write bursts 87system.physmem.perBankRdBursts::9 968137 # Per bank write bursts 88system.physmem.perBankRdBursts::10 967949 # Per bank write bursts 89system.physmem.perBankRdBursts::11 967746 # Per bank write bursts 90system.physmem.perBankRdBursts::12 967851 # Per bank write bursts 91system.physmem.perBankRdBursts::13 967741 # Per bank write bursts 92system.physmem.perBankRdBursts::14 967672 # Per bank write bursts 93system.physmem.perBankRdBursts::15 967797 # Per bank write bursts 94system.physmem.perBankWrBursts::0 6609 # Per bank write bursts 95system.physmem.perBankWrBursts::1 6410 # Per bank write bursts 96system.physmem.perBankWrBursts::2 6425 # Per bank write bursts 97system.physmem.perBankWrBursts::3 6343 # Per bank write bursts 98system.physmem.perBankWrBursts::4 6914 # Per bank write bursts 99system.physmem.perBankWrBursts::5 7103 # Per bank write bursts 100system.physmem.perBankWrBursts::6 6905 # Per bank write bursts 101system.physmem.perBankWrBursts::7 6899 # Per bank write bursts 102system.physmem.perBankWrBursts::8 7185 # Per bank write bursts 103system.physmem.perBankWrBursts::9 6844 # Per bank write bursts 104system.physmem.perBankWrBursts::10 6668 # Per bank write bursts 105system.physmem.perBankWrBursts::11 6551 # Per bank write bursts 106system.physmem.perBankWrBursts::12 6595 # Per bank write bursts 107system.physmem.perBankWrBursts::13 6390 # Per bank write bursts 108system.physmem.perBankWrBursts::14 6535 # Per bank write bursts 109system.physmem.perBankWrBursts::15 6575 # Per bank write bursts 110system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 111system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 112system.physmem.totGap 2616547722000 # Total gap between requests 113system.physmem.readPktSize::0 0 # Read request sizes (log2) 114system.physmem.readPktSize::1 0 # Read request sizes (log2) 115system.physmem.readPktSize::2 6664 # Read request sizes (log2) 116system.physmem.readPktSize::3 15335424 # Read request sizes (log2) 117system.physmem.readPktSize::4 0 # Read request sizes (log2) 118system.physmem.readPktSize::5 0 # Read request sizes (log2) 119system.physmem.readPktSize::6 152619 # Read request sizes (log2) 120system.physmem.writePktSize::0 0 # Write request sizes (log2) 121system.physmem.writePktSize::1 0 # Write request sizes (log2) 122system.physmem.writePktSize::2 754018 # Write request sizes (log2) 123system.physmem.writePktSize::3 0 # Write request sizes (log2) 124system.physmem.writePktSize::4 0 # Write request sizes (log2) 125system.physmem.writePktSize::5 0 # Write request sizes (log2) 126system.physmem.writePktSize::6 57911 # Write request sizes (log2) 127system.physmem.rdQLenPdf::0 1246677 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::1 1099488 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::2 1103361 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::3 3738048 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::4 2684438 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::5 2678406 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::6 2686634 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::7 54458 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::8 57693 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::9 20801 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::10 20770 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::11 20680 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::12 20429 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::13 20361 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::14 20300 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::15 20267 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::16 160 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 159system.physmem.wrQLenPdf::0 4862 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::1 4862 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::2 4864 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::3 4862 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::4 4862 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::5 4862 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::6 4863 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::7 4862 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::8 4862 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::9 4862 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::10 4862 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::11 4863 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::12 4862 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::13 4862 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::14 4863 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::15 4862 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::16 4862 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::17 4862 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::18 4863 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::19 4863 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::20 4862 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::21 4862 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 191system.physmem.bytesPerActivate::samples 89706 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::mean 11129.630393 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::gmean 1027.657053 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::stdev 16709.623735 # Bytes accessed per row activation 195system.physmem.bytesPerActivate::64-71 23265 25.93% 25.93% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::128-135 14539 16.21% 42.14% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::192-199 2841 3.17% 45.31% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::256-263 2049 2.28% 47.59% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::320-327 1384 1.54% 49.14% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::384-391 1206 1.34% 50.48% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::448-455 956 1.07% 51.55% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::512-519 1124 1.25% 52.80% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::576-583 653 0.73% 53.53% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::640-647 549 0.61% 54.14% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::704-711 562 0.63% 54.77% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::768-775 672 0.75% 55.51% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::832-839 328 0.37% 55.88% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::896-903 247 0.28% 56.16% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::960-967 203 0.23% 56.38% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::1024-1031 737 0.82% 57.20% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::1088-1095 166 0.19% 57.39% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1152-1159 154 0.17% 57.56% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::1216-1223 147 0.16% 57.72% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::1280-1287 151 0.17% 57.89% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::1344-1351 100 0.11% 58.00% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::1408-1415 2290 2.55% 60.56% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::1472-1479 108 0.12% 60.68% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::1536-1543 177 0.20% 60.87% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::1600-1607 64 0.07% 60.95% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::1664-1671 54 0.06% 61.01% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::1728-1735 47 0.05% 61.06% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::1792-1799 132 0.15% 61.21% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1856-1863 30 0.03% 61.24% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::1920-1927 28 0.03% 61.27% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::1984-1991 20 0.02% 61.29% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::2048-2055 301 0.34% 61.63% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::2112-2119 24 0.03% 61.65% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::2176-2183 30 0.03% 61.69% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::2240-2247 15 0.02% 61.70% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::2304-2311 101 0.11% 61.82% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::2368-2375 18 0.02% 61.84% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::2432-2439 16 0.02% 61.86% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::2496-2503 24 0.03% 61.88% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::2560-2567 89 0.10% 61.98% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::2624-2631 8 0.01% 61.99% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::2688-2695 22 0.02% 62.01% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::2752-2759 13 0.01% 62.03% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::2816-2823 154 0.17% 62.20% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::2880-2887 15 0.02% 62.22% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::2944-2951 13 0.01% 62.23% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::3008-3015 13 0.01% 62.25% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::3072-3079 380 0.42% 62.67% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::3136-3143 14 0.02% 62.69% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::3200-3207 15 0.02% 62.70% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::3264-3271 13 0.01% 62.72% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::3328-3335 154 0.17% 62.89% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::3392-3399 16 0.02% 62.91% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::3456-3463 17 0.02% 62.93% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::3520-3527 10 0.01% 62.94% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::3584-3591 98 0.11% 63.05% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::3648-3655 14 0.02% 63.06% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::3712-3719 13 0.01% 63.08% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::3776-3783 34 0.04% 63.11% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::3840-3847 92 0.10% 63.22% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::3904-3911 11 0.01% 63.23% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::3968-3975 10 0.01% 63.24% # Bytes accessed per row activation 257system.physmem.bytesPerActivate::4032-4039 9 0.01% 63.25% # Bytes accessed per row activation 258system.physmem.bytesPerActivate::4096-4103 228 0.25% 63.50% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::4160-4167 7 0.01% 63.51% # Bytes accessed per row activation 260system.physmem.bytesPerActivate::4224-4231 8 0.01% 63.52% # Bytes accessed per row activation 261system.physmem.bytesPerActivate::4288-4295 6 0.01% 63.53% # Bytes accessed per row activation 262system.physmem.bytesPerActivate::4352-4359 164 0.18% 63.71% # Bytes accessed per row activation 263system.physmem.bytesPerActivate::4416-4423 10 0.01% 63.72% # Bytes accessed per row activation 264system.physmem.bytesPerActivate::4480-4487 9 0.01% 63.73% # Bytes accessed per row activation 265system.physmem.bytesPerActivate::4544-4551 9 0.01% 63.74% # Bytes accessed per row activation 266system.physmem.bytesPerActivate::4608-4615 80 0.09% 63.83% # Bytes accessed per row activation 267system.physmem.bytesPerActivate::4672-4679 9 0.01% 63.84% # Bytes accessed per row activation 268system.physmem.bytesPerActivate::4736-4743 6 0.01% 63.85% # Bytes accessed per row activation 269system.physmem.bytesPerActivate::4800-4807 8 0.01% 63.86% # Bytes accessed per row activation 270system.physmem.bytesPerActivate::4864-4871 90 0.10% 63.96% # Bytes accessed per row activation 271system.physmem.bytesPerActivate::4928-4935 8 0.01% 63.97% # Bytes accessed per row activation 272system.physmem.bytesPerActivate::4992-4999 8 0.01% 63.97% # Bytes accessed per row activation 273system.physmem.bytesPerActivate::5056-5063 9 0.01% 63.98% # Bytes accessed per row activation 274system.physmem.bytesPerActivate::5120-5127 436 0.49% 64.47% # Bytes accessed per row activation 275system.physmem.bytesPerActivate::5184-5191 10 0.01% 64.48% # Bytes accessed per row activation 276system.physmem.bytesPerActivate::5248-5255 7 0.01% 64.49% # Bytes accessed per row activation 277system.physmem.bytesPerActivate::5312-5319 8 0.01% 64.50% # Bytes accessed per row activation 278system.physmem.bytesPerActivate::5376-5383 28 0.03% 64.53% # Bytes accessed per row activation 279system.physmem.bytesPerActivate::5440-5447 18 0.02% 64.55% # Bytes accessed per row activation 280system.physmem.bytesPerActivate::5504-5511 68 0.08% 64.63% # Bytes accessed per row activation 281system.physmem.bytesPerActivate::5568-5575 11 0.01% 64.64% # Bytes accessed per row activation 282system.physmem.bytesPerActivate::5632-5639 279 0.31% 64.95% # Bytes accessed per row activation 283system.physmem.bytesPerActivate::5696-5703 1 0.00% 64.95% # Bytes accessed per row activation 284system.physmem.bytesPerActivate::5760-5767 1 0.00% 64.95% # Bytes accessed per row activation 285system.physmem.bytesPerActivate::5888-5895 70 0.08% 65.03% # Bytes accessed per row activation 286system.physmem.bytesPerActivate::6016-6023 2 0.00% 65.03% # Bytes accessed per row activation 287system.physmem.bytesPerActivate::6144-6151 270 0.30% 65.33% # Bytes accessed per row activation 288system.physmem.bytesPerActivate::6336-6343 1 0.00% 65.33% # Bytes accessed per row activation 289system.physmem.bytesPerActivate::6400-6407 20 0.02% 65.36% # Bytes accessed per row activation 290system.physmem.bytesPerActivate::6528-6535 3 0.00% 65.36% # Bytes accessed per row activation 291system.physmem.bytesPerActivate::6592-6599 1 0.00% 65.36% # Bytes accessed per row activation 292system.physmem.bytesPerActivate::6656-6663 82 0.09% 65.45% # Bytes accessed per row activation 293system.physmem.bytesPerActivate::6784-6791 3 0.00% 65.45% # Bytes accessed per row activation 294system.physmem.bytesPerActivate::6912-6919 143 0.16% 65.61% # Bytes accessed per row activation 295system.physmem.bytesPerActivate::6976-6983 1 0.00% 65.62% # Bytes accessed per row activation 296system.physmem.bytesPerActivate::7040-7047 2 0.00% 65.62% # Bytes accessed per row activation 297system.physmem.bytesPerActivate::7168-7175 411 0.46% 66.08% # Bytes accessed per row activation 298system.physmem.bytesPerActivate::7232-7239 1 0.00% 66.08% # Bytes accessed per row activation 299system.physmem.bytesPerActivate::7424-7431 87 0.10% 66.17% # Bytes accessed per row activation 300system.physmem.bytesPerActivate::7680-7687 21 0.02% 66.20% # Bytes accessed per row activation 301system.physmem.bytesPerActivate::7744-7751 1 0.00% 66.20% # Bytes accessed per row activation 302system.physmem.bytesPerActivate::7808-7815 1 0.00% 66.20% # Bytes accessed per row activation 303system.physmem.bytesPerActivate::7936-7943 78 0.09% 66.29% # Bytes accessed per row activation 304system.physmem.bytesPerActivate::8064-8071 2 0.00% 66.29% # Bytes accessed per row activation 305system.physmem.bytesPerActivate::8192-8199 402 0.45% 66.74% # Bytes accessed per row activation 306system.physmem.bytesPerActivate::8256-8263 2 0.00% 66.74% # Bytes accessed per row activation 307system.physmem.bytesPerActivate::8448-8455 81 0.09% 66.83% # Bytes accessed per row activation 308system.physmem.bytesPerActivate::8704-8711 23 0.03% 66.86% # Bytes accessed per row activation 309system.physmem.bytesPerActivate::8832-8839 1 0.00% 66.86% # Bytes accessed per row activation 310system.physmem.bytesPerActivate::8960-8967 84 0.09% 66.95% # Bytes accessed per row activation 311system.physmem.bytesPerActivate::9024-9031 1 0.00% 66.95% # Bytes accessed per row activation 312system.physmem.bytesPerActivate::9088-9095 5 0.01% 66.96% # Bytes accessed per row activation 313system.physmem.bytesPerActivate::9216-9223 405 0.45% 67.41% # Bytes accessed per row activation 314system.physmem.bytesPerActivate::9472-9479 148 0.16% 67.57% # Bytes accessed per row activation 315system.physmem.bytesPerActivate::9728-9735 87 0.10% 67.67% # Bytes accessed per row activation 316system.physmem.bytesPerActivate::9984-9991 20 0.02% 67.69% # Bytes accessed per row activation 317system.physmem.bytesPerActivate::10048-10055 1 0.00% 67.69% # Bytes accessed per row activation 318system.physmem.bytesPerActivate::10112-10119 2 0.00% 67.70% # Bytes accessed per row activation 319system.physmem.bytesPerActivate::10240-10247 273 0.30% 68.00% # Bytes accessed per row activation 320system.physmem.bytesPerActivate::10304-10311 1 0.00% 68.00% # Bytes accessed per row activation 321system.physmem.bytesPerActivate::10496-10503 69 0.08% 68.08% # Bytes accessed per row activation 322system.physmem.bytesPerActivate::10624-10631 1 0.00% 68.08% # Bytes accessed per row activation 323system.physmem.bytesPerActivate::10752-10759 145 0.16% 68.24% # Bytes accessed per row activation 324system.physmem.bytesPerActivate::10816-10823 1 0.00% 68.24% # Bytes accessed per row activation 325system.physmem.bytesPerActivate::11008-11015 18 0.02% 68.26% # Bytes accessed per row activation 326system.physmem.bytesPerActivate::11072-11079 1 0.00% 68.26% # Bytes accessed per row activation 327system.physmem.bytesPerActivate::11136-11143 7 0.01% 68.27% # Bytes accessed per row activation 328system.physmem.bytesPerActivate::11264-11271 431 0.48% 68.75% # Bytes accessed per row activation 329system.physmem.bytesPerActivate::11520-11527 83 0.09% 68.84% # Bytes accessed per row activation 330system.physmem.bytesPerActivate::11776-11783 80 0.09% 68.93% # Bytes accessed per row activation 331system.physmem.bytesPerActivate::12032-12039 159 0.18% 69.11% # Bytes accessed per row activation 332system.physmem.bytesPerActivate::12160-12167 2 0.00% 69.11% # Bytes accessed per row activation 333system.physmem.bytesPerActivate::12288-12295 208 0.23% 69.34% # Bytes accessed per row activation 334system.physmem.bytesPerActivate::12480-12487 3 0.00% 69.35% # Bytes accessed per row activation 335system.physmem.bytesPerActivate::12544-12551 82 0.09% 69.44% # Bytes accessed per row activation 336system.physmem.bytesPerActivate::12800-12807 88 0.10% 69.54% # Bytes accessed per row activation 337system.physmem.bytesPerActivate::12928-12935 2 0.00% 69.54% # Bytes accessed per row activation 338system.physmem.bytesPerActivate::12992-12999 1 0.00% 69.54% # Bytes accessed per row activation 339system.physmem.bytesPerActivate::13056-13063 148 0.16% 69.71% # Bytes accessed per row activation 340system.physmem.bytesPerActivate::13184-13191 3 0.00% 69.71% # Bytes accessed per row activation 341system.physmem.bytesPerActivate::13312-13319 354 0.39% 70.10% # Bytes accessed per row activation 342system.physmem.bytesPerActivate::13440-13447 2 0.00% 70.11% # Bytes accessed per row activation 343system.physmem.bytesPerActivate::13568-13575 141 0.16% 70.26% # Bytes accessed per row activation 344system.physmem.bytesPerActivate::13632-13639 1 0.00% 70.26% # Bytes accessed per row activation 345system.physmem.bytesPerActivate::13824-13831 73 0.08% 70.35% # Bytes accessed per row activation 346system.physmem.bytesPerActivate::14080-14087 83 0.09% 70.44% # Bytes accessed per row activation 347system.physmem.bytesPerActivate::14208-14215 3 0.00% 70.44% # Bytes accessed per row activation 348system.physmem.bytesPerActivate::14272-14279 1 0.00% 70.44% # Bytes accessed per row activation 349system.physmem.bytesPerActivate::14336-14343 279 0.31% 70.75% # Bytes accessed per row activation 350system.physmem.bytesPerActivate::14400-14407 1 0.00% 70.75% # Bytes accessed per row activation 351system.physmem.bytesPerActivate::14464-14471 1 0.00% 70.76% # Bytes accessed per row activation 352system.physmem.bytesPerActivate::14592-14599 93 0.10% 70.86% # Bytes accessed per row activation 353system.physmem.bytesPerActivate::14656-14663 1 0.00% 70.86% # Bytes accessed per row activation 354system.physmem.bytesPerActivate::14848-14855 91 0.10% 70.96% # Bytes accessed per row activation 355system.physmem.bytesPerActivate::14976-14983 1 0.00% 70.96% # Bytes accessed per row activation 356system.physmem.bytesPerActivate::15104-15111 15 0.02% 70.98% # Bytes accessed per row activation 357system.physmem.bytesPerActivate::15232-15239 4 0.00% 70.98% # Bytes accessed per row activation 358system.physmem.bytesPerActivate::15360-15367 490 0.55% 71.53% # Bytes accessed per row activation 359system.physmem.bytesPerActivate::15424-15431 1 0.00% 71.53% # Bytes accessed per row activation 360system.physmem.bytesPerActivate::15552-15559 1 0.00% 71.53% # Bytes accessed per row activation 361system.physmem.bytesPerActivate::15616-15623 72 0.08% 71.61% # Bytes accessed per row activation 362system.physmem.bytesPerActivate::15744-15751 2 0.00% 71.62% # Bytes accessed per row activation 363system.physmem.bytesPerActivate::15872-15879 143 0.16% 71.77% # Bytes accessed per row activation 364system.physmem.bytesPerActivate::16128-16135 77 0.09% 71.86% # Bytes accessed per row activation 365system.physmem.bytesPerActivate::16256-16263 10 0.01% 71.87% # Bytes accessed per row activation 366system.physmem.bytesPerActivate::16384-16391 534 0.60% 72.47% # Bytes accessed per row activation 367system.physmem.bytesPerActivate::16640-16647 75 0.08% 72.55% # Bytes accessed per row activation 368system.physmem.bytesPerActivate::16704-16711 1 0.00% 72.55% # Bytes accessed per row activation 369system.physmem.bytesPerActivate::16768-16775 2 0.00% 72.55% # Bytes accessed per row activation 370system.physmem.bytesPerActivate::16896-16903 145 0.16% 72.72% # Bytes accessed per row activation 371system.physmem.bytesPerActivate::17152-17159 76 0.08% 72.80% # Bytes accessed per row activation 372system.physmem.bytesPerActivate::17280-17287 3 0.00% 72.80% # Bytes accessed per row activation 373system.physmem.bytesPerActivate::17408-17415 492 0.55% 73.35% # Bytes accessed per row activation 374system.physmem.bytesPerActivate::17472-17479 1 0.00% 73.35% # Bytes accessed per row activation 375system.physmem.bytesPerActivate::17664-17671 16 0.02% 73.37% # Bytes accessed per row activation 376system.physmem.bytesPerActivate::17856-17863 2 0.00% 73.37% # Bytes accessed per row activation 377system.physmem.bytesPerActivate::17920-17927 87 0.10% 73.47% # Bytes accessed per row activation 378system.physmem.bytesPerActivate::18048-18055 2 0.00% 73.47% # Bytes accessed per row activation 379system.physmem.bytesPerActivate::18176-18183 95 0.11% 73.58% # Bytes accessed per row activation 380system.physmem.bytesPerActivate::18240-18247 2 0.00% 73.58% # Bytes accessed per row activation 381system.physmem.bytesPerActivate::18304-18311 4 0.00% 73.58% # Bytes accessed per row activation 382system.physmem.bytesPerActivate::18432-18439 275 0.31% 73.89% # Bytes accessed per row activation 383system.physmem.bytesPerActivate::18560-18567 1 0.00% 73.89% # Bytes accessed per row activation 384system.physmem.bytesPerActivate::18688-18695 81 0.09% 73.98% # Bytes accessed per row activation 385system.physmem.bytesPerActivate::18944-18951 73 0.08% 74.06% # Bytes accessed per row activation 386system.physmem.bytesPerActivate::19072-19079 1 0.00% 74.07% # Bytes accessed per row activation 387system.physmem.bytesPerActivate::19200-19207 143 0.16% 74.22% # Bytes accessed per row activation 388system.physmem.bytesPerActivate::19328-19335 2 0.00% 74.23% # Bytes accessed per row activation 389system.physmem.bytesPerActivate::19392-19399 1 0.00% 74.23% # Bytes accessed per row activation 390system.physmem.bytesPerActivate::19456-19463 347 0.39% 74.61% # Bytes accessed per row activation 391system.physmem.bytesPerActivate::19584-19591 2 0.00% 74.62% # Bytes accessed per row activation 392system.physmem.bytesPerActivate::19712-19719 136 0.15% 74.77% # Bytes accessed per row activation 393system.physmem.bytesPerActivate::19776-19783 1 0.00% 74.77% # Bytes accessed per row activation 394system.physmem.bytesPerActivate::19968-19975 88 0.10% 74.87% # Bytes accessed per row activation 395system.physmem.bytesPerActivate::20032-20039 1 0.00% 74.87% # Bytes accessed per row activation 396system.physmem.bytesPerActivate::20160-20167 2 0.00% 74.87% # Bytes accessed per row activation 397system.physmem.bytesPerActivate::20224-20231 84 0.09% 74.96% # Bytes accessed per row activation 398system.physmem.bytesPerActivate::20352-20359 5 0.01% 74.97% # Bytes accessed per row activation 399system.physmem.bytesPerActivate::20480-20487 216 0.24% 75.21% # Bytes accessed per row activation 400system.physmem.bytesPerActivate::20544-20551 1 0.00% 75.21% # Bytes accessed per row activation 401system.physmem.bytesPerActivate::20736-20743 155 0.17% 75.39% # Bytes accessed per row activation 402system.physmem.bytesPerActivate::20992-20999 77 0.09% 75.47% # Bytes accessed per row activation 403system.physmem.bytesPerActivate::21184-21191 1 0.00% 75.47% # Bytes accessed per row activation 404system.physmem.bytesPerActivate::21248-21255 79 0.09% 75.56% # Bytes accessed per row activation 405system.physmem.bytesPerActivate::21376-21383 5 0.01% 75.57% # Bytes accessed per row activation 406system.physmem.bytesPerActivate::21440-21447 1 0.00% 75.57% # Bytes accessed per row activation 407system.physmem.bytesPerActivate::21504-21511 419 0.47% 76.03% # Bytes accessed per row activation 408system.physmem.bytesPerActivate::21632-21639 1 0.00% 76.04% # Bytes accessed per row activation 409system.physmem.bytesPerActivate::21696-21703 1 0.00% 76.04% # Bytes accessed per row activation 410system.physmem.bytesPerActivate::21760-21767 21 0.02% 76.06% # Bytes accessed per row activation 411system.physmem.bytesPerActivate::21888-21895 1 0.00% 76.06% # Bytes accessed per row activation 412system.physmem.bytesPerActivate::22016-22023 147 0.16% 76.22% # Bytes accessed per row activation 413system.physmem.bytesPerActivate::22272-22279 72 0.08% 76.30% # Bytes accessed per row activation 414system.physmem.bytesPerActivate::22336-22343 1 0.00% 76.31% # Bytes accessed per row activation 415system.physmem.bytesPerActivate::22400-22407 4 0.00% 76.31% # Bytes accessed per row activation 416system.physmem.bytesPerActivate::22528-22535 265 0.30% 76.61% # Bytes accessed per row activation 417system.physmem.bytesPerActivate::22784-22791 21 0.02% 76.63% # Bytes accessed per row activation 418system.physmem.bytesPerActivate::23040-23047 84 0.09% 76.72% # Bytes accessed per row activation 419system.physmem.bytesPerActivate::23168-23175 1 0.00% 76.72% # Bytes accessed per row activation 420system.physmem.bytesPerActivate::23296-23303 141 0.16% 76.88% # Bytes accessed per row activation 421system.physmem.bytesPerActivate::23424-23431 5 0.01% 76.89% # Bytes accessed per row activation 422system.physmem.bytesPerActivate::23488-23495 1 0.00% 76.89% # Bytes accessed per row activation 423system.physmem.bytesPerActivate::23552-23559 410 0.46% 77.34% # Bytes accessed per row activation 424system.physmem.bytesPerActivate::23680-23687 1 0.00% 77.35% # Bytes accessed per row activation 425system.physmem.bytesPerActivate::23808-23815 87 0.10% 77.44% # Bytes accessed per row activation 426system.physmem.bytesPerActivate::24064-24071 18 0.02% 77.46% # Bytes accessed per row activation 427system.physmem.bytesPerActivate::24320-24327 80 0.09% 77.55% # Bytes accessed per row activation 428system.physmem.bytesPerActivate::24384-24391 1 0.00% 77.55% # Bytes accessed per row activation 429system.physmem.bytesPerActivate::24448-24455 3 0.00% 77.56% # Bytes accessed per row activation 430system.physmem.bytesPerActivate::24576-24583 395 0.44% 78.00% # Bytes accessed per row activation 431system.physmem.bytesPerActivate::24704-24711 2 0.00% 78.00% # Bytes accessed per row activation 432system.physmem.bytesPerActivate::24832-24839 76 0.08% 78.08% # Bytes accessed per row activation 433system.physmem.bytesPerActivate::24896-24903 1 0.00% 78.09% # Bytes accessed per row activation 434system.physmem.bytesPerActivate::25088-25095 19 0.02% 78.11% # Bytes accessed per row activation 435system.physmem.bytesPerActivate::25280-25287 1 0.00% 78.11% # Bytes accessed per row activation 436system.physmem.bytesPerActivate::25344-25351 88 0.10% 78.21% # Bytes accessed per row activation 437system.physmem.bytesPerActivate::25472-25479 2 0.00% 78.21% # Bytes accessed per row activation 438system.physmem.bytesPerActivate::25600-25607 409 0.46% 78.66% # Bytes accessed per row activation 439system.physmem.bytesPerActivate::25728-25735 1 0.00% 78.66% # Bytes accessed per row activation 440system.physmem.bytesPerActivate::25856-25863 141 0.16% 78.82% # Bytes accessed per row activation 441system.physmem.bytesPerActivate::25920-25927 2 0.00% 78.82% # Bytes accessed per row activation 442system.physmem.bytesPerActivate::25984-25991 1 0.00% 78.83% # Bytes accessed per row activation 443system.physmem.bytesPerActivate::26112-26119 88 0.10% 78.92% # Bytes accessed per row activation 444system.physmem.bytesPerActivate::26240-26247 1 0.00% 78.92% # Bytes accessed per row activation 445system.physmem.bytesPerActivate::26304-26311 1 0.00% 78.93% # Bytes accessed per row activation 446system.physmem.bytesPerActivate::26368-26375 20 0.02% 78.95% # Bytes accessed per row activation 447system.physmem.bytesPerActivate::26496-26503 3 0.00% 78.95% # Bytes accessed per row activation 448system.physmem.bytesPerActivate::26624-26631 274 0.31% 79.26% # Bytes accessed per row activation 449system.physmem.bytesPerActivate::26688-26695 1 0.00% 79.26% # Bytes accessed per row activation 450system.physmem.bytesPerActivate::26880-26887 69 0.08% 79.33% # Bytes accessed per row activation 451system.physmem.bytesPerActivate::27008-27015 2 0.00% 79.34% # Bytes accessed per row activation 452system.physmem.bytesPerActivate::27136-27143 144 0.16% 79.50% # Bytes accessed per row activation 453system.physmem.bytesPerActivate::27392-27399 23 0.03% 79.52% # Bytes accessed per row activation 454system.physmem.bytesPerActivate::27456-27463 1 0.00% 79.52% # Bytes accessed per row activation 455system.physmem.bytesPerActivate::27520-27527 1 0.00% 79.53% # Bytes accessed per row activation 456system.physmem.bytesPerActivate::27648-27655 414 0.46% 79.99% # Bytes accessed per row activation 457system.physmem.bytesPerActivate::27776-27783 1 0.00% 79.99% # Bytes accessed per row activation 458system.physmem.bytesPerActivate::27904-27911 80 0.09% 80.08% # Bytes accessed per row activation 459system.physmem.bytesPerActivate::28032-28039 2 0.00% 80.08% # Bytes accessed per row activation 460system.physmem.bytesPerActivate::28160-28167 76 0.08% 80.16% # Bytes accessed per row activation 461system.physmem.bytesPerActivate::28288-28295 1 0.00% 80.17% # Bytes accessed per row activation 462system.physmem.bytesPerActivate::28352-28359 1 0.00% 80.17% # Bytes accessed per row activation 463system.physmem.bytesPerActivate::28416-28423 158 0.18% 80.34% # Bytes accessed per row activation 464system.physmem.bytesPerActivate::28480-28487 1 0.00% 80.34% # Bytes accessed per row activation 465system.physmem.bytesPerActivate::28544-28551 2 0.00% 80.35% # Bytes accessed per row activation 466system.physmem.bytesPerActivate::28672-28679 213 0.24% 80.58% # Bytes accessed per row activation 467system.physmem.bytesPerActivate::28928-28935 78 0.09% 80.67% # Bytes accessed per row activation 468system.physmem.bytesPerActivate::28992-28999 1 0.00% 80.67% # Bytes accessed per row activation 469system.physmem.bytesPerActivate::29184-29191 89 0.10% 80.77% # Bytes accessed per row activation 470system.physmem.bytesPerActivate::29248-29255 1 0.00% 80.77% # Bytes accessed per row activation 471system.physmem.bytesPerActivate::29312-29319 2 0.00% 80.77% # Bytes accessed per row activation 472system.physmem.bytesPerActivate::29440-29447 137 0.15% 80.93% # Bytes accessed per row activation 473system.physmem.bytesPerActivate::29504-29511 1 0.00% 80.93% # Bytes accessed per row activation 474system.physmem.bytesPerActivate::29568-29575 1 0.00% 80.93% # Bytes accessed per row activation 475system.physmem.bytesPerActivate::29696-29703 346 0.39% 81.31% # Bytes accessed per row activation 476system.physmem.bytesPerActivate::29824-29831 1 0.00% 81.32% # Bytes accessed per row activation 477system.physmem.bytesPerActivate::29888-29895 2 0.00% 81.32% # Bytes accessed per row activation 478system.physmem.bytesPerActivate::29952-29959 142 0.16% 81.48% # Bytes accessed per row activation 479system.physmem.bytesPerActivate::30080-30087 1 0.00% 81.48% # Bytes accessed per row activation 480system.physmem.bytesPerActivate::30208-30215 72 0.08% 81.56% # Bytes accessed per row activation 481system.physmem.bytesPerActivate::30336-30343 1 0.00% 81.56% # Bytes accessed per row activation 482system.physmem.bytesPerActivate::30400-30407 2 0.00% 81.56% # Bytes accessed per row activation 483system.physmem.bytesPerActivate::30464-30471 82 0.09% 81.65% # Bytes accessed per row activation 484system.physmem.bytesPerActivate::30592-30599 4 0.00% 81.66% # Bytes accessed per row activation 485system.physmem.bytesPerActivate::30720-30727 276 0.31% 81.96% # Bytes accessed per row activation 486system.physmem.bytesPerActivate::30784-30791 1 0.00% 81.97% # Bytes accessed per row activation 487system.physmem.bytesPerActivate::30848-30855 1 0.00% 81.97% # Bytes accessed per row activation 488system.physmem.bytesPerActivate::30976-30983 91 0.10% 82.07% # Bytes accessed per row activation 489system.physmem.bytesPerActivate::31168-31175 1 0.00% 82.07% # Bytes accessed per row activation 490system.physmem.bytesPerActivate::31232-31239 88 0.10% 82.17% # Bytes accessed per row activation 491system.physmem.bytesPerActivate::31488-31495 20 0.02% 82.19% # Bytes accessed per row activation 492system.physmem.bytesPerActivate::31616-31623 5 0.01% 82.20% # Bytes accessed per row activation 493system.physmem.bytesPerActivate::31680-31687 1 0.00% 82.20% # Bytes accessed per row activation 494system.physmem.bytesPerActivate::31744-31751 482 0.54% 82.73% # Bytes accessed per row activation 495system.physmem.bytesPerActivate::32000-32007 73 0.08% 82.81% # Bytes accessed per row activation 496system.physmem.bytesPerActivate::32128-32135 1 0.00% 82.82% # Bytes accessed per row activation 497system.physmem.bytesPerActivate::32256-32263 142 0.16% 82.97% # Bytes accessed per row activation 498system.physmem.bytesPerActivate::32320-32327 2 0.00% 82.98% # Bytes accessed per row activation 499system.physmem.bytesPerActivate::32384-32391 2 0.00% 82.98% # Bytes accessed per row activation 500system.physmem.bytesPerActivate::32512-32519 83 0.09% 83.07% # Bytes accessed per row activation 501system.physmem.bytesPerActivate::32640-32647 1 0.00% 83.07% # Bytes accessed per row activation 502system.physmem.bytesPerActivate::32704-32711 1 0.00% 83.07% # Bytes accessed per row activation 503system.physmem.bytesPerActivate::32768-32775 535 0.60% 83.67% # Bytes accessed per row activation 504system.physmem.bytesPerActivate::32832-32839 1 0.00% 83.67% # Bytes accessed per row activation 505system.physmem.bytesPerActivate::32896-32903 1 0.00% 83.67% # Bytes accessed per row activation 506system.physmem.bytesPerActivate::33024-33031 89 0.10% 83.77% # Bytes accessed per row activation 507system.physmem.bytesPerActivate::33280-33287 149 0.17% 83.94% # Bytes accessed per row activation 508system.physmem.bytesPerActivate::33408-33415 5 0.01% 83.94% # Bytes accessed per row activation 509system.physmem.bytesPerActivate::33536-33543 76 0.08% 84.03% # Bytes accessed per row activation 510system.physmem.bytesPerActivate::33792-33799 481 0.54% 84.56% # Bytes accessed per row activation 511system.physmem.bytesPerActivate::33856-33863 1 0.00% 84.57% # Bytes accessed per row activation 512system.physmem.bytesPerActivate::34048-34055 15 0.02% 84.58% # Bytes accessed per row activation 513system.physmem.bytesPerActivate::34304-34311 88 0.10% 84.68% # Bytes accessed per row activation 514system.physmem.bytesPerActivate::34368-34375 1 0.00% 84.68% # Bytes accessed per row activation 515system.physmem.bytesPerActivate::34432-34439 2 0.00% 84.68% # Bytes accessed per row activation 516system.physmem.bytesPerActivate::34560-34567 92 0.10% 84.79% # Bytes accessed per row activation 517system.physmem.bytesPerActivate::34624-34631 1 0.00% 84.79% # Bytes accessed per row activation 518system.physmem.bytesPerActivate::34688-34695 3 0.00% 84.79% # Bytes accessed per row activation 519system.physmem.bytesPerActivate::34816-34823 267 0.30% 85.09% # Bytes accessed per row activation 520system.physmem.bytesPerActivate::34944-34951 2 0.00% 85.09% # Bytes accessed per row activation 521system.physmem.bytesPerActivate::35072-35079 81 0.09% 85.18% # Bytes accessed per row activation 522system.physmem.bytesPerActivate::35136-35143 1 0.00% 85.18% # Bytes accessed per row activation 523system.physmem.bytesPerActivate::35200-35207 1 0.00% 85.18% # Bytes accessed per row activation 524system.physmem.bytesPerActivate::35328-35335 74 0.08% 85.27% # Bytes accessed per row activation 525system.physmem.bytesPerActivate::35584-35591 144 0.16% 85.43% # Bytes accessed per row activation 526system.physmem.bytesPerActivate::35648-35655 1 0.00% 85.43% # Bytes accessed per row activation 527system.physmem.bytesPerActivate::35712-35719 2 0.00% 85.43% # Bytes accessed per row activation 528system.physmem.bytesPerActivate::35840-35847 346 0.39% 85.81% # Bytes accessed per row activation 529system.physmem.bytesPerActivate::36032-36039 1 0.00% 85.82% # Bytes accessed per row activation 530system.physmem.bytesPerActivate::36096-36103 134 0.15% 85.97% # Bytes accessed per row activation 531system.physmem.bytesPerActivate::36288-36295 1 0.00% 85.97% # Bytes accessed per row activation 532system.physmem.bytesPerActivate::36352-36359 86 0.10% 86.06% # Bytes accessed per row activation 533system.physmem.bytesPerActivate::36480-36487 1 0.00% 86.06% # Bytes accessed per row activation 534system.physmem.bytesPerActivate::36544-36551 1 0.00% 86.06% # Bytes accessed per row activation 535system.physmem.bytesPerActivate::36608-36615 79 0.09% 86.15% # Bytes accessed per row activation 536system.physmem.bytesPerActivate::36736-36743 1 0.00% 86.15% # Bytes accessed per row activation 537system.physmem.bytesPerActivate::36864-36871 207 0.23% 86.38% # Bytes accessed per row activation 538system.physmem.bytesPerActivate::36992-36999 2 0.00% 86.39% # Bytes accessed per row activation 539system.physmem.bytesPerActivate::37056-37063 1 0.00% 86.39% # Bytes accessed per row activation 540system.physmem.bytesPerActivate::37120-37127 154 0.17% 86.56% # Bytes accessed per row activation 541system.physmem.bytesPerActivate::37184-37191 1 0.00% 86.56% # Bytes accessed per row activation 542system.physmem.bytesPerActivate::37376-37383 75 0.08% 86.64% # Bytes accessed per row activation 543system.physmem.bytesPerActivate::37504-37511 2 0.00% 86.65% # Bytes accessed per row activation 544system.physmem.bytesPerActivate::37632-37639 87 0.10% 86.74% # Bytes accessed per row activation 545system.physmem.bytesPerActivate::37888-37895 418 0.47% 87.21% # Bytes accessed per row activation 546system.physmem.bytesPerActivate::38016-38023 2 0.00% 87.21% # Bytes accessed per row activation 547system.physmem.bytesPerActivate::38080-38087 1 0.00% 87.21% # Bytes accessed per row activation 548system.physmem.bytesPerActivate::38144-38151 20 0.02% 87.23% # Bytes accessed per row activation 549system.physmem.bytesPerActivate::38208-38215 1 0.00% 87.24% # Bytes accessed per row activation 550system.physmem.bytesPerActivate::38400-38407 142 0.16% 87.39% # Bytes accessed per row activation 551system.physmem.bytesPerActivate::38528-38535 3 0.00% 87.40% # Bytes accessed per row activation 552system.physmem.bytesPerActivate::38656-38663 69 0.08% 87.47% # Bytes accessed per row activation 553system.physmem.bytesPerActivate::38848-38855 1 0.00% 87.48% # Bytes accessed per row activation 554system.physmem.bytesPerActivate::38912-38919 267 0.30% 87.77% # Bytes accessed per row activation 555system.physmem.bytesPerActivate::39040-39047 1 0.00% 87.77% # Bytes accessed per row activation 556system.physmem.bytesPerActivate::39168-39175 18 0.02% 87.79% # Bytes accessed per row activation 557system.physmem.bytesPerActivate::39232-39239 1 0.00% 87.80% # Bytes accessed per row activation 558system.physmem.bytesPerActivate::39296-39303 2 0.00% 87.80% # Bytes accessed per row activation 559system.physmem.bytesPerActivate::39424-39431 85 0.09% 87.89% # Bytes accessed per row activation 560system.physmem.bytesPerActivate::39552-39559 1 0.00% 87.89% # Bytes accessed per row activation 561system.physmem.bytesPerActivate::39616-39623 2 0.00% 87.90% # Bytes accessed per row activation 562system.physmem.bytesPerActivate::39680-39687 145 0.16% 88.06% # Bytes accessed per row activation 563system.physmem.bytesPerActivate::39936-39943 411 0.46% 88.52% # Bytes accessed per row activation 564system.physmem.bytesPerActivate::40192-40199 83 0.09% 88.61% # Bytes accessed per row activation 565system.physmem.bytesPerActivate::40256-40263 1 0.00% 88.61% # Bytes accessed per row activation 566system.physmem.bytesPerActivate::40320-40327 2 0.00% 88.61% # Bytes accessed per row activation 567system.physmem.bytesPerActivate::40448-40455 16 0.02% 88.63% # Bytes accessed per row activation 568system.physmem.bytesPerActivate::40576-40583 3 0.00% 88.63% # Bytes accessed per row activation 569system.physmem.bytesPerActivate::40640-40647 1 0.00% 88.63% # Bytes accessed per row activation 570system.physmem.bytesPerActivate::40704-40711 79 0.09% 88.72% # Bytes accessed per row activation 571system.physmem.bytesPerActivate::40960-40967 395 0.44% 89.16% # Bytes accessed per row activation 572system.physmem.bytesPerActivate::41152-41159 1 0.00% 89.16% # Bytes accessed per row activation 573system.physmem.bytesPerActivate::41216-41223 77 0.09% 89.25% # Bytes accessed per row activation 574system.physmem.bytesPerActivate::41344-41351 1 0.00% 89.25% # Bytes accessed per row activation 575system.physmem.bytesPerActivate::41472-41479 17 0.02% 89.27% # Bytes accessed per row activation 576system.physmem.bytesPerActivate::41600-41607 3 0.00% 89.27% # Bytes accessed per row activation 577system.physmem.bytesPerActivate::41728-41735 89 0.10% 89.37% # Bytes accessed per row activation 578system.physmem.bytesPerActivate::41984-41991 405 0.45% 89.82% # Bytes accessed per row activation 579system.physmem.bytesPerActivate::42048-42055 1 0.00% 89.82% # Bytes accessed per row activation 580system.physmem.bytesPerActivate::42112-42119 2 0.00% 89.83% # Bytes accessed per row activation 581system.physmem.bytesPerActivate::42240-42247 142 0.16% 89.99% # Bytes accessed per row activation 582system.physmem.bytesPerActivate::42368-42375 1 0.00% 89.99% # Bytes accessed per row activation 583system.physmem.bytesPerActivate::42496-42503 82 0.09% 90.08% # Bytes accessed per row activation 584system.physmem.bytesPerActivate::42624-42631 4 0.00% 90.08% # Bytes accessed per row activation 585system.physmem.bytesPerActivate::42752-42759 22 0.02% 90.11% # Bytes accessed per row activation 586system.physmem.bytesPerActivate::43008-43015 265 0.30% 90.40% # Bytes accessed per row activation 587system.physmem.bytesPerActivate::43136-43143 1 0.00% 90.40% # Bytes accessed per row activation 588system.physmem.bytesPerActivate::43200-43207 1 0.00% 90.40% # Bytes accessed per row activation 589system.physmem.bytesPerActivate::43264-43271 69 0.08% 90.48% # Bytes accessed per row activation 590system.physmem.bytesPerActivate::43520-43527 144 0.16% 90.64% # Bytes accessed per row activation 591system.physmem.bytesPerActivate::43648-43655 4 0.00% 90.65% # Bytes accessed per row activation 592system.physmem.bytesPerActivate::43776-43783 21 0.02% 90.67% # Bytes accessed per row activation 593system.physmem.bytesPerActivate::43840-43847 1 0.00% 90.67% # Bytes accessed per row activation 594system.physmem.bytesPerActivate::44032-44039 417 0.46% 91.14% # Bytes accessed per row activation 595system.physmem.bytesPerActivate::44096-44103 1 0.00% 91.14% # Bytes accessed per row activation 596system.physmem.bytesPerActivate::44160-44167 1 0.00% 91.14% # Bytes accessed per row activation 597system.physmem.bytesPerActivate::44288-44295 79 0.09% 91.23% # Bytes accessed per row activation 598system.physmem.bytesPerActivate::44544-44551 77 0.09% 91.31% # Bytes accessed per row activation 599system.physmem.bytesPerActivate::44672-44679 4 0.00% 91.32% # Bytes accessed per row activation 600system.physmem.bytesPerActivate::44800-44807 154 0.17% 91.49% # Bytes accessed per row activation 601system.physmem.bytesPerActivate::45056-45063 203 0.23% 91.71% # Bytes accessed per row activation 602system.physmem.bytesPerActivate::45184-45191 1 0.00% 91.72% # Bytes accessed per row activation 603system.physmem.bytesPerActivate::45312-45319 82 0.09% 91.81% # Bytes accessed per row activation 604system.physmem.bytesPerActivate::45440-45447 1 0.00% 91.81% # Bytes accessed per row activation 605system.physmem.bytesPerActivate::45504-45511 1 0.00% 91.81% # Bytes accessed per row activation 606system.physmem.bytesPerActivate::45568-45575 88 0.10% 91.91% # Bytes accessed per row activation 607system.physmem.bytesPerActivate::45696-45703 2 0.00% 91.91% # Bytes accessed per row activation 608system.physmem.bytesPerActivate::45760-45767 1 0.00% 91.91% # Bytes accessed per row activation 609system.physmem.bytesPerActivate::45824-45831 135 0.15% 92.06% # Bytes accessed per row activation 610system.physmem.bytesPerActivate::45952-45959 2 0.00% 92.06% # Bytes accessed per row activation 611system.physmem.bytesPerActivate::46080-46087 348 0.39% 92.45% # Bytes accessed per row activation 612system.physmem.bytesPerActivate::46336-46343 145 0.16% 92.61% # Bytes accessed per row activation 613system.physmem.bytesPerActivate::46592-46599 73 0.08% 92.69% # Bytes accessed per row activation 614system.physmem.bytesPerActivate::46720-46727 2 0.00% 92.70% # Bytes accessed per row activation 615system.physmem.bytesPerActivate::46848-46855 84 0.09% 92.79% # Bytes accessed per row activation 616system.physmem.bytesPerActivate::46976-46983 3 0.00% 92.79% # Bytes accessed per row activation 617system.physmem.bytesPerActivate::47104-47111 268 0.30% 93.09% # Bytes accessed per row activation 618system.physmem.bytesPerActivate::47232-47239 2 0.00% 93.09% # Bytes accessed per row activation 619system.physmem.bytesPerActivate::47296-47303 1 0.00% 93.10% # Bytes accessed per row activation 620system.physmem.bytesPerActivate::47360-47367 92 0.10% 93.20% # Bytes accessed per row activation 621system.physmem.bytesPerActivate::47424-47431 1 0.00% 93.20% # Bytes accessed per row activation 622system.physmem.bytesPerActivate::47616-47623 87 0.10% 93.30% # Bytes accessed per row activation 623system.physmem.bytesPerActivate::47680-47687 1 0.00% 93.30% # Bytes accessed per row activation 624system.physmem.bytesPerActivate::47744-47751 4 0.00% 93.30% # Bytes accessed per row activation 625system.physmem.bytesPerActivate::47872-47879 19 0.02% 93.32% # Bytes accessed per row activation 626system.physmem.bytesPerActivate::48064-48071 1 0.00% 93.32% # Bytes accessed per row activation 627system.physmem.bytesPerActivate::48128-48135 511 0.57% 93.89% # Bytes accessed per row activation 628system.physmem.bytesPerActivate::48192-48199 2 0.00% 93.90% # Bytes accessed per row activation 629system.physmem.bytesPerActivate::48256-48263 1 0.00% 93.90% # Bytes accessed per row activation 630system.physmem.bytesPerActivate::48320-48327 2 0.00% 93.90% # Bytes accessed per row activation 631system.physmem.bytesPerActivate::48384-48391 90 0.10% 94.00% # Bytes accessed per row activation 632system.physmem.bytesPerActivate::48640-48647 140 0.16% 94.16% # Bytes accessed per row activation 633system.physmem.bytesPerActivate::48768-48775 73 0.08% 94.24% # Bytes accessed per row activation 634system.physmem.bytesPerActivate::48896-48903 73 0.08% 94.32% # Bytes accessed per row activation 635system.physmem.bytesPerActivate::48960-48967 6 0.01% 94.32% # Bytes accessed per row activation 636system.physmem.bytesPerActivate::49024-49031 6 0.01% 94.33% # Bytes accessed per row activation 637system.physmem.bytesPerActivate::49088-49095 7 0.01% 94.34% # Bytes accessed per row activation 638system.physmem.bytesPerActivate::49152-49159 5078 5.66% 100.00% # Bytes accessed per row activation 639system.physmem.bytesPerActivate::total 89706 # Bytes accessed per row activation 640system.physmem.totQLat 373696644500 # Total ticks spent queuing 641system.physmem.totMemAccLat 469604897000 # Total ticks spent from burst creation until serviced by the DRAM 642system.physmem.totBusLat 77464855000 # Total ticks spent in databus transfers 643system.physmem.totBankLat 18443397500 # Total ticks spent accessing banks 644system.physmem.avgQLat 24120.40 # Average queueing delay per DRAM burst 645system.physmem.avgBankLat 1190.44 # Average bank access latency per DRAM burst 646system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 647system.physmem.avgMemAccLat 30310.84 # Average memory access latency per DRAM burst 648system.physmem.avgRdBW 378.95 # Average DRAM read bandwidth in MiByte/s 649system.physmem.avgWrBW 2.62 # Average achieved write bandwidth in MiByte/s 650system.physmem.avgRdBWSys 50.63 # Average system read bandwidth in MiByte/s 651system.physmem.avgWrBWSys 2.57 # Average system write bandwidth in MiByte/s 652system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 653system.physmem.busUtil 2.98 # Data bus utilization in percentage 654system.physmem.busUtilRead 2.96 # Data bus utilization in percentage for reads 655system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 656system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing 657system.physmem.avgWrQLen 14.55 # Average write queue length when enqueuing 658system.physmem.readRowHits 15419069 # Number of row buffer hits during reads 659system.physmem.writeRowHits 91147 # Number of row buffer hits during writes 660system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads 661system.physmem.writeRowHitRate 85.21 # Row buffer hit rate for writes 662system.physmem.avgGap 160459.07 # Average gap between requests 663system.physmem.pageHitRate 99.42 # Row buffer hit rate, read and write combined 664system.physmem.prechargeAllPercent 2.19 # Percentage of time for which DRAM has all the banks in precharge state 665system.membus.throughput 54116372 # Throughput (bytes/s) 666system.membus.trans_dist::ReadReq 16546597 # Transaction distribution 667system.membus.trans_dist::ReadResp 16546597 # Transaction distribution 668system.membus.trans_dist::WriteReq 763385 # Transaction distribution 669system.membus.trans_dist::WriteResp 763385 # Transaction distribution 670system.membus.trans_dist::Writeback 57911 # Transaction distribution 671system.membus.trans_dist::UpgradeReq 4515 # Transaction distribution 672system.membus.trans_dist::UpgradeResp 4515 # Transaction distribution 673system.membus.trans_dist::ReadExReq 132218 # Transaction distribution 674system.membus.trans_dist::ReadExResp 132218 # Transaction distribution 675system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383088 # Packet count per connected master and slave (bytes) 676system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) 677system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3850 # Packet count per connected master and slave (bytes) 678system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) 679system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893543 # Packet count per connected master and slave (bytes) 680system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280493 # Packet count per connected master and slave (bytes) 681system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30670848 # Packet count per connected master and slave (bytes) 682system.membus.pkt_count_system.iocache.mem_side::total 30670848 # Packet count per connected master and slave (bytes) 683system.membus.pkt_count::total 34951341 # Packet count per connected master and slave (bytes) 684system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390542 # Cumulative packet size per connected master and slave (bytes) 685system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) 686system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7700 # Cumulative packet size per connected master and slave (bytes) 687system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) 688system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16516648 # Cumulative packet size per connected master and slave (bytes) 689system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18914914 # Cumulative packet size per connected master and slave (bytes) 690system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 122683392 # Cumulative packet size per connected master and slave (bytes) 691system.membus.tot_pkt_size_system.iocache.mem_side::total 122683392 # Cumulative packet size per connected master and slave (bytes) 692system.membus.tot_pkt_size::total 141598306 # Cumulative packet size per connected master and slave (bytes) 693system.membus.data_through_bus 141598306 # Total data (bytes) 694system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 695system.membus.reqLayer0.occupancy 1206226000 # Layer occupancy (ticks) 696system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 697system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) 698system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 699system.membus.reqLayer2.occupancy 3614000 # Layer occupancy (ticks) 700system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 701system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) 702system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) 703system.membus.reqLayer6.occupancy 17910626500 # Layer occupancy (ticks) 704system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) 705system.membus.respLayer1.occupancy 4950468826 # Layer occupancy (ticks) 706system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 707system.membus.respLayer2.occupancy 34635984750 # Layer occupancy (ticks) 708system.membus.respLayer2.utilization 1.3 # Layer utilization (%) 709system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 710system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 711system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 712system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 713system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 714system.cf0.dma_write_txs 0 # Number of DMA write transactions. 715system.iobus.throughput 47801049 # Throughput (bytes/s) 716system.iobus.trans_dist::ReadReq 16518785 # Transaction distribution 717system.iobus.trans_dist::ReadResp 16518785 # Transaction distribution 718system.iobus.trans_dist::WriteReq 8183 # Transaction distribution 719system.iobus.trans_dist::WriteResp 8183 # Transaction distribution 720system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes) 721system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7944 # Packet count per connected master and slave (bytes) 722system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 534 # Packet count per connected master and slave (bytes) 723system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes) 724system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) 725system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 726system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) 727system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) 728system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) 729system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 730system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 731system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 732system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) 733system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) 734system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 735system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) 736system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) 737system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) 738system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) 739system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) 740system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 741system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 742system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 743system.iobus.pkt_count_system.bridge.master::total 2383088 # Packet count per connected master and slave (bytes) 744system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes) 745system.iobus.pkt_count_system.realview.clcd.dma::total 30670848 # Packet count per connected master and slave (bytes) 746system.iobus.pkt_count::total 33053936 # Packet count per connected master and slave (bytes) 747system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) 748system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15888 # Cumulative packet size per connected master and slave (bytes) 749system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1068 # Cumulative packet size per connected master and slave (bytes) 750system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes) 751system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) 752system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 753system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) 754system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) 755system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 756system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 757system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 758system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 759system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 760system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) 761system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 762system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 763system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 764system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 765system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 766system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 767system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 768system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 769system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 770system.iobus.tot_pkt_size_system.bridge.master::total 2390542 # Cumulative packet size per connected master and slave (bytes) 771system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes) 772system.iobus.tot_pkt_size_system.realview.clcd.dma::total 122683392 # Cumulative packet size per connected master and slave (bytes) 773system.iobus.tot_pkt_size::total 125073934 # Cumulative packet size per connected master and slave (bytes) 774system.iobus.data_through_bus 125073934 # Total data (bytes) 775system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) 776system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 777system.iobus.reqLayer1.occupancy 3977000 # Layer occupancy (ticks) 778system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 779system.iobus.reqLayer2.occupancy 534000 # Layer occupancy (ticks) 780system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 781system.iobus.reqLayer3.occupancy 527000 # Layer occupancy (ticks) 782system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 783system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) 784system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 785system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) 786system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) 787system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks) 788system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 789system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) 790system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 791system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) 792system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) 793system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 794system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 795system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) 796system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) 797system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) 798system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) 799system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 800system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 801system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) 802system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 803system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 804system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 805system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) 806system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 807system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 808system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 809system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) 810system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 811system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) 812system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 813system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) 814system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 815system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 816system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 817system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) 818system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 819system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) 820system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 821system.iobus.reqLayer25.occupancy 15335424000 # Layer occupancy (ticks) 822system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) 823system.iobus.respLayer0.occupancy 2374905000 # Layer occupancy (ticks) 824system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) 825system.iobus.respLayer1.occupancy 42035727250 # Layer occupancy (ticks) 826system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) 827system.cpu_clk_domain.clock 500 # Clock period in ticks 828system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 829system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 830system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 831system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 832system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 833system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 834system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 835system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 836system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 837system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 838system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 839system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 840system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 841system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 842system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 843system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 844system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 845system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 846system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 847system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 848system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 849system.cpu.dtb.inst_hits 0 # ITB inst hits 850system.cpu.dtb.inst_misses 0 # ITB inst misses 851system.cpu.dtb.read_hits 14996193 # DTB read hits 852system.cpu.dtb.read_misses 7334 # DTB read misses 853system.cpu.dtb.write_hits 11230326 # DTB write hits 854system.cpu.dtb.write_misses 2212 # DTB write misses 855system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed 856system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 857system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 858system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 859system.cpu.dtb.flush_entries 3405 # Number of entries that have been flushed from TLB 860system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 861system.cpu.dtb.prefetch_faults 192 # Number of TLB faults due to prefetch 862system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 863system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions 864system.cpu.dtb.read_accesses 15003527 # DTB read accesses 865system.cpu.dtb.write_accesses 11232538 # DTB write accesses 866system.cpu.dtb.inst_accesses 0 # ITB inst accesses 867system.cpu.dtb.hits 26226519 # DTB hits 868system.cpu.dtb.misses 9546 # DTB misses 869system.cpu.dtb.accesses 26236065 # DTB accesses 870system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 871system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 872system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 873system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 874system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 875system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 876system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 877system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 878system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 879system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 880system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 881system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 882system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 883system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 884system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 885system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 886system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 887system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 888system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 889system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 890system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 891system.cpu.itb.inst_hits 61494253 # ITB inst hits 892system.cpu.itb.inst_misses 4471 # ITB inst misses 893system.cpu.itb.read_hits 0 # DTB read hits 894system.cpu.itb.read_misses 0 # DTB read misses 895system.cpu.itb.write_hits 0 # DTB write hits 896system.cpu.itb.write_misses 0 # DTB write misses 897system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed 898system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 899system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 900system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 901system.cpu.itb.flush_entries 2370 # Number of entries that have been flushed from TLB 902system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 903system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 904system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 905system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 906system.cpu.itb.read_accesses 0 # DTB read accesses 907system.cpu.itb.write_accesses 0 # DTB write accesses 908system.cpu.itb.inst_accesses 61498724 # ITB inst accesses 909system.cpu.itb.hits 61494253 # DTB hits 910system.cpu.itb.misses 4471 # DTB misses 911system.cpu.itb.accesses 61498724 # DTB accesses 912system.cpu.numCycles 5233104166 # number of cpu cycles simulated 913system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 914system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 915system.cpu.committedInsts 60200379 # Number of instructions committed 916system.cpu.committedOps 76607188 # Number of ops (including micro ops) committed 917system.cpu.num_int_alu_accesses 69208982 # Number of integer alu accesses 918system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses 919system.cpu.num_func_calls 2140473 # number of times a function call or return occured 920system.cpu.num_conditional_control_insts 7948700 # number of instructions that are conditional controls 921system.cpu.num_int_insts 69208982 # number of integer instructions 922system.cpu.num_fp_insts 10269 # number of float instructions 923system.cpu.num_int_register_reads 401369988 # number of times the integer registers were read 924system.cpu.num_int_register_writes 74519463 # number of times the integer registers were written 925system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read 926system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written 927system.cpu.num_mem_refs 27394064 # number of memory refs 928system.cpu.num_load_insts 15660288 # Number of load instructions 929system.cpu.num_store_insts 11733776 # Number of store instructions 930system.cpu.num_idle_cycles 4581523252.608249 # Number of idle cycles 931system.cpu.num_busy_cycles 651580913.391751 # Number of busy cycles 932system.cpu.not_idle_fraction 0.124511 # Percentage of non-idle cycles 933system.cpu.idle_fraction 0.875489 # Percentage of idle cycles 934system.cpu.Branches 10308817 # Number of branches fetched 935system.cpu.kern.inst.arm 0 # number of arm instructions executed 936system.cpu.kern.inst.quiesce 83016 # number of quiesce instructions executed 937system.cpu.icache.tags.replacements 856260 # number of replacements 938system.cpu.icache.tags.tagsinuse 510.867590 # Cycle average of tags in use 939system.cpu.icache.tags.total_refs 60637481 # Total number of references to valid blocks. 940system.cpu.icache.tags.sampled_refs 856772 # Sample count of references to valid blocks. 941system.cpu.icache.tags.avg_refs 70.774350 # Average number of references to valid blocks. 942system.cpu.icache.tags.warmup_cycle 19998571250 # Cycle when the warmup percentage was hit. 943system.cpu.icache.tags.occ_blocks::cpu.inst 510.867590 # Average occupied blocks per requestor 944system.cpu.icache.tags.occ_percent::cpu.inst 0.997788 # Average percentage of cache occupancy 945system.cpu.icache.tags.occ_percent::total 0.997788 # Average percentage of cache occupancy 946system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 947system.cpu.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id 948system.cpu.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id 949system.cpu.icache.tags.age_task_id_blocks_1024::2 267 # Occupied blocks per task id 950system.cpu.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id 951system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 952system.cpu.icache.tags.tag_accesses 62351025 # Number of tag accesses 953system.cpu.icache.tags.data_accesses 62351025 # Number of data accesses 954system.cpu.icache.ReadReq_hits::cpu.inst 60637481 # number of ReadReq hits 955system.cpu.icache.ReadReq_hits::total 60637481 # number of ReadReq hits 956system.cpu.icache.demand_hits::cpu.inst 60637481 # number of demand (read+write) hits 957system.cpu.icache.demand_hits::total 60637481 # number of demand (read+write) hits 958system.cpu.icache.overall_hits::cpu.inst 60637481 # number of overall hits 959system.cpu.icache.overall_hits::total 60637481 # number of overall hits 960system.cpu.icache.ReadReq_misses::cpu.inst 856772 # number of ReadReq misses 961system.cpu.icache.ReadReq_misses::total 856772 # number of ReadReq misses 962system.cpu.icache.demand_misses::cpu.inst 856772 # number of demand (read+write) misses 963system.cpu.icache.demand_misses::total 856772 # number of demand (read+write) misses 964system.cpu.icache.overall_misses::cpu.inst 856772 # number of overall misses 965system.cpu.icache.overall_misses::total 856772 # number of overall misses 966system.cpu.icache.ReadReq_miss_latency::cpu.inst 11774299750 # number of ReadReq miss cycles 967system.cpu.icache.ReadReq_miss_latency::total 11774299750 # number of ReadReq miss cycles 968system.cpu.icache.demand_miss_latency::cpu.inst 11774299750 # number of demand (read+write) miss cycles 969system.cpu.icache.demand_miss_latency::total 11774299750 # number of demand (read+write) miss cycles 970system.cpu.icache.overall_miss_latency::cpu.inst 11774299750 # number of overall miss cycles 971system.cpu.icache.overall_miss_latency::total 11774299750 # number of overall miss cycles 972system.cpu.icache.ReadReq_accesses::cpu.inst 61494253 # number of ReadReq accesses(hits+misses) 973system.cpu.icache.ReadReq_accesses::total 61494253 # number of ReadReq accesses(hits+misses) 974system.cpu.icache.demand_accesses::cpu.inst 61494253 # number of demand (read+write) accesses 975system.cpu.icache.demand_accesses::total 61494253 # number of demand (read+write) accesses 976system.cpu.icache.overall_accesses::cpu.inst 61494253 # number of overall (read+write) accesses 977system.cpu.icache.overall_accesses::total 61494253 # number of overall (read+write) accesses 978system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013933 # miss rate for ReadReq accesses 979system.cpu.icache.ReadReq_miss_rate::total 0.013933 # miss rate for ReadReq accesses 980system.cpu.icache.demand_miss_rate::cpu.inst 0.013933 # miss rate for demand accesses 981system.cpu.icache.demand_miss_rate::total 0.013933 # miss rate for demand accesses 982system.cpu.icache.overall_miss_rate::cpu.inst 0.013933 # miss rate for overall accesses 983system.cpu.icache.overall_miss_rate::total 0.013933 # miss rate for overall accesses 984system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13742.629019 # average ReadReq miss latency 985system.cpu.icache.ReadReq_avg_miss_latency::total 13742.629019 # average ReadReq miss latency 986system.cpu.icache.demand_avg_miss_latency::cpu.inst 13742.629019 # average overall miss latency 987system.cpu.icache.demand_avg_miss_latency::total 13742.629019 # average overall miss latency 988system.cpu.icache.overall_avg_miss_latency::cpu.inst 13742.629019 # average overall miss latency 989system.cpu.icache.overall_avg_miss_latency::total 13742.629019 # average overall miss latency 990system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 991system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 992system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 993system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 994system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 995system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 996system.cpu.icache.fast_writes 0 # number of fast writes performed 997system.cpu.icache.cache_copies 0 # number of cache copies performed 998system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856772 # number of ReadReq MSHR misses 999system.cpu.icache.ReadReq_mshr_misses::total 856772 # number of ReadReq MSHR misses 1000system.cpu.icache.demand_mshr_misses::cpu.inst 856772 # number of demand (read+write) MSHR misses 1001system.cpu.icache.demand_mshr_misses::total 856772 # number of demand (read+write) MSHR misses 1002system.cpu.icache.overall_mshr_misses::cpu.inst 856772 # number of overall MSHR misses 1003system.cpu.icache.overall_mshr_misses::total 856772 # number of overall MSHR misses 1004system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10056704250 # number of ReadReq MSHR miss cycles 1005system.cpu.icache.ReadReq_mshr_miss_latency::total 10056704250 # number of ReadReq MSHR miss cycles 1006system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10056704250 # number of demand (read+write) MSHR miss cycles 1007system.cpu.icache.demand_mshr_miss_latency::total 10056704250 # number of demand (read+write) MSHR miss cycles 1008system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10056704250 # number of overall MSHR miss cycles 1009system.cpu.icache.overall_mshr_miss_latency::total 10056704250 # number of overall MSHR miss cycles 1010system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 435943750 # number of ReadReq MSHR uncacheable cycles 1011system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 435943750 # number of ReadReq MSHR uncacheable cycles 1012system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 435943750 # number of overall MSHR uncacheable cycles 1013system.cpu.icache.overall_mshr_uncacheable_latency::total 435943750 # number of overall MSHR uncacheable cycles 1014system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for ReadReq accesses 1015system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013933 # mshr miss rate for ReadReq accesses 1016system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for demand accesses 1017system.cpu.icache.demand_mshr_miss_rate::total 0.013933 # mshr miss rate for demand accesses 1018system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for overall accesses 1019system.cpu.icache.overall_mshr_miss_rate::total 0.013933 # mshr miss rate for overall accesses 1020system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11737.900223 # average ReadReq mshr miss latency 1021system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11737.900223 # average ReadReq mshr miss latency 1022system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11737.900223 # average overall mshr miss latency 1023system.cpu.icache.demand_avg_mshr_miss_latency::total 11737.900223 # average overall mshr miss latency 1024system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11737.900223 # average overall mshr miss latency 1025system.cpu.icache.overall_avg_mshr_miss_latency::total 11737.900223 # average overall mshr miss latency 1026system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1027system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1028system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1029system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1030system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1031system.cpu.l2cache.tags.replacements 62511 # number of replacements 1032system.cpu.l2cache.tags.tagsinuse 50754.773862 # Cycle average of tags in use 1033system.cpu.l2cache.tags.total_refs 1682280 # Total number of references to valid blocks. 1034system.cpu.l2cache.tags.sampled_refs 127893 # Sample count of references to valid blocks. 1035system.cpu.l2cache.tags.avg_refs 13.153808 # Average number of references to valid blocks. 1036system.cpu.l2cache.tags.warmup_cycle 2565659385000 # Cycle when the warmup percentage was hit. 1037system.cpu.l2cache.tags.occ_blocks::writebacks 37718.578019 # Average occupied blocks per requestor 1038system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.884348 # Average occupied blocks per requestor 1039system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000703 # Average occupied blocks per requestor 1040system.cpu.l2cache.tags.occ_blocks::cpu.inst 6993.361988 # Average occupied blocks per requestor 1041system.cpu.l2cache.tags.occ_blocks::cpu.data 6038.948805 # Average occupied blocks per requestor 1042system.cpu.l2cache.tags.occ_percent::writebacks 0.575540 # Average percentage of cache occupancy 1043system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy 1044system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy 1045system.cpu.l2cache.tags.occ_percent::cpu.inst 0.106710 # Average percentage of cache occupancy 1046system.cpu.l2cache.tags.occ_percent::cpu.data 0.092147 # Average percentage of cache occupancy 1047system.cpu.l2cache.tags.occ_percent::total 0.774456 # Average percentage of cache occupancy 1048system.cpu.l2cache.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id 1049system.cpu.l2cache.tags.occ_task_id_blocks::1024 65378 # Occupied blocks per task id 1050system.cpu.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id 1051system.cpu.l2cache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id 1052system.cpu.l2cache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id 1053system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2163 # Occupied blocks per task id 1054system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6898 # Occupied blocks per task id 1055system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56267 # Occupied blocks per task id 1056system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id 1057system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997589 # Percentage of cache occupancy per task id 1058system.cpu.l2cache.tags.tag_accesses 17137404 # Number of tag accesses 1059system.cpu.l2cache.tags.data_accesses 17137404 # Number of data accesses 1060system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8705 # number of ReadReq hits 1061system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3532 # number of ReadReq hits 1062system.cpu.l2cache.ReadReq_hits::cpu.inst 844551 # number of ReadReq hits 1063system.cpu.l2cache.ReadReq_hits::cpu.data 369636 # number of ReadReq hits 1064system.cpu.l2cache.ReadReq_hits::total 1226424 # number of ReadReq hits 1065system.cpu.l2cache.Writeback_hits::writebacks 595238 # number of Writeback hits 1066system.cpu.l2cache.Writeback_hits::total 595238 # number of Writeback hits 1067system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits 1068system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits 1069system.cpu.l2cache.ReadExReq_hits::cpu.data 113388 # number of ReadExReq hits 1070system.cpu.l2cache.ReadExReq_hits::total 113388 # number of ReadExReq hits 1071system.cpu.l2cache.demand_hits::cpu.dtb.walker 8705 # number of demand (read+write) hits 1072system.cpu.l2cache.demand_hits::cpu.itb.walker 3532 # number of demand (read+write) hits 1073system.cpu.l2cache.demand_hits::cpu.inst 844551 # number of demand (read+write) hits 1074system.cpu.l2cache.demand_hits::cpu.data 483024 # number of demand (read+write) hits 1075system.cpu.l2cache.demand_hits::total 1339812 # number of demand (read+write) hits 1076system.cpu.l2cache.overall_hits::cpu.dtb.walker 8705 # number of overall hits 1077system.cpu.l2cache.overall_hits::cpu.itb.walker 3532 # number of overall hits 1078system.cpu.l2cache.overall_hits::cpu.inst 844551 # number of overall hits 1079system.cpu.l2cache.overall_hits::cpu.data 483024 # number of overall hits 1080system.cpu.l2cache.overall_hits::total 1339812 # number of overall hits 1081system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses 1082system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses 1083system.cpu.l2cache.ReadReq_misses::cpu.inst 10585 # number of ReadReq misses 1084system.cpu.l2cache.ReadReq_misses::cpu.data 9809 # number of ReadReq misses 1085system.cpu.l2cache.ReadReq_misses::total 20401 # number of ReadReq misses 1086system.cpu.l2cache.UpgradeReq_misses::cpu.data 2908 # number of UpgradeReq misses 1087system.cpu.l2cache.UpgradeReq_misses::total 2908 # number of UpgradeReq misses 1088system.cpu.l2cache.ReadExReq_misses::cpu.data 133825 # number of ReadExReq misses 1089system.cpu.l2cache.ReadExReq_misses::total 133825 # number of ReadExReq misses 1090system.cpu.l2cache.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses 1091system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses 1092system.cpu.l2cache.demand_misses::cpu.inst 10585 # number of demand (read+write) misses 1093system.cpu.l2cache.demand_misses::cpu.data 143634 # number of demand (read+write) misses 1094system.cpu.l2cache.demand_misses::total 154226 # number of demand (read+write) misses 1095system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses 1096system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses 1097system.cpu.l2cache.overall_misses::cpu.inst 10585 # number of overall misses 1098system.cpu.l2cache.overall_misses::cpu.data 143634 # number of overall misses 1099system.cpu.l2cache.overall_misses::total 154226 # number of overall misses 1100system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 305250 # number of ReadReq miss cycles 1101system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 150000 # number of ReadReq miss cycles 1102system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 752786250 # number of ReadReq miss cycles 1103system.cpu.l2cache.ReadReq_miss_latency::cpu.data 737923500 # number of ReadReq miss cycles 1104system.cpu.l2cache.ReadReq_miss_latency::total 1491165000 # number of ReadReq miss cycles 1105system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 469980 # number of UpgradeReq miss cycles 1106system.cpu.l2cache.UpgradeReq_miss_latency::total 469980 # number of UpgradeReq miss cycles 1107system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9621111643 # number of ReadExReq miss cycles 1108system.cpu.l2cache.ReadExReq_miss_latency::total 9621111643 # number of ReadExReq miss cycles 1109system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 305250 # number of demand (read+write) miss cycles 1110system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 150000 # number of demand (read+write) miss cycles 1111system.cpu.l2cache.demand_miss_latency::cpu.inst 752786250 # number of demand (read+write) miss cycles 1112system.cpu.l2cache.demand_miss_latency::cpu.data 10359035143 # number of demand (read+write) miss cycles 1113system.cpu.l2cache.demand_miss_latency::total 11112276643 # number of demand (read+write) miss cycles 1114system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 305250 # number of overall miss cycles 1115system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 150000 # number of overall miss cycles 1116system.cpu.l2cache.overall_miss_latency::cpu.inst 752786250 # number of overall miss cycles 1117system.cpu.l2cache.overall_miss_latency::cpu.data 10359035143 # number of overall miss cycles 1118system.cpu.l2cache.overall_miss_latency::total 11112276643 # number of overall miss cycles 1119system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8710 # number of ReadReq accesses(hits+misses) 1120system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3534 # number of ReadReq accesses(hits+misses) 1121system.cpu.l2cache.ReadReq_accesses::cpu.inst 855136 # number of ReadReq accesses(hits+misses) 1122system.cpu.l2cache.ReadReq_accesses::cpu.data 379445 # number of ReadReq accesses(hits+misses) 1123system.cpu.l2cache.ReadReq_accesses::total 1246825 # number of ReadReq accesses(hits+misses) 1124system.cpu.l2cache.Writeback_accesses::writebacks 595238 # number of Writeback accesses(hits+misses) 1125system.cpu.l2cache.Writeback_accesses::total 595238 # number of Writeback accesses(hits+misses) 1126system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2934 # number of UpgradeReq accesses(hits+misses) 1127system.cpu.l2cache.UpgradeReq_accesses::total 2934 # number of UpgradeReq accesses(hits+misses) 1128system.cpu.l2cache.ReadExReq_accesses::cpu.data 247213 # number of ReadExReq accesses(hits+misses) 1129system.cpu.l2cache.ReadExReq_accesses::total 247213 # number of ReadExReq accesses(hits+misses) 1130system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8710 # number of demand (read+write) accesses 1131system.cpu.l2cache.demand_accesses::cpu.itb.walker 3534 # number of demand (read+write) accesses 1132system.cpu.l2cache.demand_accesses::cpu.inst 855136 # number of demand (read+write) accesses 1133system.cpu.l2cache.demand_accesses::cpu.data 626658 # number of demand (read+write) accesses 1134system.cpu.l2cache.demand_accesses::total 1494038 # number of demand (read+write) accesses 1135system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8710 # number of overall (read+write) accesses 1136system.cpu.l2cache.overall_accesses::cpu.itb.walker 3534 # number of overall (read+write) accesses 1137system.cpu.l2cache.overall_accesses::cpu.inst 855136 # number of overall (read+write) accesses 1138system.cpu.l2cache.overall_accesses::cpu.data 626658 # number of overall (read+write) accesses 1139system.cpu.l2cache.overall_accesses::total 1494038 # number of overall (read+write) accesses 1140system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000574 # miss rate for ReadReq accesses 1141system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000566 # miss rate for ReadReq accesses 1142system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012378 # miss rate for ReadReq accesses 1143system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025851 # miss rate for ReadReq accesses 1144system.cpu.l2cache.ReadReq_miss_rate::total 0.016362 # miss rate for ReadReq accesses 1145system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991138 # miss rate for UpgradeReq accesses 1146system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991138 # miss rate for UpgradeReq accesses 1147system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541335 # miss rate for ReadExReq accesses 1148system.cpu.l2cache.ReadExReq_miss_rate::total 0.541335 # miss rate for ReadExReq accesses 1149system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000574 # miss rate for demand accesses 1150system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000566 # miss rate for demand accesses 1151system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012378 # miss rate for demand accesses 1152system.cpu.l2cache.demand_miss_rate::cpu.data 0.229206 # miss rate for demand accesses 1153system.cpu.l2cache.demand_miss_rate::total 0.103228 # miss rate for demand accesses 1154system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000574 # miss rate for overall accesses 1155system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000566 # miss rate for overall accesses 1156system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012378 # miss rate for overall accesses 1157system.cpu.l2cache.overall_miss_rate::cpu.data 0.229206 # miss rate for overall accesses 1158system.cpu.l2cache.overall_miss_rate::total 0.103228 # miss rate for overall accesses 1159system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 61050 # average ReadReq miss latency 1160system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 75000 # average ReadReq miss latency 1161system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71118.209731 # average ReadReq miss latency 1162system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75229.228260 # average ReadReq miss latency 1163system.cpu.l2cache.ReadReq_avg_miss_latency::total 73092.740552 # average ReadReq miss latency 1164system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 161.616231 # average UpgradeReq miss latency 1165system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 161.616231 # average UpgradeReq miss latency 1166system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71893.231033 # average ReadExReq miss latency 1167system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71893.231033 # average ReadExReq miss latency 1168system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 61050 # average overall miss latency 1169system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 75000 # average overall miss latency 1170system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71118.209731 # average overall miss latency 1171system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72121.051722 # average overall miss latency 1172system.cpu.l2cache.demand_avg_miss_latency::total 72051.902033 # average overall miss latency 1173system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 61050 # average overall miss latency 1174system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 75000 # average overall miss latency 1175system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71118.209731 # average overall miss latency 1176system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72121.051722 # average overall miss latency 1177system.cpu.l2cache.overall_avg_miss_latency::total 72051.902033 # average overall miss latency 1178system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1179system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1180system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1181system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1182system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1183system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1184system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1185system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1186system.cpu.l2cache.writebacks::writebacks 57911 # number of writebacks 1187system.cpu.l2cache.writebacks::total 57911 # number of writebacks 1188system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 5 # number of ReadReq MSHR misses 1189system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses 1190system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10585 # number of ReadReq MSHR misses 1191system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 9809 # number of ReadReq MSHR misses 1192system.cpu.l2cache.ReadReq_mshr_misses::total 20401 # number of ReadReq MSHR misses 1193system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2908 # number of UpgradeReq MSHR misses 1194system.cpu.l2cache.UpgradeReq_mshr_misses::total 2908 # number of UpgradeReq MSHR misses 1195system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133825 # number of ReadExReq MSHR misses 1196system.cpu.l2cache.ReadExReq_mshr_misses::total 133825 # number of ReadExReq MSHR misses 1197system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 5 # number of demand (read+write) MSHR misses 1198system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses 1199system.cpu.l2cache.demand_mshr_misses::cpu.inst 10585 # number of demand (read+write) MSHR misses 1200system.cpu.l2cache.demand_mshr_misses::cpu.data 143634 # number of demand (read+write) MSHR misses 1201system.cpu.l2cache.demand_mshr_misses::total 154226 # number of demand (read+write) MSHR misses 1202system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 5 # number of overall MSHR misses 1203system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses 1204system.cpu.l2cache.overall_mshr_misses::cpu.inst 10585 # number of overall MSHR misses 1205system.cpu.l2cache.overall_mshr_misses::cpu.data 143634 # number of overall MSHR misses 1206system.cpu.l2cache.overall_mshr_misses::total 154226 # number of overall MSHR misses 1207system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 242750 # number of ReadReq MSHR miss cycles 1208system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 125000 # number of ReadReq MSHR miss cycles 1209system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 620216750 # number of ReadReq MSHR miss cycles 1210system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 615039000 # number of ReadReq MSHR miss cycles 1211system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1235623500 # number of ReadReq MSHR miss cycles 1212system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29085908 # number of UpgradeReq MSHR miss cycles 1213system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29085908 # number of UpgradeReq MSHR miss cycles 1214system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7946453357 # number of ReadExReq MSHR miss cycles 1215system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7946453357 # number of ReadExReq MSHR miss cycles 1216system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 242750 # number of demand (read+write) MSHR miss cycles 1217system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 125000 # number of demand (read+write) MSHR miss cycles 1218system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 620216750 # number of demand (read+write) MSHR miss cycles 1219system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8561492357 # number of demand (read+write) MSHR miss cycles 1220system.cpu.l2cache.demand_mshr_miss_latency::total 9182076857 # number of demand (read+write) MSHR miss cycles 1221system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 242750 # number of overall MSHR miss cycles 1222system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 125000 # number of overall MSHR miss cycles 1223system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 620216750 # number of overall MSHR miss cycles 1224system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8561492357 # number of overall MSHR miss cycles 1225system.cpu.l2cache.overall_mshr_miss_latency::total 9182076857 # number of overall MSHR miss cycles 1226system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 344358750 # number of ReadReq MSHR uncacheable cycles 1227system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166664193250 # number of ReadReq MSHR uncacheable cycles 1228system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167008552000 # number of ReadReq MSHR uncacheable cycles 1229system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 16706218159 # number of WriteReq MSHR uncacheable cycles 1230system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 16706218159 # number of WriteReq MSHR uncacheable cycles 1231system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 344358750 # number of overall MSHR uncacheable cycles 1232system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 183370411409 # number of overall MSHR uncacheable cycles 1233system.cpu.l2cache.overall_mshr_uncacheable_latency::total 183714770159 # number of overall MSHR uncacheable cycles 1234system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for ReadReq accesses 1235system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000566 # mshr miss rate for ReadReq accesses 1236system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012378 # mshr miss rate for ReadReq accesses 1237system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025851 # mshr miss rate for ReadReq accesses 1238system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016362 # mshr miss rate for ReadReq accesses 1239system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991138 # mshr miss rate for UpgradeReq accesses 1240system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991138 # mshr miss rate for UpgradeReq accesses 1241system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541335 # mshr miss rate for ReadExReq accesses 1242system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541335 # mshr miss rate for ReadExReq accesses 1243system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for demand accesses 1244system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000566 # mshr miss rate for demand accesses 1245system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012378 # mshr miss rate for demand accesses 1246system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229206 # mshr miss rate for demand accesses 1247system.cpu.l2cache.demand_mshr_miss_rate::total 0.103228 # mshr miss rate for demand accesses 1248system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for overall accesses 1249system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000566 # mshr miss rate for overall accesses 1250system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012378 # mshr miss rate for overall accesses 1251system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229206 # mshr miss rate for overall accesses 1252system.cpu.l2cache.overall_mshr_miss_rate::total 0.103228 # mshr miss rate for overall accesses 1253system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average ReadReq mshr miss latency 1254system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency 1255system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58593.930090 # average ReadReq mshr miss latency 1256system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62701.498624 # average ReadReq mshr miss latency 1257system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60566.810450 # average ReadReq mshr miss latency 1258system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.031637 # average UpgradeReq mshr miss latency 1259system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.031637 # average UpgradeReq mshr miss latency 1260system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59379.438498 # average ReadExReq mshr miss latency 1261system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59379.438498 # average ReadExReq mshr miss latency 1262system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average overall mshr miss latency 1263system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency 1264system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58593.930090 # average overall mshr miss latency 1265system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59606.307399 # average overall mshr miss latency 1266system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59536.503942 # average overall mshr miss latency 1267system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average overall mshr miss latency 1268system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency 1269system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58593.930090 # average overall mshr miss latency 1270system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59606.307399 # average overall mshr miss latency 1271system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59536.503942 # average overall mshr miss latency 1272system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1273system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1274system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1275system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1276system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1277system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1278system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1279system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1280system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1281system.cpu.dcache.tags.replacements 626146 # number of replacements 1282system.cpu.dcache.tags.tagsinuse 511.876591 # Cycle average of tags in use 1283system.cpu.dcache.tags.total_refs 23656108 # Total number of references to valid blocks. 1284system.cpu.dcache.tags.sampled_refs 626658 # Sample count of references to valid blocks. 1285system.cpu.dcache.tags.avg_refs 37.749631 # Average number of references to valid blocks. 1286system.cpu.dcache.tags.warmup_cycle 664772250 # Cycle when the warmup percentage was hit. 1287system.cpu.dcache.tags.occ_blocks::cpu.data 511.876591 # Average occupied blocks per requestor 1288system.cpu.dcache.tags.occ_percent::cpu.data 0.999759 # Average percentage of cache occupancy 1289system.cpu.dcache.tags.occ_percent::total 0.999759 # Average percentage of cache occupancy 1290system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1291system.cpu.dcache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id 1292system.cpu.dcache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id 1293system.cpu.dcache.tags.age_task_id_blocks_1024::2 109 # Occupied blocks per task id 1294system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1295system.cpu.dcache.tags.tag_accesses 97757722 # Number of tag accesses 1296system.cpu.dcache.tags.data_accesses 97757722 # Number of data accesses 1297system.cpu.dcache.ReadReq_hits::cpu.data 13196248 # number of ReadReq hits 1298system.cpu.dcache.ReadReq_hits::total 13196248 # number of ReadReq hits 1299system.cpu.dcache.WriteReq_hits::cpu.data 9972755 # number of WriteReq hits 1300system.cpu.dcache.WriteReq_hits::total 9972755 # number of WriteReq hits 1301system.cpu.dcache.LoadLockedReq_hits::cpu.data 236393 # number of LoadLockedReq hits 1302system.cpu.dcache.LoadLockedReq_hits::total 236393 # number of LoadLockedReq hits 1303system.cpu.dcache.StoreCondReq_hits::cpu.data 247778 # number of StoreCondReq hits 1304system.cpu.dcache.StoreCondReq_hits::total 247778 # number of StoreCondReq hits 1305system.cpu.dcache.demand_hits::cpu.data 23169003 # number of demand (read+write) hits 1306system.cpu.dcache.demand_hits::total 23169003 # number of demand (read+write) hits 1307system.cpu.dcache.overall_hits::cpu.data 23169003 # number of overall hits 1308system.cpu.dcache.overall_hits::total 23169003 # number of overall hits 1309system.cpu.dcache.ReadReq_misses::cpu.data 368059 # number of ReadReq misses 1310system.cpu.dcache.ReadReq_misses::total 368059 # number of ReadReq misses 1311system.cpu.dcache.WriteReq_misses::cpu.data 250147 # number of WriteReq misses 1312system.cpu.dcache.WriteReq_misses::total 250147 # number of WriteReq misses 1313system.cpu.dcache.LoadLockedReq_misses::cpu.data 11386 # number of LoadLockedReq misses 1314system.cpu.dcache.LoadLockedReq_misses::total 11386 # number of LoadLockedReq misses 1315system.cpu.dcache.demand_misses::cpu.data 618206 # number of demand (read+write) misses 1316system.cpu.dcache.demand_misses::total 618206 # number of demand (read+write) misses 1317system.cpu.dcache.overall_misses::cpu.data 618206 # number of overall misses 1318system.cpu.dcache.overall_misses::total 618206 # number of overall misses 1319system.cpu.dcache.ReadReq_miss_latency::cpu.data 5416606500 # number of ReadReq miss cycles 1320system.cpu.dcache.ReadReq_miss_latency::total 5416606500 # number of ReadReq miss cycles 1321system.cpu.dcache.WriteReq_miss_latency::cpu.data 11623055265 # number of WriteReq miss cycles 1322system.cpu.dcache.WriteReq_miss_latency::total 11623055265 # number of WriteReq miss cycles 1323system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 158362000 # number of LoadLockedReq miss cycles 1324system.cpu.dcache.LoadLockedReq_miss_latency::total 158362000 # number of LoadLockedReq miss cycles 1325system.cpu.dcache.demand_miss_latency::cpu.data 17039661765 # number of demand (read+write) miss cycles 1326system.cpu.dcache.demand_miss_latency::total 17039661765 # number of demand (read+write) miss cycles 1327system.cpu.dcache.overall_miss_latency::cpu.data 17039661765 # number of overall miss cycles 1328system.cpu.dcache.overall_miss_latency::total 17039661765 # number of overall miss cycles 1329system.cpu.dcache.ReadReq_accesses::cpu.data 13564307 # number of ReadReq accesses(hits+misses) 1330system.cpu.dcache.ReadReq_accesses::total 13564307 # number of ReadReq accesses(hits+misses) 1331system.cpu.dcache.WriteReq_accesses::cpu.data 10222902 # number of WriteReq accesses(hits+misses) 1332system.cpu.dcache.WriteReq_accesses::total 10222902 # number of WriteReq accesses(hits+misses) 1333system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247779 # number of LoadLockedReq accesses(hits+misses) 1334system.cpu.dcache.LoadLockedReq_accesses::total 247779 # number of LoadLockedReq accesses(hits+misses) 1335system.cpu.dcache.StoreCondReq_accesses::cpu.data 247778 # number of StoreCondReq accesses(hits+misses) 1336system.cpu.dcache.StoreCondReq_accesses::total 247778 # number of StoreCondReq accesses(hits+misses) 1337system.cpu.dcache.demand_accesses::cpu.data 23787209 # number of demand (read+write) accesses 1338system.cpu.dcache.demand_accesses::total 23787209 # number of demand (read+write) accesses 1339system.cpu.dcache.overall_accesses::cpu.data 23787209 # number of overall (read+write) accesses 1340system.cpu.dcache.overall_accesses::total 23787209 # number of overall (read+write) accesses 1341system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027134 # miss rate for ReadReq accesses 1342system.cpu.dcache.ReadReq_miss_rate::total 0.027134 # miss rate for ReadReq accesses 1343system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024469 # miss rate for WriteReq accesses 1344system.cpu.dcache.WriteReq_miss_rate::total 0.024469 # miss rate for WriteReq accesses 1345system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045952 # miss rate for LoadLockedReq accesses 1346system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045952 # miss rate for LoadLockedReq accesses 1347system.cpu.dcache.demand_miss_rate::cpu.data 0.025989 # miss rate for demand accesses 1348system.cpu.dcache.demand_miss_rate::total 0.025989 # miss rate for demand accesses 1349system.cpu.dcache.overall_miss_rate::cpu.data 0.025989 # miss rate for overall accesses 1350system.cpu.dcache.overall_miss_rate::total 0.025989 # miss rate for overall accesses 1351system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14716.679934 # average ReadReq miss latency 1352system.cpu.dcache.ReadReq_avg_miss_latency::total 14716.679934 # average ReadReq miss latency 1353system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46464.899699 # average WriteReq miss latency 1354system.cpu.dcache.WriteReq_avg_miss_latency::total 46464.899699 # average WriteReq miss latency 1355system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13908.484103 # average LoadLockedReq miss latency 1356system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13908.484103 # average LoadLockedReq miss latency 1357system.cpu.dcache.demand_avg_miss_latency::cpu.data 27563.080535 # average overall miss latency 1358system.cpu.dcache.demand_avg_miss_latency::total 27563.080535 # average overall miss latency 1359system.cpu.dcache.overall_avg_miss_latency::cpu.data 27563.080535 # average overall miss latency 1360system.cpu.dcache.overall_avg_miss_latency::total 27563.080535 # average overall miss latency 1361system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1362system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1363system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1364system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 1365system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1366system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1367system.cpu.dcache.fast_writes 0 # number of fast writes performed 1368system.cpu.dcache.cache_copies 0 # number of cache copies performed 1369system.cpu.dcache.writebacks::writebacks 595238 # number of writebacks 1370system.cpu.dcache.writebacks::total 595238 # number of writebacks 1371system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368059 # number of ReadReq MSHR misses 1372system.cpu.dcache.ReadReq_mshr_misses::total 368059 # number of ReadReq MSHR misses 1373system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250147 # number of WriteReq MSHR misses 1374system.cpu.dcache.WriteReq_mshr_misses::total 250147 # number of WriteReq MSHR misses 1375system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11386 # number of LoadLockedReq MSHR misses 1376system.cpu.dcache.LoadLockedReq_mshr_misses::total 11386 # number of LoadLockedReq MSHR misses 1377system.cpu.dcache.demand_mshr_misses::cpu.data 618206 # number of demand (read+write) MSHR misses 1378system.cpu.dcache.demand_mshr_misses::total 618206 # number of demand (read+write) MSHR misses 1379system.cpu.dcache.overall_mshr_misses::cpu.data 618206 # number of overall MSHR misses 1380system.cpu.dcache.overall_mshr_misses::total 618206 # number of overall MSHR misses 1381system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4678192500 # number of ReadReq MSHR miss cycles 1382system.cpu.dcache.ReadReq_mshr_miss_latency::total 4678192500 # number of ReadReq MSHR miss cycles 1383system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11070820735 # number of WriteReq MSHR miss cycles 1384system.cpu.dcache.WriteReq_mshr_miss_latency::total 11070820735 # number of WriteReq MSHR miss cycles 1385system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 135536000 # number of LoadLockedReq MSHR miss cycles 1386system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 135536000 # number of LoadLockedReq MSHR miss cycles 1387system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15749013235 # number of demand (read+write) MSHR miss cycles 1388system.cpu.dcache.demand_mshr_miss_latency::total 15749013235 # number of demand (read+write) MSHR miss cycles 1389system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15749013235 # number of overall MSHR miss cycles 1390system.cpu.dcache.overall_mshr_miss_latency::total 15749013235 # number of overall MSHR miss cycles 1391system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182058328250 # number of ReadReq MSHR uncacheable cycles 1392system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182058328250 # number of ReadReq MSHR uncacheable cycles 1393system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26237936841 # number of WriteReq MSHR uncacheable cycles 1394system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26237936841 # number of WriteReq MSHR uncacheable cycles 1395system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208296265091 # number of overall MSHR uncacheable cycles 1396system.cpu.dcache.overall_mshr_uncacheable_latency::total 208296265091 # number of overall MSHR uncacheable cycles 1397system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027134 # mshr miss rate for ReadReq accesses 1398system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027134 # mshr miss rate for ReadReq accesses 1399system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024469 # mshr miss rate for WriteReq accesses 1400system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024469 # mshr miss rate for WriteReq accesses 1401system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.045952 # mshr miss rate for LoadLockedReq accesses 1402system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.045952 # mshr miss rate for LoadLockedReq accesses 1403system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025989 # mshr miss rate for demand accesses 1404system.cpu.dcache.demand_mshr_miss_rate::total 0.025989 # mshr miss rate for demand accesses 1405system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025989 # mshr miss rate for overall accesses 1406system.cpu.dcache.overall_mshr_miss_rate::total 0.025989 # mshr miss rate for overall accesses 1407system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12710.441804 # average ReadReq mshr miss latency 1408system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12710.441804 # average ReadReq mshr miss latency 1409system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44257.259671 # average WriteReq mshr miss latency 1410system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44257.259671 # average WriteReq mshr miss latency 1411system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11903.741437 # average LoadLockedReq mshr miss latency 1412system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11903.741437 # average LoadLockedReq mshr miss latency 1413system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25475.348403 # average overall mshr miss latency 1414system.cpu.dcache.demand_avg_mshr_miss_latency::total 25475.348403 # average overall mshr miss latency 1415system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25475.348403 # average overall mshr miss latency 1416system.cpu.dcache.overall_avg_mshr_miss_latency::total 25475.348403 # average overall mshr miss latency 1417system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1418system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1419system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1420system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1421system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1422system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1423system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1424system.cpu.toL2Bus.throughput 52965248 # Throughput (bytes/s) 1425system.cpu.toL2Bus.trans_dist::ReadReq 2454635 # Transaction distribution 1426system.cpu.toL2Bus.trans_dist::ReadResp 2454635 # Transaction distribution 1427system.cpu.toL2Bus.trans_dist::WriteReq 763385 # Transaction distribution 1428system.cpu.toL2Bus.trans_dist::WriteResp 763385 # Transaction distribution 1429system.cpu.toL2Bus.trans_dist::Writeback 595238 # Transaction distribution 1430system.cpu.toL2Bus.trans_dist::UpgradeReq 2934 # Transaction distribution 1431system.cpu.toL2Bus.trans_dist::UpgradeResp 2934 # Transaction distribution 1432system.cpu.toL2Bus.trans_dist::ReadExReq 247213 # Transaction distribution 1433system.cpu.toL2Bus.trans_dist::ReadExResp 247213 # Transaction distribution 1434system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1725170 # Packet count per connected master and slave (bytes) 1435system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5749474 # Packet count per connected master and slave (bytes) 1436system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12460 # Packet count per connected master and slave (bytes) 1437system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27430 # Packet count per connected master and slave (bytes) 1438system.cpu.toL2Bus.pkt_count::total 7514534 # Packet count per connected master and slave (bytes) 1439system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54755228 # Cumulative packet size per connected master and slave (bytes) 1440system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 83615814 # Cumulative packet size per connected master and slave (bytes) 1441system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14136 # Cumulative packet size per connected master and slave (bytes) 1442system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 34840 # Cumulative packet size per connected master and slave (bytes) 1443system.cpu.toL2Bus.tot_pkt_size::total 138420018 # Cumulative packet size per connected master and slave (bytes) 1444system.cpu.toL2Bus.data_through_bus 138420018 # Total data (bytes) 1445system.cpu.toL2Bus.snoop_data_through_bus 166312 # Total snoop data (bytes) 1446system.cpu.toL2Bus.reqLayer0.occupancy 3008633500 # Layer occupancy (ticks) 1447system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1448system.cpu.toL2Bus.respLayer0.occupancy 1295454000 # Layer occupancy (ticks) 1449system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1450system.cpu.toL2Bus.respLayer1.occupancy 2534439174 # Layer occupancy (ticks) 1451system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1452system.cpu.toL2Bus.respLayer2.occupancy 8926000 # Layer occupancy (ticks) 1453system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1454system.cpu.toL2Bus.respLayer3.occupancy 18720500 # Layer occupancy (ticks) 1455system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1456system.iocache.tags.replacements 0 # number of replacements 1457system.iocache.tags.tagsinuse 0 # Cycle average of tags in use 1458system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1459system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. 1460system.iocache.tags.avg_refs nan # Average number of references to valid blocks. 1461system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1462system.iocache.tags.tag_accesses 0 # Number of tag accesses 1463system.iocache.tags.data_accesses 0 # Number of data accesses 1464system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1465system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1466system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1467system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1468system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1469system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1470system.iocache.fast_writes 0 # number of fast writes performed 1471system.iocache.cache_copies 0 # number of cache copies performed 1472system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1538398399250 # number of ReadReq MSHR uncacheable cycles 1473system.iocache.ReadReq_mshr_uncacheable_latency::total 1538398399250 # number of ReadReq MSHR uncacheable cycles 1474system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1538398399250 # number of overall MSHR uncacheable cycles 1475system.iocache.overall_mshr_uncacheable_latency::total 1538398399250 # number of overall MSHR uncacheable cycles 1476system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1477system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1478system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1479system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1480system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1481 1482---------- End Simulation Statistics ---------- 1483