stats.txt revision 9308:f634a34f2f0b
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.203606 # Number of seconds simulated 4sim_ticks 1203606499000 # Number of ticks simulated 5final_tick 1203606499000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 418240 # Simulator instruction rate (inst/s) 8host_op_rate 532998 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 8191230777 # Simulator tick rate (ticks/s) 10host_mem_usage 386340 # Number of bytes of host memory used 11host_seconds 146.94 # Real time elapsed on the host 12sim_insts 61455549 # Number of instructions simulated 13sim_ops 78317886 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.inst 354084 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.data 4259252 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.inst 364956 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.data 5307824 # Number of bytes read from this memory 22system.physmem.bytes_read::total 62191076 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu0.inst 354084 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::cpu1.inst 364956 # Number of instructions bytes read from this memory 25system.physmem.bytes_inst_read::total 719040 # Number of instructions bytes read from this memory 26system.physmem.bytes_written::writebacks 4163904 # Number of bytes written to this memory 27system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory 28system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory 29system.physmem.bytes_written::total 7191248 # Number of bytes written to this memory 30system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu0.inst 11751 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.data 66623 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu1.inst 5784 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu1.data 82961 # Number of read requests responded to by this memory 38system.physmem.num_reads::total 6655190 # Number of read requests responded to by this memory 39system.physmem.num_writes::writebacks 65061 # Number of write requests responded to by this memory 40system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory 41system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory 42system.physmem.num_writes::total 821897 # Number of write requests responded to by this memory 43system.physmem.bw_read::realview.clcd 43124154 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu0.dtb.walker 53 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::cpu0.itb.walker 160 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu0.inst 294186 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::cpu0.data 3538741 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::cpu1.dtb.walker 160 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu1.inst 303219 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu1.data 4409933 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::total 51670605 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::cpu0.inst 294186 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_inst_read::cpu1.inst 303219 # Instruction read bandwidth from this memory (bytes/s) 54system.physmem.bw_inst_read::total 597405 # Instruction read bandwidth from this memory (bytes/s) 55system.physmem.bw_write::writebacks 3459523 # Write bandwidth from this memory (bytes/s) 56system.physmem.bw_write::cpu0.data 14124 # Write bandwidth from this memory (bytes/s) 57system.physmem.bw_write::cpu1.data 2501103 # Write bandwidth from this memory (bytes/s) 58system.physmem.bw_write::total 5974750 # Write bandwidth from this memory (bytes/s) 59system.physmem.bw_total::writebacks 3459523 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::realview.clcd 43124154 # Total bandwidth to/from this memory (bytes/s) 61system.physmem.bw_total::cpu0.dtb.walker 53 # Total bandwidth to/from this memory (bytes/s) 62system.physmem.bw_total::cpu0.itb.walker 160 # Total bandwidth to/from this memory (bytes/s) 63system.physmem.bw_total::cpu0.inst 294186 # Total bandwidth to/from this memory (bytes/s) 64system.physmem.bw_total::cpu0.data 3552865 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::cpu1.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::cpu1.inst 303219 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu1.data 6911036 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::total 57645355 # Total bandwidth to/from this memory (bytes/s) 69system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 70system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 71system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 72system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 73system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 74system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 75system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 76system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 77system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 78system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s) 79system.realview.nvmem.bw_read::cpu1.inst 40 # Total read bandwidth from this memory (bytes/s) 80system.realview.nvmem.bw_read::total 56 # Total read bandwidth from this memory (bytes/s) 81system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s) 82system.realview.nvmem.bw_inst_read::cpu1.inst 40 # Instruction read bandwidth from this memory (bytes/s) 83system.realview.nvmem.bw_inst_read::total 56 # Instruction read bandwidth from this memory (bytes/s) 84system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) 85system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s) 86system.realview.nvmem.bw_total::total 56 # Total bandwidth to/from this memory (bytes/s) 87system.l2c.replacements 70188 # number of replacements 88system.l2c.tagsinuse 53228.072476 # Cycle average of tags in use 89system.l2c.total_refs 1643838 # Total number of references to valid blocks. 90system.l2c.sampled_refs 135351 # Sample count of references to valid blocks. 91system.l2c.avg_refs 12.145001 # Average number of references to valid blocks. 92system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 93system.l2c.occ_blocks::writebacks 40453.574010 # Average occupied blocks per requestor 94system.l2c.occ_blocks::cpu0.dtb.walker 0.000402 # Average occupied blocks per requestor 95system.l2c.occ_blocks::cpu0.itb.walker 0.003089 # Average occupied blocks per requestor 96system.l2c.occ_blocks::cpu0.inst 3394.604865 # Average occupied blocks per requestor 97system.l2c.occ_blocks::cpu0.data 2735.402876 # Average occupied blocks per requestor 98system.l2c.occ_blocks::cpu1.dtb.walker 2.669960 # Average occupied blocks per requestor 99system.l2c.occ_blocks::cpu1.inst 3118.943835 # Average occupied blocks per requestor 100system.l2c.occ_blocks::cpu1.data 3522.873439 # Average occupied blocks per requestor 101system.l2c.occ_percent::writebacks 0.617273 # Average percentage of cache occupancy 102system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy 103system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy 104system.l2c.occ_percent::cpu0.inst 0.051798 # Average percentage of cache occupancy 105system.l2c.occ_percent::cpu0.data 0.041739 # Average percentage of cache occupancy 106system.l2c.occ_percent::cpu1.dtb.walker 0.000041 # Average percentage of cache occupancy 107system.l2c.occ_percent::cpu1.inst 0.047591 # Average percentage of cache occupancy 108system.l2c.occ_percent::cpu1.data 0.053755 # Average percentage of cache occupancy 109system.l2c.occ_percent::total 0.812196 # Average percentage of cache occupancy 110system.l2c.ReadReq_hits::cpu0.dtb.walker 2523 # number of ReadReq hits 111system.l2c.ReadReq_hits::cpu0.itb.walker 1490 # number of ReadReq hits 112system.l2c.ReadReq_hits::cpu0.inst 278308 # number of ReadReq hits 113system.l2c.ReadReq_hits::cpu0.data 124645 # number of ReadReq hits 114system.l2c.ReadReq_hits::cpu1.dtb.walker 5210 # number of ReadReq hits 115system.l2c.ReadReq_hits::cpu1.itb.walker 1502 # number of ReadReq hits 116system.l2c.ReadReq_hits::cpu1.inst 576222 # number of ReadReq hits 117system.l2c.ReadReq_hits::cpu1.data 223363 # number of ReadReq hits 118system.l2c.ReadReq_hits::total 1213263 # number of ReadReq hits 119system.l2c.Writeback_hits::writebacks 571562 # number of Writeback hits 120system.l2c.Writeback_hits::total 571562 # number of Writeback hits 121system.l2c.UpgradeReq_hits::cpu0.data 992 # number of UpgradeReq hits 122system.l2c.UpgradeReq_hits::cpu1.data 878 # number of UpgradeReq hits 123system.l2c.UpgradeReq_hits::total 1870 # number of UpgradeReq hits 124system.l2c.SCUpgradeReq_hits::cpu0.data 189 # number of SCUpgradeReq hits 125system.l2c.SCUpgradeReq_hits::cpu1.data 96 # number of SCUpgradeReq hits 126system.l2c.SCUpgradeReq_hits::total 285 # number of SCUpgradeReq hits 127system.l2c.ReadExReq_hits::cpu0.data 39231 # number of ReadExReq hits 128system.l2c.ReadExReq_hits::cpu1.data 70244 # number of ReadExReq hits 129system.l2c.ReadExReq_hits::total 109475 # number of ReadExReq hits 130system.l2c.demand_hits::cpu0.dtb.walker 2523 # number of demand (read+write) hits 131system.l2c.demand_hits::cpu0.itb.walker 1490 # number of demand (read+write) hits 132system.l2c.demand_hits::cpu0.inst 278308 # number of demand (read+write) hits 133system.l2c.demand_hits::cpu0.data 163876 # number of demand (read+write) hits 134system.l2c.demand_hits::cpu1.dtb.walker 5210 # number of demand (read+write) hits 135system.l2c.demand_hits::cpu1.itb.walker 1502 # number of demand (read+write) hits 136system.l2c.demand_hits::cpu1.inst 576222 # number of demand (read+write) hits 137system.l2c.demand_hits::cpu1.data 293607 # number of demand (read+write) hits 138system.l2c.demand_hits::total 1322738 # number of demand (read+write) hits 139system.l2c.overall_hits::cpu0.dtb.walker 2523 # number of overall hits 140system.l2c.overall_hits::cpu0.itb.walker 1490 # number of overall hits 141system.l2c.overall_hits::cpu0.inst 278308 # number of overall hits 142system.l2c.overall_hits::cpu0.data 163876 # number of overall hits 143system.l2c.overall_hits::cpu1.dtb.walker 5210 # number of overall hits 144system.l2c.overall_hits::cpu1.itb.walker 1502 # number of overall hits 145system.l2c.overall_hits::cpu1.inst 576222 # number of overall hits 146system.l2c.overall_hits::cpu1.data 293607 # number of overall hits 147system.l2c.overall_hits::total 1322738 # number of overall hits 148system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses 149system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses 150system.l2c.ReadReq_misses::cpu0.inst 5119 # number of ReadReq misses 151system.l2c.ReadReq_misses::cpu0.data 6000 # number of ReadReq misses 152system.l2c.ReadReq_misses::cpu1.dtb.walker 3 # number of ReadReq misses 153system.l2c.ReadReq_misses::cpu1.inst 5697 # number of ReadReq misses 154system.l2c.ReadReq_misses::cpu1.data 5608 # number of ReadReq misses 155system.l2c.ReadReq_misses::total 22431 # number of ReadReq misses 156system.l2c.UpgradeReq_misses::cpu0.data 4011 # number of UpgradeReq misses 157system.l2c.UpgradeReq_misses::cpu1.data 4908 # number of UpgradeReq misses 158system.l2c.UpgradeReq_misses::total 8919 # number of UpgradeReq misses 159system.l2c.SCUpgradeReq_misses::cpu0.data 652 # number of SCUpgradeReq misses 160system.l2c.SCUpgradeReq_misses::cpu1.data 388 # number of SCUpgradeReq misses 161system.l2c.SCUpgradeReq_misses::total 1040 # number of SCUpgradeReq misses 162system.l2c.ReadExReq_misses::cpu0.data 61450 # number of ReadExReq misses 163system.l2c.ReadExReq_misses::cpu1.data 78839 # number of ReadExReq misses 164system.l2c.ReadExReq_misses::total 140289 # number of ReadExReq misses 165system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses 166system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses 167system.l2c.demand_misses::cpu0.inst 5119 # number of demand (read+write) misses 168system.l2c.demand_misses::cpu0.data 67450 # number of demand (read+write) misses 169system.l2c.demand_misses::cpu1.dtb.walker 3 # number of demand (read+write) misses 170system.l2c.demand_misses::cpu1.inst 5697 # number of demand (read+write) misses 171system.l2c.demand_misses::cpu1.data 84447 # number of demand (read+write) misses 172system.l2c.demand_misses::total 162720 # number of demand (read+write) misses 173system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses 174system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses 175system.l2c.overall_misses::cpu0.inst 5119 # number of overall misses 176system.l2c.overall_misses::cpu0.data 67450 # number of overall misses 177system.l2c.overall_misses::cpu1.dtb.walker 3 # number of overall misses 178system.l2c.overall_misses::cpu1.inst 5697 # number of overall misses 179system.l2c.overall_misses::cpu1.data 84447 # number of overall misses 180system.l2c.overall_misses::total 162720 # number of overall misses 181system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 52000 # number of ReadReq miss cycles 182system.l2c.ReadReq_miss_latency::cpu0.itb.walker 156500 # number of ReadReq miss cycles 183system.l2c.ReadReq_miss_latency::cpu0.inst 267825000 # number of ReadReq miss cycles 184system.l2c.ReadReq_miss_latency::cpu0.data 313081000 # number of ReadReq miss cycles 185system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 156000 # number of ReadReq miss cycles 186system.l2c.ReadReq_miss_latency::cpu1.inst 298083000 # number of ReadReq miss cycles 187system.l2c.ReadReq_miss_latency::cpu1.data 292866500 # number of ReadReq miss cycles 188system.l2c.ReadReq_miss_latency::total 1172220000 # number of ReadReq miss cycles 189system.l2c.UpgradeReq_miss_latency::cpu0.data 15780999 # number of UpgradeReq miss cycles 190system.l2c.UpgradeReq_miss_latency::cpu1.data 31202500 # number of UpgradeReq miss cycles 191system.l2c.UpgradeReq_miss_latency::total 46983499 # number of UpgradeReq miss cycles 192system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1357500 # number of SCUpgradeReq miss cycles 193system.l2c.SCUpgradeReq_miss_latency::cpu1.data 6172500 # number of SCUpgradeReq miss cycles 194system.l2c.SCUpgradeReq_miss_latency::total 7530000 # number of SCUpgradeReq miss cycles 195system.l2c.ReadExReq_miss_latency::cpu0.data 3221673990 # number of ReadExReq miss cycles 196system.l2c.ReadExReq_miss_latency::cpu1.data 4120152496 # number of ReadExReq miss cycles 197system.l2c.ReadExReq_miss_latency::total 7341826486 # number of ReadExReq miss cycles 198system.l2c.demand_miss_latency::cpu0.dtb.walker 52000 # number of demand (read+write) miss cycles 199system.l2c.demand_miss_latency::cpu0.itb.walker 156500 # number of demand (read+write) miss cycles 200system.l2c.demand_miss_latency::cpu0.inst 267825000 # number of demand (read+write) miss cycles 201system.l2c.demand_miss_latency::cpu0.data 3534754990 # number of demand (read+write) miss cycles 202system.l2c.demand_miss_latency::cpu1.dtb.walker 156000 # number of demand (read+write) miss cycles 203system.l2c.demand_miss_latency::cpu1.inst 298083000 # number of demand (read+write) miss cycles 204system.l2c.demand_miss_latency::cpu1.data 4413018996 # number of demand (read+write) miss cycles 205system.l2c.demand_miss_latency::total 8514046486 # number of demand (read+write) miss cycles 206system.l2c.overall_miss_latency::cpu0.dtb.walker 52000 # number of overall miss cycles 207system.l2c.overall_miss_latency::cpu0.itb.walker 156500 # number of overall miss cycles 208system.l2c.overall_miss_latency::cpu0.inst 267825000 # number of overall miss cycles 209system.l2c.overall_miss_latency::cpu0.data 3534754990 # number of overall miss cycles 210system.l2c.overall_miss_latency::cpu1.dtb.walker 156000 # number of overall miss cycles 211system.l2c.overall_miss_latency::cpu1.inst 298083000 # number of overall miss cycles 212system.l2c.overall_miss_latency::cpu1.data 4413018996 # number of overall miss cycles 213system.l2c.overall_miss_latency::total 8514046486 # number of overall miss cycles 214system.l2c.ReadReq_accesses::cpu0.dtb.walker 2524 # number of ReadReq accesses(hits+misses) 215system.l2c.ReadReq_accesses::cpu0.itb.walker 1493 # number of ReadReq accesses(hits+misses) 216system.l2c.ReadReq_accesses::cpu0.inst 283427 # number of ReadReq accesses(hits+misses) 217system.l2c.ReadReq_accesses::cpu0.data 130645 # number of ReadReq accesses(hits+misses) 218system.l2c.ReadReq_accesses::cpu1.dtb.walker 5213 # number of ReadReq accesses(hits+misses) 219system.l2c.ReadReq_accesses::cpu1.itb.walker 1502 # number of ReadReq accesses(hits+misses) 220system.l2c.ReadReq_accesses::cpu1.inst 581919 # number of ReadReq accesses(hits+misses) 221system.l2c.ReadReq_accesses::cpu1.data 228971 # number of ReadReq accesses(hits+misses) 222system.l2c.ReadReq_accesses::total 1235694 # number of ReadReq accesses(hits+misses) 223system.l2c.Writeback_accesses::writebacks 571562 # number of Writeback accesses(hits+misses) 224system.l2c.Writeback_accesses::total 571562 # number of Writeback accesses(hits+misses) 225system.l2c.UpgradeReq_accesses::cpu0.data 5003 # number of UpgradeReq accesses(hits+misses) 226system.l2c.UpgradeReq_accesses::cpu1.data 5786 # number of UpgradeReq accesses(hits+misses) 227system.l2c.UpgradeReq_accesses::total 10789 # number of UpgradeReq accesses(hits+misses) 228system.l2c.SCUpgradeReq_accesses::cpu0.data 841 # number of SCUpgradeReq accesses(hits+misses) 229system.l2c.SCUpgradeReq_accesses::cpu1.data 484 # number of SCUpgradeReq accesses(hits+misses) 230system.l2c.SCUpgradeReq_accesses::total 1325 # number of SCUpgradeReq accesses(hits+misses) 231system.l2c.ReadExReq_accesses::cpu0.data 100681 # number of ReadExReq accesses(hits+misses) 232system.l2c.ReadExReq_accesses::cpu1.data 149083 # number of ReadExReq accesses(hits+misses) 233system.l2c.ReadExReq_accesses::total 249764 # number of ReadExReq accesses(hits+misses) 234system.l2c.demand_accesses::cpu0.dtb.walker 2524 # number of demand (read+write) accesses 235system.l2c.demand_accesses::cpu0.itb.walker 1493 # number of demand (read+write) accesses 236system.l2c.demand_accesses::cpu0.inst 283427 # number of demand (read+write) accesses 237system.l2c.demand_accesses::cpu0.data 231326 # number of demand (read+write) accesses 238system.l2c.demand_accesses::cpu1.dtb.walker 5213 # number of demand (read+write) accesses 239system.l2c.demand_accesses::cpu1.itb.walker 1502 # number of demand (read+write) accesses 240system.l2c.demand_accesses::cpu1.inst 581919 # number of demand (read+write) accesses 241system.l2c.demand_accesses::cpu1.data 378054 # number of demand (read+write) accesses 242system.l2c.demand_accesses::total 1485458 # number of demand (read+write) accesses 243system.l2c.overall_accesses::cpu0.dtb.walker 2524 # number of overall (read+write) accesses 244system.l2c.overall_accesses::cpu0.itb.walker 1493 # number of overall (read+write) accesses 245system.l2c.overall_accesses::cpu0.inst 283427 # number of overall (read+write) accesses 246system.l2c.overall_accesses::cpu0.data 231326 # number of overall (read+write) accesses 247system.l2c.overall_accesses::cpu1.dtb.walker 5213 # number of overall (read+write) accesses 248system.l2c.overall_accesses::cpu1.itb.walker 1502 # number of overall (read+write) accesses 249system.l2c.overall_accesses::cpu1.inst 581919 # number of overall (read+write) accesses 250system.l2c.overall_accesses::cpu1.data 378054 # number of overall (read+write) accesses 251system.l2c.overall_accesses::total 1485458 # number of overall (read+write) accesses 252system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000396 # miss rate for ReadReq accesses 253system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.002009 # miss rate for ReadReq accesses 254system.l2c.ReadReq_miss_rate::cpu0.inst 0.018061 # miss rate for ReadReq accesses 255system.l2c.ReadReq_miss_rate::cpu0.data 0.045926 # miss rate for ReadReq accesses 256system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000575 # miss rate for ReadReq accesses 257system.l2c.ReadReq_miss_rate::cpu1.inst 0.009790 # miss rate for ReadReq accesses 258system.l2c.ReadReq_miss_rate::cpu1.data 0.024492 # miss rate for ReadReq accesses 259system.l2c.ReadReq_miss_rate::total 0.018153 # miss rate for ReadReq accesses 260system.l2c.UpgradeReq_miss_rate::cpu0.data 0.801719 # miss rate for UpgradeReq accesses 261system.l2c.UpgradeReq_miss_rate::cpu1.data 0.848254 # miss rate for UpgradeReq accesses 262system.l2c.UpgradeReq_miss_rate::total 0.826675 # miss rate for UpgradeReq accesses 263system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.775268 # miss rate for SCUpgradeReq accesses 264system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.801653 # miss rate for SCUpgradeReq accesses 265system.l2c.SCUpgradeReq_miss_rate::total 0.784906 # miss rate for SCUpgradeReq accesses 266system.l2c.ReadExReq_miss_rate::cpu0.data 0.610344 # miss rate for ReadExReq accesses 267system.l2c.ReadExReq_miss_rate::cpu1.data 0.528826 # miss rate for ReadExReq accesses 268system.l2c.ReadExReq_miss_rate::total 0.561686 # miss rate for ReadExReq accesses 269system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000396 # miss rate for demand accesses 270system.l2c.demand_miss_rate::cpu0.itb.walker 0.002009 # miss rate for demand accesses 271system.l2c.demand_miss_rate::cpu0.inst 0.018061 # miss rate for demand accesses 272system.l2c.demand_miss_rate::cpu0.data 0.291580 # miss rate for demand accesses 273system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000575 # miss rate for demand accesses 274system.l2c.demand_miss_rate::cpu1.inst 0.009790 # miss rate for demand accesses 275system.l2c.demand_miss_rate::cpu1.data 0.223373 # miss rate for demand accesses 276system.l2c.demand_miss_rate::total 0.109542 # miss rate for demand accesses 277system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000396 # miss rate for overall accesses 278system.l2c.overall_miss_rate::cpu0.itb.walker 0.002009 # miss rate for overall accesses 279system.l2c.overall_miss_rate::cpu0.inst 0.018061 # miss rate for overall accesses 280system.l2c.overall_miss_rate::cpu0.data 0.291580 # miss rate for overall accesses 281system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000575 # miss rate for overall accesses 282system.l2c.overall_miss_rate::cpu1.inst 0.009790 # miss rate for overall accesses 283system.l2c.overall_miss_rate::cpu1.data 0.223373 # miss rate for overall accesses 284system.l2c.overall_miss_rate::total 0.109542 # miss rate for overall accesses 285system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52000 # average ReadReq miss latency 286system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 52166.666667 # average ReadReq miss latency 287system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52319.789021 # average ReadReq miss latency 288system.l2c.ReadReq_avg_miss_latency::cpu0.data 52180.166667 # average ReadReq miss latency 289system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52000 # average ReadReq miss latency 290system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52322.801474 # average ReadReq miss latency 291system.l2c.ReadReq_avg_miss_latency::cpu1.data 52222.985021 # average ReadReq miss latency 292system.l2c.ReadReq_avg_miss_latency::total 52258.927377 # average ReadReq miss latency 293system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3934.430067 # average UpgradeReq miss latency 294system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6357.477588 # average UpgradeReq miss latency 295system.l2c.UpgradeReq_avg_miss_latency::total 5267.798968 # average UpgradeReq miss latency 296system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2082.055215 # average SCUpgradeReq miss latency 297system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 15908.505155 # average SCUpgradeReq miss latency 298system.l2c.SCUpgradeReq_avg_miss_latency::total 7240.384615 # average SCUpgradeReq miss latency 299system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52427.566965 # average ReadExReq miss latency 300system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52260.334302 # average ReadExReq miss latency 301system.l2c.ReadExReq_avg_miss_latency::total 52333.586283 # average ReadExReq miss latency 302system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency 303system.l2c.demand_avg_miss_latency::cpu0.itb.walker 52166.666667 # average overall miss latency 304system.l2c.demand_avg_miss_latency::cpu0.inst 52319.789021 # average overall miss latency 305system.l2c.demand_avg_miss_latency::cpu0.data 52405.559526 # average overall miss latency 306system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52000 # average overall miss latency 307system.l2c.demand_avg_miss_latency::cpu1.inst 52322.801474 # average overall miss latency 308system.l2c.demand_avg_miss_latency::cpu1.data 52257.853991 # average overall miss latency 309system.l2c.demand_avg_miss_latency::total 52323.294530 # average overall miss latency 310system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency 311system.l2c.overall_avg_miss_latency::cpu0.itb.walker 52166.666667 # average overall miss latency 312system.l2c.overall_avg_miss_latency::cpu0.inst 52319.789021 # average overall miss latency 313system.l2c.overall_avg_miss_latency::cpu0.data 52405.559526 # average overall miss latency 314system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52000 # average overall miss latency 315system.l2c.overall_avg_miss_latency::cpu1.inst 52322.801474 # average overall miss latency 316system.l2c.overall_avg_miss_latency::cpu1.data 52257.853991 # average overall miss latency 317system.l2c.overall_avg_miss_latency::total 52323.294530 # average overall miss latency 318system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 319system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 320system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 321system.l2c.blocked::no_targets 0 # number of cycles access was blocked 322system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 323system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 324system.l2c.fast_writes 0 # number of fast writes performed 325system.l2c.cache_copies 0 # number of cache copies performed 326system.l2c.writebacks::writebacks 65061 # number of writebacks 327system.l2c.writebacks::total 65061 # number of writebacks 328system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits 329system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 330system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits 331system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 332system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits 333system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits 334system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1 # number of ReadReq MSHR misses 335system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 3 # number of ReadReq MSHR misses 336system.l2c.ReadReq_mshr_misses::cpu0.inst 5118 # number of ReadReq MSHR misses 337system.l2c.ReadReq_mshr_misses::cpu0.data 6000 # number of ReadReq MSHR misses 338system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 3 # number of ReadReq MSHR misses 339system.l2c.ReadReq_mshr_misses::cpu1.inst 5697 # number of ReadReq MSHR misses 340system.l2c.ReadReq_mshr_misses::cpu1.data 5608 # number of ReadReq MSHR misses 341system.l2c.ReadReq_mshr_misses::total 22430 # number of ReadReq MSHR misses 342system.l2c.UpgradeReq_mshr_misses::cpu0.data 4011 # number of UpgradeReq MSHR misses 343system.l2c.UpgradeReq_mshr_misses::cpu1.data 4908 # number of UpgradeReq MSHR misses 344system.l2c.UpgradeReq_mshr_misses::total 8919 # number of UpgradeReq MSHR misses 345system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 652 # number of SCUpgradeReq MSHR misses 346system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 388 # number of SCUpgradeReq MSHR misses 347system.l2c.SCUpgradeReq_mshr_misses::total 1040 # number of SCUpgradeReq MSHR misses 348system.l2c.ReadExReq_mshr_misses::cpu0.data 61450 # number of ReadExReq MSHR misses 349system.l2c.ReadExReq_mshr_misses::cpu1.data 78839 # number of ReadExReq MSHR misses 350system.l2c.ReadExReq_mshr_misses::total 140289 # number of ReadExReq MSHR misses 351system.l2c.demand_mshr_misses::cpu0.dtb.walker 1 # number of demand (read+write) MSHR misses 352system.l2c.demand_mshr_misses::cpu0.itb.walker 3 # number of demand (read+write) MSHR misses 353system.l2c.demand_mshr_misses::cpu0.inst 5118 # number of demand (read+write) MSHR misses 354system.l2c.demand_mshr_misses::cpu0.data 67450 # number of demand (read+write) MSHR misses 355system.l2c.demand_mshr_misses::cpu1.dtb.walker 3 # number of demand (read+write) MSHR misses 356system.l2c.demand_mshr_misses::cpu1.inst 5697 # number of demand (read+write) MSHR misses 357system.l2c.demand_mshr_misses::cpu1.data 84447 # number of demand (read+write) MSHR misses 358system.l2c.demand_mshr_misses::total 162719 # number of demand (read+write) MSHR misses 359system.l2c.overall_mshr_misses::cpu0.dtb.walker 1 # number of overall MSHR misses 360system.l2c.overall_mshr_misses::cpu0.itb.walker 3 # number of overall MSHR misses 361system.l2c.overall_mshr_misses::cpu0.inst 5118 # number of overall MSHR misses 362system.l2c.overall_mshr_misses::cpu0.data 67450 # number of overall MSHR misses 363system.l2c.overall_mshr_misses::cpu1.dtb.walker 3 # number of overall MSHR misses 364system.l2c.overall_mshr_misses::cpu1.inst 5697 # number of overall MSHR misses 365system.l2c.overall_mshr_misses::cpu1.data 84447 # number of overall MSHR misses 366system.l2c.overall_mshr_misses::total 162719 # number of overall MSHR misses 367system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 40000 # number of ReadReq MSHR miss cycles 368system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 120000 # number of ReadReq MSHR miss cycles 369system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 204790500 # number of ReadReq MSHR miss cycles 370system.l2c.ReadReq_mshr_miss_latency::cpu0.data 240017000 # number of ReadReq MSHR miss cycles 371system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 120000 # number of ReadReq MSHR miss cycles 372system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 227965500 # number of ReadReq MSHR miss cycles 373system.l2c.ReadReq_mshr_miss_latency::cpu1.data 224340500 # number of ReadReq MSHR miss cycles 374system.l2c.ReadReq_mshr_miss_latency::total 897393500 # number of ReadReq MSHR miss cycles 375system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 160489997 # number of UpgradeReq MSHR miss cycles 376system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 196385999 # number of UpgradeReq MSHR miss cycles 377system.l2c.UpgradeReq_mshr_miss_latency::total 356875996 # number of UpgradeReq MSHR miss cycles 378system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 26081499 # number of SCUpgradeReq MSHR miss cycles 379system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 15523499 # number of SCUpgradeReq MSHR miss cycles 380system.l2c.SCUpgradeReq_mshr_miss_latency::total 41604998 # number of SCUpgradeReq MSHR miss cycles 381system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2458644990 # number of ReadExReq MSHR miss cycles 382system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3153935496 # number of ReadExReq MSHR miss cycles 383system.l2c.ReadExReq_mshr_miss_latency::total 5612580486 # number of ReadExReq MSHR miss cycles 384system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 40000 # number of demand (read+write) MSHR miss cycles 385system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 120000 # number of demand (read+write) MSHR miss cycles 386system.l2c.demand_mshr_miss_latency::cpu0.inst 204790500 # number of demand (read+write) MSHR miss cycles 387system.l2c.demand_mshr_miss_latency::cpu0.data 2698661990 # number of demand (read+write) MSHR miss cycles 388system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 120000 # number of demand (read+write) MSHR miss cycles 389system.l2c.demand_mshr_miss_latency::cpu1.inst 227965500 # number of demand (read+write) MSHR miss cycles 390system.l2c.demand_mshr_miss_latency::cpu1.data 3378275996 # number of demand (read+write) MSHR miss cycles 391system.l2c.demand_mshr_miss_latency::total 6509973986 # number of demand (read+write) MSHR miss cycles 392system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 40000 # number of overall MSHR miss cycles 393system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 120000 # number of overall MSHR miss cycles 394system.l2c.overall_mshr_miss_latency::cpu0.inst 204790500 # number of overall MSHR miss cycles 395system.l2c.overall_mshr_miss_latency::cpu0.data 2698661990 # number of overall MSHR miss cycles 396system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 120000 # number of overall MSHR miss cycles 397system.l2c.overall_mshr_miss_latency::cpu1.inst 227965500 # number of overall MSHR miss cycles 398system.l2c.overall_mshr_miss_latency::cpu1.data 3378275996 # number of overall MSHR miss cycles 399system.l2c.overall_mshr_miss_latency::total 6509973986 # number of overall MSHR miss cycles 400system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 265520000 # number of ReadReq MSHR uncacheable cycles 401system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 11136863000 # number of ReadReq MSHR uncacheable cycles 402system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3961500 # number of ReadReq MSHR uncacheable cycles 403system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 155607031000 # number of ReadReq MSHR uncacheable cycles 404system.l2c.ReadReq_mshr_uncacheable_latency::total 167013375500 # number of ReadReq MSHR uncacheable cycles 405system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1070738498 # number of WriteReq MSHR uncacheable cycles 406system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 30849143000 # number of WriteReq MSHR uncacheable cycles 407system.l2c.WriteReq_mshr_uncacheable_latency::total 31919881498 # number of WriteReq MSHR uncacheable cycles 408system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 265520000 # number of overall MSHR uncacheable cycles 409system.l2c.overall_mshr_uncacheable_latency::cpu0.data 12207601498 # number of overall MSHR uncacheable cycles 410system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3961500 # number of overall MSHR uncacheable cycles 411system.l2c.overall_mshr_uncacheable_latency::cpu1.data 186456174000 # number of overall MSHR uncacheable cycles 412system.l2c.overall_mshr_uncacheable_latency::total 198933256998 # number of overall MSHR uncacheable cycles 413system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000396 # mshr miss rate for ReadReq accesses 414system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.002009 # mshr miss rate for ReadReq accesses 415system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.018058 # mshr miss rate for ReadReq accesses 416system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.045926 # mshr miss rate for ReadReq accesses 417system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000575 # mshr miss rate for ReadReq accesses 418system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009790 # mshr miss rate for ReadReq accesses 419system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024492 # mshr miss rate for ReadReq accesses 420system.l2c.ReadReq_mshr_miss_rate::total 0.018152 # mshr miss rate for ReadReq accesses 421system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.801719 # mshr miss rate for UpgradeReq accesses 422system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.848254 # mshr miss rate for UpgradeReq accesses 423system.l2c.UpgradeReq_mshr_miss_rate::total 0.826675 # mshr miss rate for UpgradeReq accesses 424system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.775268 # mshr miss rate for SCUpgradeReq accesses 425system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.801653 # mshr miss rate for SCUpgradeReq accesses 426system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.784906 # mshr miss rate for SCUpgradeReq accesses 427system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.610344 # mshr miss rate for ReadExReq accesses 428system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.528826 # mshr miss rate for ReadExReq accesses 429system.l2c.ReadExReq_mshr_miss_rate::total 0.561686 # mshr miss rate for ReadExReq accesses 430system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000396 # mshr miss rate for demand accesses 431system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.002009 # mshr miss rate for demand accesses 432system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018058 # mshr miss rate for demand accesses 433system.l2c.demand_mshr_miss_rate::cpu0.data 0.291580 # mshr miss rate for demand accesses 434system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000575 # mshr miss rate for demand accesses 435system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009790 # mshr miss rate for demand accesses 436system.l2c.demand_mshr_miss_rate::cpu1.data 0.223373 # mshr miss rate for demand accesses 437system.l2c.demand_mshr_miss_rate::total 0.109541 # mshr miss rate for demand accesses 438system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000396 # mshr miss rate for overall accesses 439system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.002009 # mshr miss rate for overall accesses 440system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018058 # mshr miss rate for overall accesses 441system.l2c.overall_mshr_miss_rate::cpu0.data 0.291580 # mshr miss rate for overall accesses 442system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000575 # mshr miss rate for overall accesses 443system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009790 # mshr miss rate for overall accesses 444system.l2c.overall_mshr_miss_rate::cpu1.data 0.223373 # mshr miss rate for overall accesses 445system.l2c.overall_mshr_miss_rate::total 0.109541 # mshr miss rate for overall accesses 446system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency 447system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average ReadReq mshr miss latency 448system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40013.774912 # average ReadReq mshr miss latency 449system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40002.833333 # average ReadReq mshr miss latency 450system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average ReadReq mshr miss latency 451system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40015.007899 # average ReadReq mshr miss latency 452system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40003.655492 # average ReadReq mshr miss latency 453system.l2c.ReadReq_avg_mshr_miss_latency::total 40008.626839 # average ReadReq mshr miss latency 454system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40012.464971 # average UpgradeReq mshr miss latency 455system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40013.447229 # average UpgradeReq mshr miss latency 456system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40013.005494 # average UpgradeReq mshr miss latency 457system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40002.299080 # average SCUpgradeReq mshr miss latency 458system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40009.018041 # average SCUpgradeReq mshr miss latency 459system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40004.805769 # average SCUpgradeReq mshr miss latency 460system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40010.496176 # average ReadExReq mshr miss latency 461system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40004.762820 # average ReadExReq mshr miss latency 462system.l2c.ReadExReq_avg_mshr_miss_latency::total 40007.274170 # average ReadExReq mshr miss latency 463system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency 464system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency 465system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40013.774912 # average overall mshr miss latency 466system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40009.814529 # average overall mshr miss latency 467system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency 468system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40015.007899 # average overall mshr miss latency 469system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40004.689284 # average overall mshr miss latency 470system.l2c.demand_avg_mshr_miss_latency::total 40007.460628 # average overall mshr miss latency 471system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency 472system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency 473system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40013.774912 # average overall mshr miss latency 474system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40009.814529 # average overall mshr miss latency 475system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency 476system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40015.007899 # average overall mshr miss latency 477system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40004.689284 # average overall mshr miss latency 478system.l2c.overall_avg_mshr_miss_latency::total 40007.460628 # average overall mshr miss latency 479system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 480system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 481system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 482system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 483system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 484system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 485system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 486system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 487system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 488system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 489system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 490system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 491system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 492system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 493system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 494system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 495system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 496system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 497system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 498system.cf0.dma_write_txs 0 # Number of DMA write transactions. 499system.cpu0.dtb.inst_hits 0 # ITB inst hits 500system.cpu0.dtb.inst_misses 0 # ITB inst misses 501system.cpu0.dtb.read_hits 4800569 # DTB read hits 502system.cpu0.dtb.read_misses 2116 # DTB read misses 503system.cpu0.dtb.write_hits 4101188 # DTB write hits 504system.cpu0.dtb.write_misses 405 # DTB write misses 505system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 506system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 507system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 508system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 509system.cpu0.dtb.flush_entries 1539 # Number of entries that have been flushed from TLB 510system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 511system.cpu0.dtb.prefetch_faults 91 # Number of TLB faults due to prefetch 512system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 513system.cpu0.dtb.perms_faults 203 # Number of TLB faults due to permissions restrictions 514system.cpu0.dtb.read_accesses 4802685 # DTB read accesses 515system.cpu0.dtb.write_accesses 4101593 # DTB write accesses 516system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 517system.cpu0.dtb.hits 8901757 # DTB hits 518system.cpu0.dtb.misses 2521 # DTB misses 519system.cpu0.dtb.accesses 8904278 # DTB accesses 520system.cpu0.itb.inst_hits 19425317 # ITB inst hits 521system.cpu0.itb.inst_misses 1350 # ITB inst misses 522system.cpu0.itb.read_hits 0 # DTB read hits 523system.cpu0.itb.read_misses 0 # DTB read misses 524system.cpu0.itb.write_hits 0 # DTB write hits 525system.cpu0.itb.write_misses 0 # DTB write misses 526system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 527system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 528system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 529system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 530system.cpu0.itb.flush_entries 1347 # Number of entries that have been flushed from TLB 531system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 532system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 533system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 534system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 535system.cpu0.itb.read_accesses 0 # DTB read accesses 536system.cpu0.itb.write_accesses 0 # DTB write accesses 537system.cpu0.itb.inst_accesses 19426667 # ITB inst accesses 538system.cpu0.itb.hits 19425317 # DTB hits 539system.cpu0.itb.misses 1350 # DTB misses 540system.cpu0.itb.accesses 19426667 # DTB accesses 541system.cpu0.numCycles 2405785466 # number of cpu cycles simulated 542system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 543system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 544system.cpu0.committedInsts 19048205 # Number of instructions committed 545system.cpu0.committedOps 25051835 # Number of ops (including micro ops) committed 546system.cpu0.num_int_alu_accesses 22684157 # Number of integer alu accesses 547system.cpu0.num_fp_alu_accesses 4364 # Number of float alu accesses 548system.cpu0.num_func_calls 868672 # number of times a function call or return occured 549system.cpu0.num_conditional_control_insts 2620308 # number of instructions that are conditional controls 550system.cpu0.num_int_insts 22684157 # number of integer instructions 551system.cpu0.num_fp_insts 4364 # number of float instructions 552system.cpu0.num_int_register_reads 128951400 # number of times the integer registers were read 553system.cpu0.num_int_register_writes 23731440 # number of times the integer registers were written 554system.cpu0.num_fp_register_reads 3980 # number of times the floating registers were read 555system.cpu0.num_fp_register_writes 384 # number of times the floating registers were written 556system.cpu0.num_mem_refs 9388218 # number of memory refs 557system.cpu0.num_load_insts 5047895 # Number of load instructions 558system.cpu0.num_store_insts 4340323 # Number of store instructions 559system.cpu0.num_idle_cycles 2301327262.807119 # Number of idle cycles 560system.cpu0.num_busy_cycles 104458203.192881 # Number of busy cycles 561system.cpu0.not_idle_fraction 0.043420 # Percentage of non-idle cycles 562system.cpu0.idle_fraction 0.956580 # Percentage of idle cycles 563system.cpu0.kern.inst.arm 0 # number of arm instructions executed 564system.cpu0.kern.inst.quiesce 34019 # number of quiesce instructions executed 565system.cpu0.icache.replacements 283204 # number of replacements 566system.cpu0.icache.tagsinuse 509.502445 # Cycle average of tags in use 567system.cpu0.icache.total_refs 19141584 # Total number of references to valid blocks. 568system.cpu0.icache.sampled_refs 283716 # Sample count of references to valid blocks. 569system.cpu0.icache.avg_refs 67.467411 # Average number of references to valid blocks. 570system.cpu0.icache.warmup_cycle 75588601000 # Cycle when the warmup percentage was hit. 571system.cpu0.icache.occ_blocks::cpu0.inst 509.502445 # Average occupied blocks per requestor 572system.cpu0.icache.occ_percent::cpu0.inst 0.995122 # Average percentage of cache occupancy 573system.cpu0.icache.occ_percent::total 0.995122 # Average percentage of cache occupancy 574system.cpu0.icache.ReadReq_hits::cpu0.inst 19141584 # number of ReadReq hits 575system.cpu0.icache.ReadReq_hits::total 19141584 # number of ReadReq hits 576system.cpu0.icache.demand_hits::cpu0.inst 19141584 # number of demand (read+write) hits 577system.cpu0.icache.demand_hits::total 19141584 # number of demand (read+write) hits 578system.cpu0.icache.overall_hits::cpu0.inst 19141584 # number of overall hits 579system.cpu0.icache.overall_hits::total 19141584 # number of overall hits 580system.cpu0.icache.ReadReq_misses::cpu0.inst 283716 # number of ReadReq misses 581system.cpu0.icache.ReadReq_misses::total 283716 # number of ReadReq misses 582system.cpu0.icache.demand_misses::cpu0.inst 283716 # number of demand (read+write) misses 583system.cpu0.icache.demand_misses::total 283716 # number of demand (read+write) misses 584system.cpu0.icache.overall_misses::cpu0.inst 283716 # number of overall misses 585system.cpu0.icache.overall_misses::total 283716 # number of overall misses 586system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 3929859500 # number of ReadReq miss cycles 587system.cpu0.icache.ReadReq_miss_latency::total 3929859500 # number of ReadReq miss cycles 588system.cpu0.icache.demand_miss_latency::cpu0.inst 3929859500 # number of demand (read+write) miss cycles 589system.cpu0.icache.demand_miss_latency::total 3929859500 # number of demand (read+write) miss cycles 590system.cpu0.icache.overall_miss_latency::cpu0.inst 3929859500 # number of overall miss cycles 591system.cpu0.icache.overall_miss_latency::total 3929859500 # number of overall miss cycles 592system.cpu0.icache.ReadReq_accesses::cpu0.inst 19425300 # number of ReadReq accesses(hits+misses) 593system.cpu0.icache.ReadReq_accesses::total 19425300 # number of ReadReq accesses(hits+misses) 594system.cpu0.icache.demand_accesses::cpu0.inst 19425300 # number of demand (read+write) accesses 595system.cpu0.icache.demand_accesses::total 19425300 # number of demand (read+write) accesses 596system.cpu0.icache.overall_accesses::cpu0.inst 19425300 # number of overall (read+write) accesses 597system.cpu0.icache.overall_accesses::total 19425300 # number of overall (read+write) accesses 598system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014605 # miss rate for ReadReq accesses 599system.cpu0.icache.ReadReq_miss_rate::total 0.014605 # miss rate for ReadReq accesses 600system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014605 # miss rate for demand accesses 601system.cpu0.icache.demand_miss_rate::total 0.014605 # miss rate for demand accesses 602system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014605 # miss rate for overall accesses 603system.cpu0.icache.overall_miss_rate::total 0.014605 # miss rate for overall accesses 604system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13851.384836 # average ReadReq miss latency 605system.cpu0.icache.ReadReq_avg_miss_latency::total 13851.384836 # average ReadReq miss latency 606system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13851.384836 # average overall miss latency 607system.cpu0.icache.demand_avg_miss_latency::total 13851.384836 # average overall miss latency 608system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13851.384836 # average overall miss latency 609system.cpu0.icache.overall_avg_miss_latency::total 13851.384836 # average overall miss latency 610system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 611system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 612system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 613system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 614system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 615system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 616system.cpu0.icache.fast_writes 0 # number of fast writes performed 617system.cpu0.icache.cache_copies 0 # number of cache copies performed 618system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 283716 # number of ReadReq MSHR misses 619system.cpu0.icache.ReadReq_mshr_misses::total 283716 # number of ReadReq MSHR misses 620system.cpu0.icache.demand_mshr_misses::cpu0.inst 283716 # number of demand (read+write) MSHR misses 621system.cpu0.icache.demand_mshr_misses::total 283716 # number of demand (read+write) MSHR misses 622system.cpu0.icache.overall_mshr_misses::cpu0.inst 283716 # number of overall MSHR misses 623system.cpu0.icache.overall_mshr_misses::total 283716 # number of overall MSHR misses 624system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 3362427500 # number of ReadReq MSHR miss cycles 625system.cpu0.icache.ReadReq_mshr_miss_latency::total 3362427500 # number of ReadReq MSHR miss cycles 626system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 3362427500 # number of demand (read+write) MSHR miss cycles 627system.cpu0.icache.demand_mshr_miss_latency::total 3362427500 # number of demand (read+write) MSHR miss cycles 628system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 3362427500 # number of overall MSHR miss cycles 629system.cpu0.icache.overall_mshr_miss_latency::total 3362427500 # number of overall MSHR miss cycles 630system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 353907000 # number of ReadReq MSHR uncacheable cycles 631system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 353907000 # number of ReadReq MSHR uncacheable cycles 632system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 353907000 # number of overall MSHR uncacheable cycles 633system.cpu0.icache.overall_mshr_uncacheable_latency::total 353907000 # number of overall MSHR uncacheable cycles 634system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014605 # mshr miss rate for ReadReq accesses 635system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014605 # mshr miss rate for ReadReq accesses 636system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014605 # mshr miss rate for demand accesses 637system.cpu0.icache.demand_mshr_miss_rate::total 0.014605 # mshr miss rate for demand accesses 638system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014605 # mshr miss rate for overall accesses 639system.cpu0.icache.overall_mshr_miss_rate::total 0.014605 # mshr miss rate for overall accesses 640system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11851.384836 # average ReadReq mshr miss latency 641system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11851.384836 # average ReadReq mshr miss latency 642system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11851.384836 # average overall mshr miss latency 643system.cpu0.icache.demand_avg_mshr_miss_latency::total 11851.384836 # average overall mshr miss latency 644system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11851.384836 # average overall mshr miss latency 645system.cpu0.icache.overall_avg_mshr_miss_latency::total 11851.384836 # average overall mshr miss latency 646system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 647system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 648system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 649system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 650system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 651system.cpu0.dcache.replacements 220249 # number of replacements 652system.cpu0.dcache.tagsinuse 456.517669 # Cycle average of tags in use 653system.cpu0.dcache.total_refs 8560161 # Total number of references to valid blocks. 654system.cpu0.dcache.sampled_refs 220619 # Sample count of references to valid blocks. 655system.cpu0.dcache.avg_refs 38.800652 # Average number of references to valid blocks. 656system.cpu0.dcache.warmup_cycle 656029000 # Cycle when the warmup percentage was hit. 657system.cpu0.dcache.occ_blocks::cpu0.data 456.517669 # Average occupied blocks per requestor 658system.cpu0.dcache.occ_percent::cpu0.data 0.891636 # Average percentage of cache occupancy 659system.cpu0.dcache.occ_percent::total 0.891636 # Average percentage of cache occupancy 660system.cpu0.dcache.ReadReq_hits::cpu0.data 4452439 # number of ReadReq hits 661system.cpu0.dcache.ReadReq_hits::total 4452439 # number of ReadReq hits 662system.cpu0.dcache.WriteReq_hits::cpu0.data 3852551 # number of WriteReq hits 663system.cpu0.dcache.WriteReq_hits::total 3852551 # number of WriteReq hits 664system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 117730 # number of LoadLockedReq hits 665system.cpu0.dcache.LoadLockedReq_hits::total 117730 # number of LoadLockedReq hits 666system.cpu0.dcache.StoreCondReq_hits::cpu0.data 117854 # number of StoreCondReq hits 667system.cpu0.dcache.StoreCondReq_hits::total 117854 # number of StoreCondReq hits 668system.cpu0.dcache.demand_hits::cpu0.data 8304990 # number of demand (read+write) hits 669system.cpu0.dcache.demand_hits::total 8304990 # number of demand (read+write) hits 670system.cpu0.dcache.overall_hits::cpu0.data 8304990 # number of overall hits 671system.cpu0.dcache.overall_hits::total 8304990 # number of overall hits 672system.cpu0.dcache.ReadReq_misses::cpu0.data 146457 # number of ReadReq misses 673system.cpu0.dcache.ReadReq_misses::total 146457 # number of ReadReq misses 674system.cpu0.dcache.WriteReq_misses::cpu0.data 116961 # number of WriteReq misses 675system.cpu0.dcache.WriteReq_misses::total 116961 # number of WriteReq misses 676system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 7881 # number of LoadLockedReq misses 677system.cpu0.dcache.LoadLockedReq_misses::total 7881 # number of LoadLockedReq misses 678system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7692 # number of StoreCondReq misses 679system.cpu0.dcache.StoreCondReq_misses::total 7692 # number of StoreCondReq misses 680system.cpu0.dcache.demand_misses::cpu0.data 263418 # number of demand (read+write) misses 681system.cpu0.dcache.demand_misses::total 263418 # number of demand (read+write) misses 682system.cpu0.dcache.overall_misses::cpu0.data 263418 # number of overall misses 683system.cpu0.dcache.overall_misses::total 263418 # number of overall misses 684system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 1991139500 # number of ReadReq miss cycles 685system.cpu0.dcache.ReadReq_miss_latency::total 1991139500 # number of ReadReq miss cycles 686system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4199443500 # number of WriteReq miss cycles 687system.cpu0.dcache.WriteReq_miss_latency::total 4199443500 # number of WriteReq miss cycles 688system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 70259000 # number of LoadLockedReq miss cycles 689system.cpu0.dcache.LoadLockedReq_miss_latency::total 70259000 # number of LoadLockedReq miss cycles 690system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 66131000 # number of StoreCondReq miss cycles 691system.cpu0.dcache.StoreCondReq_miss_latency::total 66131000 # number of StoreCondReq miss cycles 692system.cpu0.dcache.demand_miss_latency::cpu0.data 6190583000 # number of demand (read+write) miss cycles 693system.cpu0.dcache.demand_miss_latency::total 6190583000 # number of demand (read+write) miss cycles 694system.cpu0.dcache.overall_miss_latency::cpu0.data 6190583000 # number of overall miss cycles 695system.cpu0.dcache.overall_miss_latency::total 6190583000 # number of overall miss cycles 696system.cpu0.dcache.ReadReq_accesses::cpu0.data 4598896 # number of ReadReq accesses(hits+misses) 697system.cpu0.dcache.ReadReq_accesses::total 4598896 # number of ReadReq accesses(hits+misses) 698system.cpu0.dcache.WriteReq_accesses::cpu0.data 3969512 # number of WriteReq accesses(hits+misses) 699system.cpu0.dcache.WriteReq_accesses::total 3969512 # number of WriteReq accesses(hits+misses) 700system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 125611 # number of LoadLockedReq accesses(hits+misses) 701system.cpu0.dcache.LoadLockedReq_accesses::total 125611 # number of LoadLockedReq accesses(hits+misses) 702system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 125546 # number of StoreCondReq accesses(hits+misses) 703system.cpu0.dcache.StoreCondReq_accesses::total 125546 # number of StoreCondReq accesses(hits+misses) 704system.cpu0.dcache.demand_accesses::cpu0.data 8568408 # number of demand (read+write) accesses 705system.cpu0.dcache.demand_accesses::total 8568408 # number of demand (read+write) accesses 706system.cpu0.dcache.overall_accesses::cpu0.data 8568408 # number of overall (read+write) accesses 707system.cpu0.dcache.overall_accesses::total 8568408 # number of overall (read+write) accesses 708system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.031846 # miss rate for ReadReq accesses 709system.cpu0.dcache.ReadReq_miss_rate::total 0.031846 # miss rate for ReadReq accesses 710system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.029465 # miss rate for WriteReq accesses 711system.cpu0.dcache.WriteReq_miss_rate::total 0.029465 # miss rate for WriteReq accesses 712system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.062741 # miss rate for LoadLockedReq accesses 713system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.062741 # miss rate for LoadLockedReq accesses 714system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.061268 # miss rate for StoreCondReq accesses 715system.cpu0.dcache.StoreCondReq_miss_rate::total 0.061268 # miss rate for StoreCondReq accesses 716system.cpu0.dcache.demand_miss_rate::cpu0.data 0.030743 # miss rate for demand accesses 717system.cpu0.dcache.demand_miss_rate::total 0.030743 # miss rate for demand accesses 718system.cpu0.dcache.overall_miss_rate::cpu0.data 0.030743 # miss rate for overall accesses 719system.cpu0.dcache.overall_miss_rate::total 0.030743 # miss rate for overall accesses 720system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13595.386359 # average ReadReq miss latency 721system.cpu0.dcache.ReadReq_avg_miss_latency::total 13595.386359 # average ReadReq miss latency 722system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35904.647703 # average WriteReq miss latency 723system.cpu0.dcache.WriteReq_avg_miss_latency::total 35904.647703 # average WriteReq miss latency 724system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 8914.985408 # average LoadLockedReq miss latency 725system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 8914.985408 # average LoadLockedReq miss latency 726system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8597.373895 # average StoreCondReq miss latency 727system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 8597.373895 # average StoreCondReq miss latency 728system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 23500.987024 # average overall miss latency 729system.cpu0.dcache.demand_avg_miss_latency::total 23500.987024 # average overall miss latency 730system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23500.987024 # average overall miss latency 731system.cpu0.dcache.overall_avg_miss_latency::total 23500.987024 # average overall miss latency 732system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 733system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 734system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 735system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 736system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 737system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 738system.cpu0.dcache.fast_writes 0 # number of fast writes performed 739system.cpu0.dcache.cache_copies 0 # number of cache copies performed 740system.cpu0.dcache.writebacks::writebacks 205058 # number of writebacks 741system.cpu0.dcache.writebacks::total 205058 # number of writebacks 742system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 146457 # number of ReadReq MSHR misses 743system.cpu0.dcache.ReadReq_mshr_misses::total 146457 # number of ReadReq MSHR misses 744system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 116961 # number of WriteReq MSHR misses 745system.cpu0.dcache.WriteReq_mshr_misses::total 116961 # number of WriteReq MSHR misses 746system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 7881 # number of LoadLockedReq MSHR misses 747system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7881 # number of LoadLockedReq MSHR misses 748system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7690 # number of StoreCondReq MSHR misses 749system.cpu0.dcache.StoreCondReq_mshr_misses::total 7690 # number of StoreCondReq MSHR misses 750system.cpu0.dcache.demand_mshr_misses::cpu0.data 263418 # number of demand (read+write) MSHR misses 751system.cpu0.dcache.demand_mshr_misses::total 263418 # number of demand (read+write) MSHR misses 752system.cpu0.dcache.overall_mshr_misses::cpu0.data 263418 # number of overall MSHR misses 753system.cpu0.dcache.overall_mshr_misses::total 263418 # number of overall MSHR misses 754system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 1698225500 # number of ReadReq MSHR miss cycles 755system.cpu0.dcache.ReadReq_mshr_miss_latency::total 1698225500 # number of ReadReq MSHR miss cycles 756system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3965521500 # number of WriteReq MSHR miss cycles 757system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3965521500 # number of WriteReq MSHR miss cycles 758system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 54497000 # number of LoadLockedReq MSHR miss cycles 759system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 54497000 # number of LoadLockedReq MSHR miss cycles 760system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 50753000 # number of StoreCondReq MSHR miss cycles 761system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 50753000 # number of StoreCondReq MSHR miss cycles 762system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles 763system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles 764system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 5663747000 # number of demand (read+write) MSHR miss cycles 765system.cpu0.dcache.demand_mshr_miss_latency::total 5663747000 # number of demand (read+write) MSHR miss cycles 766system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 5663747000 # number of overall MSHR miss cycles 767system.cpu0.dcache.overall_mshr_miss_latency::total 5663747000 # number of overall MSHR miss cycles 768system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 12130745000 # number of ReadReq MSHR uncacheable cycles 769system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 12130745000 # number of ReadReq MSHR uncacheable cycles 770system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1193494500 # number of WriteReq MSHR uncacheable cycles 771system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1193494500 # number of WriteReq MSHR uncacheable cycles 772system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 13324239500 # number of overall MSHR uncacheable cycles 773system.cpu0.dcache.overall_mshr_uncacheable_latency::total 13324239500 # number of overall MSHR uncacheable cycles 774system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.031846 # mshr miss rate for ReadReq accesses 775system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.031846 # mshr miss rate for ReadReq accesses 776system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.029465 # mshr miss rate for WriteReq accesses 777system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.029465 # mshr miss rate for WriteReq accesses 778system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.062741 # mshr miss rate for LoadLockedReq accesses 779system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.062741 # mshr miss rate for LoadLockedReq accesses 780system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.061252 # mshr miss rate for StoreCondReq accesses 781system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.061252 # mshr miss rate for StoreCondReq accesses 782system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030743 # mshr miss rate for demand accesses 783system.cpu0.dcache.demand_mshr_miss_rate::total 0.030743 # mshr miss rate for demand accesses 784system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030743 # mshr miss rate for overall accesses 785system.cpu0.dcache.overall_mshr_miss_rate::total 0.030743 # mshr miss rate for overall accesses 786system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11595.386359 # average ReadReq mshr miss latency 787system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11595.386359 # average ReadReq mshr miss latency 788system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33904.647703 # average WriteReq mshr miss latency 789system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33904.647703 # average WriteReq mshr miss latency 790system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 6914.985408 # average LoadLockedReq mshr miss latency 791system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6914.985408 # average LoadLockedReq mshr miss latency 792system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6599.869961 # average StoreCondReq mshr miss latency 793system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6599.869961 # average StoreCondReq mshr miss latency 794system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 795system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 796system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21500.987024 # average overall mshr miss latency 797system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21500.987024 # average overall mshr miss latency 798system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21500.987024 # average overall mshr miss latency 799system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21500.987024 # average overall mshr miss latency 800system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 801system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 802system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 803system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 804system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 805system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 806system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 807system.cpu1.dtb.inst_hits 0 # ITB inst hits 808system.cpu1.dtb.inst_misses 0 # ITB inst misses 809system.cpu1.dtb.read_hits 10589201 # DTB read hits 810system.cpu1.dtb.read_misses 5231 # DTB read misses 811system.cpu1.dtb.write_hits 7383574 # DTB write hits 812system.cpu1.dtb.write_misses 1834 # DTB write misses 813system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 814system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 815system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 816system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 817system.cpu1.dtb.flush_entries 2257 # Number of entries that have been flushed from TLB 818system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 819system.cpu1.dtb.prefetch_faults 193 # Number of TLB faults due to prefetch 820system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 821system.cpu1.dtb.perms_faults 249 # Number of TLB faults due to permissions restrictions 822system.cpu1.dtb.read_accesses 10594432 # DTB read accesses 823system.cpu1.dtb.write_accesses 7385408 # DTB write accesses 824system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 825system.cpu1.dtb.hits 17972775 # DTB hits 826system.cpu1.dtb.misses 7065 # DTB misses 827system.cpu1.dtb.accesses 17979840 # DTB accesses 828system.cpu1.itb.inst_hits 43338256 # ITB inst hits 829system.cpu1.itb.inst_misses 3017 # ITB inst misses 830system.cpu1.itb.read_hits 0 # DTB read hits 831system.cpu1.itb.read_misses 0 # DTB read misses 832system.cpu1.itb.write_hits 0 # DTB write hits 833system.cpu1.itb.write_misses 0 # DTB write misses 834system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 835system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 836system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 837system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 838system.cpu1.itb.flush_entries 1458 # Number of entries that have been flushed from TLB 839system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 840system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 841system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 842system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 843system.cpu1.itb.read_accesses 0 # DTB read accesses 844system.cpu1.itb.write_accesses 0 # DTB write accesses 845system.cpu1.itb.inst_accesses 43341273 # ITB inst accesses 846system.cpu1.itb.hits 43338256 # DTB hits 847system.cpu1.itb.misses 3017 # DTB misses 848system.cpu1.itb.accesses 43341273 # DTB accesses 849system.cpu1.numCycles 2407212998 # number of cpu cycles simulated 850system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 851system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 852system.cpu1.committedInsts 42407344 # Number of instructions committed 853system.cpu1.committedOps 53266051 # Number of ops (including micro ops) committed 854system.cpu1.num_int_alu_accesses 47734651 # Number of integer alu accesses 855system.cpu1.num_fp_alu_accesses 5457 # Number of float alu accesses 856system.cpu1.num_func_calls 1334953 # number of times a function call or return occured 857system.cpu1.num_conditional_control_insts 5482869 # number of instructions that are conditional controls 858system.cpu1.num_int_insts 47734651 # number of integer instructions 859system.cpu1.num_fp_insts 5457 # number of float instructions 860system.cpu1.num_int_register_reads 274813771 # number of times the integer registers were read 861system.cpu1.num_int_register_writes 51971016 # number of times the integer registers were written 862system.cpu1.num_fp_register_reads 3577 # number of times the floating registers were read 863system.cpu1.num_fp_register_writes 1884 # number of times the floating registers were written 864system.cpu1.num_mem_refs 18681443 # number of memory refs 865system.cpu1.num_load_insts 10999206 # Number of load instructions 866system.cpu1.num_store_insts 7682237 # Number of store instructions 867system.cpu1.num_idle_cycles 1827286039.250482 # Number of idle cycles 868system.cpu1.num_busy_cycles 579926958.749518 # Number of busy cycles 869system.cpu1.not_idle_fraction 0.240912 # Percentage of non-idle cycles 870system.cpu1.idle_fraction 0.759088 # Percentage of idle cycles 871system.cpu1.kern.inst.arm 0 # number of arm instructions executed 872system.cpu1.kern.inst.quiesce 56704 # number of quiesce instructions executed 873system.cpu1.icache.replacements 582576 # number of replacements 874system.cpu1.icache.tagsinuse 479.066528 # Cycle average of tags in use 875system.cpu1.icache.total_refs 42755164 # Total number of references to valid blocks. 876system.cpu1.icache.sampled_refs 583088 # Sample count of references to valid blocks. 877system.cpu1.icache.avg_refs 73.325405 # Average number of references to valid blocks. 878system.cpu1.icache.warmup_cycle 92849627500 # Cycle when the warmup percentage was hit. 879system.cpu1.icache.occ_blocks::cpu1.inst 479.066528 # Average occupied blocks per requestor 880system.cpu1.icache.occ_percent::cpu1.inst 0.935677 # Average percentage of cache occupancy 881system.cpu1.icache.occ_percent::total 0.935677 # Average percentage of cache occupancy 882system.cpu1.icache.ReadReq_hits::cpu1.inst 42755164 # number of ReadReq hits 883system.cpu1.icache.ReadReq_hits::total 42755164 # number of ReadReq hits 884system.cpu1.icache.demand_hits::cpu1.inst 42755164 # number of demand (read+write) hits 885system.cpu1.icache.demand_hits::total 42755164 # number of demand (read+write) hits 886system.cpu1.icache.overall_hits::cpu1.inst 42755164 # number of overall hits 887system.cpu1.icache.overall_hits::total 42755164 # number of overall hits 888system.cpu1.icache.ReadReq_misses::cpu1.inst 583088 # number of ReadReq misses 889system.cpu1.icache.ReadReq_misses::total 583088 # number of ReadReq misses 890system.cpu1.icache.demand_misses::cpu1.inst 583088 # number of demand (read+write) misses 891system.cpu1.icache.demand_misses::total 583088 # number of demand (read+write) misses 892system.cpu1.icache.overall_misses::cpu1.inst 583088 # number of overall misses 893system.cpu1.icache.overall_misses::total 583088 # number of overall misses 894system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7852005500 # number of ReadReq miss cycles 895system.cpu1.icache.ReadReq_miss_latency::total 7852005500 # number of ReadReq miss cycles 896system.cpu1.icache.demand_miss_latency::cpu1.inst 7852005500 # number of demand (read+write) miss cycles 897system.cpu1.icache.demand_miss_latency::total 7852005500 # number of demand (read+write) miss cycles 898system.cpu1.icache.overall_miss_latency::cpu1.inst 7852005500 # number of overall miss cycles 899system.cpu1.icache.overall_miss_latency::total 7852005500 # number of overall miss cycles 900system.cpu1.icache.ReadReq_accesses::cpu1.inst 43338252 # number of ReadReq accesses(hits+misses) 901system.cpu1.icache.ReadReq_accesses::total 43338252 # number of ReadReq accesses(hits+misses) 902system.cpu1.icache.demand_accesses::cpu1.inst 43338252 # number of demand (read+write) accesses 903system.cpu1.icache.demand_accesses::total 43338252 # number of demand (read+write) accesses 904system.cpu1.icache.overall_accesses::cpu1.inst 43338252 # number of overall (read+write) accesses 905system.cpu1.icache.overall_accesses::total 43338252 # number of overall (read+write) accesses 906system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013454 # miss rate for ReadReq accesses 907system.cpu1.icache.ReadReq_miss_rate::total 0.013454 # miss rate for ReadReq accesses 908system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013454 # miss rate for demand accesses 909system.cpu1.icache.demand_miss_rate::total 0.013454 # miss rate for demand accesses 910system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013454 # miss rate for overall accesses 911system.cpu1.icache.overall_miss_rate::total 0.013454 # miss rate for overall accesses 912system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13466.244375 # average ReadReq miss latency 913system.cpu1.icache.ReadReq_avg_miss_latency::total 13466.244375 # average ReadReq miss latency 914system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13466.244375 # average overall miss latency 915system.cpu1.icache.demand_avg_miss_latency::total 13466.244375 # average overall miss latency 916system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13466.244375 # average overall miss latency 917system.cpu1.icache.overall_avg_miss_latency::total 13466.244375 # average overall miss latency 918system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 919system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 920system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 921system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 922system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 923system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 924system.cpu1.icache.fast_writes 0 # number of fast writes performed 925system.cpu1.icache.cache_copies 0 # number of cache copies performed 926system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 583088 # number of ReadReq MSHR misses 927system.cpu1.icache.ReadReq_mshr_misses::total 583088 # number of ReadReq MSHR misses 928system.cpu1.icache.demand_mshr_misses::cpu1.inst 583088 # number of demand (read+write) MSHR misses 929system.cpu1.icache.demand_mshr_misses::total 583088 # number of demand (read+write) MSHR misses 930system.cpu1.icache.overall_mshr_misses::cpu1.inst 583088 # number of overall MSHR misses 931system.cpu1.icache.overall_mshr_misses::total 583088 # number of overall MSHR misses 932system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6685829500 # number of ReadReq MSHR miss cycles 933system.cpu1.icache.ReadReq_mshr_miss_latency::total 6685829500 # number of ReadReq MSHR miss cycles 934system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6685829500 # number of demand (read+write) MSHR miss cycles 935system.cpu1.icache.demand_mshr_miss_latency::total 6685829500 # number of demand (read+write) MSHR miss cycles 936system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6685829500 # number of overall MSHR miss cycles 937system.cpu1.icache.overall_mshr_miss_latency::total 6685829500 # number of overall MSHR miss cycles 938system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5251000 # number of ReadReq MSHR uncacheable cycles 939system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5251000 # number of ReadReq MSHR uncacheable cycles 940system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5251000 # number of overall MSHR uncacheable cycles 941system.cpu1.icache.overall_mshr_uncacheable_latency::total 5251000 # number of overall MSHR uncacheable cycles 942system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013454 # mshr miss rate for ReadReq accesses 943system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013454 # mshr miss rate for ReadReq accesses 944system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013454 # mshr miss rate for demand accesses 945system.cpu1.icache.demand_mshr_miss_rate::total 0.013454 # mshr miss rate for demand accesses 946system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013454 # mshr miss rate for overall accesses 947system.cpu1.icache.overall_mshr_miss_rate::total 0.013454 # mshr miss rate for overall accesses 948system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11466.244375 # average ReadReq mshr miss latency 949system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11466.244375 # average ReadReq mshr miss latency 950system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11466.244375 # average overall mshr miss latency 951system.cpu1.icache.demand_avg_mshr_miss_latency::total 11466.244375 # average overall mshr miss latency 952system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11466.244375 # average overall mshr miss latency 953system.cpu1.icache.overall_avg_mshr_miss_latency::total 11466.244375 # average overall mshr miss latency 954system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 955system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 956system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 957system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 958system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 959system.cpu1.dcache.replacements 401285 # number of replacements 960system.cpu1.dcache.tagsinuse 473.299929 # Cycle average of tags in use 961system.cpu1.dcache.total_refs 15679399 # Total number of references to valid blocks. 962system.cpu1.dcache.sampled_refs 401797 # Sample count of references to valid blocks. 963system.cpu1.dcache.avg_refs 39.023186 # Average number of references to valid blocks. 964system.cpu1.dcache.warmup_cycle 84382221000 # Cycle when the warmup percentage was hit. 965system.cpu1.dcache.occ_blocks::cpu1.data 473.299929 # Average occupied blocks per requestor 966system.cpu1.dcache.occ_percent::cpu1.data 0.924414 # Average percentage of cache occupancy 967system.cpu1.dcache.occ_percent::total 0.924414 # Average percentage of cache occupancy 968system.cpu1.dcache.ReadReq_hits::cpu1.data 9100620 # number of ReadReq hits 969system.cpu1.dcache.ReadReq_hits::total 9100620 # number of ReadReq hits 970system.cpu1.dcache.WriteReq_hits::cpu1.data 6322619 # number of WriteReq hits 971system.cpu1.dcache.WriteReq_hits::total 6322619 # number of WriteReq hits 972system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 111839 # number of LoadLockedReq hits 973system.cpu1.dcache.LoadLockedReq_hits::total 111839 # number of LoadLockedReq hits 974system.cpu1.dcache.StoreCondReq_hits::cpu1.data 114463 # number of StoreCondReq hits 975system.cpu1.dcache.StoreCondReq_hits::total 114463 # number of StoreCondReq hits 976system.cpu1.dcache.demand_hits::cpu1.data 15423239 # number of demand (read+write) hits 977system.cpu1.dcache.demand_hits::total 15423239 # number of demand (read+write) hits 978system.cpu1.dcache.overall_hits::cpu1.data 15423239 # number of overall hits 979system.cpu1.dcache.overall_hits::total 15423239 # number of overall hits 980system.cpu1.dcache.ReadReq_misses::cpu1.data 253127 # number of ReadReq misses 981system.cpu1.dcache.ReadReq_misses::total 253127 # number of ReadReq misses 982system.cpu1.dcache.WriteReq_misses::cpu1.data 178055 # number of WriteReq misses 983system.cpu1.dcache.WriteReq_misses::total 178055 # number of WriteReq misses 984system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13099 # number of LoadLockedReq misses 985system.cpu1.dcache.LoadLockedReq_misses::total 13099 # number of LoadLockedReq misses 986system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10399 # number of StoreCondReq misses 987system.cpu1.dcache.StoreCondReq_misses::total 10399 # number of StoreCondReq misses 988system.cpu1.dcache.demand_misses::cpu1.data 431182 # number of demand (read+write) misses 989system.cpu1.dcache.demand_misses::total 431182 # number of demand (read+write) misses 990system.cpu1.dcache.overall_misses::cpu1.data 431182 # number of overall misses 991system.cpu1.dcache.overall_misses::total 431182 # number of overall misses 992system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3277248500 # number of ReadReq miss cycles 993system.cpu1.dcache.ReadReq_miss_latency::total 3277248500 # number of ReadReq miss cycles 994system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5648876500 # number of WriteReq miss cycles 995system.cpu1.dcache.WriteReq_miss_latency::total 5648876500 # number of WriteReq miss cycles 996system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 115793500 # number of LoadLockedReq miss cycles 997system.cpu1.dcache.LoadLockedReq_miss_latency::total 115793500 # number of LoadLockedReq miss cycles 998system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 63008000 # number of StoreCondReq miss cycles 999system.cpu1.dcache.StoreCondReq_miss_latency::total 63008000 # number of StoreCondReq miss cycles 1000system.cpu1.dcache.demand_miss_latency::cpu1.data 8926125000 # number of demand (read+write) miss cycles 1001system.cpu1.dcache.demand_miss_latency::total 8926125000 # number of demand (read+write) miss cycles 1002system.cpu1.dcache.overall_miss_latency::cpu1.data 8926125000 # number of overall miss cycles 1003system.cpu1.dcache.overall_miss_latency::total 8926125000 # number of overall miss cycles 1004system.cpu1.dcache.ReadReq_accesses::cpu1.data 9353747 # number of ReadReq accesses(hits+misses) 1005system.cpu1.dcache.ReadReq_accesses::total 9353747 # number of ReadReq accesses(hits+misses) 1006system.cpu1.dcache.WriteReq_accesses::cpu1.data 6500674 # number of WriteReq accesses(hits+misses) 1007system.cpu1.dcache.WriteReq_accesses::total 6500674 # number of WriteReq accesses(hits+misses) 1008system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 124938 # number of LoadLockedReq accesses(hits+misses) 1009system.cpu1.dcache.LoadLockedReq_accesses::total 124938 # number of LoadLockedReq accesses(hits+misses) 1010system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 124862 # number of StoreCondReq accesses(hits+misses) 1011system.cpu1.dcache.StoreCondReq_accesses::total 124862 # number of StoreCondReq accesses(hits+misses) 1012system.cpu1.dcache.demand_accesses::cpu1.data 15854421 # number of demand (read+write) accesses 1013system.cpu1.dcache.demand_accesses::total 15854421 # number of demand (read+write) accesses 1014system.cpu1.dcache.overall_accesses::cpu1.data 15854421 # number of overall (read+write) accesses 1015system.cpu1.dcache.overall_accesses::total 15854421 # number of overall (read+write) accesses 1016system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.027062 # miss rate for ReadReq accesses 1017system.cpu1.dcache.ReadReq_miss_rate::total 0.027062 # miss rate for ReadReq accesses 1018system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027390 # miss rate for WriteReq accesses 1019system.cpu1.dcache.WriteReq_miss_rate::total 0.027390 # miss rate for WriteReq accesses 1020system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.104844 # miss rate for LoadLockedReq accesses 1021system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.104844 # miss rate for LoadLockedReq accesses 1022system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.083284 # miss rate for StoreCondReq accesses 1023system.cpu1.dcache.StoreCondReq_miss_rate::total 0.083284 # miss rate for StoreCondReq accesses 1024system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027196 # miss rate for demand accesses 1025system.cpu1.dcache.demand_miss_rate::total 0.027196 # miss rate for demand accesses 1026system.cpu1.dcache.overall_miss_rate::cpu1.data 0.027196 # miss rate for overall accesses 1027system.cpu1.dcache.overall_miss_rate::total 0.027196 # miss rate for overall accesses 1028system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12947.052270 # average ReadReq miss latency 1029system.cpu1.dcache.ReadReq_avg_miss_latency::total 12947.052270 # average ReadReq miss latency 1030system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 31725.458426 # average WriteReq miss latency 1031system.cpu1.dcache.WriteReq_avg_miss_latency::total 31725.458426 # average WriteReq miss latency 1032system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8839.873273 # average LoadLockedReq miss latency 1033system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8839.873273 # average LoadLockedReq miss latency 1034system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 6059.044139 # average StoreCondReq miss latency 1035system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 6059.044139 # average StoreCondReq miss latency 1036system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20701.525110 # average overall miss latency 1037system.cpu1.dcache.demand_avg_miss_latency::total 20701.525110 # average overall miss latency 1038system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20701.525110 # average overall miss latency 1039system.cpu1.dcache.overall_avg_miss_latency::total 20701.525110 # average overall miss latency 1040system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1041system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1042system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1043system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1044system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1045system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1046system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1047system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1048system.cpu1.dcache.writebacks::writebacks 366504 # number of writebacks 1049system.cpu1.dcache.writebacks::total 366504 # number of writebacks 1050system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 253127 # number of ReadReq MSHR misses 1051system.cpu1.dcache.ReadReq_mshr_misses::total 253127 # number of ReadReq MSHR misses 1052system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 178055 # number of WriteReq MSHR misses 1053system.cpu1.dcache.WriteReq_mshr_misses::total 178055 # number of WriteReq MSHR misses 1054system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 13099 # number of LoadLockedReq MSHR misses 1055system.cpu1.dcache.LoadLockedReq_mshr_misses::total 13099 # number of LoadLockedReq MSHR misses 1056system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10394 # number of StoreCondReq MSHR misses 1057system.cpu1.dcache.StoreCondReq_mshr_misses::total 10394 # number of StoreCondReq MSHR misses 1058system.cpu1.dcache.demand_mshr_misses::cpu1.data 431182 # number of demand (read+write) MSHR misses 1059system.cpu1.dcache.demand_mshr_misses::total 431182 # number of demand (read+write) MSHR misses 1060system.cpu1.dcache.overall_mshr_misses::cpu1.data 431182 # number of overall MSHR misses 1061system.cpu1.dcache.overall_mshr_misses::total 431182 # number of overall MSHR misses 1062system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2770994500 # number of ReadReq MSHR miss cycles 1063system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2770994500 # number of ReadReq MSHR miss cycles 1064system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5292766500 # number of WriteReq MSHR miss cycles 1065system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5292766500 # number of WriteReq MSHR miss cycles 1066system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89595500 # number of LoadLockedReq MSHR miss cycles 1067system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89595500 # number of LoadLockedReq MSHR miss cycles 1068system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 42224000 # number of StoreCondReq MSHR miss cycles 1069system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 42224000 # number of StoreCondReq MSHR miss cycles 1070system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2000 # number of StoreCondFailReq MSHR miss cycles 1071system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2000 # number of StoreCondFailReq MSHR miss cycles 1072system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8063761000 # number of demand (read+write) MSHR miss cycles 1073system.cpu1.dcache.demand_mshr_miss_latency::total 8063761000 # number of demand (read+write) MSHR miss cycles 1074system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8063761000 # number of overall MSHR miss cycles 1075system.cpu1.dcache.overall_mshr_miss_latency::total 8063761000 # number of overall MSHR miss cycles 1076system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 170066366500 # number of ReadReq MSHR uncacheable cycles 1077system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 170066366500 # number of ReadReq MSHR uncacheable cycles 1078system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 40314514000 # number of WriteReq MSHR uncacheable cycles 1079system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 40314514000 # number of WriteReq MSHR uncacheable cycles 1080system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 210380880500 # number of overall MSHR uncacheable cycles 1081system.cpu1.dcache.overall_mshr_uncacheable_latency::total 210380880500 # number of overall MSHR uncacheable cycles 1082system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027062 # mshr miss rate for ReadReq accesses 1083system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.027062 # mshr miss rate for ReadReq accesses 1084system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027390 # mshr miss rate for WriteReq accesses 1085system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027390 # mshr miss rate for WriteReq accesses 1086system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.104844 # mshr miss rate for LoadLockedReq accesses 1087system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.104844 # mshr miss rate for LoadLockedReq accesses 1088system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.083244 # mshr miss rate for StoreCondReq accesses 1089system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.083244 # mshr miss rate for StoreCondReq accesses 1090system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027196 # mshr miss rate for demand accesses 1091system.cpu1.dcache.demand_mshr_miss_rate::total 0.027196 # mshr miss rate for demand accesses 1092system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027196 # mshr miss rate for overall accesses 1093system.cpu1.dcache.overall_mshr_miss_rate::total 0.027196 # mshr miss rate for overall accesses 1094system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10947.052270 # average ReadReq mshr miss latency 1095system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10947.052270 # average ReadReq mshr miss latency 1096system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29725.458426 # average WriteReq mshr miss latency 1097system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 29725.458426 # average WriteReq mshr miss latency 1098system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6839.873273 # average LoadLockedReq mshr miss latency 1099system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6839.873273 # average LoadLockedReq mshr miss latency 1100system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4062.343660 # average StoreCondReq mshr miss latency 1101system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4062.343660 # average StoreCondReq mshr miss latency 1102system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1103system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1104system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18701.525110 # average overall mshr miss latency 1105system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18701.525110 # average overall mshr miss latency 1106system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18701.525110 # average overall mshr miss latency 1107system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18701.525110 # average overall mshr miss latency 1108system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1109system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1110system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1111system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1112system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1113system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1114system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1115system.iocache.replacements 0 # number of replacements 1116system.iocache.tagsinuse 0 # Cycle average of tags in use 1117system.iocache.total_refs 0 # Total number of references to valid blocks. 1118system.iocache.sampled_refs 0 # Sample count of references to valid blocks. 1119system.iocache.avg_refs nan # Average number of references to valid blocks. 1120system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1121system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1122system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1123system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1124system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1125system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1126system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1127system.iocache.fast_writes 0 # number of fast writes performed 1128system.iocache.cache_copies 0 # number of cache copies performed 1129system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 522347967555 # number of ReadReq MSHR uncacheable cycles 1130system.iocache.ReadReq_mshr_uncacheable_latency::total 522347967555 # number of ReadReq MSHR uncacheable cycles 1131system.iocache.overall_mshr_uncacheable_latency::realview.clcd 522347967555 # number of overall MSHR uncacheable cycles 1132system.iocache.overall_mshr_uncacheable_latency::total 522347967555 # number of overall MSHR uncacheable cycles 1133system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1134system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1135system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1136system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1137system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1138 1139---------- End Simulation Statistics ---------- 1140