stats.txt revision 9005:f681719e2e99
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.169707 # Number of seconds simulated 4sim_ticks 1169707043000 # Number of ticks simulated 5final_tick 1169707043000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 754175 # Simulator instruction rate (inst/s) 8host_op_rate 964493 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 14598169556 # Simulator tick rate (ticks/s) 10host_mem_usage 379804 # Number of bytes of host memory used 11host_seconds 80.13 # Real time elapsed on the host 12sim_insts 60429704 # Number of instructions simulated 13sim_ops 77281862 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 61898788 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 1004992 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 10078928 # Number of bytes written to this memory 17system.physmem.num_reads 6478591 # Number of read requests responded to by this memory 18system.physmem.num_writes 867017 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory 20system.physmem.bw_read 52918197 # Total read bandwidth from this memory (bytes/s) 21system.physmem.bw_inst_read 859183 # Instruction read bandwidth from this memory (bytes/s) 22system.physmem.bw_write 8616626 # Write bandwidth from this memory (bytes/s) 23system.physmem.bw_total 61534823 # Total bandwidth to/from this memory (bytes/s) 24system.realview.nvmem.bytes_read 68 # Number of bytes read from this memory 25system.realview.nvmem.bytes_inst_read 68 # Number of instructions bytes read from this memory 26system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory 27system.realview.nvmem.num_reads 17 # Number of read requests responded to by this memory 28system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory 29system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory 30system.realview.nvmem.bw_read 58 # Total read bandwidth from this memory (bytes/s) 31system.realview.nvmem.bw_inst_read 58 # Instruction read bandwidth from this memory (bytes/s) 32system.realview.nvmem.bw_total 58 # Total bandwidth to/from this memory (bytes/s) 33system.l2c.replacements 125934 # number of replacements 34system.l2c.tagsinuse 27532.100282 # Cycle average of tags in use 35system.l2c.total_refs 1500548 # Total number of references to valid blocks. 36system.l2c.sampled_refs 155551 # Sample count of references to valid blocks. 37system.l2c.avg_refs 9.646663 # Average number of references to valid blocks. 38system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 39system.l2c.occ_blocks::writebacks 17789.012398 # Average occupied blocks per requestor 40system.l2c.occ_blocks::cpu0.dtb.walker 1.363432 # Average occupied blocks per requestor 41system.l2c.occ_blocks::cpu0.itb.walker 0.117594 # Average occupied blocks per requestor 42system.l2c.occ_blocks::cpu0.inst 2294.743571 # Average occupied blocks per requestor 43system.l2c.occ_blocks::cpu0.data 2778.537805 # Average occupied blocks per requestor 44system.l2c.occ_blocks::cpu1.dtb.walker 5.252408 # Average occupied blocks per requestor 45system.l2c.occ_blocks::cpu1.itb.walker 0.023319 # Average occupied blocks per requestor 46system.l2c.occ_blocks::cpu1.inst 2406.434925 # Average occupied blocks per requestor 47system.l2c.occ_blocks::cpu1.data 2256.614830 # Average occupied blocks per requestor 48system.l2c.occ_percent::writebacks 0.271439 # Average percentage of cache occupancy 49system.l2c.occ_percent::cpu0.dtb.walker 0.000021 # Average percentage of cache occupancy 50system.l2c.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy 51system.l2c.occ_percent::cpu0.inst 0.035015 # Average percentage of cache occupancy 52system.l2c.occ_percent::cpu0.data 0.042397 # Average percentage of cache occupancy 53system.l2c.occ_percent::cpu1.dtb.walker 0.000080 # Average percentage of cache occupancy 54system.l2c.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy 55system.l2c.occ_percent::cpu1.inst 0.036719 # Average percentage of cache occupancy 56system.l2c.occ_percent::cpu1.data 0.034433 # Average percentage of cache occupancy 57system.l2c.occ_percent::total 0.420107 # Average percentage of cache occupancy 58system.l2c.ReadReq_hits::cpu0.dtb.walker 4097 # number of ReadReq hits 59system.l2c.ReadReq_hits::cpu0.itb.walker 1763 # number of ReadReq hits 60system.l2c.ReadReq_hits::cpu0.inst 399350 # number of ReadReq hits 61system.l2c.ReadReq_hits::cpu0.data 205866 # number of ReadReq hits 62system.l2c.ReadReq_hits::cpu1.dtb.walker 5680 # number of ReadReq hits 63system.l2c.ReadReq_hits::cpu1.itb.walker 1949 # number of ReadReq hits 64system.l2c.ReadReq_hits::cpu1.inst 446193 # number of ReadReq hits 65system.l2c.ReadReq_hits::cpu1.data 140780 # number of ReadReq hits 66system.l2c.ReadReq_hits::total 1205678 # number of ReadReq hits 67system.l2c.Writeback_hits::writebacks 577354 # number of Writeback hits 68system.l2c.Writeback_hits::total 577354 # number of Writeback hits 69system.l2c.UpgradeReq_hits::cpu0.data 1189 # number of UpgradeReq hits 70system.l2c.UpgradeReq_hits::cpu1.data 549 # number of UpgradeReq hits 71system.l2c.UpgradeReq_hits::total 1738 # number of UpgradeReq hits 72system.l2c.SCUpgradeReq_hits::cpu0.data 223 # number of SCUpgradeReq hits 73system.l2c.SCUpgradeReq_hits::cpu1.data 193 # number of SCUpgradeReq hits 74system.l2c.SCUpgradeReq_hits::total 416 # number of SCUpgradeReq hits 75system.l2c.ReadExReq_hits::cpu0.data 53827 # number of ReadExReq hits 76system.l2c.ReadExReq_hits::cpu1.data 49705 # number of ReadExReq hits 77system.l2c.ReadExReq_hits::total 103532 # number of ReadExReq hits 78system.l2c.demand_hits::cpu0.dtb.walker 4097 # number of demand (read+write) hits 79system.l2c.demand_hits::cpu0.itb.walker 1763 # number of demand (read+write) hits 80system.l2c.demand_hits::cpu0.inst 399350 # number of demand (read+write) hits 81system.l2c.demand_hits::cpu0.data 259693 # number of demand (read+write) hits 82system.l2c.demand_hits::cpu1.dtb.walker 5680 # number of demand (read+write) hits 83system.l2c.demand_hits::cpu1.itb.walker 1949 # number of demand (read+write) hits 84system.l2c.demand_hits::cpu1.inst 446193 # number of demand (read+write) hits 85system.l2c.demand_hits::cpu1.data 190485 # number of demand (read+write) hits 86system.l2c.demand_hits::total 1309210 # number of demand (read+write) hits 87system.l2c.overall_hits::cpu0.dtb.walker 4097 # number of overall hits 88system.l2c.overall_hits::cpu0.itb.walker 1763 # number of overall hits 89system.l2c.overall_hits::cpu0.inst 399350 # number of overall hits 90system.l2c.overall_hits::cpu0.data 259693 # number of overall hits 91system.l2c.overall_hits::cpu1.dtb.walker 5680 # number of overall hits 92system.l2c.overall_hits::cpu1.itb.walker 1949 # number of overall hits 93system.l2c.overall_hits::cpu1.inst 446193 # number of overall hits 94system.l2c.overall_hits::cpu1.data 190485 # number of overall hits 95system.l2c.overall_hits::total 1309210 # number of overall hits 96system.l2c.ReadReq_misses::cpu0.dtb.walker 10 # number of ReadReq misses 97system.l2c.ReadReq_misses::cpu0.itb.walker 4 # number of ReadReq misses 98system.l2c.ReadReq_misses::cpu0.inst 7942 # number of ReadReq misses 99system.l2c.ReadReq_misses::cpu0.data 11318 # number of ReadReq misses 100system.l2c.ReadReq_misses::cpu1.dtb.walker 18 # number of ReadReq misses 101system.l2c.ReadReq_misses::cpu1.itb.walker 5 # number of ReadReq misses 102system.l2c.ReadReq_misses::cpu1.inst 7342 # number of ReadReq misses 103system.l2c.ReadReq_misses::cpu1.data 8301 # number of ReadReq misses 104system.l2c.ReadReq_misses::total 34940 # number of ReadReq misses 105system.l2c.UpgradeReq_misses::cpu0.data 4674 # number of UpgradeReq misses 106system.l2c.UpgradeReq_misses::cpu1.data 3622 # number of UpgradeReq misses 107system.l2c.UpgradeReq_misses::total 8296 # number of UpgradeReq misses 108system.l2c.SCUpgradeReq_misses::cpu0.data 567 # number of SCUpgradeReq misses 109system.l2c.SCUpgradeReq_misses::cpu1.data 452 # number of SCUpgradeReq misses 110system.l2c.SCUpgradeReq_misses::total 1019 # number of SCUpgradeReq misses 111system.l2c.ReadExReq_misses::cpu0.data 71101 # number of ReadExReq misses 112system.l2c.ReadExReq_misses::cpu1.data 76239 # number of ReadExReq misses 113system.l2c.ReadExReq_misses::total 147340 # number of ReadExReq misses 114system.l2c.demand_misses::cpu0.dtb.walker 10 # number of demand (read+write) misses 115system.l2c.demand_misses::cpu0.itb.walker 4 # number of demand (read+write) misses 116system.l2c.demand_misses::cpu0.inst 7942 # number of demand (read+write) misses 117system.l2c.demand_misses::cpu0.data 82419 # number of demand (read+write) misses 118system.l2c.demand_misses::cpu1.dtb.walker 18 # number of demand (read+write) misses 119system.l2c.demand_misses::cpu1.itb.walker 5 # number of demand (read+write) misses 120system.l2c.demand_misses::cpu1.inst 7342 # number of demand (read+write) misses 121system.l2c.demand_misses::cpu1.data 84540 # number of demand (read+write) misses 122system.l2c.demand_misses::total 182280 # number of demand (read+write) misses 123system.l2c.overall_misses::cpu0.dtb.walker 10 # number of overall misses 124system.l2c.overall_misses::cpu0.itb.walker 4 # number of overall misses 125system.l2c.overall_misses::cpu0.inst 7942 # number of overall misses 126system.l2c.overall_misses::cpu0.data 82419 # number of overall misses 127system.l2c.overall_misses::cpu1.dtb.walker 18 # number of overall misses 128system.l2c.overall_misses::cpu1.itb.walker 5 # number of overall misses 129system.l2c.overall_misses::cpu1.inst 7342 # number of overall misses 130system.l2c.overall_misses::cpu1.data 84540 # number of overall misses 131system.l2c.overall_misses::total 182280 # number of overall misses 132system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 520000 # number of ReadReq miss cycles 133system.l2c.ReadReq_miss_latency::cpu0.itb.walker 208500 # number of ReadReq miss cycles 134system.l2c.ReadReq_miss_latency::cpu0.inst 414166000 # number of ReadReq miss cycles 135system.l2c.ReadReq_miss_latency::cpu0.data 589465000 # number of ReadReq miss cycles 136system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 940000 # number of ReadReq miss cycles 137system.l2c.ReadReq_miss_latency::cpu1.itb.walker 260000 # number of ReadReq miss cycles 138system.l2c.ReadReq_miss_latency::cpu1.inst 383790500 # number of ReadReq miss cycles 139system.l2c.ReadReq_miss_latency::cpu1.data 432860500 # number of ReadReq miss cycles 140system.l2c.ReadReq_miss_latency::total 1822210500 # number of ReadReq miss cycles 141system.l2c.UpgradeReq_miss_latency::cpu0.data 30607000 # number of UpgradeReq miss cycles 142system.l2c.UpgradeReq_miss_latency::cpu1.data 30466000 # number of UpgradeReq miss cycles 143system.l2c.UpgradeReq_miss_latency::total 61073000 # number of UpgradeReq miss cycles 144system.l2c.SCUpgradeReq_miss_latency::cpu0.data 4060000 # number of SCUpgradeReq miss cycles 145system.l2c.SCUpgradeReq_miss_latency::cpu1.data 5045000 # number of SCUpgradeReq miss cycles 146system.l2c.SCUpgradeReq_miss_latency::total 9105000 # number of SCUpgradeReq miss cycles 147system.l2c.ReadExReq_miss_latency::cpu0.data 3700498000 # number of ReadExReq miss cycles 148system.l2c.ReadExReq_miss_latency::cpu1.data 3973370000 # number of ReadExReq miss cycles 149system.l2c.ReadExReq_miss_latency::total 7673868000 # number of ReadExReq miss cycles 150system.l2c.demand_miss_latency::cpu0.dtb.walker 520000 # number of demand (read+write) miss cycles 151system.l2c.demand_miss_latency::cpu0.itb.walker 208500 # number of demand (read+write) miss cycles 152system.l2c.demand_miss_latency::cpu0.inst 414166000 # number of demand (read+write) miss cycles 153system.l2c.demand_miss_latency::cpu0.data 4289963000 # number of demand (read+write) miss cycles 154system.l2c.demand_miss_latency::cpu1.dtb.walker 940000 # number of demand (read+write) miss cycles 155system.l2c.demand_miss_latency::cpu1.itb.walker 260000 # number of demand (read+write) miss cycles 156system.l2c.demand_miss_latency::cpu1.inst 383790500 # number of demand (read+write) miss cycles 157system.l2c.demand_miss_latency::cpu1.data 4406230500 # number of demand (read+write) miss cycles 158system.l2c.demand_miss_latency::total 9496078500 # number of demand (read+write) miss cycles 159system.l2c.overall_miss_latency::cpu0.dtb.walker 520000 # number of overall miss cycles 160system.l2c.overall_miss_latency::cpu0.itb.walker 208500 # number of overall miss cycles 161system.l2c.overall_miss_latency::cpu0.inst 414166000 # number of overall miss cycles 162system.l2c.overall_miss_latency::cpu0.data 4289963000 # number of overall miss cycles 163system.l2c.overall_miss_latency::cpu1.dtb.walker 940000 # number of overall miss cycles 164system.l2c.overall_miss_latency::cpu1.itb.walker 260000 # number of overall miss cycles 165system.l2c.overall_miss_latency::cpu1.inst 383790500 # number of overall miss cycles 166system.l2c.overall_miss_latency::cpu1.data 4406230500 # number of overall miss cycles 167system.l2c.overall_miss_latency::total 9496078500 # number of overall miss cycles 168system.l2c.ReadReq_accesses::cpu0.dtb.walker 4107 # number of ReadReq accesses(hits+misses) 169system.l2c.ReadReq_accesses::cpu0.itb.walker 1767 # number of ReadReq accesses(hits+misses) 170system.l2c.ReadReq_accesses::cpu0.inst 407292 # number of ReadReq accesses(hits+misses) 171system.l2c.ReadReq_accesses::cpu0.data 217184 # number of ReadReq accesses(hits+misses) 172system.l2c.ReadReq_accesses::cpu1.dtb.walker 5698 # number of ReadReq accesses(hits+misses) 173system.l2c.ReadReq_accesses::cpu1.itb.walker 1954 # number of ReadReq accesses(hits+misses) 174system.l2c.ReadReq_accesses::cpu1.inst 453535 # number of ReadReq accesses(hits+misses) 175system.l2c.ReadReq_accesses::cpu1.data 149081 # number of ReadReq accesses(hits+misses) 176system.l2c.ReadReq_accesses::total 1240618 # number of ReadReq accesses(hits+misses) 177system.l2c.Writeback_accesses::writebacks 577354 # number of Writeback accesses(hits+misses) 178system.l2c.Writeback_accesses::total 577354 # number of Writeback accesses(hits+misses) 179system.l2c.UpgradeReq_accesses::cpu0.data 5863 # number of UpgradeReq accesses(hits+misses) 180system.l2c.UpgradeReq_accesses::cpu1.data 4171 # number of UpgradeReq accesses(hits+misses) 181system.l2c.UpgradeReq_accesses::total 10034 # number of UpgradeReq accesses(hits+misses) 182system.l2c.SCUpgradeReq_accesses::cpu0.data 790 # number of SCUpgradeReq accesses(hits+misses) 183system.l2c.SCUpgradeReq_accesses::cpu1.data 645 # number of SCUpgradeReq accesses(hits+misses) 184system.l2c.SCUpgradeReq_accesses::total 1435 # number of SCUpgradeReq accesses(hits+misses) 185system.l2c.ReadExReq_accesses::cpu0.data 124928 # number of ReadExReq accesses(hits+misses) 186system.l2c.ReadExReq_accesses::cpu1.data 125944 # number of ReadExReq accesses(hits+misses) 187system.l2c.ReadExReq_accesses::total 250872 # number of ReadExReq accesses(hits+misses) 188system.l2c.demand_accesses::cpu0.dtb.walker 4107 # number of demand (read+write) accesses 189system.l2c.demand_accesses::cpu0.itb.walker 1767 # number of demand (read+write) accesses 190system.l2c.demand_accesses::cpu0.inst 407292 # number of demand (read+write) accesses 191system.l2c.demand_accesses::cpu0.data 342112 # number of demand (read+write) accesses 192system.l2c.demand_accesses::cpu1.dtb.walker 5698 # number of demand (read+write) accesses 193system.l2c.demand_accesses::cpu1.itb.walker 1954 # number of demand (read+write) accesses 194system.l2c.demand_accesses::cpu1.inst 453535 # number of demand (read+write) accesses 195system.l2c.demand_accesses::cpu1.data 275025 # number of demand (read+write) accesses 196system.l2c.demand_accesses::total 1491490 # number of demand (read+write) accesses 197system.l2c.overall_accesses::cpu0.dtb.walker 4107 # number of overall (read+write) accesses 198system.l2c.overall_accesses::cpu0.itb.walker 1767 # number of overall (read+write) accesses 199system.l2c.overall_accesses::cpu0.inst 407292 # number of overall (read+write) accesses 200system.l2c.overall_accesses::cpu0.data 342112 # number of overall (read+write) accesses 201system.l2c.overall_accesses::cpu1.dtb.walker 5698 # number of overall (read+write) accesses 202system.l2c.overall_accesses::cpu1.itb.walker 1954 # number of overall (read+write) accesses 203system.l2c.overall_accesses::cpu1.inst 453535 # number of overall (read+write) accesses 204system.l2c.overall_accesses::cpu1.data 275025 # number of overall (read+write) accesses 205system.l2c.overall_accesses::total 1491490 # number of overall (read+write) accesses 206system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.002435 # miss rate for ReadReq accesses 207system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.002264 # miss rate for ReadReq accesses 208system.l2c.ReadReq_miss_rate::cpu0.inst 0.019500 # miss rate for ReadReq accesses 209system.l2c.ReadReq_miss_rate::cpu0.data 0.052112 # miss rate for ReadReq accesses 210system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.003159 # miss rate for ReadReq accesses 211system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.002559 # miss rate for ReadReq accesses 212system.l2c.ReadReq_miss_rate::cpu1.inst 0.016188 # miss rate for ReadReq accesses 213system.l2c.ReadReq_miss_rate::cpu1.data 0.055681 # miss rate for ReadReq accesses 214system.l2c.UpgradeReq_miss_rate::cpu0.data 0.797203 # miss rate for UpgradeReq accesses 215system.l2c.UpgradeReq_miss_rate::cpu1.data 0.868377 # miss rate for UpgradeReq accesses 216system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.717722 # miss rate for SCUpgradeReq accesses 217system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.700775 # miss rate for SCUpgradeReq accesses 218system.l2c.ReadExReq_miss_rate::cpu0.data 0.569136 # miss rate for ReadExReq accesses 219system.l2c.ReadExReq_miss_rate::cpu1.data 0.605340 # miss rate for ReadExReq accesses 220system.l2c.demand_miss_rate::cpu0.dtb.walker 0.002435 # miss rate for demand accesses 221system.l2c.demand_miss_rate::cpu0.itb.walker 0.002264 # miss rate for demand accesses 222system.l2c.demand_miss_rate::cpu0.inst 0.019500 # miss rate for demand accesses 223system.l2c.demand_miss_rate::cpu0.data 0.240912 # miss rate for demand accesses 224system.l2c.demand_miss_rate::cpu1.dtb.walker 0.003159 # miss rate for demand accesses 225system.l2c.demand_miss_rate::cpu1.itb.walker 0.002559 # miss rate for demand accesses 226system.l2c.demand_miss_rate::cpu1.inst 0.016188 # miss rate for demand accesses 227system.l2c.demand_miss_rate::cpu1.data 0.307390 # miss rate for demand accesses 228system.l2c.overall_miss_rate::cpu0.dtb.walker 0.002435 # miss rate for overall accesses 229system.l2c.overall_miss_rate::cpu0.itb.walker 0.002264 # miss rate for overall accesses 230system.l2c.overall_miss_rate::cpu0.inst 0.019500 # miss rate for overall accesses 231system.l2c.overall_miss_rate::cpu0.data 0.240912 # miss rate for overall accesses 232system.l2c.overall_miss_rate::cpu1.dtb.walker 0.003159 # miss rate for overall accesses 233system.l2c.overall_miss_rate::cpu1.itb.walker 0.002559 # miss rate for overall accesses 234system.l2c.overall_miss_rate::cpu1.inst 0.016188 # miss rate for overall accesses 235system.l2c.overall_miss_rate::cpu1.data 0.307390 # miss rate for overall accesses 236system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52000 # average ReadReq miss latency 237system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 52125 # average ReadReq miss latency 238system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52148.829010 # average ReadReq miss latency 239system.l2c.ReadReq_avg_miss_latency::cpu0.data 52082.081640 # average ReadReq miss latency 240system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52222.222222 # average ReadReq miss latency 241system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 52000 # average ReadReq miss latency 242system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52273.290656 # average ReadReq miss latency 243system.l2c.ReadReq_avg_miss_latency::cpu1.data 52145.584869 # average ReadReq miss latency 244system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6548.352589 # average UpgradeReq miss latency 245system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 8411.374931 # average UpgradeReq miss latency 246system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 7160.493827 # average SCUpgradeReq miss latency 247system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 11161.504425 # average SCUpgradeReq miss latency 248system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52045.653366 # average ReadExReq miss latency 249system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52117.289052 # average ReadExReq miss latency 250system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency 251system.l2c.demand_avg_miss_latency::cpu0.itb.walker 52125 # average overall miss latency 252system.l2c.demand_avg_miss_latency::cpu0.inst 52148.829010 # average overall miss latency 253system.l2c.demand_avg_miss_latency::cpu0.data 52050.655795 # average overall miss latency 254system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52222.222222 # average overall miss latency 255system.l2c.demand_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency 256system.l2c.demand_avg_miss_latency::cpu1.inst 52273.290656 # average overall miss latency 257system.l2c.demand_avg_miss_latency::cpu1.data 52120.067424 # average overall miss latency 258system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency 259system.l2c.overall_avg_miss_latency::cpu0.itb.walker 52125 # average overall miss latency 260system.l2c.overall_avg_miss_latency::cpu0.inst 52148.829010 # average overall miss latency 261system.l2c.overall_avg_miss_latency::cpu0.data 52050.655795 # average overall miss latency 262system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52222.222222 # average overall miss latency 263system.l2c.overall_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency 264system.l2c.overall_avg_miss_latency::cpu1.inst 52273.290656 # average overall miss latency 265system.l2c.overall_avg_miss_latency::cpu1.data 52120.067424 # average overall miss latency 266system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 267system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 268system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 269system.l2c.blocked::no_targets 0 # number of cycles access was blocked 270system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 271system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 272system.l2c.fast_writes 0 # number of fast writes performed 273system.l2c.cache_copies 0 # number of cache copies performed 274system.l2c.writebacks::writebacks 110181 # number of writebacks 275system.l2c.writebacks::total 110181 # number of writebacks 276system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits 277system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 278system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits 279system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 280system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits 281system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits 282system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 10 # number of ReadReq MSHR misses 283system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 4 # number of ReadReq MSHR misses 284system.l2c.ReadReq_mshr_misses::cpu0.inst 7941 # number of ReadReq MSHR misses 285system.l2c.ReadReq_mshr_misses::cpu0.data 11318 # number of ReadReq MSHR misses 286system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 18 # number of ReadReq MSHR misses 287system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 5 # number of ReadReq MSHR misses 288system.l2c.ReadReq_mshr_misses::cpu1.inst 7342 # number of ReadReq MSHR misses 289system.l2c.ReadReq_mshr_misses::cpu1.data 8301 # number of ReadReq MSHR misses 290system.l2c.ReadReq_mshr_misses::total 34939 # number of ReadReq MSHR misses 291system.l2c.UpgradeReq_mshr_misses::cpu0.data 4674 # number of UpgradeReq MSHR misses 292system.l2c.UpgradeReq_mshr_misses::cpu1.data 3622 # number of UpgradeReq MSHR misses 293system.l2c.UpgradeReq_mshr_misses::total 8296 # number of UpgradeReq MSHR misses 294system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 567 # number of SCUpgradeReq MSHR misses 295system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 452 # number of SCUpgradeReq MSHR misses 296system.l2c.SCUpgradeReq_mshr_misses::total 1019 # number of SCUpgradeReq MSHR misses 297system.l2c.ReadExReq_mshr_misses::cpu0.data 71101 # number of ReadExReq MSHR misses 298system.l2c.ReadExReq_mshr_misses::cpu1.data 76239 # number of ReadExReq MSHR misses 299system.l2c.ReadExReq_mshr_misses::total 147340 # number of ReadExReq MSHR misses 300system.l2c.demand_mshr_misses::cpu0.dtb.walker 10 # number of demand (read+write) MSHR misses 301system.l2c.demand_mshr_misses::cpu0.itb.walker 4 # number of demand (read+write) MSHR misses 302system.l2c.demand_mshr_misses::cpu0.inst 7941 # number of demand (read+write) MSHR misses 303system.l2c.demand_mshr_misses::cpu0.data 82419 # number of demand (read+write) MSHR misses 304system.l2c.demand_mshr_misses::cpu1.dtb.walker 18 # number of demand (read+write) MSHR misses 305system.l2c.demand_mshr_misses::cpu1.itb.walker 5 # number of demand (read+write) MSHR misses 306system.l2c.demand_mshr_misses::cpu1.inst 7342 # number of demand (read+write) MSHR misses 307system.l2c.demand_mshr_misses::cpu1.data 84540 # number of demand (read+write) MSHR misses 308system.l2c.demand_mshr_misses::total 182279 # number of demand (read+write) MSHR misses 309system.l2c.overall_mshr_misses::cpu0.dtb.walker 10 # number of overall MSHR misses 310system.l2c.overall_mshr_misses::cpu0.itb.walker 4 # number of overall MSHR misses 311system.l2c.overall_mshr_misses::cpu0.inst 7941 # number of overall MSHR misses 312system.l2c.overall_mshr_misses::cpu0.data 82419 # number of overall MSHR misses 313system.l2c.overall_mshr_misses::cpu1.dtb.walker 18 # number of overall MSHR misses 314system.l2c.overall_mshr_misses::cpu1.itb.walker 5 # number of overall MSHR misses 315system.l2c.overall_mshr_misses::cpu1.inst 7342 # number of overall MSHR misses 316system.l2c.overall_mshr_misses::cpu1.data 84540 # number of overall MSHR misses 317system.l2c.overall_mshr_misses::total 182279 # number of overall MSHR misses 318system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 400000 # number of ReadReq MSHR miss cycles 319system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 160000 # number of ReadReq MSHR miss cycles 320system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 318844000 # number of ReadReq MSHR miss cycles 321system.l2c.ReadReq_mshr_miss_latency::cpu0.data 453649000 # number of ReadReq MSHR miss cycles 322system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 724000 # number of ReadReq MSHR miss cycles 323system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 200000 # number of ReadReq MSHR miss cycles 324system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 295681000 # number of ReadReq MSHR miss cycles 325system.l2c.ReadReq_mshr_miss_latency::cpu1.data 333248000 # number of ReadReq MSHR miss cycles 326system.l2c.ReadReq_mshr_miss_latency::total 1402906000 # number of ReadReq MSHR miss cycles 327system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 187154000 # number of UpgradeReq MSHR miss cycles 328system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 145115000 # number of UpgradeReq MSHR miss cycles 329system.l2c.UpgradeReq_mshr_miss_latency::total 332269000 # number of UpgradeReq MSHR miss cycles 330system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 22686000 # number of SCUpgradeReq MSHR miss cycles 331system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 18114000 # number of SCUpgradeReq MSHR miss cycles 332system.l2c.SCUpgradeReq_mshr_miss_latency::total 40800000 # number of SCUpgradeReq MSHR miss cycles 333system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2847286000 # number of ReadExReq MSHR miss cycles 334system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3058502000 # number of ReadExReq MSHR miss cycles 335system.l2c.ReadExReq_mshr_miss_latency::total 5905788000 # number of ReadExReq MSHR miss cycles 336system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 400000 # number of demand (read+write) MSHR miss cycles 337system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 160000 # number of demand (read+write) MSHR miss cycles 338system.l2c.demand_mshr_miss_latency::cpu0.inst 318844000 # number of demand (read+write) MSHR miss cycles 339system.l2c.demand_mshr_miss_latency::cpu0.data 3300935000 # number of demand (read+write) MSHR miss cycles 340system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 724000 # number of demand (read+write) MSHR miss cycles 341system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 200000 # number of demand (read+write) MSHR miss cycles 342system.l2c.demand_mshr_miss_latency::cpu1.inst 295681000 # number of demand (read+write) MSHR miss cycles 343system.l2c.demand_mshr_miss_latency::cpu1.data 3391750000 # number of demand (read+write) MSHR miss cycles 344system.l2c.demand_mshr_miss_latency::total 7308694000 # number of demand (read+write) MSHR miss cycles 345system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 400000 # number of overall MSHR miss cycles 346system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 160000 # number of overall MSHR miss cycles 347system.l2c.overall_mshr_miss_latency::cpu0.inst 318844000 # number of overall MSHR miss cycles 348system.l2c.overall_mshr_miss_latency::cpu0.data 3300935000 # number of overall MSHR miss cycles 349system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 724000 # number of overall MSHR miss cycles 350system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 200000 # number of overall MSHR miss cycles 351system.l2c.overall_mshr_miss_latency::cpu1.inst 295681000 # number of overall MSHR miss cycles 352system.l2c.overall_mshr_miss_latency::cpu1.data 3391750000 # number of overall MSHR miss cycles 353system.l2c.overall_mshr_miss_latency::total 7308694000 # number of overall MSHR miss cycles 354system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 265520000 # number of ReadReq MSHR uncacheable cycles 355system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 9316699500 # number of ReadReq MSHR uncacheable cycles 356system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3961000 # number of ReadReq MSHR uncacheable cycles 357system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 122238098500 # number of ReadReq MSHR uncacheable cycles 358system.l2c.ReadReq_mshr_uncacheable_latency::total 131824279000 # number of ReadReq MSHR uncacheable cycles 359system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 699595000 # number of WriteReq MSHR uncacheable cycles 360system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 30626242500 # number of WriteReq MSHR uncacheable cycles 361system.l2c.WriteReq_mshr_uncacheable_latency::total 31325837500 # number of WriteReq MSHR uncacheable cycles 362system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 265520000 # number of overall MSHR uncacheable cycles 363system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10016294500 # number of overall MSHR uncacheable cycles 364system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3961000 # number of overall MSHR uncacheable cycles 365system.l2c.overall_mshr_uncacheable_latency::cpu1.data 152864341000 # number of overall MSHR uncacheable cycles 366system.l2c.overall_mshr_uncacheable_latency::total 163150116500 # number of overall MSHR uncacheable cycles 367system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.002435 # mshr miss rate for ReadReq accesses 368system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.002264 # mshr miss rate for ReadReq accesses 369system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.019497 # mshr miss rate for ReadReq accesses 370system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.052112 # mshr miss rate for ReadReq accesses 371system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.003159 # mshr miss rate for ReadReq accesses 372system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.002559 # mshr miss rate for ReadReq accesses 373system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.016188 # mshr miss rate for ReadReq accesses 374system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.055681 # mshr miss rate for ReadReq accesses 375system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.797203 # mshr miss rate for UpgradeReq accesses 376system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.868377 # mshr miss rate for UpgradeReq accesses 377system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.717722 # mshr miss rate for SCUpgradeReq accesses 378system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.700775 # mshr miss rate for SCUpgradeReq accesses 379system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.569136 # mshr miss rate for ReadExReq accesses 380system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.605340 # mshr miss rate for ReadExReq accesses 381system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.002435 # mshr miss rate for demand accesses 382system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.002264 # mshr miss rate for demand accesses 383system.l2c.demand_mshr_miss_rate::cpu0.inst 0.019497 # mshr miss rate for demand accesses 384system.l2c.demand_mshr_miss_rate::cpu0.data 0.240912 # mshr miss rate for demand accesses 385system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.003159 # mshr miss rate for demand accesses 386system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.002559 # mshr miss rate for demand accesses 387system.l2c.demand_mshr_miss_rate::cpu1.inst 0.016188 # mshr miss rate for demand accesses 388system.l2c.demand_mshr_miss_rate::cpu1.data 0.307390 # mshr miss rate for demand accesses 389system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.002435 # mshr miss rate for overall accesses 390system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.002264 # mshr miss rate for overall accesses 391system.l2c.overall_mshr_miss_rate::cpu0.inst 0.019497 # mshr miss rate for overall accesses 392system.l2c.overall_mshr_miss_rate::cpu0.data 0.240912 # mshr miss rate for overall accesses 393system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.003159 # mshr miss rate for overall accesses 394system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.002559 # mshr miss rate for overall accesses 395system.l2c.overall_mshr_miss_rate::cpu1.inst 0.016188 # mshr miss rate for overall accesses 396system.l2c.overall_mshr_miss_rate::cpu1.data 0.307390 # mshr miss rate for overall accesses 397system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency 398system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average ReadReq mshr miss latency 399system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40151.618184 # average ReadReq mshr miss latency 400system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40082.081640 # average ReadReq mshr miss latency 401system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40222.222222 # average ReadReq mshr miss latency 402system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average ReadReq mshr miss latency 403system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40272.541542 # average ReadReq mshr miss latency 404system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40145.524636 # average ReadReq mshr miss latency 405system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40041.506205 # average UpgradeReq mshr miss latency 406system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40064.881281 # average UpgradeReq mshr miss latency 407system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40010.582011 # average SCUpgradeReq mshr miss latency 408system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40075.221239 # average SCUpgradeReq mshr miss latency 409system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40045.653366 # average ReadExReq mshr miss latency 410system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40117.289052 # average ReadExReq mshr miss latency 411system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency 412system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency 413system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40151.618184 # average overall mshr miss latency 414system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40050.655795 # average overall mshr miss latency 415system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40222.222222 # average overall mshr miss latency 416system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency 417system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40272.541542 # average overall mshr miss latency 418system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40120.061509 # average overall mshr miss latency 419system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency 420system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency 421system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40151.618184 # average overall mshr miss latency 422system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40050.655795 # average overall mshr miss latency 423system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40222.222222 # average overall mshr miss latency 424system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency 425system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40272.541542 # average overall mshr miss latency 426system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40120.061509 # average overall mshr miss latency 427system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 428system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 429system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 430system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 431system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 432system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 433system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 434system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 435system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 436system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 437system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 438system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 439system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 440system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 441system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 442system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 443system.cf0.dma_write_txs 0 # Number of DMA write transactions. 444system.cpu0.dtb.inst_hits 0 # ITB inst hits 445system.cpu0.dtb.inst_misses 0 # ITB inst misses 446system.cpu0.dtb.read_hits 7070142 # DTB read hits 447system.cpu0.dtb.read_misses 3739 # DTB read misses 448system.cpu0.dtb.write_hits 5655287 # DTB write hits 449system.cpu0.dtb.write_misses 802 # DTB write misses 450system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 451system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 452system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 453system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 454system.cpu0.dtb.flush_entries 1791 # Number of entries that have been flushed from TLB 455system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 456system.cpu0.dtb.prefetch_faults 143 # Number of TLB faults due to prefetch 457system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 458system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions 459system.cpu0.dtb.read_accesses 7073881 # DTB read accesses 460system.cpu0.dtb.write_accesses 5656089 # DTB write accesses 461system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 462system.cpu0.dtb.hits 12725429 # DTB hits 463system.cpu0.dtb.misses 4541 # DTB misses 464system.cpu0.dtb.accesses 12729970 # DTB accesses 465system.cpu0.itb.inst_hits 29439632 # ITB inst hits 466system.cpu0.itb.inst_misses 2205 # ITB inst misses 467system.cpu0.itb.read_hits 0 # DTB read hits 468system.cpu0.itb.read_misses 0 # DTB read misses 469system.cpu0.itb.write_hits 0 # DTB write hits 470system.cpu0.itb.write_misses 0 # DTB write misses 471system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 472system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 473system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 474system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 475system.cpu0.itb.flush_entries 1332 # Number of entries that have been flushed from TLB 476system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 477system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 478system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 479system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 480system.cpu0.itb.read_accesses 0 # DTB read accesses 481system.cpu0.itb.write_accesses 0 # DTB write accesses 482system.cpu0.itb.inst_accesses 29441837 # ITB inst accesses 483system.cpu0.itb.hits 29439632 # DTB hits 484system.cpu0.itb.misses 2205 # DTB misses 485system.cpu0.itb.accesses 29441837 # DTB accesses 486system.cpu0.numCycles 2339414086 # number of cpu cycles simulated 487system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 488system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 489system.cpu0.committedInsts 28747266 # Number of instructions committed 490system.cpu0.committedOps 37085213 # Number of ops (including micro ops) committed 491system.cpu0.num_int_alu_accesses 33031535 # Number of integer alu accesses 492system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses 493system.cpu0.num_func_calls 1116936 # number of times a function call or return occured 494system.cpu0.num_conditional_control_insts 4321526 # number of instructions that are conditional controls 495system.cpu0.num_int_insts 33031535 # number of integer instructions 496system.cpu0.num_fp_insts 3860 # number of float instructions 497system.cpu0.num_int_register_reads 189616194 # number of times the integer registers were read 498system.cpu0.num_int_register_writes 36089294 # number of times the integer registers were written 499system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read 500system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written 501system.cpu0.num_mem_refs 13393398 # number of memory refs 502system.cpu0.num_load_insts 7407664 # Number of load instructions 503system.cpu0.num_store_insts 5985734 # Number of store instructions 504system.cpu0.num_idle_cycles 2203122575.338117 # Number of idle cycles 505system.cpu0.num_busy_cycles 136291510.661883 # Number of busy cycles 506system.cpu0.not_idle_fraction 0.058259 # Percentage of non-idle cycles 507system.cpu0.idle_fraction 0.941741 # Percentage of idle cycles 508system.cpu0.kern.inst.arm 0 # number of arm instructions executed 509system.cpu0.kern.inst.quiesce 46688 # number of quiesce instructions executed 510system.cpu0.icache.replacements 408172 # number of replacements 511system.cpu0.icache.tagsinuse 509.512645 # Cycle average of tags in use 512system.cpu0.icache.total_refs 29030930 # Total number of references to valid blocks. 513system.cpu0.icache.sampled_refs 408684 # Sample count of references to valid blocks. 514system.cpu0.icache.avg_refs 71.035152 # Average number of references to valid blocks. 515system.cpu0.icache.warmup_cycle 74928815000 # Cycle when the warmup percentage was hit. 516system.cpu0.icache.occ_blocks::cpu0.inst 509.512645 # Average occupied blocks per requestor 517system.cpu0.icache.occ_percent::cpu0.inst 0.995142 # Average percentage of cache occupancy 518system.cpu0.icache.occ_percent::total 0.995142 # Average percentage of cache occupancy 519system.cpu0.icache.ReadReq_hits::cpu0.inst 29030930 # number of ReadReq hits 520system.cpu0.icache.ReadReq_hits::total 29030930 # number of ReadReq hits 521system.cpu0.icache.demand_hits::cpu0.inst 29030930 # number of demand (read+write) hits 522system.cpu0.icache.demand_hits::total 29030930 # number of demand (read+write) hits 523system.cpu0.icache.overall_hits::cpu0.inst 29030930 # number of overall hits 524system.cpu0.icache.overall_hits::total 29030930 # number of overall hits 525system.cpu0.icache.ReadReq_misses::cpu0.inst 408685 # number of ReadReq misses 526system.cpu0.icache.ReadReq_misses::total 408685 # number of ReadReq misses 527system.cpu0.icache.demand_misses::cpu0.inst 408685 # number of demand (read+write) misses 528system.cpu0.icache.demand_misses::total 408685 # number of demand (read+write) misses 529system.cpu0.icache.overall_misses::cpu0.inst 408685 # number of overall misses 530system.cpu0.icache.overall_misses::total 408685 # number of overall misses 531system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6059464500 # number of ReadReq miss cycles 532system.cpu0.icache.ReadReq_miss_latency::total 6059464500 # number of ReadReq miss cycles 533system.cpu0.icache.demand_miss_latency::cpu0.inst 6059464500 # number of demand (read+write) miss cycles 534system.cpu0.icache.demand_miss_latency::total 6059464500 # number of demand (read+write) miss cycles 535system.cpu0.icache.overall_miss_latency::cpu0.inst 6059464500 # number of overall miss cycles 536system.cpu0.icache.overall_miss_latency::total 6059464500 # number of overall miss cycles 537system.cpu0.icache.ReadReq_accesses::cpu0.inst 29439615 # number of ReadReq accesses(hits+misses) 538system.cpu0.icache.ReadReq_accesses::total 29439615 # number of ReadReq accesses(hits+misses) 539system.cpu0.icache.demand_accesses::cpu0.inst 29439615 # number of demand (read+write) accesses 540system.cpu0.icache.demand_accesses::total 29439615 # number of demand (read+write) accesses 541system.cpu0.icache.overall_accesses::cpu0.inst 29439615 # number of overall (read+write) accesses 542system.cpu0.icache.overall_accesses::total 29439615 # number of overall (read+write) accesses 543system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013882 # miss rate for ReadReq accesses 544system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013882 # miss rate for demand accesses 545system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013882 # miss rate for overall accesses 546system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14826.735750 # average ReadReq miss latency 547system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14826.735750 # average overall miss latency 548system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14826.735750 # average overall miss latency 549system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 550system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 551system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 552system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 553system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 554system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 555system.cpu0.icache.fast_writes 0 # number of fast writes performed 556system.cpu0.icache.cache_copies 0 # number of cache copies performed 557system.cpu0.icache.writebacks::writebacks 16458 # number of writebacks 558system.cpu0.icache.writebacks::total 16458 # number of writebacks 559system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 408685 # number of ReadReq MSHR misses 560system.cpu0.icache.ReadReq_mshr_misses::total 408685 # number of ReadReq MSHR misses 561system.cpu0.icache.demand_mshr_misses::cpu0.inst 408685 # number of demand (read+write) MSHR misses 562system.cpu0.icache.demand_mshr_misses::total 408685 # number of demand (read+write) MSHR misses 563system.cpu0.icache.overall_mshr_misses::cpu0.inst 408685 # number of overall MSHR misses 564system.cpu0.icache.overall_mshr_misses::total 408685 # number of overall MSHR misses 565system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4832163500 # number of ReadReq MSHR miss cycles 566system.cpu0.icache.ReadReq_mshr_miss_latency::total 4832163500 # number of ReadReq MSHR miss cycles 567system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4832163500 # number of demand (read+write) MSHR miss cycles 568system.cpu0.icache.demand_mshr_miss_latency::total 4832163500 # number of demand (read+write) MSHR miss cycles 569system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4832163500 # number of overall MSHR miss cycles 570system.cpu0.icache.overall_mshr_miss_latency::total 4832163500 # number of overall MSHR miss cycles 571system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 351814000 # number of ReadReq MSHR uncacheable cycles 572system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 351814000 # number of ReadReq MSHR uncacheable cycles 573system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 351814000 # number of overall MSHR uncacheable cycles 574system.cpu0.icache.overall_mshr_uncacheable_latency::total 351814000 # number of overall MSHR uncacheable cycles 575system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013882 # mshr miss rate for ReadReq accesses 576system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013882 # mshr miss rate for demand accesses 577system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013882 # mshr miss rate for overall accesses 578system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11823.686947 # average ReadReq mshr miss latency 579system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11823.686947 # average overall mshr miss latency 580system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11823.686947 # average overall mshr miss latency 581system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 582system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 583system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 584system.cpu0.dcache.replacements 335831 # number of replacements 585system.cpu0.dcache.tagsinuse 404.122879 # Cycle average of tags in use 586system.cpu0.dcache.total_refs 12265513 # Total number of references to valid blocks. 587system.cpu0.dcache.sampled_refs 336343 # Sample count of references to valid blocks. 588system.cpu0.dcache.avg_refs 36.467276 # Average number of references to valid blocks. 589system.cpu0.dcache.warmup_cycle 663204000 # Cycle when the warmup percentage was hit. 590system.cpu0.dcache.occ_blocks::cpu0.data 404.122879 # Average occupied blocks per requestor 591system.cpu0.dcache.occ_percent::cpu0.data 0.789302 # Average percentage of cache occupancy 592system.cpu0.dcache.occ_percent::total 0.789302 # Average percentage of cache occupancy 593system.cpu0.dcache.ReadReq_hits::cpu0.data 6596660 # number of ReadReq hits 594system.cpu0.dcache.ReadReq_hits::total 6596660 # number of ReadReq hits 595system.cpu0.dcache.WriteReq_hits::cpu0.data 5349249 # number of WriteReq hits 596system.cpu0.dcache.WriteReq_hits::total 5349249 # number of WriteReq hits 597system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147717 # number of LoadLockedReq hits 598system.cpu0.dcache.LoadLockedReq_hits::total 147717 # number of LoadLockedReq hits 599system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149695 # number of StoreCondReq hits 600system.cpu0.dcache.StoreCondReq_hits::total 149695 # number of StoreCondReq hits 601system.cpu0.dcache.demand_hits::cpu0.data 11945909 # number of demand (read+write) hits 602system.cpu0.dcache.demand_hits::total 11945909 # number of demand (read+write) hits 603system.cpu0.dcache.overall_hits::cpu0.data 11945909 # number of overall hits 604system.cpu0.dcache.overall_hits::total 11945909 # number of overall hits 605system.cpu0.dcache.ReadReq_misses::cpu0.data 231189 # number of ReadReq misses 606system.cpu0.dcache.ReadReq_misses::total 231189 # number of ReadReq misses 607system.cpu0.dcache.WriteReq_misses::cpu0.data 142616 # number of WriteReq misses 608system.cpu0.dcache.WriteReq_misses::total 142616 # number of WriteReq misses 609system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9505 # number of LoadLockedReq misses 610system.cpu0.dcache.LoadLockedReq_misses::total 9505 # number of LoadLockedReq misses 611system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7464 # number of StoreCondReq misses 612system.cpu0.dcache.StoreCondReq_misses::total 7464 # number of StoreCondReq misses 613system.cpu0.dcache.demand_misses::cpu0.data 373805 # number of demand (read+write) misses 614system.cpu0.dcache.demand_misses::total 373805 # number of demand (read+write) misses 615system.cpu0.dcache.overall_misses::cpu0.data 373805 # number of overall misses 616system.cpu0.dcache.overall_misses::total 373805 # number of overall misses 617system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3541904000 # number of ReadReq miss cycles 618system.cpu0.dcache.ReadReq_miss_latency::total 3541904000 # number of ReadReq miss cycles 619system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5075999000 # number of WriteReq miss cycles 620system.cpu0.dcache.WriteReq_miss_latency::total 5075999000 # number of WriteReq miss cycles 621system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 104931000 # number of LoadLockedReq miss cycles 622system.cpu0.dcache.LoadLockedReq_miss_latency::total 104931000 # number of LoadLockedReq miss cycles 623system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 68264000 # number of StoreCondReq miss cycles 624system.cpu0.dcache.StoreCondReq_miss_latency::total 68264000 # number of StoreCondReq miss cycles 625system.cpu0.dcache.demand_miss_latency::cpu0.data 8617903000 # number of demand (read+write) miss cycles 626system.cpu0.dcache.demand_miss_latency::total 8617903000 # number of demand (read+write) miss cycles 627system.cpu0.dcache.overall_miss_latency::cpu0.data 8617903000 # number of overall miss cycles 628system.cpu0.dcache.overall_miss_latency::total 8617903000 # number of overall miss cycles 629system.cpu0.dcache.ReadReq_accesses::cpu0.data 6827849 # number of ReadReq accesses(hits+misses) 630system.cpu0.dcache.ReadReq_accesses::total 6827849 # number of ReadReq accesses(hits+misses) 631system.cpu0.dcache.WriteReq_accesses::cpu0.data 5491865 # number of WriteReq accesses(hits+misses) 632system.cpu0.dcache.WriteReq_accesses::total 5491865 # number of WriteReq accesses(hits+misses) 633system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157222 # number of LoadLockedReq accesses(hits+misses) 634system.cpu0.dcache.LoadLockedReq_accesses::total 157222 # number of LoadLockedReq accesses(hits+misses) 635system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157159 # number of StoreCondReq accesses(hits+misses) 636system.cpu0.dcache.StoreCondReq_accesses::total 157159 # number of StoreCondReq accesses(hits+misses) 637system.cpu0.dcache.demand_accesses::cpu0.data 12319714 # number of demand (read+write) accesses 638system.cpu0.dcache.demand_accesses::total 12319714 # number of demand (read+write) accesses 639system.cpu0.dcache.overall_accesses::cpu0.data 12319714 # number of overall (read+write) accesses 640system.cpu0.dcache.overall_accesses::total 12319714 # number of overall (read+write) accesses 641system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033860 # miss rate for ReadReq accesses 642system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025969 # miss rate for WriteReq accesses 643system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.060456 # miss rate for LoadLockedReq accesses 644system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047493 # miss rate for StoreCondReq accesses 645system.cpu0.dcache.demand_miss_rate::cpu0.data 0.030342 # miss rate for demand accesses 646system.cpu0.dcache.overall_miss_rate::cpu0.data 0.030342 # miss rate for overall accesses 647system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15320.382890 # average ReadReq miss latency 648system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35592.072418 # average WriteReq miss latency 649system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11039.558127 # average LoadLockedReq miss latency 650system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9145.766345 # average StoreCondReq miss latency 651system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 23054.541807 # average overall miss latency 652system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23054.541807 # average overall miss latency 653system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 654system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 655system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 656system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 657system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 658system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 659system.cpu0.dcache.fast_writes 0 # number of fast writes performed 660system.cpu0.dcache.cache_copies 0 # number of cache copies performed 661system.cpu0.dcache.writebacks::writebacks 287163 # number of writebacks 662system.cpu0.dcache.writebacks::total 287163 # number of writebacks 663system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 231189 # number of ReadReq MSHR misses 664system.cpu0.dcache.ReadReq_mshr_misses::total 231189 # number of ReadReq MSHR misses 665system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 142616 # number of WriteReq MSHR misses 666system.cpu0.dcache.WriteReq_mshr_misses::total 142616 # number of WriteReq MSHR misses 667system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9505 # number of LoadLockedReq MSHR misses 668system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9505 # number of LoadLockedReq MSHR misses 669system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7461 # number of StoreCondReq MSHR misses 670system.cpu0.dcache.StoreCondReq_mshr_misses::total 7461 # number of StoreCondReq MSHR misses 671system.cpu0.dcache.demand_mshr_misses::cpu0.data 373805 # number of demand (read+write) MSHR misses 672system.cpu0.dcache.demand_mshr_misses::total 373805 # number of demand (read+write) MSHR misses 673system.cpu0.dcache.overall_mshr_misses::cpu0.data 373805 # number of overall MSHR misses 674system.cpu0.dcache.overall_mshr_misses::total 373805 # number of overall MSHR misses 675system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2848236000 # number of ReadReq MSHR miss cycles 676system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2848236000 # number of ReadReq MSHR miss cycles 677system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4648049500 # number of WriteReq MSHR miss cycles 678system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4648049500 # number of WriteReq MSHR miss cycles 679system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 76416000 # number of LoadLockedReq MSHR miss cycles 680system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 76416000 # number of LoadLockedReq MSHR miss cycles 681system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 45881000 # number of StoreCondReq MSHR miss cycles 682system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 45881000 # number of StoreCondReq MSHR miss cycles 683system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7496285500 # number of demand (read+write) MSHR miss cycles 684system.cpu0.dcache.demand_mshr_miss_latency::total 7496285500 # number of demand (read+write) MSHR miss cycles 685system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7496285500 # number of overall MSHR miss cycles 686system.cpu0.dcache.overall_mshr_miss_latency::total 7496285500 # number of overall MSHR miss cycles 687system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 10423748000 # number of ReadReq MSHR uncacheable cycles 688system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 10423748000 # number of ReadReq MSHR uncacheable cycles 689system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 822757000 # number of WriteReq MSHR uncacheable cycles 690system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 822757000 # number of WriteReq MSHR uncacheable cycles 691system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11246505000 # number of overall MSHR uncacheable cycles 692system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11246505000 # number of overall MSHR uncacheable cycles 693system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033860 # mshr miss rate for ReadReq accesses 694system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025969 # mshr miss rate for WriteReq accesses 695system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.060456 # mshr miss rate for LoadLockedReq accesses 696system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047474 # mshr miss rate for StoreCondReq accesses 697system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030342 # mshr miss rate for demand accesses 698system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030342 # mshr miss rate for overall accesses 699system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12319.946018 # average ReadReq mshr miss latency 700system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32591.360717 # average WriteReq mshr miss latency 701system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8039.558127 # average LoadLockedReq mshr miss latency 702system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6149.443774 # average StoreCondReq mshr miss latency 703system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20054.000080 # average overall mshr miss latency 704system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20054.000080 # average overall mshr miss latency 705system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 706system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 707system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 708system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 709system.cpu1.dtb.inst_hits 0 # ITB inst hits 710system.cpu1.dtb.inst_misses 0 # ITB inst misses 711system.cpu1.dtb.read_hits 8313009 # DTB read hits 712system.cpu1.dtb.read_misses 3663 # DTB read misses 713system.cpu1.dtb.write_hits 5829499 # DTB write hits 714system.cpu1.dtb.write_misses 1439 # DTB write misses 715system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 716system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 717system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 718system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 719system.cpu1.dtb.flush_entries 1967 # Number of entries that have been flushed from TLB 720system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 721system.cpu1.dtb.prefetch_faults 136 # Number of TLB faults due to prefetch 722system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 723system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions 724system.cpu1.dtb.read_accesses 8316672 # DTB read accesses 725system.cpu1.dtb.write_accesses 5830938 # DTB write accesses 726system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 727system.cpu1.dtb.hits 14142508 # DTB hits 728system.cpu1.dtb.misses 5102 # DTB misses 729system.cpu1.dtb.accesses 14147610 # DTB accesses 730system.cpu1.itb.inst_hits 32286240 # ITB inst hits 731system.cpu1.itb.inst_misses 2171 # ITB inst misses 732system.cpu1.itb.read_hits 0 # DTB read hits 733system.cpu1.itb.read_misses 0 # DTB read misses 734system.cpu1.itb.write_hits 0 # DTB write hits 735system.cpu1.itb.write_misses 0 # DTB write misses 736system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 737system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 738system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 739system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 740system.cpu1.itb.flush_entries 1495 # Number of entries that have been flushed from TLB 741system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 742system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 743system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 744system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 745system.cpu1.itb.read_accesses 0 # DTB read accesses 746system.cpu1.itb.write_accesses 0 # DTB write accesses 747system.cpu1.itb.inst_accesses 32288411 # ITB inst accesses 748system.cpu1.itb.hits 32286240 # DTB hits 749system.cpu1.itb.misses 2171 # DTB misses 750system.cpu1.itb.accesses 32288411 # DTB accesses 751system.cpu1.numCycles 2338003468 # number of cpu cycles simulated 752system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 753system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 754system.cpu1.committedInsts 31682438 # Number of instructions committed 755system.cpu1.committedOps 40196649 # Number of ops (including micro ops) committed 756system.cpu1.num_int_alu_accesses 36868206 # Number of integer alu accesses 757system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses 758system.cpu1.num_func_calls 909270 # number of times a function call or return occured 759system.cpu1.num_conditional_control_insts 3487065 # number of instructions that are conditional controls 760system.cpu1.num_int_insts 36868206 # number of integer instructions 761system.cpu1.num_fp_insts 6793 # number of float instructions 762system.cpu1.num_int_register_reads 210764243 # number of times the integer registers were read 763system.cpu1.num_int_register_writes 38547083 # number of times the integer registers were written 764system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read 765system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written 766system.cpu1.num_mem_refs 14680299 # number of memory refs 767system.cpu1.num_load_insts 8634860 # Number of load instructions 768system.cpu1.num_store_insts 6045439 # Number of store instructions 769system.cpu1.num_idle_cycles 1858954745.472398 # Number of idle cycles 770system.cpu1.num_busy_cycles 479048722.527602 # Number of busy cycles 771system.cpu1.not_idle_fraction 0.204896 # Percentage of non-idle cycles 772system.cpu1.idle_fraction 0.795104 # Percentage of idle cycles 773system.cpu1.kern.inst.arm 0 # number of arm instructions executed 774system.cpu1.kern.inst.quiesce 43911 # number of quiesce instructions executed 775system.cpu1.icache.replacements 454317 # number of replacements 776system.cpu1.icache.tagsinuse 478.423780 # Cycle average of tags in use 777system.cpu1.icache.total_refs 31831407 # Total number of references to valid blocks. 778system.cpu1.icache.sampled_refs 454829 # Sample count of references to valid blocks. 779system.cpu1.icache.avg_refs 69.985438 # Average number of references to valid blocks. 780system.cpu1.icache.warmup_cycle 91926225000 # Cycle when the warmup percentage was hit. 781system.cpu1.icache.occ_blocks::cpu1.inst 478.423780 # Average occupied blocks per requestor 782system.cpu1.icache.occ_percent::cpu1.inst 0.934421 # Average percentage of cache occupancy 783system.cpu1.icache.occ_percent::total 0.934421 # Average percentage of cache occupancy 784system.cpu1.icache.ReadReq_hits::cpu1.inst 31831407 # number of ReadReq hits 785system.cpu1.icache.ReadReq_hits::total 31831407 # number of ReadReq hits 786system.cpu1.icache.demand_hits::cpu1.inst 31831407 # number of demand (read+write) hits 787system.cpu1.icache.demand_hits::total 31831407 # number of demand (read+write) hits 788system.cpu1.icache.overall_hits::cpu1.inst 31831407 # number of overall hits 789system.cpu1.icache.overall_hits::total 31831407 # number of overall hits 790system.cpu1.icache.ReadReq_misses::cpu1.inst 454829 # number of ReadReq misses 791system.cpu1.icache.ReadReq_misses::total 454829 # number of ReadReq misses 792system.cpu1.icache.demand_misses::cpu1.inst 454829 # number of demand (read+write) misses 793system.cpu1.icache.demand_misses::total 454829 # number of demand (read+write) misses 794system.cpu1.icache.overall_misses::cpu1.inst 454829 # number of overall misses 795system.cpu1.icache.overall_misses::total 454829 # number of overall misses 796system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6679957000 # number of ReadReq miss cycles 797system.cpu1.icache.ReadReq_miss_latency::total 6679957000 # number of ReadReq miss cycles 798system.cpu1.icache.demand_miss_latency::cpu1.inst 6679957000 # number of demand (read+write) miss cycles 799system.cpu1.icache.demand_miss_latency::total 6679957000 # number of demand (read+write) miss cycles 800system.cpu1.icache.overall_miss_latency::cpu1.inst 6679957000 # number of overall miss cycles 801system.cpu1.icache.overall_miss_latency::total 6679957000 # number of overall miss cycles 802system.cpu1.icache.ReadReq_accesses::cpu1.inst 32286236 # number of ReadReq accesses(hits+misses) 803system.cpu1.icache.ReadReq_accesses::total 32286236 # number of ReadReq accesses(hits+misses) 804system.cpu1.icache.demand_accesses::cpu1.inst 32286236 # number of demand (read+write) accesses 805system.cpu1.icache.demand_accesses::total 32286236 # number of demand (read+write) accesses 806system.cpu1.icache.overall_accesses::cpu1.inst 32286236 # number of overall (read+write) accesses 807system.cpu1.icache.overall_accesses::total 32286236 # number of overall (read+write) accesses 808system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014087 # miss rate for ReadReq accesses 809system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014087 # miss rate for demand accesses 810system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014087 # miss rate for overall accesses 811system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14686.743809 # average ReadReq miss latency 812system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14686.743809 # average overall miss latency 813system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14686.743809 # average overall miss latency 814system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 815system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 816system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 817system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 818system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 819system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 820system.cpu1.icache.fast_writes 0 # number of fast writes performed 821system.cpu1.icache.cache_copies 0 # number of cache copies performed 822system.cpu1.icache.writebacks::writebacks 19149 # number of writebacks 823system.cpu1.icache.writebacks::total 19149 # number of writebacks 824system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 454829 # number of ReadReq MSHR misses 825system.cpu1.icache.ReadReq_mshr_misses::total 454829 # number of ReadReq MSHR misses 826system.cpu1.icache.demand_mshr_misses::cpu1.inst 454829 # number of demand (read+write) MSHR misses 827system.cpu1.icache.demand_mshr_misses::total 454829 # number of demand (read+write) MSHR misses 828system.cpu1.icache.overall_mshr_misses::cpu1.inst 454829 # number of overall MSHR misses 829system.cpu1.icache.overall_mshr_misses::total 454829 # number of overall MSHR misses 830system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5314262500 # number of ReadReq MSHR miss cycles 831system.cpu1.icache.ReadReq_mshr_miss_latency::total 5314262500 # number of ReadReq MSHR miss cycles 832system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5314262500 # number of demand (read+write) MSHR miss cycles 833system.cpu1.icache.demand_mshr_miss_latency::total 5314262500 # number of demand (read+write) MSHR miss cycles 834system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5314262500 # number of overall MSHR miss cycles 835system.cpu1.icache.overall_mshr_miss_latency::total 5314262500 # number of overall MSHR miss cycles 836system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5250000 # number of ReadReq MSHR uncacheable cycles 837system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5250000 # number of ReadReq MSHR uncacheable cycles 838system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5250000 # number of overall MSHR uncacheable cycles 839system.cpu1.icache.overall_mshr_uncacheable_latency::total 5250000 # number of overall MSHR uncacheable cycles 840system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014087 # mshr miss rate for ReadReq accesses 841system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014087 # mshr miss rate for demand accesses 842system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014087 # mshr miss rate for overall accesses 843system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11684.088965 # average ReadReq mshr miss latency 844system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11684.088965 # average overall mshr miss latency 845system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11684.088965 # average overall mshr miss latency 846system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 847system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 848system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 849system.cpu1.dcache.replacements 294642 # number of replacements 850system.cpu1.dcache.tagsinuse 457.752328 # Cycle average of tags in use 851system.cpu1.dcache.total_refs 11964721 # Total number of references to valid blocks. 852system.cpu1.dcache.sampled_refs 295088 # Sample count of references to valid blocks. 853system.cpu1.dcache.avg_refs 40.546281 # Average number of references to valid blocks. 854system.cpu1.dcache.warmup_cycle 89831748000 # Cycle when the warmup percentage was hit. 855system.cpu1.dcache.occ_blocks::cpu1.data 457.752328 # Average occupied blocks per requestor 856system.cpu1.dcache.occ_percent::cpu1.data 0.894048 # Average percentage of cache occupancy 857system.cpu1.dcache.occ_percent::total 0.894048 # Average percentage of cache occupancy 858system.cpu1.dcache.ReadReq_hits::cpu1.data 6946891 # number of ReadReq hits 859system.cpu1.dcache.ReadReq_hits::total 6946891 # number of ReadReq hits 860system.cpu1.dcache.WriteReq_hits::cpu1.data 4828705 # number of WriteReq hits 861system.cpu1.dcache.WriteReq_hits::total 4828705 # number of WriteReq hits 862system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 81776 # number of LoadLockedReq hits 863system.cpu1.dcache.LoadLockedReq_hits::total 81776 # number of LoadLockedReq hits 864system.cpu1.dcache.StoreCondReq_hits::cpu1.data 83111 # number of StoreCondReq hits 865system.cpu1.dcache.StoreCondReq_hits::total 83111 # number of StoreCondReq hits 866system.cpu1.dcache.demand_hits::cpu1.data 11775596 # number of demand (read+write) hits 867system.cpu1.dcache.demand_hits::total 11775596 # number of demand (read+write) hits 868system.cpu1.dcache.overall_hits::cpu1.data 11775596 # number of overall hits 869system.cpu1.dcache.overall_hits::total 11775596 # number of overall hits 870system.cpu1.dcache.ReadReq_misses::cpu1.data 172105 # number of ReadReq misses 871system.cpu1.dcache.ReadReq_misses::total 172105 # number of ReadReq misses 872system.cpu1.dcache.WriteReq_misses::cpu1.data 150416 # number of WriteReq misses 873system.cpu1.dcache.WriteReq_misses::total 150416 # number of WriteReq misses 874system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11123 # number of LoadLockedReq misses 875system.cpu1.dcache.LoadLockedReq_misses::total 11123 # number of LoadLockedReq misses 876system.cpu1.dcache.StoreCondReq_misses::cpu1.data 9715 # number of StoreCondReq misses 877system.cpu1.dcache.StoreCondReq_misses::total 9715 # number of StoreCondReq misses 878system.cpu1.dcache.demand_misses::cpu1.data 322521 # number of demand (read+write) misses 879system.cpu1.dcache.demand_misses::total 322521 # number of demand (read+write) misses 880system.cpu1.dcache.overall_misses::cpu1.data 322521 # number of overall misses 881system.cpu1.dcache.overall_misses::total 322521 # number of overall misses 882system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2496186500 # number of ReadReq miss cycles 883system.cpu1.dcache.ReadReq_miss_latency::total 2496186500 # number of ReadReq miss cycles 884system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5287724000 # number of WriteReq miss cycles 885system.cpu1.dcache.WriteReq_miss_latency::total 5287724000 # number of WriteReq miss cycles 886system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 124574500 # number of LoadLockedReq miss cycles 887system.cpu1.dcache.LoadLockedReq_miss_latency::total 124574500 # number of LoadLockedReq miss cycles 888system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 73632000 # number of StoreCondReq miss cycles 889system.cpu1.dcache.StoreCondReq_miss_latency::total 73632000 # number of StoreCondReq miss cycles 890system.cpu1.dcache.demand_miss_latency::cpu1.data 7783910500 # number of demand (read+write) miss cycles 891system.cpu1.dcache.demand_miss_latency::total 7783910500 # number of demand (read+write) miss cycles 892system.cpu1.dcache.overall_miss_latency::cpu1.data 7783910500 # number of overall miss cycles 893system.cpu1.dcache.overall_miss_latency::total 7783910500 # number of overall miss cycles 894system.cpu1.dcache.ReadReq_accesses::cpu1.data 7118996 # number of ReadReq accesses(hits+misses) 895system.cpu1.dcache.ReadReq_accesses::total 7118996 # number of ReadReq accesses(hits+misses) 896system.cpu1.dcache.WriteReq_accesses::cpu1.data 4979121 # number of WriteReq accesses(hits+misses) 897system.cpu1.dcache.WriteReq_accesses::total 4979121 # number of WriteReq accesses(hits+misses) 898system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 92899 # number of LoadLockedReq accesses(hits+misses) 899system.cpu1.dcache.LoadLockedReq_accesses::total 92899 # number of LoadLockedReq accesses(hits+misses) 900system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92826 # number of StoreCondReq accesses(hits+misses) 901system.cpu1.dcache.StoreCondReq_accesses::total 92826 # number of StoreCondReq accesses(hits+misses) 902system.cpu1.dcache.demand_accesses::cpu1.data 12098117 # number of demand (read+write) accesses 903system.cpu1.dcache.demand_accesses::total 12098117 # number of demand (read+write) accesses 904system.cpu1.dcache.overall_accesses::cpu1.data 12098117 # number of overall (read+write) accesses 905system.cpu1.dcache.overall_accesses::total 12098117 # number of overall (read+write) accesses 906system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.024175 # miss rate for ReadReq accesses 907system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030209 # miss rate for WriteReq accesses 908system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119732 # miss rate for LoadLockedReq accesses 909system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.104658 # miss rate for StoreCondReq accesses 910system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026659 # miss rate for demand accesses 911system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026659 # miss rate for overall accesses 912system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14503.858110 # average ReadReq miss latency 913system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 35153.999575 # average WriteReq miss latency 914system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11199.721298 # average LoadLockedReq miss latency 915system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7579.207411 # average StoreCondReq miss latency 916system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24134.585035 # average overall miss latency 917system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24134.585035 # average overall miss latency 918system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 919system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 920system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 921system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 922system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 923system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 924system.cpu1.dcache.fast_writes 0 # number of fast writes performed 925system.cpu1.dcache.cache_copies 0 # number of cache copies performed 926system.cpu1.dcache.writebacks::writebacks 254584 # number of writebacks 927system.cpu1.dcache.writebacks::total 254584 # number of writebacks 928system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 172105 # number of ReadReq MSHR misses 929system.cpu1.dcache.ReadReq_mshr_misses::total 172105 # number of ReadReq MSHR misses 930system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150416 # number of WriteReq MSHR misses 931system.cpu1.dcache.WriteReq_mshr_misses::total 150416 # number of WriteReq MSHR misses 932system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11123 # number of LoadLockedReq MSHR misses 933system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11123 # number of LoadLockedReq MSHR misses 934system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9710 # number of StoreCondReq MSHR misses 935system.cpu1.dcache.StoreCondReq_mshr_misses::total 9710 # number of StoreCondReq MSHR misses 936system.cpu1.dcache.demand_mshr_misses::cpu1.data 322521 # number of demand (read+write) MSHR misses 937system.cpu1.dcache.demand_mshr_misses::total 322521 # number of demand (read+write) MSHR misses 938system.cpu1.dcache.overall_mshr_misses::cpu1.data 322521 # number of overall MSHR misses 939system.cpu1.dcache.overall_mshr_misses::total 322521 # number of overall MSHR misses 940system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1979754000 # number of ReadReq MSHR miss cycles 941system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1979754000 # number of ReadReq MSHR miss cycles 942system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4836439500 # number of WriteReq MSHR miss cycles 943system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4836439500 # number of WriteReq MSHR miss cycles 944system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 91205500 # number of LoadLockedReq MSHR miss cycles 945system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 91205500 # number of LoadLockedReq MSHR miss cycles 946system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 44502000 # number of StoreCondReq MSHR miss cycles 947system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 44502000 # number of StoreCondReq MSHR miss cycles 948system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6816193500 # number of demand (read+write) MSHR miss cycles 949system.cpu1.dcache.demand_mshr_miss_latency::total 6816193500 # number of demand (read+write) MSHR miss cycles 950system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6816193500 # number of overall MSHR miss cycles 951system.cpu1.dcache.overall_mshr_miss_latency::total 6816193500 # number of overall MSHR miss cycles 952system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 136553272000 # number of ReadReq MSHR uncacheable cycles 953system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 136553272000 # number of ReadReq MSHR uncacheable cycles 954system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 39714562000 # number of WriteReq MSHR uncacheable cycles 955system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 39714562000 # number of WriteReq MSHR uncacheable cycles 956system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 176267834000 # number of overall MSHR uncacheable cycles 957system.cpu1.dcache.overall_mshr_uncacheable_latency::total 176267834000 # number of overall MSHR uncacheable cycles 958system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024175 # mshr miss rate for ReadReq accesses 959system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030209 # mshr miss rate for WriteReq accesses 960system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119732 # mshr miss rate for LoadLockedReq accesses 961system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.104604 # mshr miss rate for StoreCondReq accesses 962system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026659 # mshr miss rate for demand accesses 963system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026659 # mshr miss rate for overall accesses 964system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11503.175387 # average ReadReq mshr miss latency 965system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32153.756914 # average WriteReq mshr miss latency 966system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8199.721298 # average LoadLockedReq mshr miss latency 967system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4583.110196 # average StoreCondReq mshr miss latency 968system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 21134.107546 # average overall mshr miss latency 969system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21134.107546 # average overall mshr miss latency 970system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 971system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 972system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 973system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 974system.iocache.replacements 0 # number of replacements 975system.iocache.tagsinuse 0 # Cycle average of tags in use 976system.iocache.total_refs 0 # Total number of references to valid blocks. 977system.iocache.sampled_refs 0 # Sample count of references to valid blocks. 978system.iocache.avg_refs nan # Average number of references to valid blocks. 979system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 980system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 981system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 982system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 983system.iocache.blocked::no_targets 0 # number of cycles access was blocked 984system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 985system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 986system.iocache.fast_writes 0 # number of fast writes performed 987system.iocache.cache_copies 0 # number of cache copies performed 988system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 550616164273 # number of ReadReq MSHR uncacheable cycles 989system.iocache.ReadReq_mshr_uncacheable_latency::total 550616164273 # number of ReadReq MSHR uncacheable cycles 990system.iocache.overall_mshr_uncacheable_latency::realview.clcd 550616164273 # number of overall MSHR uncacheable cycles 991system.iocache.overall_mshr_uncacheable_latency::total 550616164273 # number of overall MSHR uncacheable cycles 992system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 993system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 994system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 995 996---------- End Simulation Statistics ---------- 997