stats.txt revision 8802:ef66a9083bc4
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.669611 # Number of seconds simulated 4sim_ticks 2669611225000 # Number of ticks simulated 5final_tick 2669611225000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 842154 # Simulator instruction rate (inst/s) 8host_tick_rate 28671225175 # Simulator tick rate (ticks/s) 9host_mem_usage 380676 # Number of bytes of host memory used 10host_seconds 93.11 # Real time elapsed on the host 11sim_insts 78413959 # Number of instructions simulated 12system.nvmem.bytes_read 68 # Number of bytes read from this memory 13system.nvmem.bytes_inst_read 68 # Number of instructions bytes read from this memory 14system.nvmem.bytes_written 0 # Number of bytes written to this memory 15system.nvmem.num_reads 17 # Number of read requests responded to by this memory 16system.nvmem.num_writes 0 # Number of write requests responded to by this memory 17system.nvmem.num_other 0 # Number of other requests responded to by this memory 18system.nvmem.bw_read 25 # Total read bandwidth from this memory (bytes/s) 19system.nvmem.bw_inst_read 25 # Instruction read bandwidth from this memory (bytes/s) 20system.nvmem.bw_total 25 # Total bandwidth to/from this memory (bytes/s) 21system.physmem.bytes_read 134334820 # Number of bytes read from this memory 22system.physmem.bytes_inst_read 1003520 # Number of instructions bytes read from this memory 23system.physmem.bytes_written 10194256 # Number of bytes written to this memory 24system.physmem.num_reads 15523876 # Number of read requests responded to by this memory 25system.physmem.num_writes 869239 # Number of write requests responded to by this memory 26system.physmem.num_other 0 # Number of other requests responded to by this memory 27system.physmem.bw_read 50319994 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read 375905 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_write 3818629 # Write bandwidth from this memory (bytes/s) 30system.physmem.bw_total 54138623 # Total bandwidth to/from this memory (bytes/s) 31system.l2c.replacements 127749 # number of replacements 32system.l2c.tagsinuse 26172.513439 # Cycle average of tags in use 33system.l2c.total_refs 1540412 # Total number of references to valid blocks. 34system.l2c.sampled_refs 157158 # Sample count of references to valid blocks. 35system.l2c.avg_refs 9.801677 # Average number of references to valid blocks. 36system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 37system.l2c.occ_blocks::0 6351.465954 # Average occupied blocks per context 38system.l2c.occ_blocks::1 4614.904109 # Average occupied blocks per context 39system.l2c.occ_blocks::2 15206.143377 # Average occupied blocks per context 40system.l2c.occ_percent::0 0.096916 # Average percentage of cache occupancy 41system.l2c.occ_percent::1 0.070418 # Average percentage of cache occupancy 42system.l2c.occ_percent::2 0.232027 # Average percentage of cache occupancy 43system.l2c.ReadReq_hits::0 562859 # number of ReadReq hits 44system.l2c.ReadReq_hits::1 656143 # number of ReadReq hits 45system.l2c.ReadReq_hits::2 11798 # number of ReadReq hits 46system.l2c.ReadReq_hits::total 1230800 # number of ReadReq hits 47system.l2c.Writeback_hits::0 589400 # number of Writeback hits 48system.l2c.Writeback_hits::total 589400 # number of Writeback hits 49system.l2c.UpgradeReq_hits::0 1143 # number of UpgradeReq hits 50system.l2c.UpgradeReq_hits::1 692 # number of UpgradeReq hits 51system.l2c.UpgradeReq_hits::total 1835 # number of UpgradeReq hits 52system.l2c.SCUpgradeReq_hits::0 168 # number of SCUpgradeReq hits 53system.l2c.SCUpgradeReq_hits::1 186 # number of SCUpgradeReq hits 54system.l2c.SCUpgradeReq_hits::total 354 # number of SCUpgradeReq hits 55system.l2c.ReadExReq_hits::0 42506 # number of ReadExReq hits 56system.l2c.ReadExReq_hits::1 58554 # number of ReadExReq hits 57system.l2c.ReadExReq_hits::total 101060 # number of ReadExReq hits 58system.l2c.demand_hits::0 605365 # number of demand (read+write) hits 59system.l2c.demand_hits::1 714697 # number of demand (read+write) hits 60system.l2c.demand_hits::2 11798 # number of demand (read+write) hits 61system.l2c.demand_hits::total 1331860 # number of demand (read+write) hits 62system.l2c.overall_hits::0 605365 # number of overall hits 63system.l2c.overall_hits::1 714697 # number of overall hits 64system.l2c.overall_hits::2 11798 # number of overall hits 65system.l2c.overall_hits::total 1331860 # number of overall hits 66system.l2c.ReadReq_misses::0 18655 # number of ReadReq misses 67system.l2c.ReadReq_misses::1 16034 # number of ReadReq misses 68system.l2c.ReadReq_misses::2 50 # number of ReadReq misses 69system.l2c.ReadReq_misses::total 34739 # number of ReadReq misses 70system.l2c.UpgradeReq_misses::0 3515 # number of UpgradeReq misses 71system.l2c.UpgradeReq_misses::1 5223 # number of UpgradeReq misses 72system.l2c.UpgradeReq_misses::total 8738 # number of UpgradeReq misses 73system.l2c.SCUpgradeReq_misses::0 546 # number of SCUpgradeReq misses 74system.l2c.SCUpgradeReq_misses::1 614 # number of SCUpgradeReq misses 75system.l2c.SCUpgradeReq_misses::total 1160 # number of SCUpgradeReq misses 76system.l2c.ReadExReq_misses::0 97324 # number of ReadExReq misses 77system.l2c.ReadExReq_misses::1 51524 # number of ReadExReq misses 78system.l2c.ReadExReq_misses::total 148848 # number of ReadExReq misses 79system.l2c.demand_misses::0 115979 # number of demand (read+write) misses 80system.l2c.demand_misses::1 67558 # number of demand (read+write) misses 81system.l2c.demand_misses::2 50 # number of demand (read+write) misses 82system.l2c.demand_misses::total 183587 # number of demand (read+write) misses 83system.l2c.overall_misses::0 115979 # number of overall misses 84system.l2c.overall_misses::1 67558 # number of overall misses 85system.l2c.overall_misses::2 50 # number of overall misses 86system.l2c.overall_misses::total 183587 # number of overall misses 87system.l2c.ReadReq_miss_latency 1812504500 # number of ReadReq miss cycles 88system.l2c.UpgradeReq_miss_latency 56471000 # number of UpgradeReq miss cycles 89system.l2c.SCUpgradeReq_miss_latency 6300000 # number of SCUpgradeReq miss cycles 90system.l2c.ReadExReq_miss_latency 7751543000 # number of ReadExReq miss cycles 91system.l2c.demand_miss_latency 9564047500 # number of demand (read+write) miss cycles 92system.l2c.overall_miss_latency 9564047500 # number of overall miss cycles 93system.l2c.ReadReq_accesses::0 581514 # number of ReadReq accesses(hits+misses) 94system.l2c.ReadReq_accesses::1 672177 # number of ReadReq accesses(hits+misses) 95system.l2c.ReadReq_accesses::2 11848 # number of ReadReq accesses(hits+misses) 96system.l2c.ReadReq_accesses::total 1265539 # number of ReadReq accesses(hits+misses) 97system.l2c.Writeback_accesses::0 589400 # number of Writeback accesses(hits+misses) 98system.l2c.Writeback_accesses::total 589400 # number of Writeback accesses(hits+misses) 99system.l2c.UpgradeReq_accesses::0 4658 # number of UpgradeReq accesses(hits+misses) 100system.l2c.UpgradeReq_accesses::1 5915 # number of UpgradeReq accesses(hits+misses) 101system.l2c.UpgradeReq_accesses::total 10573 # number of UpgradeReq accesses(hits+misses) 102system.l2c.SCUpgradeReq_accesses::0 714 # number of SCUpgradeReq accesses(hits+misses) 103system.l2c.SCUpgradeReq_accesses::1 800 # number of SCUpgradeReq accesses(hits+misses) 104system.l2c.SCUpgradeReq_accesses::total 1514 # number of SCUpgradeReq accesses(hits+misses) 105system.l2c.ReadExReq_accesses::0 139830 # number of ReadExReq accesses(hits+misses) 106system.l2c.ReadExReq_accesses::1 110078 # number of ReadExReq accesses(hits+misses) 107system.l2c.ReadExReq_accesses::total 249908 # number of ReadExReq accesses(hits+misses) 108system.l2c.demand_accesses::0 721344 # number of demand (read+write) accesses 109system.l2c.demand_accesses::1 782255 # number of demand (read+write) accesses 110system.l2c.demand_accesses::2 11848 # number of demand (read+write) accesses 111system.l2c.demand_accesses::total 1515447 # number of demand (read+write) accesses 112system.l2c.overall_accesses::0 721344 # number of overall (read+write) accesses 113system.l2c.overall_accesses::1 782255 # number of overall (read+write) accesses 114system.l2c.overall_accesses::2 11848 # number of overall (read+write) accesses 115system.l2c.overall_accesses::total 1515447 # number of overall (read+write) accesses 116system.l2c.ReadReq_miss_rate::0 0.032080 # miss rate for ReadReq accesses 117system.l2c.ReadReq_miss_rate::1 0.023854 # miss rate for ReadReq accesses 118system.l2c.ReadReq_miss_rate::2 0.004220 # miss rate for ReadReq accesses 119system.l2c.ReadReq_miss_rate::total 0.060154 # miss rate for ReadReq accesses 120system.l2c.UpgradeReq_miss_rate::0 0.754616 # miss rate for UpgradeReq accesses 121system.l2c.UpgradeReq_miss_rate::1 0.883009 # miss rate for UpgradeReq accesses 122system.l2c.SCUpgradeReq_miss_rate::0 0.764706 # miss rate for SCUpgradeReq accesses 123system.l2c.SCUpgradeReq_miss_rate::1 0.767500 # miss rate for SCUpgradeReq accesses 124system.l2c.ReadExReq_miss_rate::0 0.696017 # miss rate for ReadExReq accesses 125system.l2c.ReadExReq_miss_rate::1 0.468068 # miss rate for ReadExReq accesses 126system.l2c.demand_miss_rate::0 0.160782 # miss rate for demand accesses 127system.l2c.demand_miss_rate::1 0.086363 # miss rate for demand accesses 128system.l2c.demand_miss_rate::2 0.004220 # miss rate for demand accesses 129system.l2c.demand_miss_rate::total 0.251365 # miss rate for demand accesses 130system.l2c.overall_miss_rate::0 0.160782 # miss rate for overall accesses 131system.l2c.overall_miss_rate::1 0.086363 # miss rate for overall accesses 132system.l2c.overall_miss_rate::2 0.004220 # miss rate for overall accesses 133system.l2c.overall_miss_rate::total 0.251365 # miss rate for overall accesses 134system.l2c.ReadReq_avg_miss_latency::0 97159.179845 # average ReadReq miss latency 135system.l2c.ReadReq_avg_miss_latency::1 113041.318448 # average ReadReq miss latency 136system.l2c.ReadReq_avg_miss_latency::2 36250090 # average ReadReq miss latency 137system.l2c.ReadReq_avg_miss_latency::total 36460290.498293 # average ReadReq miss latency 138system.l2c.UpgradeReq_avg_miss_latency::0 16065.718350 # average UpgradeReq miss latency 139system.l2c.UpgradeReq_avg_miss_latency::1 10811.985449 # average UpgradeReq miss latency 140system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency 141system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency 142system.l2c.SCUpgradeReq_avg_miss_latency::0 11538.461538 # average SCUpgradeReq miss latency 143system.l2c.SCUpgradeReq_avg_miss_latency::1 10260.586319 # average SCUpgradeReq miss latency 144system.l2c.SCUpgradeReq_avg_miss_latency::2 inf # average SCUpgradeReq miss latency 145system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency 146system.l2c.ReadExReq_avg_miss_latency::0 79646.777773 # average ReadExReq miss latency 147system.l2c.ReadExReq_avg_miss_latency::1 150445.287633 # average ReadExReq miss latency 148system.l2c.ReadExReq_avg_miss_latency::2 inf # average ReadExReq miss latency 149system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency 150system.l2c.demand_avg_miss_latency::0 82463.614103 # average overall miss latency 151system.l2c.demand_avg_miss_latency::1 141567.949022 # average overall miss latency 152system.l2c.demand_avg_miss_latency::2 191280950 # average overall miss latency 153system.l2c.demand_avg_miss_latency::total 191504981.563124 # average overall miss latency 154system.l2c.overall_avg_miss_latency::0 82463.614103 # average overall miss latency 155system.l2c.overall_avg_miss_latency::1 141567.949022 # average overall miss latency 156system.l2c.overall_avg_miss_latency::2 191280950 # average overall miss latency 157system.l2c.overall_avg_miss_latency::total 191504981.563124 # average overall miss latency 158system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 159system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 160system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 161system.l2c.blocked::no_targets 0 # number of cycles access was blocked 162system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 163system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 164system.l2c.fast_writes 0 # number of fast writes performed 165system.l2c.cache_copies 0 # number of cache copies performed 166system.l2c.writebacks 111955 # number of writebacks 167system.l2c.ReadReq_mshr_hits 9 # number of ReadReq MSHR hits 168system.l2c.demand_mshr_hits 9 # number of demand (read+write) MSHR hits 169system.l2c.overall_mshr_hits 9 # number of overall MSHR hits 170system.l2c.ReadReq_mshr_misses 34730 # number of ReadReq MSHR misses 171system.l2c.UpgradeReq_mshr_misses 8738 # number of UpgradeReq MSHR misses 172system.l2c.SCUpgradeReq_mshr_misses 1160 # number of SCUpgradeReq MSHR misses 173system.l2c.ReadExReq_mshr_misses 148848 # number of ReadExReq MSHR misses 174system.l2c.demand_mshr_misses 183578 # number of demand (read+write) MSHR misses 175system.l2c.overall_mshr_misses 183578 # number of overall MSHR misses 176system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 177system.l2c.ReadReq_mshr_miss_latency 1395310000 # number of ReadReq MSHR miss cycles 178system.l2c.UpgradeReq_mshr_miss_latency 350593500 # number of UpgradeReq MSHR miss cycles 179system.l2c.SCUpgradeReq_mshr_miss_latency 46546000 # number of SCUpgradeReq MSHR miss cycles 180system.l2c.ReadExReq_mshr_miss_latency 5965367000 # number of ReadExReq MSHR miss cycles 181system.l2c.demand_mshr_miss_latency 7360677000 # number of demand (read+write) MSHR miss cycles 182system.l2c.overall_mshr_miss_latency 7360677000 # number of overall MSHR miss cycles 183system.l2c.ReadReq_mshr_uncacheable_latency 131926671000 # number of ReadReq MSHR uncacheable cycles 184system.l2c.WriteReq_mshr_uncacheable_latency 31372379500 # number of WriteReq MSHR uncacheable cycles 185system.l2c.overall_mshr_uncacheable_latency 163299050500 # number of overall MSHR uncacheable cycles 186system.l2c.ReadReq_mshr_miss_rate::0 0.059723 # mshr miss rate for ReadReq accesses 187system.l2c.ReadReq_mshr_miss_rate::1 0.051668 # mshr miss rate for ReadReq accesses 188system.l2c.ReadReq_mshr_miss_rate::2 2.931296 # mshr miss rate for ReadReq accesses 189system.l2c.ReadReq_mshr_miss_rate::total 3.042688 # mshr miss rate for ReadReq accesses 190system.l2c.UpgradeReq_mshr_miss_rate::0 1.875912 # mshr miss rate for UpgradeReq accesses 191system.l2c.UpgradeReq_mshr_miss_rate::1 1.477261 # mshr miss rate for UpgradeReq accesses 192system.l2c.UpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for UpgradeReq accesses 193system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses 194system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.624650 # mshr miss rate for SCUpgradeReq accesses 195system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.450000 # mshr miss rate for SCUpgradeReq accesses 196system.l2c.SCUpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for SCUpgradeReq accesses 197system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses 198system.l2c.ReadExReq_mshr_miss_rate::0 1.064493 # mshr miss rate for ReadExReq accesses 199system.l2c.ReadExReq_mshr_miss_rate::1 1.352205 # mshr miss rate for ReadExReq accesses 200system.l2c.ReadExReq_mshr_miss_rate::2 inf # mshr miss rate for ReadExReq accesses 201system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses 202system.l2c.demand_mshr_miss_rate::0 0.254494 # mshr miss rate for demand accesses 203system.l2c.demand_mshr_miss_rate::1 0.234678 # mshr miss rate for demand accesses 204system.l2c.demand_mshr_miss_rate::2 15.494429 # mshr miss rate for demand accesses 205system.l2c.demand_mshr_miss_rate::total 15.983602 # mshr miss rate for demand accesses 206system.l2c.overall_mshr_miss_rate::0 0.254494 # mshr miss rate for overall accesses 207system.l2c.overall_mshr_miss_rate::1 0.234678 # mshr miss rate for overall accesses 208system.l2c.overall_mshr_miss_rate::2 15.494429 # mshr miss rate for overall accesses 209system.l2c.overall_mshr_miss_rate::total 15.983602 # mshr miss rate for overall accesses 210system.l2c.ReadReq_avg_mshr_miss_latency 40175.928592 # average ReadReq mshr miss latency 211system.l2c.UpgradeReq_avg_mshr_miss_latency 40122.854200 # average UpgradeReq mshr miss latency 212system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40125.862069 # average SCUpgradeReq mshr miss latency 213system.l2c.ReadExReq_avg_mshr_miss_latency 40076.903956 # average ReadExReq mshr miss latency 214system.l2c.demand_avg_mshr_miss_latency 40095.637822 # average overall mshr miss latency 215system.l2c.overall_avg_mshr_miss_latency 40095.637822 # average overall mshr miss latency 216system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency 217system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency 218system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency 219system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated 220system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 221system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 222system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 223system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 224system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 225system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 226system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 227system.cf0.dma_write_txs 0 # Number of DMA write transactions. 228system.cpu0.dtb.inst_hits 0 # ITB inst hits 229system.cpu0.dtb.inst_misses 0 # ITB inst misses 230system.cpu0.dtb.read_hits 7857580 # DTB read hits 231system.cpu0.dtb.read_misses 1898 # DTB read misses 232system.cpu0.dtb.write_hits 6224259 # DTB write hits 233system.cpu0.dtb.write_misses 1143 # DTB write misses 234system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 235system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 236system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 237system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 238system.cpu0.dtb.flush_entries 1404 # Number of entries that have been flushed from TLB 239system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 240system.cpu0.dtb.prefetch_faults 79 # Number of TLB faults due to prefetch 241system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 242system.cpu0.dtb.perms_faults 191 # Number of TLB faults due to permissions restrictions 243system.cpu0.dtb.read_accesses 7859478 # DTB read accesses 244system.cpu0.dtb.write_accesses 6225402 # DTB write accesses 245system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 246system.cpu0.dtb.hits 14081839 # DTB hits 247system.cpu0.dtb.misses 3041 # DTB misses 248system.cpu0.dtb.accesses 14084880 # DTB accesses 249system.cpu0.itb.inst_hits 35747911 # ITB inst hits 250system.cpu0.itb.inst_misses 1204 # ITB inst misses 251system.cpu0.itb.read_hits 0 # DTB read hits 252system.cpu0.itb.read_misses 0 # DTB read misses 253system.cpu0.itb.write_hits 0 # DTB write hits 254system.cpu0.itb.write_misses 0 # DTB write misses 255system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 256system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 257system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 258system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 259system.cpu0.itb.flush_entries 1262 # Number of entries that have been flushed from TLB 260system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 261system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 262system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 263system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 264system.cpu0.itb.read_accesses 0 # DTB read accesses 265system.cpu0.itb.write_accesses 0 # DTB write accesses 266system.cpu0.itb.inst_accesses 35749115 # ITB inst accesses 267system.cpu0.itb.hits 35747911 # DTB hits 268system.cpu0.itb.misses 1204 # DTB misses 269system.cpu0.itb.accesses 35749115 # DTB accesses 270system.cpu0.numCycles 5337805216 # number of cpu cycles simulated 271system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 272system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 273system.cpu0.num_insts 43969024 # Number of instructions executed 274system.cpu0.num_int_alu_accesses 39881498 # Number of integer alu accesses 275system.cpu0.num_fp_alu_accesses 4107 # Number of float alu accesses 276system.cpu0.num_func_calls 977479 # number of times a function call or return occured 277system.cpu0.num_conditional_control_insts 4512711 # number of instructions that are conditional controls 278system.cpu0.num_int_insts 39881498 # number of integer instructions 279system.cpu0.num_fp_insts 4107 # number of float instructions 280system.cpu0.num_int_register_reads 225043856 # number of times the integer registers were read 281system.cpu0.num_int_register_writes 43158045 # number of times the integer registers were written 282system.cpu0.num_fp_register_reads 3851 # number of times the floating registers were read 283system.cpu0.num_fp_register_writes 256 # number of times the floating registers were written 284system.cpu0.num_mem_refs 14677999 # number of memory refs 285system.cpu0.num_load_insts 8148547 # Number of load instructions 286system.cpu0.num_store_insts 6529452 # Number of store instructions 287system.cpu0.num_idle_cycles 5107410781.564784 # Number of idle cycles 288system.cpu0.num_busy_cycles 230394434.435216 # Number of busy cycles 289system.cpu0.not_idle_fraction 0.043163 # Percentage of non-idle cycles 290system.cpu0.idle_fraction 0.956837 # Percentage of idle cycles 291system.cpu0.kern.inst.arm 0 # number of arm instructions executed 292system.cpu0.kern.inst.quiesce 38525 # number of quiesce instructions executed 293system.cpu0.icache.replacements 380069 # number of replacements 294system.cpu0.icache.tagsinuse 510.849663 # Cycle average of tags in use 295system.cpu0.icache.total_refs 35367311 # Total number of references to valid blocks. 296system.cpu0.icache.sampled_refs 380581 # Sample count of references to valid blocks. 297system.cpu0.icache.avg_refs 92.929786 # Average number of references to valid blocks. 298system.cpu0.icache.warmup_cycle 74921716000 # Cycle when the warmup percentage was hit. 299system.cpu0.icache.occ_blocks::0 510.849663 # Average occupied blocks per context 300system.cpu0.icache.occ_percent::0 0.997753 # Average percentage of cache occupancy 301system.cpu0.icache.ReadReq_hits::0 35367311 # number of ReadReq hits 302system.cpu0.icache.ReadReq_hits::total 35367311 # number of ReadReq hits 303system.cpu0.icache.demand_hits::0 35367311 # number of demand (read+write) hits 304system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits 305system.cpu0.icache.demand_hits::total 35367311 # number of demand (read+write) hits 306system.cpu0.icache.overall_hits::0 35367311 # number of overall hits 307system.cpu0.icache.overall_hits::1 0 # number of overall hits 308system.cpu0.icache.overall_hits::total 35367311 # number of overall hits 309system.cpu0.icache.ReadReq_misses::0 380583 # number of ReadReq misses 310system.cpu0.icache.ReadReq_misses::total 380583 # number of ReadReq misses 311system.cpu0.icache.demand_misses::0 380583 # number of demand (read+write) misses 312system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses 313system.cpu0.icache.demand_misses::total 380583 # number of demand (read+write) misses 314system.cpu0.icache.overall_misses::0 380583 # number of overall misses 315system.cpu0.icache.overall_misses::1 0 # number of overall misses 316system.cpu0.icache.overall_misses::total 380583 # number of overall misses 317system.cpu0.icache.ReadReq_miss_latency 5651439000 # number of ReadReq miss cycles 318system.cpu0.icache.demand_miss_latency 5651439000 # number of demand (read+write) miss cycles 319system.cpu0.icache.overall_miss_latency 5651439000 # number of overall miss cycles 320system.cpu0.icache.ReadReq_accesses::0 35747894 # number of ReadReq accesses(hits+misses) 321system.cpu0.icache.ReadReq_accesses::total 35747894 # number of ReadReq accesses(hits+misses) 322system.cpu0.icache.demand_accesses::0 35747894 # number of demand (read+write) accesses 323system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses 324system.cpu0.icache.demand_accesses::total 35747894 # number of demand (read+write) accesses 325system.cpu0.icache.overall_accesses::0 35747894 # number of overall (read+write) accesses 326system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses 327system.cpu0.icache.overall_accesses::total 35747894 # number of overall (read+write) accesses 328system.cpu0.icache.ReadReq_miss_rate::0 0.010646 # miss rate for ReadReq accesses 329system.cpu0.icache.demand_miss_rate::0 0.010646 # miss rate for demand accesses 330system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses 331system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses 332system.cpu0.icache.overall_miss_rate::0 0.010646 # miss rate for overall accesses 333system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses 334system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses 335system.cpu0.icache.ReadReq_avg_miss_latency::0 14849.425749 # average ReadReq miss latency 336system.cpu0.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency 337system.cpu0.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency 338system.cpu0.icache.demand_avg_miss_latency::0 14849.425749 # average overall miss latency 339system.cpu0.icache.demand_avg_miss_latency::1 inf # average overall miss latency 340system.cpu0.icache.demand_avg_miss_latency::total inf # average overall miss latency 341system.cpu0.icache.overall_avg_miss_latency::0 14849.425749 # average overall miss latency 342system.cpu0.icache.overall_avg_miss_latency::1 inf # average overall miss latency 343system.cpu0.icache.overall_avg_miss_latency::total inf # average overall miss latency 344system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 345system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 346system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 347system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 348system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 349system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 350system.cpu0.icache.fast_writes 0 # number of fast writes performed 351system.cpu0.icache.cache_copies 0 # number of cache copies performed 352system.cpu0.icache.writebacks 12960 # number of writebacks 353system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 354system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits 355system.cpu0.icache.ReadReq_mshr_misses 380583 # number of ReadReq MSHR misses 356system.cpu0.icache.demand_mshr_misses 380583 # number of demand (read+write) MSHR misses 357system.cpu0.icache.overall_mshr_misses 380583 # number of overall MSHR misses 358system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 359system.cpu0.icache.ReadReq_mshr_miss_latency 4509188500 # number of ReadReq MSHR miss cycles 360system.cpu0.icache.demand_mshr_miss_latency 4509188500 # number of demand (read+write) MSHR miss cycles 361system.cpu0.icache.overall_mshr_miss_latency 4509188500 # number of overall MSHR miss cycles 362system.cpu0.icache.ReadReq_mshr_uncacheable_latency 351814000 # number of ReadReq MSHR uncacheable cycles 363system.cpu0.icache.overall_mshr_uncacheable_latency 351814000 # number of overall MSHR uncacheable cycles 364system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.010646 # mshr miss rate for ReadReq accesses 365system.cpu0.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses 366system.cpu0.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses 367system.cpu0.icache.demand_mshr_miss_rate::0 0.010646 # mshr miss rate for demand accesses 368system.cpu0.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses 369system.cpu0.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses 370system.cpu0.icache.overall_mshr_miss_rate::0 0.010646 # mshr miss rate for overall accesses 371system.cpu0.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses 372system.cpu0.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses 373system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11848.108034 # average ReadReq mshr miss latency 374system.cpu0.icache.demand_avg_mshr_miss_latency 11848.108034 # average overall mshr miss latency 375system.cpu0.icache.overall_avg_mshr_miss_latency 11848.108034 # average overall mshr miss latency 376system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency 377system.cpu0.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency 378system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated 379system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 380system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 381system.cpu0.dcache.replacements 334596 # number of replacements 382system.cpu0.dcache.tagsinuse 450.118381 # Cycle average of tags in use 383system.cpu0.dcache.total_refs 12875674 # Total number of references to valid blocks. 384system.cpu0.dcache.sampled_refs 335004 # Sample count of references to valid blocks. 385system.cpu0.dcache.avg_refs 38.434389 # Average number of references to valid blocks. 386system.cpu0.dcache.warmup_cycle 663204000 # Cycle when the warmup percentage was hit. 387system.cpu0.dcache.occ_blocks::0 450.118381 # Average occupied blocks per context 388system.cpu0.dcache.occ_percent::0 0.879137 # Average percentage of cache occupancy 389system.cpu0.dcache.ReadReq_hits::0 7428609 # number of ReadReq hits 390system.cpu0.dcache.ReadReq_hits::total 7428609 # number of ReadReq hits 391system.cpu0.dcache.WriteReq_hits::0 5172633 # number of WriteReq hits 392system.cpu0.dcache.WriteReq_hits::total 5172633 # number of WriteReq hits 393system.cpu0.dcache.LoadLockedReq_hits::0 126778 # number of LoadLockedReq hits 394system.cpu0.dcache.LoadLockedReq_hits::total 126778 # number of LoadLockedReq hits 395system.cpu0.dcache.StoreCondReq_hits::0 127996 # number of StoreCondReq hits 396system.cpu0.dcache.StoreCondReq_hits::total 127996 # number of StoreCondReq hits 397system.cpu0.dcache.demand_hits::0 12601242 # number of demand (read+write) hits 398system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits 399system.cpu0.dcache.demand_hits::total 12601242 # number of demand (read+write) hits 400system.cpu0.dcache.overall_hits::0 12601242 # number of overall hits 401system.cpu0.dcache.overall_hits::1 0 # number of overall hits 402system.cpu0.dcache.overall_hits::total 12601242 # number of overall hits 403system.cpu0.dcache.ReadReq_misses::0 217330 # number of ReadReq misses 404system.cpu0.dcache.ReadReq_misses::total 217330 # number of ReadReq misses 405system.cpu0.dcache.WriteReq_misses::0 155538 # number of WriteReq misses 406system.cpu0.dcache.WriteReq_misses::total 155538 # number of WriteReq misses 407system.cpu0.dcache.LoadLockedReq_misses::0 9456 # number of LoadLockedReq misses 408system.cpu0.dcache.LoadLockedReq_misses::total 9456 # number of LoadLockedReq misses 409system.cpu0.dcache.StoreCondReq_misses::0 8189 # number of StoreCondReq misses 410system.cpu0.dcache.StoreCondReq_misses::total 8189 # number of StoreCondReq misses 411system.cpu0.dcache.demand_misses::0 372868 # number of demand (read+write) misses 412system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses 413system.cpu0.dcache.demand_misses::total 372868 # number of demand (read+write) misses 414system.cpu0.dcache.overall_misses::0 372868 # number of overall misses 415system.cpu0.dcache.overall_misses::1 0 # number of overall misses 416system.cpu0.dcache.overall_misses::total 372868 # number of overall misses 417system.cpu0.dcache.ReadReq_miss_latency 3330686000 # number of ReadReq miss cycles 418system.cpu0.dcache.WriteReq_miss_latency 6317758500 # number of WriteReq miss cycles 419system.cpu0.dcache.LoadLockedReq_miss_latency 100249000 # number of LoadLockedReq miss cycles 420system.cpu0.dcache.StoreCondReq_miss_latency 70240000 # number of StoreCondReq miss cycles 421system.cpu0.dcache.demand_miss_latency 9648444500 # number of demand (read+write) miss cycles 422system.cpu0.dcache.overall_miss_latency 9648444500 # number of overall miss cycles 423system.cpu0.dcache.ReadReq_accesses::0 7645939 # number of ReadReq accesses(hits+misses) 424system.cpu0.dcache.ReadReq_accesses::total 7645939 # number of ReadReq accesses(hits+misses) 425system.cpu0.dcache.WriteReq_accesses::0 5328171 # number of WriteReq accesses(hits+misses) 426system.cpu0.dcache.WriteReq_accesses::total 5328171 # number of WriteReq accesses(hits+misses) 427system.cpu0.dcache.LoadLockedReq_accesses::0 136234 # number of LoadLockedReq accesses(hits+misses) 428system.cpu0.dcache.LoadLockedReq_accesses::total 136234 # number of LoadLockedReq accesses(hits+misses) 429system.cpu0.dcache.StoreCondReq_accesses::0 136185 # number of StoreCondReq accesses(hits+misses) 430system.cpu0.dcache.StoreCondReq_accesses::total 136185 # number of StoreCondReq accesses(hits+misses) 431system.cpu0.dcache.demand_accesses::0 12974110 # number of demand (read+write) accesses 432system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses 433system.cpu0.dcache.demand_accesses::total 12974110 # number of demand (read+write) accesses 434system.cpu0.dcache.overall_accesses::0 12974110 # number of overall (read+write) accesses 435system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses 436system.cpu0.dcache.overall_accesses::total 12974110 # number of overall (read+write) accesses 437system.cpu0.dcache.ReadReq_miss_rate::0 0.028424 # miss rate for ReadReq accesses 438system.cpu0.dcache.WriteReq_miss_rate::0 0.029192 # miss rate for WriteReq accesses 439system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.069410 # miss rate for LoadLockedReq accesses 440system.cpu0.dcache.StoreCondReq_miss_rate::0 0.060131 # miss rate for StoreCondReq accesses 441system.cpu0.dcache.demand_miss_rate::0 0.028739 # miss rate for demand accesses 442system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses 443system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses 444system.cpu0.dcache.overall_miss_rate::0 0.028739 # miss rate for overall accesses 445system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses 446system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses 447system.cpu0.dcache.ReadReq_avg_miss_latency::0 15325.477385 # average ReadReq miss latency 448system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency 449system.cpu0.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency 450system.cpu0.dcache.WriteReq_avg_miss_latency::0 40618.745901 # average WriteReq miss latency 451system.cpu0.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency 452system.cpu0.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency 453system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 10601.628596 # average LoadLockedReq miss latency 454system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency 455system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency 456system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 8577.359873 # average StoreCondReq miss latency 457system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency 458system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency 459system.cpu0.dcache.demand_avg_miss_latency::0 25876.300728 # average overall miss latency 460system.cpu0.dcache.demand_avg_miss_latency::1 inf # average overall miss latency 461system.cpu0.dcache.demand_avg_miss_latency::total inf # average overall miss latency 462system.cpu0.dcache.overall_avg_miss_latency::0 25876.300728 # average overall miss latency 463system.cpu0.dcache.overall_avg_miss_latency::1 inf # average overall miss latency 464system.cpu0.dcache.overall_avg_miss_latency::total inf # average overall miss latency 465system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 466system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 467system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 468system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 469system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 470system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 471system.cpu0.dcache.fast_writes 0 # number of fast writes performed 472system.cpu0.dcache.cache_copies 0 # number of cache copies performed 473system.cpu0.dcache.writebacks 294891 # number of writebacks 474system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 475system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits 476system.cpu0.dcache.ReadReq_mshr_misses 217330 # number of ReadReq MSHR misses 477system.cpu0.dcache.WriteReq_mshr_misses 155538 # number of WriteReq MSHR misses 478system.cpu0.dcache.LoadLockedReq_mshr_misses 9456 # number of LoadLockedReq MSHR misses 479system.cpu0.dcache.StoreCondReq_mshr_misses 8184 # number of StoreCondReq MSHR misses 480system.cpu0.dcache.demand_mshr_misses 372868 # number of demand (read+write) MSHR misses 481system.cpu0.dcache.overall_mshr_misses 372868 # number of overall MSHR misses 482system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 483system.cpu0.dcache.ReadReq_mshr_miss_latency 2678673500 # number of ReadReq MSHR miss cycles 484system.cpu0.dcache.WriteReq_mshr_miss_latency 5851029000 # number of WriteReq MSHR miss cycles 485system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 71881000 # number of LoadLockedReq MSHR miss cycles 486system.cpu0.dcache.StoreCondReq_mshr_miss_latency 45691000 # number of StoreCondReq MSHR miss cycles 487system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency 1000 # number of StoreCondFailReq MSHR miss cycles 488system.cpu0.dcache.demand_mshr_miss_latency 8529702500 # number of demand (read+write) MSHR miss cycles 489system.cpu0.dcache.overall_mshr_miss_latency 8529702500 # number of overall MSHR miss cycles 490system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 9171180500 # number of ReadReq MSHR uncacheable cycles 491system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 40129379500 # number of WriteReq MSHR uncacheable cycles 492system.cpu0.dcache.overall_mshr_uncacheable_latency 49300560000 # number of overall MSHR uncacheable cycles 493system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.028424 # mshr miss rate for ReadReq accesses 494system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses 495system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses 496system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.029192 # mshr miss rate for WriteReq accesses 497system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses 498system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses 499system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.069410 # mshr miss rate for LoadLockedReq accesses 500system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses 501system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses 502system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.060095 # mshr miss rate for StoreCondReq accesses 503system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses 504system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses 505system.cpu0.dcache.demand_mshr_miss_rate::0 0.028739 # mshr miss rate for demand accesses 506system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses 507system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses 508system.cpu0.dcache.overall_mshr_miss_rate::0 0.028739 # mshr miss rate for overall accesses 509system.cpu0.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses 510system.cpu0.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses 511system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 12325.373855 # average ReadReq mshr miss latency 512system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 37618.003318 # average WriteReq mshr miss latency 513system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 7601.628596 # average LoadLockedReq mshr miss latency 514system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 5582.966764 # average StoreCondReq mshr miss latency 515system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency inf # average StoreCondFailReq mshr miss latency 516system.cpu0.dcache.demand_avg_mshr_miss_latency 22875.930624 # average overall mshr miss latency 517system.cpu0.dcache.overall_avg_mshr_miss_latency 22875.930624 # average overall mshr miss latency 518system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency 519system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency 520system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency 521system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 522system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 523system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 524system.cpu1.dtb.inst_hits 0 # ITB inst hits 525system.cpu1.dtb.inst_misses 0 # ITB inst misses 526system.cpu1.dtb.read_hits 7762496 # DTB read hits 527system.cpu1.dtb.read_misses 5432 # DTB read misses 528system.cpu1.dtb.write_hits 5411648 # DTB write hits 529system.cpu1.dtb.write_misses 1096 # DTB write misses 530system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 531system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 532system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 533system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 534system.cpu1.dtb.flush_entries 2346 # Number of entries that have been flushed from TLB 535system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 536system.cpu1.dtb.prefetch_faults 166 # Number of TLB faults due to prefetch 537system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 538system.cpu1.dtb.perms_faults 261 # Number of TLB faults due to permissions restrictions 539system.cpu1.dtb.read_accesses 7767928 # DTB read accesses 540system.cpu1.dtb.write_accesses 5412744 # DTB write accesses 541system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 542system.cpu1.dtb.hits 13174144 # DTB hits 543system.cpu1.dtb.misses 6528 # DTB misses 544system.cpu1.dtb.accesses 13180672 # DTB accesses 545system.cpu1.itb.inst_hits 26848280 # ITB inst hits 546system.cpu1.itb.inst_misses 3154 # ITB inst misses 547system.cpu1.itb.read_hits 0 # DTB read hits 548system.cpu1.itb.read_misses 0 # DTB read misses 549system.cpu1.itb.write_hits 0 # DTB write hits 550system.cpu1.itb.write_misses 0 # DTB write misses 551system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 552system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 553system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 554system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 555system.cpu1.itb.flush_entries 1544 # Number of entries that have been flushed from TLB 556system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 557system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 558system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 559system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 560system.cpu1.itb.read_accesses 0 # DTB read accesses 561system.cpu1.itb.write_accesses 0 # DTB write accesses 562system.cpu1.itb.inst_accesses 26851434 # ITB inst accesses 563system.cpu1.itb.hits 26848280 # DTB hits 564system.cpu1.itb.misses 3154 # DTB misses 565system.cpu1.itb.accesses 26851434 # DTB accesses 566system.cpu1.numCycles 5339222450 # number of cpu cycles simulated 567system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 568system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 569system.cpu1.num_insts 34444935 # Number of instructions executed 570system.cpu1.num_int_alu_accesses 31033253 # Number of integer alu accesses 571system.cpu1.num_fp_alu_accesses 5714 # Number of float alu accesses 572system.cpu1.num_func_calls 1093852 # number of times a function call or return occured 573system.cpu1.num_conditional_control_insts 3362553 # number of instructions that are conditional controls 574system.cpu1.num_int_insts 31033253 # number of integer instructions 575system.cpu1.num_fp_insts 5714 # number of float instructions 576system.cpu1.num_int_register_reads 181157193 # number of times the integer registers were read 577system.cpu1.num_int_register_writes 32585304 # number of times the integer registers were written 578system.cpu1.num_fp_register_reads 3770 # number of times the floating registers were read 579system.cpu1.num_fp_register_writes 1948 # number of times the floating registers were written 580system.cpu1.num_mem_refs 13796843 # number of memory refs 581system.cpu1.num_load_insts 8139019 # Number of load instructions 582system.cpu1.num_store_insts 5657824 # Number of store instructions 583system.cpu1.num_idle_cycles 4950307250.068146 # Number of idle cycles 584system.cpu1.num_busy_cycles 388915199.931854 # Number of busy cycles 585system.cpu1.not_idle_fraction 0.072841 # Percentage of non-idle cycles 586system.cpu1.idle_fraction 0.927159 # Percentage of idle cycles 587system.cpu1.kern.inst.arm 0 # number of arm instructions executed 588system.cpu1.kern.inst.quiesce 53838 # number of quiesce instructions executed 589system.cpu1.icache.replacements 508221 # number of replacements 590system.cpu1.icache.tagsinuse 497.375159 # Cycle average of tags in use 591system.cpu1.icache.total_refs 26339543 # Total number of references to valid blocks. 592system.cpu1.icache.sampled_refs 508733 # Sample count of references to valid blocks. 593system.cpu1.icache.avg_refs 51.774788 # Average number of references to valid blocks. 594system.cpu1.icache.warmup_cycle 191336880000 # Cycle when the warmup percentage was hit. 595system.cpu1.icache.occ_blocks::0 497.375159 # Average occupied blocks per context 596system.cpu1.icache.occ_percent::0 0.971436 # Average percentage of cache occupancy 597system.cpu1.icache.ReadReq_hits::0 26339543 # number of ReadReq hits 598system.cpu1.icache.ReadReq_hits::total 26339543 # number of ReadReq hits 599system.cpu1.icache.demand_hits::0 26339543 # number of demand (read+write) hits 600system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits 601system.cpu1.icache.demand_hits::total 26339543 # number of demand (read+write) hits 602system.cpu1.icache.overall_hits::0 26339543 # number of overall hits 603system.cpu1.icache.overall_hits::1 0 # number of overall hits 604system.cpu1.icache.overall_hits::total 26339543 # number of overall hits 605system.cpu1.icache.ReadReq_misses::0 508733 # number of ReadReq misses 606system.cpu1.icache.ReadReq_misses::total 508733 # number of ReadReq misses 607system.cpu1.icache.demand_misses::0 508733 # number of demand (read+write) misses 608system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses 609system.cpu1.icache.demand_misses::total 508733 # number of demand (read+write) misses 610system.cpu1.icache.overall_misses::0 508733 # number of overall misses 611system.cpu1.icache.overall_misses::1 0 # number of overall misses 612system.cpu1.icache.overall_misses::total 508733 # number of overall misses 613system.cpu1.icache.ReadReq_miss_latency 7436442000 # number of ReadReq miss cycles 614system.cpu1.icache.demand_miss_latency 7436442000 # number of demand (read+write) miss cycles 615system.cpu1.icache.overall_miss_latency 7436442000 # number of overall miss cycles 616system.cpu1.icache.ReadReq_accesses::0 26848276 # number of ReadReq accesses(hits+misses) 617system.cpu1.icache.ReadReq_accesses::total 26848276 # number of ReadReq accesses(hits+misses) 618system.cpu1.icache.demand_accesses::0 26848276 # number of demand (read+write) accesses 619system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses 620system.cpu1.icache.demand_accesses::total 26848276 # number of demand (read+write) accesses 621system.cpu1.icache.overall_accesses::0 26848276 # number of overall (read+write) accesses 622system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses 623system.cpu1.icache.overall_accesses::total 26848276 # number of overall (read+write) accesses 624system.cpu1.icache.ReadReq_miss_rate::0 0.018948 # miss rate for ReadReq accesses 625system.cpu1.icache.demand_miss_rate::0 0.018948 # miss rate for demand accesses 626system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses 627system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses 628system.cpu1.icache.overall_miss_rate::0 0.018948 # miss rate for overall accesses 629system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses 630system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses 631system.cpu1.icache.ReadReq_avg_miss_latency::0 14617.573462 # average ReadReq miss latency 632system.cpu1.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency 633system.cpu1.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency 634system.cpu1.icache.demand_avg_miss_latency::0 14617.573462 # average overall miss latency 635system.cpu1.icache.demand_avg_miss_latency::1 inf # average overall miss latency 636system.cpu1.icache.demand_avg_miss_latency::total inf # average overall miss latency 637system.cpu1.icache.overall_avg_miss_latency::0 14617.573462 # average overall miss latency 638system.cpu1.icache.overall_avg_miss_latency::1 inf # average overall miss latency 639system.cpu1.icache.overall_avg_miss_latency::total inf # average overall miss latency 640system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 641system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 642system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 643system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 644system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 645system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 646system.cpu1.icache.fast_writes 0 # number of fast writes performed 647system.cpu1.icache.cache_copies 0 # number of cache copies performed 648system.cpu1.icache.writebacks 27998 # number of writebacks 649system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 650system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits 651system.cpu1.icache.ReadReq_mshr_misses 508733 # number of ReadReq MSHR misses 652system.cpu1.icache.demand_mshr_misses 508733 # number of demand (read+write) MSHR misses 653system.cpu1.icache.overall_mshr_misses 508733 # number of overall MSHR misses 654system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 655system.cpu1.icache.ReadReq_mshr_miss_latency 5908060000 # number of ReadReq MSHR miss cycles 656system.cpu1.icache.demand_mshr_miss_latency 5908060000 # number of demand (read+write) MSHR miss cycles 657system.cpu1.icache.overall_mshr_miss_latency 5908060000 # number of overall MSHR miss cycles 658system.cpu1.icache.ReadReq_mshr_uncacheable_latency 5250000 # number of ReadReq MSHR uncacheable cycles 659system.cpu1.icache.overall_mshr_uncacheable_latency 5250000 # number of overall MSHR uncacheable cycles 660system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.018948 # mshr miss rate for ReadReq accesses 661system.cpu1.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses 662system.cpu1.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses 663system.cpu1.icache.demand_mshr_miss_rate::0 0.018948 # mshr miss rate for demand accesses 664system.cpu1.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses 665system.cpu1.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses 666system.cpu1.icache.overall_mshr_miss_rate::0 0.018948 # mshr miss rate for overall accesses 667system.cpu1.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses 668system.cpu1.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses 669system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11613.282409 # average ReadReq mshr miss latency 670system.cpu1.icache.demand_avg_mshr_miss_latency 11613.282409 # average overall mshr miss latency 671system.cpu1.icache.overall_avg_mshr_miss_latency 11613.282409 # average overall mshr miss latency 672system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency 673system.cpu1.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency 674system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated 675system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 676system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 677system.cpu1.dcache.replacements 295754 # number of replacements 678system.cpu1.dcache.tagsinuse 467.166427 # Cycle average of tags in use 679system.cpu1.dcache.total_refs 11737107 # Total number of references to valid blocks. 680system.cpu1.dcache.sampled_refs 296266 # Sample count of references to valid blocks. 681system.cpu1.dcache.avg_refs 39.616787 # Average number of references to valid blocks. 682system.cpu1.dcache.warmup_cycle 75924171000 # Cycle when the warmup percentage was hit. 683system.cpu1.dcache.occ_blocks::0 467.166427 # Average occupied blocks per context 684system.cpu1.dcache.occ_percent::0 0.912434 # Average percentage of cache occupancy 685system.cpu1.dcache.ReadReq_hits::0 6345290 # number of ReadReq hits 686system.cpu1.dcache.ReadReq_hits::total 6345290 # number of ReadReq hits 687system.cpu1.dcache.WriteReq_hits::0 5152610 # number of WriteReq hits 688system.cpu1.dcache.WriteReq_hits::total 5152610 # number of WriteReq hits 689system.cpu1.dcache.LoadLockedReq_hits::0 104795 # number of LoadLockedReq hits 690system.cpu1.dcache.LoadLockedReq_hits::total 104795 # number of LoadLockedReq hits 691system.cpu1.dcache.StoreCondReq_hits::0 106403 # number of StoreCondReq hits 692system.cpu1.dcache.StoreCondReq_hits::total 106403 # number of StoreCondReq hits 693system.cpu1.dcache.demand_hits::0 11497900 # number of demand (read+write) hits 694system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits 695system.cpu1.dcache.demand_hits::total 11497900 # number of demand (read+write) hits 696system.cpu1.dcache.overall_hits::0 11497900 # number of overall hits 697system.cpu1.dcache.overall_hits::1 0 # number of overall hits 698system.cpu1.dcache.overall_hits::total 11497900 # number of overall hits 699system.cpu1.dcache.ReadReq_misses::0 188245 # number of ReadReq misses 700system.cpu1.dcache.ReadReq_misses::total 188245 # number of ReadReq misses 701system.cpu1.dcache.WriteReq_misses::0 137493 # number of WriteReq misses 702system.cpu1.dcache.WriteReq_misses::total 137493 # number of WriteReq misses 703system.cpu1.dcache.LoadLockedReq_misses::0 11557 # number of LoadLockedReq misses 704system.cpu1.dcache.LoadLockedReq_misses::total 11557 # number of LoadLockedReq misses 705system.cpu1.dcache.StoreCondReq_misses::0 9906 # number of StoreCondReq misses 706system.cpu1.dcache.StoreCondReq_misses::total 9906 # number of StoreCondReq misses 707system.cpu1.dcache.demand_misses::0 325738 # number of demand (read+write) misses 708system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses 709system.cpu1.dcache.demand_misses::total 325738 # number of demand (read+write) misses 710system.cpu1.dcache.overall_misses::0 325738 # number of overall misses 711system.cpu1.dcache.overall_misses::1 0 # number of overall misses 712system.cpu1.dcache.overall_misses::total 325738 # number of overall misses 713system.cpu1.dcache.ReadReq_miss_latency 2729023500 # number of ReadReq miss cycles 714system.cpu1.dcache.WriteReq_miss_latency 4123985000 # number of WriteReq miss cycles 715system.cpu1.dcache.LoadLockedReq_miss_latency 131721000 # number of LoadLockedReq miss cycles 716system.cpu1.dcache.StoreCondReq_miss_latency 82493000 # number of StoreCondReq miss cycles 717system.cpu1.dcache.demand_miss_latency 6853008500 # number of demand (read+write) miss cycles 718system.cpu1.dcache.overall_miss_latency 6853008500 # number of overall miss cycles 719system.cpu1.dcache.ReadReq_accesses::0 6533535 # number of ReadReq accesses(hits+misses) 720system.cpu1.dcache.ReadReq_accesses::total 6533535 # number of ReadReq accesses(hits+misses) 721system.cpu1.dcache.WriteReq_accesses::0 5290103 # number of WriteReq accesses(hits+misses) 722system.cpu1.dcache.WriteReq_accesses::total 5290103 # number of WriteReq accesses(hits+misses) 723system.cpu1.dcache.LoadLockedReq_accesses::0 116352 # number of LoadLockedReq accesses(hits+misses) 724system.cpu1.dcache.LoadLockedReq_accesses::total 116352 # number of LoadLockedReq accesses(hits+misses) 725system.cpu1.dcache.StoreCondReq_accesses::0 116309 # number of StoreCondReq accesses(hits+misses) 726system.cpu1.dcache.StoreCondReq_accesses::total 116309 # number of StoreCondReq accesses(hits+misses) 727system.cpu1.dcache.demand_accesses::0 11823638 # number of demand (read+write) accesses 728system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses 729system.cpu1.dcache.demand_accesses::total 11823638 # number of demand (read+write) accesses 730system.cpu1.dcache.overall_accesses::0 11823638 # number of overall (read+write) accesses 731system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses 732system.cpu1.dcache.overall_accesses::total 11823638 # number of overall (read+write) accesses 733system.cpu1.dcache.ReadReq_miss_rate::0 0.028812 # miss rate for ReadReq accesses 734system.cpu1.dcache.WriteReq_miss_rate::0 0.025991 # miss rate for WriteReq accesses 735system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.099328 # miss rate for LoadLockedReq accesses 736system.cpu1.dcache.StoreCondReq_miss_rate::0 0.085170 # miss rate for StoreCondReq accesses 737system.cpu1.dcache.demand_miss_rate::0 0.027550 # miss rate for demand accesses 738system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses 739system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses 740system.cpu1.dcache.overall_miss_rate::0 0.027550 # miss rate for overall accesses 741system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses 742system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses 743system.cpu1.dcache.ReadReq_avg_miss_latency::0 14497.189832 # average ReadReq miss latency 744system.cpu1.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency 745system.cpu1.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency 746system.cpu1.dcache.WriteReq_avg_miss_latency::0 29994.145156 # average WriteReq miss latency 747system.cpu1.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency 748system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency 749system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 11397.508004 # average LoadLockedReq miss latency 750system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency 751system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency 752system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 8327.579245 # average StoreCondReq miss latency 753system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency 754system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency 755system.cpu1.dcache.demand_avg_miss_latency::0 21038.406634 # average overall miss latency 756system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency 757system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency 758system.cpu1.dcache.overall_avg_miss_latency::0 21038.406634 # average overall miss latency 759system.cpu1.dcache.overall_avg_miss_latency::1 inf # average overall miss latency 760system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency 761system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 762system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 763system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 764system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 765system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 766system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 767system.cpu1.dcache.fast_writes 0 # number of fast writes performed 768system.cpu1.dcache.cache_copies 0 # number of cache copies performed 769system.cpu1.dcache.writebacks 253551 # number of writebacks 770system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 771system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits 772system.cpu1.dcache.ReadReq_mshr_misses 188245 # number of ReadReq MSHR misses 773system.cpu1.dcache.WriteReq_mshr_misses 137493 # number of WriteReq MSHR misses 774system.cpu1.dcache.LoadLockedReq_mshr_misses 11557 # number of LoadLockedReq MSHR misses 775system.cpu1.dcache.StoreCondReq_mshr_misses 9900 # number of StoreCondReq MSHR misses 776system.cpu1.dcache.demand_mshr_misses 325738 # number of demand (read+write) MSHR misses 777system.cpu1.dcache.overall_mshr_misses 325738 # number of overall MSHR misses 778system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 779system.cpu1.dcache.ReadReq_mshr_miss_latency 2164153000 # number of ReadReq MSHR miss cycles 780system.cpu1.dcache.WriteReq_mshr_miss_latency 3711466500 # number of WriteReq MSHR miss cycles 781system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 97050000 # number of LoadLockedReq MSHR miss cycles 782system.cpu1.dcache.StoreCondReq_mshr_miss_latency 52793000 # number of StoreCondReq MSHR miss cycles 783system.cpu1.dcache.demand_mshr_miss_latency 5875619500 # number of demand (read+write) MSHR miss cycles 784system.cpu1.dcache.overall_mshr_miss_latency 5875619500 # number of overall MSHR miss cycles 785system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 137931975000 # number of ReadReq MSHR uncacheable cycles 786system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 470526000 # number of WriteReq MSHR uncacheable cycles 787system.cpu1.dcache.overall_mshr_uncacheable_latency 138402501000 # number of overall MSHR uncacheable cycles 788system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.028812 # mshr miss rate for ReadReq accesses 789system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses 790system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses 791system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.025991 # mshr miss rate for WriteReq accesses 792system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses 793system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses 794system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.099328 # mshr miss rate for LoadLockedReq accesses 795system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses 796system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses 797system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.085118 # mshr miss rate for StoreCondReq accesses 798system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses 799system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses 800system.cpu1.dcache.demand_mshr_miss_rate::0 0.027550 # mshr miss rate for demand accesses 801system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses 802system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses 803system.cpu1.dcache.overall_mshr_miss_rate::0 0.027550 # mshr miss rate for overall accesses 804system.cpu1.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses 805system.cpu1.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses 806system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11496.470026 # average ReadReq mshr miss latency 807system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 26993.857869 # average WriteReq mshr miss latency 808system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 8397.508004 # average LoadLockedReq mshr miss latency 809system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 5332.626263 # average StoreCondReq mshr miss latency 810system.cpu1.dcache.demand_avg_mshr_miss_latency 18037.869392 # average overall mshr miss latency 811system.cpu1.dcache.overall_avg_mshr_miss_latency 18037.869392 # average overall mshr miss latency 812system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency 813system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency 814system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency 815system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 816system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 817system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 818system.iocache.replacements 0 # number of replacements 819system.iocache.tagsinuse 0 # Cycle average of tags in use 820system.iocache.total_refs 0 # Total number of references to valid blocks. 821system.iocache.sampled_refs 0 # Sample count of references to valid blocks. 822system.iocache.avg_refs no_value # Average number of references to valid blocks. 823system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 824system.iocache.demand_hits::0 0 # number of demand (read+write) hits 825system.iocache.demand_hits::1 0 # number of demand (read+write) hits 826system.iocache.demand_hits::total 0 # number of demand (read+write) hits 827system.iocache.overall_hits::0 0 # number of overall hits 828system.iocache.overall_hits::1 0 # number of overall hits 829system.iocache.overall_hits::total 0 # number of overall hits 830system.iocache.demand_misses::0 0 # number of demand (read+write) misses 831system.iocache.demand_misses::1 0 # number of demand (read+write) misses 832system.iocache.demand_misses::total 0 # number of demand (read+write) misses 833system.iocache.overall_misses::0 0 # number of overall misses 834system.iocache.overall_misses::1 0 # number of overall misses 835system.iocache.overall_misses::total 0 # number of overall misses 836system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles 837system.iocache.overall_miss_latency 0 # number of overall miss cycles 838system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses 839system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses 840system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses 841system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses 842system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses 843system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses 844system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses 845system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses 846system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses 847system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses 848system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses 849system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses 850system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency 851system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency 852system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency 853system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency 854system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency 855system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency 856system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 857system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 858system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 859system.iocache.blocked::no_targets 0 # number of cycles access was blocked 860system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 861system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 862system.iocache.fast_writes 0 # number of fast writes performed 863system.iocache.cache_copies 0 # number of cache copies performed 864system.iocache.writebacks 0 # number of writebacks 865system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 866system.iocache.overall_mshr_hits 0 # number of overall MSHR hits 867system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 868system.iocache.overall_mshr_misses 0 # number of overall MSHR misses 869system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 870system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 871system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 872system.iocache.ReadReq_mshr_uncacheable_latency 1342252853622 # number of ReadReq MSHR uncacheable cycles 873system.iocache.overall_mshr_uncacheable_latency 1342252853622 # number of overall MSHR uncacheable cycles 874system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses 875system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses 876system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses 877system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses 878system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses 879system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses 880system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 881system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 882system.iocache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency 883system.iocache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency 884system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated 885system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 886system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 887 888---------- End Simulation Statistics ---------- 889