stats.txt revision 11731:c473ca7cc650
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.870989 # Number of seconds simulated 4sim_ticks 2870988926500 # Number of ticks simulated 5final_tick 2870988926500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 334502 # Simulator instruction rate (inst/s) 8host_op_rate 404603 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 7301303629 # Simulator tick rate (ticks/s) 10host_mem_usage 607968 # Number of bytes of host memory used 11host_seconds 393.22 # Real time elapsed on the host 12sim_insts 131531628 # Number of instructions simulated 13sim_ops 159096162 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 1180196 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 1293924 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu0.l2cache.prefetcher 8559616 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.inst 153620 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.data 569684 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.l2cache.prefetcher 405184 # Number of bytes read from this memory 25system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 26system.physmem.bytes_read::total 12163760 # Number of bytes read from this memory 27system.physmem.bytes_inst_read::cpu0.inst 1180196 # Number of instructions bytes read from this memory 28system.physmem.bytes_inst_read::cpu1.inst 153620 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::total 1333816 # Number of instructions bytes read from this memory 30system.physmem.bytes_written::writebacks 8766400 # Number of bytes written to this memory 31system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory 32system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory 33system.physmem.bytes_written::total 8783964 # Number of bytes written to this memory 34system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.inst 26894 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.data 20737 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.l2cache.prefetcher 133744 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu1.inst 2555 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.data 8922 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.l2cache.prefetcher 6331 # Number of read requests responded to by this memory 42system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 43system.physmem.num_reads::total 199207 # Number of read requests responded to by this memory 44system.physmem.num_writes::writebacks 136975 # Number of write requests responded to by this memory 45system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory 46system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory 47system.physmem.num_writes::total 141366 # Number of write requests responded to by this memory 48system.physmem.bw_read::cpu0.dtb.walker 156 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu0.inst 411076 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu0.data 450689 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.l2cache.prefetcher 2981417 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu1.inst 53508 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu1.data 198428 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu1.l2cache.prefetcher 141130 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::realview.ide 334 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::total 4236784 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_inst_read::cpu0.inst 411076 # Instruction read bandwidth from this memory (bytes/s) 59system.physmem.bw_inst_read::cpu1.inst 53508 # Instruction read bandwidth from this memory (bytes/s) 60system.physmem.bw_inst_read::total 464584 # Instruction read bandwidth from this memory (bytes/s) 61system.physmem.bw_write::writebacks 3053443 # Write bandwidth from this memory (bytes/s) 62system.physmem.bw_write::cpu0.data 6104 # Write bandwidth from this memory (bytes/s) 63system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) 64system.physmem.bw_write::total 3059560 # Write bandwidth from this memory (bytes/s) 65system.physmem.bw_total::writebacks 3053443 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::cpu0.dtb.walker 156 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::cpu0.inst 411076 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::cpu0.data 456793 # Total bandwidth to/from this memory (bytes/s) 70system.physmem.bw_total::cpu0.l2cache.prefetcher 2981417 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu1.inst 53508 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu1.data 198442 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu1.l2cache.prefetcher 141130 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::realview.ide 334 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::total 7296344 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.readReqs 199207 # Number of read requests accepted 77system.physmem.writeReqs 141366 # Number of write requests accepted 78system.physmem.readBursts 199207 # Number of DRAM read bursts, including those serviced by the write queue 79system.physmem.writeBursts 141366 # Number of DRAM write bursts, including those merged in the write queue 80system.physmem.bytesReadDRAM 12740608 # Total number of bytes read from DRAM 81system.physmem.bytesReadWrQ 8640 # Total number of bytes read from write queue 82system.physmem.bytesWritten 8796800 # Total number of bytes written to DRAM 83system.physmem.bytesReadSys 12163760 # Total read bytes from the system interface side 84system.physmem.bytesWrittenSys 8783964 # Total written bytes from the system interface side 85system.physmem.servicedByWrQ 135 # Number of DRAM read bursts serviced by the write queue 86system.physmem.mergedWrBursts 3897 # Number of DRAM write bursts merged with an existing one 87system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 88system.physmem.perBankRdBursts::0 11688 # Per bank write bursts 89system.physmem.perBankRdBursts::1 11970 # Per bank write bursts 90system.physmem.perBankRdBursts::2 12095 # Per bank write bursts 91system.physmem.perBankRdBursts::3 12159 # Per bank write bursts 92system.physmem.perBankRdBursts::4 20723 # Per bank write bursts 93system.physmem.perBankRdBursts::5 12090 # Per bank write bursts 94system.physmem.perBankRdBursts::6 12329 # Per bank write bursts 95system.physmem.perBankRdBursts::7 12246 # Per bank write bursts 96system.physmem.perBankRdBursts::8 12200 # Per bank write bursts 97system.physmem.perBankRdBursts::9 12543 # Per bank write bursts 98system.physmem.perBankRdBursts::10 11897 # Per bank write bursts 99system.physmem.perBankRdBursts::11 11487 # Per bank write bursts 100system.physmem.perBankRdBursts::12 11682 # Per bank write bursts 101system.physmem.perBankRdBursts::13 11835 # Per bank write bursts 102system.physmem.perBankRdBursts::14 11042 # Per bank write bursts 103system.physmem.perBankRdBursts::15 11086 # Per bank write bursts 104system.physmem.perBankWrBursts::0 8412 # Per bank write bursts 105system.physmem.perBankWrBursts::1 8881 # Per bank write bursts 106system.physmem.perBankWrBursts::2 9049 # Per bank write bursts 107system.physmem.perBankWrBursts::3 8857 # Per bank write bursts 108system.physmem.perBankWrBursts::4 8522 # Per bank write bursts 109system.physmem.perBankWrBursts::5 8714 # Per bank write bursts 110system.physmem.perBankWrBursts::6 9020 # Per bank write bursts 111system.physmem.perBankWrBursts::7 8690 # Per bank write bursts 112system.physmem.perBankWrBursts::8 8720 # Per bank write bursts 113system.physmem.perBankWrBursts::9 9031 # Per bank write bursts 114system.physmem.perBankWrBursts::10 8698 # Per bank write bursts 115system.physmem.perBankWrBursts::11 8602 # Per bank write bursts 116system.physmem.perBankWrBursts::12 8645 # Per bank write bursts 117system.physmem.perBankWrBursts::13 8180 # Per bank write bursts 118system.physmem.perBankWrBursts::14 7869 # Per bank write bursts 119system.physmem.perBankWrBursts::15 7560 # Per bank write bursts 120system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 121system.physmem.numWrRetry 78 # Number of times write queue was full causing retry 122system.physmem.totGap 2870987895000 # Total gap between requests 123system.physmem.readPktSize::0 0 # Read request sizes (log2) 124system.physmem.readPktSize::1 0 # Read request sizes (log2) 125system.physmem.readPktSize::2 9732 # Read request sizes (log2) 126system.physmem.readPktSize::3 28 # Read request sizes (log2) 127system.physmem.readPktSize::4 0 # Read request sizes (log2) 128system.physmem.readPktSize::5 0 # Read request sizes (log2) 129system.physmem.readPktSize::6 189447 # Read request sizes (log2) 130system.physmem.writePktSize::0 0 # Write request sizes (log2) 131system.physmem.writePktSize::1 0 # Write request sizes (log2) 132system.physmem.writePktSize::2 4391 # Write request sizes (log2) 133system.physmem.writePktSize::3 0 # Write request sizes (log2) 134system.physmem.writePktSize::4 0 # Write request sizes (log2) 135system.physmem.writePktSize::5 0 # Write request sizes (log2) 136system.physmem.writePktSize::6 136975 # Write request sizes (log2) 137system.physmem.rdQLenPdf::0 135724 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::1 17225 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::2 10602 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::3 8875 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::4 7477 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::5 5952 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::6 5078 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::7 4199 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::8 3667 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::9 121 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::10 77 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::11 48 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::12 18 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::13 5 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::14 2 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 169system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::15 2512 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::16 3419 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::17 4336 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::18 5352 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::19 6399 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::20 6487 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::21 7013 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::22 7539 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::23 8538 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::24 8343 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::25 9670 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::26 10012 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::27 8667 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::28 8175 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::29 8451 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::30 9504 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::31 7890 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::32 7649 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::33 684 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::34 494 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::35 441 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::36 314 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::37 288 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::38 258 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::39 286 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::40 251 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::41 223 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::42 221 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::43 209 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::44 247 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::45 202 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::46 216 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::47 176 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::48 210 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::49 198 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::50 219 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::51 158 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::52 200 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::53 194 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::54 153 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::55 170 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::56 240 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::57 166 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::58 129 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::59 213 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::60 198 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::61 190 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::62 118 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::63 232 # What write queue length does an incoming req see 233system.physmem.bytesPerActivate::samples 85540 # Bytes accessed per row activation 234system.physmem.bytesPerActivate::mean 251.780968 # Bytes accessed per row activation 235system.physmem.bytesPerActivate::gmean 143.250026 # Bytes accessed per row activation 236system.physmem.bytesPerActivate::stdev 307.334701 # Bytes accessed per row activation 237system.physmem.bytesPerActivate::0-127 42821 50.06% 50.06% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::128-255 18143 21.21% 71.27% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::256-383 6218 7.27% 78.54% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::384-511 3674 4.30% 82.83% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::512-639 2664 3.11% 85.95% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::640-767 1727 2.02% 87.97% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::768-895 953 1.11% 89.08% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::896-1023 967 1.13% 90.21% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::1024-1151 8373 9.79% 100.00% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::total 85540 # Bytes accessed per row activation 247system.physmem.rdPerTurnAround::samples 6799 # Reads before turning the bus around for writes 248system.physmem.rdPerTurnAround::mean 29.279453 # Reads before turning the bus around for writes 249system.physmem.rdPerTurnAround::stdev 564.517669 # Reads before turning the bus around for writes 250system.physmem.rdPerTurnAround::0-2047 6797 99.97% 99.97% # Reads before turning the bus around for writes 251system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes 252system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes 253system.physmem.rdPerTurnAround::total 6799 # Reads before turning the bus around for writes 254system.physmem.wrPerTurnAround::samples 6799 # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::mean 20.216208 # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::gmean 18.546976 # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::stdev 13.866150 # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::16-19 5813 85.50% 85.50% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::20-23 291 4.28% 89.78% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::24-27 61 0.90% 90.68% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::28-31 49 0.72% 91.40% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::32-35 268 3.94% 95.34% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::36-39 20 0.29% 95.63% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::40-43 11 0.16% 95.79% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::44-47 22 0.32% 96.12% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::48-51 12 0.18% 96.29% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::52-55 7 0.10% 96.40% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::56-59 6 0.09% 96.48% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::60-63 11 0.16% 96.65% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::64-67 154 2.27% 98.91% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::68-71 6 0.09% 99.00% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::72-75 3 0.04% 99.04% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::76-79 7 0.10% 99.15% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::80-83 4 0.06% 99.21% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::88-91 3 0.04% 99.25% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::92-95 1 0.01% 99.26% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::96-99 4 0.06% 99.32% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::100-103 1 0.01% 99.34% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::108-111 5 0.07% 99.41% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::112-115 1 0.01% 99.43% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::116-119 2 0.03% 99.46% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::124-127 4 0.06% 99.51% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::128-131 9 0.13% 99.65% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::132-135 4 0.06% 99.71% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::136-139 1 0.01% 99.72% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::140-143 4 0.06% 99.78% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::156-159 3 0.04% 99.82% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::160-163 2 0.03% 99.85% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::164-167 1 0.01% 99.87% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::168-171 1 0.01% 99.88% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::172-175 2 0.03% 99.91% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::176-179 1 0.01% 99.93% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::192-195 4 0.06% 99.99% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::204-207 1 0.01% 100.00% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::total 6799 # Writes before turning the bus around for reads 296system.physmem.totQLat 9415943788 # Total ticks spent queuing 297system.physmem.totMemAccLat 13148543788 # Total ticks spent from burst creation until serviced by the DRAM 298system.physmem.totBusLat 995360000 # Total ticks spent in databus transfers 299system.physmem.avgQLat 47299.19 # Average queueing delay per DRAM burst 300system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 301system.physmem.avgMemAccLat 66049.19 # Average memory access latency per DRAM burst 302system.physmem.avgRdBW 4.44 # Average DRAM read bandwidth in MiByte/s 303system.physmem.avgWrBW 3.06 # Average achieved write bandwidth in MiByte/s 304system.physmem.avgRdBWSys 4.24 # Average system read bandwidth in MiByte/s 305system.physmem.avgWrBWSys 3.06 # Average system write bandwidth in MiByte/s 306system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 307system.physmem.busUtil 0.06 # Data bus utilization in percentage 308system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 309system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 310system.physmem.avgRdQLen 1.13 # Average read queue length when enqueuing 311system.physmem.avgWrQLen 24.01 # Average write queue length when enqueuing 312system.physmem.readRowHits 166164 # Number of row buffer hits during reads 313system.physmem.writeRowHits 84817 # Number of row buffer hits during writes 314system.physmem.readRowHitRate 83.47 # Row buffer hit rate for reads 315system.physmem.writeRowHitRate 61.70 # Row buffer hit rate for writes 316system.physmem.avgGap 8429875.22 # Average gap between requests 317system.physmem.pageHitRate 74.58 # Row buffer hit rate, read and write combined 318system.physmem_0.actEnergy 312774840 # Energy for activate commands per rank (pJ) 319system.physmem_0.preEnergy 166239975 # Energy for precharge commands per rank (pJ) 320system.physmem_0.readEnergy 751842000 # Energy for read commands per rank (pJ) 321system.physmem_0.writeEnergy 366156900 # Energy for write commands per rank (pJ) 322system.physmem_0.refreshEnergy 6214010400.000001 # Energy for refresh commands per rank (pJ) 323system.physmem_0.actBackEnergy 5556704280 # Energy for active background per rank (pJ) 324system.physmem_0.preBackEnergy 357731520 # Energy for precharge background per rank (pJ) 325system.physmem_0.actPowerDownEnergy 11629133730 # Energy for active power-down per rank (pJ) 326system.physmem_0.prePowerDownEnergy 9364882080 # Energy for precharge power-down per rank (pJ) 327system.physmem_0.selfRefreshEnergy 675113260110 # Energy for self refresh per rank (pJ) 328system.physmem_0.totalEnergy 709836228825 # Total energy per rank (pJ) 329system.physmem_0.averagePower 247.244502 # Core power per rank (mW) 330system.physmem_0.totalIdleTime 2857863952057 # Total Idle time Per DRAM Rank 331system.physmem_0.memoryStateTime::IDLE 659296177 # Time in different power states 332system.physmem_0.memoryStateTime::REF 2641884000 # Time in different power states 333system.physmem_0.memoryStateTime::SREF 2807973624000 # Time in different power states 334system.physmem_0.memoryStateTime::PRE_PDN 24387714557 # Time in different power states 335system.physmem_0.memoryStateTime::ACT 9823730266 # Time in different power states 336system.physmem_0.memoryStateTime::ACT_PDN 25502677500 # Time in different power states 337system.physmem_1.actEnergy 297987900 # Energy for activate commands per rank (pJ) 338system.physmem_1.preEnergy 158384325 # Energy for precharge commands per rank (pJ) 339system.physmem_1.readEnergy 669532080 # Energy for read commands per rank (pJ) 340system.physmem_1.writeEnergy 351332100 # Energy for write commands per rank (pJ) 341system.physmem_1.refreshEnergy 6199259040.000001 # Energy for refresh commands per rank (pJ) 342system.physmem_1.actBackEnergy 5628324780 # Energy for active background per rank (pJ) 343system.physmem_1.preBackEnergy 351060000 # Energy for precharge background per rank (pJ) 344system.physmem_1.actPowerDownEnergy 11278473150 # Energy for active power-down per rank (pJ) 345system.physmem_1.prePowerDownEnergy 9521383680 # Energy for precharge power-down per rank (pJ) 346system.physmem_1.selfRefreshEnergy 675168861345 # Energy for self refresh per rank (pJ) 347system.physmem_1.totalEnergy 709627419000 # Total energy per rank (pJ) 348system.physmem_1.averagePower 247.171771 # Core power per rank (mW) 349system.physmem_1.totalIdleTime 2857510482171 # Total Idle time Per DRAM Rank 350system.physmem_1.memoryStateTime::IDLE 643430972 # Time in different power states 351system.physmem_1.memoryStateTime::REF 2635632000 # Time in different power states 352system.physmem_1.memoryStateTime::SREF 2808196835750 # Time in different power states 353system.physmem_1.memoryStateTime::PRE_PDN 24795240087 # Time in different power states 354system.physmem_1.memoryStateTime::ACT 9984355357 # Time in different power states 355system.physmem_1.memoryStateTime::ACT_PDN 24733432334 # Time in different power states 356system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 357system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 358system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 359system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 360system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 361system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 362system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 363system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 364system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 365system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 366system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) 367system.realview.nvmem.bw_read::cpu1.inst 17 # Total read bandwidth from this memory (bytes/s) 368system.realview.nvmem.bw_read::total 24 # Total read bandwidth from this memory (bytes/s) 369system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) 370system.realview.nvmem.bw_inst_read::cpu1.inst 17 # Instruction read bandwidth from this memory (bytes/s) 371system.realview.nvmem.bw_inst_read::total 24 # Instruction read bandwidth from this memory (bytes/s) 372system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) 373system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s) 374system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s) 375system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 376system.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 377system.bridge.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 378system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 379system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 380system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 381system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 382system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 383system.cf0.dma_write_txs 631 # Number of DMA write transactions. 384system.cpu_clk_domain.clock 500 # Clock period in ticks 385system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 386system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 387system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 388system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 389system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 390system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 391system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 392system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 393system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 394system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 395system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 396system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 397system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 398system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 399system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 400system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 401system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 402system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 403system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 404system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 405system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 406system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 407system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 408system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 409system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 410system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 411system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 412system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 413system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 414system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 415system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 416system.cpu0.dtb.walker.walks 7799 # Table walker walks requested 417system.cpu0.dtb.walker.walksShort 7799 # Table walker walks initiated with short descriptors 418system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1450 # Level at which table walker walks with short descriptors terminate 419system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6349 # Level at which table walker walks with short descriptors terminate 420system.cpu0.dtb.walker.walkWaitTime::samples 7799 # Table walker wait (enqueue to first request) latency 421system.cpu0.dtb.walker.walkWaitTime::0 7799 100.00% 100.00% # Table walker wait (enqueue to first request) latency 422system.cpu0.dtb.walker.walkWaitTime::total 7799 # Table walker wait (enqueue to first request) latency 423system.cpu0.dtb.walker.walkCompletionTime::samples 6405 # Table walker service (enqueue to completion) latency 424system.cpu0.dtb.walker.walkCompletionTime::mean 12453.161593 # Table walker service (enqueue to completion) latency 425system.cpu0.dtb.walker.walkCompletionTime::gmean 11389.819011 # Table walker service (enqueue to completion) latency 426system.cpu0.dtb.walker.walkCompletionTime::stdev 6523.003169 # Table walker service (enqueue to completion) latency 427system.cpu0.dtb.walker.walkCompletionTime::0-16383 5861 91.51% 91.51% # Table walker service (enqueue to completion) latency 428system.cpu0.dtb.walker.walkCompletionTime::16384-32767 469 7.32% 98.83% # Table walker service (enqueue to completion) latency 429system.cpu0.dtb.walker.walkCompletionTime::32768-49151 66 1.03% 99.86% # Table walker service (enqueue to completion) latency 430system.cpu0.dtb.walker.walkCompletionTime::49152-65535 4 0.06% 99.92% # Table walker service (enqueue to completion) latency 431system.cpu0.dtb.walker.walkCompletionTime::98304-114687 3 0.05% 99.97% # Table walker service (enqueue to completion) latency 432system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.02% 99.98% # Table walker service (enqueue to completion) latency 433system.cpu0.dtb.walker.walkCompletionTime::212992-229375 1 0.02% 100.00% # Table walker service (enqueue to completion) latency 434system.cpu0.dtb.walker.walkCompletionTime::total 6405 # Table walker service (enqueue to completion) latency 435system.cpu0.dtb.walker.walksPending::samples 1181300000 # Table walker pending requests distribution 436system.cpu0.dtb.walker.walksPending::0 1181300000 100.00% 100.00% # Table walker pending requests distribution 437system.cpu0.dtb.walker.walksPending::total 1181300000 # Table walker pending requests distribution 438system.cpu0.dtb.walker.walkPageSizes::4K 4994 77.97% 77.97% # Table walker page sizes translated 439system.cpu0.dtb.walker.walkPageSizes::1M 1411 22.03% 100.00% # Table walker page sizes translated 440system.cpu0.dtb.walker.walkPageSizes::total 6405 # Table walker page sizes translated 441system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7799 # Table walker requests started/completed, data/inst 442system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 443system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7799 # Table walker requests started/completed, data/inst 444system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6405 # Table walker requests started/completed, data/inst 445system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 446system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6405 # Table walker requests started/completed, data/inst 447system.cpu0.dtb.walker.walkRequestOrigin::total 14204 # Table walker requests started/completed, data/inst 448system.cpu0.dtb.inst_hits 0 # ITB inst hits 449system.cpu0.dtb.inst_misses 0 # ITB inst misses 450system.cpu0.dtb.read_hits 25116933 # DTB read hits 451system.cpu0.dtb.read_misses 6669 # DTB read misses 452system.cpu0.dtb.write_hits 18718433 # DTB write hits 453system.cpu0.dtb.write_misses 1130 # DTB write misses 454system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 455system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 456system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 457system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 458system.cpu0.dtb.flush_entries 3389 # Number of entries that have been flushed from TLB 459system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 460system.cpu0.dtb.prefetch_faults 1753 # Number of TLB faults due to prefetch 461system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 462system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions 463system.cpu0.dtb.read_accesses 25123602 # DTB read accesses 464system.cpu0.dtb.write_accesses 18719563 # DTB write accesses 465system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 466system.cpu0.dtb.hits 43835366 # DTB hits 467system.cpu0.dtb.misses 7799 # DTB misses 468system.cpu0.dtb.accesses 43843165 # DTB accesses 469system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 470system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 471system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 472system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 473system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 474system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 475system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 476system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 477system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 478system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 479system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 480system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 481system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 482system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 483system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 484system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 485system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 486system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 487system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 488system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 489system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 490system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 491system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 492system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 493system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 494system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 495system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 496system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 497system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 498system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 499system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 500system.cpu0.itb.walker.walks 3348 # Table walker walks requested 501system.cpu0.itb.walker.walksShort 3348 # Table walker walks initiated with short descriptors 502system.cpu0.itb.walker.walksShortTerminationLevel::Level1 299 # Level at which table walker walks with short descriptors terminate 503system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3049 # Level at which table walker walks with short descriptors terminate 504system.cpu0.itb.walker.walkWaitTime::samples 3348 # Table walker wait (enqueue to first request) latency 505system.cpu0.itb.walker.walkWaitTime::0 3348 100.00% 100.00% # Table walker wait (enqueue to first request) latency 506system.cpu0.itb.walker.walkWaitTime::total 3348 # Table walker wait (enqueue to first request) latency 507system.cpu0.itb.walker.walkCompletionTime::samples 2332 # Table walker service (enqueue to completion) latency 508system.cpu0.itb.walker.walkCompletionTime::mean 12654.159520 # Table walker service (enqueue to completion) latency 509system.cpu0.itb.walker.walkCompletionTime::gmean 11787.335553 # Table walker service (enqueue to completion) latency 510system.cpu0.itb.walker.walkCompletionTime::stdev 5848.484815 # Table walker service (enqueue to completion) latency 511system.cpu0.itb.walker.walkCompletionTime::0-8191 389 16.68% 16.68% # Table walker service (enqueue to completion) latency 512system.cpu0.itb.walker.walkCompletionTime::8192-16383 1671 71.66% 88.34% # Table walker service (enqueue to completion) latency 513system.cpu0.itb.walker.walkCompletionTime::16384-24575 217 9.31% 97.64% # Table walker service (enqueue to completion) latency 514system.cpu0.itb.walker.walkCompletionTime::24576-32767 27 1.16% 98.80% # Table walker service (enqueue to completion) latency 515system.cpu0.itb.walker.walkCompletionTime::32768-40959 21 0.90% 99.70% # Table walker service (enqueue to completion) latency 516system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.74% # Table walker service (enqueue to completion) latency 517system.cpu0.itb.walker.walkCompletionTime::49152-57343 3 0.13% 99.87% # Table walker service (enqueue to completion) latency 518system.cpu0.itb.walker.walkCompletionTime::57344-65535 1 0.04% 99.91% # Table walker service (enqueue to completion) latency 519system.cpu0.itb.walker.walkCompletionTime::98304-106495 1 0.04% 99.96% # Table walker service (enqueue to completion) latency 520system.cpu0.itb.walker.walkCompletionTime::122880-131071 1 0.04% 100.00% # Table walker service (enqueue to completion) latency 521system.cpu0.itb.walker.walkCompletionTime::total 2332 # Table walker service (enqueue to completion) latency 522system.cpu0.itb.walker.walksPending::samples 1180899500 # Table walker pending requests distribution 523system.cpu0.itb.walker.walksPending::0 1180899500 100.00% 100.00% # Table walker pending requests distribution 524system.cpu0.itb.walker.walksPending::total 1180899500 # Table walker pending requests distribution 525system.cpu0.itb.walker.walkPageSizes::4K 2033 87.18% 87.18% # Table walker page sizes translated 526system.cpu0.itb.walker.walkPageSizes::1M 299 12.82% 100.00% # Table walker page sizes translated 527system.cpu0.itb.walker.walkPageSizes::total 2332 # Table walker page sizes translated 528system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 529system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3348 # Table walker requests started/completed, data/inst 530system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3348 # Table walker requests started/completed, data/inst 531system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 532system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2332 # Table walker requests started/completed, data/inst 533system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2332 # Table walker requests started/completed, data/inst 534system.cpu0.itb.walker.walkRequestOrigin::total 5680 # Table walker requests started/completed, data/inst 535system.cpu0.itb.inst_hits 118797664 # ITB inst hits 536system.cpu0.itb.inst_misses 3348 # ITB inst misses 537system.cpu0.itb.read_hits 0 # DTB read hits 538system.cpu0.itb.read_misses 0 # DTB read misses 539system.cpu0.itb.write_hits 0 # DTB write hits 540system.cpu0.itb.write_misses 0 # DTB write misses 541system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 542system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 543system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 544system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 545system.cpu0.itb.flush_entries 2086 # Number of entries that have been flushed from TLB 546system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 547system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 548system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 549system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 550system.cpu0.itb.read_accesses 0 # DTB read accesses 551system.cpu0.itb.write_accesses 0 # DTB write accesses 552system.cpu0.itb.inst_accesses 118801012 # ITB inst accesses 553system.cpu0.itb.hits 118797664 # DTB hits 554system.cpu0.itb.misses 3348 # DTB misses 555system.cpu0.itb.accesses 118801012 # DTB accesses 556system.cpu0.numPwrStateTransitions 3664 # Number of power state transitions 557system.cpu0.pwrStateClkGateDist::samples 1832 # Distribution of time spent in the clock gated state 558system.cpu0.pwrStateClkGateDist::mean 1490824715.864083 # Distribution of time spent in the clock gated state 559system.cpu0.pwrStateClkGateDist::stdev 23921725256.931263 # Distribution of time spent in the clock gated state 560system.cpu0.pwrStateClkGateDist::underflows 1059 57.81% 57.81% # Distribution of time spent in the clock gated state 561system.cpu0.pwrStateClkGateDist::1000-5e+10 768 41.92% 99.73% # Distribution of time spent in the clock gated state 562system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.78% # Distribution of time spent in the clock gated state 563system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.22% 100.00% # Distribution of time spent in the clock gated state 564system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 565system.cpu0.pwrStateClkGateDist::max_value 499964287288 # Distribution of time spent in the clock gated state 566system.cpu0.pwrStateClkGateDist::total 1832 # Distribution of time spent in the clock gated state 567system.cpu0.pwrStateResidencyTicks::ON 139798047037 # Cumulative time (in ticks) in various power states 568system.cpu0.pwrStateResidencyTicks::CLK_GATED 2731190879463 # Cumulative time (in ticks) in various power states 569system.cpu0.numCycles 5741977853 # number of cpu cycles simulated 570system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 571system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 572system.cpu0.kern.inst.arm 0 # number of arm instructions executed 573system.cpu0.kern.inst.quiesce 1832 # number of quiesce instructions executed 574system.cpu0.committedInsts 115134358 # Number of instructions committed 575system.cpu0.committedOps 139131175 # Number of ops (including micro ops) committed 576system.cpu0.num_int_alu_accesses 123155389 # Number of integer alu accesses 577system.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses 578system.cpu0.num_func_calls 12669084 # number of times a function call or return occured 579system.cpu0.num_conditional_control_insts 15658471 # number of instructions that are conditional controls 580system.cpu0.num_int_insts 123155389 # number of integer instructions 581system.cpu0.num_fp_insts 9755 # number of float instructions 582system.cpu0.num_int_register_reads 226724524 # number of times the integer registers were read 583system.cpu0.num_int_register_writes 85578914 # number of times the integer registers were written 584system.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read 585system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written 586system.cpu0.num_cc_register_reads 504070716 # number of times the CC registers were read 587system.cpu0.num_cc_register_writes 52161373 # number of times the CC registers were written 588system.cpu0.num_mem_refs 44970744 # number of memory refs 589system.cpu0.num_load_insts 25368600 # Number of load instructions 590system.cpu0.num_store_insts 19602144 # Number of store instructions 591system.cpu0.num_idle_cycles 5462381758.924097 # Number of idle cycles 592system.cpu0.num_busy_cycles 279596094.075903 # Number of busy cycles 593system.cpu0.not_idle_fraction 0.048693 # Percentage of non-idle cycles 594system.cpu0.idle_fraction 0.951307 # Percentage of idle cycles 595system.cpu0.Branches 29063879 # Number of branches fetched 596system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction 597system.cpu0.op_class::IntAlu 97803517 68.44% 68.45% # Class of executed instruction 598system.cpu0.op_class::IntMult 109759 0.08% 68.52% # Class of executed instruction 599system.cpu0.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction 600system.cpu0.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction 601system.cpu0.op_class::FloatCmp 0 0.00% 68.52% # Class of executed instruction 602system.cpu0.op_class::FloatCvt 0 0.00% 68.52% # Class of executed instruction 603system.cpu0.op_class::FloatMult 0 0.00% 68.52% # Class of executed instruction 604system.cpu0.op_class::FloatMultAcc 0 0.00% 68.52% # Class of executed instruction 605system.cpu0.op_class::FloatDiv 0 0.00% 68.52% # Class of executed instruction 606system.cpu0.op_class::FloatMisc 0 0.00% 68.52% # Class of executed instruction 607system.cpu0.op_class::FloatSqrt 0 0.00% 68.52% # Class of executed instruction 608system.cpu0.op_class::SimdAdd 0 0.00% 68.52% # Class of executed instruction 609system.cpu0.op_class::SimdAddAcc 0 0.00% 68.52% # Class of executed instruction 610system.cpu0.op_class::SimdAlu 0 0.00% 68.52% # Class of executed instruction 611system.cpu0.op_class::SimdCmp 0 0.00% 68.52% # Class of executed instruction 612system.cpu0.op_class::SimdCvt 0 0.00% 68.52% # Class of executed instruction 613system.cpu0.op_class::SimdMisc 0 0.00% 68.52% # Class of executed instruction 614system.cpu0.op_class::SimdMult 0 0.00% 68.52% # Class of executed instruction 615system.cpu0.op_class::SimdMultAcc 0 0.00% 68.52% # Class of executed instruction 616system.cpu0.op_class::SimdShift 0 0.00% 68.52% # Class of executed instruction 617system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.52% # Class of executed instruction 618system.cpu0.op_class::SimdSqrt 0 0.00% 68.52% # Class of executed instruction 619system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.52% # Class of executed instruction 620system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.52% # Class of executed instruction 621system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.52% # Class of executed instruction 622system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.52% # Class of executed instruction 623system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.52% # Class of executed instruction 624system.cpu0.op_class::SimdFloatMisc 8141 0.01% 68.53% # Class of executed instruction 625system.cpu0.op_class::SimdFloatMult 0 0.00% 68.53% # Class of executed instruction 626system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.53% # Class of executed instruction 627system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.53% # Class of executed instruction 628system.cpu0.op_class::MemRead 25366344 17.75% 86.28% # Class of executed instruction 629system.cpu0.op_class::MemWrite 19594649 13.71% 99.99% # Class of executed instruction 630system.cpu0.op_class::FloatMemRead 2256 0.00% 99.99% # Class of executed instruction 631system.cpu0.op_class::FloatMemWrite 7495 0.01% 100.00% # Class of executed instruction 632system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 633system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 634system.cpu0.op_class::total 142894434 # Class of executed instruction 635system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 636system.cpu0.dcache.tags.replacements 691910 # number of replacements 637system.cpu0.dcache.tags.tagsinuse 491.841324 # Cycle average of tags in use 638system.cpu0.dcache.tags.total_refs 42965158 # Total number of references to valid blocks. 639system.cpu0.dcache.tags.sampled_refs 692422 # Sample count of references to valid blocks. 640system.cpu0.dcache.tags.avg_refs 62.050539 # Average number of references to valid blocks. 641system.cpu0.dcache.tags.warmup_cycle 1207348000 # Cycle when the warmup percentage was hit. 642system.cpu0.dcache.tags.occ_blocks::cpu0.data 491.841324 # Average occupied blocks per requestor 643system.cpu0.dcache.tags.occ_percent::cpu0.data 0.960628 # Average percentage of cache occupancy 644system.cpu0.dcache.tags.occ_percent::total 0.960628 # Average percentage of cache occupancy 645system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 646system.cpu0.dcache.tags.age_task_id_blocks_1024::0 115 # Occupied blocks per task id 647system.cpu0.dcache.tags.age_task_id_blocks_1024::1 286 # Occupied blocks per task id 648system.cpu0.dcache.tags.age_task_id_blocks_1024::2 111 # Occupied blocks per task id 649system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 650system.cpu0.dcache.tags.tag_accesses 88306903 # Number of tag accesses 651system.cpu0.dcache.tags.data_accesses 88306903 # Number of data accesses 652system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 653system.cpu0.dcache.ReadReq_hits::cpu0.data 23857214 # number of ReadReq hits 654system.cpu0.dcache.ReadReq_hits::total 23857214 # number of ReadReq hits 655system.cpu0.dcache.WriteReq_hits::cpu0.data 17987587 # number of WriteReq hits 656system.cpu0.dcache.WriteReq_hits::total 17987587 # number of WriteReq hits 657system.cpu0.dcache.SoftPFReq_hits::cpu0.data 319351 # number of SoftPFReq hits 658system.cpu0.dcache.SoftPFReq_hits::total 319351 # number of SoftPFReq hits 659system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 364951 # number of LoadLockedReq hits 660system.cpu0.dcache.LoadLockedReq_hits::total 364951 # number of LoadLockedReq hits 661system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361858 # number of StoreCondReq hits 662system.cpu0.dcache.StoreCondReq_hits::total 361858 # number of StoreCondReq hits 663system.cpu0.dcache.demand_hits::cpu0.data 41844801 # number of demand (read+write) hits 664system.cpu0.dcache.demand_hits::total 41844801 # number of demand (read+write) hits 665system.cpu0.dcache.overall_hits::cpu0.data 42164152 # number of overall hits 666system.cpu0.dcache.overall_hits::total 42164152 # number of overall hits 667system.cpu0.dcache.ReadReq_misses::cpu0.data 395864 # number of ReadReq misses 668system.cpu0.dcache.ReadReq_misses::total 395864 # number of ReadReq misses 669system.cpu0.dcache.WriteReq_misses::cpu0.data 325028 # number of WriteReq misses 670system.cpu0.dcache.WriteReq_misses::total 325028 # number of WriteReq misses 671system.cpu0.dcache.SoftPFReq_misses::cpu0.data 126936 # number of SoftPFReq misses 672system.cpu0.dcache.SoftPFReq_misses::total 126936 # number of SoftPFReq misses 673system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21386 # number of LoadLockedReq misses 674system.cpu0.dcache.LoadLockedReq_misses::total 21386 # number of LoadLockedReq misses 675system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19587 # number of StoreCondReq misses 676system.cpu0.dcache.StoreCondReq_misses::total 19587 # number of StoreCondReq misses 677system.cpu0.dcache.demand_misses::cpu0.data 720892 # number of demand (read+write) misses 678system.cpu0.dcache.demand_misses::total 720892 # number of demand (read+write) misses 679system.cpu0.dcache.overall_misses::cpu0.data 847828 # number of overall misses 680system.cpu0.dcache.overall_misses::total 847828 # number of overall misses 681system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5519668500 # number of ReadReq miss cycles 682system.cpu0.dcache.ReadReq_miss_latency::total 5519668500 # number of ReadReq miss cycles 683system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6305983500 # number of WriteReq miss cycles 684system.cpu0.dcache.WriteReq_miss_latency::total 6305983500 # number of WriteReq miss cycles 685system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 336140000 # number of LoadLockedReq miss cycles 686system.cpu0.dcache.LoadLockedReq_miss_latency::total 336140000 # number of LoadLockedReq miss cycles 687system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 459598500 # number of StoreCondReq miss cycles 688system.cpu0.dcache.StoreCondReq_miss_latency::total 459598500 # number of StoreCondReq miss cycles 689system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1175500 # number of StoreCondFailReq miss cycles 690system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1175500 # number of StoreCondFailReq miss cycles 691system.cpu0.dcache.demand_miss_latency::cpu0.data 11825652000 # number of demand (read+write) miss cycles 692system.cpu0.dcache.demand_miss_latency::total 11825652000 # number of demand (read+write) miss cycles 693system.cpu0.dcache.overall_miss_latency::cpu0.data 11825652000 # number of overall miss cycles 694system.cpu0.dcache.overall_miss_latency::total 11825652000 # number of overall miss cycles 695system.cpu0.dcache.ReadReq_accesses::cpu0.data 24253078 # number of ReadReq accesses(hits+misses) 696system.cpu0.dcache.ReadReq_accesses::total 24253078 # number of ReadReq accesses(hits+misses) 697system.cpu0.dcache.WriteReq_accesses::cpu0.data 18312615 # number of WriteReq accesses(hits+misses) 698system.cpu0.dcache.WriteReq_accesses::total 18312615 # number of WriteReq accesses(hits+misses) 699system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446287 # number of SoftPFReq accesses(hits+misses) 700system.cpu0.dcache.SoftPFReq_accesses::total 446287 # number of SoftPFReq accesses(hits+misses) 701system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386337 # number of LoadLockedReq accesses(hits+misses) 702system.cpu0.dcache.LoadLockedReq_accesses::total 386337 # number of LoadLockedReq accesses(hits+misses) 703system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381445 # number of StoreCondReq accesses(hits+misses) 704system.cpu0.dcache.StoreCondReq_accesses::total 381445 # number of StoreCondReq accesses(hits+misses) 705system.cpu0.dcache.demand_accesses::cpu0.data 42565693 # number of demand (read+write) accesses 706system.cpu0.dcache.demand_accesses::total 42565693 # number of demand (read+write) accesses 707system.cpu0.dcache.overall_accesses::cpu0.data 43011980 # number of overall (read+write) accesses 708system.cpu0.dcache.overall_accesses::total 43011980 # number of overall (read+write) accesses 709system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016322 # miss rate for ReadReq accesses 710system.cpu0.dcache.ReadReq_miss_rate::total 0.016322 # miss rate for ReadReq accesses 711system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017749 # miss rate for WriteReq accesses 712system.cpu0.dcache.WriteReq_miss_rate::total 0.017749 # miss rate for WriteReq accesses 713system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.284427 # miss rate for SoftPFReq accesses 714system.cpu0.dcache.SoftPFReq_miss_rate::total 0.284427 # miss rate for SoftPFReq accesses 715system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055356 # miss rate for LoadLockedReq accesses 716system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055356 # miss rate for LoadLockedReq accesses 717system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051349 # miss rate for StoreCondReq accesses 718system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051349 # miss rate for StoreCondReq accesses 719system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016936 # miss rate for demand accesses 720system.cpu0.dcache.demand_miss_rate::total 0.016936 # miss rate for demand accesses 721system.cpu0.dcache.overall_miss_rate::cpu0.data 0.019711 # miss rate for overall accesses 722system.cpu0.dcache.overall_miss_rate::total 0.019711 # miss rate for overall accesses 723system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13943.345442 # average ReadReq miss latency 724system.cpu0.dcache.ReadReq_avg_miss_latency::total 13943.345442 # average ReadReq miss latency 725system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19401.354653 # average WriteReq miss latency 726system.cpu0.dcache.WriteReq_avg_miss_latency::total 19401.354653 # average WriteReq miss latency 727system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15717.759282 # average LoadLockedReq miss latency 728system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15717.759282 # average LoadLockedReq miss latency 729system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23464.466228 # average StoreCondReq miss latency 730system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23464.466228 # average StoreCondReq miss latency 731system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 732system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 733system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16404.193693 # average overall miss latency 734system.cpu0.dcache.demand_avg_miss_latency::total 16404.193693 # average overall miss latency 735system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13948.173450 # average overall miss latency 736system.cpu0.dcache.overall_avg_miss_latency::total 13948.173450 # average overall miss latency 737system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 738system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 739system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 740system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 741system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 742system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 743system.cpu0.dcache.writebacks::writebacks 691910 # number of writebacks 744system.cpu0.dcache.writebacks::total 691910 # number of writebacks 745system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25218 # number of ReadReq MSHR hits 746system.cpu0.dcache.ReadReq_mshr_hits::total 25218 # number of ReadReq MSHR hits 747system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1 # number of WriteReq MSHR hits 748system.cpu0.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits 749system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15019 # number of LoadLockedReq MSHR hits 750system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15019 # number of LoadLockedReq MSHR hits 751system.cpu0.dcache.demand_mshr_hits::cpu0.data 25219 # number of demand (read+write) MSHR hits 752system.cpu0.dcache.demand_mshr_hits::total 25219 # number of demand (read+write) MSHR hits 753system.cpu0.dcache.overall_mshr_hits::cpu0.data 25219 # number of overall MSHR hits 754system.cpu0.dcache.overall_mshr_hits::total 25219 # number of overall MSHR hits 755system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 370646 # number of ReadReq MSHR misses 756system.cpu0.dcache.ReadReq_mshr_misses::total 370646 # number of ReadReq MSHR misses 757system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 325027 # number of WriteReq MSHR misses 758system.cpu0.dcache.WriteReq_mshr_misses::total 325027 # number of WriteReq MSHR misses 759system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 99914 # number of SoftPFReq MSHR misses 760system.cpu0.dcache.SoftPFReq_mshr_misses::total 99914 # number of SoftPFReq MSHR misses 761system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6367 # number of LoadLockedReq MSHR misses 762system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6367 # number of LoadLockedReq MSHR misses 763system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19587 # number of StoreCondReq MSHR misses 764system.cpu0.dcache.StoreCondReq_mshr_misses::total 19587 # number of StoreCondReq MSHR misses 765system.cpu0.dcache.demand_mshr_misses::cpu0.data 695673 # number of demand (read+write) MSHR misses 766system.cpu0.dcache.demand_mshr_misses::total 695673 # number of demand (read+write) MSHR misses 767system.cpu0.dcache.overall_mshr_misses::cpu0.data 795587 # number of overall MSHR misses 768system.cpu0.dcache.overall_mshr_misses::total 795587 # number of overall MSHR misses 769system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31782 # number of ReadReq MSHR uncacheable 770system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31782 # number of ReadReq MSHR uncacheable 771system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28454 # number of WriteReq MSHR uncacheable 772system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28454 # number of WriteReq MSHR uncacheable 773system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60236 # number of overall MSHR uncacheable misses 774system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60236 # number of overall MSHR uncacheable misses 775system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4741194000 # number of ReadReq MSHR miss cycles 776system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4741194000 # number of ReadReq MSHR miss cycles 777system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5980473000 # number of WriteReq MSHR miss cycles 778system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5980473000 # number of WriteReq MSHR miss cycles 779system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1654728000 # number of SoftPFReq MSHR miss cycles 780system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1654728000 # number of SoftPFReq MSHR miss cycles 781system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 97962000 # number of LoadLockedReq MSHR miss cycles 782system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 97962000 # number of LoadLockedReq MSHR miss cycles 783system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 440045500 # number of StoreCondReq MSHR miss cycles 784system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 440045500 # number of StoreCondReq MSHR miss cycles 785system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1141500 # number of StoreCondFailReq MSHR miss cycles 786system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1141500 # number of StoreCondFailReq MSHR miss cycles 787system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10721667000 # number of demand (read+write) MSHR miss cycles 788system.cpu0.dcache.demand_mshr_miss_latency::total 10721667000 # number of demand (read+write) MSHR miss cycles 789system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12376395000 # number of overall MSHR miss cycles 790system.cpu0.dcache.overall_mshr_miss_latency::total 12376395000 # number of overall MSHR miss cycles 791system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6631909500 # number of ReadReq MSHR uncacheable cycles 792system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6631909500 # number of ReadReq MSHR uncacheable cycles 793system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6631909500 # number of overall MSHR uncacheable cycles 794system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6631909500 # number of overall MSHR uncacheable cycles 795system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015282 # mshr miss rate for ReadReq accesses 796system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015282 # mshr miss rate for ReadReq accesses 797system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017749 # mshr miss rate for WriteReq accesses 798system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017749 # mshr miss rate for WriteReq accesses 799system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.223878 # mshr miss rate for SoftPFReq accesses 800system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.223878 # mshr miss rate for SoftPFReq accesses 801system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016480 # mshr miss rate for LoadLockedReq accesses 802system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016480 # mshr miss rate for LoadLockedReq accesses 803system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051349 # mshr miss rate for StoreCondReq accesses 804system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051349 # mshr miss rate for StoreCondReq accesses 805system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016344 # mshr miss rate for demand accesses 806system.cpu0.dcache.demand_mshr_miss_rate::total 0.016344 # mshr miss rate for demand accesses 807system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018497 # mshr miss rate for overall accesses 808system.cpu0.dcache.overall_mshr_miss_rate::total 0.018497 # mshr miss rate for overall accesses 809system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12791.704214 # average ReadReq mshr miss latency 810system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12791.704214 # average ReadReq mshr miss latency 811system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18399.926775 # average WriteReq mshr miss latency 812system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18399.926775 # average WriteReq mshr miss latency 813system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16561.522910 # average SoftPFReq mshr miss latency 814system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16561.522910 # average SoftPFReq mshr miss latency 815system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15385.896026 # average LoadLockedReq mshr miss latency 816system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15385.896026 # average LoadLockedReq mshr miss latency 817system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22466.202073 # average StoreCondReq mshr miss latency 818system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22466.202073 # average StoreCondReq mshr miss latency 819system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 820system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 821system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15411.934918 # average overall mshr miss latency 822system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15411.934918 # average overall mshr miss latency 823system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15556.306224 # average overall mshr miss latency 824system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15556.306224 # average overall mshr miss latency 825system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208668.727582 # average ReadReq mshr uncacheable latency 826system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208668.727582 # average ReadReq mshr uncacheable latency 827system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 110098.769839 # average overall mshr uncacheable latency 828system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 110098.769839 # average overall mshr uncacheable latency 829system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 830system.cpu0.icache.tags.replacements 1101405 # number of replacements 831system.cpu0.icache.tags.tagsinuse 511.436911 # Cycle average of tags in use 832system.cpu0.icache.tags.total_refs 117695738 # Total number of references to valid blocks. 833system.cpu0.icache.tags.sampled_refs 1101917 # Sample count of references to valid blocks. 834system.cpu0.icache.tags.avg_refs 106.809985 # Average number of references to valid blocks. 835system.cpu0.icache.tags.warmup_cycle 14178985000 # Cycle when the warmup percentage was hit. 836system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.436911 # Average occupied blocks per requestor 837system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998900 # Average percentage of cache occupancy 838system.cpu0.icache.tags.occ_percent::total 0.998900 # Average percentage of cache occupancy 839system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 840system.cpu0.icache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id 841system.cpu0.icache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id 842system.cpu0.icache.tags.age_task_id_blocks_1024::2 215 # Occupied blocks per task id 843system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 844system.cpu0.icache.tags.tag_accesses 238697254 # Number of tag accesses 845system.cpu0.icache.tags.data_accesses 238697254 # Number of data accesses 846system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 847system.cpu0.icache.ReadReq_hits::cpu0.inst 117695738 # number of ReadReq hits 848system.cpu0.icache.ReadReq_hits::total 117695738 # number of ReadReq hits 849system.cpu0.icache.demand_hits::cpu0.inst 117695738 # number of demand (read+write) hits 850system.cpu0.icache.demand_hits::total 117695738 # number of demand (read+write) hits 851system.cpu0.icache.overall_hits::cpu0.inst 117695738 # number of overall hits 852system.cpu0.icache.overall_hits::total 117695738 # number of overall hits 853system.cpu0.icache.ReadReq_misses::cpu0.inst 1101926 # number of ReadReq misses 854system.cpu0.icache.ReadReq_misses::total 1101926 # number of ReadReq misses 855system.cpu0.icache.demand_misses::cpu0.inst 1101926 # number of demand (read+write) misses 856system.cpu0.icache.demand_misses::total 1101926 # number of demand (read+write) misses 857system.cpu0.icache.overall_misses::cpu0.inst 1101926 # number of overall misses 858system.cpu0.icache.overall_misses::total 1101926 # number of overall misses 859system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11884591500 # number of ReadReq miss cycles 860system.cpu0.icache.ReadReq_miss_latency::total 11884591500 # number of ReadReq miss cycles 861system.cpu0.icache.demand_miss_latency::cpu0.inst 11884591500 # number of demand (read+write) miss cycles 862system.cpu0.icache.demand_miss_latency::total 11884591500 # number of demand (read+write) miss cycles 863system.cpu0.icache.overall_miss_latency::cpu0.inst 11884591500 # number of overall miss cycles 864system.cpu0.icache.overall_miss_latency::total 11884591500 # number of overall miss cycles 865system.cpu0.icache.ReadReq_accesses::cpu0.inst 118797664 # number of ReadReq accesses(hits+misses) 866system.cpu0.icache.ReadReq_accesses::total 118797664 # number of ReadReq accesses(hits+misses) 867system.cpu0.icache.demand_accesses::cpu0.inst 118797664 # number of demand (read+write) accesses 868system.cpu0.icache.demand_accesses::total 118797664 # number of demand (read+write) accesses 869system.cpu0.icache.overall_accesses::cpu0.inst 118797664 # number of overall (read+write) accesses 870system.cpu0.icache.overall_accesses::total 118797664 # number of overall (read+write) accesses 871system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009276 # miss rate for ReadReq accesses 872system.cpu0.icache.ReadReq_miss_rate::total 0.009276 # miss rate for ReadReq accesses 873system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009276 # miss rate for demand accesses 874system.cpu0.icache.demand_miss_rate::total 0.009276 # miss rate for demand accesses 875system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009276 # miss rate for overall accesses 876system.cpu0.icache.overall_miss_rate::total 0.009276 # miss rate for overall accesses 877system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10785.290029 # average ReadReq miss latency 878system.cpu0.icache.ReadReq_avg_miss_latency::total 10785.290029 # average ReadReq miss latency 879system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10785.290029 # average overall miss latency 880system.cpu0.icache.demand_avg_miss_latency::total 10785.290029 # average overall miss latency 881system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10785.290029 # average overall miss latency 882system.cpu0.icache.overall_avg_miss_latency::total 10785.290029 # average overall miss latency 883system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 884system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 885system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 886system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 887system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 888system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 889system.cpu0.icache.writebacks::writebacks 1101405 # number of writebacks 890system.cpu0.icache.writebacks::total 1101405 # number of writebacks 891system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1101926 # number of ReadReq MSHR misses 892system.cpu0.icache.ReadReq_mshr_misses::total 1101926 # number of ReadReq MSHR misses 893system.cpu0.icache.demand_mshr_misses::cpu0.inst 1101926 # number of demand (read+write) MSHR misses 894system.cpu0.icache.demand_mshr_misses::total 1101926 # number of demand (read+write) MSHR misses 895system.cpu0.icache.overall_mshr_misses::cpu0.inst 1101926 # number of overall MSHR misses 896system.cpu0.icache.overall_mshr_misses::total 1101926 # number of overall MSHR misses 897system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable 898system.cpu0.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable 899system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses 900system.cpu0.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses 901system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11333628500 # number of ReadReq MSHR miss cycles 902system.cpu0.icache.ReadReq_mshr_miss_latency::total 11333628500 # number of ReadReq MSHR miss cycles 903system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11333628500 # number of demand (read+write) MSHR miss cycles 904system.cpu0.icache.demand_mshr_miss_latency::total 11333628500 # number of demand (read+write) MSHR miss cycles 905system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11333628500 # number of overall MSHR miss cycles 906system.cpu0.icache.overall_mshr_miss_latency::total 11333628500 # number of overall MSHR miss cycles 907system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 863305500 # number of ReadReq MSHR uncacheable cycles 908system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 863305500 # number of ReadReq MSHR uncacheable cycles 909system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 863305500 # number of overall MSHR uncacheable cycles 910system.cpu0.icache.overall_mshr_uncacheable_latency::total 863305500 # number of overall MSHR uncacheable cycles 911system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009276 # mshr miss rate for ReadReq accesses 912system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009276 # mshr miss rate for ReadReq accesses 913system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009276 # mshr miss rate for demand accesses 914system.cpu0.icache.demand_mshr_miss_rate::total 0.009276 # mshr miss rate for demand accesses 915system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009276 # mshr miss rate for overall accesses 916system.cpu0.icache.overall_mshr_miss_rate::total 0.009276 # mshr miss rate for overall accesses 917system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10285.290029 # average ReadReq mshr miss latency 918system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10285.290029 # average ReadReq mshr miss latency 919system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10285.290029 # average overall mshr miss latency 920system.cpu0.icache.demand_avg_mshr_miss_latency::total 10285.290029 # average overall mshr miss latency 921system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10285.290029 # average overall mshr miss latency 922system.cpu0.icache.overall_avg_mshr_miss_latency::total 10285.290029 # average overall mshr miss latency 923system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 95688.927067 # average ReadReq mshr uncacheable latency 924system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 95688.927067 # average ReadReq mshr uncacheable latency 925system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 95688.927067 # average overall mshr uncacheable latency 926system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 95688.927067 # average overall mshr uncacheable latency 927system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 928system.cpu0.l2cache.prefetcher.num_hwpf_issued 1842335 # number of hwpf issued 929system.cpu0.l2cache.prefetcher.pfIdentified 1842343 # number of prefetch candidates identified 930system.cpu0.l2cache.prefetcher.pfBufferHit 7 # number of redundant prefetches already in prefetch queue 931system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 932system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 933system.cpu0.l2cache.prefetcher.pfSpanPage 236049 # number of prefetches not generated due to page crossing 934system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 935system.cpu0.l2cache.tags.replacements 259510 # number of replacements 936system.cpu0.l2cache.tags.tagsinuse 15639.759609 # Cycle average of tags in use 937system.cpu0.l2cache.tags.total_refs 1683263 # Total number of references to valid blocks. 938system.cpu0.l2cache.tags.sampled_refs 275158 # Sample count of references to valid blocks. 939system.cpu0.l2cache.tags.avg_refs 6.117442 # Average number of references to valid blocks. 940system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 941system.cpu0.l2cache.tags.occ_blocks::writebacks 14465.018905 # Average occupied blocks per requestor 942system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 1.607944 # Average occupied blocks per requestor 943system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.119153 # Average occupied blocks per requestor 944system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1173.013607 # Average occupied blocks per requestor 945system.cpu0.l2cache.tags.occ_percent::writebacks 0.882875 # Average percentage of cache occupancy 946system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000098 # Average percentage of cache occupancy 947system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000007 # Average percentage of cache occupancy 948system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.071595 # Average percentage of cache occupancy 949system.cpu0.l2cache.tags.occ_percent::total 0.954575 # Average percentage of cache occupancy 950system.cpu0.l2cache.tags.occ_task_id_blocks::1022 297 # Occupied blocks per task id 951system.cpu0.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id 952system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15346 # Occupied blocks per task id 953system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 6 # Occupied blocks per task id 954system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 36 # Occupied blocks per task id 955system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 136 # Occupied blocks per task id 956system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 119 # Occupied blocks per task id 957system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id 958system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 959system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id 960system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 196 # Occupied blocks per task id 961system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 812 # Occupied blocks per task id 962system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 6067 # Occupied blocks per task id 963system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6453 # Occupied blocks per task id 964system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1818 # Occupied blocks per task id 965system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.018127 # Percentage of cache occupancy per task id 966system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000305 # Percentage of cache occupancy per task id 967system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.936646 # Percentage of cache occupancy per task id 968system.cpu0.l2cache.tags.tag_accesses 61207036 # Number of tag accesses 969system.cpu0.l2cache.tags.data_accesses 61207036 # Number of data accesses 970system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 971system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 9838 # number of ReadReq hits 972system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4464 # number of ReadReq hits 973system.cpu0.l2cache.ReadReq_hits::total 14302 # number of ReadReq hits 974system.cpu0.l2cache.WritebackDirty_hits::writebacks 475527 # number of WritebackDirty hits 975system.cpu0.l2cache.WritebackDirty_hits::total 475527 # number of WritebackDirty hits 976system.cpu0.l2cache.WritebackClean_hits::writebacks 1289984 # number of WritebackClean hits 977system.cpu0.l2cache.WritebackClean_hits::total 1289984 # number of WritebackClean hits 978system.cpu0.l2cache.ReadExReq_hits::cpu0.data 227136 # number of ReadExReq hits 979system.cpu0.l2cache.ReadExReq_hits::total 227136 # number of ReadExReq hits 980system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1039867 # number of ReadCleanReq hits 981system.cpu0.l2cache.ReadCleanReq_hits::total 1039867 # number of ReadCleanReq hits 982system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 376033 # number of ReadSharedReq hits 983system.cpu0.l2cache.ReadSharedReq_hits::total 376033 # number of ReadSharedReq hits 984system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 9838 # number of demand (read+write) hits 985system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4464 # number of demand (read+write) hits 986system.cpu0.l2cache.demand_hits::cpu0.inst 1039867 # number of demand (read+write) hits 987system.cpu0.l2cache.demand_hits::cpu0.data 603169 # number of demand (read+write) hits 988system.cpu0.l2cache.demand_hits::total 1657338 # number of demand (read+write) hits 989system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 9838 # number of overall hits 990system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4464 # number of overall hits 991system.cpu0.l2cache.overall_hits::cpu0.inst 1039867 # number of overall hits 992system.cpu0.l2cache.overall_hits::cpu0.data 603169 # number of overall hits 993system.cpu0.l2cache.overall_hits::total 1657338 # number of overall hits 994system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 303 # number of ReadReq misses 995system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 138 # number of ReadReq misses 996system.cpu0.l2cache.ReadReq_misses::total 441 # number of ReadReq misses 997system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 54610 # number of UpgradeReq misses 998system.cpu0.l2cache.UpgradeReq_misses::total 54610 # number of UpgradeReq misses 999system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19582 # number of SCUpgradeReq misses 1000system.cpu0.l2cache.SCUpgradeReq_misses::total 19582 # number of SCUpgradeReq misses 1001system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 5 # number of SCUpgradeFailReq misses 1002system.cpu0.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses 1003system.cpu0.l2cache.ReadExReq_misses::cpu0.data 43281 # number of ReadExReq misses 1004system.cpu0.l2cache.ReadExReq_misses::total 43281 # number of ReadExReq misses 1005system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 62059 # number of ReadCleanReq misses 1006system.cpu0.l2cache.ReadCleanReq_misses::total 62059 # number of ReadCleanReq misses 1007system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 100894 # number of ReadSharedReq misses 1008system.cpu0.l2cache.ReadSharedReq_misses::total 100894 # number of ReadSharedReq misses 1009system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 303 # number of demand (read+write) misses 1010system.cpu0.l2cache.demand_misses::cpu0.itb.walker 138 # number of demand (read+write) misses 1011system.cpu0.l2cache.demand_misses::cpu0.inst 62059 # number of demand (read+write) misses 1012system.cpu0.l2cache.demand_misses::cpu0.data 144175 # number of demand (read+write) misses 1013system.cpu0.l2cache.demand_misses::total 206675 # number of demand (read+write) misses 1014system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 303 # number of overall misses 1015system.cpu0.l2cache.overall_misses::cpu0.itb.walker 138 # number of overall misses 1016system.cpu0.l2cache.overall_misses::cpu0.inst 62059 # number of overall misses 1017system.cpu0.l2cache.overall_misses::cpu0.data 144175 # number of overall misses 1018system.cpu0.l2cache.overall_misses::total 206675 # number of overall misses 1019system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 8179000 # number of ReadReq miss cycles 1020system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3277000 # number of ReadReq miss cycles 1021system.cpu0.l2cache.ReadReq_miss_latency::total 11456000 # number of ReadReq miss cycles 1022system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 32137500 # number of UpgradeReq miss cycles 1023system.cpu0.l2cache.UpgradeReq_miss_latency::total 32137500 # number of UpgradeReq miss cycles 1024system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 8911500 # number of SCUpgradeReq miss cycles 1025system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 8911500 # number of SCUpgradeReq miss cycles 1026system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1089999 # number of SCUpgradeFailReq miss cycles 1027system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1089999 # number of SCUpgradeFailReq miss cycles 1028system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2751603000 # number of ReadExReq miss cycles 1029system.cpu0.l2cache.ReadExReq_miss_latency::total 2751603000 # number of ReadExReq miss cycles 1030system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 3417541500 # number of ReadCleanReq miss cycles 1031system.cpu0.l2cache.ReadCleanReq_miss_latency::total 3417541500 # number of ReadCleanReq miss cycles 1032system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3327393000 # number of ReadSharedReq miss cycles 1033system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3327393000 # number of ReadSharedReq miss cycles 1034system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 8179000 # number of demand (read+write) miss cycles 1035system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3277000 # number of demand (read+write) miss cycles 1036system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3417541500 # number of demand (read+write) miss cycles 1037system.cpu0.l2cache.demand_miss_latency::cpu0.data 6078996000 # number of demand (read+write) miss cycles 1038system.cpu0.l2cache.demand_miss_latency::total 9507993500 # number of demand (read+write) miss cycles 1039system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 8179000 # number of overall miss cycles 1040system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3277000 # number of overall miss cycles 1041system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3417541500 # number of overall miss cycles 1042system.cpu0.l2cache.overall_miss_latency::cpu0.data 6078996000 # number of overall miss cycles 1043system.cpu0.l2cache.overall_miss_latency::total 9507993500 # number of overall miss cycles 1044system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 10141 # number of ReadReq accesses(hits+misses) 1045system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4602 # number of ReadReq accesses(hits+misses) 1046system.cpu0.l2cache.ReadReq_accesses::total 14743 # number of ReadReq accesses(hits+misses) 1047system.cpu0.l2cache.WritebackDirty_accesses::writebacks 475527 # number of WritebackDirty accesses(hits+misses) 1048system.cpu0.l2cache.WritebackDirty_accesses::total 475527 # number of WritebackDirty accesses(hits+misses) 1049system.cpu0.l2cache.WritebackClean_accesses::writebacks 1289984 # number of WritebackClean accesses(hits+misses) 1050system.cpu0.l2cache.WritebackClean_accesses::total 1289984 # number of WritebackClean accesses(hits+misses) 1051system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 54610 # number of UpgradeReq accesses(hits+misses) 1052system.cpu0.l2cache.UpgradeReq_accesses::total 54610 # number of UpgradeReq accesses(hits+misses) 1053system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 19582 # number of SCUpgradeReq accesses(hits+misses) 1054system.cpu0.l2cache.SCUpgradeReq_accesses::total 19582 # number of SCUpgradeReq accesses(hits+misses) 1055system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 5 # number of SCUpgradeFailReq accesses(hits+misses) 1056system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses) 1057system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 270417 # number of ReadExReq accesses(hits+misses) 1058system.cpu0.l2cache.ReadExReq_accesses::total 270417 # number of ReadExReq accesses(hits+misses) 1059system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1101926 # number of ReadCleanReq accesses(hits+misses) 1060system.cpu0.l2cache.ReadCleanReq_accesses::total 1101926 # number of ReadCleanReq accesses(hits+misses) 1061system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 476927 # number of ReadSharedReq accesses(hits+misses) 1062system.cpu0.l2cache.ReadSharedReq_accesses::total 476927 # number of ReadSharedReq accesses(hits+misses) 1063system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 10141 # number of demand (read+write) accesses 1064system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4602 # number of demand (read+write) accesses 1065system.cpu0.l2cache.demand_accesses::cpu0.inst 1101926 # number of demand (read+write) accesses 1066system.cpu0.l2cache.demand_accesses::cpu0.data 747344 # number of demand (read+write) accesses 1067system.cpu0.l2cache.demand_accesses::total 1864013 # number of demand (read+write) accesses 1068system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 10141 # number of overall (read+write) accesses 1069system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4602 # number of overall (read+write) accesses 1070system.cpu0.l2cache.overall_accesses::cpu0.inst 1101926 # number of overall (read+write) accesses 1071system.cpu0.l2cache.overall_accesses::cpu0.data 747344 # number of overall (read+write) accesses 1072system.cpu0.l2cache.overall_accesses::total 1864013 # number of overall (read+write) accesses 1073system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.029879 # miss rate for ReadReq accesses 1074system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.029987 # miss rate for ReadReq accesses 1075system.cpu0.l2cache.ReadReq_miss_rate::total 0.029913 # miss rate for ReadReq accesses 1076system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses 1077system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 1078system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 1079system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1080system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1081system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1082system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.160053 # miss rate for ReadExReq accesses 1083system.cpu0.l2cache.ReadExReq_miss_rate::total 0.160053 # miss rate for ReadExReq accesses 1084system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.056319 # miss rate for ReadCleanReq accesses 1085system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.056319 # miss rate for ReadCleanReq accesses 1086system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.211550 # miss rate for ReadSharedReq accesses 1087system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.211550 # miss rate for ReadSharedReq accesses 1088system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.029879 # miss rate for demand accesses 1089system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.029987 # miss rate for demand accesses 1090system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.056319 # miss rate for demand accesses 1091system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.192917 # miss rate for demand accesses 1092system.cpu0.l2cache.demand_miss_rate::total 0.110876 # miss rate for demand accesses 1093system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.029879 # miss rate for overall accesses 1094system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.029987 # miss rate for overall accesses 1095system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.056319 # miss rate for overall accesses 1096system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.192917 # miss rate for overall accesses 1097system.cpu0.l2cache.overall_miss_rate::total 0.110876 # miss rate for overall accesses 1098system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 26993.399340 # average ReadReq miss latency 1099system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23746.376812 # average ReadReq miss latency 1100system.cpu0.l2cache.ReadReq_avg_miss_latency::total 25977.324263 # average ReadReq miss latency 1101system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 588.491119 # average UpgradeReq miss latency 1102system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 588.491119 # average UpgradeReq miss latency 1103system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 455.086304 # average SCUpgradeReq miss latency 1104system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 455.086304 # average SCUpgradeReq miss latency 1105system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 217999.800000 # average SCUpgradeFailReq miss latency 1106system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 217999.800000 # average SCUpgradeFailReq miss latency 1107system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 63575.310182 # average ReadExReq miss latency 1108system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 63575.310182 # average ReadExReq miss latency 1109system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 55069.232505 # average ReadCleanReq miss latency 1110system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 55069.232505 # average ReadCleanReq miss latency 1111system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 32979.096874 # average ReadSharedReq miss latency 1112system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 32979.096874 # average ReadSharedReq miss latency 1113system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 26993.399340 # average overall miss latency 1114system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23746.376812 # average overall miss latency 1115system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 55069.232505 # average overall miss latency 1116system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 42164.009017 # average overall miss latency 1117system.cpu0.l2cache.demand_avg_miss_latency::total 46004.565139 # average overall miss latency 1118system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 26993.399340 # average overall miss latency 1119system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23746.376812 # average overall miss latency 1120system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 55069.232505 # average overall miss latency 1121system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 42164.009017 # average overall miss latency 1122system.cpu0.l2cache.overall_avg_miss_latency::total 46004.565139 # average overall miss latency 1123system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1124system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1125system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1126system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1127system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1128system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1129system.cpu0.l2cache.unused_prefetches 10584 # number of HardPF blocks evicted w/o reference 1130system.cpu0.l2cache.writebacks::writebacks 226675 # number of writebacks 1131system.cpu0.l2cache.writebacks::total 226675 # number of writebacks 1132system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1590 # number of ReadExReq MSHR hits 1133system.cpu0.l2cache.ReadExReq_mshr_hits::total 1590 # number of ReadExReq MSHR hits 1134system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 30 # number of ReadSharedReq MSHR hits 1135system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 30 # number of ReadSharedReq MSHR hits 1136system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1620 # number of demand (read+write) MSHR hits 1137system.cpu0.l2cache.demand_mshr_hits::total 1620 # number of demand (read+write) MSHR hits 1138system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1620 # number of overall MSHR hits 1139system.cpu0.l2cache.overall_mshr_hits::total 1620 # number of overall MSHR hits 1140system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 303 # number of ReadReq MSHR misses 1141system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 138 # number of ReadReq MSHR misses 1142system.cpu0.l2cache.ReadReq_mshr_misses::total 441 # number of ReadReq MSHR misses 1143system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 262593 # number of HardPFReq MSHR misses 1144system.cpu0.l2cache.HardPFReq_mshr_misses::total 262593 # number of HardPFReq MSHR misses 1145system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 54610 # number of UpgradeReq MSHR misses 1146system.cpu0.l2cache.UpgradeReq_mshr_misses::total 54610 # number of UpgradeReq MSHR misses 1147system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19582 # number of SCUpgradeReq MSHR misses 1148system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19582 # number of SCUpgradeReq MSHR misses 1149system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 5 # number of SCUpgradeFailReq MSHR misses 1150system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses 1151system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41691 # number of ReadExReq MSHR misses 1152system.cpu0.l2cache.ReadExReq_mshr_misses::total 41691 # number of ReadExReq MSHR misses 1153system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 62059 # number of ReadCleanReq MSHR misses 1154system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 62059 # number of ReadCleanReq MSHR misses 1155system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 100864 # number of ReadSharedReq MSHR misses 1156system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 100864 # number of ReadSharedReq MSHR misses 1157system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 303 # number of demand (read+write) MSHR misses 1158system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 138 # number of demand (read+write) MSHR misses 1159system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 62059 # number of demand (read+write) MSHR misses 1160system.cpu0.l2cache.demand_mshr_misses::cpu0.data 142555 # number of demand (read+write) MSHR misses 1161system.cpu0.l2cache.demand_mshr_misses::total 205055 # number of demand (read+write) MSHR misses 1162system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 303 # number of overall MSHR misses 1163system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 138 # number of overall MSHR misses 1164system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 62059 # number of overall MSHR misses 1165system.cpu0.l2cache.overall_mshr_misses::cpu0.data 142555 # number of overall MSHR misses 1166system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 262593 # number of overall MSHR misses 1167system.cpu0.l2cache.overall_mshr_misses::total 467648 # number of overall MSHR misses 1168system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable 1169system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31782 # number of ReadReq MSHR uncacheable 1170system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 40804 # number of ReadReq MSHR uncacheable 1171system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28454 # number of WriteReq MSHR uncacheable 1172system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28454 # number of WriteReq MSHR uncacheable 1173system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses 1174system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60236 # number of overall MSHR uncacheable misses 1175system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 69258 # number of overall MSHR uncacheable misses 1176system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 6361000 # number of ReadReq MSHR miss cycles 1177system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2449000 # number of ReadReq MSHR miss cycles 1178system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 8810000 # number of ReadReq MSHR miss cycles 1179system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 16813897141 # number of HardPFReq MSHR miss cycles 1180system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 16813897141 # number of HardPFReq MSHR miss cycles 1181system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 934853500 # number of UpgradeReq MSHR miss cycles 1182system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 934853500 # number of UpgradeReq MSHR miss cycles 1183system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 293341500 # number of SCUpgradeReq MSHR miss cycles 1184system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 293341500 # number of SCUpgradeReq MSHR miss cycles 1185system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 885999 # number of SCUpgradeFailReq MSHR miss cycles 1186system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 885999 # number of SCUpgradeFailReq MSHR miss cycles 1187system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2209696500 # number of ReadExReq MSHR miss cycles 1188system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2209696500 # number of ReadExReq MSHR miss cycles 1189system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 3045187500 # number of ReadCleanReq MSHR miss cycles 1190system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 3045187500 # number of ReadCleanReq MSHR miss cycles 1191system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2716829000 # number of ReadSharedReq MSHR miss cycles 1192system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2716829000 # number of ReadSharedReq MSHR miss cycles 1193system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 6361000 # number of demand (read+write) MSHR miss cycles 1194system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2449000 # number of demand (read+write) MSHR miss cycles 1195system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3045187500 # number of demand (read+write) MSHR miss cycles 1196system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 4926525500 # number of demand (read+write) MSHR miss cycles 1197system.cpu0.l2cache.demand_mshr_miss_latency::total 7980523000 # number of demand (read+write) MSHR miss cycles 1198system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 6361000 # number of overall MSHR miss cycles 1199system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2449000 # number of overall MSHR miss cycles 1200system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3045187500 # number of overall MSHR miss cycles 1201system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 4926525500 # number of overall MSHR miss cycles 1202system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 16813897141 # number of overall MSHR miss cycles 1203system.cpu0.l2cache.overall_mshr_miss_latency::total 24794420141 # number of overall MSHR miss cycles 1204system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 795640500 # number of ReadReq MSHR uncacheable cycles 1205system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6377241500 # number of ReadReq MSHR uncacheable cycles 1206system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7172882000 # number of ReadReq MSHR uncacheable cycles 1207system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 795640500 # number of overall MSHR uncacheable cycles 1208system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6377241500 # number of overall MSHR uncacheable cycles 1209system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7172882000 # number of overall MSHR uncacheable cycles 1210system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.029879 # mshr miss rate for ReadReq accesses 1211system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.029987 # mshr miss rate for ReadReq accesses 1212system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.029913 # mshr miss rate for ReadReq accesses 1213system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1214system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1215system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses 1216system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 1217system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses 1218system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1219system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1220system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1221system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.154173 # mshr miss rate for ReadExReq accesses 1222system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.154173 # mshr miss rate for ReadExReq accesses 1223system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.056319 # mshr miss rate for ReadCleanReq accesses 1224system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.056319 # mshr miss rate for ReadCleanReq accesses 1225system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.211487 # mshr miss rate for ReadSharedReq accesses 1226system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.211487 # mshr miss rate for ReadSharedReq accesses 1227system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.029879 # mshr miss rate for demand accesses 1228system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.029987 # mshr miss rate for demand accesses 1229system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.056319 # mshr miss rate for demand accesses 1230system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.190749 # mshr miss rate for demand accesses 1231system.cpu0.l2cache.demand_mshr_miss_rate::total 0.110007 # mshr miss rate for demand accesses 1232system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.029879 # mshr miss rate for overall accesses 1233system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.029987 # mshr miss rate for overall accesses 1234system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.056319 # mshr miss rate for overall accesses 1235system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.190749 # mshr miss rate for overall accesses 1236system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1237system.cpu0.l2cache.overall_mshr_miss_rate::total 0.250882 # mshr miss rate for overall accesses 1238system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 20993.399340 # average ReadReq mshr miss latency 1239system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17746.376812 # average ReadReq mshr miss latency 1240system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 19977.324263 # average ReadReq mshr miss latency 1241system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 64030.256484 # average HardPFReq mshr miss latency 1242system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 64030.256484 # average HardPFReq mshr miss latency 1243system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17118.723677 # average UpgradeReq mshr miss latency 1244system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17118.723677 # average UpgradeReq mshr miss latency 1245system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14980.160351 # average SCUpgradeReq mshr miss latency 1246system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14980.160351 # average SCUpgradeReq mshr miss latency 1247system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 177199.800000 # average SCUpgradeFailReq mshr miss latency 1248system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 177199.800000 # average SCUpgradeFailReq mshr miss latency 1249system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 53001.762970 # average ReadExReq mshr miss latency 1250system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 53001.762970 # average ReadExReq mshr miss latency 1251system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 49069.232505 # average ReadCleanReq mshr miss latency 1252system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49069.232505 # average ReadCleanReq mshr miss latency 1253system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26935.566704 # average ReadSharedReq mshr miss latency 1254system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26935.566704 # average ReadSharedReq mshr miss latency 1255system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 20993.399340 # average overall mshr miss latency 1256system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17746.376812 # average overall mshr miss latency 1257system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 49069.232505 # average overall mshr miss latency 1258system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 34558.770299 # average overall mshr miss latency 1259system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 38918.938821 # average overall mshr miss latency 1260system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 20993.399340 # average overall mshr miss latency 1261system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17746.376812 # average overall mshr miss latency 1262system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 49069.232505 # average overall mshr miss latency 1263system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 34558.770299 # average overall mshr miss latency 1264system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 64030.256484 # average overall mshr miss latency 1265system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 53019.408061 # average overall mshr miss latency 1266system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88188.927067 # average ReadReq mshr uncacheable latency 1267system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200655.764269 # average ReadReq mshr uncacheable latency 1268system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 175788.697187 # average ReadReq mshr uncacheable latency 1269system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88188.927067 # average overall mshr uncacheable latency 1270system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105870.932665 # average overall mshr uncacheable latency 1271system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 103567.558982 # average overall mshr uncacheable latency 1272system.cpu0.toL2Bus.snoop_filter.tot_requests 3728751 # Total number of requests made to the snoop filter. 1273system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1879521 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1274system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27804 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1275system.cpu0.toL2Bus.snoop_filter.tot_snoops 211480 # Total number of snoops made to the snoop filter. 1276system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 209803 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1277system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 1677 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1278system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 1279system.cpu0.toL2Bus.trans_dist::ReadReq 61377 # Transaction distribution 1280system.cpu0.toL2Bus.trans_dist::ReadResp 1688185 # Transaction distribution 1281system.cpu0.toL2Bus.trans_dist::WriteReq 28454 # Transaction distribution 1282system.cpu0.toL2Bus.trans_dist::WriteResp 28454 # Transaction distribution 1283system.cpu0.toL2Bus.trans_dist::WritebackDirty 702444 # Transaction distribution 1284system.cpu0.toL2Bus.trans_dist::WritebackClean 1317788 # Transaction distribution 1285system.cpu0.toL2Bus.trans_dist::CleanEvict 79827 # Transaction distribution 1286system.cpu0.toL2Bus.trans_dist::HardPFReq 309039 # Transaction distribution 1287system.cpu0.toL2Bus.trans_dist::UpgradeReq 86996 # Transaction distribution 1288system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 41768 # Transaction distribution 1289system.cpu0.toL2Bus.trans_dist::UpgradeResp 111544 # Transaction distribution 1290system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 48 # Transaction distribution 1291system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 77 # Transaction distribution 1292system.cpu0.toL2Bus.trans_dist::ReadExReq 289661 # Transaction distribution 1293system.cpu0.toL2Bus.trans_dist::ReadExResp 286091 # Transaction distribution 1294system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1101926 # Transaction distribution 1295system.cpu0.toL2Bus.trans_dist::ReadSharedReq 562800 # Transaction distribution 1296system.cpu0.toL2Bus.trans_dist::InvalidateReq 3273 # Transaction distribution 1297system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3323301 # Packet count per connected master and slave (bytes) 1298system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2556545 # Packet count per connected master and slave (bytes) 1299system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10999 # Packet count per connected master and slave (bytes) 1300system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 24289 # Packet count per connected master and slave (bytes) 1301system.cpu0.toL2Bus.pkt_count::total 5915134 # Packet count per connected master and slave (bytes) 1302system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 141049272 # Cumulative packet size per connected master and slave (bytes) 1303system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 96382808 # Cumulative packet size per connected master and slave (bytes) 1304system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 18408 # Cumulative packet size per connected master and slave (bytes) 1305system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 40564 # Cumulative packet size per connected master and slave (bytes) 1306system.cpu0.toL2Bus.pkt_size::total 237491052 # Cumulative packet size per connected master and slave (bytes) 1307system.cpu0.toL2Bus.snoops 885699 # Total snoops (count) 1308system.cpu0.toL2Bus.snoopTraffic 18622452 # Total snoop traffic (bytes) 1309system.cpu0.toL2Bus.snoop_fanout::samples 2792086 # Request fanout histogram 1310system.cpu0.toL2Bus.snoop_fanout::mean 0.090598 # Request fanout histogram 1311system.cpu0.toL2Bus.snoop_fanout::stdev 0.289121 # Request fanout histogram 1312system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1313system.cpu0.toL2Bus.snoop_fanout::0 2540806 91.00% 91.00% # Request fanout histogram 1314system.cpu0.toL2Bus.snoop_fanout::1 249603 8.94% 99.94% # Request fanout histogram 1315system.cpu0.toL2Bus.snoop_fanout::2 1677 0.06% 100.00% # Request fanout histogram 1316system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1317system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1318system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1319system.cpu0.toL2Bus.snoop_fanout::total 2792086 # Request fanout histogram 1320system.cpu0.toL2Bus.reqLayer0.occupancy 3710834999 # Layer occupancy (ticks) 1321system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1322system.cpu0.toL2Bus.snoopLayer0.occupancy 114296030 # Layer occupancy (ticks) 1323system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1324system.cpu0.toL2Bus.respLayer0.occupancy 1661911000 # Layer occupancy (ticks) 1325system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1326system.cpu0.toL2Bus.respLayer1.occupancy 1204165985 # Layer occupancy (ticks) 1327system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1328system.cpu0.toL2Bus.respLayer2.occupancy 6397000 # Layer occupancy (ticks) 1329system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1330system.cpu0.toL2Bus.respLayer3.occupancy 14154986 # Layer occupancy (ticks) 1331system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1332system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 1333system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1334system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1335system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1336system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1337system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1338system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1339system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1340system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1341system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1342system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1343system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1344system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1345system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1346system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1347system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1348system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1349system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1350system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1351system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1352system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1353system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1354system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1355system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1356system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1357system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1358system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1359system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1360system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1361system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1362system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 1363system.cpu1.dtb.walker.walks 3359 # Table walker walks requested 1364system.cpu1.dtb.walker.walksShort 3359 # Table walker walks initiated with short descriptors 1365system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 669 # Level at which table walker walks with short descriptors terminate 1366system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2690 # Level at which table walker walks with short descriptors terminate 1367system.cpu1.dtb.walker.walkWaitTime::samples 3359 # Table walker wait (enqueue to first request) latency 1368system.cpu1.dtb.walker.walkWaitTime::0 3359 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1369system.cpu1.dtb.walker.walkWaitTime::total 3359 # Table walker wait (enqueue to first request) latency 1370system.cpu1.dtb.walker.walkCompletionTime::samples 2589 # Table walker service (enqueue to completion) latency 1371system.cpu1.dtb.walker.walkCompletionTime::mean 12693.897258 # Table walker service (enqueue to completion) latency 1372system.cpu1.dtb.walker.walkCompletionTime::gmean 11812.728196 # Table walker service (enqueue to completion) latency 1373system.cpu1.dtb.walker.walkCompletionTime::stdev 5453.033399 # Table walker service (enqueue to completion) latency 1374system.cpu1.dtb.walker.walkCompletionTime::0-4095 2 0.08% 0.08% # Table walker service (enqueue to completion) latency 1375system.cpu1.dtb.walker.walkCompletionTime::4096-8191 579 22.36% 22.44% # Table walker service (enqueue to completion) latency 1376system.cpu1.dtb.walker.walkCompletionTime::8192-12287 1101 42.53% 64.97% # Table walker service (enqueue to completion) latency 1377system.cpu1.dtb.walker.walkCompletionTime::12288-16383 577 22.29% 87.25% # Table walker service (enqueue to completion) latency 1378system.cpu1.dtb.walker.walkCompletionTime::16384-20479 84 3.24% 90.50% # Table walker service (enqueue to completion) latency 1379system.cpu1.dtb.walker.walkCompletionTime::20480-24575 148 5.72% 96.21% # Table walker service (enqueue to completion) latency 1380system.cpu1.dtb.walker.walkCompletionTime::24576-28671 49 1.89% 98.11% # Table walker service (enqueue to completion) latency 1381system.cpu1.dtb.walker.walkCompletionTime::28672-32767 18 0.70% 98.80% # Table walker service (enqueue to completion) latency 1382system.cpu1.dtb.walker.walkCompletionTime::32768-36863 23 0.89% 99.69% # Table walker service (enqueue to completion) latency 1383system.cpu1.dtb.walker.walkCompletionTime::36864-40959 2 0.08% 99.77% # Table walker service (enqueue to completion) latency 1384system.cpu1.dtb.walker.walkCompletionTime::40960-45055 4 0.15% 99.92% # Table walker service (enqueue to completion) latency 1385system.cpu1.dtb.walker.walkCompletionTime::49152-53247 1 0.04% 99.96% # Table walker service (enqueue to completion) latency 1386system.cpu1.dtb.walker.walkCompletionTime::57344-61439 1 0.04% 100.00% # Table walker service (enqueue to completion) latency 1387system.cpu1.dtb.walker.walkCompletionTime::total 2589 # Table walker service (enqueue to completion) latency 1388system.cpu1.dtb.walker.walksPending::samples -1937787828 # Table walker pending requests distribution 1389system.cpu1.dtb.walker.walksPending::0 -1937787828 100.00% 100.00% # Table walker pending requests distribution 1390system.cpu1.dtb.walker.walksPending::total -1937787828 # Table walker pending requests distribution 1391system.cpu1.dtb.walker.walkPageSizes::4K 1928 74.47% 74.47% # Table walker page sizes translated 1392system.cpu1.dtb.walker.walkPageSizes::1M 661 25.53% 100.00% # Table walker page sizes translated 1393system.cpu1.dtb.walker.walkPageSizes::total 2589 # Table walker page sizes translated 1394system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3359 # Table walker requests started/completed, data/inst 1395system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1396system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3359 # Table walker requests started/completed, data/inst 1397system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2589 # Table walker requests started/completed, data/inst 1398system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1399system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2589 # Table walker requests started/completed, data/inst 1400system.cpu1.dtb.walker.walkRequestOrigin::total 5948 # Table walker requests started/completed, data/inst 1401system.cpu1.dtb.inst_hits 0 # ITB inst hits 1402system.cpu1.dtb.inst_misses 0 # ITB inst misses 1403system.cpu1.dtb.read_hits 3975776 # DTB read hits 1404system.cpu1.dtb.read_misses 2856 # DTB read misses 1405system.cpu1.dtb.write_hits 3446428 # DTB write hits 1406system.cpu1.dtb.write_misses 503 # DTB write misses 1407system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1408system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1409system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1410system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1411system.cpu1.dtb.flush_entries 1973 # Number of entries that have been flushed from TLB 1412system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 1413system.cpu1.dtb.prefetch_faults 329 # Number of TLB faults due to prefetch 1414system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1415system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions 1416system.cpu1.dtb.read_accesses 3978632 # DTB read accesses 1417system.cpu1.dtb.write_accesses 3446931 # DTB write accesses 1418system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1419system.cpu1.dtb.hits 7422204 # DTB hits 1420system.cpu1.dtb.misses 3359 # DTB misses 1421system.cpu1.dtb.accesses 7425563 # DTB accesses 1422system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 1423system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1424system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1425system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1426system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1427system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1428system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1429system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1430system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1431system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1432system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1433system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1434system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1435system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1436system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1437system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1438system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1439system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1440system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1441system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1442system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1443system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1444system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1445system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1446system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1447system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1448system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1449system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1450system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1451system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1452system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 1453system.cpu1.itb.walker.walks 1746 # Table walker walks requested 1454system.cpu1.itb.walker.walksShort 1746 # Table walker walks initiated with short descriptors 1455system.cpu1.itb.walker.walksShortTerminationLevel::Level1 168 # Level at which table walker walks with short descriptors terminate 1456system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1578 # Level at which table walker walks with short descriptors terminate 1457system.cpu1.itb.walker.walkWaitTime::samples 1746 # Table walker wait (enqueue to first request) latency 1458system.cpu1.itb.walker.walkWaitTime::0 1746 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1459system.cpu1.itb.walker.walkWaitTime::total 1746 # Table walker wait (enqueue to first request) latency 1460system.cpu1.itb.walker.walkCompletionTime::samples 1107 # Table walker service (enqueue to completion) latency 1461system.cpu1.itb.walker.walkCompletionTime::mean 13066.847335 # Table walker service (enqueue to completion) latency 1462system.cpu1.itb.walker.walkCompletionTime::gmean 12198.452511 # Table walker service (enqueue to completion) latency 1463system.cpu1.itb.walker.walkCompletionTime::stdev 5775.216215 # Table walker service (enqueue to completion) latency 1464system.cpu1.itb.walker.walkCompletionTime::4096-8191 143 12.92% 12.92% # Table walker service (enqueue to completion) latency 1465system.cpu1.itb.walker.walkCompletionTime::8192-12287 638 57.63% 70.55% # Table walker service (enqueue to completion) latency 1466system.cpu1.itb.walker.walkCompletionTime::12288-16383 167 15.09% 85.64% # Table walker service (enqueue to completion) latency 1467system.cpu1.itb.walker.walkCompletionTime::16384-20479 51 4.61% 90.24% # Table walker service (enqueue to completion) latency 1468system.cpu1.itb.walker.walkCompletionTime::20480-24575 51 4.61% 94.85% # Table walker service (enqueue to completion) latency 1469system.cpu1.itb.walker.walkCompletionTime::24576-28671 28 2.53% 97.38% # Table walker service (enqueue to completion) latency 1470system.cpu1.itb.walker.walkCompletionTime::28672-32767 17 1.54% 98.92% # Table walker service (enqueue to completion) latency 1471system.cpu1.itb.walker.walkCompletionTime::32768-36863 1 0.09% 99.01% # Table walker service (enqueue to completion) latency 1472system.cpu1.itb.walker.walkCompletionTime::36864-40959 5 0.45% 99.46% # Table walker service (enqueue to completion) latency 1473system.cpu1.itb.walker.walkCompletionTime::40960-45055 3 0.27% 99.73% # Table walker service (enqueue to completion) latency 1474system.cpu1.itb.walker.walkCompletionTime::49152-53247 3 0.27% 100.00% # Table walker service (enqueue to completion) latency 1475system.cpu1.itb.walker.walkCompletionTime::total 1107 # Table walker service (enqueue to completion) latency 1476system.cpu1.itb.walker.walksPending::samples -1938367828 # Table walker pending requests distribution 1477system.cpu1.itb.walker.walksPending::0 -1938367828 100.00% 100.00% # Table walker pending requests distribution 1478system.cpu1.itb.walker.walksPending::total -1938367828 # Table walker pending requests distribution 1479system.cpu1.itb.walker.walkPageSizes::4K 939 84.82% 84.82% # Table walker page sizes translated 1480system.cpu1.itb.walker.walkPageSizes::1M 168 15.18% 100.00% # Table walker page sizes translated 1481system.cpu1.itb.walker.walkPageSizes::total 1107 # Table walker page sizes translated 1482system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1483system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1746 # Table walker requests started/completed, data/inst 1484system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1746 # Table walker requests started/completed, data/inst 1485system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1486system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1107 # Table walker requests started/completed, data/inst 1487system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1107 # Table walker requests started/completed, data/inst 1488system.cpu1.itb.walker.walkRequestOrigin::total 2853 # Table walker requests started/completed, data/inst 1489system.cpu1.itb.inst_hits 16753470 # ITB inst hits 1490system.cpu1.itb.inst_misses 1746 # ITB inst misses 1491system.cpu1.itb.read_hits 0 # DTB read hits 1492system.cpu1.itb.read_misses 0 # DTB read misses 1493system.cpu1.itb.write_hits 0 # DTB write hits 1494system.cpu1.itb.write_misses 0 # DTB write misses 1495system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1496system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1497system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1498system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1499system.cpu1.itb.flush_entries 1084 # Number of entries that have been flushed from TLB 1500system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1501system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1502system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1503system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1504system.cpu1.itb.read_accesses 0 # DTB read accesses 1505system.cpu1.itb.write_accesses 0 # DTB write accesses 1506system.cpu1.itb.inst_accesses 16755216 # ITB inst accesses 1507system.cpu1.itb.hits 16753470 # DTB hits 1508system.cpu1.itb.misses 1746 # DTB misses 1509system.cpu1.itb.accesses 16755216 # DTB accesses 1510system.cpu1.numPwrStateTransitions 5461 # Number of power state transitions 1511system.cpu1.pwrStateClkGateDist::samples 2731 # Distribution of time spent in the clock gated state 1512system.cpu1.pwrStateClkGateDist::mean 1041523757.275357 # Distribution of time spent in the clock gated state 1513system.cpu1.pwrStateClkGateDist::stdev 25854556705.104488 # Distribution of time spent in the clock gated state 1514system.cpu1.pwrStateClkGateDist::underflows 1955 71.59% 71.59% # Distribution of time spent in the clock gated state 1515system.cpu1.pwrStateClkGateDist::1000-5e+10 770 28.19% 99.78% # Distribution of time spent in the clock gated state 1516system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.07% 99.85% # Distribution of time spent in the clock gated state 1517system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state 1518system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state 1519system.cpu1.pwrStateClkGateDist::8e+11-8.5e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state 1520system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.04% 100.00% # Distribution of time spent in the clock gated state 1521system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 1522system.cpu1.pwrStateClkGateDist::max_value 929980418584 # Distribution of time spent in the clock gated state 1523system.cpu1.pwrStateClkGateDist::total 2731 # Distribution of time spent in the clock gated state 1524system.cpu1.pwrStateResidencyTicks::ON 26587545381 # Cumulative time (in ticks) in various power states 1525system.cpu1.pwrStateResidencyTicks::CLK_GATED 2844401381119 # Cumulative time (in ticks) in various power states 1526system.cpu1.numCycles 5741033861 # number of cpu cycles simulated 1527system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1528system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1529system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1530system.cpu1.kern.inst.quiesce 2731 # number of quiesce instructions executed 1531system.cpu1.committedInsts 16397270 # Number of instructions committed 1532system.cpu1.committedOps 19964987 # Number of ops (including micro ops) committed 1533system.cpu1.num_int_alu_accesses 17986629 # Number of integer alu accesses 1534system.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses 1535system.cpu1.num_func_calls 1033857 # number of times a function call or return occured 1536system.cpu1.num_conditional_control_insts 1854028 # number of instructions that are conditional controls 1537system.cpu1.num_int_insts 17986629 # number of integer instructions 1538system.cpu1.num_fp_insts 1792 # number of float instructions 1539system.cpu1.num_int_register_reads 32622652 # number of times the integer registers were read 1540system.cpu1.num_int_register_writes 12608250 # number of times the integer registers were written 1541system.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read 1542system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written 1543system.cpu1.num_cc_register_reads 72946565 # number of times the CC registers were read 1544system.cpu1.num_cc_register_writes 6544066 # number of times the CC registers were written 1545system.cpu1.num_mem_refs 7656991 # number of memory refs 1546system.cpu1.num_load_insts 4087327 # Number of load instructions 1547system.cpu1.num_store_insts 3569664 # Number of store instructions 1548system.cpu1.num_idle_cycles 5687867512.323336 # Number of idle cycles 1549system.cpu1.num_busy_cycles 53166348.676665 # Number of busy cycles 1550system.cpu1.not_idle_fraction 0.009261 # Percentage of non-idle cycles 1551system.cpu1.idle_fraction 0.990739 # Percentage of idle cycles 1552system.cpu1.Branches 2968001 # Number of branches fetched 1553system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction 1554system.cpu1.op_class::IntAlu 12630695 62.17% 62.17% # Class of executed instruction 1555system.cpu1.op_class::IntMult 26529 0.13% 62.30% # Class of executed instruction 1556system.cpu1.op_class::IntDiv 0 0.00% 62.30% # Class of executed instruction 1557system.cpu1.op_class::FloatAdd 0 0.00% 62.30% # Class of executed instruction 1558system.cpu1.op_class::FloatCmp 0 0.00% 62.30% # Class of executed instruction 1559system.cpu1.op_class::FloatCvt 0 0.00% 62.30% # Class of executed instruction 1560system.cpu1.op_class::FloatMult 0 0.00% 62.30% # Class of executed instruction 1561system.cpu1.op_class::FloatMultAcc 0 0.00% 62.30% # Class of executed instruction 1562system.cpu1.op_class::FloatDiv 0 0.00% 62.30% # Class of executed instruction 1563system.cpu1.op_class::FloatMisc 0 0.00% 62.30% # Class of executed instruction 1564system.cpu1.op_class::FloatSqrt 0 0.00% 62.30% # Class of executed instruction 1565system.cpu1.op_class::SimdAdd 0 0.00% 62.30% # Class of executed instruction 1566system.cpu1.op_class::SimdAddAcc 0 0.00% 62.30% # Class of executed instruction 1567system.cpu1.op_class::SimdAlu 0 0.00% 62.30% # Class of executed instruction 1568system.cpu1.op_class::SimdCmp 0 0.00% 62.30% # Class of executed instruction 1569system.cpu1.op_class::SimdCvt 0 0.00% 62.30% # Class of executed instruction 1570system.cpu1.op_class::SimdMisc 0 0.00% 62.30% # Class of executed instruction 1571system.cpu1.op_class::SimdMult 0 0.00% 62.30% # Class of executed instruction 1572system.cpu1.op_class::SimdMultAcc 0 0.00% 62.30% # Class of executed instruction 1573system.cpu1.op_class::SimdShift 0 0.00% 62.30% # Class of executed instruction 1574system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.30% # Class of executed instruction 1575system.cpu1.op_class::SimdSqrt 0 0.00% 62.30% # Class of executed instruction 1576system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.30% # Class of executed instruction 1577system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.30% # Class of executed instruction 1578system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.30% # Class of executed instruction 1579system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.30% # Class of executed instruction 1580system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.30% # Class of executed instruction 1581system.cpu1.op_class::SimdFloatMisc 3311 0.02% 62.31% # Class of executed instruction 1582system.cpu1.op_class::SimdFloatMult 0 0.00% 62.31% # Class of executed instruction 1583system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.31% # Class of executed instruction 1584system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.31% # Class of executed instruction 1585system.cpu1.op_class::MemRead 4086811 20.11% 82.43% # Class of executed instruction 1586system.cpu1.op_class::MemWrite 3568388 17.56% 99.99% # Class of executed instruction 1587system.cpu1.op_class::FloatMemRead 516 0.00% 99.99% # Class of executed instruction 1588system.cpu1.op_class::FloatMemWrite 1276 0.01% 100.00% # Class of executed instruction 1589system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 1590system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 1591system.cpu1.op_class::total 20317592 # Class of executed instruction 1592system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 1593system.cpu1.dcache.tags.replacements 188214 # number of replacements 1594system.cpu1.dcache.tags.tagsinuse 469.650282 # Cycle average of tags in use 1595system.cpu1.dcache.tags.total_refs 7155880 # Total number of references to valid blocks. 1596system.cpu1.dcache.tags.sampled_refs 188578 # Sample count of references to valid blocks. 1597system.cpu1.dcache.tags.avg_refs 37.946526 # Average number of references to valid blocks. 1598system.cpu1.dcache.tags.warmup_cycle 105561245500 # Cycle when the warmup percentage was hit. 1599system.cpu1.dcache.tags.occ_blocks::cpu1.data 469.650282 # Average occupied blocks per requestor 1600system.cpu1.dcache.tags.occ_percent::cpu1.data 0.917286 # Average percentage of cache occupancy 1601system.cpu1.dcache.tags.occ_percent::total 0.917286 # Average percentage of cache occupancy 1602system.cpu1.dcache.tags.occ_task_id_blocks::1024 364 # Occupied blocks per task id 1603system.cpu1.dcache.tags.age_task_id_blocks_1024::2 343 # Occupied blocks per task id 1604system.cpu1.dcache.tags.age_task_id_blocks_1024::3 21 # Occupied blocks per task id 1605system.cpu1.dcache.tags.occ_task_id_percent::1024 0.710938 # Percentage of cache occupancy per task id 1606system.cpu1.dcache.tags.tag_accesses 15064679 # Number of tag accesses 1607system.cpu1.dcache.tags.data_accesses 15064679 # Number of data accesses 1608system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 1609system.cpu1.dcache.ReadReq_hits::cpu1.data 3662279 # number of ReadReq hits 1610system.cpu1.dcache.ReadReq_hits::total 3662279 # number of ReadReq hits 1611system.cpu1.dcache.WriteReq_hits::cpu1.data 3257080 # number of WriteReq hits 1612system.cpu1.dcache.WriteReq_hits::total 3257080 # number of WriteReq hits 1613system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49206 # number of SoftPFReq hits 1614system.cpu1.dcache.SoftPFReq_hits::total 49206 # number of SoftPFReq hits 1615system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 79332 # number of LoadLockedReq hits 1616system.cpu1.dcache.LoadLockedReq_hits::total 79332 # number of LoadLockedReq hits 1617system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71298 # number of StoreCondReq hits 1618system.cpu1.dcache.StoreCondReq_hits::total 71298 # number of StoreCondReq hits 1619system.cpu1.dcache.demand_hits::cpu1.data 6919359 # number of demand (read+write) hits 1620system.cpu1.dcache.demand_hits::total 6919359 # number of demand (read+write) hits 1621system.cpu1.dcache.overall_hits::cpu1.data 6968565 # number of overall hits 1622system.cpu1.dcache.overall_hits::total 6968565 # number of overall hits 1623system.cpu1.dcache.ReadReq_misses::cpu1.data 134376 # number of ReadReq misses 1624system.cpu1.dcache.ReadReq_misses::total 134376 # number of ReadReq misses 1625system.cpu1.dcache.WriteReq_misses::cpu1.data 92202 # number of WriteReq misses 1626system.cpu1.dcache.WriteReq_misses::total 92202 # number of WriteReq misses 1627system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30516 # number of SoftPFReq misses 1628system.cpu1.dcache.SoftPFReq_misses::total 30516 # number of SoftPFReq misses 1629system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17009 # number of LoadLockedReq misses 1630system.cpu1.dcache.LoadLockedReq_misses::total 17009 # number of LoadLockedReq misses 1631system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23197 # number of StoreCondReq misses 1632system.cpu1.dcache.StoreCondReq_misses::total 23197 # number of StoreCondReq misses 1633system.cpu1.dcache.demand_misses::cpu1.data 226578 # number of demand (read+write) misses 1634system.cpu1.dcache.demand_misses::total 226578 # number of demand (read+write) misses 1635system.cpu1.dcache.overall_misses::cpu1.data 257094 # number of overall misses 1636system.cpu1.dcache.overall_misses::total 257094 # number of overall misses 1637system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2053970000 # number of ReadReq miss cycles 1638system.cpu1.dcache.ReadReq_miss_latency::total 2053970000 # number of ReadReq miss cycles 1639system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2521876000 # number of WriteReq miss cycles 1640system.cpu1.dcache.WriteReq_miss_latency::total 2521876000 # number of WriteReq miss cycles 1641system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 321694000 # number of LoadLockedReq miss cycles 1642system.cpu1.dcache.LoadLockedReq_miss_latency::total 321694000 # number of LoadLockedReq miss cycles 1643system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 544347500 # number of StoreCondReq miss cycles 1644system.cpu1.dcache.StoreCondReq_miss_latency::total 544347500 # number of StoreCondReq miss cycles 1645system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1836500 # number of StoreCondFailReq miss cycles 1646system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1836500 # number of StoreCondFailReq miss cycles 1647system.cpu1.dcache.demand_miss_latency::cpu1.data 4575846000 # number of demand (read+write) miss cycles 1648system.cpu1.dcache.demand_miss_latency::total 4575846000 # number of demand (read+write) miss cycles 1649system.cpu1.dcache.overall_miss_latency::cpu1.data 4575846000 # number of overall miss cycles 1650system.cpu1.dcache.overall_miss_latency::total 4575846000 # number of overall miss cycles 1651system.cpu1.dcache.ReadReq_accesses::cpu1.data 3796655 # number of ReadReq accesses(hits+misses) 1652system.cpu1.dcache.ReadReq_accesses::total 3796655 # number of ReadReq accesses(hits+misses) 1653system.cpu1.dcache.WriteReq_accesses::cpu1.data 3349282 # number of WriteReq accesses(hits+misses) 1654system.cpu1.dcache.WriteReq_accesses::total 3349282 # number of WriteReq accesses(hits+misses) 1655system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79722 # number of SoftPFReq accesses(hits+misses) 1656system.cpu1.dcache.SoftPFReq_accesses::total 79722 # number of SoftPFReq accesses(hits+misses) 1657system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96341 # number of LoadLockedReq accesses(hits+misses) 1658system.cpu1.dcache.LoadLockedReq_accesses::total 96341 # number of LoadLockedReq accesses(hits+misses) 1659system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94495 # number of StoreCondReq accesses(hits+misses) 1660system.cpu1.dcache.StoreCondReq_accesses::total 94495 # number of StoreCondReq accesses(hits+misses) 1661system.cpu1.dcache.demand_accesses::cpu1.data 7145937 # number of demand (read+write) accesses 1662system.cpu1.dcache.demand_accesses::total 7145937 # number of demand (read+write) accesses 1663system.cpu1.dcache.overall_accesses::cpu1.data 7225659 # number of overall (read+write) accesses 1664system.cpu1.dcache.overall_accesses::total 7225659 # number of overall (read+write) accesses 1665system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035393 # miss rate for ReadReq accesses 1666system.cpu1.dcache.ReadReq_miss_rate::total 0.035393 # miss rate for ReadReq accesses 1667system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027529 # miss rate for WriteReq accesses 1668system.cpu1.dcache.WriteReq_miss_rate::total 0.027529 # miss rate for WriteReq accesses 1669system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.382780 # miss rate for SoftPFReq accesses 1670system.cpu1.dcache.SoftPFReq_miss_rate::total 0.382780 # miss rate for SoftPFReq accesses 1671system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.176550 # miss rate for LoadLockedReq accesses 1672system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.176550 # miss rate for LoadLockedReq accesses 1673system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.245484 # miss rate for StoreCondReq accesses 1674system.cpu1.dcache.StoreCondReq_miss_rate::total 0.245484 # miss rate for StoreCondReq accesses 1675system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031707 # miss rate for demand accesses 1676system.cpu1.dcache.demand_miss_rate::total 0.031707 # miss rate for demand accesses 1677system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035581 # miss rate for overall accesses 1678system.cpu1.dcache.overall_miss_rate::total 0.035581 # miss rate for overall accesses 1679system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15285.244389 # average ReadReq miss latency 1680system.cpu1.dcache.ReadReq_avg_miss_latency::total 15285.244389 # average ReadReq miss latency 1681system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 27351.640962 # average WriteReq miss latency 1682system.cpu1.dcache.WriteReq_avg_miss_latency::total 27351.640962 # average WriteReq miss latency 1683system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18913.163619 # average LoadLockedReq miss latency 1684system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18913.163619 # average LoadLockedReq miss latency 1685system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23466.288744 # average StoreCondReq miss latency 1686system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23466.288744 # average StoreCondReq miss latency 1687system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1688system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1689system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20195.455870 # average overall miss latency 1690system.cpu1.dcache.demand_avg_miss_latency::total 20195.455870 # average overall miss latency 1691system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17798.338351 # average overall miss latency 1692system.cpu1.dcache.overall_avg_miss_latency::total 17798.338351 # average overall miss latency 1693system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1694system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1695system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1696system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1697system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1698system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1699system.cpu1.dcache.writebacks::writebacks 188214 # number of writebacks 1700system.cpu1.dcache.writebacks::total 188214 # number of writebacks 1701system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 253 # number of ReadReq MSHR hits 1702system.cpu1.dcache.ReadReq_mshr_hits::total 253 # number of ReadReq MSHR hits 1703system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12043 # number of LoadLockedReq MSHR hits 1704system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12043 # number of LoadLockedReq MSHR hits 1705system.cpu1.dcache.demand_mshr_hits::cpu1.data 253 # number of demand (read+write) MSHR hits 1706system.cpu1.dcache.demand_mshr_hits::total 253 # number of demand (read+write) MSHR hits 1707system.cpu1.dcache.overall_mshr_hits::cpu1.data 253 # number of overall MSHR hits 1708system.cpu1.dcache.overall_mshr_hits::total 253 # number of overall MSHR hits 1709system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 134123 # number of ReadReq MSHR misses 1710system.cpu1.dcache.ReadReq_mshr_misses::total 134123 # number of ReadReq MSHR misses 1711system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 92202 # number of WriteReq MSHR misses 1712system.cpu1.dcache.WriteReq_mshr_misses::total 92202 # number of WriteReq MSHR misses 1713system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29799 # number of SoftPFReq MSHR misses 1714system.cpu1.dcache.SoftPFReq_mshr_misses::total 29799 # number of SoftPFReq MSHR misses 1715system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4966 # number of LoadLockedReq MSHR misses 1716system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4966 # number of LoadLockedReq MSHR misses 1717system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23197 # number of StoreCondReq MSHR misses 1718system.cpu1.dcache.StoreCondReq_mshr_misses::total 23197 # number of StoreCondReq MSHR misses 1719system.cpu1.dcache.demand_mshr_misses::cpu1.data 226325 # number of demand (read+write) MSHR misses 1720system.cpu1.dcache.demand_mshr_misses::total 226325 # number of demand (read+write) MSHR misses 1721system.cpu1.dcache.overall_mshr_misses::cpu1.data 256124 # number of overall MSHR misses 1722system.cpu1.dcache.overall_mshr_misses::total 256124 # number of overall MSHR misses 1723system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3085 # number of ReadReq MSHR uncacheable 1724system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3085 # number of ReadReq MSHR uncacheable 1725system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2441 # number of WriteReq MSHR uncacheable 1726system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2441 # number of WriteReq MSHR uncacheable 1727system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5526 # number of overall MSHR uncacheable misses 1728system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5526 # number of overall MSHR uncacheable misses 1729system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1909849500 # number of ReadReq MSHR miss cycles 1730system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1909849500 # number of ReadReq MSHR miss cycles 1731system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2429674000 # number of WriteReq MSHR miss cycles 1732system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2429674000 # number of WriteReq MSHR miss cycles 1733system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 508192000 # number of SoftPFReq MSHR miss cycles 1734system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 508192000 # number of SoftPFReq MSHR miss cycles 1735system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89547000 # number of LoadLockedReq MSHR miss cycles 1736system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89547000 # number of LoadLockedReq MSHR miss cycles 1737system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 521193500 # number of StoreCondReq MSHR miss cycles 1738system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 521193500 # number of StoreCondReq MSHR miss cycles 1739system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1793500 # number of StoreCondFailReq MSHR miss cycles 1740system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1793500 # number of StoreCondFailReq MSHR miss cycles 1741system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4339523500 # number of demand (read+write) MSHR miss cycles 1742system.cpu1.dcache.demand_mshr_miss_latency::total 4339523500 # number of demand (read+write) MSHR miss cycles 1743system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4847715500 # number of overall MSHR miss cycles 1744system.cpu1.dcache.overall_mshr_miss_latency::total 4847715500 # number of overall MSHR miss cycles 1745system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 443097000 # number of ReadReq MSHR uncacheable cycles 1746system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 443097000 # number of ReadReq MSHR uncacheable cycles 1747system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 443097000 # number of overall MSHR uncacheable cycles 1748system.cpu1.dcache.overall_mshr_uncacheable_latency::total 443097000 # number of overall MSHR uncacheable cycles 1749system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035327 # mshr miss rate for ReadReq accesses 1750system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035327 # mshr miss rate for ReadReq accesses 1751system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027529 # mshr miss rate for WriteReq accesses 1752system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027529 # mshr miss rate for WriteReq accesses 1753system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.373786 # mshr miss rate for SoftPFReq accesses 1754system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.373786 # mshr miss rate for SoftPFReq accesses 1755system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.051546 # mshr miss rate for LoadLockedReq accesses 1756system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.051546 # mshr miss rate for LoadLockedReq accesses 1757system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.245484 # mshr miss rate for StoreCondReq accesses 1758system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.245484 # mshr miss rate for StoreCondReq accesses 1759system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031672 # mshr miss rate for demand accesses 1760system.cpu1.dcache.demand_mshr_miss_rate::total 0.031672 # mshr miss rate for demand accesses 1761system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035446 # mshr miss rate for overall accesses 1762system.cpu1.dcache.overall_mshr_miss_rate::total 0.035446 # mshr miss rate for overall accesses 1763system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14239.537589 # average ReadReq mshr miss latency 1764system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14239.537589 # average ReadReq mshr miss latency 1765system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26351.640962 # average WriteReq mshr miss latency 1766system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26351.640962 # average WriteReq mshr miss latency 1767system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17053.995101 # average SoftPFReq mshr miss latency 1768system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17053.995101 # average SoftPFReq mshr miss latency 1769system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18032.017720 # average LoadLockedReq mshr miss latency 1770system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18032.017720 # average LoadLockedReq mshr miss latency 1771system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22468.142432 # average StoreCondReq mshr miss latency 1772system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22468.142432 # average StoreCondReq mshr miss latency 1773system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1774system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1775system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19173.858389 # average overall mshr miss latency 1776system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19173.858389 # average overall mshr miss latency 1777system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18927.220799 # average overall mshr miss latency 1778system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18927.220799 # average overall mshr miss latency 1779system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143629.497569 # average ReadReq mshr uncacheable latency 1780system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 143629.497569 # average ReadReq mshr uncacheable latency 1781system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 80184.039088 # average overall mshr uncacheable latency 1782system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 80184.039088 # average overall mshr uncacheable latency 1783system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 1784system.cpu1.icache.tags.replacements 506865 # number of replacements 1785system.cpu1.icache.tags.tagsinuse 498.456606 # Cycle average of tags in use 1786system.cpu1.icache.tags.total_refs 16246088 # Total number of references to valid blocks. 1787system.cpu1.icache.tags.sampled_refs 507377 # Sample count of references to valid blocks. 1788system.cpu1.icache.tags.avg_refs 32.019757 # Average number of references to valid blocks. 1789system.cpu1.icache.tags.warmup_cycle 85409397000 # Cycle when the warmup percentage was hit. 1790system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.456606 # Average occupied blocks per requestor 1791system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973548 # Average percentage of cache occupancy 1792system.cpu1.icache.tags.occ_percent::total 0.973548 # Average percentage of cache occupancy 1793system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1794system.cpu1.icache.tags.age_task_id_blocks_1024::2 389 # Occupied blocks per task id 1795system.cpu1.icache.tags.age_task_id_blocks_1024::3 119 # Occupied blocks per task id 1796system.cpu1.icache.tags.age_task_id_blocks_1024::4 4 # Occupied blocks per task id 1797system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1798system.cpu1.icache.tags.tag_accesses 34014307 # Number of tag accesses 1799system.cpu1.icache.tags.data_accesses 34014307 # Number of data accesses 1800system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 1801system.cpu1.icache.ReadReq_hits::cpu1.inst 16246088 # number of ReadReq hits 1802system.cpu1.icache.ReadReq_hits::total 16246088 # number of ReadReq hits 1803system.cpu1.icache.demand_hits::cpu1.inst 16246088 # number of demand (read+write) hits 1804system.cpu1.icache.demand_hits::total 16246088 # number of demand (read+write) hits 1805system.cpu1.icache.overall_hits::cpu1.inst 16246088 # number of overall hits 1806system.cpu1.icache.overall_hits::total 16246088 # number of overall hits 1807system.cpu1.icache.ReadReq_misses::cpu1.inst 507377 # number of ReadReq misses 1808system.cpu1.icache.ReadReq_misses::total 507377 # number of ReadReq misses 1809system.cpu1.icache.demand_misses::cpu1.inst 507377 # number of demand (read+write) misses 1810system.cpu1.icache.demand_misses::total 507377 # number of demand (read+write) misses 1811system.cpu1.icache.overall_misses::cpu1.inst 507377 # number of overall misses 1812system.cpu1.icache.overall_misses::total 507377 # number of overall misses 1813system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4790701000 # number of ReadReq miss cycles 1814system.cpu1.icache.ReadReq_miss_latency::total 4790701000 # number of ReadReq miss cycles 1815system.cpu1.icache.demand_miss_latency::cpu1.inst 4790701000 # number of demand (read+write) miss cycles 1816system.cpu1.icache.demand_miss_latency::total 4790701000 # number of demand (read+write) miss cycles 1817system.cpu1.icache.overall_miss_latency::cpu1.inst 4790701000 # number of overall miss cycles 1818system.cpu1.icache.overall_miss_latency::total 4790701000 # number of overall miss cycles 1819system.cpu1.icache.ReadReq_accesses::cpu1.inst 16753465 # number of ReadReq accesses(hits+misses) 1820system.cpu1.icache.ReadReq_accesses::total 16753465 # number of ReadReq accesses(hits+misses) 1821system.cpu1.icache.demand_accesses::cpu1.inst 16753465 # number of demand (read+write) accesses 1822system.cpu1.icache.demand_accesses::total 16753465 # number of demand (read+write) accesses 1823system.cpu1.icache.overall_accesses::cpu1.inst 16753465 # number of overall (read+write) accesses 1824system.cpu1.icache.overall_accesses::total 16753465 # number of overall (read+write) accesses 1825system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030285 # miss rate for ReadReq accesses 1826system.cpu1.icache.ReadReq_miss_rate::total 0.030285 # miss rate for ReadReq accesses 1827system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030285 # miss rate for demand accesses 1828system.cpu1.icache.demand_miss_rate::total 0.030285 # miss rate for demand accesses 1829system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030285 # miss rate for overall accesses 1830system.cpu1.icache.overall_miss_rate::total 0.030285 # miss rate for overall accesses 1831system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9442.093355 # average ReadReq miss latency 1832system.cpu1.icache.ReadReq_avg_miss_latency::total 9442.093355 # average ReadReq miss latency 1833system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9442.093355 # average overall miss latency 1834system.cpu1.icache.demand_avg_miss_latency::total 9442.093355 # average overall miss latency 1835system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9442.093355 # average overall miss latency 1836system.cpu1.icache.overall_avg_miss_latency::total 9442.093355 # average overall miss latency 1837system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1838system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1839system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1840system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1841system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1842system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1843system.cpu1.icache.writebacks::writebacks 506865 # number of writebacks 1844system.cpu1.icache.writebacks::total 506865 # number of writebacks 1845system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 507377 # number of ReadReq MSHR misses 1846system.cpu1.icache.ReadReq_mshr_misses::total 507377 # number of ReadReq MSHR misses 1847system.cpu1.icache.demand_mshr_misses::cpu1.inst 507377 # number of demand (read+write) MSHR misses 1848system.cpu1.icache.demand_mshr_misses::total 507377 # number of demand (read+write) MSHR misses 1849system.cpu1.icache.overall_mshr_misses::cpu1.inst 507377 # number of overall MSHR misses 1850system.cpu1.icache.overall_mshr_misses::total 507377 # number of overall MSHR misses 1851system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable 1852system.cpu1.icache.ReadReq_mshr_uncacheable::total 177 # number of ReadReq MSHR uncacheable 1853system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses 1854system.cpu1.icache.overall_mshr_uncacheable_misses::total 177 # number of overall MSHR uncacheable misses 1855system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4537012500 # number of ReadReq MSHR miss cycles 1856system.cpu1.icache.ReadReq_mshr_miss_latency::total 4537012500 # number of ReadReq MSHR miss cycles 1857system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4537012500 # number of demand (read+write) MSHR miss cycles 1858system.cpu1.icache.demand_mshr_miss_latency::total 4537012500 # number of demand (read+write) MSHR miss cycles 1859system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4537012500 # number of overall MSHR miss cycles 1860system.cpu1.icache.overall_mshr_miss_latency::total 4537012500 # number of overall MSHR miss cycles 1861system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 17068500 # number of ReadReq MSHR uncacheable cycles 1862system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 17068500 # number of ReadReq MSHR uncacheable cycles 1863system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 17068500 # number of overall MSHR uncacheable cycles 1864system.cpu1.icache.overall_mshr_uncacheable_latency::total 17068500 # number of overall MSHR uncacheable cycles 1865system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.030285 # mshr miss rate for ReadReq accesses 1866system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.030285 # mshr miss rate for ReadReq accesses 1867system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.030285 # mshr miss rate for demand accesses 1868system.cpu1.icache.demand_mshr_miss_rate::total 0.030285 # mshr miss rate for demand accesses 1869system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.030285 # mshr miss rate for overall accesses 1870system.cpu1.icache.overall_mshr_miss_rate::total 0.030285 # mshr miss rate for overall accesses 1871system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8942.093355 # average ReadReq mshr miss latency 1872system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8942.093355 # average ReadReq mshr miss latency 1873system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8942.093355 # average overall mshr miss latency 1874system.cpu1.icache.demand_avg_mshr_miss_latency::total 8942.093355 # average overall mshr miss latency 1875system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8942.093355 # average overall mshr miss latency 1876system.cpu1.icache.overall_avg_mshr_miss_latency::total 8942.093355 # average overall mshr miss latency 1877system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 96432.203390 # average ReadReq mshr uncacheable latency 1878system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 96432.203390 # average ReadReq mshr uncacheable latency 1879system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 96432.203390 # average overall mshr uncacheable latency 1880system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 96432.203390 # average overall mshr uncacheable latency 1881system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 1882system.cpu1.l2cache.prefetcher.num_hwpf_issued 202159 # number of hwpf issued 1883system.cpu1.l2cache.prefetcher.pfIdentified 202159 # number of prefetch candidates identified 1884system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 1885system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1886system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1887system.cpu1.l2cache.prefetcher.pfSpanPage 59833 # number of prefetches not generated due to page crossing 1888system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 1889system.cpu1.l2cache.tags.replacements 43683 # number of replacements 1890system.cpu1.l2cache.tags.tagsinuse 14553.446834 # Cycle average of tags in use 1891system.cpu1.l2cache.tags.total_refs 604546 # Total number of references to valid blocks. 1892system.cpu1.l2cache.tags.sampled_refs 57834 # Sample count of references to valid blocks. 1893system.cpu1.l2cache.tags.avg_refs 10.453124 # Average number of references to valid blocks. 1894system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1895system.cpu1.l2cache.tags.occ_blocks::writebacks 14136.855711 # Average occupied blocks per requestor 1896system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 2.245443 # Average occupied blocks per requestor 1897system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.035798 # Average occupied blocks per requestor 1898system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 412.309882 # Average occupied blocks per requestor 1899system.cpu1.l2cache.tags.occ_percent::writebacks 0.862845 # Average percentage of cache occupancy 1900system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000137 # Average percentage of cache occupancy 1901system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000124 # Average percentage of cache occupancy 1902system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.025165 # Average percentage of cache occupancy 1903system.cpu1.l2cache.tags.occ_percent::total 0.888272 # Average percentage of cache occupancy 1904system.cpu1.l2cache.tags.occ_task_id_blocks::1022 316 # Occupied blocks per task id 1905system.cpu1.l2cache.tags.occ_task_id_blocks::1023 10 # Occupied blocks per task id 1906system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13825 # Occupied blocks per task id 1907system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 6 # Occupied blocks per task id 1908system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 17 # Occupied blocks per task id 1909system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 293 # Occupied blocks per task id 1910system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id 1911system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id 1912system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1016 # Occupied blocks per task id 1913system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2429 # Occupied blocks per task id 1914system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 10380 # Occupied blocks per task id 1915system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.019287 # Percentage of cache occupancy per task id 1916system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000610 # Percentage of cache occupancy per task id 1917system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.843811 # Percentage of cache occupancy per task id 1918system.cpu1.l2cache.tags.tag_accesses 24413579 # Number of tag accesses 1919system.cpu1.l2cache.tags.data_accesses 24413579 # Number of data accesses 1920system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 1921system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3816 # number of ReadReq hits 1922system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2015 # number of ReadReq hits 1923system.cpu1.l2cache.ReadReq_hits::total 5831 # number of ReadReq hits 1924system.cpu1.l2cache.WritebackDirty_hits::writebacks 114934 # number of WritebackDirty hits 1925system.cpu1.l2cache.WritebackDirty_hits::total 114934 # number of WritebackDirty hits 1926system.cpu1.l2cache.WritebackClean_hits::writebacks 568988 # number of WritebackClean hits 1927system.cpu1.l2cache.WritebackClean_hits::total 568988 # number of WritebackClean hits 1928system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27893 # number of ReadExReq hits 1929system.cpu1.l2cache.ReadExReq_hits::total 27893 # number of ReadExReq hits 1930system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 485948 # number of ReadCleanReq hits 1931system.cpu1.l2cache.ReadCleanReq_hits::total 485948 # number of ReadCleanReq hits 1932system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 99069 # number of ReadSharedReq hits 1933system.cpu1.l2cache.ReadSharedReq_hits::total 99069 # number of ReadSharedReq hits 1934system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3816 # number of demand (read+write) hits 1935system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2015 # number of demand (read+write) hits 1936system.cpu1.l2cache.demand_hits::cpu1.inst 485948 # number of demand (read+write) hits 1937system.cpu1.l2cache.demand_hits::cpu1.data 126962 # number of demand (read+write) hits 1938system.cpu1.l2cache.demand_hits::total 618741 # number of demand (read+write) hits 1939system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3816 # number of overall hits 1940system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2015 # number of overall hits 1941system.cpu1.l2cache.overall_hits::cpu1.inst 485948 # number of overall hits 1942system.cpu1.l2cache.overall_hits::cpu1.data 126962 # number of overall hits 1943system.cpu1.l2cache.overall_hits::total 618741 # number of overall hits 1944system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 441 # number of ReadReq misses 1945system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 325 # number of ReadReq misses 1946system.cpu1.l2cache.ReadReq_misses::total 766 # number of ReadReq misses 1947system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29445 # number of UpgradeReq misses 1948system.cpu1.l2cache.UpgradeReq_misses::total 29445 # number of UpgradeReq misses 1949system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23189 # number of SCUpgradeReq misses 1950system.cpu1.l2cache.SCUpgradeReq_misses::total 23189 # number of SCUpgradeReq misses 1951system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 8 # number of SCUpgradeFailReq misses 1952system.cpu1.l2cache.SCUpgradeFailReq_misses::total 8 # number of SCUpgradeFailReq misses 1953system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34864 # number of ReadExReq misses 1954system.cpu1.l2cache.ReadExReq_misses::total 34864 # number of ReadExReq misses 1955system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 21429 # number of ReadCleanReq misses 1956system.cpu1.l2cache.ReadCleanReq_misses::total 21429 # number of ReadCleanReq misses 1957system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 69819 # number of ReadSharedReq misses 1958system.cpu1.l2cache.ReadSharedReq_misses::total 69819 # number of ReadSharedReq misses 1959system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 441 # number of demand (read+write) misses 1960system.cpu1.l2cache.demand_misses::cpu1.itb.walker 325 # number of demand (read+write) misses 1961system.cpu1.l2cache.demand_misses::cpu1.inst 21429 # number of demand (read+write) misses 1962system.cpu1.l2cache.demand_misses::cpu1.data 104683 # number of demand (read+write) misses 1963system.cpu1.l2cache.demand_misses::total 126878 # number of demand (read+write) misses 1964system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 441 # number of overall misses 1965system.cpu1.l2cache.overall_misses::cpu1.itb.walker 325 # number of overall misses 1966system.cpu1.l2cache.overall_misses::cpu1.inst 21429 # number of overall misses 1967system.cpu1.l2cache.overall_misses::cpu1.data 104683 # number of overall misses 1968system.cpu1.l2cache.overall_misses::total 126878 # number of overall misses 1969system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 9097000 # number of ReadReq miss cycles 1970system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 6572000 # number of ReadReq miss cycles 1971system.cpu1.l2cache.ReadReq_miss_latency::total 15669000 # number of ReadReq miss cycles 1972system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 14547500 # number of UpgradeReq miss cycles 1973system.cpu1.l2cache.UpgradeReq_miss_latency::total 14547500 # number of UpgradeReq miss cycles 1974system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 17306000 # number of SCUpgradeReq miss cycles 1975system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 17306000 # number of SCUpgradeReq miss cycles 1976system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1729000 # number of SCUpgradeFailReq miss cycles 1977system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1729000 # number of SCUpgradeFailReq miss cycles 1978system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1479795000 # number of ReadExReq miss cycles 1979system.cpu1.l2cache.ReadExReq_miss_latency::total 1479795000 # number of ReadExReq miss cycles 1980system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 845906500 # number of ReadCleanReq miss cycles 1981system.cpu1.l2cache.ReadCleanReq_miss_latency::total 845906500 # number of ReadCleanReq miss cycles 1982system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1606277000 # number of ReadSharedReq miss cycles 1983system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1606277000 # number of ReadSharedReq miss cycles 1984system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 9097000 # number of demand (read+write) miss cycles 1985system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 6572000 # number of demand (read+write) miss cycles 1986system.cpu1.l2cache.demand_miss_latency::cpu1.inst 845906500 # number of demand (read+write) miss cycles 1987system.cpu1.l2cache.demand_miss_latency::cpu1.data 3086072000 # number of demand (read+write) miss cycles 1988system.cpu1.l2cache.demand_miss_latency::total 3947647500 # number of demand (read+write) miss cycles 1989system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 9097000 # number of overall miss cycles 1990system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 6572000 # number of overall miss cycles 1991system.cpu1.l2cache.overall_miss_latency::cpu1.inst 845906500 # number of overall miss cycles 1992system.cpu1.l2cache.overall_miss_latency::cpu1.data 3086072000 # number of overall miss cycles 1993system.cpu1.l2cache.overall_miss_latency::total 3947647500 # number of overall miss cycles 1994system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 4257 # number of ReadReq accesses(hits+misses) 1995system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2340 # number of ReadReq accesses(hits+misses) 1996system.cpu1.l2cache.ReadReq_accesses::total 6597 # number of ReadReq accesses(hits+misses) 1997system.cpu1.l2cache.WritebackDirty_accesses::writebacks 114934 # number of WritebackDirty accesses(hits+misses) 1998system.cpu1.l2cache.WritebackDirty_accesses::total 114934 # number of WritebackDirty accesses(hits+misses) 1999system.cpu1.l2cache.WritebackClean_accesses::writebacks 568988 # number of WritebackClean accesses(hits+misses) 2000system.cpu1.l2cache.WritebackClean_accesses::total 568988 # number of WritebackClean accesses(hits+misses) 2001system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29445 # number of UpgradeReq accesses(hits+misses) 2002system.cpu1.l2cache.UpgradeReq_accesses::total 29445 # number of UpgradeReq accesses(hits+misses) 2003system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23189 # number of SCUpgradeReq accesses(hits+misses) 2004system.cpu1.l2cache.SCUpgradeReq_accesses::total 23189 # number of SCUpgradeReq accesses(hits+misses) 2005system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 8 # number of SCUpgradeFailReq accesses(hits+misses) 2006system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 8 # number of SCUpgradeFailReq accesses(hits+misses) 2007system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 62757 # number of ReadExReq accesses(hits+misses) 2008system.cpu1.l2cache.ReadExReq_accesses::total 62757 # number of ReadExReq accesses(hits+misses) 2009system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 507377 # number of ReadCleanReq accesses(hits+misses) 2010system.cpu1.l2cache.ReadCleanReq_accesses::total 507377 # number of ReadCleanReq accesses(hits+misses) 2011system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 168888 # number of ReadSharedReq accesses(hits+misses) 2012system.cpu1.l2cache.ReadSharedReq_accesses::total 168888 # number of ReadSharedReq accesses(hits+misses) 2013system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 4257 # number of demand (read+write) accesses 2014system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2340 # number of demand (read+write) accesses 2015system.cpu1.l2cache.demand_accesses::cpu1.inst 507377 # number of demand (read+write) accesses 2016system.cpu1.l2cache.demand_accesses::cpu1.data 231645 # number of demand (read+write) accesses 2017system.cpu1.l2cache.demand_accesses::total 745619 # number of demand (read+write) accesses 2018system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 4257 # number of overall (read+write) accesses 2019system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2340 # number of overall (read+write) accesses 2020system.cpu1.l2cache.overall_accesses::cpu1.inst 507377 # number of overall (read+write) accesses 2021system.cpu1.l2cache.overall_accesses::cpu1.data 231645 # number of overall (read+write) accesses 2022system.cpu1.l2cache.overall_accesses::total 745619 # number of overall (read+write) accesses 2023system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.103594 # miss rate for ReadReq accesses 2024system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.138889 # miss rate for ReadReq accesses 2025system.cpu1.l2cache.ReadReq_miss_rate::total 0.116113 # miss rate for ReadReq accesses 2026system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 2027system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 2028system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 2029system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 2030system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2031system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 2032system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.555540 # miss rate for ReadExReq accesses 2033system.cpu1.l2cache.ReadExReq_miss_rate::total 0.555540 # miss rate for ReadExReq accesses 2034system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.042235 # miss rate for ReadCleanReq accesses 2035system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.042235 # miss rate for ReadCleanReq accesses 2036system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.413404 # miss rate for ReadSharedReq accesses 2037system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.413404 # miss rate for ReadSharedReq accesses 2038system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.103594 # miss rate for demand accesses 2039system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.138889 # miss rate for demand accesses 2040system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.042235 # miss rate for demand accesses 2041system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.451911 # miss rate for demand accesses 2042system.cpu1.l2cache.demand_miss_rate::total 0.170165 # miss rate for demand accesses 2043system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.103594 # miss rate for overall accesses 2044system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.138889 # miss rate for overall accesses 2045system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.042235 # miss rate for overall accesses 2046system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.451911 # miss rate for overall accesses 2047system.cpu1.l2cache.overall_miss_rate::total 0.170165 # miss rate for overall accesses 2048system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20628.117914 # average ReadReq miss latency 2049system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20221.538462 # average ReadReq miss latency 2050system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20455.613577 # average ReadReq miss latency 2051system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 494.056716 # average UpgradeReq miss latency 2052system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 494.056716 # average UpgradeReq miss latency 2053system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 746.302126 # average SCUpgradeReq miss latency 2054system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 746.302126 # average SCUpgradeReq miss latency 2055system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 216125 # average SCUpgradeFailReq miss latency 2056system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 216125 # average SCUpgradeFailReq miss latency 2057system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 42444.785452 # average ReadExReq miss latency 2058system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 42444.785452 # average ReadExReq miss latency 2059system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 39474.847170 # average ReadCleanReq miss latency 2060system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 39474.847170 # average ReadCleanReq miss latency 2061system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23006.302009 # average ReadSharedReq miss latency 2062system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23006.302009 # average ReadSharedReq miss latency 2063system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20628.117914 # average overall miss latency 2064system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20221.538462 # average overall miss latency 2065system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 39474.847170 # average overall miss latency 2066system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 29480.163923 # average overall miss latency 2067system.cpu1.l2cache.demand_avg_miss_latency::total 31113.727360 # average overall miss latency 2068system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20628.117914 # average overall miss latency 2069system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20221.538462 # average overall miss latency 2070system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 39474.847170 # average overall miss latency 2071system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 29480.163923 # average overall miss latency 2072system.cpu1.l2cache.overall_avg_miss_latency::total 31113.727360 # average overall miss latency 2073system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2074system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2075system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 2076system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2077system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2078system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2079system.cpu1.l2cache.unused_prefetches 815 # number of HardPF blocks evicted w/o reference 2080system.cpu1.l2cache.writebacks::writebacks 32960 # number of writebacks 2081system.cpu1.l2cache.writebacks::total 32960 # number of writebacks 2082system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 84 # number of ReadExReq MSHR hits 2083system.cpu1.l2cache.ReadExReq_mshr_hits::total 84 # number of ReadExReq MSHR hits 2084system.cpu1.l2cache.demand_mshr_hits::cpu1.data 84 # number of demand (read+write) MSHR hits 2085system.cpu1.l2cache.demand_mshr_hits::total 84 # number of demand (read+write) MSHR hits 2086system.cpu1.l2cache.overall_mshr_hits::cpu1.data 84 # number of overall MSHR hits 2087system.cpu1.l2cache.overall_mshr_hits::total 84 # number of overall MSHR hits 2088system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 441 # number of ReadReq MSHR misses 2089system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 325 # number of ReadReq MSHR misses 2090system.cpu1.l2cache.ReadReq_mshr_misses::total 766 # number of ReadReq MSHR misses 2091system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 25865 # number of HardPFReq MSHR misses 2092system.cpu1.l2cache.HardPFReq_mshr_misses::total 25865 # number of HardPFReq MSHR misses 2093system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29445 # number of UpgradeReq MSHR misses 2094system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29445 # number of UpgradeReq MSHR misses 2095system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23189 # number of SCUpgradeReq MSHR misses 2096system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23189 # number of SCUpgradeReq MSHR misses 2097system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 8 # number of SCUpgradeFailReq MSHR misses 2098system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 8 # number of SCUpgradeFailReq MSHR misses 2099system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34780 # number of ReadExReq MSHR misses 2100system.cpu1.l2cache.ReadExReq_mshr_misses::total 34780 # number of ReadExReq MSHR misses 2101system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 21429 # number of ReadCleanReq MSHR misses 2102system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 21429 # number of ReadCleanReq MSHR misses 2103system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 69819 # number of ReadSharedReq MSHR misses 2104system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 69819 # number of ReadSharedReq MSHR misses 2105system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 441 # number of demand (read+write) MSHR misses 2106system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 325 # number of demand (read+write) MSHR misses 2107system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 21429 # number of demand (read+write) MSHR misses 2108system.cpu1.l2cache.demand_mshr_misses::cpu1.data 104599 # number of demand (read+write) MSHR misses 2109system.cpu1.l2cache.demand_mshr_misses::total 126794 # number of demand (read+write) MSHR misses 2110system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 441 # number of overall MSHR misses 2111system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 325 # number of overall MSHR misses 2112system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 21429 # number of overall MSHR misses 2113system.cpu1.l2cache.overall_mshr_misses::cpu1.data 104599 # number of overall MSHR misses 2114system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 25865 # number of overall MSHR misses 2115system.cpu1.l2cache.overall_mshr_misses::total 152659 # number of overall MSHR misses 2116system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable 2117system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 3085 # number of ReadReq MSHR uncacheable 2118system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 3262 # number of ReadReq MSHR uncacheable 2119system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2441 # number of WriteReq MSHR uncacheable 2120system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2441 # number of WriteReq MSHR uncacheable 2121system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses 2122system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5526 # number of overall MSHR uncacheable misses 2123system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5703 # number of overall MSHR uncacheable misses 2124system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 6451000 # number of ReadReq MSHR miss cycles 2125system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 4622000 # number of ReadReq MSHR miss cycles 2126system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 11073000 # number of ReadReq MSHR miss cycles 2127system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 943203517 # number of HardPFReq MSHR miss cycles 2128system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 943203517 # number of HardPFReq MSHR miss cycles 2129system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 450885000 # number of UpgradeReq MSHR miss cycles 2130system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 450885000 # number of UpgradeReq MSHR miss cycles 2131system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 347198000 # number of SCUpgradeReq MSHR miss cycles 2132system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 347198000 # number of SCUpgradeReq MSHR miss cycles 2133system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1471000 # number of SCUpgradeFailReq MSHR miss cycles 2134system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1471000 # number of SCUpgradeFailReq MSHR miss cycles 2135system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1260374500 # number of ReadExReq MSHR miss cycles 2136system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1260374500 # number of ReadExReq MSHR miss cycles 2137system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 717332500 # number of ReadCleanReq MSHR miss cycles 2138system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 717332500 # number of ReadCleanReq MSHR miss cycles 2139system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1187363000 # number of ReadSharedReq MSHR miss cycles 2140system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1187363000 # number of ReadSharedReq MSHR miss cycles 2141system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 6451000 # number of demand (read+write) MSHR miss cycles 2142system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4622000 # number of demand (read+write) MSHR miss cycles 2143system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 717332500 # number of demand (read+write) MSHR miss cycles 2144system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2447737500 # number of demand (read+write) MSHR miss cycles 2145system.cpu1.l2cache.demand_mshr_miss_latency::total 3176143000 # number of demand (read+write) MSHR miss cycles 2146system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 6451000 # number of overall MSHR miss cycles 2147system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4622000 # number of overall MSHR miss cycles 2148system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 717332500 # number of overall MSHR miss cycles 2149system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2447737500 # number of overall MSHR miss cycles 2150system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 943203517 # number of overall MSHR miss cycles 2151system.cpu1.l2cache.overall_mshr_miss_latency::total 4119346517 # number of overall MSHR miss cycles 2152system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 15741000 # number of ReadReq MSHR uncacheable cycles 2153system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 418070500 # number of ReadReq MSHR uncacheable cycles 2154system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 433811500 # number of ReadReq MSHR uncacheable cycles 2155system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 15741000 # number of overall MSHR uncacheable cycles 2156system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 418070500 # number of overall MSHR uncacheable cycles 2157system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 433811500 # number of overall MSHR uncacheable cycles 2158system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.103594 # mshr miss rate for ReadReq accesses 2159system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.138889 # mshr miss rate for ReadReq accesses 2160system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.116113 # mshr miss rate for ReadReq accesses 2161system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2162system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2163system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 2164system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 2165system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses 2166system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 2167system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2168system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 2169system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.554201 # mshr miss rate for ReadExReq accesses 2170system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.554201 # mshr miss rate for ReadExReq accesses 2171system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.042235 # mshr miss rate for ReadCleanReq accesses 2172system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.042235 # mshr miss rate for ReadCleanReq accesses 2173system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.413404 # mshr miss rate for ReadSharedReq accesses 2174system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.413404 # mshr miss rate for ReadSharedReq accesses 2175system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.103594 # mshr miss rate for demand accesses 2176system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.138889 # mshr miss rate for demand accesses 2177system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.042235 # mshr miss rate for demand accesses 2178system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.451549 # mshr miss rate for demand accesses 2179system.cpu1.l2cache.demand_mshr_miss_rate::total 0.170052 # mshr miss rate for demand accesses 2180system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.103594 # mshr miss rate for overall accesses 2181system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.138889 # mshr miss rate for overall accesses 2182system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.042235 # mshr miss rate for overall accesses 2183system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.451549 # mshr miss rate for overall accesses 2184system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2185system.cpu1.l2cache.overall_mshr_miss_rate::total 0.204741 # mshr miss rate for overall accesses 2186system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14628.117914 # average ReadReq mshr miss latency 2187system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14221.538462 # average ReadReq mshr miss latency 2188system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14455.613577 # average ReadReq mshr miss latency 2189system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36466.403132 # average HardPFReq mshr miss latency 2190system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 36466.403132 # average HardPFReq mshr miss latency 2191system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15312.786551 # average UpgradeReq mshr miss latency 2192system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15312.786551 # average UpgradeReq mshr miss latency 2193system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14972.530079 # average SCUpgradeReq mshr miss latency 2194system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14972.530079 # average SCUpgradeReq mshr miss latency 2195system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 183875 # average SCUpgradeFailReq mshr miss latency 2196system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 183875 # average SCUpgradeFailReq mshr miss latency 2197system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36238.484761 # average ReadExReq mshr miss latency 2198system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36238.484761 # average ReadExReq mshr miss latency 2199system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 33474.847170 # average ReadCleanReq mshr miss latency 2200system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33474.847170 # average ReadCleanReq mshr miss latency 2201system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17006.302009 # average ReadSharedReq mshr miss latency 2202system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17006.302009 # average ReadSharedReq mshr miss latency 2203system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14628.117914 # average overall mshr miss latency 2204system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14221.538462 # average overall mshr miss latency 2205system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 33474.847170 # average overall mshr miss latency 2206system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 23401.155843 # average overall mshr miss latency 2207system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25049.631686 # average overall mshr miss latency 2208system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14628.117914 # average overall mshr miss latency 2209system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14221.538462 # average overall mshr miss latency 2210system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 33474.847170 # average overall mshr miss latency 2211system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 23401.155843 # average overall mshr miss latency 2212system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36466.403132 # average overall mshr miss latency 2213system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26983.974197 # average overall mshr miss latency 2214system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 88932.203390 # average ReadReq mshr uncacheable latency 2215system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 135517.179903 # average ReadReq mshr uncacheable latency 2216system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 132989.423666 # average ReadReq mshr uncacheable latency 2217system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 88932.203390 # average overall mshr uncacheable latency 2218system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75655.175534 # average overall mshr uncacheable latency 2219system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 76067.245309 # average overall mshr uncacheable latency 2220system.cpu1.toL2Bus.snoop_filter.tot_requests 1493074 # Total number of requests made to the snoop filter. 2221system.cpu1.toL2Bus.snoop_filter.hit_single_requests 754096 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2222system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11157 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2223system.cpu1.toL2Bus.snoop_filter.tot_snoops 112771 # Total number of snoops made to the snoop filter. 2224system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 104472 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2225system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 8299 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2226system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 2227system.cpu1.toL2Bus.trans_dist::ReadReq 12635 # Transaction distribution 2228system.cpu1.toL2Bus.trans_dist::ReadResp 726264 # Transaction distribution 2229system.cpu1.toL2Bus.trans_dist::WriteReq 2441 # Transaction distribution 2230system.cpu1.toL2Bus.trans_dist::WriteResp 2441 # Transaction distribution 2231system.cpu1.toL2Bus.trans_dist::WritebackDirty 148991 # Transaction distribution 2232system.cpu1.toL2Bus.trans_dist::WritebackClean 580145 # Transaction distribution 2233system.cpu1.toL2Bus.trans_dist::CleanEvict 27848 # Transaction distribution 2234system.cpu1.toL2Bus.trans_dist::HardPFReq 30881 # Transaction distribution 2235system.cpu1.toL2Bus.trans_dist::UpgradeReq 70910 # Transaction distribution 2236system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 40918 # Transaction distribution 2237system.cpu1.toL2Bus.trans_dist::UpgradeResp 85257 # Transaction distribution 2238system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 42 # Transaction distribution 2239system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 77 # Transaction distribution 2240system.cpu1.toL2Bus.trans_dist::ReadExReq 69946 # Transaction distribution 2241system.cpu1.toL2Bus.trans_dist::ReadExResp 67407 # Transaction distribution 2242system.cpu1.toL2Bus.trans_dist::ReadCleanReq 507377 # Transaction distribution 2243system.cpu1.toL2Bus.trans_dist::ReadSharedReq 264100 # Transaction distribution 2244system.cpu1.toL2Bus.trans_dist::InvalidateReq 245 # Transaction distribution 2245system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1521973 # Packet count per connected master and slave (bytes) 2246system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 842546 # Packet count per connected master and slave (bytes) 2247system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5664 # Packet count per connected master and slave (bytes) 2248system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 10306 # Packet count per connected master and slave (bytes) 2249system.cpu1.toL2Bus.pkt_count::total 2380489 # Packet count per connected master and slave (bytes) 2250system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 64912196 # Cumulative packet size per connected master and slave (bytes) 2251system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29583168 # Cumulative packet size per connected master and slave (bytes) 2252system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 9360 # Cumulative packet size per connected master and slave (bytes) 2253system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 17028 # Cumulative packet size per connected master and slave (bytes) 2254system.cpu1.toL2Bus.pkt_size::total 94521752 # Cumulative packet size per connected master and slave (bytes) 2255system.cpu1.toL2Bus.snoops 332142 # Total snoops (count) 2256system.cpu1.toL2Bus.snoopTraffic 4881760 # Total snoop traffic (bytes) 2257system.cpu1.toL2Bus.snoop_fanout::samples 1061400 # Request fanout histogram 2258system.cpu1.toL2Bus.snoop_fanout::mean 0.130546 # Request fanout histogram 2259system.cpu1.toL2Bus.snoop_fanout::stdev 0.359362 # Request fanout histogram 2260system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2261system.cpu1.toL2Bus.snoop_fanout::0 931138 87.73% 87.73% # Request fanout histogram 2262system.cpu1.toL2Bus.snoop_fanout::1 121963 11.49% 99.22% # Request fanout histogram 2263system.cpu1.toL2Bus.snoop_fanout::2 8299 0.78% 100.00% # Request fanout histogram 2264system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2265system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2266system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2267system.cpu1.toL2Bus.snoop_fanout::total 1061400 # Request fanout histogram 2268system.cpu1.toL2Bus.reqLayer0.occupancy 1447209000 # Layer occupancy (ticks) 2269system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 2270system.cpu1.toL2Bus.snoopLayer0.occupancy 79433455 # Layer occupancy (ticks) 2271system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2272system.cpu1.toL2Bus.respLayer0.occupancy 761242500 # Layer occupancy (ticks) 2273system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2274system.cpu1.toL2Bus.respLayer1.occupancy 378138998 # Layer occupancy (ticks) 2275system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2276system.cpu1.toL2Bus.respLayer2.occupancy 3324000 # Layer occupancy (ticks) 2277system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2278system.cpu1.toL2Bus.respLayer3.occupancy 6050996 # Layer occupancy (ticks) 2279system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2280system.iobus.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 2281system.iobus.trans_dist::ReadReq 31015 # Transaction distribution 2282system.iobus.trans_dist::ReadResp 31015 # Transaction distribution 2283system.iobus.trans_dist::WriteReq 59422 # Transaction distribution 2284system.iobus.trans_dist::WriteResp 59422 # Transaction distribution 2285system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes) 2286system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 2287system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 2288system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 2289system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 2290system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 2291system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 2292system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 2293system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2294system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2295system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2296system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 2297system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 2298system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 2299system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 2300system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 2301system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 2302system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 2303system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 2304system.iobus.pkt_count_system.bridge.master::total 107916 # Packet count per connected master and slave (bytes) 2305system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes) 2306system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes) 2307system.iobus.pkt_count::total 180874 # Packet count per connected master and slave (bytes) 2308system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes) 2309system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 2310system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) 2311system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 2312system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 2313system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 2314system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 2315system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 2316system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2317system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2318system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2319system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 2320system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2321system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2322system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 2323system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 2324system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2325system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 2326system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 2327system.iobus.pkt_size_system.bridge.master::total 162796 # Cumulative packet size per connected master and slave (bytes) 2328system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes) 2329system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes) 2330system.iobus.pkt_size::total 2484068 # Cumulative packet size per connected master and slave (bytes) 2331system.iobus.reqLayer0.occupancy 48592000 # Layer occupancy (ticks) 2332system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2333system.iobus.reqLayer1.occupancy 106000 # Layer occupancy (ticks) 2334system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2335system.iobus.reqLayer2.occupancy 318500 # Layer occupancy (ticks) 2336system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2337system.iobus.reqLayer3.occupancy 31500 # Layer occupancy (ticks) 2338system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2339system.iobus.reqLayer4.occupancy 15000 # Layer occupancy (ticks) 2340system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 2341system.iobus.reqLayer7.occupancy 92000 # Layer occupancy (ticks) 2342system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 2343system.iobus.reqLayer8.occupancy 615500 # Layer occupancy (ticks) 2344system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 2345system.iobus.reqLayer10.occupancy 22500 # Layer occupancy (ticks) 2346system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2347system.iobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks) 2348system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2349system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) 2350system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2351system.iobus.reqLayer15.occupancy 11000 # Layer occupancy (ticks) 2352system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 2353system.iobus.reqLayer16.occupancy 46500 # Layer occupancy (ticks) 2354system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2355system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks) 2356system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 2357system.iobus.reqLayer18.occupancy 10500 # Layer occupancy (ticks) 2358system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 2359system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) 2360system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 2361system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) 2362system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 2363system.iobus.reqLayer21.occupancy 10500 # Layer occupancy (ticks) 2364system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 2365system.iobus.reqLayer23.occupancy 6203500 # Layer occupancy (ticks) 2366system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2367system.iobus.reqLayer24.occupancy 32039500 # Layer occupancy (ticks) 2368system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2369system.iobus.reqLayer25.occupancy 187757841 # Layer occupancy (ticks) 2370system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2371system.iobus.respLayer0.occupancy 84718000 # Layer occupancy (ticks) 2372system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2373system.iobus.respLayer3.occupancy 36782000 # Layer occupancy (ticks) 2374system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2375system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 2376system.iocache.tags.replacements 36445 # number of replacements 2377system.iocache.tags.tagsinuse 14.377097 # Cycle average of tags in use 2378system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 2379system.iocache.tags.sampled_refs 36461 # Sample count of references to valid blocks. 2380system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 2381system.iocache.tags.warmup_cycle 290025611000 # Cycle when the warmup percentage was hit. 2382system.iocache.tags.occ_blocks::realview.ide 14.377097 # Average occupied blocks per requestor 2383system.iocache.tags.occ_percent::realview.ide 0.898569 # Average percentage of cache occupancy 2384system.iocache.tags.occ_percent::total 0.898569 # Average percentage of cache occupancy 2385system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2386system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2387system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2388system.iocache.tags.tag_accesses 328311 # Number of tag accesses 2389system.iocache.tags.data_accesses 328311 # Number of data accesses 2390system.iocache.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 2391system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses 2392system.iocache.ReadReq_misses::total 255 # number of ReadReq misses 2393system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 2394system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 2395system.iocache.demand_misses::realview.ide 36479 # number of demand (read+write) misses 2396system.iocache.demand_misses::total 36479 # number of demand (read+write) misses 2397system.iocache.overall_misses::realview.ide 36479 # number of overall misses 2398system.iocache.overall_misses::total 36479 # number of overall misses 2399system.iocache.ReadReq_miss_latency::realview.ide 40988875 # number of ReadReq miss cycles 2400system.iocache.ReadReq_miss_latency::total 40988875 # number of ReadReq miss cycles 2401system.iocache.WriteLineReq_miss_latency::realview.ide 4375977966 # number of WriteLineReq miss cycles 2402system.iocache.WriteLineReq_miss_latency::total 4375977966 # number of WriteLineReq miss cycles 2403system.iocache.demand_miss_latency::realview.ide 4416966841 # number of demand (read+write) miss cycles 2404system.iocache.demand_miss_latency::total 4416966841 # number of demand (read+write) miss cycles 2405system.iocache.overall_miss_latency::realview.ide 4416966841 # number of overall miss cycles 2406system.iocache.overall_miss_latency::total 4416966841 # number of overall miss cycles 2407system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) 2408system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) 2409system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 2410system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) 2411system.iocache.demand_accesses::realview.ide 36479 # number of demand (read+write) accesses 2412system.iocache.demand_accesses::total 36479 # number of demand (read+write) accesses 2413system.iocache.overall_accesses::realview.ide 36479 # number of overall (read+write) accesses 2414system.iocache.overall_accesses::total 36479 # number of overall (read+write) accesses 2415system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2416system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2417system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 2418system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 2419system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2420system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2421system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2422system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2423system.iocache.ReadReq_avg_miss_latency::realview.ide 160740.686275 # average ReadReq miss latency 2424system.iocache.ReadReq_avg_miss_latency::total 160740.686275 # average ReadReq miss latency 2425system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120803.278655 # average WriteLineReq miss latency 2426system.iocache.WriteLineReq_avg_miss_latency::total 120803.278655 # average WriteLineReq miss latency 2427system.iocache.demand_avg_miss_latency::realview.ide 121082.454042 # average overall miss latency 2428system.iocache.demand_avg_miss_latency::total 121082.454042 # average overall miss latency 2429system.iocache.overall_avg_miss_latency::realview.ide 121082.454042 # average overall miss latency 2430system.iocache.overall_avg_miss_latency::total 121082.454042 # average overall miss latency 2431system.iocache.blocked_cycles::no_mshrs 56 # number of cycles access was blocked 2432system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2433system.iocache.blocked::no_mshrs 6 # number of cycles access was blocked 2434system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2435system.iocache.avg_blocked_cycles::no_mshrs 9.333333 # average number of cycles each access was blocked 2436system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2437system.iocache.writebacks::writebacks 36190 # number of writebacks 2438system.iocache.writebacks::total 36190 # number of writebacks 2439system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses 2440system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses 2441system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses 2442system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses 2443system.iocache.demand_mshr_misses::realview.ide 36479 # number of demand (read+write) MSHR misses 2444system.iocache.demand_mshr_misses::total 36479 # number of demand (read+write) MSHR misses 2445system.iocache.overall_mshr_misses::realview.ide 36479 # number of overall MSHR misses 2446system.iocache.overall_mshr_misses::total 36479 # number of overall MSHR misses 2447system.iocache.ReadReq_mshr_miss_latency::realview.ide 28238875 # number of ReadReq MSHR miss cycles 2448system.iocache.ReadReq_mshr_miss_latency::total 28238875 # number of ReadReq MSHR miss cycles 2449system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2562446714 # number of WriteLineReq MSHR miss cycles 2450system.iocache.WriteLineReq_mshr_miss_latency::total 2562446714 # number of WriteLineReq MSHR miss cycles 2451system.iocache.demand_mshr_miss_latency::realview.ide 2590685589 # number of demand (read+write) MSHR miss cycles 2452system.iocache.demand_mshr_miss_latency::total 2590685589 # number of demand (read+write) MSHR miss cycles 2453system.iocache.overall_mshr_miss_latency::realview.ide 2590685589 # number of overall MSHR miss cycles 2454system.iocache.overall_mshr_miss_latency::total 2590685589 # number of overall MSHR miss cycles 2455system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2456system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2457system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 2458system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 2459system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2460system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2461system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2462system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 2463system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 110740.686275 # average ReadReq mshr miss latency 2464system.iocache.ReadReq_avg_mshr_miss_latency::total 110740.686275 # average ReadReq mshr miss latency 2465system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70738.922096 # average WriteLineReq mshr miss latency 2466system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70738.922096 # average WriteLineReq mshr miss latency 2467system.iocache.demand_avg_mshr_miss_latency::realview.ide 71018.547356 # average overall mshr miss latency 2468system.iocache.demand_avg_mshr_miss_latency::total 71018.547356 # average overall mshr miss latency 2469system.iocache.overall_avg_mshr_miss_latency::realview.ide 71018.547356 # average overall mshr miss latency 2470system.iocache.overall_avg_mshr_miss_latency::total 71018.547356 # average overall mshr miss latency 2471system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 2472system.l2c.tags.replacements 137086 # number of replacements 2473system.l2c.tags.tagsinuse 65074.643000 # Cycle average of tags in use 2474system.l2c.tags.total_refs 524868 # Total number of references to valid blocks. 2475system.l2c.tags.sampled_refs 202455 # Sample count of references to valid blocks. 2476system.l2c.tags.avg_refs 2.592517 # Average number of references to valid blocks. 2477system.l2c.tags.warmup_cycle 103102985000 # Cycle when the warmup percentage was hit. 2478system.l2c.tags.occ_blocks::writebacks 6607.466111 # Average occupied blocks per requestor 2479system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.944223 # Average occupied blocks per requestor 2480system.l2c.tags.occ_blocks::cpu0.itb.walker 0.038978 # Average occupied blocks per requestor 2481system.l2c.tags.occ_blocks::cpu0.inst 7194.422354 # Average occupied blocks per requestor 2482system.l2c.tags.occ_blocks::cpu0.data 6927.905114 # Average occupied blocks per requestor 2483system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37164.228779 # Average occupied blocks per requestor 2484system.l2c.tags.occ_blocks::cpu1.inst 1475.884148 # Average occupied blocks per requestor 2485system.l2c.tags.occ_blocks::cpu1.data 3147.084233 # Average occupied blocks per requestor 2486system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2554.669060 # Average occupied blocks per requestor 2487system.l2c.tags.occ_percent::writebacks 0.100822 # Average percentage of cache occupancy 2488system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000045 # Average percentage of cache occupancy 2489system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy 2490system.l2c.tags.occ_percent::cpu0.inst 0.109778 # Average percentage of cache occupancy 2491system.l2c.tags.occ_percent::cpu0.data 0.105711 # Average percentage of cache occupancy 2492system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.567081 # Average percentage of cache occupancy 2493system.l2c.tags.occ_percent::cpu1.inst 0.022520 # Average percentage of cache occupancy 2494system.l2c.tags.occ_percent::cpu1.data 0.048021 # Average percentage of cache occupancy 2495system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.038981 # Average percentage of cache occupancy 2496system.l2c.tags.occ_percent::total 0.992960 # Average percentage of cache occupancy 2497system.l2c.tags.occ_task_id_blocks::1022 34101 # Occupied blocks per task id 2498system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id 2499system.l2c.tags.occ_task_id_blocks::1024 31263 # Occupied blocks per task id 2500system.l2c.tags.age_task_id_blocks_1022::2 163 # Occupied blocks per task id 2501system.l2c.tags.age_task_id_blocks_1022::3 4783 # Occupied blocks per task id 2502system.l2c.tags.age_task_id_blocks_1022::4 29155 # Occupied blocks per task id 2503system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id 2504system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id 2505system.l2c.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id 2506system.l2c.tags.age_task_id_blocks_1024::2 109 # Occupied blocks per task id 2507system.l2c.tags.age_task_id_blocks_1024::3 1095 # Occupied blocks per task id 2508system.l2c.tags.age_task_id_blocks_1024::4 30056 # Occupied blocks per task id 2509system.l2c.tags.occ_task_id_percent::1022 0.520340 # Percentage of cache occupancy per task id 2510system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id 2511system.l2c.tags.occ_task_id_percent::1024 0.477036 # Percentage of cache occupancy per task id 2512system.l2c.tags.tag_accesses 6098343 # Number of tag accesses 2513system.l2c.tags.data_accesses 6098343 # Number of data accesses 2514system.l2c.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 2515system.l2c.WritebackDirty_hits::writebacks 259635 # number of WritebackDirty hits 2516system.l2c.WritebackDirty_hits::total 259635 # number of WritebackDirty hits 2517system.l2c.UpgradeReq_hits::cpu0.data 39907 # number of UpgradeReq hits 2518system.l2c.UpgradeReq_hits::cpu1.data 4995 # number of UpgradeReq hits 2519system.l2c.UpgradeReq_hits::total 44902 # number of UpgradeReq hits 2520system.l2c.SCUpgradeReq_hits::cpu0.data 2353 # number of SCUpgradeReq hits 2521system.l2c.SCUpgradeReq_hits::cpu1.data 2177 # number of SCUpgradeReq hits 2522system.l2c.SCUpgradeReq_hits::total 4530 # number of SCUpgradeReq hits 2523system.l2c.ReadExReq_hits::cpu0.data 3978 # number of ReadExReq hits 2524system.l2c.ReadExReq_hits::cpu1.data 1485 # number of ReadExReq hits 2525system.l2c.ReadExReq_hits::total 5463 # number of ReadExReq hits 2526system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 146 # number of ReadSharedReq hits 2527system.l2c.ReadSharedReq_hits::cpu0.itb.walker 71 # number of ReadSharedReq hits 2528system.l2c.ReadSharedReq_hits::cpu0.inst 44179 # number of ReadSharedReq hits 2529system.l2c.ReadSharedReq_hits::cpu0.data 52512 # number of ReadSharedReq hits 2530system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 45683 # number of ReadSharedReq hits 2531system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 56 # number of ReadSharedReq hits 2532system.l2c.ReadSharedReq_hits::cpu1.itb.walker 30 # number of ReadSharedReq hits 2533system.l2c.ReadSharedReq_hits::cpu1.inst 19035 # number of ReadSharedReq hits 2534system.l2c.ReadSharedReq_hits::cpu1.data 10985 # number of ReadSharedReq hits 2535system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 5208 # number of ReadSharedReq hits 2536system.l2c.ReadSharedReq_hits::total 177905 # number of ReadSharedReq hits 2537system.l2c.demand_hits::cpu0.dtb.walker 146 # number of demand (read+write) hits 2538system.l2c.demand_hits::cpu0.itb.walker 71 # number of demand (read+write) hits 2539system.l2c.demand_hits::cpu0.inst 44179 # number of demand (read+write) hits 2540system.l2c.demand_hits::cpu0.data 56490 # number of demand (read+write) hits 2541system.l2c.demand_hits::cpu0.l2cache.prefetcher 45683 # number of demand (read+write) hits 2542system.l2c.demand_hits::cpu1.dtb.walker 56 # number of demand (read+write) hits 2543system.l2c.demand_hits::cpu1.itb.walker 30 # number of demand (read+write) hits 2544system.l2c.demand_hits::cpu1.inst 19035 # number of demand (read+write) hits 2545system.l2c.demand_hits::cpu1.data 12470 # number of demand (read+write) hits 2546system.l2c.demand_hits::cpu1.l2cache.prefetcher 5208 # number of demand (read+write) hits 2547system.l2c.demand_hits::total 183368 # number of demand (read+write) hits 2548system.l2c.overall_hits::cpu0.dtb.walker 146 # number of overall hits 2549system.l2c.overall_hits::cpu0.itb.walker 71 # number of overall hits 2550system.l2c.overall_hits::cpu0.inst 44179 # number of overall hits 2551system.l2c.overall_hits::cpu0.data 56490 # number of overall hits 2552system.l2c.overall_hits::cpu0.l2cache.prefetcher 45683 # number of overall hits 2553system.l2c.overall_hits::cpu1.dtb.walker 56 # number of overall hits 2554system.l2c.overall_hits::cpu1.itb.walker 30 # number of overall hits 2555system.l2c.overall_hits::cpu1.inst 19035 # number of overall hits 2556system.l2c.overall_hits::cpu1.data 12470 # number of overall hits 2557system.l2c.overall_hits::cpu1.l2cache.prefetcher 5208 # number of overall hits 2558system.l2c.overall_hits::total 183368 # number of overall hits 2559system.l2c.UpgradeReq_misses::cpu0.data 508 # number of UpgradeReq misses 2560system.l2c.UpgradeReq_misses::cpu1.data 339 # number of UpgradeReq misses 2561system.l2c.UpgradeReq_misses::total 847 # number of UpgradeReq misses 2562system.l2c.SCUpgradeReq_misses::cpu0.data 113 # number of SCUpgradeReq misses 2563system.l2c.SCUpgradeReq_misses::cpu1.data 106 # number of SCUpgradeReq misses 2564system.l2c.SCUpgradeReq_misses::total 219 # number of SCUpgradeReq misses 2565system.l2c.ReadExReq_misses::cpu0.data 11276 # number of ReadExReq misses 2566system.l2c.ReadExReq_misses::cpu1.data 7954 # number of ReadExReq misses 2567system.l2c.ReadExReq_misses::total 19230 # number of ReadExReq misses 2568system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 7 # number of ReadSharedReq misses 2569system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2 # number of ReadSharedReq misses 2570system.l2c.ReadSharedReq_misses::cpu0.inst 17880 # number of ReadSharedReq misses 2571system.l2c.ReadSharedReq_misses::cpu0.data 9100 # number of ReadSharedReq misses 2572system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 133915 # number of ReadSharedReq misses 2573system.l2c.ReadSharedReq_misses::cpu1.inst 2394 # number of ReadSharedReq misses 2574system.l2c.ReadSharedReq_misses::cpu1.data 952 # number of ReadSharedReq misses 2575system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 6331 # number of ReadSharedReq misses 2576system.l2c.ReadSharedReq_misses::total 170581 # number of ReadSharedReq misses 2577system.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses 2578system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses 2579system.l2c.demand_misses::cpu0.inst 17880 # number of demand (read+write) misses 2580system.l2c.demand_misses::cpu0.data 20376 # number of demand (read+write) misses 2581system.l2c.demand_misses::cpu0.l2cache.prefetcher 133915 # number of demand (read+write) misses 2582system.l2c.demand_misses::cpu1.inst 2394 # number of demand (read+write) misses 2583system.l2c.demand_misses::cpu1.data 8906 # number of demand (read+write) misses 2584system.l2c.demand_misses::cpu1.l2cache.prefetcher 6331 # number of demand (read+write) misses 2585system.l2c.demand_misses::total 189811 # number of demand (read+write) misses 2586system.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses 2587system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses 2588system.l2c.overall_misses::cpu0.inst 17880 # number of overall misses 2589system.l2c.overall_misses::cpu0.data 20376 # number of overall misses 2590system.l2c.overall_misses::cpu0.l2cache.prefetcher 133915 # number of overall misses 2591system.l2c.overall_misses::cpu1.inst 2394 # number of overall misses 2592system.l2c.overall_misses::cpu1.data 8906 # number of overall misses 2593system.l2c.overall_misses::cpu1.l2cache.prefetcher 6331 # number of overall misses 2594system.l2c.overall_misses::total 189811 # number of overall misses 2595system.l2c.UpgradeReq_miss_latency::cpu0.data 9776500 # number of UpgradeReq miss cycles 2596system.l2c.UpgradeReq_miss_latency::cpu1.data 1123500 # number of UpgradeReq miss cycles 2597system.l2c.UpgradeReq_miss_latency::total 10900000 # number of UpgradeReq miss cycles 2598system.l2c.SCUpgradeReq_miss_latency::cpu0.data 603500 # number of SCUpgradeReq miss cycles 2599system.l2c.SCUpgradeReq_miss_latency::cpu1.data 259000 # number of SCUpgradeReq miss cycles 2600system.l2c.SCUpgradeReq_miss_latency::total 862500 # number of SCUpgradeReq miss cycles 2601system.l2c.ReadExReq_miss_latency::cpu0.data 1642507500 # number of ReadExReq miss cycles 2602system.l2c.ReadExReq_miss_latency::cpu1.data 809344500 # number of ReadExReq miss cycles 2603system.l2c.ReadExReq_miss_latency::total 2451852000 # number of ReadExReq miss cycles 2604system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 1270000 # number of ReadSharedReq miss cycles 2605system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 179500 # number of ReadSharedReq miss cycles 2606system.l2c.ReadSharedReq_miss_latency::cpu0.inst 1949692500 # number of ReadSharedReq miss cycles 2607system.l2c.ReadSharedReq_miss_latency::cpu0.data 1106153000 # number of ReadSharedReq miss cycles 2608system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 16003328825 # number of ReadSharedReq miss cycles 2609system.l2c.ReadSharedReq_miss_latency::cpu1.inst 265577500 # number of ReadSharedReq miss cycles 2610system.l2c.ReadSharedReq_miss_latency::cpu1.data 121124000 # number of ReadSharedReq miss cycles 2611system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 827024607 # number of ReadSharedReq miss cycles 2612system.l2c.ReadSharedReq_miss_latency::total 20274349932 # number of ReadSharedReq miss cycles 2613system.l2c.demand_miss_latency::cpu0.dtb.walker 1270000 # number of demand (read+write) miss cycles 2614system.l2c.demand_miss_latency::cpu0.itb.walker 179500 # number of demand (read+write) miss cycles 2615system.l2c.demand_miss_latency::cpu0.inst 1949692500 # number of demand (read+write) miss cycles 2616system.l2c.demand_miss_latency::cpu0.data 2748660500 # number of demand (read+write) miss cycles 2617system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 16003328825 # number of demand (read+write) miss cycles 2618system.l2c.demand_miss_latency::cpu1.inst 265577500 # number of demand (read+write) miss cycles 2619system.l2c.demand_miss_latency::cpu1.data 930468500 # number of demand (read+write) miss cycles 2620system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 827024607 # number of demand (read+write) miss cycles 2621system.l2c.demand_miss_latency::total 22726201932 # number of demand (read+write) miss cycles 2622system.l2c.overall_miss_latency::cpu0.dtb.walker 1270000 # number of overall miss cycles 2623system.l2c.overall_miss_latency::cpu0.itb.walker 179500 # number of overall miss cycles 2624system.l2c.overall_miss_latency::cpu0.inst 1949692500 # number of overall miss cycles 2625system.l2c.overall_miss_latency::cpu0.data 2748660500 # number of overall miss cycles 2626system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 16003328825 # number of overall miss cycles 2627system.l2c.overall_miss_latency::cpu1.inst 265577500 # number of overall miss cycles 2628system.l2c.overall_miss_latency::cpu1.data 930468500 # number of overall miss cycles 2629system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 827024607 # number of overall miss cycles 2630system.l2c.overall_miss_latency::total 22726201932 # number of overall miss cycles 2631system.l2c.WritebackDirty_accesses::writebacks 259635 # number of WritebackDirty accesses(hits+misses) 2632system.l2c.WritebackDirty_accesses::total 259635 # number of WritebackDirty accesses(hits+misses) 2633system.l2c.UpgradeReq_accesses::cpu0.data 40415 # number of UpgradeReq accesses(hits+misses) 2634system.l2c.UpgradeReq_accesses::cpu1.data 5334 # number of UpgradeReq accesses(hits+misses) 2635system.l2c.UpgradeReq_accesses::total 45749 # number of UpgradeReq accesses(hits+misses) 2636system.l2c.SCUpgradeReq_accesses::cpu0.data 2466 # number of SCUpgradeReq accesses(hits+misses) 2637system.l2c.SCUpgradeReq_accesses::cpu1.data 2283 # number of SCUpgradeReq accesses(hits+misses) 2638system.l2c.SCUpgradeReq_accesses::total 4749 # number of SCUpgradeReq accesses(hits+misses) 2639system.l2c.ReadExReq_accesses::cpu0.data 15254 # number of ReadExReq accesses(hits+misses) 2640system.l2c.ReadExReq_accesses::cpu1.data 9439 # number of ReadExReq accesses(hits+misses) 2641system.l2c.ReadExReq_accesses::total 24693 # number of ReadExReq accesses(hits+misses) 2642system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 153 # number of ReadSharedReq accesses(hits+misses) 2643system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 73 # number of ReadSharedReq accesses(hits+misses) 2644system.l2c.ReadSharedReq_accesses::cpu0.inst 62059 # number of ReadSharedReq accesses(hits+misses) 2645system.l2c.ReadSharedReq_accesses::cpu0.data 61612 # number of ReadSharedReq accesses(hits+misses) 2646system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 179598 # number of ReadSharedReq accesses(hits+misses) 2647system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 56 # number of ReadSharedReq accesses(hits+misses) 2648system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 30 # number of ReadSharedReq accesses(hits+misses) 2649system.l2c.ReadSharedReq_accesses::cpu1.inst 21429 # number of ReadSharedReq accesses(hits+misses) 2650system.l2c.ReadSharedReq_accesses::cpu1.data 11937 # number of ReadSharedReq accesses(hits+misses) 2651system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 11539 # number of ReadSharedReq accesses(hits+misses) 2652system.l2c.ReadSharedReq_accesses::total 348486 # number of ReadSharedReq accesses(hits+misses) 2653system.l2c.demand_accesses::cpu0.dtb.walker 153 # number of demand (read+write) accesses 2654system.l2c.demand_accesses::cpu0.itb.walker 73 # number of demand (read+write) accesses 2655system.l2c.demand_accesses::cpu0.inst 62059 # number of demand (read+write) accesses 2656system.l2c.demand_accesses::cpu0.data 76866 # number of demand (read+write) accesses 2657system.l2c.demand_accesses::cpu0.l2cache.prefetcher 179598 # number of demand (read+write) accesses 2658system.l2c.demand_accesses::cpu1.dtb.walker 56 # number of demand (read+write) accesses 2659system.l2c.demand_accesses::cpu1.itb.walker 30 # number of demand (read+write) accesses 2660system.l2c.demand_accesses::cpu1.inst 21429 # number of demand (read+write) accesses 2661system.l2c.demand_accesses::cpu1.data 21376 # number of demand (read+write) accesses 2662system.l2c.demand_accesses::cpu1.l2cache.prefetcher 11539 # number of demand (read+write) accesses 2663system.l2c.demand_accesses::total 373179 # number of demand (read+write) accesses 2664system.l2c.overall_accesses::cpu0.dtb.walker 153 # number of overall (read+write) accesses 2665system.l2c.overall_accesses::cpu0.itb.walker 73 # number of overall (read+write) accesses 2666system.l2c.overall_accesses::cpu0.inst 62059 # number of overall (read+write) accesses 2667system.l2c.overall_accesses::cpu0.data 76866 # number of overall (read+write) accesses 2668system.l2c.overall_accesses::cpu0.l2cache.prefetcher 179598 # number of overall (read+write) accesses 2669system.l2c.overall_accesses::cpu1.dtb.walker 56 # number of overall (read+write) accesses 2670system.l2c.overall_accesses::cpu1.itb.walker 30 # number of overall (read+write) accesses 2671system.l2c.overall_accesses::cpu1.inst 21429 # number of overall (read+write) accesses 2672system.l2c.overall_accesses::cpu1.data 21376 # number of overall (read+write) accesses 2673system.l2c.overall_accesses::cpu1.l2cache.prefetcher 11539 # number of overall (read+write) accesses 2674system.l2c.overall_accesses::total 373179 # number of overall (read+write) accesses 2675system.l2c.UpgradeReq_miss_rate::cpu0.data 0.012570 # miss rate for UpgradeReq accesses 2676system.l2c.UpgradeReq_miss_rate::cpu1.data 0.063555 # miss rate for UpgradeReq accesses 2677system.l2c.UpgradeReq_miss_rate::total 0.018514 # miss rate for UpgradeReq accesses 2678system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.045823 # miss rate for SCUpgradeReq accesses 2679system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.046430 # miss rate for SCUpgradeReq accesses 2680system.l2c.SCUpgradeReq_miss_rate::total 0.046115 # miss rate for SCUpgradeReq accesses 2681system.l2c.ReadExReq_miss_rate::cpu0.data 0.739216 # miss rate for ReadExReq accesses 2682system.l2c.ReadExReq_miss_rate::cpu1.data 0.842674 # miss rate for ReadExReq accesses 2683system.l2c.ReadExReq_miss_rate::total 0.778763 # miss rate for ReadExReq accesses 2684system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.045752 # miss rate for ReadSharedReq accesses 2685system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.027397 # miss rate for ReadSharedReq accesses 2686system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.288113 # miss rate for ReadSharedReq accesses 2687system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.147699 # miss rate for ReadSharedReq accesses 2688system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.745637 # miss rate for ReadSharedReq accesses 2689system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.111718 # miss rate for ReadSharedReq accesses 2690system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.079752 # miss rate for ReadSharedReq accesses 2691system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.548661 # miss rate for ReadSharedReq accesses 2692system.l2c.ReadSharedReq_miss_rate::total 0.489492 # miss rate for ReadSharedReq accesses 2693system.l2c.demand_miss_rate::cpu0.dtb.walker 0.045752 # miss rate for demand accesses 2694system.l2c.demand_miss_rate::cpu0.itb.walker 0.027397 # miss rate for demand accesses 2695system.l2c.demand_miss_rate::cpu0.inst 0.288113 # miss rate for demand accesses 2696system.l2c.demand_miss_rate::cpu0.data 0.265085 # miss rate for demand accesses 2697system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.745637 # miss rate for demand accesses 2698system.l2c.demand_miss_rate::cpu1.inst 0.111718 # miss rate for demand accesses 2699system.l2c.demand_miss_rate::cpu1.data 0.416635 # miss rate for demand accesses 2700system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.548661 # miss rate for demand accesses 2701system.l2c.demand_miss_rate::total 0.508633 # miss rate for demand accesses 2702system.l2c.overall_miss_rate::cpu0.dtb.walker 0.045752 # miss rate for overall accesses 2703system.l2c.overall_miss_rate::cpu0.itb.walker 0.027397 # miss rate for overall accesses 2704system.l2c.overall_miss_rate::cpu0.inst 0.288113 # miss rate for overall accesses 2705system.l2c.overall_miss_rate::cpu0.data 0.265085 # miss rate for overall accesses 2706system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.745637 # miss rate for overall accesses 2707system.l2c.overall_miss_rate::cpu1.inst 0.111718 # miss rate for overall accesses 2708system.l2c.overall_miss_rate::cpu1.data 0.416635 # miss rate for overall accesses 2709system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.548661 # miss rate for overall accesses 2710system.l2c.overall_miss_rate::total 0.508633 # miss rate for overall accesses 2711system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 19245.078740 # average UpgradeReq miss latency 2712system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3314.159292 # average UpgradeReq miss latency 2713system.l2c.UpgradeReq_avg_miss_latency::total 12868.949233 # average UpgradeReq miss latency 2714system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5340.707965 # average SCUpgradeReq miss latency 2715system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2443.396226 # average SCUpgradeReq miss latency 2716system.l2c.SCUpgradeReq_avg_miss_latency::total 3938.356164 # average SCUpgradeReq miss latency 2717system.l2c.ReadExReq_avg_miss_latency::cpu0.data 145664.020929 # average ReadExReq miss latency 2718system.l2c.ReadExReq_avg_miss_latency::cpu1.data 101753.143073 # average ReadExReq miss latency 2719system.l2c.ReadExReq_avg_miss_latency::total 127501.404056 # average ReadExReq miss latency 2720system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 181428.571429 # average ReadSharedReq miss latency 2721system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 89750 # average ReadSharedReq miss latency 2722system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 109043.204698 # average ReadSharedReq miss latency 2723system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 121555.274725 # average ReadSharedReq miss latency 2724system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 119503.631595 # average ReadSharedReq miss latency 2725system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 110934.628237 # average ReadSharedReq miss latency 2726system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 127231.092437 # average ReadSharedReq miss latency 2727system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 130630.959880 # average ReadSharedReq miss latency 2728system.l2c.ReadSharedReq_avg_miss_latency::total 118854.678610 # average ReadSharedReq miss latency 2729system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 181428.571429 # average overall miss latency 2730system.l2c.demand_avg_miss_latency::cpu0.itb.walker 89750 # average overall miss latency 2731system.l2c.demand_avg_miss_latency::cpu0.inst 109043.204698 # average overall miss latency 2732system.l2c.demand_avg_miss_latency::cpu0.data 134896.962112 # average overall miss latency 2733system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 119503.631595 # average overall miss latency 2734system.l2c.demand_avg_miss_latency::cpu1.inst 110934.628237 # average overall miss latency 2735system.l2c.demand_avg_miss_latency::cpu1.data 104476.588817 # average overall miss latency 2736system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 130630.959880 # average overall miss latency 2737system.l2c.demand_avg_miss_latency::total 119730.689644 # average overall miss latency 2738system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 181428.571429 # average overall miss latency 2739system.l2c.overall_avg_miss_latency::cpu0.itb.walker 89750 # average overall miss latency 2740system.l2c.overall_avg_miss_latency::cpu0.inst 109043.204698 # average overall miss latency 2741system.l2c.overall_avg_miss_latency::cpu0.data 134896.962112 # average overall miss latency 2742system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 119503.631595 # average overall miss latency 2743system.l2c.overall_avg_miss_latency::cpu1.inst 110934.628237 # average overall miss latency 2744system.l2c.overall_avg_miss_latency::cpu1.data 104476.588817 # average overall miss latency 2745system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 130630.959880 # average overall miss latency 2746system.l2c.overall_avg_miss_latency::total 119730.689644 # average overall miss latency 2747system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2748system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2749system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 2750system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2751system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2752system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2753system.l2c.writebacks::writebacks 100785 # number of writebacks 2754system.l2c.writebacks::total 100785 # number of writebacks 2755system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 1 # number of ReadSharedReq MSHR hits 2756system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 4 # number of ReadSharedReq MSHR hits 2757system.l2c.ReadSharedReq_mshr_hits::total 5 # number of ReadSharedReq MSHR hits 2758system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits 2759system.l2c.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits 2760system.l2c.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits 2761system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits 2762system.l2c.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits 2763system.l2c.overall_mshr_hits::total 5 # number of overall MSHR hits 2764system.l2c.CleanEvict_mshr_misses::writebacks 3664 # number of CleanEvict MSHR misses 2765system.l2c.CleanEvict_mshr_misses::total 3664 # number of CleanEvict MSHR misses 2766system.l2c.UpgradeReq_mshr_misses::cpu0.data 508 # number of UpgradeReq MSHR misses 2767system.l2c.UpgradeReq_mshr_misses::cpu1.data 339 # number of UpgradeReq MSHR misses 2768system.l2c.UpgradeReq_mshr_misses::total 847 # number of UpgradeReq MSHR misses 2769system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 113 # number of SCUpgradeReq MSHR misses 2770system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 106 # number of SCUpgradeReq MSHR misses 2771system.l2c.SCUpgradeReq_mshr_misses::total 219 # number of SCUpgradeReq MSHR misses 2772system.l2c.ReadExReq_mshr_misses::cpu0.data 11276 # number of ReadExReq MSHR misses 2773system.l2c.ReadExReq_mshr_misses::cpu1.data 7954 # number of ReadExReq MSHR misses 2774system.l2c.ReadExReq_mshr_misses::total 19230 # number of ReadExReq MSHR misses 2775system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 7 # number of ReadSharedReq MSHR misses 2776system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 2 # number of ReadSharedReq MSHR misses 2777system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 17879 # number of ReadSharedReq MSHR misses 2778system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9100 # number of ReadSharedReq MSHR misses 2779system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 133915 # number of ReadSharedReq MSHR misses 2780system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2390 # number of ReadSharedReq MSHR misses 2781system.l2c.ReadSharedReq_mshr_misses::cpu1.data 952 # number of ReadSharedReq MSHR misses 2782system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 6331 # number of ReadSharedReq MSHR misses 2783system.l2c.ReadSharedReq_mshr_misses::total 170576 # number of ReadSharedReq MSHR misses 2784system.l2c.demand_mshr_misses::cpu0.dtb.walker 7 # number of demand (read+write) MSHR misses 2785system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses 2786system.l2c.demand_mshr_misses::cpu0.inst 17879 # number of demand (read+write) MSHR misses 2787system.l2c.demand_mshr_misses::cpu0.data 20376 # number of demand (read+write) MSHR misses 2788system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 133915 # number of demand (read+write) MSHR misses 2789system.l2c.demand_mshr_misses::cpu1.inst 2390 # number of demand (read+write) MSHR misses 2790system.l2c.demand_mshr_misses::cpu1.data 8906 # number of demand (read+write) MSHR misses 2791system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 6331 # number of demand (read+write) MSHR misses 2792system.l2c.demand_mshr_misses::total 189806 # number of demand (read+write) MSHR misses 2793system.l2c.overall_mshr_misses::cpu0.dtb.walker 7 # number of overall MSHR misses 2794system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses 2795system.l2c.overall_mshr_misses::cpu0.inst 17879 # number of overall MSHR misses 2796system.l2c.overall_mshr_misses::cpu0.data 20376 # number of overall MSHR misses 2797system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 133915 # number of overall MSHR misses 2798system.l2c.overall_mshr_misses::cpu1.inst 2390 # number of overall MSHR misses 2799system.l2c.overall_mshr_misses::cpu1.data 8906 # number of overall MSHR misses 2800system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 6331 # number of overall MSHR misses 2801system.l2c.overall_mshr_misses::total 189806 # number of overall MSHR misses 2802system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable 2803system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31782 # number of ReadReq MSHR uncacheable 2804system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable 2805system.l2c.ReadReq_mshr_uncacheable::cpu1.data 3082 # number of ReadReq MSHR uncacheable 2806system.l2c.ReadReq_mshr_uncacheable::total 44063 # number of ReadReq MSHR uncacheable 2807system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28454 # number of WriteReq MSHR uncacheable 2808system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2441 # number of WriteReq MSHR uncacheable 2809system.l2c.WriteReq_mshr_uncacheable::total 30895 # number of WriteReq MSHR uncacheable 2810system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses 2811system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60236 # number of overall MSHR uncacheable misses 2812system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses 2813system.l2c.overall_mshr_uncacheable_misses::cpu1.data 5523 # number of overall MSHR uncacheable misses 2814system.l2c.overall_mshr_uncacheable_misses::total 74958 # number of overall MSHR uncacheable misses 2815system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 11966500 # number of UpgradeReq MSHR miss cycles 2816system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 7400000 # number of UpgradeReq MSHR miss cycles 2817system.l2c.UpgradeReq_mshr_miss_latency::total 19366500 # number of UpgradeReq MSHR miss cycles 2818system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 2957500 # number of SCUpgradeReq MSHR miss cycles 2819system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 2539000 # number of SCUpgradeReq MSHR miss cycles 2820system.l2c.SCUpgradeReq_mshr_miss_latency::total 5496500 # number of SCUpgradeReq MSHR miss cycles 2821system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1529747500 # number of ReadExReq MSHR miss cycles 2822system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 729804500 # number of ReadExReq MSHR miss cycles 2823system.l2c.ReadExReq_mshr_miss_latency::total 2259552000 # number of ReadExReq MSHR miss cycles 2824system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 1200000 # number of ReadSharedReq MSHR miss cycles 2825system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 159500 # number of ReadSharedReq MSHR miss cycles 2826system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1770876500 # number of ReadSharedReq MSHR miss cycles 2827system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1015153000 # number of ReadSharedReq MSHR miss cycles 2828system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 14664172837 # number of ReadSharedReq MSHR miss cycles 2829system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 241454001 # number of ReadSharedReq MSHR miss cycles 2830system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 111604000 # number of ReadSharedReq MSHR miss cycles 2831system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 763713609 # number of ReadSharedReq MSHR miss cycles 2832system.l2c.ReadSharedReq_mshr_miss_latency::total 18568333447 # number of ReadSharedReq MSHR miss cycles 2833system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 1200000 # number of demand (read+write) MSHR miss cycles 2834system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 159500 # number of demand (read+write) MSHR miss cycles 2835system.l2c.demand_mshr_miss_latency::cpu0.inst 1770876500 # number of demand (read+write) MSHR miss cycles 2836system.l2c.demand_mshr_miss_latency::cpu0.data 2544900500 # number of demand (read+write) MSHR miss cycles 2837system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 14664172837 # number of demand (read+write) MSHR miss cycles 2838system.l2c.demand_mshr_miss_latency::cpu1.inst 241454001 # number of demand (read+write) MSHR miss cycles 2839system.l2c.demand_mshr_miss_latency::cpu1.data 841408500 # number of demand (read+write) MSHR miss cycles 2840system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 763713609 # number of demand (read+write) MSHR miss cycles 2841system.l2c.demand_mshr_miss_latency::total 20827885447 # number of demand (read+write) MSHR miss cycles 2842system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 1200000 # number of overall MSHR miss cycles 2843system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 159500 # number of overall MSHR miss cycles 2844system.l2c.overall_mshr_miss_latency::cpu0.inst 1770876500 # number of overall MSHR miss cycles 2845system.l2c.overall_mshr_miss_latency::cpu0.data 2544900500 # number of overall MSHR miss cycles 2846system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 14664172837 # number of overall MSHR miss cycles 2847system.l2c.overall_mshr_miss_latency::cpu1.inst 241454001 # number of overall MSHR miss cycles 2848system.l2c.overall_mshr_miss_latency::cpu1.data 841408500 # number of overall MSHR miss cycles 2849system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 763713609 # number of overall MSHR miss cycles 2850system.l2c.overall_mshr_miss_latency::total 20827885447 # number of overall MSHR miss cycles 2851system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 633244000 # number of ReadReq MSHR uncacheable cycles 2852system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5805153000 # number of ReadReq MSHR uncacheable cycles 2853system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 12555000 # number of ReadReq MSHR uncacheable cycles 2854system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 362546500 # number of ReadReq MSHR uncacheable cycles 2855system.l2c.ReadReq_mshr_uncacheable_latency::total 6813498500 # number of ReadReq MSHR uncacheable cycles 2856system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 633244000 # number of overall MSHR uncacheable cycles 2857system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5805153000 # number of overall MSHR uncacheable cycles 2858system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 12555000 # number of overall MSHR uncacheable cycles 2859system.l2c.overall_mshr_uncacheable_latency::cpu1.data 362546500 # number of overall MSHR uncacheable cycles 2860system.l2c.overall_mshr_uncacheable_latency::total 6813498500 # number of overall MSHR uncacheable cycles 2861system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 2862system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 2863system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.012570 # mshr miss rate for UpgradeReq accesses 2864system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.063555 # mshr miss rate for UpgradeReq accesses 2865system.l2c.UpgradeReq_mshr_miss_rate::total 0.018514 # mshr miss rate for UpgradeReq accesses 2866system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.045823 # mshr miss rate for SCUpgradeReq accesses 2867system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.046430 # mshr miss rate for SCUpgradeReq accesses 2868system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.046115 # mshr miss rate for SCUpgradeReq accesses 2869system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.739216 # mshr miss rate for ReadExReq accesses 2870system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.842674 # mshr miss rate for ReadExReq accesses 2871system.l2c.ReadExReq_mshr_miss_rate::total 0.778763 # mshr miss rate for ReadExReq accesses 2872system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.045752 # mshr miss rate for ReadSharedReq accesses 2873system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.027397 # mshr miss rate for ReadSharedReq accesses 2874system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.288097 # mshr miss rate for ReadSharedReq accesses 2875system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.147699 # mshr miss rate for ReadSharedReq accesses 2876system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.745637 # mshr miss rate for ReadSharedReq accesses 2877system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.111531 # mshr miss rate for ReadSharedReq accesses 2878system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.079752 # mshr miss rate for ReadSharedReq accesses 2879system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.548661 # mshr miss rate for ReadSharedReq accesses 2880system.l2c.ReadSharedReq_mshr_miss_rate::total 0.489477 # mshr miss rate for ReadSharedReq accesses 2881system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.045752 # mshr miss rate for demand accesses 2882system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.027397 # mshr miss rate for demand accesses 2883system.l2c.demand_mshr_miss_rate::cpu0.inst 0.288097 # mshr miss rate for demand accesses 2884system.l2c.demand_mshr_miss_rate::cpu0.data 0.265085 # mshr miss rate for demand accesses 2885system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.745637 # mshr miss rate for demand accesses 2886system.l2c.demand_mshr_miss_rate::cpu1.inst 0.111531 # mshr miss rate for demand accesses 2887system.l2c.demand_mshr_miss_rate::cpu1.data 0.416635 # mshr miss rate for demand accesses 2888system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.548661 # mshr miss rate for demand accesses 2889system.l2c.demand_mshr_miss_rate::total 0.508619 # mshr miss rate for demand accesses 2890system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.045752 # mshr miss rate for overall accesses 2891system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.027397 # mshr miss rate for overall accesses 2892system.l2c.overall_mshr_miss_rate::cpu0.inst 0.288097 # mshr miss rate for overall accesses 2893system.l2c.overall_mshr_miss_rate::cpu0.data 0.265085 # mshr miss rate for overall accesses 2894system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.745637 # mshr miss rate for overall accesses 2895system.l2c.overall_mshr_miss_rate::cpu1.inst 0.111531 # mshr miss rate for overall accesses 2896system.l2c.overall_mshr_miss_rate::cpu1.data 0.416635 # mshr miss rate for overall accesses 2897system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.548661 # mshr miss rate for overall accesses 2898system.l2c.overall_mshr_miss_rate::total 0.508619 # mshr miss rate for overall accesses 2899system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23556.102362 # average UpgradeReq mshr miss latency 2900system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21828.908555 # average UpgradeReq mshr miss latency 2901system.l2c.UpgradeReq_avg_mshr_miss_latency::total 22864.817001 # average UpgradeReq mshr miss latency 2902system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26172.566372 # average SCUpgradeReq mshr miss latency 2903system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 23952.830189 # average SCUpgradeReq mshr miss latency 2904system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25098.173516 # average SCUpgradeReq mshr miss latency 2905system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 135664.020929 # average ReadExReq mshr miss latency 2906system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 91753.143073 # average ReadExReq mshr miss latency 2907system.l2c.ReadExReq_avg_mshr_miss_latency::total 117501.404056 # average ReadExReq mshr miss latency 2908system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 171428.571429 # average ReadSharedReq mshr miss latency 2909system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 79750 # average ReadSharedReq mshr miss latency 2910system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 99047.849432 # average ReadSharedReq mshr miss latency 2911system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 111555.274725 # average ReadSharedReq mshr miss latency 2912system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109503.586880 # average ReadSharedReq mshr miss latency 2913system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 101026.778661 # average ReadSharedReq mshr miss latency 2914system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 117231.092437 # average ReadSharedReq mshr miss latency 2915system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 120630.802243 # average ReadSharedReq mshr miss latency 2916system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 108856.658891 # average ReadSharedReq mshr miss latency 2917system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 171428.571429 # average overall mshr miss latency 2918system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 79750 # average overall mshr miss latency 2919system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 99047.849432 # average overall mshr miss latency 2920system.l2c.demand_avg_mshr_miss_latency::cpu0.data 124896.962112 # average overall mshr miss latency 2921system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109503.586880 # average overall mshr miss latency 2922system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 101026.778661 # average overall mshr miss latency 2923system.l2c.demand_avg_mshr_miss_latency::cpu1.data 94476.588817 # average overall mshr miss latency 2924system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 120630.802243 # average overall mshr miss latency 2925system.l2c.demand_avg_mshr_miss_latency::total 109732.492371 # average overall mshr miss latency 2926system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 171428.571429 # average overall mshr miss latency 2927system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 79750 # average overall mshr miss latency 2928system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 99047.849432 # average overall mshr miss latency 2929system.l2c.overall_avg_mshr_miss_latency::cpu0.data 124896.962112 # average overall mshr miss latency 2930system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109503.586880 # average overall mshr miss latency 2931system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 101026.778661 # average overall mshr miss latency 2932system.l2c.overall_avg_mshr_miss_latency::cpu1.data 94476.588817 # average overall mshr miss latency 2933system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 120630.802243 # average overall mshr miss latency 2934system.l2c.overall_avg_mshr_miss_latency::total 109732.492371 # average overall mshr miss latency 2935system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 70188.871647 # average ReadReq mshr uncacheable latency 2936system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182655.370965 # average ReadReq mshr uncacheable latency 2937system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 70932.203390 # average ReadReq mshr uncacheable latency 2938system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117633.517197 # average ReadReq mshr uncacheable latency 2939system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 154630.835395 # average ReadReq mshr uncacheable latency 2940system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 70188.871647 # average overall mshr uncacheable latency 2941system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96373.480975 # average overall mshr uncacheable latency 2942system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 70932.203390 # average overall mshr uncacheable latency 2943system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 65643.038204 # average overall mshr uncacheable latency 2944system.l2c.overall_avg_mshr_uncacheable_latency::total 90897.549294 # average overall mshr uncacheable latency 2945system.membus.snoop_filter.tot_requests 503139 # Total number of requests made to the snoop filter. 2946system.membus.snoop_filter.hit_single_requests 282937 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2947system.membus.snoop_filter.hit_multi_requests 589 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2948system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 2949system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2950system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2951system.membus.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 2952system.membus.trans_dist::ReadReq 44063 # Transaction distribution 2953system.membus.trans_dist::ReadResp 214894 # Transaction distribution 2954system.membus.trans_dist::WriteReq 30895 # Transaction distribution 2955system.membus.trans_dist::WriteResp 30895 # Transaction distribution 2956system.membus.trans_dist::WritebackDirty 136975 # Transaction distribution 2957system.membus.trans_dist::CleanEvict 16276 # Transaction distribution 2958system.membus.trans_dist::UpgradeReq 64763 # Transaction distribution 2959system.membus.trans_dist::SCUpgradeReq 38177 # Transaction distribution 2960system.membus.trans_dist::UpgradeResp 17 # Transaction distribution 2961system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution 2962system.membus.trans_dist::ReadExReq 39789 # Transaction distribution 2963system.membus.trans_dist::ReadExResp 19204 # Transaction distribution 2964system.membus.trans_dist::ReadSharedReq 170831 # Transaction distribution 2965system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 2966system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107916 # Packet count per connected master and slave (bytes) 2967system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) 2968system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13664 # Packet count per connected master and slave (bytes) 2969system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 647846 # Packet count per connected master and slave (bytes) 2970system.membus.pkt_count_system.l2c.mem_side::total 769460 # Packet count per connected master and slave (bytes) 2971system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72939 # Packet count per connected master and slave (bytes) 2972system.membus.pkt_count_system.iocache.mem_side::total 72939 # Packet count per connected master and slave (bytes) 2973system.membus.pkt_count::total 842399 # Packet count per connected master and slave (bytes) 2974system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162796 # Cumulative packet size per connected master and slave (bytes) 2975system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) 2976system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27328 # Cumulative packet size per connected master and slave (bytes) 2977system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18630604 # Cumulative packet size per connected master and slave (bytes) 2978system.membus.pkt_size_system.l2c.mem_side::total 18820796 # Cumulative packet size per connected master and slave (bytes) 2979system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) 2980system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) 2981system.membus.pkt_size::total 21137916 # Cumulative packet size per connected master and slave (bytes) 2982system.membus.snoops 123039 # Total snoops (count) 2983system.membus.snoopTraffic 37632 # Total snoop traffic (bytes) 2984system.membus.snoop_fanout::samples 424743 # Request fanout histogram 2985system.membus.snoop_fanout::mean 0.012198 # Request fanout histogram 2986system.membus.snoop_fanout::stdev 0.109769 # Request fanout histogram 2987system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2988system.membus.snoop_fanout::0 419562 98.78% 98.78% # Request fanout histogram 2989system.membus.snoop_fanout::1 5181 1.22% 100.00% # Request fanout histogram 2990system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 2991system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2992system.membus.snoop_fanout::min_value 0 # Request fanout histogram 2993system.membus.snoop_fanout::max_value 1 # Request fanout histogram 2994system.membus.snoop_fanout::total 424743 # Request fanout histogram 2995system.membus.reqLayer0.occupancy 88158500 # Layer occupancy (ticks) 2996system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 2997system.membus.reqLayer1.occupancy 19000 # Layer occupancy (ticks) 2998system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 2999system.membus.reqLayer2.occupancy 11394500 # Layer occupancy (ticks) 3000system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 3001system.membus.reqLayer5.occupancy 971210962 # Layer occupancy (ticks) 3002system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 3003system.membus.respLayer2.occupancy 1112716909 # Layer occupancy (ticks) 3004system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 3005system.membus.respLayer3.occupancy 1441377 # Layer occupancy (ticks) 3006system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 3007system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 3008system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 3009system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 3010system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 3011system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 3012system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 3013system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 3014system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 3015system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 3016system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 3017system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 3018system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 3019system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 3020system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 3021system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 3022system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3023system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3024system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3025system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3026system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3027system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 3028system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 3029system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 3030system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 3031system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 3032system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 3033system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 3034system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 3035system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 3036system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 3037system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 3038system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 3039system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 3040system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 3041system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 3042system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 3043system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 3044system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 3045system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 3046system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3047system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3048system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 3049system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3050system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 3051system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 3052system.realview.ethernet.droppedPackets 0 # number of packets dropped 3053system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 3054system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 3055system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 3056system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 3057system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 3058system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 3059system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 3060system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 3061system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 3062system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 3063system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 3064system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 3065system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 3066system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 3067system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 3068system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 3069system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 3070system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 3071system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 3072system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 3073system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 3074system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 3075system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 3076system.toL2Bus.snoop_filter.tot_requests 1012483 # Total number of requests made to the snoop filter. 3077system.toL2Bus.snoop_filter.hit_single_requests 538775 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3078system.toL2Bus.snoop_filter.hit_multi_requests 174846 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3079system.toL2Bus.snoop_filter.tot_snoops 29019 # Total number of snoops made to the snoop filter. 3080system.toL2Bus.snoop_filter.hit_single_snoops 27944 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3081system.toL2Bus.snoop_filter.hit_multi_snoops 1075 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3082system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states 3083system.toL2Bus.trans_dist::ReadReq 44066 # Transaction distribution 3084system.toL2Bus.trans_dist::ReadResp 511105 # Transaction distribution 3085system.toL2Bus.trans_dist::WriteReq 30895 # Transaction distribution 3086system.toL2Bus.trans_dist::WriteResp 30895 # Transaction distribution 3087system.toL2Bus.trans_dist::WritebackDirty 360420 # Transaction distribution 3088system.toL2Bus.trans_dist::CleanEvict 118997 # Transaction distribution 3089system.toL2Bus.trans_dist::UpgradeReq 109639 # Transaction distribution 3090system.toL2Bus.trans_dist::SCUpgradeReq 42707 # Transaction distribution 3091system.toL2Bus.trans_dist::UpgradeResp 152346 # Transaction distribution 3092system.toL2Bus.trans_dist::SCUpgradeFailReq 77 # Transaction distribution 3093system.toL2Bus.trans_dist::UpgradeFailResp 77 # Transaction distribution 3094system.toL2Bus.trans_dist::ReadExReq 50919 # Transaction distribution 3095system.toL2Bus.trans_dist::ReadExResp 50919 # Transaction distribution 3096system.toL2Bus.trans_dist::ReadSharedReq 467041 # Transaction distribution 3097system.toL2Bus.trans_dist::InvalidateReq 4574 # Transaction distribution 3098system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1269868 # Packet count per connected master and slave (bytes) 3099system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 316423 # Packet count per connected master and slave (bytes) 3100system.toL2Bus.pkt_count::total 1586291 # Packet count per connected master and slave (bytes) 3101system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 35149508 # Cumulative packet size per connected master and slave (bytes) 3102system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5612856 # Cumulative packet size per connected master and slave (bytes) 3103system.toL2Bus.pkt_size::total 40762364 # Cumulative packet size per connected master and slave (bytes) 3104system.toL2Bus.snoops 388626 # Total snoops (count) 3105system.toL2Bus.snoopTraffic 15721036 # Total snoop traffic (bytes) 3106system.toL2Bus.snoop_fanout::samples 887021 # Request fanout histogram 3107system.toL2Bus.snoop_fanout::mean 0.395992 # Request fanout histogram 3108system.toL2Bus.snoop_fanout::stdev 0.491535 # Request fanout histogram 3109system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3110system.toL2Bus.snoop_fanout::0 536843 60.52% 60.52% # Request fanout histogram 3111system.toL2Bus.snoop_fanout::1 349103 39.36% 99.88% # Request fanout histogram 3112system.toL2Bus.snoop_fanout::2 1075 0.12% 100.00% # Request fanout histogram 3113system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3114system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 3115system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 3116system.toL2Bus.snoop_fanout::total 887021 # Request fanout histogram 3117system.toL2Bus.reqLayer0.occupancy 892902016 # Layer occupancy (ticks) 3118system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 3119system.toL2Bus.snoopLayer0.occupancy 360623 # Layer occupancy (ticks) 3120system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3121system.toL2Bus.respLayer0.occupancy 675868420 # Layer occupancy (ticks) 3122system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3123system.toL2Bus.respLayer1.occupancy 239041660 # Layer occupancy (ticks) 3124system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3125 3126---------- End Simulation Statistics ---------- 3127