stats.txt revision 11356:a80884911971
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.871806 # Number of seconds simulated 4sim_ticks 2871806231000 # Number of ticks simulated 5final_tick 2871806231000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 937604 # Simulator instruction rate (inst/s) 8host_op_rate 1134083 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 20478123685 # Simulator tick rate (ticks/s) 10host_mem_usage 614632 # Number of bytes of host memory used 11host_seconds 140.24 # Real time elapsed on the host 12sim_insts 131483712 # Number of instructions simulated 13sim_ops 159036662 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 384 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 1158756 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 1268260 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 8634112 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.inst 151380 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.data 543380 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.l2cache.prefetcher 351296 # Number of bytes read from this memory 24system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 25system.physmem.bytes_read::total 12108656 # Number of bytes read from this memory 26system.physmem.bytes_inst_read::cpu0.inst 1158756 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::cpu1.inst 151380 # Number of instructions bytes read from this memory 28system.physmem.bytes_inst_read::total 1310136 # Number of instructions bytes read from this memory 29system.physmem.bytes_written::writebacks 8536192 # Number of bytes written to this memory 30system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory 31system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory 32system.physmem.bytes_written::total 8553756 # Number of bytes written to this memory 33system.physmem.num_reads::cpu0.dtb.walker 6 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu0.inst 26559 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.data 20336 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.l2cache.prefetcher 134908 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu1.inst 2520 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu1.data 8511 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.l2cache.prefetcher 5489 # Number of read requests responded to by this memory 41system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 42system.physmem.num_reads::total 198346 # Number of read requests responded to by this memory 43system.physmem.num_writes::writebacks 133378 # Number of write requests responded to by this memory 44system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory 45system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory 46system.physmem.num_writes::total 137769 # Number of write requests responded to by this memory 47system.physmem.bw_read::cpu0.dtb.walker 134 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu0.inst 403494 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu0.data 441625 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu0.l2cache.prefetcher 3006509 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu1.inst 52712 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu1.data 189212 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu1.l2cache.prefetcher 122326 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::realview.ide 334 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::total 4216390 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_inst_read::cpu0.inst 403494 # Instruction read bandwidth from this memory (bytes/s) 58system.physmem.bw_inst_read::cpu1.inst 52712 # Instruction read bandwidth from this memory (bytes/s) 59system.physmem.bw_inst_read::total 456206 # Instruction read bandwidth from this memory (bytes/s) 60system.physmem.bw_write::writebacks 2972412 # Write bandwidth from this memory (bytes/s) 61system.physmem.bw_write::cpu0.data 6102 # Write bandwidth from this memory (bytes/s) 62system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) 63system.physmem.bw_write::total 2978528 # Write bandwidth from this memory (bytes/s) 64system.physmem.bw_total::writebacks 2972412 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::cpu0.dtb.walker 134 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu0.inst 403494 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::cpu0.data 447727 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::cpu0.l2cache.prefetcher 3006509 # Total bandwidth to/from this memory (bytes/s) 70system.physmem.bw_total::cpu1.inst 52712 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu1.data 189226 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu1.l2cache.prefetcher 122326 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::realview.ide 334 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::total 7194919 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.readReqs 198346 # Number of read requests accepted 76system.physmem.writeReqs 137769 # Number of write requests accepted 77system.physmem.readBursts 198346 # Number of DRAM read bursts, including those serviced by the write queue 78system.physmem.writeBursts 137769 # Number of DRAM write bursts, including those merged in the write queue 79system.physmem.bytesReadDRAM 12684736 # Total number of bytes read from DRAM 80system.physmem.bytesReadWrQ 9408 # Total number of bytes read from write queue 81system.physmem.bytesWritten 8566272 # Total number of bytes written to DRAM 82system.physmem.bytesReadSys 12108656 # Total read bytes from the system interface side 83system.physmem.bytesWrittenSys 8553756 # Total written bytes from the system interface side 84system.physmem.servicedByWrQ 147 # Number of DRAM read bursts serviced by the write queue 85system.physmem.mergedWrBursts 3895 # Number of DRAM write bursts merged with an existing one 86system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 87system.physmem.perBankRdBursts::0 11680 # Per bank write bursts 88system.physmem.perBankRdBursts::1 11729 # Per bank write bursts 89system.physmem.perBankRdBursts::2 12020 # Per bank write bursts 90system.physmem.perBankRdBursts::3 11779 # Per bank write bursts 91system.physmem.perBankRdBursts::4 20245 # Per bank write bursts 92system.physmem.perBankRdBursts::5 11824 # Per bank write bursts 93system.physmem.perBankRdBursts::6 12521 # Per bank write bursts 94system.physmem.perBankRdBursts::7 12818 # Per bank write bursts 95system.physmem.perBankRdBursts::8 12201 # Per bank write bursts 96system.physmem.perBankRdBursts::9 12749 # Per bank write bursts 97system.physmem.perBankRdBursts::10 11883 # Per bank write bursts 98system.physmem.perBankRdBursts::11 11375 # Per bank write bursts 99system.physmem.perBankRdBursts::12 11512 # Per bank write bursts 100system.physmem.perBankRdBursts::13 11780 # Per bank write bursts 101system.physmem.perBankRdBursts::14 10986 # Per bank write bursts 102system.physmem.perBankRdBursts::15 11097 # Per bank write bursts 103system.physmem.perBankWrBursts::0 8306 # Per bank write bursts 104system.physmem.perBankWrBursts::1 8598 # Per bank write bursts 105system.physmem.perBankWrBursts::2 8866 # Per bank write bursts 106system.physmem.perBankWrBursts::3 8386 # Per bank write bursts 107system.physmem.perBankWrBursts::4 7973 # Per bank write bursts 108system.physmem.perBankWrBursts::5 8273 # Per bank write bursts 109system.physmem.perBankWrBursts::6 8936 # Per bank write bursts 110system.physmem.perBankWrBursts::7 8926 # Per bank write bursts 111system.physmem.perBankWrBursts::8 8615 # Per bank write bursts 112system.physmem.perBankWrBursts::9 9047 # Per bank write bursts 113system.physmem.perBankWrBursts::10 8395 # Per bank write bursts 114system.physmem.perBankWrBursts::11 8237 # Per bank write bursts 115system.physmem.perBankWrBursts::12 8245 # Per bank write bursts 116system.physmem.perBankWrBursts::13 7999 # Per bank write bursts 117system.physmem.perBankWrBursts::14 7661 # Per bank write bursts 118system.physmem.perBankWrBursts::15 7385 # Per bank write bursts 119system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 120system.physmem.numWrRetry 23 # Number of times write queue was full causing retry 121system.physmem.totGap 2871805791000 # Total gap between requests 122system.physmem.readPktSize::0 0 # Read request sizes (log2) 123system.physmem.readPktSize::1 0 # Read request sizes (log2) 124system.physmem.readPktSize::2 9732 # Read request sizes (log2) 125system.physmem.readPktSize::3 28 # Read request sizes (log2) 126system.physmem.readPktSize::4 0 # Read request sizes (log2) 127system.physmem.readPktSize::5 0 # Read request sizes (log2) 128system.physmem.readPktSize::6 188586 # Read request sizes (log2) 129system.physmem.writePktSize::0 0 # Write request sizes (log2) 130system.physmem.writePktSize::1 0 # Write request sizes (log2) 131system.physmem.writePktSize::2 4391 # Write request sizes (log2) 132system.physmem.writePktSize::3 0 # Write request sizes (log2) 133system.physmem.writePktSize::4 0 # Write request sizes (log2) 134system.physmem.writePktSize::5 0 # Write request sizes (log2) 135system.physmem.writePktSize::6 133378 # Write request sizes (log2) 136system.physmem.rdQLenPdf::0 139268 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::1 15633 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::2 10299 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::3 8733 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::4 6919 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::5 5418 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::6 4551 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::7 3807 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::8 3363 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::9 88 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::10 59 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::11 39 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::12 13 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::13 7 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::14 2 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 168system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::15 2693 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::16 3746 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::17 5145 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::18 5069 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::19 6471 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::20 6514 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::21 6841 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::22 7304 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::23 7920 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::24 7786 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::25 8498 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::26 9425 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::27 8154 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::28 8749 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::29 10972 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::30 8700 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::31 7710 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::32 7561 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::33 1075 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::34 375 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::35 275 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::36 211 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::37 203 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::38 176 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::39 136 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::40 112 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::41 129 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::42 120 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::43 113 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::44 150 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::45 141 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::46 83 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::47 99 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::48 84 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::49 93 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::50 124 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::51 88 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::52 115 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::53 92 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::54 65 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::55 64 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::56 80 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::57 70 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::58 54 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::59 46 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::60 53 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::61 63 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::62 31 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::63 81 # What write queue length does an incoming req see 232system.physmem.bytesPerActivate::samples 87931 # Bytes accessed per row activation 233system.physmem.bytesPerActivate::mean 241.677497 # Bytes accessed per row activation 234system.physmem.bytesPerActivate::gmean 136.342742 # Bytes accessed per row activation 235system.physmem.bytesPerActivate::stdev 304.582310 # Bytes accessed per row activation 236system.physmem.bytesPerActivate::0-127 46815 53.24% 53.24% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::128-255 17415 19.81% 73.05% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::256-383 6112 6.95% 80.00% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::384-511 3386 3.85% 83.85% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::512-639 2470 2.81% 86.66% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::640-767 1473 1.68% 88.33% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::768-895 853 0.97% 89.30% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::896-1023 929 1.06% 90.36% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::1024-1151 8478 9.64% 100.00% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::total 87931 # Bytes accessed per row activation 246system.physmem.rdPerTurnAround::samples 6424 # Reads before turning the bus around for writes 247system.physmem.rdPerTurnAround::mean 30.852584 # Reads before turning the bus around for writes 248system.physmem.rdPerTurnAround::stdev 590.448326 # Reads before turning the bus around for writes 249system.physmem.rdPerTurnAround::0-2047 6422 99.97% 99.97% # Reads before turning the bus around for writes 250system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes 251system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes 252system.physmem.rdPerTurnAround::total 6424 # Reads before turning the bus around for writes 253system.physmem.wrPerTurnAround::samples 6424 # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::mean 20.835616 # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::gmean 18.963518 # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::stdev 13.817635 # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::16-19 5349 83.27% 83.27% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::20-23 441 6.86% 90.13% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::24-27 73 1.14% 91.27% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::28-31 47 0.73% 92.00% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::32-35 38 0.59% 92.59% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::36-39 25 0.39% 92.98% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::40-43 52 0.81% 93.79% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::44-47 19 0.30% 94.08% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::48-51 115 1.79% 95.87% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::52-55 11 0.17% 96.05% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::56-59 10 0.16% 96.20% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::60-63 10 0.16% 96.36% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::64-67 81 1.26% 97.62% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::68-71 9 0.14% 97.76% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::72-75 4 0.06% 97.82% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::76-79 28 0.44% 98.26% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::80-83 75 1.17% 99.42% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::84-87 5 0.08% 99.50% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::88-91 3 0.05% 99.55% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::92-95 3 0.05% 99.60% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::108-111 2 0.03% 99.63% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::120-123 1 0.02% 99.64% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::128-131 10 0.16% 99.80% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::132-135 1 0.02% 99.81% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::140-143 1 0.02% 99.83% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::144-147 7 0.11% 99.94% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::148-151 1 0.02% 99.95% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::156-159 1 0.02% 99.97% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::176-179 2 0.03% 100.00% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::total 6424 # Writes before turning the bus around for reads 287system.physmem.totQLat 4482627455 # Total ticks spent queuing 288system.physmem.totMemAccLat 8198858705 # Total ticks spent from burst creation until serviced by the DRAM 289system.physmem.totBusLat 990995000 # Total ticks spent in databus transfers 290system.physmem.avgQLat 22616.80 # Average queueing delay per DRAM burst 291system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 292system.physmem.avgMemAccLat 41366.80 # Average memory access latency per DRAM burst 293system.physmem.avgRdBW 4.42 # Average DRAM read bandwidth in MiByte/s 294system.physmem.avgWrBW 2.98 # Average achieved write bandwidth in MiByte/s 295system.physmem.avgRdBWSys 4.22 # Average system read bandwidth in MiByte/s 296system.physmem.avgWrBWSys 2.98 # Average system write bandwidth in MiByte/s 297system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 298system.physmem.busUtil 0.06 # Data bus utilization in percentage 299system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 300system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 301system.physmem.avgRdQLen 1.19 # Average read queue length when enqueuing 302system.physmem.avgWrQLen 24.41 # Average write queue length when enqueuing 303system.physmem.readRowHits 165480 # Number of row buffer hits during reads 304system.physmem.writeRowHits 78635 # Number of row buffer hits during writes 305system.physmem.readRowHitRate 83.49 # Row buffer hit rate for reads 306system.physmem.writeRowHitRate 58.74 # Row buffer hit rate for writes 307system.physmem.avgGap 8544116.72 # Average gap between requests 308system.physmem.pageHitRate 73.51 # Row buffer hit rate, read and write combined 309system.physmem_0.actEnergy 342929160 # Energy for activate commands per rank (pJ) 310system.physmem_0.preEnergy 187114125 # Energy for precharge commands per rank (pJ) 311system.physmem_0.readEnergy 816004800 # Energy for read commands per rank (pJ) 312system.physmem_0.writeEnergy 442350720 # Energy for write commands per rank (pJ) 313system.physmem_0.refreshEnergy 187572184800 # Energy for refresh commands per rank (pJ) 314system.physmem_0.actBackEnergy 85984866225 # Energy for active background per rank (pJ) 315system.physmem_0.preBackEnergy 1647656379000 # Energy for precharge background per rank (pJ) 316system.physmem_0.totalEnergy 1923001828830 # Total energy per rank (pJ) 317system.physmem_0.averagePower 669.614852 # Core power per rank (mW) 318system.physmem_0.memoryStateTime::IDLE 2740877422516 # Time in different power states 319system.physmem_0.memoryStateTime::REF 95895800000 # Time in different power states 320system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 321system.physmem_0.memoryStateTime::ACT 35029624984 # Time in different power states 322system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 323system.physmem_1.actEnergy 321829200 # Energy for activate commands per rank (pJ) 324system.physmem_1.preEnergy 175601250 # Energy for precharge commands per rank (pJ) 325system.physmem_1.readEnergy 729939600 # Energy for read commands per rank (pJ) 326system.physmem_1.writeEnergy 424984320 # Energy for write commands per rank (pJ) 327system.physmem_1.refreshEnergy 187572184800 # Energy for refresh commands per rank (pJ) 328system.physmem_1.actBackEnergy 85018582845 # Energy for active background per rank (pJ) 329system.physmem_1.preBackEnergy 1648503996000 # Energy for precharge background per rank (pJ) 330system.physmem_1.totalEnergy 1922747118015 # Total energy per rank (pJ) 331system.physmem_1.averagePower 669.526158 # Core power per rank (mW) 332system.physmem_1.memoryStateTime::IDLE 2742296701194 # Time in different power states 333system.physmem_1.memoryStateTime::REF 95895800000 # Time in different power states 334system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 335system.physmem_1.memoryStateTime::ACT 33613567806 # Time in different power states 336system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 337system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 338system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 339system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 340system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 341system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 342system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 343system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 344system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 345system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 346system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) 347system.realview.nvmem.bw_read::cpu1.inst 17 # Total read bandwidth from this memory (bytes/s) 348system.realview.nvmem.bw_read::total 24 # Total read bandwidth from this memory (bytes/s) 349system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) 350system.realview.nvmem.bw_inst_read::cpu1.inst 17 # Instruction read bandwidth from this memory (bytes/s) 351system.realview.nvmem.bw_inst_read::total 24 # Instruction read bandwidth from this memory (bytes/s) 352system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) 353system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s) 354system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s) 355system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 356system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 357system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 358system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 359system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 360system.cf0.dma_write_txs 631 # Number of DMA write transactions. 361system.cpu_clk_domain.clock 500 # Clock period in ticks 362system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 363system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 364system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 365system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 366system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 367system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 368system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 369system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 370system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 371system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 372system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 373system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 374system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 375system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 376system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 377system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 378system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 379system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 380system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 381system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 382system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 383system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 384system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 385system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 386system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 387system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 388system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 389system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 390system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 391system.cpu0.dtb.walker.walks 8733 # Table walker walks requested 392system.cpu0.dtb.walker.walksShort 8733 # Table walker walks initiated with short descriptors 393system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1652 # Level at which table walker walks with short descriptors terminate 394system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 7081 # Level at which table walker walks with short descriptors terminate 395system.cpu0.dtb.walker.walkWaitTime::samples 8733 # Table walker wait (enqueue to first request) latency 396system.cpu0.dtb.walker.walkWaitTime::0 8733 100.00% 100.00% # Table walker wait (enqueue to first request) latency 397system.cpu0.dtb.walker.walkWaitTime::total 8733 # Table walker wait (enqueue to first request) latency 398system.cpu0.dtb.walker.walkCompletionTime::samples 7215 # Table walker service (enqueue to completion) latency 399system.cpu0.dtb.walker.walkCompletionTime::mean 12160.221760 # Table walker service (enqueue to completion) latency 400system.cpu0.dtb.walker.walkCompletionTime::gmean 11349.326630 # Table walker service (enqueue to completion) latency 401system.cpu0.dtb.walker.walkCompletionTime::stdev 6137.175819 # Table walker service (enqueue to completion) latency 402system.cpu0.dtb.walker.walkCompletionTime::0-32767 7184 99.57% 99.57% # Table walker service (enqueue to completion) latency 403system.cpu0.dtb.walker.walkCompletionTime::32768-65535 27 0.37% 99.94% # Table walker service (enqueue to completion) latency 404system.cpu0.dtb.walker.walkCompletionTime::131072-163839 3 0.04% 99.99% # Table walker service (enqueue to completion) latency 405system.cpu0.dtb.walker.walkCompletionTime::294912-327679 1 0.01% 100.00% # Table walker service (enqueue to completion) latency 406system.cpu0.dtb.walker.walkCompletionTime::total 7215 # Table walker service (enqueue to completion) latency 407system.cpu0.dtb.walker.walksPending::samples 1809726500 # Table walker pending requests distribution 408system.cpu0.dtb.walker.walksPending::0 1809726500 100.00% 100.00% # Table walker pending requests distribution 409system.cpu0.dtb.walker.walksPending::total 1809726500 # Table walker pending requests distribution 410system.cpu0.dtb.walker.walkPageSizes::4K 5610 77.75% 77.75% # Table walker page sizes translated 411system.cpu0.dtb.walker.walkPageSizes::1M 1605 22.25% 100.00% # Table walker page sizes translated 412system.cpu0.dtb.walker.walkPageSizes::total 7215 # Table walker page sizes translated 413system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 8733 # Table walker requests started/completed, data/inst 414system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 415system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 8733 # Table walker requests started/completed, data/inst 416system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7215 # Table walker requests started/completed, data/inst 417system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 418system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7215 # Table walker requests started/completed, data/inst 419system.cpu0.dtb.walker.walkRequestOrigin::total 15948 # Table walker requests started/completed, data/inst 420system.cpu0.dtb.inst_hits 0 # ITB inst hits 421system.cpu0.dtb.inst_misses 0 # ITB inst misses 422system.cpu0.dtb.read_hits 25746594 # DTB read hits 423system.cpu0.dtb.read_misses 7520 # DTB read misses 424system.cpu0.dtb.write_hits 19247313 # DTB write hits 425system.cpu0.dtb.write_misses 1213 # DTB write misses 426system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 427system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 428system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 429system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 430system.cpu0.dtb.flush_entries 3753 # Number of entries that have been flushed from TLB 431system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 432system.cpu0.dtb.prefetch_faults 1863 # Number of TLB faults due to prefetch 433system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 434system.cpu0.dtb.perms_faults 321 # Number of TLB faults due to permissions restrictions 435system.cpu0.dtb.read_accesses 25754114 # DTB read accesses 436system.cpu0.dtb.write_accesses 19248526 # DTB write accesses 437system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 438system.cpu0.dtb.hits 44993907 # DTB hits 439system.cpu0.dtb.misses 8733 # DTB misses 440system.cpu0.dtb.accesses 45002640 # DTB accesses 441system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 442system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 443system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 444system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 445system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 446system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 447system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 448system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 449system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 450system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 451system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 452system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 453system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 454system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 455system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 456system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 457system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 458system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 459system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 460system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 461system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 462system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 463system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 464system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 465system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 466system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 467system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 468system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 469system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 470system.cpu0.itb.walker.walks 3674 # Table walker walks requested 471system.cpu0.itb.walker.walksShort 3674 # Table walker walks initiated with short descriptors 472system.cpu0.itb.walker.walksShortTerminationLevel::Level1 320 # Level at which table walker walks with short descriptors terminate 473system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3354 # Level at which table walker walks with short descriptors terminate 474system.cpu0.itb.walker.walkWaitTime::samples 3674 # Table walker wait (enqueue to first request) latency 475system.cpu0.itb.walker.walkWaitTime::0 3674 100.00% 100.00% # Table walker wait (enqueue to first request) latency 476system.cpu0.itb.walker.walkWaitTime::total 3674 # Table walker wait (enqueue to first request) latency 477system.cpu0.itb.walker.walkCompletionTime::samples 2576 # Table walker service (enqueue to completion) latency 478system.cpu0.itb.walker.walkCompletionTime::mean 12667.119565 # Table walker service (enqueue to completion) latency 479system.cpu0.itb.walker.walkCompletionTime::gmean 11857.484982 # Table walker service (enqueue to completion) latency 480system.cpu0.itb.walker.walkCompletionTime::stdev 6117.849264 # Table walker service (enqueue to completion) latency 481system.cpu0.itb.walker.walkCompletionTime::0-16383 2266 87.97% 87.97% # Table walker service (enqueue to completion) latency 482system.cpu0.itb.walker.walkCompletionTime::16384-32767 279 10.83% 98.80% # Table walker service (enqueue to completion) latency 483system.cpu0.itb.walker.walkCompletionTime::32768-49151 28 1.09% 99.88% # Table walker service (enqueue to completion) latency 484system.cpu0.itb.walker.walkCompletionTime::49152-65535 1 0.04% 99.92% # Table walker service (enqueue to completion) latency 485system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.04% 99.96% # Table walker service (enqueue to completion) latency 486system.cpu0.itb.walker.walkCompletionTime::163840-180223 1 0.04% 100.00% # Table walker service (enqueue to completion) latency 487system.cpu0.itb.walker.walkCompletionTime::total 2576 # Table walker service (enqueue to completion) latency 488system.cpu0.itb.walker.walksPending::samples 1809154500 # Table walker pending requests distribution 489system.cpu0.itb.walker.walksPending::0 1809154500 100.00% 100.00% # Table walker pending requests distribution 490system.cpu0.itb.walker.walksPending::total 1809154500 # Table walker pending requests distribution 491system.cpu0.itb.walker.walkPageSizes::4K 2256 87.58% 87.58% # Table walker page sizes translated 492system.cpu0.itb.walker.walkPageSizes::1M 320 12.42% 100.00% # Table walker page sizes translated 493system.cpu0.itb.walker.walkPageSizes::total 2576 # Table walker page sizes translated 494system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 495system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3674 # Table walker requests started/completed, data/inst 496system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3674 # Table walker requests started/completed, data/inst 497system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 498system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2576 # Table walker requests started/completed, data/inst 499system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2576 # Table walker requests started/completed, data/inst 500system.cpu0.itb.walker.walkRequestOrigin::total 6250 # Table walker requests started/completed, data/inst 501system.cpu0.itb.inst_hits 121577578 # ITB inst hits 502system.cpu0.itb.inst_misses 3674 # ITB inst misses 503system.cpu0.itb.read_hits 0 # DTB read hits 504system.cpu0.itb.read_misses 0 # DTB read misses 505system.cpu0.itb.write_hits 0 # DTB write hits 506system.cpu0.itb.write_misses 0 # DTB write misses 507system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 508system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 509system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 510system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 511system.cpu0.itb.flush_entries 2371 # Number of entries that have been flushed from TLB 512system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 513system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 514system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 515system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 516system.cpu0.itb.read_accesses 0 # DTB read accesses 517system.cpu0.itb.write_accesses 0 # DTB write accesses 518system.cpu0.itb.inst_accesses 121581252 # ITB inst accesses 519system.cpu0.itb.hits 121577578 # DTB hits 520system.cpu0.itb.misses 3674 # DTB misses 521system.cpu0.itb.accesses 121581252 # DTB accesses 522system.cpu0.numCycles 5743612462 # number of cpu cycles simulated 523system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 524system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 525system.cpu0.kern.inst.arm 0 # number of arm instructions executed 526system.cpu0.kern.inst.quiesce 1891 # number of quiesce instructions executed 527system.cpu0.committedInsts 117761026 # Number of instructions committed 528system.cpu0.committedOps 142319020 # Number of ops (including micro ops) committed 529system.cpu0.num_int_alu_accesses 125932364 # Number of integer alu accesses 530system.cpu0.num_fp_alu_accesses 11483 # Number of float alu accesses 531system.cpu0.num_func_calls 12772321 # number of times a function call or return occured 532system.cpu0.num_conditional_control_insts 16008283 # number of instructions that are conditional controls 533system.cpu0.num_int_insts 125932364 # number of integer instructions 534system.cpu0.num_fp_insts 11483 # number of float instructions 535system.cpu0.num_int_register_reads 231711074 # number of times the integer registers were read 536system.cpu0.num_int_register_writes 87448067 # number of times the integer registers were written 537system.cpu0.num_fp_register_reads 8771 # number of times the floating registers were read 538system.cpu0.num_fp_register_writes 2716 # number of times the floating registers were written 539system.cpu0.num_cc_register_reads 515452324 # number of times the CC registers were read 540system.cpu0.num_cc_register_writes 53494266 # number of times the CC registers were written 541system.cpu0.num_mem_refs 46150372 # number of memory refs 542system.cpu0.num_load_insts 26005626 # Number of load instructions 543system.cpu0.num_store_insts 20144746 # Number of store instructions 544system.cpu0.num_idle_cycles 5456042423.958100 # Number of idle cycles 545system.cpu0.num_busy_cycles 287570038.041900 # Number of busy cycles 546system.cpu0.not_idle_fraction 0.050068 # Percentage of non-idle cycles 547system.cpu0.idle_fraction 0.949932 # Percentage of idle cycles 548system.cpu0.Branches 29545974 # Number of branches fetched 549system.cpu0.op_class::No_OpClass 2315 0.00% 0.00% # Class of executed instruction 550system.cpu0.op_class::IntAlu 99839256 68.33% 68.33% # Class of executed instruction 551system.cpu0.op_class::IntMult 112113 0.08% 68.41% # Class of executed instruction 552system.cpu0.op_class::IntDiv 0 0.00% 68.41% # Class of executed instruction 553system.cpu0.op_class::FloatAdd 0 0.00% 68.41% # Class of executed instruction 554system.cpu0.op_class::FloatCmp 0 0.00% 68.41% # Class of executed instruction 555system.cpu0.op_class::FloatCvt 0 0.00% 68.41% # Class of executed instruction 556system.cpu0.op_class::FloatMult 0 0.00% 68.41% # Class of executed instruction 557system.cpu0.op_class::FloatDiv 0 0.00% 68.41% # Class of executed instruction 558system.cpu0.op_class::FloatSqrt 0 0.00% 68.41% # Class of executed instruction 559system.cpu0.op_class::SimdAdd 0 0.00% 68.41% # Class of executed instruction 560system.cpu0.op_class::SimdAddAcc 0 0.00% 68.41% # Class of executed instruction 561system.cpu0.op_class::SimdAlu 0 0.00% 68.41% # Class of executed instruction 562system.cpu0.op_class::SimdCmp 0 0.00% 68.41% # Class of executed instruction 563system.cpu0.op_class::SimdCvt 0 0.00% 68.41% # Class of executed instruction 564system.cpu0.op_class::SimdMisc 0 0.00% 68.41% # Class of executed instruction 565system.cpu0.op_class::SimdMult 0 0.00% 68.41% # Class of executed instruction 566system.cpu0.op_class::SimdMultAcc 0 0.00% 68.41% # Class of executed instruction 567system.cpu0.op_class::SimdShift 0 0.00% 68.41% # Class of executed instruction 568system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.41% # Class of executed instruction 569system.cpu0.op_class::SimdSqrt 0 0.00% 68.41% # Class of executed instruction 570system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.41% # Class of executed instruction 571system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.41% # Class of executed instruction 572system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.41% # Class of executed instruction 573system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.41% # Class of executed instruction 574system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.41% # Class of executed instruction 575system.cpu0.op_class::SimdFloatMisc 8315 0.01% 68.41% # Class of executed instruction 576system.cpu0.op_class::SimdFloatMult 0 0.00% 68.41% # Class of executed instruction 577system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.41% # Class of executed instruction 578system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.41% # Class of executed instruction 579system.cpu0.op_class::MemRead 26005626 17.80% 86.21% # Class of executed instruction 580system.cpu0.op_class::MemWrite 20144746 13.79% 100.00% # Class of executed instruction 581system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 582system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 583system.cpu0.op_class::total 146112371 # Class of executed instruction 584system.cpu0.dcache.tags.replacements 733230 # number of replacements 585system.cpu0.dcache.tags.tagsinuse 488.702331 # Cycle average of tags in use 586system.cpu0.dcache.tags.total_refs 44081285 # Total number of references to valid blocks. 587system.cpu0.dcache.tags.sampled_refs 733742 # Sample count of references to valid blocks. 588system.cpu0.dcache.tags.avg_refs 60.077364 # Average number of references to valid blocks. 589system.cpu0.dcache.tags.warmup_cycle 1836359000 # Cycle when the warmup percentage was hit. 590system.cpu0.dcache.tags.occ_blocks::cpu0.data 488.702331 # Average occupied blocks per requestor 591system.cpu0.dcache.tags.occ_percent::cpu0.data 0.954497 # Average percentage of cache occupancy 592system.cpu0.dcache.tags.occ_percent::total 0.954497 # Average percentage of cache occupancy 593system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 594system.cpu0.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id 595system.cpu0.dcache.tags.age_task_id_blocks_1024::1 310 # Occupied blocks per task id 596system.cpu0.dcache.tags.age_task_id_blocks_1024::2 94 # Occupied blocks per task id 597system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 598system.cpu0.dcache.tags.tag_accesses 90665231 # Number of tag accesses 599system.cpu0.dcache.tags.data_accesses 90665231 # Number of data accesses 600system.cpu0.dcache.ReadReq_hits::cpu0.data 24440591 # number of ReadReq hits 601system.cpu0.dcache.ReadReq_hits::total 24440591 # number of ReadReq hits 602system.cpu0.dcache.WriteReq_hits::cpu0.data 18493820 # number of WriteReq hits 603system.cpu0.dcache.WriteReq_hits::total 18493820 # number of WriteReq hits 604system.cpu0.dcache.SoftPFReq_hits::cpu0.data 326163 # number of SoftPFReq hits 605system.cpu0.dcache.SoftPFReq_hits::total 326163 # number of SoftPFReq hits 606system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 374037 # number of LoadLockedReq hits 607system.cpu0.dcache.LoadLockedReq_hits::total 374037 # number of LoadLockedReq hits 608system.cpu0.dcache.StoreCondReq_hits::cpu0.data 371586 # number of StoreCondReq hits 609system.cpu0.dcache.StoreCondReq_hits::total 371586 # number of StoreCondReq hits 610system.cpu0.dcache.demand_hits::cpu0.data 42934411 # number of demand (read+write) hits 611system.cpu0.dcache.demand_hits::total 42934411 # number of demand (read+write) hits 612system.cpu0.dcache.overall_hits::cpu0.data 43260574 # number of overall hits 613system.cpu0.dcache.overall_hits::total 43260574 # number of overall hits 614system.cpu0.dcache.ReadReq_misses::cpu0.data 418663 # number of ReadReq misses 615system.cpu0.dcache.ReadReq_misses::total 418663 # number of ReadReq misses 616system.cpu0.dcache.WriteReq_misses::cpu0.data 337563 # number of WriteReq misses 617system.cpu0.dcache.WriteReq_misses::total 337563 # number of WriteReq misses 618system.cpu0.dcache.SoftPFReq_misses::cpu0.data 133473 # number of SoftPFReq misses 619system.cpu0.dcache.SoftPFReq_misses::total 133473 # number of SoftPFReq misses 620system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 22401 # number of LoadLockedReq misses 621system.cpu0.dcache.LoadLockedReq_misses::total 22401 # number of LoadLockedReq misses 622system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19896 # number of StoreCondReq misses 623system.cpu0.dcache.StoreCondReq_misses::total 19896 # number of StoreCondReq misses 624system.cpu0.dcache.demand_misses::cpu0.data 756226 # number of demand (read+write) misses 625system.cpu0.dcache.demand_misses::total 756226 # number of demand (read+write) misses 626system.cpu0.dcache.overall_misses::cpu0.data 889699 # number of overall misses 627system.cpu0.dcache.overall_misses::total 889699 # number of overall misses 628system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5670544000 # number of ReadReq miss cycles 629system.cpu0.dcache.ReadReq_miss_latency::total 5670544000 # number of ReadReq miss cycles 630system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6922080500 # number of WriteReq miss cycles 631system.cpu0.dcache.WriteReq_miss_latency::total 6922080500 # number of WriteReq miss cycles 632system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 345375500 # number of LoadLockedReq miss cycles 633system.cpu0.dcache.LoadLockedReq_miss_latency::total 345375500 # number of LoadLockedReq miss cycles 634system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 506120500 # number of StoreCondReq miss cycles 635system.cpu0.dcache.StoreCondReq_miss_latency::total 506120500 # number of StoreCondReq miss cycles 636system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1857000 # number of StoreCondFailReq miss cycles 637system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1857000 # number of StoreCondFailReq miss cycles 638system.cpu0.dcache.demand_miss_latency::cpu0.data 12592624500 # number of demand (read+write) miss cycles 639system.cpu0.dcache.demand_miss_latency::total 12592624500 # number of demand (read+write) miss cycles 640system.cpu0.dcache.overall_miss_latency::cpu0.data 12592624500 # number of overall miss cycles 641system.cpu0.dcache.overall_miss_latency::total 12592624500 # number of overall miss cycles 642system.cpu0.dcache.ReadReq_accesses::cpu0.data 24859254 # number of ReadReq accesses(hits+misses) 643system.cpu0.dcache.ReadReq_accesses::total 24859254 # number of ReadReq accesses(hits+misses) 644system.cpu0.dcache.WriteReq_accesses::cpu0.data 18831383 # number of WriteReq accesses(hits+misses) 645system.cpu0.dcache.WriteReq_accesses::total 18831383 # number of WriteReq accesses(hits+misses) 646system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 459636 # number of SoftPFReq accesses(hits+misses) 647system.cpu0.dcache.SoftPFReq_accesses::total 459636 # number of SoftPFReq accesses(hits+misses) 648system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 396438 # number of LoadLockedReq accesses(hits+misses) 649system.cpu0.dcache.LoadLockedReq_accesses::total 396438 # number of LoadLockedReq accesses(hits+misses) 650system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 391482 # number of StoreCondReq accesses(hits+misses) 651system.cpu0.dcache.StoreCondReq_accesses::total 391482 # number of StoreCondReq accesses(hits+misses) 652system.cpu0.dcache.demand_accesses::cpu0.data 43690637 # number of demand (read+write) accesses 653system.cpu0.dcache.demand_accesses::total 43690637 # number of demand (read+write) accesses 654system.cpu0.dcache.overall_accesses::cpu0.data 44150273 # number of overall (read+write) accesses 655system.cpu0.dcache.overall_accesses::total 44150273 # number of overall (read+write) accesses 656system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016841 # miss rate for ReadReq accesses 657system.cpu0.dcache.ReadReq_miss_rate::total 0.016841 # miss rate for ReadReq accesses 658system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017926 # miss rate for WriteReq accesses 659system.cpu0.dcache.WriteReq_miss_rate::total 0.017926 # miss rate for WriteReq accesses 660system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.290388 # miss rate for SoftPFReq accesses 661system.cpu0.dcache.SoftPFReq_miss_rate::total 0.290388 # miss rate for SoftPFReq accesses 662system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056506 # miss rate for LoadLockedReq accesses 663system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056506 # miss rate for LoadLockedReq accesses 664system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.050822 # miss rate for StoreCondReq accesses 665system.cpu0.dcache.StoreCondReq_miss_rate::total 0.050822 # miss rate for StoreCondReq accesses 666system.cpu0.dcache.demand_miss_rate::cpu0.data 0.017309 # miss rate for demand accesses 667system.cpu0.dcache.demand_miss_rate::total 0.017309 # miss rate for demand accesses 668system.cpu0.dcache.overall_miss_rate::cpu0.data 0.020152 # miss rate for overall accesses 669system.cpu0.dcache.overall_miss_rate::total 0.020152 # miss rate for overall accesses 670system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13544.411615 # average ReadReq miss latency 671system.cpu0.dcache.ReadReq_avg_miss_latency::total 13544.411615 # average ReadReq miss latency 672system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20506.040354 # average WriteReq miss latency 673system.cpu0.dcache.WriteReq_avg_miss_latency::total 20506.040354 # average WriteReq miss latency 674system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15417.860810 # average LoadLockedReq miss latency 675system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15417.860810 # average LoadLockedReq miss latency 676system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25438.304182 # average StoreCondReq miss latency 677system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25438.304182 # average StoreCondReq miss latency 678system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 679system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 680system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16651.932756 # average overall miss latency 681system.cpu0.dcache.demand_avg_miss_latency::total 16651.932756 # average overall miss latency 682system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14153.803140 # average overall miss latency 683system.cpu0.dcache.overall_avg_miss_latency::total 14153.803140 # average overall miss latency 684system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 685system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 686system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 687system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 688system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 689system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 690system.cpu0.dcache.fast_writes 0 # number of fast writes performed 691system.cpu0.dcache.cache_copies 0 # number of cache copies performed 692system.cpu0.dcache.writebacks::writebacks 733230 # number of writebacks 693system.cpu0.dcache.writebacks::total 733230 # number of writebacks 694system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25285 # number of ReadReq MSHR hits 695system.cpu0.dcache.ReadReq_mshr_hits::total 25285 # number of ReadReq MSHR hits 696system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1 # number of WriteReq MSHR hits 697system.cpu0.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits 698system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15695 # number of LoadLockedReq MSHR hits 699system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15695 # number of LoadLockedReq MSHR hits 700system.cpu0.dcache.demand_mshr_hits::cpu0.data 25286 # number of demand (read+write) MSHR hits 701system.cpu0.dcache.demand_mshr_hits::total 25286 # number of demand (read+write) MSHR hits 702system.cpu0.dcache.overall_mshr_hits::cpu0.data 25286 # number of overall MSHR hits 703system.cpu0.dcache.overall_mshr_hits::total 25286 # number of overall MSHR hits 704system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 393378 # number of ReadReq MSHR misses 705system.cpu0.dcache.ReadReq_mshr_misses::total 393378 # number of ReadReq MSHR misses 706system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 337562 # number of WriteReq MSHR misses 707system.cpu0.dcache.WriteReq_mshr_misses::total 337562 # number of WriteReq MSHR misses 708system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 106333 # number of SoftPFReq MSHR misses 709system.cpu0.dcache.SoftPFReq_mshr_misses::total 106333 # number of SoftPFReq MSHR misses 710system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6706 # number of LoadLockedReq MSHR misses 711system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6706 # number of LoadLockedReq MSHR misses 712system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19896 # number of StoreCondReq MSHR misses 713system.cpu0.dcache.StoreCondReq_mshr_misses::total 19896 # number of StoreCondReq MSHR misses 714system.cpu0.dcache.demand_mshr_misses::cpu0.data 730940 # number of demand (read+write) MSHR misses 715system.cpu0.dcache.demand_mshr_misses::total 730940 # number of demand (read+write) MSHR misses 716system.cpu0.dcache.overall_mshr_misses::cpu0.data 837273 # number of overall MSHR misses 717system.cpu0.dcache.overall_mshr_misses::total 837273 # number of overall MSHR misses 718system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31817 # number of ReadReq MSHR uncacheable 719system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31817 # number of ReadReq MSHR uncacheable 720system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28499 # number of WriteReq MSHR uncacheable 721system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28499 # number of WriteReq MSHR uncacheable 722system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60316 # number of overall MSHR uncacheable misses 723system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60316 # number of overall MSHR uncacheable misses 724system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4848200000 # number of ReadReq MSHR miss cycles 725system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4848200000 # number of ReadReq MSHR miss cycles 726system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6584514000 # number of WriteReq MSHR miss cycles 727system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6584514000 # number of WriteReq MSHR miss cycles 728system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1737943000 # number of SoftPFReq MSHR miss cycles 729system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1737943000 # number of SoftPFReq MSHR miss cycles 730system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 103994500 # number of LoadLockedReq MSHR miss cycles 731system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 103994500 # number of LoadLockedReq MSHR miss cycles 732system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 486281500 # number of StoreCondReq MSHR miss cycles 733system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 486281500 # number of StoreCondReq MSHR miss cycles 734system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1800000 # number of StoreCondFailReq MSHR miss cycles 735system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1800000 # number of StoreCondFailReq MSHR miss cycles 736system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11432714000 # number of demand (read+write) MSHR miss cycles 737system.cpu0.dcache.demand_mshr_miss_latency::total 11432714000 # number of demand (read+write) MSHR miss cycles 738system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13170657000 # number of overall MSHR miss cycles 739system.cpu0.dcache.overall_mshr_miss_latency::total 13170657000 # number of overall MSHR miss cycles 740system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6628843000 # number of ReadReq MSHR uncacheable cycles 741system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6628843000 # number of ReadReq MSHR uncacheable cycles 742system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5400920500 # number of WriteReq MSHR uncacheable cycles 743system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5400920500 # number of WriteReq MSHR uncacheable cycles 744system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12029763500 # number of overall MSHR uncacheable cycles 745system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12029763500 # number of overall MSHR uncacheable cycles 746system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015824 # mshr miss rate for ReadReq accesses 747system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015824 # mshr miss rate for ReadReq accesses 748system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017926 # mshr miss rate for WriteReq accesses 749system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017926 # mshr miss rate for WriteReq accesses 750system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.231342 # mshr miss rate for SoftPFReq accesses 751system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.231342 # mshr miss rate for SoftPFReq accesses 752system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016916 # mshr miss rate for LoadLockedReq accesses 753system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016916 # mshr miss rate for LoadLockedReq accesses 754system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.050822 # mshr miss rate for StoreCondReq accesses 755system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.050822 # mshr miss rate for StoreCondReq accesses 756system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016730 # mshr miss rate for demand accesses 757system.cpu0.dcache.demand_mshr_miss_rate::total 0.016730 # mshr miss rate for demand accesses 758system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018964 # mshr miss rate for overall accesses 759system.cpu0.dcache.overall_mshr_miss_rate::total 0.018964 # mshr miss rate for overall accesses 760system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12324.532638 # average ReadReq mshr miss latency 761system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12324.532638 # average ReadReq mshr miss latency 762system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19506.087771 # average WriteReq mshr miss latency 763system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19506.087771 # average WriteReq mshr miss latency 764system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16344.342772 # average SoftPFReq mshr miss latency 765system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16344.342772 # average SoftPFReq mshr miss latency 766system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15507.679690 # average LoadLockedReq mshr miss latency 767system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15507.679690 # average LoadLockedReq mshr miss latency 768system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24441.169079 # average StoreCondReq mshr miss latency 769system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24441.169079 # average StoreCondReq mshr miss latency 770system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 771system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 772system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15641.111446 # average overall mshr miss latency 773system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15641.111446 # average overall mshr miss latency 774system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15730.421260 # average overall mshr miss latency 775system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15730.421260 # average overall mshr miss latency 776system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208342.804161 # average ReadReq mshr uncacheable latency 777system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208342.804161 # average ReadReq mshr uncacheable latency 778system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189512.632022 # average WriteReq mshr uncacheable latency 779system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189512.632022 # average WriteReq mshr uncacheable latency 780system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 199445.644605 # average overall mshr uncacheable latency 781system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199445.644605 # average overall mshr uncacheable latency 782system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 783system.cpu0.icache.tags.replacements 1147026 # number of replacements 784system.cpu0.icache.tags.tagsinuse 511.321434 # Cycle average of tags in use 785system.cpu0.icache.tags.total_refs 120430031 # Total number of references to valid blocks. 786system.cpu0.icache.tags.sampled_refs 1147538 # Sample count of references to valid blocks. 787system.cpu0.icache.tags.avg_refs 104.946443 # Average number of references to valid blocks. 788system.cpu0.icache.tags.warmup_cycle 14862010000 # Cycle when the warmup percentage was hit. 789system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.321434 # Average occupied blocks per requestor 790system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998675 # Average percentage of cache occupancy 791system.cpu0.icache.tags.occ_percent::total 0.998675 # Average percentage of cache occupancy 792system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 793system.cpu0.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id 794system.cpu0.icache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id 795system.cpu0.icache.tags.age_task_id_blocks_1024::2 223 # Occupied blocks per task id 796system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 797system.cpu0.icache.tags.tag_accesses 244302703 # Number of tag accesses 798system.cpu0.icache.tags.data_accesses 244302703 # Number of data accesses 799system.cpu0.icache.ReadReq_hits::cpu0.inst 120430031 # number of ReadReq hits 800system.cpu0.icache.ReadReq_hits::total 120430031 # number of ReadReq hits 801system.cpu0.icache.demand_hits::cpu0.inst 120430031 # number of demand (read+write) hits 802system.cpu0.icache.demand_hits::total 120430031 # number of demand (read+write) hits 803system.cpu0.icache.overall_hits::cpu0.inst 120430031 # number of overall hits 804system.cpu0.icache.overall_hits::total 120430031 # number of overall hits 805system.cpu0.icache.ReadReq_misses::cpu0.inst 1147547 # number of ReadReq misses 806system.cpu0.icache.ReadReq_misses::total 1147547 # number of ReadReq misses 807system.cpu0.icache.demand_misses::cpu0.inst 1147547 # number of demand (read+write) misses 808system.cpu0.icache.demand_misses::total 1147547 # number of demand (read+write) misses 809system.cpu0.icache.overall_misses::cpu0.inst 1147547 # number of overall misses 810system.cpu0.icache.overall_misses::total 1147547 # number of overall misses 811system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12241983500 # number of ReadReq miss cycles 812system.cpu0.icache.ReadReq_miss_latency::total 12241983500 # number of ReadReq miss cycles 813system.cpu0.icache.demand_miss_latency::cpu0.inst 12241983500 # number of demand (read+write) miss cycles 814system.cpu0.icache.demand_miss_latency::total 12241983500 # number of demand (read+write) miss cycles 815system.cpu0.icache.overall_miss_latency::cpu0.inst 12241983500 # number of overall miss cycles 816system.cpu0.icache.overall_miss_latency::total 12241983500 # number of overall miss cycles 817system.cpu0.icache.ReadReq_accesses::cpu0.inst 121577578 # number of ReadReq accesses(hits+misses) 818system.cpu0.icache.ReadReq_accesses::total 121577578 # number of ReadReq accesses(hits+misses) 819system.cpu0.icache.demand_accesses::cpu0.inst 121577578 # number of demand (read+write) accesses 820system.cpu0.icache.demand_accesses::total 121577578 # number of demand (read+write) accesses 821system.cpu0.icache.overall_accesses::cpu0.inst 121577578 # number of overall (read+write) accesses 822system.cpu0.icache.overall_accesses::total 121577578 # number of overall (read+write) accesses 823system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009439 # miss rate for ReadReq accesses 824system.cpu0.icache.ReadReq_miss_rate::total 0.009439 # miss rate for ReadReq accesses 825system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009439 # miss rate for demand accesses 826system.cpu0.icache.demand_miss_rate::total 0.009439 # miss rate for demand accesses 827system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009439 # miss rate for overall accesses 828system.cpu0.icache.overall_miss_rate::total 0.009439 # miss rate for overall accesses 829system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10667.958262 # average ReadReq miss latency 830system.cpu0.icache.ReadReq_avg_miss_latency::total 10667.958262 # average ReadReq miss latency 831system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10667.958262 # average overall miss latency 832system.cpu0.icache.demand_avg_miss_latency::total 10667.958262 # average overall miss latency 833system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10667.958262 # average overall miss latency 834system.cpu0.icache.overall_avg_miss_latency::total 10667.958262 # average overall miss latency 835system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 836system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 837system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 838system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 839system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 840system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 841system.cpu0.icache.fast_writes 0 # number of fast writes performed 842system.cpu0.icache.cache_copies 0 # number of cache copies performed 843system.cpu0.icache.writebacks::writebacks 1147026 # number of writebacks 844system.cpu0.icache.writebacks::total 1147026 # number of writebacks 845system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1147547 # number of ReadReq MSHR misses 846system.cpu0.icache.ReadReq_mshr_misses::total 1147547 # number of ReadReq MSHR misses 847system.cpu0.icache.demand_mshr_misses::cpu0.inst 1147547 # number of demand (read+write) MSHR misses 848system.cpu0.icache.demand_mshr_misses::total 1147547 # number of demand (read+write) MSHR misses 849system.cpu0.icache.overall_mshr_misses::cpu0.inst 1147547 # number of overall MSHR misses 850system.cpu0.icache.overall_mshr_misses::total 1147547 # number of overall MSHR misses 851system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable 852system.cpu0.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable 853system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses 854system.cpu0.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses 855system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11668210000 # number of ReadReq MSHR miss cycles 856system.cpu0.icache.ReadReq_mshr_miss_latency::total 11668210000 # number of ReadReq MSHR miss cycles 857system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11668210000 # number of demand (read+write) MSHR miss cycles 858system.cpu0.icache.demand_mshr_miss_latency::total 11668210000 # number of demand (read+write) MSHR miss cycles 859system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11668210000 # number of overall MSHR miss cycles 860system.cpu0.icache.overall_mshr_miss_latency::total 11668210000 # number of overall MSHR miss cycles 861system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1253876500 # number of ReadReq MSHR uncacheable cycles 862system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1253876500 # number of ReadReq MSHR uncacheable cycles 863system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1253876500 # number of overall MSHR uncacheable cycles 864system.cpu0.icache.overall_mshr_uncacheable_latency::total 1253876500 # number of overall MSHR uncacheable cycles 865system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009439 # mshr miss rate for ReadReq accesses 866system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009439 # mshr miss rate for ReadReq accesses 867system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009439 # mshr miss rate for demand accesses 868system.cpu0.icache.demand_mshr_miss_rate::total 0.009439 # mshr miss rate for demand accesses 869system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009439 # mshr miss rate for overall accesses 870system.cpu0.icache.overall_mshr_miss_rate::total 0.009439 # mshr miss rate for overall accesses 871system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10167.958262 # average ReadReq mshr miss latency 872system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10167.958262 # average ReadReq mshr miss latency 873system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10167.958262 # average overall mshr miss latency 874system.cpu0.icache.demand_avg_mshr_miss_latency::total 10167.958262 # average overall mshr miss latency 875system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10167.958262 # average overall mshr miss latency 876system.cpu0.icache.overall_avg_mshr_miss_latency::total 10167.958262 # average overall mshr miss latency 877system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138979.882509 # average ReadReq mshr uncacheable latency 878system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138979.882509 # average ReadReq mshr uncacheable latency 879system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138979.882509 # average overall mshr uncacheable latency 880system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138979.882509 # average overall mshr uncacheable latency 881system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 882system.cpu0.l2cache.prefetcher.num_hwpf_issued 1935584 # number of hwpf issued 883system.cpu0.l2cache.prefetcher.pfIdentified 1935659 # number of prefetch candidates identified 884system.cpu0.l2cache.prefetcher.pfBufferHit 66 # number of redundant prefetches already in prefetch queue 885system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 886system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 887system.cpu0.l2cache.prefetcher.pfSpanPage 246453 # number of prefetches not generated due to page crossing 888system.cpu0.l2cache.tags.replacements 273594 # number of replacements 889system.cpu0.l2cache.tags.tagsinuse 16077.204583 # Cycle average of tags in use 890system.cpu0.l2cache.tags.total_refs 3064483 # Total number of references to valid blocks. 891system.cpu0.l2cache.tags.sampled_refs 289692 # Sample count of references to valid blocks. 892system.cpu0.l2cache.tags.avg_refs 10.578418 # Average number of references to valid blocks. 893system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 894system.cpu0.l2cache.tags.occ_blocks::writebacks 14597.123435 # Average occupied blocks per requestor 895system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 2.512757 # Average occupied blocks per requestor 896system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.144663 # Average occupied blocks per requestor 897system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1477.423728 # Average occupied blocks per requestor 898system.cpu0.l2cache.tags.occ_percent::writebacks 0.890938 # Average percentage of cache occupancy 899system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000153 # Average percentage of cache occupancy 900system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000009 # Average percentage of cache occupancy 901system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.090175 # Average percentage of cache occupancy 902system.cpu0.l2cache.tags.occ_percent::total 0.981275 # Average percentage of cache occupancy 903system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1029 # Occupied blocks per task id 904system.cpu0.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id 905system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15061 # Occupied blocks per task id 906system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 10 # Occupied blocks per task id 907system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 254 # Occupied blocks per task id 908system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 333 # Occupied blocks per task id 909system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 432 # Occupied blocks per task id 910system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id 911system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 912system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id 913system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id 914system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id 915system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3292 # Occupied blocks per task id 916system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7648 # Occupied blocks per task id 917system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3847 # Occupied blocks per task id 918system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.062805 # Percentage of cache occupancy per task id 919system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id 920system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.919250 # Percentage of cache occupancy per task id 921system.cpu0.l2cache.tags.tag_accesses 62842008 # Number of tag accesses 922system.cpu0.l2cache.tags.data_accesses 62842008 # Number of data accesses 923system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 11176 # number of ReadReq hits 924system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4956 # number of ReadReq hits 925system.cpu0.l2cache.ReadReq_hits::total 16132 # number of ReadReq hits 926system.cpu0.l2cache.WritebackDirty_hits::writebacks 502092 # number of WritebackDirty hits 927system.cpu0.l2cache.WritebackDirty_hits::total 502092 # number of WritebackDirty hits 928system.cpu0.l2cache.WritebackClean_hits::writebacks 1349261 # number of WritebackClean hits 929system.cpu0.l2cache.WritebackClean_hits::total 1349261 # number of WritebackClean hits 930system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 1 # number of UpgradeReq hits 931system.cpu0.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits 932system.cpu0.l2cache.ReadExReq_hits::cpu0.data 238948 # number of ReadExReq hits 933system.cpu0.l2cache.ReadExReq_hits::total 238948 # number of ReadExReq hits 934system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1101688 # number of ReadCleanReq hits 935system.cpu0.l2cache.ReadCleanReq_hits::total 1101688 # number of ReadCleanReq hits 936system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 411953 # number of ReadSharedReq hits 937system.cpu0.l2cache.ReadSharedReq_hits::total 411953 # number of ReadSharedReq hits 938system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 11176 # number of demand (read+write) hits 939system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4956 # number of demand (read+write) hits 940system.cpu0.l2cache.demand_hits::cpu0.inst 1101688 # number of demand (read+write) hits 941system.cpu0.l2cache.demand_hits::cpu0.data 650901 # number of demand (read+write) hits 942system.cpu0.l2cache.demand_hits::total 1768721 # number of demand (read+write) hits 943system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 11176 # number of overall hits 944system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4956 # number of overall hits 945system.cpu0.l2cache.overall_hits::cpu0.inst 1101688 # number of overall hits 946system.cpu0.l2cache.overall_hits::cpu0.data 650901 # number of overall hits 947system.cpu0.l2cache.overall_hits::total 1768721 # number of overall hits 948system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 156 # number of ReadReq misses 949system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 75 # number of ReadReq misses 950system.cpu0.l2cache.ReadReq_misses::total 231 # number of ReadReq misses 951system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55191 # number of UpgradeReq misses 952system.cpu0.l2cache.UpgradeReq_misses::total 55191 # number of UpgradeReq misses 953system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19886 # number of SCUpgradeReq misses 954system.cpu0.l2cache.SCUpgradeReq_misses::total 19886 # number of SCUpgradeReq misses 955system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 10 # number of SCUpgradeFailReq misses 956system.cpu0.l2cache.SCUpgradeFailReq_misses::total 10 # number of SCUpgradeFailReq misses 957system.cpu0.l2cache.ReadExReq_misses::cpu0.data 43422 # number of ReadExReq misses 958system.cpu0.l2cache.ReadExReq_misses::total 43422 # number of ReadExReq misses 959system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 45859 # number of ReadCleanReq misses 960system.cpu0.l2cache.ReadCleanReq_misses::total 45859 # number of ReadCleanReq misses 961system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 94464 # number of ReadSharedReq misses 962system.cpu0.l2cache.ReadSharedReq_misses::total 94464 # number of ReadSharedReq misses 963system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 156 # number of demand (read+write) misses 964system.cpu0.l2cache.demand_misses::cpu0.itb.walker 75 # number of demand (read+write) misses 965system.cpu0.l2cache.demand_misses::cpu0.inst 45859 # number of demand (read+write) misses 966system.cpu0.l2cache.demand_misses::cpu0.data 137886 # number of demand (read+write) misses 967system.cpu0.l2cache.demand_misses::total 183976 # number of demand (read+write) misses 968system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 156 # number of overall misses 969system.cpu0.l2cache.overall_misses::cpu0.itb.walker 75 # number of overall misses 970system.cpu0.l2cache.overall_misses::cpu0.inst 45859 # number of overall misses 971system.cpu0.l2cache.overall_misses::cpu0.data 137886 # number of overall misses 972system.cpu0.l2cache.overall_misses::total 183976 # number of overall misses 973system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 4297500 # number of ReadReq miss cycles 974system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2025500 # number of ReadReq miss cycles 975system.cpu0.l2cache.ReadReq_miss_latency::total 6323000 # number of ReadReq miss cycles 976system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 162363000 # number of UpgradeReq miss cycles 977system.cpu0.l2cache.UpgradeReq_miss_latency::total 162363000 # number of UpgradeReq miss cycles 978system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 41658000 # number of SCUpgradeReq miss cycles 979system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 41658000 # number of SCUpgradeReq miss cycles 980system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1712496 # number of SCUpgradeFailReq miss cycles 981system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1712496 # number of SCUpgradeFailReq miss cycles 982system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2783886000 # number of ReadExReq miss cycles 983system.cpu0.l2cache.ReadExReq_miss_latency::total 2783886000 # number of ReadExReq miss cycles 984system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 3283750500 # number of ReadCleanReq miss cycles 985system.cpu0.l2cache.ReadCleanReq_miss_latency::total 3283750500 # number of ReadCleanReq miss cycles 986system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3241501500 # number of ReadSharedReq miss cycles 987system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3241501500 # number of ReadSharedReq miss cycles 988system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 4297500 # number of demand (read+write) miss cycles 989system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2025500 # number of demand (read+write) miss cycles 990system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3283750500 # number of demand (read+write) miss cycles 991system.cpu0.l2cache.demand_miss_latency::cpu0.data 6025387500 # number of demand (read+write) miss cycles 992system.cpu0.l2cache.demand_miss_latency::total 9315461000 # number of demand (read+write) miss cycles 993system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 4297500 # number of overall miss cycles 994system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2025500 # number of overall miss cycles 995system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3283750500 # number of overall miss cycles 996system.cpu0.l2cache.overall_miss_latency::cpu0.data 6025387500 # number of overall miss cycles 997system.cpu0.l2cache.overall_miss_latency::total 9315461000 # number of overall miss cycles 998system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 11332 # number of ReadReq accesses(hits+misses) 999system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 5031 # number of ReadReq accesses(hits+misses) 1000system.cpu0.l2cache.ReadReq_accesses::total 16363 # number of ReadReq accesses(hits+misses) 1001system.cpu0.l2cache.WritebackDirty_accesses::writebacks 502092 # number of WritebackDirty accesses(hits+misses) 1002system.cpu0.l2cache.WritebackDirty_accesses::total 502092 # number of WritebackDirty accesses(hits+misses) 1003system.cpu0.l2cache.WritebackClean_accesses::writebacks 1349261 # number of WritebackClean accesses(hits+misses) 1004system.cpu0.l2cache.WritebackClean_accesses::total 1349261 # number of WritebackClean accesses(hits+misses) 1005system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55192 # number of UpgradeReq accesses(hits+misses) 1006system.cpu0.l2cache.UpgradeReq_accesses::total 55192 # number of UpgradeReq accesses(hits+misses) 1007system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 19886 # number of SCUpgradeReq accesses(hits+misses) 1008system.cpu0.l2cache.SCUpgradeReq_accesses::total 19886 # number of SCUpgradeReq accesses(hits+misses) 1009system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 10 # number of SCUpgradeFailReq accesses(hits+misses) 1010system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 10 # number of SCUpgradeFailReq accesses(hits+misses) 1011system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 282370 # number of ReadExReq accesses(hits+misses) 1012system.cpu0.l2cache.ReadExReq_accesses::total 282370 # number of ReadExReq accesses(hits+misses) 1013system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1147547 # number of ReadCleanReq accesses(hits+misses) 1014system.cpu0.l2cache.ReadCleanReq_accesses::total 1147547 # number of ReadCleanReq accesses(hits+misses) 1015system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 506417 # number of ReadSharedReq accesses(hits+misses) 1016system.cpu0.l2cache.ReadSharedReq_accesses::total 506417 # number of ReadSharedReq accesses(hits+misses) 1017system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 11332 # number of demand (read+write) accesses 1018system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 5031 # number of demand (read+write) accesses 1019system.cpu0.l2cache.demand_accesses::cpu0.inst 1147547 # number of demand (read+write) accesses 1020system.cpu0.l2cache.demand_accesses::cpu0.data 788787 # number of demand (read+write) accesses 1021system.cpu0.l2cache.demand_accesses::total 1952697 # number of demand (read+write) accesses 1022system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 11332 # number of overall (read+write) accesses 1023system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 5031 # number of overall (read+write) accesses 1024system.cpu0.l2cache.overall_accesses::cpu0.inst 1147547 # number of overall (read+write) accesses 1025system.cpu0.l2cache.overall_accesses::cpu0.data 788787 # number of overall (read+write) accesses 1026system.cpu0.l2cache.overall_accesses::total 1952697 # number of overall (read+write) accesses 1027system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.013766 # miss rate for ReadReq accesses 1028system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.014908 # miss rate for ReadReq accesses 1029system.cpu0.l2cache.ReadReq_miss_rate::total 0.014117 # miss rate for ReadReq accesses 1030system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999982 # miss rate for UpgradeReq accesses 1031system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999982 # miss rate for UpgradeReq accesses 1032system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 1033system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1034system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1035system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1036system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.153777 # miss rate for ReadExReq accesses 1037system.cpu0.l2cache.ReadExReq_miss_rate::total 0.153777 # miss rate for ReadExReq accesses 1038system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.039963 # miss rate for ReadCleanReq accesses 1039system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.039963 # miss rate for ReadCleanReq accesses 1040system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.186534 # miss rate for ReadSharedReq accesses 1041system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.186534 # miss rate for ReadSharedReq accesses 1042system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.013766 # miss rate for demand accesses 1043system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.014908 # miss rate for demand accesses 1044system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.039963 # miss rate for demand accesses 1045system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.174808 # miss rate for demand accesses 1046system.cpu0.l2cache.demand_miss_rate::total 0.094216 # miss rate for demand accesses 1047system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.013766 # miss rate for overall accesses 1048system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.014908 # miss rate for overall accesses 1049system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.039963 # miss rate for overall accesses 1050system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.174808 # miss rate for overall accesses 1051system.cpu0.l2cache.overall_miss_rate::total 0.094216 # miss rate for overall accesses 1052system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 27548.076923 # average ReadReq miss latency 1053system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 27006.666667 # average ReadReq miss latency 1054system.cpu0.l2cache.ReadReq_avg_miss_latency::total 27372.294372 # average ReadReq miss latency 1055system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 2941.838343 # average UpgradeReq miss latency 1056system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 2941.838343 # average UpgradeReq miss latency 1057system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 2094.840591 # average SCUpgradeReq miss latency 1058system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 2094.840591 # average SCUpgradeReq miss latency 1059system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 171249.600000 # average SCUpgradeFailReq miss latency 1060system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 171249.600000 # average SCUpgradeFailReq miss latency 1061system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 64112.339367 # average ReadExReq miss latency 1062system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 64112.339367 # average ReadExReq miss latency 1063system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 71605.366449 # average ReadCleanReq miss latency 1064system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 71605.366449 # average ReadCleanReq miss latency 1065system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 34314.675432 # average ReadSharedReq miss latency 1066system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 34314.675432 # average ReadSharedReq miss latency 1067system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 27548.076923 # average overall miss latency 1068system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 27006.666667 # average overall miss latency 1069system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 71605.366449 # average overall miss latency 1070system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 43698.326879 # average overall miss latency 1071system.cpu0.l2cache.demand_avg_miss_latency::total 50634.109884 # average overall miss latency 1072system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 27548.076923 # average overall miss latency 1073system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 27006.666667 # average overall miss latency 1074system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 71605.366449 # average overall miss latency 1075system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 43698.326879 # average overall miss latency 1076system.cpu0.l2cache.overall_avg_miss_latency::total 50634.109884 # average overall miss latency 1077system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1078system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1079system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1080system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1081system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1082system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1083system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1084system.cpu0.l2cache.cache_copies 0 # number of cache copies performed 1085system.cpu0.l2cache.writebacks::writebacks 231848 # number of writebacks 1086system.cpu0.l2cache.writebacks::total 231848 # number of writebacks 1087system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1793 # number of ReadExReq MSHR hits 1088system.cpu0.l2cache.ReadExReq_mshr_hits::total 1793 # number of ReadExReq MSHR hits 1089system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 59 # number of ReadSharedReq MSHR hits 1090system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 59 # number of ReadSharedReq MSHR hits 1091system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1852 # number of demand (read+write) MSHR hits 1092system.cpu0.l2cache.demand_mshr_hits::total 1852 # number of demand (read+write) MSHR hits 1093system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1852 # number of overall MSHR hits 1094system.cpu0.l2cache.overall_mshr_hits::total 1852 # number of overall MSHR hits 1095system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 156 # number of ReadReq MSHR misses 1096system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 75 # number of ReadReq MSHR misses 1097system.cpu0.l2cache.ReadReq_mshr_misses::total 231 # number of ReadReq MSHR misses 1098system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 264648 # number of HardPFReq MSHR misses 1099system.cpu0.l2cache.HardPFReq_mshr_misses::total 264648 # number of HardPFReq MSHR misses 1100system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 55191 # number of UpgradeReq MSHR misses 1101system.cpu0.l2cache.UpgradeReq_mshr_misses::total 55191 # number of UpgradeReq MSHR misses 1102system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19886 # number of SCUpgradeReq MSHR misses 1103system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19886 # number of SCUpgradeReq MSHR misses 1104system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 10 # number of SCUpgradeFailReq MSHR misses 1105system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 10 # number of SCUpgradeFailReq MSHR misses 1106system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41629 # number of ReadExReq MSHR misses 1107system.cpu0.l2cache.ReadExReq_mshr_misses::total 41629 # number of ReadExReq MSHR misses 1108system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 45859 # number of ReadCleanReq MSHR misses 1109system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 45859 # number of ReadCleanReq MSHR misses 1110system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 94405 # number of ReadSharedReq MSHR misses 1111system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 94405 # number of ReadSharedReq MSHR misses 1112system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 156 # number of demand (read+write) MSHR misses 1113system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 75 # number of demand (read+write) MSHR misses 1114system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 45859 # number of demand (read+write) MSHR misses 1115system.cpu0.l2cache.demand_mshr_misses::cpu0.data 136034 # number of demand (read+write) MSHR misses 1116system.cpu0.l2cache.demand_mshr_misses::total 182124 # number of demand (read+write) MSHR misses 1117system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 156 # number of overall MSHR misses 1118system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 75 # number of overall MSHR misses 1119system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 45859 # number of overall MSHR misses 1120system.cpu0.l2cache.overall_mshr_misses::cpu0.data 136034 # number of overall MSHR misses 1121system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 264648 # number of overall MSHR misses 1122system.cpu0.l2cache.overall_mshr_misses::total 446772 # number of overall MSHR misses 1123system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable 1124system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31817 # number of ReadReq MSHR uncacheable 1125system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 40839 # number of ReadReq MSHR uncacheable 1126system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28499 # number of WriteReq MSHR uncacheable 1127system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28499 # number of WriteReq MSHR uncacheable 1128system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses 1129system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60316 # number of overall MSHR uncacheable misses 1130system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 69338 # number of overall MSHR uncacheable misses 1131system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 3361500 # number of ReadReq MSHR miss cycles 1132system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 1575500 # number of ReadReq MSHR miss cycles 1133system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 4937000 # number of ReadReq MSHR miss cycles 1134system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 20425308140 # number of HardPFReq MSHR miss cycles 1135system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 20425308140 # number of HardPFReq MSHR miss cycles 1136system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 1407414000 # number of UpgradeReq MSHR miss cycles 1137system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 1407414000 # number of UpgradeReq MSHR miss cycles 1138system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 337427000 # number of SCUpgradeReq MSHR miss cycles 1139system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 337427000 # number of SCUpgradeReq MSHR miss cycles 1140system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1370496 # number of SCUpgradeFailReq MSHR miss cycles 1141system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1370496 # number of SCUpgradeFailReq MSHR miss cycles 1142system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2353646000 # number of ReadExReq MSHR miss cycles 1143system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2353646000 # number of ReadExReq MSHR miss cycles 1144system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 3008596500 # number of ReadCleanReq MSHR miss cycles 1145system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 3008596500 # number of ReadCleanReq MSHR miss cycles 1146system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2668850500 # number of ReadSharedReq MSHR miss cycles 1147system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2668850500 # number of ReadSharedReq MSHR miss cycles 1148system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 3361500 # number of demand (read+write) MSHR miss cycles 1149system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 1575500 # number of demand (read+write) MSHR miss cycles 1150system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3008596500 # number of demand (read+write) MSHR miss cycles 1151system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 5022496500 # number of demand (read+write) MSHR miss cycles 1152system.cpu0.l2cache.demand_mshr_miss_latency::total 8036030000 # number of demand (read+write) MSHR miss cycles 1153system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 3361500 # number of overall MSHR miss cycles 1154system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 1575500 # number of overall MSHR miss cycles 1155system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3008596500 # number of overall MSHR miss cycles 1156system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 5022496500 # number of overall MSHR miss cycles 1157system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 20425308140 # number of overall MSHR miss cycles 1158system.cpu0.l2cache.overall_mshr_miss_latency::total 28461338140 # number of overall MSHR miss cycles 1159system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1186211500 # number of ReadReq MSHR uncacheable cycles 1160system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6373893500 # number of ReadReq MSHR uncacheable cycles 1161system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7560105000 # number of ReadReq MSHR uncacheable cycles 1162system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5187056500 # number of WriteReq MSHR uncacheable cycles 1163system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5187056500 # number of WriteReq MSHR uncacheable cycles 1164system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 1186211500 # number of overall MSHR uncacheable cycles 1165system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11560950000 # number of overall MSHR uncacheable cycles 1166system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12747161500 # number of overall MSHR uncacheable cycles 1167system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.013766 # mshr miss rate for ReadReq accesses 1168system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.014908 # mshr miss rate for ReadReq accesses 1169system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.014117 # mshr miss rate for ReadReq accesses 1170system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1171system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1172system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999982 # mshr miss rate for UpgradeReq accesses 1173system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999982 # mshr miss rate for UpgradeReq accesses 1174system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses 1175system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1176system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1177system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1178system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.147427 # mshr miss rate for ReadExReq accesses 1179system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.147427 # mshr miss rate for ReadExReq accesses 1180system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.039963 # mshr miss rate for ReadCleanReq accesses 1181system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.039963 # mshr miss rate for ReadCleanReq accesses 1182system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.186418 # mshr miss rate for ReadSharedReq accesses 1183system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.186418 # mshr miss rate for ReadSharedReq accesses 1184system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.013766 # mshr miss rate for demand accesses 1185system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.014908 # mshr miss rate for demand accesses 1186system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.039963 # mshr miss rate for demand accesses 1187system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.172460 # mshr miss rate for demand accesses 1188system.cpu0.l2cache.demand_mshr_miss_rate::total 0.093268 # mshr miss rate for demand accesses 1189system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.013766 # mshr miss rate for overall accesses 1190system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.014908 # mshr miss rate for overall accesses 1191system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.039963 # mshr miss rate for overall accesses 1192system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.172460 # mshr miss rate for overall accesses 1193system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1194system.cpu0.l2cache.overall_mshr_miss_rate::total 0.228797 # mshr miss rate for overall accesses 1195system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 21548.076923 # average ReadReq mshr miss latency 1196system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 21006.666667 # average ReadReq mshr miss latency 1197system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 21372.294372 # average ReadReq mshr miss latency 1198system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 77179.151703 # average HardPFReq mshr miss latency 1199system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 77179.151703 # average HardPFReq mshr miss latency 1200system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 25500.788172 # average UpgradeReq mshr miss latency 1201system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 25500.788172 # average UpgradeReq mshr miss latency 1202system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16968.067988 # average SCUpgradeReq mshr miss latency 1203system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16968.067988 # average SCUpgradeReq mshr miss latency 1204system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 137049.600000 # average SCUpgradeFailReq mshr miss latency 1205system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 137049.600000 # average SCUpgradeFailReq mshr miss latency 1206system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 56538.614908 # average ReadExReq mshr miss latency 1207system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 56538.614908 # average ReadExReq mshr miss latency 1208system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 65605.366449 # average ReadCleanReq mshr miss latency 1209system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65605.366449 # average ReadCleanReq mshr miss latency 1210system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28270.224035 # average ReadSharedReq mshr miss latency 1211system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28270.224035 # average ReadSharedReq mshr miss latency 1212system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 21548.076923 # average overall mshr miss latency 1213system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 21006.666667 # average overall mshr miss latency 1214system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 65605.366449 # average overall mshr miss latency 1215system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 36920.891101 # average overall mshr miss latency 1216system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 44123.948519 # average overall mshr miss latency 1217system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 21548.076923 # average overall mshr miss latency 1218system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 21006.666667 # average overall mshr miss latency 1219system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 65605.366449 # average overall mshr miss latency 1220system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 36920.891101 # average overall mshr miss latency 1221system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 77179.151703 # average overall mshr miss latency 1222system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 63704.390920 # average overall mshr miss latency 1223system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509 # average ReadReq mshr uncacheable latency 1224system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200329.807964 # average ReadReq mshr uncacheable latency 1225system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 185119.738485 # average ReadReq mshr uncacheable latency 1226system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182008.368715 # average WriteReq mshr uncacheable latency 1227system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 182008.368715 # average WriteReq mshr uncacheable latency 1228system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509 # average overall mshr uncacheable latency 1229system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 191673.022084 # average overall mshr uncacheable latency 1230system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 183840.916958 # average overall mshr uncacheable latency 1231system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1232system.cpu0.toL2Bus.snoop_filter.tot_requests 3905427 # Total number of requests made to the snoop filter. 1233system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1969134 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1234system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 28903 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1235system.cpu0.toL2Bus.snoop_filter.tot_snoops 319838 # Total number of snoops made to the snoop filter. 1236system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 316964 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1237system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 2874 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1238system.cpu0.toL2Bus.trans_dist::ReadReq 63699 # Transaction distribution 1239system.cpu0.toL2Bus.trans_dist::ReadResp 1766064 # Transaction distribution 1240system.cpu0.toL2Bus.trans_dist::WriteReq 28499 # Transaction distribution 1241system.cpu0.toL2Bus.trans_dist::WriteResp 28499 # Transaction distribution 1242system.cpu0.toL2Bus.trans_dist::WritebackDirty 734457 # Transaction distribution 1243system.cpu0.toL2Bus.trans_dist::WritebackClean 1378164 # Transaction distribution 1244system.cpu0.toL2Bus.trans_dist::CleanEvict 189732 # Transaction distribution 1245system.cpu0.toL2Bus.trans_dist::HardPFReq 311664 # Transaction distribution 1246system.cpu0.toL2Bus.trans_dist::UpgradeReq 85807 # Transaction distribution 1247system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 41981 # Transaction distribution 1248system.cpu0.toL2Bus.trans_dist::UpgradeResp 112714 # Transaction distribution 1249system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 57 # Transaction distribution 1250system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 104 # Transaction distribution 1251system.cpu0.toL2Bus.trans_dist::ReadExReq 301438 # Transaction distribution 1252system.cpu0.toL2Bus.trans_dist::ReadExResp 298033 # Transaction distribution 1253system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1147547 # Transaction distribution 1254system.cpu0.toL2Bus.trans_dist::ReadSharedReq 575765 # Transaction distribution 1255system.cpu0.toL2Bus.trans_dist::InvalidateReq 3263 # Transaction distribution 1256system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3460164 # Packet count per connected master and slave (bytes) 1257system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2683424 # Packet count per connected master and slave (bytes) 1258system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12059 # Packet count per connected master and slave (bytes) 1259system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 27146 # Packet count per connected master and slave (bytes) 1260system.cpu0.toL2Bus.pkt_count::total 6182793 # Packet count per connected master and slave (bytes) 1261system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 146888760 # Cumulative packet size per connected master and slave (bytes) 1262system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 101708758 # Cumulative packet size per connected master and slave (bytes) 1263system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 20124 # Cumulative packet size per connected master and slave (bytes) 1264system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 45328 # Cumulative packet size per connected master and slave (bytes) 1265system.cpu0.toL2Bus.pkt_size::total 248662970 # Cumulative packet size per connected master and slave (bytes) 1266system.cpu0.toL2Bus.snoops 986506 # Total snoops (count) 1267system.cpu0.toL2Bus.snoop_fanout::samples 2981817 # Request fanout histogram 1268system.cpu0.toL2Bus.snoop_fanout::mean 0.122538 # Request fanout histogram 1269system.cpu0.toL2Bus.snoop_fanout::stdev 0.330833 # Request fanout histogram 1270system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1271system.cpu0.toL2Bus.snoop_fanout::0 2619305 87.84% 87.84% # Request fanout histogram 1272system.cpu0.toL2Bus.snoop_fanout::1 359638 12.06% 99.90% # Request fanout histogram 1273system.cpu0.toL2Bus.snoop_fanout::2 2874 0.10% 100.00% # Request fanout histogram 1274system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1275system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1276system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1277system.cpu0.toL2Bus.snoop_fanout::total 2981817 # Request fanout histogram 1278system.cpu0.toL2Bus.reqLayer0.occupancy 3886437494 # Layer occupancy (ticks) 1279system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1280system.cpu0.toL2Bus.snoopLayer0.occupancy 115091926 # Layer occupancy (ticks) 1281system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1282system.cpu0.toL2Bus.respLayer0.occupancy 1730342500 # Layer occupancy (ticks) 1283system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1284system.cpu0.toL2Bus.respLayer1.occupancy 1266858980 # Layer occupancy (ticks) 1285system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1286system.cpu0.toL2Bus.respLayer2.occupancy 7028000 # Layer occupancy (ticks) 1287system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1288system.cpu0.toL2Bus.respLayer3.occupancy 15821984 # Layer occupancy (ticks) 1289system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1290system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1291system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1292system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1293system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1294system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1295system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1296system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1297system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1298system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1299system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1300system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1301system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1302system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1303system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1304system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1305system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1306system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1307system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1308system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1309system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1310system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1311system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1312system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1313system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1314system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1315system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1316system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1317system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1318system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1319system.cpu1.dtb.walker.walks 2347 # Table walker walks requested 1320system.cpu1.dtb.walker.walksShort 2347 # Table walker walks initiated with short descriptors 1321system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 475 # Level at which table walker walks with short descriptors terminate 1322system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1872 # Level at which table walker walks with short descriptors terminate 1323system.cpu1.dtb.walker.walkWaitTime::samples 2347 # Table walker wait (enqueue to first request) latency 1324system.cpu1.dtb.walker.walkWaitTime::0 2347 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1325system.cpu1.dtb.walker.walkWaitTime::total 2347 # Table walker wait (enqueue to first request) latency 1326system.cpu1.dtb.walker.walkCompletionTime::samples 1701 # Table walker service (enqueue to completion) latency 1327system.cpu1.dtb.walker.walkCompletionTime::mean 11647.854203 # Table walker service (enqueue to completion) latency 1328system.cpu1.dtb.walker.walkCompletionTime::gmean 11021.395784 # Table walker service (enqueue to completion) latency 1329system.cpu1.dtb.walker.walkCompletionTime::stdev 4763.004778 # Table walker service (enqueue to completion) latency 1330system.cpu1.dtb.walker.walkCompletionTime::0-4095 3 0.18% 0.18% # Table walker service (enqueue to completion) latency 1331system.cpu1.dtb.walker.walkCompletionTime::4096-8191 360 21.16% 21.34% # Table walker service (enqueue to completion) latency 1332system.cpu1.dtb.walker.walkCompletionTime::8192-12287 989 58.14% 79.48% # Table walker service (enqueue to completion) latency 1333system.cpu1.dtb.walker.walkCompletionTime::12288-16383 206 12.11% 91.59% # Table walker service (enqueue to completion) latency 1334system.cpu1.dtb.walker.walkCompletionTime::16384-20479 34 2.00% 93.59% # Table walker service (enqueue to completion) latency 1335system.cpu1.dtb.walker.walkCompletionTime::20480-24575 60 3.53% 97.12% # Table walker service (enqueue to completion) latency 1336system.cpu1.dtb.walker.walkCompletionTime::24576-28671 28 1.65% 98.77% # Table walker service (enqueue to completion) latency 1337system.cpu1.dtb.walker.walkCompletionTime::28672-32767 11 0.65% 99.41% # Table walker service (enqueue to completion) latency 1338system.cpu1.dtb.walker.walkCompletionTime::32768-36863 1 0.06% 99.47% # Table walker service (enqueue to completion) latency 1339system.cpu1.dtb.walker.walkCompletionTime::36864-40959 2 0.12% 99.59% # Table walker service (enqueue to completion) latency 1340system.cpu1.dtb.walker.walkCompletionTime::40960-45055 3 0.18% 99.76% # Table walker service (enqueue to completion) latency 1341system.cpu1.dtb.walker.walkCompletionTime::49152-53247 3 0.18% 99.94% # Table walker service (enqueue to completion) latency 1342system.cpu1.dtb.walker.walkCompletionTime::57344-61439 1 0.06% 100.00% # Table walker service (enqueue to completion) latency 1343system.cpu1.dtb.walker.walkCompletionTime::total 1701 # Table walker service (enqueue to completion) latency 1344system.cpu1.dtb.walker.walksPending::samples -1207257828 # Table walker pending requests distribution 1345system.cpu1.dtb.walker.walksPending::0 -1207257828 100.00% 100.00% # Table walker pending requests distribution 1346system.cpu1.dtb.walker.walksPending::total -1207257828 # Table walker pending requests distribution 1347system.cpu1.dtb.walker.walkPageSizes::4K 1226 72.08% 72.08% # Table walker page sizes translated 1348system.cpu1.dtb.walker.walkPageSizes::1M 475 27.92% 100.00% # Table walker page sizes translated 1349system.cpu1.dtb.walker.walkPageSizes::total 1701 # Table walker page sizes translated 1350system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 2347 # Table walker requests started/completed, data/inst 1351system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1352system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 2347 # Table walker requests started/completed, data/inst 1353system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1701 # Table walker requests started/completed, data/inst 1354system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1355system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1701 # Table walker requests started/completed, data/inst 1356system.cpu1.dtb.walker.walkRequestOrigin::total 4048 # Table walker requests started/completed, data/inst 1357system.cpu1.dtb.inst_hits 0 # ITB inst hits 1358system.cpu1.dtb.inst_misses 0 # ITB inst misses 1359system.cpu1.dtb.read_hits 3334777 # DTB read hits 1360system.cpu1.dtb.read_misses 1951 # DTB read misses 1361system.cpu1.dtb.write_hits 2915290 # DTB write hits 1362system.cpu1.dtb.write_misses 396 # DTB write misses 1363system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1364system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1365system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1366system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1367system.cpu1.dtb.flush_entries 1652 # Number of entries that have been flushed from TLB 1368system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 1369system.cpu1.dtb.prefetch_faults 260 # Number of TLB faults due to prefetch 1370system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1371system.cpu1.dtb.perms_faults 124 # Number of TLB faults due to permissions restrictions 1372system.cpu1.dtb.read_accesses 3336728 # DTB read accesses 1373system.cpu1.dtb.write_accesses 2915686 # DTB write accesses 1374system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1375system.cpu1.dtb.hits 6250067 # DTB hits 1376system.cpu1.dtb.misses 2347 # DTB misses 1377system.cpu1.dtb.accesses 6252414 # DTB accesses 1378system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1379system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1380system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1381system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1382system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1383system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1384system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1385system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1386system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1387system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1388system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1389system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1390system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1391system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1392system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1393system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1394system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1395system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1396system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1397system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1398system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1399system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1400system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1401system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1402system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1403system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1404system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1405system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1406system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1407system.cpu1.itb.walker.walks 1376 # Table walker walks requested 1408system.cpu1.itb.walker.walksShort 1376 # Table walker walks initiated with short descriptors 1409system.cpu1.itb.walker.walksShortTerminationLevel::Level1 134 # Level at which table walker walks with short descriptors terminate 1410system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1242 # Level at which table walker walks with short descriptors terminate 1411system.cpu1.itb.walker.walkWaitTime::samples 1376 # Table walker wait (enqueue to first request) latency 1412system.cpu1.itb.walker.walkWaitTime::0 1376 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1413system.cpu1.itb.walker.walkWaitTime::total 1376 # Table walker wait (enqueue to first request) latency 1414system.cpu1.itb.walker.walkCompletionTime::samples 819 # Table walker service (enqueue to completion) latency 1415system.cpu1.itb.walker.walkCompletionTime::mean 11933.455433 # Table walker service (enqueue to completion) latency 1416system.cpu1.itb.walker.walkCompletionTime::gmean 11302.540712 # Table walker service (enqueue to completion) latency 1417system.cpu1.itb.walker.walkCompletionTime::stdev 5121.103483 # Table walker service (enqueue to completion) latency 1418system.cpu1.itb.walker.walkCompletionTime::4096-8191 113 13.80% 13.80% # Table walker service (enqueue to completion) latency 1419system.cpu1.itb.walker.walkCompletionTime::8192-12287 572 69.84% 83.64% # Table walker service (enqueue to completion) latency 1420system.cpu1.itb.walker.walkCompletionTime::12288-16383 87 10.62% 94.26% # Table walker service (enqueue to completion) latency 1421system.cpu1.itb.walker.walkCompletionTime::16384-20479 7 0.85% 95.12% # Table walker service (enqueue to completion) latency 1422system.cpu1.itb.walker.walkCompletionTime::20480-24575 1 0.12% 95.24% # Table walker service (enqueue to completion) latency 1423system.cpu1.itb.walker.walkCompletionTime::24576-28671 23 2.81% 98.05% # Table walker service (enqueue to completion) latency 1424system.cpu1.itb.walker.walkCompletionTime::28672-32767 8 0.98% 99.02% # Table walker service (enqueue to completion) latency 1425system.cpu1.itb.walker.walkCompletionTime::36864-40959 4 0.49% 99.51% # Table walker service (enqueue to completion) latency 1426system.cpu1.itb.walker.walkCompletionTime::40960-45055 2 0.24% 99.76% # Table walker service (enqueue to completion) latency 1427system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.12% 99.88% # Table walker service (enqueue to completion) latency 1428system.cpu1.itb.walker.walkCompletionTime::57344-61439 1 0.12% 100.00% # Table walker service (enqueue to completion) latency 1429system.cpu1.itb.walker.walkCompletionTime::total 819 # Table walker service (enqueue to completion) latency 1430system.cpu1.itb.walker.walksPending::samples -1208095828 # Table walker pending requests distribution 1431system.cpu1.itb.walker.walksPending::0 -1208095828 100.00% 100.00% # Table walker pending requests distribution 1432system.cpu1.itb.walker.walksPending::total -1208095828 # Table walker pending requests distribution 1433system.cpu1.itb.walker.walkPageSizes::4K 685 83.64% 83.64% # Table walker page sizes translated 1434system.cpu1.itb.walker.walkPageSizes::1M 134 16.36% 100.00% # Table walker page sizes translated 1435system.cpu1.itb.walker.walkPageSizes::total 819 # Table walker page sizes translated 1436system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1437system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1376 # Table walker requests started/completed, data/inst 1438system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1376 # Table walker requests started/completed, data/inst 1439system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1440system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 819 # Table walker requests started/completed, data/inst 1441system.cpu1.itb.walker.walkRequestOrigin_Completed::total 819 # Table walker requests started/completed, data/inst 1442system.cpu1.itb.walker.walkRequestOrigin::total 2195 # Table walker requests started/completed, data/inst 1443system.cpu1.itb.inst_hits 13921759 # ITB inst hits 1444system.cpu1.itb.inst_misses 1376 # ITB inst misses 1445system.cpu1.itb.read_hits 0 # DTB read hits 1446system.cpu1.itb.read_misses 0 # DTB read misses 1447system.cpu1.itb.write_hits 0 # DTB write hits 1448system.cpu1.itb.write_misses 0 # DTB write misses 1449system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1450system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1451system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1452system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1453system.cpu1.itb.flush_entries 883 # Number of entries that have been flushed from TLB 1454system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1455system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1456system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1457system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1458system.cpu1.itb.read_accesses 0 # DTB read accesses 1459system.cpu1.itb.write_accesses 0 # DTB write accesses 1460system.cpu1.itb.inst_accesses 13923135 # ITB inst accesses 1461system.cpu1.itb.hits 13921759 # DTB hits 1462system.cpu1.itb.misses 1376 # DTB misses 1463system.cpu1.itb.accesses 13923135 # DTB accesses 1464system.cpu1.numCycles 5742672703 # number of cpu cycles simulated 1465system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1466system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1467system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1468system.cpu1.kern.inst.quiesce 2702 # number of quiesce instructions executed 1469system.cpu1.committedInsts 13722686 # Number of instructions committed 1470system.cpu1.committedOps 16717642 # Number of ops (including micro ops) committed 1471system.cpu1.num_int_alu_accesses 15156242 # Number of integer alu accesses 1472system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses 1473system.cpu1.num_func_calls 915130 # number of times a function call or return occured 1474system.cpu1.num_conditional_control_insts 1497977 # number of instructions that are conditional controls 1475system.cpu1.num_int_insts 15156242 # number of integer instructions 1476system.cpu1.num_fp_insts 0 # number of float instructions 1477system.cpu1.num_int_register_reads 27539507 # number of times the integer registers were read 1478system.cpu1.num_int_register_writes 10698774 # number of times the integer registers were written 1479system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read 1480system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written 1481system.cpu1.num_cc_register_reads 61342237 # number of times the CC registers were read 1482system.cpu1.num_cc_register_writes 5194989 # number of times the CC registers were written 1483system.cpu1.num_mem_refs 6464220 # number of memory refs 1484system.cpu1.num_load_insts 3439445 # Number of load instructions 1485system.cpu1.num_store_insts 3024775 # Number of store instructions 1486system.cpu1.num_idle_cycles 5696078911.641530 # Number of idle cycles 1487system.cpu1.num_busy_cycles 46593791.358469 # Number of busy cycles 1488system.cpu1.not_idle_fraction 0.008114 # Percentage of non-idle cycles 1489system.cpu1.idle_fraction 0.991886 # Percentage of idle cycles 1490system.cpu1.Branches 2464409 # Number of branches fetched 1491system.cpu1.op_class::No_OpClass 24 0.00% 0.00% # Class of executed instruction 1492system.cpu1.op_class::IntAlu 10544854 61.90% 61.90% # Class of executed instruction 1493system.cpu1.op_class::IntMult 24300 0.14% 62.04% # Class of executed instruction 1494system.cpu1.op_class::IntDiv 0 0.00% 62.04% # Class of executed instruction 1495system.cpu1.op_class::FloatAdd 0 0.00% 62.04% # Class of executed instruction 1496system.cpu1.op_class::FloatCmp 0 0.00% 62.04% # Class of executed instruction 1497system.cpu1.op_class::FloatCvt 0 0.00% 62.04% # Class of executed instruction 1498system.cpu1.op_class::FloatMult 0 0.00% 62.04% # Class of executed instruction 1499system.cpu1.op_class::FloatDiv 0 0.00% 62.04% # Class of executed instruction 1500system.cpu1.op_class::FloatSqrt 0 0.00% 62.04% # Class of executed instruction 1501system.cpu1.op_class::SimdAdd 0 0.00% 62.04% # Class of executed instruction 1502system.cpu1.op_class::SimdAddAcc 0 0.00% 62.04% # Class of executed instruction 1503system.cpu1.op_class::SimdAlu 0 0.00% 62.04% # Class of executed instruction 1504system.cpu1.op_class::SimdCmp 0 0.00% 62.04% # Class of executed instruction 1505system.cpu1.op_class::SimdCvt 0 0.00% 62.04% # Class of executed instruction 1506system.cpu1.op_class::SimdMisc 0 0.00% 62.04% # Class of executed instruction 1507system.cpu1.op_class::SimdMult 0 0.00% 62.04% # Class of executed instruction 1508system.cpu1.op_class::SimdMultAcc 0 0.00% 62.04% # Class of executed instruction 1509system.cpu1.op_class::SimdShift 0 0.00% 62.04% # Class of executed instruction 1510system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.04% # Class of executed instruction 1511system.cpu1.op_class::SimdSqrt 0 0.00% 62.04% # Class of executed instruction 1512system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.04% # Class of executed instruction 1513system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.04% # Class of executed instruction 1514system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.04% # Class of executed instruction 1515system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.04% # Class of executed instruction 1516system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.04% # Class of executed instruction 1517system.cpu1.op_class::SimdFloatMisc 3186 0.02% 62.06% # Class of executed instruction 1518system.cpu1.op_class::SimdFloatMult 0 0.00% 62.06% # Class of executed instruction 1519system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.06% # Class of executed instruction 1520system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.06% # Class of executed instruction 1521system.cpu1.op_class::MemRead 3439445 20.19% 82.25% # Class of executed instruction 1522system.cpu1.op_class::MemWrite 3024775 17.75% 100.00% # Class of executed instruction 1523system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 1524system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 1525system.cpu1.op_class::total 17036584 # Class of executed instruction 1526system.cpu1.dcache.tags.replacements 148452 # number of replacements 1527system.cpu1.dcache.tags.tagsinuse 468.602887 # Cycle average of tags in use 1528system.cpu1.dcache.tags.total_refs 6022671 # Total number of references to valid blocks. 1529system.cpu1.dcache.tags.sampled_refs 148794 # Sample count of references to valid blocks. 1530system.cpu1.dcache.tags.avg_refs 40.476572 # Average number of references to valid blocks. 1531system.cpu1.dcache.tags.warmup_cycle 106290860000 # Cycle when the warmup percentage was hit. 1532system.cpu1.dcache.tags.occ_blocks::cpu1.data 468.602887 # Average occupied blocks per requestor 1533system.cpu1.dcache.tags.occ_percent::cpu1.data 0.915240 # Average percentage of cache occupancy 1534system.cpu1.dcache.tags.occ_percent::total 0.915240 # Average percentage of cache occupancy 1535system.cpu1.dcache.tags.occ_task_id_blocks::1024 342 # Occupied blocks per task id 1536system.cpu1.dcache.tags.age_task_id_blocks_1024::2 306 # Occupied blocks per task id 1537system.cpu1.dcache.tags.age_task_id_blocks_1024::3 36 # Occupied blocks per task id 1538system.cpu1.dcache.tags.occ_task_id_percent::1024 0.667969 # Percentage of cache occupancy per task id 1539system.cpu1.dcache.tags.tag_accesses 12680857 # Number of tag accesses 1540system.cpu1.dcache.tags.data_accesses 12680857 # Number of data accesses 1541system.cpu1.dcache.ReadReq_hits::cpu1.data 3066042 # number of ReadReq hits 1542system.cpu1.dcache.ReadReq_hits::total 3066042 # number of ReadReq hits 1543system.cpu1.dcache.WriteReq_hits::cpu1.data 2748534 # number of WriteReq hits 1544system.cpu1.dcache.WriteReq_hits::total 2748534 # number of WriteReq hits 1545system.cpu1.dcache.SoftPFReq_hits::cpu1.data 41898 # number of SoftPFReq hits 1546system.cpu1.dcache.SoftPFReq_hits::total 41898 # number of SoftPFReq hits 1547system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 69885 # number of LoadLockedReq hits 1548system.cpu1.dcache.LoadLockedReq_hits::total 69885 # number of LoadLockedReq hits 1549system.cpu1.dcache.StoreCondReq_hits::cpu1.data 61599 # number of StoreCondReq hits 1550system.cpu1.dcache.StoreCondReq_hits::total 61599 # number of StoreCondReq hits 1551system.cpu1.dcache.demand_hits::cpu1.data 5814576 # number of demand (read+write) hits 1552system.cpu1.dcache.demand_hits::total 5814576 # number of demand (read+write) hits 1553system.cpu1.dcache.overall_hits::cpu1.data 5856474 # number of overall hits 1554system.cpu1.dcache.overall_hits::total 5856474 # number of overall hits 1555system.cpu1.dcache.ReadReq_misses::cpu1.data 112908 # number of ReadReq misses 1556system.cpu1.dcache.ReadReq_misses::total 112908 # number of ReadReq misses 1557system.cpu1.dcache.WriteReq_misses::cpu1.data 79472 # number of WriteReq misses 1558system.cpu1.dcache.WriteReq_misses::total 79472 # number of WriteReq misses 1559system.cpu1.dcache.SoftPFReq_misses::cpu1.data 24389 # number of SoftPFReq misses 1560system.cpu1.dcache.SoftPFReq_misses::total 24389 # number of SoftPFReq misses 1561system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16600 # number of LoadLockedReq misses 1562system.cpu1.dcache.LoadLockedReq_misses::total 16600 # number of LoadLockedReq misses 1563system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23097 # number of StoreCondReq misses 1564system.cpu1.dcache.StoreCondReq_misses::total 23097 # number of StoreCondReq misses 1565system.cpu1.dcache.demand_misses::cpu1.data 192380 # number of demand (read+write) misses 1566system.cpu1.dcache.demand_misses::total 192380 # number of demand (read+write) misses 1567system.cpu1.dcache.overall_misses::cpu1.data 216769 # number of overall misses 1568system.cpu1.dcache.overall_misses::total 216769 # number of overall misses 1569system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1761858500 # number of ReadReq miss cycles 1570system.cpu1.dcache.ReadReq_miss_latency::total 1761858500 # number of ReadReq miss cycles 1571system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2707072000 # number of WriteReq miss cycles 1572system.cpu1.dcache.WriteReq_miss_latency::total 2707072000 # number of WriteReq miss cycles 1573system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 321180000 # number of LoadLockedReq miss cycles 1574system.cpu1.dcache.LoadLockedReq_miss_latency::total 321180000 # number of LoadLockedReq miss cycles 1575system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 626224500 # number of StoreCondReq miss cycles 1576system.cpu1.dcache.StoreCondReq_miss_latency::total 626224500 # number of StoreCondReq miss cycles 1577system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 5032000 # number of StoreCondFailReq miss cycles 1578system.cpu1.dcache.StoreCondFailReq_miss_latency::total 5032000 # number of StoreCondFailReq miss cycles 1579system.cpu1.dcache.demand_miss_latency::cpu1.data 4468930500 # number of demand (read+write) miss cycles 1580system.cpu1.dcache.demand_miss_latency::total 4468930500 # number of demand (read+write) miss cycles 1581system.cpu1.dcache.overall_miss_latency::cpu1.data 4468930500 # number of overall miss cycles 1582system.cpu1.dcache.overall_miss_latency::total 4468930500 # number of overall miss cycles 1583system.cpu1.dcache.ReadReq_accesses::cpu1.data 3178950 # number of ReadReq accesses(hits+misses) 1584system.cpu1.dcache.ReadReq_accesses::total 3178950 # number of ReadReq accesses(hits+misses) 1585system.cpu1.dcache.WriteReq_accesses::cpu1.data 2828006 # number of WriteReq accesses(hits+misses) 1586system.cpu1.dcache.WriteReq_accesses::total 2828006 # number of WriteReq accesses(hits+misses) 1587system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 66287 # number of SoftPFReq accesses(hits+misses) 1588system.cpu1.dcache.SoftPFReq_accesses::total 66287 # number of SoftPFReq accesses(hits+misses) 1589system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 86485 # number of LoadLockedReq accesses(hits+misses) 1590system.cpu1.dcache.LoadLockedReq_accesses::total 86485 # number of LoadLockedReq accesses(hits+misses) 1591system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 84696 # number of StoreCondReq accesses(hits+misses) 1592system.cpu1.dcache.StoreCondReq_accesses::total 84696 # number of StoreCondReq accesses(hits+misses) 1593system.cpu1.dcache.demand_accesses::cpu1.data 6006956 # number of demand (read+write) accesses 1594system.cpu1.dcache.demand_accesses::total 6006956 # number of demand (read+write) accesses 1595system.cpu1.dcache.overall_accesses::cpu1.data 6073243 # number of overall (read+write) accesses 1596system.cpu1.dcache.overall_accesses::total 6073243 # number of overall (read+write) accesses 1597system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035517 # miss rate for ReadReq accesses 1598system.cpu1.dcache.ReadReq_miss_rate::total 0.035517 # miss rate for ReadReq accesses 1599system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.028102 # miss rate for WriteReq accesses 1600system.cpu1.dcache.WriteReq_miss_rate::total 0.028102 # miss rate for WriteReq accesses 1601system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.367930 # miss rate for SoftPFReq accesses 1602system.cpu1.dcache.SoftPFReq_miss_rate::total 0.367930 # miss rate for SoftPFReq accesses 1603system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.191941 # miss rate for LoadLockedReq accesses 1604system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.191941 # miss rate for LoadLockedReq accesses 1605system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.272705 # miss rate for StoreCondReq accesses 1606system.cpu1.dcache.StoreCondReq_miss_rate::total 0.272705 # miss rate for StoreCondReq accesses 1607system.cpu1.dcache.demand_miss_rate::cpu1.data 0.032026 # miss rate for demand accesses 1608system.cpu1.dcache.demand_miss_rate::total 0.032026 # miss rate for demand accesses 1609system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035692 # miss rate for overall accesses 1610system.cpu1.dcache.overall_miss_rate::total 0.035692 # miss rate for overall accesses 1611system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15604.372587 # average ReadReq miss latency 1612system.cpu1.dcache.ReadReq_avg_miss_latency::total 15604.372587 # average ReadReq miss latency 1613system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34063.217234 # average WriteReq miss latency 1614system.cpu1.dcache.WriteReq_avg_miss_latency::total 34063.217234 # average WriteReq miss latency 1615system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19348.192771 # average LoadLockedReq miss latency 1616system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19348.192771 # average LoadLockedReq miss latency 1617system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27112.806858 # average StoreCondReq miss latency 1618system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27112.806858 # average StoreCondReq miss latency 1619system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1620system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1621system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23229.704231 # average overall miss latency 1622system.cpu1.dcache.demand_avg_miss_latency::total 23229.704231 # average overall miss latency 1623system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20616.095936 # average overall miss latency 1624system.cpu1.dcache.overall_avg_miss_latency::total 20616.095936 # average overall miss latency 1625system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1626system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1627system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1628system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1629system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1630system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1631system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1632system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1633system.cpu1.dcache.writebacks::writebacks 148452 # number of writebacks 1634system.cpu1.dcache.writebacks::total 148452 # number of writebacks 1635system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 223 # number of ReadReq MSHR hits 1636system.cpu1.dcache.ReadReq_mshr_hits::total 223 # number of ReadReq MSHR hits 1637system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 11671 # number of LoadLockedReq MSHR hits 1638system.cpu1.dcache.LoadLockedReq_mshr_hits::total 11671 # number of LoadLockedReq MSHR hits 1639system.cpu1.dcache.demand_mshr_hits::cpu1.data 223 # number of demand (read+write) MSHR hits 1640system.cpu1.dcache.demand_mshr_hits::total 223 # number of demand (read+write) MSHR hits 1641system.cpu1.dcache.overall_mshr_hits::cpu1.data 223 # number of overall MSHR hits 1642system.cpu1.dcache.overall_mshr_hits::total 223 # number of overall MSHR hits 1643system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 112685 # number of ReadReq MSHR misses 1644system.cpu1.dcache.ReadReq_mshr_misses::total 112685 # number of ReadReq MSHR misses 1645system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 79472 # number of WriteReq MSHR misses 1646system.cpu1.dcache.WriteReq_mshr_misses::total 79472 # number of WriteReq MSHR misses 1647system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 23925 # number of SoftPFReq MSHR misses 1648system.cpu1.dcache.SoftPFReq_mshr_misses::total 23925 # number of SoftPFReq MSHR misses 1649system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4929 # number of LoadLockedReq MSHR misses 1650system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4929 # number of LoadLockedReq MSHR misses 1651system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23097 # number of StoreCondReq MSHR misses 1652system.cpu1.dcache.StoreCondReq_mshr_misses::total 23097 # number of StoreCondReq MSHR misses 1653system.cpu1.dcache.demand_mshr_misses::cpu1.data 192157 # number of demand (read+write) MSHR misses 1654system.cpu1.dcache.demand_mshr_misses::total 192157 # number of demand (read+write) MSHR misses 1655system.cpu1.dcache.overall_mshr_misses::cpu1.data 216082 # number of overall MSHR misses 1656system.cpu1.dcache.overall_mshr_misses::total 216082 # number of overall MSHR misses 1657system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3082 # number of ReadReq MSHR uncacheable 1658system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3082 # number of ReadReq MSHR uncacheable 1659system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2423 # number of WriteReq MSHR uncacheable 1660system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2423 # number of WriteReq MSHR uncacheable 1661system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5505 # number of overall MSHR uncacheable misses 1662system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5505 # number of overall MSHR uncacheable misses 1663system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1634927500 # number of ReadReq MSHR miss cycles 1664system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1634927500 # number of ReadReq MSHR miss cycles 1665system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2627600000 # number of WriteReq MSHR miss cycles 1666system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2627600000 # number of WriteReq MSHR miss cycles 1667system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 437401500 # number of SoftPFReq MSHR miss cycles 1668system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 437401500 # number of SoftPFReq MSHR miss cycles 1669system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 91610500 # number of LoadLockedReq MSHR miss cycles 1670system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 91610500 # number of LoadLockedReq MSHR miss cycles 1671system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 603174500 # number of StoreCondReq MSHR miss cycles 1672system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 603174500 # number of StoreCondReq MSHR miss cycles 1673system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 4985000 # number of StoreCondFailReq MSHR miss cycles 1674system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 4985000 # number of StoreCondFailReq MSHR miss cycles 1675system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4262527500 # number of demand (read+write) MSHR miss cycles 1676system.cpu1.dcache.demand_mshr_miss_latency::total 4262527500 # number of demand (read+write) MSHR miss cycles 1677system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4699929000 # number of overall MSHR miss cycles 1678system.cpu1.dcache.overall_mshr_miss_latency::total 4699929000 # number of overall MSHR miss cycles 1679system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 439527500 # number of ReadReq MSHR uncacheable cycles 1680system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 439527500 # number of ReadReq MSHR uncacheable cycles 1681system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 303136500 # number of WriteReq MSHR uncacheable cycles 1682system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 303136500 # number of WriteReq MSHR uncacheable cycles 1683system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 742664000 # number of overall MSHR uncacheable cycles 1684system.cpu1.dcache.overall_mshr_uncacheable_latency::total 742664000 # number of overall MSHR uncacheable cycles 1685system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035447 # mshr miss rate for ReadReq accesses 1686system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035447 # mshr miss rate for ReadReq accesses 1687system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028102 # mshr miss rate for WriteReq accesses 1688system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028102 # mshr miss rate for WriteReq accesses 1689system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.360930 # mshr miss rate for SoftPFReq accesses 1690system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.360930 # mshr miss rate for SoftPFReq accesses 1691system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.056993 # mshr miss rate for LoadLockedReq accesses 1692system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.056993 # mshr miss rate for LoadLockedReq accesses 1693system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.272705 # mshr miss rate for StoreCondReq accesses 1694system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.272705 # mshr miss rate for StoreCondReq accesses 1695system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031989 # mshr miss rate for demand accesses 1696system.cpu1.dcache.demand_mshr_miss_rate::total 0.031989 # mshr miss rate for demand accesses 1697system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035579 # mshr miss rate for overall accesses 1698system.cpu1.dcache.overall_mshr_miss_rate::total 0.035579 # mshr miss rate for overall accesses 1699system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14508.829924 # average ReadReq mshr miss latency 1700system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14508.829924 # average ReadReq mshr miss latency 1701system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33063.217234 # average WriteReq mshr miss latency 1702system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33063.217234 # average WriteReq mshr miss latency 1703system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18282.194357 # average SoftPFReq mshr miss latency 1704system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 18282.194357 # average SoftPFReq mshr miss latency 1705system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18586.021505 # average LoadLockedReq mshr miss latency 1706system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18586.021505 # average LoadLockedReq mshr miss latency 1707system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26114.841754 # average StoreCondReq mshr miss latency 1708system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26114.841754 # average StoreCondReq mshr miss latency 1709system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1710system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1711system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22182.525227 # average overall mshr miss latency 1712system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22182.525227 # average overall mshr miss latency 1713system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21750.673355 # average overall mshr miss latency 1714system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21750.673355 # average overall mshr miss latency 1715system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 142611.129137 # average ReadReq mshr uncacheable latency 1716system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 142611.129137 # average ReadReq mshr uncacheable latency 1717system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 125107.924061 # average WriteReq mshr uncacheable latency 1718system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 125107.924061 # average WriteReq mshr uncacheable latency 1719system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 134907.175295 # average overall mshr uncacheable latency 1720system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 134907.175295 # average overall mshr uncacheable latency 1721system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1722system.cpu1.icache.tags.replacements 463484 # number of replacements 1723system.cpu1.icache.tags.tagsinuse 498.310914 # Cycle average of tags in use 1724system.cpu1.icache.tags.total_refs 13457758 # Total number of references to valid blocks. 1725system.cpu1.icache.tags.sampled_refs 463996 # Sample count of references to valid blocks. 1726system.cpu1.icache.tags.avg_refs 29.004039 # Average number of references to valid blocks. 1727system.cpu1.icache.tags.warmup_cycle 106358922000 # Cycle when the warmup percentage was hit. 1728system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.310914 # Average occupied blocks per requestor 1729system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973264 # Average percentage of cache occupancy 1730system.cpu1.icache.tags.occ_percent::total 0.973264 # Average percentage of cache occupancy 1731system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1732system.cpu1.icache.tags.age_task_id_blocks_1024::2 387 # Occupied blocks per task id 1733system.cpu1.icache.tags.age_task_id_blocks_1024::3 118 # Occupied blocks per task id 1734system.cpu1.icache.tags.age_task_id_blocks_1024::4 7 # Occupied blocks per task id 1735system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1736system.cpu1.icache.tags.tag_accesses 28307504 # Number of tag accesses 1737system.cpu1.icache.tags.data_accesses 28307504 # Number of data accesses 1738system.cpu1.icache.ReadReq_hits::cpu1.inst 13457758 # number of ReadReq hits 1739system.cpu1.icache.ReadReq_hits::total 13457758 # number of ReadReq hits 1740system.cpu1.icache.demand_hits::cpu1.inst 13457758 # number of demand (read+write) hits 1741system.cpu1.icache.demand_hits::total 13457758 # number of demand (read+write) hits 1742system.cpu1.icache.overall_hits::cpu1.inst 13457758 # number of overall hits 1743system.cpu1.icache.overall_hits::total 13457758 # number of overall hits 1744system.cpu1.icache.ReadReq_misses::cpu1.inst 463996 # number of ReadReq misses 1745system.cpu1.icache.ReadReq_misses::total 463996 # number of ReadReq misses 1746system.cpu1.icache.demand_misses::cpu1.inst 463996 # number of demand (read+write) misses 1747system.cpu1.icache.demand_misses::total 463996 # number of demand (read+write) misses 1748system.cpu1.icache.overall_misses::cpu1.inst 463996 # number of overall misses 1749system.cpu1.icache.overall_misses::total 463996 # number of overall misses 1750system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4214067500 # number of ReadReq miss cycles 1751system.cpu1.icache.ReadReq_miss_latency::total 4214067500 # number of ReadReq miss cycles 1752system.cpu1.icache.demand_miss_latency::cpu1.inst 4214067500 # number of demand (read+write) miss cycles 1753system.cpu1.icache.demand_miss_latency::total 4214067500 # number of demand (read+write) miss cycles 1754system.cpu1.icache.overall_miss_latency::cpu1.inst 4214067500 # number of overall miss cycles 1755system.cpu1.icache.overall_miss_latency::total 4214067500 # number of overall miss cycles 1756system.cpu1.icache.ReadReq_accesses::cpu1.inst 13921754 # number of ReadReq accesses(hits+misses) 1757system.cpu1.icache.ReadReq_accesses::total 13921754 # number of ReadReq accesses(hits+misses) 1758system.cpu1.icache.demand_accesses::cpu1.inst 13921754 # number of demand (read+write) accesses 1759system.cpu1.icache.demand_accesses::total 13921754 # number of demand (read+write) accesses 1760system.cpu1.icache.overall_accesses::cpu1.inst 13921754 # number of overall (read+write) accesses 1761system.cpu1.icache.overall_accesses::total 13921754 # number of overall (read+write) accesses 1762system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.033329 # miss rate for ReadReq accesses 1763system.cpu1.icache.ReadReq_miss_rate::total 0.033329 # miss rate for ReadReq accesses 1764system.cpu1.icache.demand_miss_rate::cpu1.inst 0.033329 # miss rate for demand accesses 1765system.cpu1.icache.demand_miss_rate::total 0.033329 # miss rate for demand accesses 1766system.cpu1.icache.overall_miss_rate::cpu1.inst 0.033329 # miss rate for overall accesses 1767system.cpu1.icache.overall_miss_rate::total 0.033329 # miss rate for overall accesses 1768system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9082.120320 # average ReadReq miss latency 1769system.cpu1.icache.ReadReq_avg_miss_latency::total 9082.120320 # average ReadReq miss latency 1770system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9082.120320 # average overall miss latency 1771system.cpu1.icache.demand_avg_miss_latency::total 9082.120320 # average overall miss latency 1772system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9082.120320 # average overall miss latency 1773system.cpu1.icache.overall_avg_miss_latency::total 9082.120320 # average overall miss latency 1774system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1775system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1776system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1777system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1778system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1779system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1780system.cpu1.icache.fast_writes 0 # number of fast writes performed 1781system.cpu1.icache.cache_copies 0 # number of cache copies performed 1782system.cpu1.icache.writebacks::writebacks 463484 # number of writebacks 1783system.cpu1.icache.writebacks::total 463484 # number of writebacks 1784system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 463996 # number of ReadReq MSHR misses 1785system.cpu1.icache.ReadReq_mshr_misses::total 463996 # number of ReadReq MSHR misses 1786system.cpu1.icache.demand_mshr_misses::cpu1.inst 463996 # number of demand (read+write) MSHR misses 1787system.cpu1.icache.demand_mshr_misses::total 463996 # number of demand (read+write) MSHR misses 1788system.cpu1.icache.overall_mshr_misses::cpu1.inst 463996 # number of overall MSHR misses 1789system.cpu1.icache.overall_mshr_misses::total 463996 # number of overall MSHR misses 1790system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable 1791system.cpu1.icache.ReadReq_mshr_uncacheable::total 177 # number of ReadReq MSHR uncacheable 1792system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses 1793system.cpu1.icache.overall_mshr_uncacheable_misses::total 177 # number of overall MSHR uncacheable misses 1794system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3982069500 # number of ReadReq MSHR miss cycles 1795system.cpu1.icache.ReadReq_mshr_miss_latency::total 3982069500 # number of ReadReq MSHR miss cycles 1796system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3982069500 # number of demand (read+write) MSHR miss cycles 1797system.cpu1.icache.demand_mshr_miss_latency::total 3982069500 # number of demand (read+write) MSHR miss cycles 1798system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3982069500 # number of overall MSHR miss cycles 1799system.cpu1.icache.overall_mshr_miss_latency::total 3982069500 # number of overall MSHR miss cycles 1800system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 23546500 # number of ReadReq MSHR uncacheable cycles 1801system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 23546500 # number of ReadReq MSHR uncacheable cycles 1802system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 23546500 # number of overall MSHR uncacheable cycles 1803system.cpu1.icache.overall_mshr_uncacheable_latency::total 23546500 # number of overall MSHR uncacheable cycles 1804system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.033329 # mshr miss rate for ReadReq accesses 1805system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.033329 # mshr miss rate for ReadReq accesses 1806system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.033329 # mshr miss rate for demand accesses 1807system.cpu1.icache.demand_mshr_miss_rate::total 0.033329 # mshr miss rate for demand accesses 1808system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.033329 # mshr miss rate for overall accesses 1809system.cpu1.icache.overall_mshr_miss_rate::total 0.033329 # mshr miss rate for overall accesses 1810system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8582.120320 # average ReadReq mshr miss latency 1811system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8582.120320 # average ReadReq mshr miss latency 1812system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8582.120320 # average overall mshr miss latency 1813system.cpu1.icache.demand_avg_mshr_miss_latency::total 8582.120320 # average overall mshr miss latency 1814system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8582.120320 # average overall mshr miss latency 1815system.cpu1.icache.overall_avg_mshr_miss_latency::total 8582.120320 # average overall mshr miss latency 1816system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 133031.073446 # average ReadReq mshr uncacheable latency 1817system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 133031.073446 # average ReadReq mshr uncacheable latency 1818system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 133031.073446 # average overall mshr uncacheable latency 1819system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 133031.073446 # average overall mshr uncacheable latency 1820system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1821system.cpu1.l2cache.prefetcher.num_hwpf_issued 117918 # number of hwpf issued 1822system.cpu1.l2cache.prefetcher.pfIdentified 117936 # number of prefetch candidates identified 1823system.cpu1.l2cache.prefetcher.pfBufferHit 16 # number of redundant prefetches already in prefetch queue 1824system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1825system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1826system.cpu1.l2cache.prefetcher.pfSpanPage 50208 # number of prefetches not generated due to page crossing 1827system.cpu1.l2cache.tags.replacements 31332 # number of replacements 1828system.cpu1.l2cache.tags.tagsinuse 14956.481117 # Cycle average of tags in use 1829system.cpu1.l2cache.tags.total_refs 1042665 # Total number of references to valid blocks. 1830system.cpu1.l2cache.tags.sampled_refs 46454 # Sample count of references to valid blocks. 1831system.cpu1.l2cache.tags.avg_refs 22.445107 # Average number of references to valid blocks. 1832system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1833system.cpu1.l2cache.tags.occ_blocks::writebacks 14460.199894 # Average occupied blocks per requestor 1834system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 2.270812 # Average occupied blocks per requestor 1835system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.044709 # Average occupied blocks per requestor 1836system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 491.965701 # Average occupied blocks per requestor 1837system.cpu1.l2cache.tags.occ_percent::writebacks 0.882581 # Average percentage of cache occupancy 1838system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000139 # Average percentage of cache occupancy 1839system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000125 # Average percentage of cache occupancy 1840system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.030027 # Average percentage of cache occupancy 1841system.cpu1.l2cache.tags.occ_percent::total 0.912871 # Average percentage of cache occupancy 1842system.cpu1.l2cache.tags.occ_task_id_blocks::1022 960 # Occupied blocks per task id 1843system.cpu1.l2cache.tags.occ_task_id_blocks::1023 31 # Occupied blocks per task id 1844system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14131 # Occupied blocks per task id 1845system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 2 # Occupied blocks per task id 1846system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 38 # Occupied blocks per task id 1847system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 920 # Occupied blocks per task id 1848system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id 1849system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 1850system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 25 # Occupied blocks per task id 1851system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 423 # Occupied blocks per task id 1852system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1663 # Occupied blocks per task id 1853system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 12045 # Occupied blocks per task id 1854system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.058594 # Percentage of cache occupancy per task id 1855system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001892 # Percentage of cache occupancy per task id 1856system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.862488 # Percentage of cache occupancy per task id 1857system.cpu1.l2cache.tags.tag_accesses 21157161 # Number of tag accesses 1858system.cpu1.l2cache.tags.data_accesses 21157161 # Number of data accesses 1859system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 2444 # number of ReadReq hits 1860system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1492 # number of ReadReq hits 1861system.cpu1.l2cache.ReadReq_hits::total 3936 # number of ReadReq hits 1862system.cpu1.l2cache.WritebackDirty_hits::writebacks 91966 # number of WritebackDirty hits 1863system.cpu1.l2cache.WritebackDirty_hits::total 91966 # number of WritebackDirty hits 1864system.cpu1.l2cache.WritebackClean_hits::writebacks 509880 # number of WritebackClean hits 1865system.cpu1.l2cache.WritebackClean_hits::total 509880 # number of WritebackClean hits 1866system.cpu1.l2cache.ReadExReq_hits::cpu1.data 18290 # number of ReadExReq hits 1867system.cpu1.l2cache.ReadExReq_hits::total 18290 # number of ReadExReq hits 1868system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 455220 # number of ReadCleanReq hits 1869system.cpu1.l2cache.ReadCleanReq_hits::total 455220 # number of ReadCleanReq hits 1870system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 77690 # number of ReadSharedReq hits 1871system.cpu1.l2cache.ReadSharedReq_hits::total 77690 # number of ReadSharedReq hits 1872system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 2444 # number of demand (read+write) hits 1873system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1492 # number of demand (read+write) hits 1874system.cpu1.l2cache.demand_hits::cpu1.inst 455220 # number of demand (read+write) hits 1875system.cpu1.l2cache.demand_hits::cpu1.data 95980 # number of demand (read+write) hits 1876system.cpu1.l2cache.demand_hits::total 555136 # number of demand (read+write) hits 1877system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 2444 # number of overall hits 1878system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1492 # number of overall hits 1879system.cpu1.l2cache.overall_hits::cpu1.inst 455220 # number of overall hits 1880system.cpu1.l2cache.overall_hits::cpu1.data 95980 # number of overall hits 1881system.cpu1.l2cache.overall_hits::total 555136 # number of overall hits 1882system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 348 # number of ReadReq misses 1883system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 298 # number of ReadReq misses 1884system.cpu1.l2cache.ReadReq_misses::total 646 # number of ReadReq misses 1885system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29049 # number of UpgradeReq misses 1886system.cpu1.l2cache.UpgradeReq_misses::total 29049 # number of UpgradeReq misses 1887system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23092 # number of SCUpgradeReq misses 1888system.cpu1.l2cache.SCUpgradeReq_misses::total 23092 # number of SCUpgradeReq misses 1889system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 5 # number of SCUpgradeFailReq misses 1890system.cpu1.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses 1891system.cpu1.l2cache.ReadExReq_misses::cpu1.data 32133 # number of ReadExReq misses 1892system.cpu1.l2cache.ReadExReq_misses::total 32133 # number of ReadExReq misses 1893system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 8776 # number of ReadCleanReq misses 1894system.cpu1.l2cache.ReadCleanReq_misses::total 8776 # number of ReadCleanReq misses 1895system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 63849 # number of ReadSharedReq misses 1896system.cpu1.l2cache.ReadSharedReq_misses::total 63849 # number of ReadSharedReq misses 1897system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 348 # number of demand (read+write) misses 1898system.cpu1.l2cache.demand_misses::cpu1.itb.walker 298 # number of demand (read+write) misses 1899system.cpu1.l2cache.demand_misses::cpu1.inst 8776 # number of demand (read+write) misses 1900system.cpu1.l2cache.demand_misses::cpu1.data 95982 # number of demand (read+write) misses 1901system.cpu1.l2cache.demand_misses::total 105404 # number of demand (read+write) misses 1902system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 348 # number of overall misses 1903system.cpu1.l2cache.overall_misses::cpu1.itb.walker 298 # number of overall misses 1904system.cpu1.l2cache.overall_misses::cpu1.inst 8776 # number of overall misses 1905system.cpu1.l2cache.overall_misses::cpu1.data 95982 # number of overall misses 1906system.cpu1.l2cache.overall_misses::total 105404 # number of overall misses 1907system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 6985500 # number of ReadReq miss cycles 1908system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5943500 # number of ReadReq miss cycles 1909system.cpu1.l2cache.ReadReq_miss_latency::total 12929000 # number of ReadReq miss cycles 1910system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 63798000 # number of UpgradeReq miss cycles 1911system.cpu1.l2cache.UpgradeReq_miss_latency::total 63798000 # number of UpgradeReq miss cycles 1912system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 54501000 # number of SCUpgradeReq miss cycles 1913system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 54501000 # number of SCUpgradeReq miss cycles 1914system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 4914000 # number of SCUpgradeFailReq miss cycles 1915system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 4914000 # number of SCUpgradeFailReq miss cycles 1916system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1634363000 # number of ReadExReq miss cycles 1917system.cpu1.l2cache.ReadExReq_miss_latency::total 1634363000 # number of ReadExReq miss cycles 1918system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 528873500 # number of ReadCleanReq miss cycles 1919system.cpu1.l2cache.ReadCleanReq_miss_latency::total 528873500 # number of ReadCleanReq miss cycles 1920system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1442259000 # number of ReadSharedReq miss cycles 1921system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1442259000 # number of ReadSharedReq miss cycles 1922system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 6985500 # number of demand (read+write) miss cycles 1923system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5943500 # number of demand (read+write) miss cycles 1924system.cpu1.l2cache.demand_miss_latency::cpu1.inst 528873500 # number of demand (read+write) miss cycles 1925system.cpu1.l2cache.demand_miss_latency::cpu1.data 3076622000 # number of demand (read+write) miss cycles 1926system.cpu1.l2cache.demand_miss_latency::total 3618424500 # number of demand (read+write) miss cycles 1927system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 6985500 # number of overall miss cycles 1928system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5943500 # number of overall miss cycles 1929system.cpu1.l2cache.overall_miss_latency::cpu1.inst 528873500 # number of overall miss cycles 1930system.cpu1.l2cache.overall_miss_latency::cpu1.data 3076622000 # number of overall miss cycles 1931system.cpu1.l2cache.overall_miss_latency::total 3618424500 # number of overall miss cycles 1932system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 2792 # number of ReadReq accesses(hits+misses) 1933system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1790 # number of ReadReq accesses(hits+misses) 1934system.cpu1.l2cache.ReadReq_accesses::total 4582 # number of ReadReq accesses(hits+misses) 1935system.cpu1.l2cache.WritebackDirty_accesses::writebacks 91966 # number of WritebackDirty accesses(hits+misses) 1936system.cpu1.l2cache.WritebackDirty_accesses::total 91966 # number of WritebackDirty accesses(hits+misses) 1937system.cpu1.l2cache.WritebackClean_accesses::writebacks 509880 # number of WritebackClean accesses(hits+misses) 1938system.cpu1.l2cache.WritebackClean_accesses::total 509880 # number of WritebackClean accesses(hits+misses) 1939system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29049 # number of UpgradeReq accesses(hits+misses) 1940system.cpu1.l2cache.UpgradeReq_accesses::total 29049 # number of UpgradeReq accesses(hits+misses) 1941system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23092 # number of SCUpgradeReq accesses(hits+misses) 1942system.cpu1.l2cache.SCUpgradeReq_accesses::total 23092 # number of SCUpgradeReq accesses(hits+misses) 1943system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 5 # number of SCUpgradeFailReq accesses(hits+misses) 1944system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses) 1945system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 50423 # number of ReadExReq accesses(hits+misses) 1946system.cpu1.l2cache.ReadExReq_accesses::total 50423 # number of ReadExReq accesses(hits+misses) 1947system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 463996 # number of ReadCleanReq accesses(hits+misses) 1948system.cpu1.l2cache.ReadCleanReq_accesses::total 463996 # number of ReadCleanReq accesses(hits+misses) 1949system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 141539 # number of ReadSharedReq accesses(hits+misses) 1950system.cpu1.l2cache.ReadSharedReq_accesses::total 141539 # number of ReadSharedReq accesses(hits+misses) 1951system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 2792 # number of demand (read+write) accesses 1952system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 1790 # number of demand (read+write) accesses 1953system.cpu1.l2cache.demand_accesses::cpu1.inst 463996 # number of demand (read+write) accesses 1954system.cpu1.l2cache.demand_accesses::cpu1.data 191962 # number of demand (read+write) accesses 1955system.cpu1.l2cache.demand_accesses::total 660540 # number of demand (read+write) accesses 1956system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 2792 # number of overall (read+write) accesses 1957system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 1790 # number of overall (read+write) accesses 1958system.cpu1.l2cache.overall_accesses::cpu1.inst 463996 # number of overall (read+write) accesses 1959system.cpu1.l2cache.overall_accesses::cpu1.data 191962 # number of overall (read+write) accesses 1960system.cpu1.l2cache.overall_accesses::total 660540 # number of overall (read+write) accesses 1961system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.124642 # miss rate for ReadReq accesses 1962system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.166480 # miss rate for ReadReq accesses 1963system.cpu1.l2cache.ReadReq_miss_rate::total 0.140986 # miss rate for ReadReq accesses 1964system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 1965system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 1966system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 1967system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1968system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 1969system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1970system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.637269 # miss rate for ReadExReq accesses 1971system.cpu1.l2cache.ReadExReq_miss_rate::total 0.637269 # miss rate for ReadExReq accesses 1972system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.018914 # miss rate for ReadCleanReq accesses 1973system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.018914 # miss rate for ReadCleanReq accesses 1974system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.451105 # miss rate for ReadSharedReq accesses 1975system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.451105 # miss rate for ReadSharedReq accesses 1976system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.124642 # miss rate for demand accesses 1977system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.166480 # miss rate for demand accesses 1978system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.018914 # miss rate for demand accesses 1979system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.500005 # miss rate for demand accesses 1980system.cpu1.l2cache.demand_miss_rate::total 0.159572 # miss rate for demand accesses 1981system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.124642 # miss rate for overall accesses 1982system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.166480 # miss rate for overall accesses 1983system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.018914 # miss rate for overall accesses 1984system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.500005 # miss rate for overall accesses 1985system.cpu1.l2cache.overall_miss_rate::total 0.159572 # miss rate for overall accesses 1986system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20073.275862 # average ReadReq miss latency 1987system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19944.630872 # average ReadReq miss latency 1988system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20013.931889 # average ReadReq miss latency 1989system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 2196.220180 # average UpgradeReq miss latency 1990system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 2196.220180 # average UpgradeReq miss latency 1991system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 2360.168024 # average SCUpgradeReq miss latency 1992system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 2360.168024 # average SCUpgradeReq miss latency 1993system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 982800 # average SCUpgradeFailReq miss latency 1994system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 982800 # average SCUpgradeFailReq miss latency 1995system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 50862.446706 # average ReadExReq miss latency 1996system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 50862.446706 # average ReadExReq miss latency 1997system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 60263.616682 # average ReadCleanReq miss latency 1998system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 60263.616682 # average ReadCleanReq miss latency 1999system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22588.591834 # average ReadSharedReq miss latency 2000system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22588.591834 # average ReadSharedReq miss latency 2001system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20073.275862 # average overall miss latency 2002system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 19944.630872 # average overall miss latency 2003system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 60263.616682 # average overall miss latency 2004system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 32054.155988 # average overall miss latency 2005system.cpu1.l2cache.demand_avg_miss_latency::total 34329.100414 # average overall miss latency 2006system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20073.275862 # average overall miss latency 2007system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 19944.630872 # average overall miss latency 2008system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 60263.616682 # average overall miss latency 2009system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 32054.155988 # average overall miss latency 2010system.cpu1.l2cache.overall_avg_miss_latency::total 34329.100414 # average overall miss latency 2011system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2012system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2013system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 2014system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2015system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2016system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2017system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 2018system.cpu1.l2cache.cache_copies 0 # number of cache copies performed 2019system.cpu1.l2cache.writebacks::writebacks 26072 # number of writebacks 2020system.cpu1.l2cache.writebacks::total 26072 # number of writebacks 2021system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 73 # number of ReadExReq MSHR hits 2022system.cpu1.l2cache.ReadExReq_mshr_hits::total 73 # number of ReadExReq MSHR hits 2023system.cpu1.l2cache.demand_mshr_hits::cpu1.data 73 # number of demand (read+write) MSHR hits 2024system.cpu1.l2cache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits 2025system.cpu1.l2cache.overall_mshr_hits::cpu1.data 73 # number of overall MSHR hits 2026system.cpu1.l2cache.overall_mshr_hits::total 73 # number of overall MSHR hits 2027system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 348 # number of ReadReq MSHR misses 2028system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 298 # number of ReadReq MSHR misses 2029system.cpu1.l2cache.ReadReq_mshr_misses::total 646 # number of ReadReq MSHR misses 2030system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 20991 # number of HardPFReq MSHR misses 2031system.cpu1.l2cache.HardPFReq_mshr_misses::total 20991 # number of HardPFReq MSHR misses 2032system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29049 # number of UpgradeReq MSHR misses 2033system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29049 # number of UpgradeReq MSHR misses 2034system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23092 # number of SCUpgradeReq MSHR misses 2035system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23092 # number of SCUpgradeReq MSHR misses 2036system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 5 # number of SCUpgradeFailReq MSHR misses 2037system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses 2038system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 32060 # number of ReadExReq MSHR misses 2039system.cpu1.l2cache.ReadExReq_mshr_misses::total 32060 # number of ReadExReq MSHR misses 2040system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 8776 # number of ReadCleanReq MSHR misses 2041system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 8776 # number of ReadCleanReq MSHR misses 2042system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 63849 # number of ReadSharedReq MSHR misses 2043system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 63849 # number of ReadSharedReq MSHR misses 2044system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 348 # number of demand (read+write) MSHR misses 2045system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 298 # number of demand (read+write) MSHR misses 2046system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 8776 # number of demand (read+write) MSHR misses 2047system.cpu1.l2cache.demand_mshr_misses::cpu1.data 95909 # number of demand (read+write) MSHR misses 2048system.cpu1.l2cache.demand_mshr_misses::total 105331 # number of demand (read+write) MSHR misses 2049system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 348 # number of overall MSHR misses 2050system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 298 # number of overall MSHR misses 2051system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 8776 # number of overall MSHR misses 2052system.cpu1.l2cache.overall_mshr_misses::cpu1.data 95909 # number of overall MSHR misses 2053system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 20991 # number of overall MSHR misses 2054system.cpu1.l2cache.overall_mshr_misses::total 126322 # number of overall MSHR misses 2055system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable 2056system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 3082 # number of ReadReq MSHR uncacheable 2057system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 3259 # number of ReadReq MSHR uncacheable 2058system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2423 # number of WriteReq MSHR uncacheable 2059system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2423 # number of WriteReq MSHR uncacheable 2060system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses 2061system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5505 # number of overall MSHR uncacheable misses 2062system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5682 # number of overall MSHR uncacheable misses 2063system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4897500 # number of ReadReq MSHR miss cycles 2064system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 4155500 # number of ReadReq MSHR miss cycles 2065system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 9053000 # number of ReadReq MSHR miss cycles 2066system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 927478543 # number of HardPFReq MSHR miss cycles 2067system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 927478543 # number of HardPFReq MSHR miss cycles 2068system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 578238500 # number of UpgradeReq MSHR miss cycles 2069system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 578238500 # number of UpgradeReq MSHR miss cycles 2070system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 429963000 # number of SCUpgradeReq MSHR miss cycles 2071system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 429963000 # number of SCUpgradeReq MSHR miss cycles 2072system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 4632000 # number of SCUpgradeFailReq MSHR miss cycles 2073system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4632000 # number of SCUpgradeFailReq MSHR miss cycles 2074system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1434110000 # number of ReadExReq MSHR miss cycles 2075system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1434110000 # number of ReadExReq MSHR miss cycles 2076system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 476217500 # number of ReadCleanReq MSHR miss cycles 2077system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 476217500 # number of ReadCleanReq MSHR miss cycles 2078system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1059165000 # number of ReadSharedReq MSHR miss cycles 2079system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1059165000 # number of ReadSharedReq MSHR miss cycles 2080system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 4897500 # number of demand (read+write) MSHR miss cycles 2081system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4155500 # number of demand (read+write) MSHR miss cycles 2082system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 476217500 # number of demand (read+write) MSHR miss cycles 2083system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2493275000 # number of demand (read+write) MSHR miss cycles 2084system.cpu1.l2cache.demand_mshr_miss_latency::total 2978545500 # number of demand (read+write) MSHR miss cycles 2085system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 4897500 # number of overall MSHR miss cycles 2086system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4155500 # number of overall MSHR miss cycles 2087system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 476217500 # number of overall MSHR miss cycles 2088system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2493275000 # number of overall MSHR miss cycles 2089system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 927478543 # number of overall MSHR miss cycles 2090system.cpu1.l2cache.overall_mshr_miss_latency::total 3906024043 # number of overall MSHR miss cycles 2091system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 22219000 # number of ReadReq MSHR uncacheable cycles 2092system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 414523000 # number of ReadReq MSHR uncacheable cycles 2093system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 436742000 # number of ReadReq MSHR uncacheable cycles 2094system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 284955500 # number of WriteReq MSHR uncacheable cycles 2095system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 284955500 # number of WriteReq MSHR uncacheable cycles 2096system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 22219000 # number of overall MSHR uncacheable cycles 2097system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 699478500 # number of overall MSHR uncacheable cycles 2098system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 721697500 # number of overall MSHR uncacheable cycles 2099system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.124642 # mshr miss rate for ReadReq accesses 2100system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.166480 # mshr miss rate for ReadReq accesses 2101system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.140986 # mshr miss rate for ReadReq accesses 2102system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2103system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2104system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 2105system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 2106system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses 2107system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 2108system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2109system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 2110system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.635821 # mshr miss rate for ReadExReq accesses 2111system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.635821 # mshr miss rate for ReadExReq accesses 2112system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.018914 # mshr miss rate for ReadCleanReq accesses 2113system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.018914 # mshr miss rate for ReadCleanReq accesses 2114system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.451105 # mshr miss rate for ReadSharedReq accesses 2115system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.451105 # mshr miss rate for ReadSharedReq accesses 2116system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.124642 # mshr miss rate for demand accesses 2117system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.166480 # mshr miss rate for demand accesses 2118system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.018914 # mshr miss rate for demand accesses 2119system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.499625 # mshr miss rate for demand accesses 2120system.cpu1.l2cache.demand_mshr_miss_rate::total 0.159462 # mshr miss rate for demand accesses 2121system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.124642 # mshr miss rate for overall accesses 2122system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.166480 # mshr miss rate for overall accesses 2123system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.018914 # mshr miss rate for overall accesses 2124system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.499625 # mshr miss rate for overall accesses 2125system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2126system.cpu1.l2cache.overall_mshr_miss_rate::total 0.191241 # mshr miss rate for overall accesses 2127system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14073.275862 # average ReadReq mshr miss latency 2128system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13944.630872 # average ReadReq mshr miss latency 2129system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14013.931889 # average ReadReq mshr miss latency 2130system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44184.581154 # average HardPFReq mshr miss latency 2131system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 44184.581154 # average HardPFReq mshr miss latency 2132system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19905.624978 # average UpgradeReq mshr miss latency 2133system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19905.624978 # average UpgradeReq mshr miss latency 2134system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18619.565217 # average SCUpgradeReq mshr miss latency 2135system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18619.565217 # average SCUpgradeReq mshr miss latency 2136system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 926400 # average SCUpgradeFailReq mshr miss latency 2137system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 926400 # average SCUpgradeFailReq mshr miss latency 2138system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 44732.064878 # average ReadExReq mshr miss latency 2139system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 44732.064878 # average ReadExReq mshr miss latency 2140system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 54263.616682 # average ReadCleanReq mshr miss latency 2141system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 54263.616682 # average ReadCleanReq mshr miss latency 2142system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16588.591834 # average ReadSharedReq mshr miss latency 2143system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16588.591834 # average ReadSharedReq mshr miss latency 2144system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14073.275862 # average overall mshr miss latency 2145system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13944.630872 # average overall mshr miss latency 2146system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 54263.616682 # average overall mshr miss latency 2147system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 25996.256868 # average overall mshr miss latency 2148system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 28277.957107 # average overall mshr miss latency 2149system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14073.275862 # average overall mshr miss latency 2150system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13944.630872 # average overall mshr miss latency 2151system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 54263.616682 # average overall mshr miss latency 2152system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 25996.256868 # average overall mshr miss latency 2153system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44184.581154 # average overall mshr miss latency 2154system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 30921.170050 # average overall mshr miss latency 2155system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 125531.073446 # average ReadReq mshr uncacheable latency 2156system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 134498.053212 # average ReadReq mshr uncacheable latency 2157system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 134011.046333 # average ReadReq mshr uncacheable latency 2158system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117604.416013 # average WriteReq mshr uncacheable latency 2159system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 117604.416013 # average WriteReq mshr uncacheable latency 2160system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 125531.073446 # average overall mshr uncacheable latency 2161system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 127062.397820 # average overall mshr uncacheable latency 2162system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 127014.695530 # average overall mshr uncacheable latency 2163system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 2164system.cpu1.toL2Bus.snoop_filter.tot_requests 1324952 # Total number of requests made to the snoop filter. 2165system.cpu1.toL2Bus.snoop_filter.hit_single_requests 669028 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2166system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 10089 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2167system.cpu1.toL2Bus.snoop_filter.tot_snoops 168501 # Total number of snoops made to the snoop filter. 2168system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 166697 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2169system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1804 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2170system.cpu1.toL2Bus.trans_dist::ReadReq 10096 # Transaction distribution 2171system.cpu1.toL2Bus.trans_dist::ReadResp 652859 # Transaction distribution 2172system.cpu1.toL2Bus.trans_dist::WriteReq 2423 # Transaction distribution 2173system.cpu1.toL2Bus.trans_dist::WriteResp 2423 # Transaction distribution 2174system.cpu1.toL2Bus.trans_dist::WritebackDirty 119114 # Transaction distribution 2175system.cpu1.toL2Bus.trans_dist::WritebackClean 519969 # Transaction distribution 2176system.cpu1.toL2Bus.trans_dist::CleanEvict 86535 # Transaction distribution 2177system.cpu1.toL2Bus.trans_dist::HardPFReq 25223 # Transaction distribution 2178system.cpu1.toL2Bus.trans_dist::UpgradeReq 70168 # Transaction distribution 2179system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 40922 # Transaction distribution 2180system.cpu1.toL2Bus.trans_dist::UpgradeResp 84814 # Transaction distribution 2181system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 62 # Transaction distribution 2182system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 104 # Transaction distribution 2183system.cpu1.toL2Bus.trans_dist::ReadExReq 57641 # Transaction distribution 2184system.cpu1.toL2Bus.trans_dist::ReadExResp 55180 # Transaction distribution 2185system.cpu1.toL2Bus.trans_dist::ReadCleanReq 463996 # Transaction distribution 2186system.cpu1.toL2Bus.trans_dist::ReadSharedReq 214635 # Transaction distribution 2187system.cpu1.toL2Bus.trans_dist::InvalidateReq 32 # Transaction distribution 2188system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1391830 # Packet count per connected master and slave (bytes) 2189system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 722434 # Packet count per connected master and slave (bytes) 2190system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 4408 # Packet count per connected master and slave (bytes) 2191system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 7011 # Packet count per connected master and slave (bytes) 2192system.cpu1.toL2Bus.pkt_count::total 2125683 # Packet count per connected master and slave (bytes) 2193system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 59359428 # Cumulative packet size per connected master and slave (bytes) 2194system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24498524 # Cumulative packet size per connected master and slave (bytes) 2195system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7160 # Cumulative packet size per connected master and slave (bytes) 2196system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 11168 # Cumulative packet size per connected master and slave (bytes) 2197system.cpu1.toL2Bus.pkt_size::total 83876280 # Cumulative packet size per connected master and slave (bytes) 2198system.cpu1.toL2Bus.snoops 355270 # Total snoops (count) 2199system.cpu1.toL2Bus.snoop_fanout::samples 998881 # Request fanout histogram 2200system.cpu1.toL2Bus.snoop_fanout::mean 0.185518 # Request fanout histogram 2201system.cpu1.toL2Bus.snoop_fanout::stdev 0.393336 # Request fanout histogram 2202system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2203system.cpu1.toL2Bus.snoop_fanout::0 815375 81.63% 81.63% # Request fanout histogram 2204system.cpu1.toL2Bus.snoop_fanout::1 181702 18.19% 99.82% # Request fanout histogram 2205system.cpu1.toL2Bus.snoop_fanout::2 1804 0.18% 100.00% # Request fanout histogram 2206system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2207system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2208system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2209system.cpu1.toL2Bus.snoop_fanout::total 998881 # Request fanout histogram 2210system.cpu1.toL2Bus.reqLayer0.occupancy 1279425500 # Layer occupancy (ticks) 2211system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 2212system.cpu1.toL2Bus.snoopLayer0.occupancy 79453408 # Layer occupancy (ticks) 2213system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2214system.cpu1.toL2Bus.respLayer0.occupancy 696171000 # Layer occupancy (ticks) 2215system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2216system.cpu1.toL2Bus.respLayer1.occupancy 318356500 # Layer occupancy (ticks) 2217system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2218system.cpu1.toL2Bus.respLayer2.occupancy 2618000 # Layer occupancy (ticks) 2219system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2220system.cpu1.toL2Bus.respLayer3.occupancy 4219000 # Layer occupancy (ticks) 2221system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2222system.iobus.trans_dist::ReadReq 31021 # Transaction distribution 2223system.iobus.trans_dist::ReadResp 31021 # Transaction distribution 2224system.iobus.trans_dist::WriteReq 59425 # Transaction distribution 2225system.iobus.trans_dist::WriteResp 59425 # Transaction distribution 2226system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56620 # Packet count per connected master and slave (bytes) 2227system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 2228system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 2229system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 2230system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 2231system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 2232system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 2233system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 2234system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2235system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2236system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2237system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 2238system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 2239system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 2240system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 2241system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 2242system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 2243system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 2244system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 2245system.iobus.pkt_count_system.bridge.master::total 107934 # Packet count per connected master and slave (bytes) 2246system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes) 2247system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes) 2248system.iobus.pkt_count::total 180892 # Packet count per connected master and slave (bytes) 2249system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71564 # Cumulative packet size per connected master and slave (bytes) 2250system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 2251system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) 2252system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 2253system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 2254system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 2255system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 2256system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 2257system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2258system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2259system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2260system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 2261system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2262system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2263system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 2264system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 2265system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2266system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 2267system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 2268system.iobus.pkt_size_system.bridge.master::total 162814 # Cumulative packet size per connected master and slave (bytes) 2269system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes) 2270system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes) 2271system.iobus.pkt_size::total 2484086 # Cumulative packet size per connected master and slave (bytes) 2272system.iobus.reqLayer0.occupancy 48736000 # Layer occupancy (ticks) 2273system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2274system.iobus.reqLayer1.occupancy 106500 # Layer occupancy (ticks) 2275system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2276system.iobus.reqLayer2.occupancy 319500 # Layer occupancy (ticks) 2277system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2278system.iobus.reqLayer3.occupancy 32500 # Layer occupancy (ticks) 2279system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2280system.iobus.reqLayer4.occupancy 16000 # Layer occupancy (ticks) 2281system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 2282system.iobus.reqLayer7.occupancy 93000 # Layer occupancy (ticks) 2283system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 2284system.iobus.reqLayer8.occupancy 609000 # Layer occupancy (ticks) 2285system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 2286system.iobus.reqLayer10.occupancy 23500 # Layer occupancy (ticks) 2287system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2288system.iobus.reqLayer13.occupancy 12000 # Layer occupancy (ticks) 2289system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2290system.iobus.reqLayer14.occupancy 11500 # Layer occupancy (ticks) 2291system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2292system.iobus.reqLayer15.occupancy 11500 # Layer occupancy (ticks) 2293system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 2294system.iobus.reqLayer16.occupancy 48000 # Layer occupancy (ticks) 2295system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2296system.iobus.reqLayer17.occupancy 11500 # Layer occupancy (ticks) 2297system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 2298system.iobus.reqLayer18.occupancy 11500 # Layer occupancy (ticks) 2299system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 2300system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) 2301system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 2302system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) 2303system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 2304system.iobus.reqLayer21.occupancy 12000 # Layer occupancy (ticks) 2305system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 2306system.iobus.reqLayer23.occupancy 6160500 # Layer occupancy (ticks) 2307system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2308system.iobus.reqLayer24.occupancy 32043500 # Layer occupancy (ticks) 2309system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2310system.iobus.reqLayer25.occupancy 187096722 # Layer occupancy (ticks) 2311system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2312system.iobus.respLayer0.occupancy 84733000 # Layer occupancy (ticks) 2313system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2314system.iobus.respLayer3.occupancy 36782000 # Layer occupancy (ticks) 2315system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2316system.iocache.tags.replacements 36461 # number of replacements 2317system.iocache.tags.tagsinuse 14.380038 # Cycle average of tags in use 2318system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 2319system.iocache.tags.sampled_refs 36477 # Sample count of references to valid blocks. 2320system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 2321system.iocache.tags.warmup_cycle 290749964000 # Cycle when the warmup percentage was hit. 2322system.iocache.tags.occ_blocks::realview.ide 14.380038 # Average occupied blocks per requestor 2323system.iocache.tags.occ_percent::realview.ide 0.898752 # Average percentage of cache occupancy 2324system.iocache.tags.occ_percent::total 0.898752 # Average percentage of cache occupancy 2325system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2326system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2327system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2328system.iocache.tags.tag_accesses 328311 # Number of tag accesses 2329system.iocache.tags.data_accesses 328311 # Number of data accesses 2330system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses 2331system.iocache.ReadReq_misses::total 255 # number of ReadReq misses 2332system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 2333system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 2334system.iocache.demand_misses::realview.ide 255 # number of demand (read+write) misses 2335system.iocache.demand_misses::total 255 # number of demand (read+write) misses 2336system.iocache.overall_misses::realview.ide 255 # number of overall misses 2337system.iocache.overall_misses::total 255 # number of overall misses 2338system.iocache.ReadReq_miss_latency::realview.ide 32883377 # number of ReadReq miss cycles 2339system.iocache.ReadReq_miss_latency::total 32883377 # number of ReadReq miss cycles 2340system.iocache.WriteLineReq_miss_latency::realview.ide 4577110345 # number of WriteLineReq miss cycles 2341system.iocache.WriteLineReq_miss_latency::total 4577110345 # number of WriteLineReq miss cycles 2342system.iocache.demand_miss_latency::realview.ide 32883377 # number of demand (read+write) miss cycles 2343system.iocache.demand_miss_latency::total 32883377 # number of demand (read+write) miss cycles 2344system.iocache.overall_miss_latency::realview.ide 32883377 # number of overall miss cycles 2345system.iocache.overall_miss_latency::total 32883377 # number of overall miss cycles 2346system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) 2347system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) 2348system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 2349system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) 2350system.iocache.demand_accesses::realview.ide 255 # number of demand (read+write) accesses 2351system.iocache.demand_accesses::total 255 # number of demand (read+write) accesses 2352system.iocache.overall_accesses::realview.ide 255 # number of overall (read+write) accesses 2353system.iocache.overall_accesses::total 255 # number of overall (read+write) accesses 2354system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2355system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2356system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 2357system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 2358system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2359system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2360system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2361system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2362system.iocache.ReadReq_avg_miss_latency::realview.ide 128954.419608 # average ReadReq miss latency 2363system.iocache.ReadReq_avg_miss_latency::total 128954.419608 # average ReadReq miss latency 2364system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126355.740531 # average WriteLineReq miss latency 2365system.iocache.WriteLineReq_avg_miss_latency::total 126355.740531 # average WriteLineReq miss latency 2366system.iocache.demand_avg_miss_latency::realview.ide 128954.419608 # average overall miss latency 2367system.iocache.demand_avg_miss_latency::total 128954.419608 # average overall miss latency 2368system.iocache.overall_avg_miss_latency::realview.ide 128954.419608 # average overall miss latency 2369system.iocache.overall_avg_miss_latency::total 128954.419608 # average overall miss latency 2370system.iocache.blocked_cycles::no_mshrs 24 # number of cycles access was blocked 2371system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2372system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked 2373system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2374system.iocache.avg_blocked_cycles::no_mshrs 12 # average number of cycles each access was blocked 2375system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2376system.iocache.fast_writes 0 # number of fast writes performed 2377system.iocache.cache_copies 0 # number of cache copies performed 2378system.iocache.writebacks::writebacks 36206 # number of writebacks 2379system.iocache.writebacks::total 36206 # number of writebacks 2380system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses 2381system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses 2382system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses 2383system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses 2384system.iocache.demand_mshr_misses::realview.ide 255 # number of demand (read+write) MSHR misses 2385system.iocache.demand_mshr_misses::total 255 # number of demand (read+write) MSHR misses 2386system.iocache.overall_mshr_misses::realview.ide 255 # number of overall MSHR misses 2387system.iocache.overall_mshr_misses::total 255 # number of overall MSHR misses 2388system.iocache.ReadReq_mshr_miss_latency::realview.ide 20133377 # number of ReadReq MSHR miss cycles 2389system.iocache.ReadReq_mshr_miss_latency::total 20133377 # number of ReadReq MSHR miss cycles 2390system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2764215832 # number of WriteLineReq MSHR miss cycles 2391system.iocache.WriteLineReq_mshr_miss_latency::total 2764215832 # number of WriteLineReq MSHR miss cycles 2392system.iocache.demand_mshr_miss_latency::realview.ide 20133377 # number of demand (read+write) MSHR miss cycles 2393system.iocache.demand_mshr_miss_latency::total 20133377 # number of demand (read+write) MSHR miss cycles 2394system.iocache.overall_mshr_miss_latency::realview.ide 20133377 # number of overall MSHR miss cycles 2395system.iocache.overall_mshr_miss_latency::total 20133377 # number of overall MSHR miss cycles 2396system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2397system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2398system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 2399system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 2400system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2401system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2402system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2403system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 2404system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 78954.419608 # average ReadReq mshr miss latency 2405system.iocache.ReadReq_avg_mshr_miss_latency::total 78954.419608 # average ReadReq mshr miss latency 2406system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76308.961793 # average WriteLineReq mshr miss latency 2407system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76308.961793 # average WriteLineReq mshr miss latency 2408system.iocache.demand_avg_mshr_miss_latency::realview.ide 78954.419608 # average overall mshr miss latency 2409system.iocache.demand_avg_mshr_miss_latency::total 78954.419608 # average overall mshr miss latency 2410system.iocache.overall_avg_mshr_miss_latency::realview.ide 78954.419608 # average overall mshr miss latency 2411system.iocache.overall_avg_mshr_miss_latency::total 78954.419608 # average overall mshr miss latency 2412system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2413system.l2c.tags.replacements 124374 # number of replacements 2414system.l2c.tags.tagsinuse 62971.222447 # Cycle average of tags in use 2415system.l2c.tags.total_refs 421293 # Total number of references to valid blocks. 2416system.l2c.tags.sampled_refs 188431 # Sample count of references to valid blocks. 2417system.l2c.tags.avg_refs 2.235795 # Average number of references to valid blocks. 2418system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2419system.l2c.tags.occ_blocks::writebacks 13456.936548 # Average occupied blocks per requestor 2420system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.884029 # Average occupied blocks per requestor 2421system.l2c.tags.occ_blocks::cpu0.itb.walker 0.161578 # Average occupied blocks per requestor 2422system.l2c.tags.occ_blocks::cpu0.inst 7408.035333 # Average occupied blocks per requestor 2423system.l2c.tags.occ_blocks::cpu0.data 2772.307356 # Average occupied blocks per requestor 2424system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 35669.502662 # Average occupied blocks per requestor 2425system.l2c.tags.occ_blocks::cpu1.inst 1440.723489 # Average occupied blocks per requestor 2426system.l2c.tags.occ_blocks::cpu1.data 421.652649 # Average occupied blocks per requestor 2427system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1798.018803 # Average occupied blocks per requestor 2428system.l2c.tags.occ_percent::writebacks 0.205337 # Average percentage of cache occupancy 2429system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000059 # Average percentage of cache occupancy 2430system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy 2431system.l2c.tags.occ_percent::cpu0.inst 0.113038 # Average percentage of cache occupancy 2432system.l2c.tags.occ_percent::cpu0.data 0.042302 # Average percentage of cache occupancy 2433system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.544273 # Average percentage of cache occupancy 2434system.l2c.tags.occ_percent::cpu1.inst 0.021984 # Average percentage of cache occupancy 2435system.l2c.tags.occ_percent::cpu1.data 0.006434 # Average percentage of cache occupancy 2436system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.027436 # Average percentage of cache occupancy 2437system.l2c.tags.occ_percent::total 0.960865 # Average percentage of cache occupancy 2438system.l2c.tags.occ_task_id_blocks::1022 32172 # Occupied blocks per task id 2439system.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id 2440system.l2c.tags.occ_task_id_blocks::1024 31879 # Occupied blocks per task id 2441system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id 2442system.l2c.tags.age_task_id_blocks_1022::2 296 # Occupied blocks per task id 2443system.l2c.tags.age_task_id_blocks_1022::3 5261 # Occupied blocks per task id 2444system.l2c.tags.age_task_id_blocks_1022::4 26614 # Occupied blocks per task id 2445system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id 2446system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id 2447system.l2c.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id 2448system.l2c.tags.age_task_id_blocks_1024::2 368 # Occupied blocks per task id 2449system.l2c.tags.age_task_id_blocks_1024::3 2433 # Occupied blocks per task id 2450system.l2c.tags.age_task_id_blocks_1024::4 29060 # Occupied blocks per task id 2451system.l2c.tags.occ_task_id_percent::1022 0.490906 # Percentage of cache occupancy per task id 2452system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id 2453system.l2c.tags.occ_task_id_percent::1024 0.486435 # Percentage of cache occupancy per task id 2454system.l2c.tags.tag_accesses 5838028 # Number of tag accesses 2455system.l2c.tags.data_accesses 5838028 # Number of data accesses 2456system.l2c.WritebackDirty_hits::writebacks 257920 # number of WritebackDirty hits 2457system.l2c.WritebackDirty_hits::total 257920 # number of WritebackDirty hits 2458system.l2c.UpgradeReq_hits::cpu0.data 32259 # number of UpgradeReq hits 2459system.l2c.UpgradeReq_hits::cpu1.data 1955 # number of UpgradeReq hits 2460system.l2c.UpgradeReq_hits::total 34214 # number of UpgradeReq hits 2461system.l2c.SCUpgradeReq_hits::cpu0.data 2096 # number of SCUpgradeReq hits 2462system.l2c.SCUpgradeReq_hits::cpu1.data 941 # number of SCUpgradeReq hits 2463system.l2c.SCUpgradeReq_hits::total 3037 # number of SCUpgradeReq hits 2464system.l2c.ReadExReq_hits::cpu0.data 4136 # number of ReadExReq hits 2465system.l2c.ReadExReq_hits::cpu1.data 1368 # number of ReadExReq hits 2466system.l2c.ReadExReq_hits::total 5504 # number of ReadExReq hits 2467system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 86 # number of ReadSharedReq hits 2468system.l2c.ReadSharedReq_hits::cpu0.itb.walker 68 # number of ReadSharedReq hits 2469system.l2c.ReadSharedReq_hits::cpu0.inst 28311 # number of ReadSharedReq hits 2470system.l2c.ReadSharedReq_hits::cpu0.data 47114 # number of ReadSharedReq hits 2471system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 47400 # number of ReadSharedReq hits 2472system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 25 # number of ReadSharedReq hits 2473system.l2c.ReadSharedReq_hits::cpu1.itb.walker 16 # number of ReadSharedReq hits 2474system.l2c.ReadSharedReq_hits::cpu1.inst 6412 # number of ReadSharedReq hits 2475system.l2c.ReadSharedReq_hits::cpu1.data 5086 # number of ReadSharedReq hits 2476system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 3327 # number of ReadSharedReq hits 2477system.l2c.ReadSharedReq_hits::total 137845 # number of ReadSharedReq hits 2478system.l2c.demand_hits::cpu0.dtb.walker 86 # number of demand (read+write) hits 2479system.l2c.demand_hits::cpu0.itb.walker 68 # number of demand (read+write) hits 2480system.l2c.demand_hits::cpu0.inst 28311 # number of demand (read+write) hits 2481system.l2c.demand_hits::cpu0.data 51250 # number of demand (read+write) hits 2482system.l2c.demand_hits::cpu0.l2cache.prefetcher 47400 # number of demand (read+write) hits 2483system.l2c.demand_hits::cpu1.dtb.walker 25 # number of demand (read+write) hits 2484system.l2c.demand_hits::cpu1.itb.walker 16 # number of demand (read+write) hits 2485system.l2c.demand_hits::cpu1.inst 6412 # number of demand (read+write) hits 2486system.l2c.demand_hits::cpu1.data 6454 # number of demand (read+write) hits 2487system.l2c.demand_hits::cpu1.l2cache.prefetcher 3327 # number of demand (read+write) hits 2488system.l2c.demand_hits::total 143349 # number of demand (read+write) hits 2489system.l2c.overall_hits::cpu0.dtb.walker 86 # number of overall hits 2490system.l2c.overall_hits::cpu0.itb.walker 68 # number of overall hits 2491system.l2c.overall_hits::cpu0.inst 28311 # number of overall hits 2492system.l2c.overall_hits::cpu0.data 51250 # number of overall hits 2493system.l2c.overall_hits::cpu0.l2cache.prefetcher 47400 # number of overall hits 2494system.l2c.overall_hits::cpu1.dtb.walker 25 # number of overall hits 2495system.l2c.overall_hits::cpu1.itb.walker 16 # number of overall hits 2496system.l2c.overall_hits::cpu1.inst 6412 # number of overall hits 2497system.l2c.overall_hits::cpu1.data 6454 # number of overall hits 2498system.l2c.overall_hits::cpu1.l2cache.prefetcher 3327 # number of overall hits 2499system.l2c.overall_hits::total 143349 # number of overall hits 2500system.l2c.UpgradeReq_misses::cpu0.data 9332 # number of UpgradeReq misses 2501system.l2c.UpgradeReq_misses::cpu1.data 2240 # number of UpgradeReq misses 2502system.l2c.UpgradeReq_misses::total 11572 # number of UpgradeReq misses 2503system.l2c.SCUpgradeReq_misses::cpu0.data 606 # number of SCUpgradeReq misses 2504system.l2c.SCUpgradeReq_misses::cpu1.data 1282 # number of SCUpgradeReq misses 2505system.l2c.SCUpgradeReq_misses::total 1888 # number of SCUpgradeReq misses 2506system.l2c.ReadExReq_misses::cpu0.data 11165 # number of ReadExReq misses 2507system.l2c.ReadExReq_misses::cpu1.data 7705 # number of ReadExReq misses 2508system.l2c.ReadExReq_misses::total 18870 # number of ReadExReq misses 2509system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 6 # number of ReadSharedReq misses 2510system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2 # number of ReadSharedReq misses 2511system.l2c.ReadSharedReq_misses::cpu0.inst 17548 # number of ReadSharedReq misses 2512system.l2c.ReadSharedReq_misses::cpu0.data 8846 # number of ReadSharedReq misses 2513system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 135065 # number of ReadSharedReq misses 2514system.l2c.ReadSharedReq_misses::cpu1.inst 2364 # number of ReadSharedReq misses 2515system.l2c.ReadSharedReq_misses::cpu1.data 796 # number of ReadSharedReq misses 2516system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 5489 # number of ReadSharedReq misses 2517system.l2c.ReadSharedReq_misses::total 170116 # number of ReadSharedReq misses 2518system.l2c.demand_misses::cpu0.dtb.walker 6 # number of demand (read+write) misses 2519system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses 2520system.l2c.demand_misses::cpu0.inst 17548 # number of demand (read+write) misses 2521system.l2c.demand_misses::cpu0.data 20011 # number of demand (read+write) misses 2522system.l2c.demand_misses::cpu0.l2cache.prefetcher 135065 # number of demand (read+write) misses 2523system.l2c.demand_misses::cpu1.inst 2364 # number of demand (read+write) misses 2524system.l2c.demand_misses::cpu1.data 8501 # number of demand (read+write) misses 2525system.l2c.demand_misses::cpu1.l2cache.prefetcher 5489 # number of demand (read+write) misses 2526system.l2c.demand_misses::total 188986 # number of demand (read+write) misses 2527system.l2c.overall_misses::cpu0.dtb.walker 6 # number of overall misses 2528system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses 2529system.l2c.overall_misses::cpu0.inst 17548 # number of overall misses 2530system.l2c.overall_misses::cpu0.data 20011 # number of overall misses 2531system.l2c.overall_misses::cpu0.l2cache.prefetcher 135065 # number of overall misses 2532system.l2c.overall_misses::cpu1.inst 2364 # number of overall misses 2533system.l2c.overall_misses::cpu1.data 8501 # number of overall misses 2534system.l2c.overall_misses::cpu1.l2cache.prefetcher 5489 # number of overall misses 2535system.l2c.overall_misses::total 188986 # number of overall misses 2536system.l2c.UpgradeReq_miss_latency::cpu0.data 27811000 # number of UpgradeReq miss cycles 2537system.l2c.UpgradeReq_miss_latency::cpu1.data 6496500 # number of UpgradeReq miss cycles 2538system.l2c.UpgradeReq_miss_latency::total 34307500 # number of UpgradeReq miss cycles 2539system.l2c.SCUpgradeReq_miss_latency::cpu0.data 5695500 # number of SCUpgradeReq miss cycles 2540system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2358500 # number of SCUpgradeReq miss cycles 2541system.l2c.SCUpgradeReq_miss_latency::total 8054000 # number of SCUpgradeReq miss cycles 2542system.l2c.ReadExReq_miss_latency::cpu0.data 1626743500 # number of ReadExReq miss cycles 2543system.l2c.ReadExReq_miss_latency::cpu1.data 1013044000 # number of ReadExReq miss cycles 2544system.l2c.ReadExReq_miss_latency::total 2639787500 # number of ReadExReq miss cycles 2545system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 809500 # number of ReadSharedReq miss cycles 2546system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 272000 # number of ReadSharedReq miss cycles 2547system.l2c.ReadSharedReq_miss_latency::cpu0.inst 2308407000 # number of ReadSharedReq miss cycles 2548system.l2c.ReadSharedReq_miss_latency::cpu0.data 1204319000 # number of ReadSharedReq miss cycles 2549system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 19595366985 # number of ReadSharedReq miss cycles 2550system.l2c.ReadSharedReq_miss_latency::cpu1.inst 315452500 # number of ReadSharedReq miss cycles 2551system.l2c.ReadSharedReq_miss_latency::cpu1.data 119571000 # number of ReadSharedReq miss cycles 2552system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 851586047 # number of ReadSharedReq miss cycles 2553system.l2c.ReadSharedReq_miss_latency::total 24395784032 # number of ReadSharedReq miss cycles 2554system.l2c.demand_miss_latency::cpu0.dtb.walker 809500 # number of demand (read+write) miss cycles 2555system.l2c.demand_miss_latency::cpu0.itb.walker 272000 # number of demand (read+write) miss cycles 2556system.l2c.demand_miss_latency::cpu0.inst 2308407000 # number of demand (read+write) miss cycles 2557system.l2c.demand_miss_latency::cpu0.data 2831062500 # number of demand (read+write) miss cycles 2558system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 19595366985 # number of demand (read+write) miss cycles 2559system.l2c.demand_miss_latency::cpu1.inst 315452500 # number of demand (read+write) miss cycles 2560system.l2c.demand_miss_latency::cpu1.data 1132615000 # number of demand (read+write) miss cycles 2561system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 851586047 # number of demand (read+write) miss cycles 2562system.l2c.demand_miss_latency::total 27035571532 # number of demand (read+write) miss cycles 2563system.l2c.overall_miss_latency::cpu0.dtb.walker 809500 # number of overall miss cycles 2564system.l2c.overall_miss_latency::cpu0.itb.walker 272000 # number of overall miss cycles 2565system.l2c.overall_miss_latency::cpu0.inst 2308407000 # number of overall miss cycles 2566system.l2c.overall_miss_latency::cpu0.data 2831062500 # number of overall miss cycles 2567system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 19595366985 # number of overall miss cycles 2568system.l2c.overall_miss_latency::cpu1.inst 315452500 # number of overall miss cycles 2569system.l2c.overall_miss_latency::cpu1.data 1132615000 # number of overall miss cycles 2570system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 851586047 # number of overall miss cycles 2571system.l2c.overall_miss_latency::total 27035571532 # number of overall miss cycles 2572system.l2c.WritebackDirty_accesses::writebacks 257920 # number of WritebackDirty accesses(hits+misses) 2573system.l2c.WritebackDirty_accesses::total 257920 # number of WritebackDirty accesses(hits+misses) 2574system.l2c.UpgradeReq_accesses::cpu0.data 41591 # number of UpgradeReq accesses(hits+misses) 2575system.l2c.UpgradeReq_accesses::cpu1.data 4195 # number of UpgradeReq accesses(hits+misses) 2576system.l2c.UpgradeReq_accesses::total 45786 # number of UpgradeReq accesses(hits+misses) 2577system.l2c.SCUpgradeReq_accesses::cpu0.data 2702 # number of SCUpgradeReq accesses(hits+misses) 2578system.l2c.SCUpgradeReq_accesses::cpu1.data 2223 # number of SCUpgradeReq accesses(hits+misses) 2579system.l2c.SCUpgradeReq_accesses::total 4925 # number of SCUpgradeReq accesses(hits+misses) 2580system.l2c.ReadExReq_accesses::cpu0.data 15301 # number of ReadExReq accesses(hits+misses) 2581system.l2c.ReadExReq_accesses::cpu1.data 9073 # number of ReadExReq accesses(hits+misses) 2582system.l2c.ReadExReq_accesses::total 24374 # number of ReadExReq accesses(hits+misses) 2583system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 92 # number of ReadSharedReq accesses(hits+misses) 2584system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 70 # number of ReadSharedReq accesses(hits+misses) 2585system.l2c.ReadSharedReq_accesses::cpu0.inst 45859 # number of ReadSharedReq accesses(hits+misses) 2586system.l2c.ReadSharedReq_accesses::cpu0.data 55960 # number of ReadSharedReq accesses(hits+misses) 2587system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 182465 # number of ReadSharedReq accesses(hits+misses) 2588system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 25 # number of ReadSharedReq accesses(hits+misses) 2589system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 16 # number of ReadSharedReq accesses(hits+misses) 2590system.l2c.ReadSharedReq_accesses::cpu1.inst 8776 # number of ReadSharedReq accesses(hits+misses) 2591system.l2c.ReadSharedReq_accesses::cpu1.data 5882 # number of ReadSharedReq accesses(hits+misses) 2592system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 8816 # number of ReadSharedReq accesses(hits+misses) 2593system.l2c.ReadSharedReq_accesses::total 307961 # number of ReadSharedReq accesses(hits+misses) 2594system.l2c.demand_accesses::cpu0.dtb.walker 92 # number of demand (read+write) accesses 2595system.l2c.demand_accesses::cpu0.itb.walker 70 # number of demand (read+write) accesses 2596system.l2c.demand_accesses::cpu0.inst 45859 # number of demand (read+write) accesses 2597system.l2c.demand_accesses::cpu0.data 71261 # number of demand (read+write) accesses 2598system.l2c.demand_accesses::cpu0.l2cache.prefetcher 182465 # number of demand (read+write) accesses 2599system.l2c.demand_accesses::cpu1.dtb.walker 25 # number of demand (read+write) accesses 2600system.l2c.demand_accesses::cpu1.itb.walker 16 # number of demand (read+write) accesses 2601system.l2c.demand_accesses::cpu1.inst 8776 # number of demand (read+write) accesses 2602system.l2c.demand_accesses::cpu1.data 14955 # number of demand (read+write) accesses 2603system.l2c.demand_accesses::cpu1.l2cache.prefetcher 8816 # number of demand (read+write) accesses 2604system.l2c.demand_accesses::total 332335 # number of demand (read+write) accesses 2605system.l2c.overall_accesses::cpu0.dtb.walker 92 # number of overall (read+write) accesses 2606system.l2c.overall_accesses::cpu0.itb.walker 70 # number of overall (read+write) accesses 2607system.l2c.overall_accesses::cpu0.inst 45859 # number of overall (read+write) accesses 2608system.l2c.overall_accesses::cpu0.data 71261 # number of overall (read+write) accesses 2609system.l2c.overall_accesses::cpu0.l2cache.prefetcher 182465 # number of overall (read+write) accesses 2610system.l2c.overall_accesses::cpu1.dtb.walker 25 # number of overall (read+write) accesses 2611system.l2c.overall_accesses::cpu1.itb.walker 16 # number of overall (read+write) accesses 2612system.l2c.overall_accesses::cpu1.inst 8776 # number of overall (read+write) accesses 2613system.l2c.overall_accesses::cpu1.data 14955 # number of overall (read+write) accesses 2614system.l2c.overall_accesses::cpu1.l2cache.prefetcher 8816 # number of overall (read+write) accesses 2615system.l2c.overall_accesses::total 332335 # number of overall (read+write) accesses 2616system.l2c.UpgradeReq_miss_rate::cpu0.data 0.224375 # miss rate for UpgradeReq accesses 2617system.l2c.UpgradeReq_miss_rate::cpu1.data 0.533969 # miss rate for UpgradeReq accesses 2618system.l2c.UpgradeReq_miss_rate::total 0.252741 # miss rate for UpgradeReq accesses 2619system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.224278 # miss rate for SCUpgradeReq accesses 2620system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.576698 # miss rate for SCUpgradeReq accesses 2621system.l2c.SCUpgradeReq_miss_rate::total 0.383350 # miss rate for SCUpgradeReq accesses 2622system.l2c.ReadExReq_miss_rate::cpu0.data 0.729691 # miss rate for ReadExReq accesses 2623system.l2c.ReadExReq_miss_rate::cpu1.data 0.849223 # miss rate for ReadExReq accesses 2624system.l2c.ReadExReq_miss_rate::total 0.774186 # miss rate for ReadExReq accesses 2625system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.065217 # miss rate for ReadSharedReq accesses 2626system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.028571 # miss rate for ReadSharedReq accesses 2627system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.382651 # miss rate for ReadSharedReq accesses 2628system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.158077 # miss rate for ReadSharedReq accesses 2629system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.740224 # miss rate for ReadSharedReq accesses 2630system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.269371 # miss rate for ReadSharedReq accesses 2631system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.135328 # miss rate for ReadSharedReq accesses 2632system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.622618 # miss rate for ReadSharedReq accesses 2633system.l2c.ReadSharedReq_miss_rate::total 0.552395 # miss rate for ReadSharedReq accesses 2634system.l2c.demand_miss_rate::cpu0.dtb.walker 0.065217 # miss rate for demand accesses 2635system.l2c.demand_miss_rate::cpu0.itb.walker 0.028571 # miss rate for demand accesses 2636system.l2c.demand_miss_rate::cpu0.inst 0.382651 # miss rate for demand accesses 2637system.l2c.demand_miss_rate::cpu0.data 0.280813 # miss rate for demand accesses 2638system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.740224 # miss rate for demand accesses 2639system.l2c.demand_miss_rate::cpu1.inst 0.269371 # miss rate for demand accesses 2640system.l2c.demand_miss_rate::cpu1.data 0.568439 # miss rate for demand accesses 2641system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.622618 # miss rate for demand accesses 2642system.l2c.demand_miss_rate::total 0.568661 # miss rate for demand accesses 2643system.l2c.overall_miss_rate::cpu0.dtb.walker 0.065217 # miss rate for overall accesses 2644system.l2c.overall_miss_rate::cpu0.itb.walker 0.028571 # miss rate for overall accesses 2645system.l2c.overall_miss_rate::cpu0.inst 0.382651 # miss rate for overall accesses 2646system.l2c.overall_miss_rate::cpu0.data 0.280813 # miss rate for overall accesses 2647system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.740224 # miss rate for overall accesses 2648system.l2c.overall_miss_rate::cpu1.inst 0.269371 # miss rate for overall accesses 2649system.l2c.overall_miss_rate::cpu1.data 0.568439 # miss rate for overall accesses 2650system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.622618 # miss rate for overall accesses 2651system.l2c.overall_miss_rate::total 0.568661 # miss rate for overall accesses 2652system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2980.175739 # average UpgradeReq miss latency 2653system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2900.223214 # average UpgradeReq miss latency 2654system.l2c.UpgradeReq_avg_miss_latency::total 2964.699274 # average UpgradeReq miss latency 2655system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 9398.514851 # average SCUpgradeReq miss latency 2656system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1839.703588 # average SCUpgradeReq miss latency 2657system.l2c.SCUpgradeReq_avg_miss_latency::total 4265.889831 # average SCUpgradeReq miss latency 2658system.l2c.ReadExReq_avg_miss_latency::cpu0.data 145700.268697 # average ReadExReq miss latency 2659system.l2c.ReadExReq_avg_miss_latency::cpu1.data 131478.780013 # average ReadExReq miss latency 2660system.l2c.ReadExReq_avg_miss_latency::total 139893.349232 # average ReadExReq miss latency 2661system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 134916.666667 # average ReadSharedReq miss latency 2662system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 136000 # average ReadSharedReq miss latency 2663system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 131548.153636 # average ReadSharedReq miss latency 2664system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 136142.776396 # average ReadSharedReq miss latency 2665system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 145081.012735 # average ReadSharedReq miss latency 2666system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 133440.143824 # average ReadSharedReq miss latency 2667system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 150214.824121 # average ReadSharedReq miss latency 2668system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 155144.114957 # average ReadSharedReq miss latency 2669system.l2c.ReadSharedReq_avg_miss_latency::total 143406.757930 # average ReadSharedReq miss latency 2670system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 134916.666667 # average overall miss latency 2671system.l2c.demand_avg_miss_latency::cpu0.itb.walker 136000 # average overall miss latency 2672system.l2c.demand_avg_miss_latency::cpu0.inst 131548.153636 # average overall miss latency 2673system.l2c.demand_avg_miss_latency::cpu0.data 141475.313578 # average overall miss latency 2674system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 145081.012735 # average overall miss latency 2675system.l2c.demand_avg_miss_latency::cpu1.inst 133440.143824 # average overall miss latency 2676system.l2c.demand_avg_miss_latency::cpu1.data 133233.149041 # average overall miss latency 2677system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 155144.114957 # average overall miss latency 2678system.l2c.demand_avg_miss_latency::total 143055.948758 # average overall miss latency 2679system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 134916.666667 # average overall miss latency 2680system.l2c.overall_avg_miss_latency::cpu0.itb.walker 136000 # average overall miss latency 2681system.l2c.overall_avg_miss_latency::cpu0.inst 131548.153636 # average overall miss latency 2682system.l2c.overall_avg_miss_latency::cpu0.data 141475.313578 # average overall miss latency 2683system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 145081.012735 # average overall miss latency 2684system.l2c.overall_avg_miss_latency::cpu1.inst 133440.143824 # average overall miss latency 2685system.l2c.overall_avg_miss_latency::cpu1.data 133233.149041 # average overall miss latency 2686system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 155144.114957 # average overall miss latency 2687system.l2c.overall_avg_miss_latency::total 143055.948758 # average overall miss latency 2688system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2689system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2690system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 2691system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2692system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2693system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2694system.l2c.fast_writes 0 # number of fast writes performed 2695system.l2c.cache_copies 0 # number of cache copies performed 2696system.l2c.writebacks::writebacks 97172 # number of writebacks 2697system.l2c.writebacks::total 97172 # number of writebacks 2698system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 4 # number of ReadSharedReq MSHR hits 2699system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 9 # number of ReadSharedReq MSHR hits 2700system.l2c.ReadSharedReq_mshr_hits::total 13 # number of ReadSharedReq MSHR hits 2701system.l2c.demand_mshr_hits::cpu0.inst 4 # number of demand (read+write) MSHR hits 2702system.l2c.demand_mshr_hits::cpu1.inst 9 # number of demand (read+write) MSHR hits 2703system.l2c.demand_mshr_hits::total 13 # number of demand (read+write) MSHR hits 2704system.l2c.overall_mshr_hits::cpu0.inst 4 # number of overall MSHR hits 2705system.l2c.overall_mshr_hits::cpu1.inst 9 # number of overall MSHR hits 2706system.l2c.overall_mshr_hits::total 13 # number of overall MSHR hits 2707system.l2c.CleanEvict_mshr_misses::writebacks 2825 # number of CleanEvict MSHR misses 2708system.l2c.CleanEvict_mshr_misses::total 2825 # number of CleanEvict MSHR misses 2709system.l2c.UpgradeReq_mshr_misses::cpu0.data 9332 # number of UpgradeReq MSHR misses 2710system.l2c.UpgradeReq_mshr_misses::cpu1.data 2240 # number of UpgradeReq MSHR misses 2711system.l2c.UpgradeReq_mshr_misses::total 11572 # number of UpgradeReq MSHR misses 2712system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 606 # number of SCUpgradeReq MSHR misses 2713system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1282 # number of SCUpgradeReq MSHR misses 2714system.l2c.SCUpgradeReq_mshr_misses::total 1888 # number of SCUpgradeReq MSHR misses 2715system.l2c.ReadExReq_mshr_misses::cpu0.data 11165 # number of ReadExReq MSHR misses 2716system.l2c.ReadExReq_mshr_misses::cpu1.data 7705 # number of ReadExReq MSHR misses 2717system.l2c.ReadExReq_mshr_misses::total 18870 # number of ReadExReq MSHR misses 2718system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 6 # number of ReadSharedReq MSHR misses 2719system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 2 # number of ReadSharedReq MSHR misses 2720system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 17544 # number of ReadSharedReq MSHR misses 2721system.l2c.ReadSharedReq_mshr_misses::cpu0.data 8846 # number of ReadSharedReq MSHR misses 2722system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 135065 # number of ReadSharedReq MSHR misses 2723system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2355 # number of ReadSharedReq MSHR misses 2724system.l2c.ReadSharedReq_mshr_misses::cpu1.data 796 # number of ReadSharedReq MSHR misses 2725system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 5489 # number of ReadSharedReq MSHR misses 2726system.l2c.ReadSharedReq_mshr_misses::total 170103 # number of ReadSharedReq MSHR misses 2727system.l2c.demand_mshr_misses::cpu0.dtb.walker 6 # number of demand (read+write) MSHR misses 2728system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses 2729system.l2c.demand_mshr_misses::cpu0.inst 17544 # number of demand (read+write) MSHR misses 2730system.l2c.demand_mshr_misses::cpu0.data 20011 # number of demand (read+write) MSHR misses 2731system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 135065 # number of demand (read+write) MSHR misses 2732system.l2c.demand_mshr_misses::cpu1.inst 2355 # number of demand (read+write) MSHR misses 2733system.l2c.demand_mshr_misses::cpu1.data 8501 # number of demand (read+write) MSHR misses 2734system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 5489 # number of demand (read+write) MSHR misses 2735system.l2c.demand_mshr_misses::total 188973 # number of demand (read+write) MSHR misses 2736system.l2c.overall_mshr_misses::cpu0.dtb.walker 6 # number of overall MSHR misses 2737system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses 2738system.l2c.overall_mshr_misses::cpu0.inst 17544 # number of overall MSHR misses 2739system.l2c.overall_mshr_misses::cpu0.data 20011 # number of overall MSHR misses 2740system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 135065 # number of overall MSHR misses 2741system.l2c.overall_mshr_misses::cpu1.inst 2355 # number of overall MSHR misses 2742system.l2c.overall_mshr_misses::cpu1.data 8501 # number of overall MSHR misses 2743system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 5489 # number of overall MSHR misses 2744system.l2c.overall_mshr_misses::total 188973 # number of overall MSHR misses 2745system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable 2746system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31817 # number of ReadReq MSHR uncacheable 2747system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable 2748system.l2c.ReadReq_mshr_uncacheable::cpu1.data 3079 # number of ReadReq MSHR uncacheable 2749system.l2c.ReadReq_mshr_uncacheable::total 44095 # number of ReadReq MSHR uncacheable 2750system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28499 # number of WriteReq MSHR uncacheable 2751system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2423 # number of WriteReq MSHR uncacheable 2752system.l2c.WriteReq_mshr_uncacheable::total 30922 # number of WriteReq MSHR uncacheable 2753system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses 2754system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60316 # number of overall MSHR uncacheable misses 2755system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses 2756system.l2c.overall_mshr_uncacheable_misses::cpu1.data 5502 # number of overall MSHR uncacheable misses 2757system.l2c.overall_mshr_uncacheable_misses::total 75017 # number of overall MSHR uncacheable misses 2758system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 678754000 # number of UpgradeReq MSHR miss cycles 2759system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 162023000 # number of UpgradeReq MSHR miss cycles 2760system.l2c.UpgradeReq_mshr_miss_latency::total 840777000 # number of UpgradeReq MSHR miss cycles 2761system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 45192500 # number of SCUpgradeReq MSHR miss cycles 2762system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 94781500 # number of SCUpgradeReq MSHR miss cycles 2763system.l2c.SCUpgradeReq_mshr_miss_latency::total 139974000 # number of SCUpgradeReq MSHR miss cycles 2764system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1515091017 # number of ReadExReq MSHR miss cycles 2765system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 935989514 # number of ReadExReq MSHR miss cycles 2766system.l2c.ReadExReq_mshr_miss_latency::total 2451080531 # number of ReadExReq MSHR miss cycles 2767system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 749500 # number of ReadSharedReq MSHR miss cycles 2768system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 252000 # number of ReadSharedReq MSHR miss cycles 2769system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 2132646516 # number of ReadSharedReq MSHR miss cycles 2770system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1115857006 # number of ReadSharedReq MSHR miss cycles 2771system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 18244681120 # number of ReadSharedReq MSHR miss cycles 2772system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 291145013 # number of ReadSharedReq MSHR miss cycles 2773system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 111607507 # number of ReadSharedReq MSHR miss cycles 2774system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 796678627 # number of ReadSharedReq MSHR miss cycles 2775system.l2c.ReadSharedReq_mshr_miss_latency::total 22693617289 # number of ReadSharedReq MSHR miss cycles 2776system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 749500 # number of demand (read+write) MSHR miss cycles 2777system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 252000 # number of demand (read+write) MSHR miss cycles 2778system.l2c.demand_mshr_miss_latency::cpu0.inst 2132646516 # number of demand (read+write) MSHR miss cycles 2779system.l2c.demand_mshr_miss_latency::cpu0.data 2630948023 # number of demand (read+write) MSHR miss cycles 2780system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 18244681120 # number of demand (read+write) MSHR miss cycles 2781system.l2c.demand_mshr_miss_latency::cpu1.inst 291145013 # number of demand (read+write) MSHR miss cycles 2782system.l2c.demand_mshr_miss_latency::cpu1.data 1047597021 # number of demand (read+write) MSHR miss cycles 2783system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 796678627 # number of demand (read+write) MSHR miss cycles 2784system.l2c.demand_mshr_miss_latency::total 25144697820 # number of demand (read+write) MSHR miss cycles 2785system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 749500 # number of overall MSHR miss cycles 2786system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 252000 # number of overall MSHR miss cycles 2787system.l2c.overall_mshr_miss_latency::cpu0.inst 2132646516 # number of overall MSHR miss cycles 2788system.l2c.overall_mshr_miss_latency::cpu0.data 2630948023 # number of overall MSHR miss cycles 2789system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 18244681120 # number of overall MSHR miss cycles 2790system.l2c.overall_mshr_miss_latency::cpu1.inst 291145013 # number of overall MSHR miss cycles 2791system.l2c.overall_mshr_miss_latency::cpu1.data 1047597021 # number of overall MSHR miss cycles 2792system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 796678627 # number of overall MSHR miss cycles 2793system.l2c.overall_mshr_miss_latency::total 25144697820 # number of overall MSHR miss cycles 2794system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 1023815000 # number of ReadReq MSHR uncacheable cycles 2795system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5801182501 # number of ReadReq MSHR uncacheable cycles 2796system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 19032500 # number of ReadReq MSHR uncacheable cycles 2797system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 359054501 # number of ReadReq MSHR uncacheable cycles 2798system.l2c.ReadReq_mshr_uncacheable_latency::total 7203084502 # number of ReadReq MSHR uncacheable cycles 2799system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4702546001 # number of WriteReq MSHR uncacheable cycles 2800system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 243701000 # number of WriteReq MSHR uncacheable cycles 2801system.l2c.WriteReq_mshr_uncacheable_latency::total 4946247001 # number of WriteReq MSHR uncacheable cycles 2802system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 1023815000 # number of overall MSHR uncacheable cycles 2803system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10503728502 # number of overall MSHR uncacheable cycles 2804system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 19032500 # number of overall MSHR uncacheable cycles 2805system.l2c.overall_mshr_uncacheable_latency::cpu1.data 602755501 # number of overall MSHR uncacheable cycles 2806system.l2c.overall_mshr_uncacheable_latency::total 12149331503 # number of overall MSHR uncacheable cycles 2807system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 2808system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 2809system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.224375 # mshr miss rate for UpgradeReq accesses 2810system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.533969 # mshr miss rate for UpgradeReq accesses 2811system.l2c.UpgradeReq_mshr_miss_rate::total 0.252741 # mshr miss rate for UpgradeReq accesses 2812system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.224278 # mshr miss rate for SCUpgradeReq accesses 2813system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.576698 # mshr miss rate for SCUpgradeReq accesses 2814system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.383350 # mshr miss rate for SCUpgradeReq accesses 2815system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.729691 # mshr miss rate for ReadExReq accesses 2816system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.849223 # mshr miss rate for ReadExReq accesses 2817system.l2c.ReadExReq_mshr_miss_rate::total 0.774186 # mshr miss rate for ReadExReq accesses 2818system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.065217 # mshr miss rate for ReadSharedReq accesses 2819system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.028571 # mshr miss rate for ReadSharedReq accesses 2820system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.382564 # mshr miss rate for ReadSharedReq accesses 2821system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.158077 # mshr miss rate for ReadSharedReq accesses 2822system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.740224 # mshr miss rate for ReadSharedReq accesses 2823system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.268345 # mshr miss rate for ReadSharedReq accesses 2824system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.135328 # mshr miss rate for ReadSharedReq accesses 2825system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.622618 # mshr miss rate for ReadSharedReq accesses 2826system.l2c.ReadSharedReq_mshr_miss_rate::total 0.552352 # mshr miss rate for ReadSharedReq accesses 2827system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.065217 # mshr miss rate for demand accesses 2828system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.028571 # mshr miss rate for demand accesses 2829system.l2c.demand_mshr_miss_rate::cpu0.inst 0.382564 # mshr miss rate for demand accesses 2830system.l2c.demand_mshr_miss_rate::cpu0.data 0.280813 # mshr miss rate for demand accesses 2831system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.740224 # mshr miss rate for demand accesses 2832system.l2c.demand_mshr_miss_rate::cpu1.inst 0.268345 # mshr miss rate for demand accesses 2833system.l2c.demand_mshr_miss_rate::cpu1.data 0.568439 # mshr miss rate for demand accesses 2834system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.622618 # mshr miss rate for demand accesses 2835system.l2c.demand_mshr_miss_rate::total 0.568622 # mshr miss rate for demand accesses 2836system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.065217 # mshr miss rate for overall accesses 2837system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.028571 # mshr miss rate for overall accesses 2838system.l2c.overall_mshr_miss_rate::cpu0.inst 0.382564 # mshr miss rate for overall accesses 2839system.l2c.overall_mshr_miss_rate::cpu0.data 0.280813 # mshr miss rate for overall accesses 2840system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.740224 # mshr miss rate for overall accesses 2841system.l2c.overall_mshr_miss_rate::cpu1.inst 0.268345 # mshr miss rate for overall accesses 2842system.l2c.overall_mshr_miss_rate::cpu1.data 0.568439 # mshr miss rate for overall accesses 2843system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.622618 # mshr miss rate for overall accesses 2844system.l2c.overall_mshr_miss_rate::total 0.568622 # mshr miss rate for overall accesses 2845system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 72734.033433 # average UpgradeReq mshr miss latency 2846system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 72331.696429 # average UpgradeReq mshr miss latency 2847system.l2c.UpgradeReq_avg_mshr_miss_latency::total 72656.152783 # average UpgradeReq mshr miss latency 2848system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 74575.082508 # average SCUpgradeReq mshr miss latency 2849system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73932.527301 # average SCUpgradeReq mshr miss latency 2850system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 74138.771186 # average SCUpgradeReq mshr miss latency 2851system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 135700.046305 # average ReadExReq mshr miss latency 2852system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121478.197794 # average ReadExReq mshr miss latency 2853system.l2c.ReadExReq_avg_mshr_miss_latency::total 129892.979915 # average ReadExReq mshr miss latency 2854system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 124916.666667 # average ReadSharedReq mshr miss latency 2855system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 126000 # average ReadSharedReq mshr miss latency 2856system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 121559.878933 # average ReadSharedReq mshr miss latency 2857system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 126142.550983 # average ReadSharedReq mshr miss latency 2858system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135080.747196 # average ReadSharedReq mshr miss latency 2859system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 123628.455626 # average ReadSharedReq mshr miss latency 2860system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 140210.435930 # average ReadSharedReq mshr miss latency 2861system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 145140.941337 # average ReadSharedReq mshr miss latency 2862system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 133411.035014 # average ReadSharedReq mshr miss latency 2863system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 124916.666667 # average overall mshr miss latency 2864system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 126000 # average overall mshr miss latency 2865system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121559.878933 # average overall mshr miss latency 2866system.l2c.demand_avg_mshr_miss_latency::cpu0.data 131475.089851 # average overall mshr miss latency 2867system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135080.747196 # average overall mshr miss latency 2868system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 123628.455626 # average overall mshr miss latency 2869system.l2c.demand_avg_mshr_miss_latency::cpu1.data 123232.210446 # average overall mshr miss latency 2870system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 145140.941337 # average overall mshr miss latency 2871system.l2c.demand_avg_mshr_miss_latency::total 133059.737740 # average overall mshr miss latency 2872system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 124916.666667 # average overall mshr miss latency 2873system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 126000 # average overall mshr miss latency 2874system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121559.878933 # average overall mshr miss latency 2875system.l2c.overall_avg_mshr_miss_latency::cpu0.data 131475.089851 # average overall mshr miss latency 2876system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135080.747196 # average overall mshr miss latency 2877system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 123628.455626 # average overall mshr miss latency 2878system.l2c.overall_avg_mshr_miss_latency::cpu1.data 123232.210446 # average overall mshr miss latency 2879system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 145140.941337 # average overall mshr miss latency 2880system.l2c.overall_avg_mshr_miss_latency::total 133059.737740 # average overall mshr miss latency 2881system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113479.827089 # average ReadReq mshr uncacheable latency 2882system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182329.650847 # average ReadReq mshr uncacheable latency 2883system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 107528.248588 # average ReadReq mshr uncacheable latency 2884system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116613.998376 # average ReadReq mshr uncacheable latency 2885system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 163353.770314 # average ReadReq mshr uncacheable latency 2886system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165007.403804 # average WriteReq mshr uncacheable latency 2887system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 100578.208832 # average WriteReq mshr uncacheable latency 2888system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159958.831932 # average WriteReq mshr uncacheable latency 2889system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113479.827089 # average overall mshr uncacheable latency 2890system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 174144.978148 # average overall mshr uncacheable latency 2891system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 107528.248588 # average overall mshr uncacheable latency 2892system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 109552.072156 # average overall mshr uncacheable latency 2893system.l2c.overall_avg_mshr_uncacheable_latency::total 161954.377048 # average overall mshr uncacheable latency 2894system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 2895system.membus.trans_dist::ReadReq 44095 # Transaction distribution 2896system.membus.trans_dist::ReadResp 214453 # Transaction distribution 2897system.membus.trans_dist::WriteReq 30922 # Transaction distribution 2898system.membus.trans_dist::WriteResp 30922 # Transaction distribution 2899system.membus.trans_dist::WritebackDirty 133378 # Transaction distribution 2900system.membus.trans_dist::CleanEvict 14958 # Transaction distribution 2901system.membus.trans_dist::UpgradeReq 73332 # Transaction distribution 2902system.membus.trans_dist::SCUpgradeReq 39852 # Transaction distribution 2903system.membus.trans_dist::UpgradeResp 2 # Transaction distribution 2904system.membus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution 2905system.membus.trans_dist::ReadExReq 39426 # Transaction distribution 2906system.membus.trans_dist::ReadExResp 18801 # Transaction distribution 2907system.membus.trans_dist::ReadSharedReq 170358 # Transaction distribution 2908system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 2909system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107934 # Packet count per connected master and slave (bytes) 2910system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) 2911system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13764 # Packet count per connected master and slave (bytes) 2912system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 651465 # Packet count per connected master and slave (bytes) 2913system.membus.pkt_count_system.l2c.mem_side::total 773197 # Packet count per connected master and slave (bytes) 2914system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72955 # Packet count per connected master and slave (bytes) 2915system.membus.pkt_count_system.iocache.mem_side::total 72955 # Packet count per connected master and slave (bytes) 2916system.membus.pkt_count::total 846152 # Packet count per connected master and slave (bytes) 2917system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162814 # Cumulative packet size per connected master and slave (bytes) 2918system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) 2919system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27528 # Cumulative packet size per connected master and slave (bytes) 2920system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18344268 # Cumulative packet size per connected master and slave (bytes) 2921system.membus.pkt_size_system.l2c.mem_side::total 18534678 # Cumulative packet size per connected master and slave (bytes) 2922system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) 2923system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) 2924system.membus.pkt_size::total 20852822 # Cumulative packet size per connected master and slave (bytes) 2925system.membus.snoops 120859 # Total snoops (count) 2926system.membus.snoop_fanout::samples 582572 # Request fanout histogram 2927system.membus.snoop_fanout::mean 1 # Request fanout histogram 2928system.membus.snoop_fanout::stdev 0 # Request fanout histogram 2929system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2930system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 2931system.membus.snoop_fanout::1 582572 100.00% 100.00% # Request fanout histogram 2932system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 2933system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2934system.membus.snoop_fanout::min_value 1 # Request fanout histogram 2935system.membus.snoop_fanout::max_value 1 # Request fanout histogram 2936system.membus.snoop_fanout::total 582572 # Request fanout histogram 2937system.membus.reqLayer0.occupancy 88269500 # Layer occupancy (ticks) 2938system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 2939system.membus.reqLayer1.occupancy 19000 # Layer occupancy (ticks) 2940system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 2941system.membus.reqLayer2.occupancy 11360500 # Layer occupancy (ticks) 2942system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 2943system.membus.reqLayer5.occupancy 969988933 # Layer occupancy (ticks) 2944system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 2945system.membus.respLayer2.occupancy 1109172490 # Layer occupancy (ticks) 2946system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 2947system.membus.respLayer3.occupancy 1385877 # Layer occupancy (ticks) 2948system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 2949system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 2950system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 2951system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 2952system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 2953system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 2954system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 2955system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 2956system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 2957system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 2958system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 2959system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 2960system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 2961system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 2962system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 2963system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 2964system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 2965system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 2966system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 2967system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 2968system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 2969system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 2970system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 2971system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 2972system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 2973system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 2974system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 2975system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 2976system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 2977system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 2978system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 2979system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 2980system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 2981system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 2982system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 2983system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 2984system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 2985system.realview.ethernet.droppedPackets 0 # number of packets dropped 2986system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 2987system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 2988system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 2989system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 2990system.toL2Bus.snoop_filter.tot_requests 961097 # Total number of requests made to the snoop filter. 2991system.toL2Bus.snoop_filter.hit_single_requests 519247 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2992system.toL2Bus.snoop_filter.hit_multi_requests 138785 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2993system.toL2Bus.snoop_filter.tot_snoops 20683 # Total number of snoops made to the snoop filter. 2994system.toL2Bus.snoop_filter.hit_single_snoops 19864 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2995system.toL2Bus.snoop_filter.hit_multi_snoops 819 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2996system.toL2Bus.trans_dist::ReadReq 44098 # Transaction distribution 2997system.toL2Bus.trans_dist::ReadResp 467805 # Transaction distribution 2998system.toL2Bus.trans_dist::WriteReq 30922 # Transaction distribution 2999system.toL2Bus.trans_dist::WriteResp 30922 # Transaction distribution 3000system.toL2Bus.trans_dist::WritebackDirty 391320 # Transaction distribution 3001system.toL2Bus.trans_dist::CleanEvict 106223 # Transaction distribution 3002system.toL2Bus.trans_dist::UpgradeReq 107477 # Transaction distribution 3003system.toL2Bus.trans_dist::SCUpgradeReq 42889 # Transaction distribution 3004system.toL2Bus.trans_dist::UpgradeResp 150366 # Transaction distribution 3005system.toL2Bus.trans_dist::SCUpgradeFailReq 104 # Transaction distribution 3006system.toL2Bus.trans_dist::UpgradeFailResp 104 # Transaction distribution 3007system.toL2Bus.trans_dist::ReadExReq 50473 # Transaction distribution 3008system.toL2Bus.trans_dist::ReadExResp 50473 # Transaction distribution 3009system.toL2Bus.trans_dist::ReadSharedReq 423722 # Transaction distribution 3010system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution 3011system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1241271 # Packet count per connected master and slave (bytes) 3012system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 253131 # Packet count per connected master and slave (bytes) 3013system.toL2Bus.pkt_count::total 1494402 # Packet count per connected master and slave (bytes) 3014system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34264962 # Cumulative packet size per connected master and slave (bytes) 3015system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 3773844 # Cumulative packet size per connected master and slave (bytes) 3016system.toL2Bus.pkt_size::total 38038806 # Cumulative packet size per connected master and slave (bytes) 3017system.toL2Bus.snoops 438960 # Total snoops (count) 3018system.toL2Bus.snoop_fanout::samples 896783 # Request fanout histogram 3019system.toL2Bus.snoop_fanout::mean 0.336520 # Request fanout histogram 3020system.toL2Bus.snoop_fanout::stdev 0.474448 # Request fanout histogram 3021system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3022system.toL2Bus.snoop_fanout::0 595817 66.44% 66.44% # Request fanout histogram 3023system.toL2Bus.snoop_fanout::1 300147 33.47% 99.91% # Request fanout histogram 3024system.toL2Bus.snoop_fanout::2 819 0.09% 100.00% # Request fanout histogram 3025system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3026system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 3027system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 3028system.toL2Bus.snoop_fanout::total 896783 # Request fanout histogram 3029system.toL2Bus.reqLayer0.occupancy 864823852 # Layer occupancy (ticks) 3030system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 3031system.toL2Bus.snoopLayer0.occupancy 360123 # Layer occupancy (ticks) 3032system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3033system.toL2Bus.respLayer0.occupancy 645977888 # Layer occupancy (ticks) 3034system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3035system.toL2Bus.respLayer1.occupancy 202227821 # Layer occupancy (ticks) 3036system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3037 3038---------- End Simulation Statistics ---------- 3039