stats.txt revision 11239:3be64e1f80ed
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.871820 # Number of seconds simulated 4sim_ticks 2871819744000 # Number of ticks simulated 5final_tick 2871819744000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 357244 # Simulator instruction rate (inst/s) 8host_op_rate 432116 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 7805602288 # Simulator tick rate (ticks/s) 10host_mem_usage 614840 # Number of bytes of host memory used 11host_seconds 367.92 # Real time elapsed on the host 12sim_insts 131436334 # Number of instructions simulated 13sim_ops 158983282 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 1155428 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 1268388 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 8606976 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.inst 151764 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.data 551380 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.l2cache.prefetcher 345088 # Number of bytes read from this memory 25system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 26system.physmem.bytes_read::total 12080624 # Number of bytes read from this memory 27system.physmem.bytes_inst_read::cpu0.inst 1155428 # Number of instructions bytes read from this memory 28system.physmem.bytes_inst_read::cpu1.inst 151764 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::total 1307192 # Number of instructions bytes read from this memory 30system.physmem.bytes_written::writebacks 8516928 # Number of bytes written to this memory 31system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory 32system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory 33system.physmem.bytes_written::total 8534492 # Number of bytes written to this memory 34system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.inst 26507 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.data 20338 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.l2cache.prefetcher 134484 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.inst 2526 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.data 8636 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.l2cache.prefetcher 5392 # Number of read requests responded to by this memory 43system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 44system.physmem.num_reads::total 197908 # Number of read requests responded to by this memory 45system.physmem.num_writes::writebacks 133077 # Number of write requests responded to by this memory 46system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory 47system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory 48system.physmem.num_writes::total 137468 # Number of write requests responded to by this memory 49system.physmem.bw_read::cpu0.dtb.walker 156 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu0.inst 402333 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.data 441667 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.l2cache.prefetcher 2997046 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu1.dtb.walker 22 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu1.inst 52846 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu1.data 191997 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.l2cache.prefetcher 120164 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::realview.ide 334 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::total 4206609 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_inst_read::cpu0.inst 402333 # Instruction read bandwidth from this memory (bytes/s) 61system.physmem.bw_inst_read::cpu1.inst 52846 # Instruction read bandwidth from this memory (bytes/s) 62system.physmem.bw_inst_read::total 455179 # Instruction read bandwidth from this memory (bytes/s) 63system.physmem.bw_write::writebacks 2965690 # Write bandwidth from this memory (bytes/s) 64system.physmem.bw_write::cpu0.data 6102 # Write bandwidth from this memory (bytes/s) 65system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) 66system.physmem.bw_write::total 2971806 # Write bandwidth from this memory (bytes/s) 67system.physmem.bw_total::writebacks 2965690 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::cpu0.dtb.walker 156 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) 70system.physmem.bw_total::cpu0.inst 402333 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu0.data 447769 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.l2cache.prefetcher 2997046 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu1.dtb.walker 22 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu1.inst 52846 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu1.data 192011 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu1.l2cache.prefetcher 120164 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::realview.ide 334 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::total 7178416 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.readReqs 197908 # Number of read requests accepted 80system.physmem.writeReqs 137468 # Number of write requests accepted 81system.physmem.readBursts 197908 # Number of DRAM read bursts, including those serviced by the write queue 82system.physmem.writeBursts 137468 # Number of DRAM write bursts, including those merged in the write queue 83system.physmem.bytesReadDRAM 12655744 # Total number of bytes read from DRAM 84system.physmem.bytesReadWrQ 10368 # Total number of bytes read from write queue 85system.physmem.bytesWritten 8547392 # Total number of bytes written to DRAM 86system.physmem.bytesReadSys 12080624 # Total read bytes from the system interface side 87system.physmem.bytesWrittenSys 8534492 # Total written bytes from the system interface side 88system.physmem.servicedByWrQ 162 # Number of DRAM read bursts serviced by the write queue 89system.physmem.mergedWrBursts 3895 # Number of DRAM write bursts merged with an existing one 90system.physmem.neitherReadNorWriteReqs 64406 # Number of requests that are neither read nor write 91system.physmem.perBankRdBursts::0 11744 # Per bank write bursts 92system.physmem.perBankRdBursts::1 11857 # Per bank write bursts 93system.physmem.perBankRdBursts::2 11924 # Per bank write bursts 94system.physmem.perBankRdBursts::3 11590 # Per bank write bursts 95system.physmem.perBankRdBursts::4 20227 # Per bank write bursts 96system.physmem.perBankRdBursts::5 11881 # Per bank write bursts 97system.physmem.perBankRdBursts::6 12481 # Per bank write bursts 98system.physmem.perBankRdBursts::7 12857 # Per bank write bursts 99system.physmem.perBankRdBursts::8 12335 # Per bank write bursts 100system.physmem.perBankRdBursts::9 12711 # Per bank write bursts 101system.physmem.perBankRdBursts::10 11891 # Per bank write bursts 102system.physmem.perBankRdBursts::11 11251 # Per bank write bursts 103system.physmem.perBankRdBursts::12 11484 # Per bank write bursts 104system.physmem.perBankRdBursts::13 11698 # Per bank write bursts 105system.physmem.perBankRdBursts::14 10879 # Per bank write bursts 106system.physmem.perBankRdBursts::15 10936 # Per bank write bursts 107system.physmem.perBankWrBursts::0 8367 # Per bank write bursts 108system.physmem.perBankWrBursts::1 8665 # Per bank write bursts 109system.physmem.perBankWrBursts::2 8799 # Per bank write bursts 110system.physmem.perBankWrBursts::3 8189 # Per bank write bursts 111system.physmem.perBankWrBursts::4 7964 # Per bank write bursts 112system.physmem.perBankWrBursts::5 8309 # Per bank write bursts 113system.physmem.perBankWrBursts::6 8959 # Per bank write bursts 114system.physmem.perBankWrBursts::7 8936 # Per bank write bursts 115system.physmem.perBankWrBursts::8 8719 # Per bank write bursts 116system.physmem.perBankWrBursts::9 9048 # Per bank write bursts 117system.physmem.perBankWrBursts::10 8437 # Per bank write bursts 118system.physmem.perBankWrBursts::11 8181 # Per bank write bursts 119system.physmem.perBankWrBursts::12 8223 # Per bank write bursts 120system.physmem.perBankWrBursts::13 7876 # Per bank write bursts 121system.physmem.perBankWrBursts::14 7572 # Per bank write bursts 122system.physmem.perBankWrBursts::15 7309 # Per bank write bursts 123system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 124system.physmem.numWrRetry 22 # Number of times write queue was full causing retry 125system.physmem.totGap 2871819304000 # Total gap between requests 126system.physmem.readPktSize::0 0 # Read request sizes (log2) 127system.physmem.readPktSize::1 0 # Read request sizes (log2) 128system.physmem.readPktSize::2 9732 # Read request sizes (log2) 129system.physmem.readPktSize::3 28 # Read request sizes (log2) 130system.physmem.readPktSize::4 0 # Read request sizes (log2) 131system.physmem.readPktSize::5 0 # Read request sizes (log2) 132system.physmem.readPktSize::6 188148 # Read request sizes (log2) 133system.physmem.writePktSize::0 0 # Write request sizes (log2) 134system.physmem.writePktSize::1 0 # Write request sizes (log2) 135system.physmem.writePktSize::2 4391 # Write request sizes (log2) 136system.physmem.writePktSize::3 0 # Write request sizes (log2) 137system.physmem.writePktSize::4 0 # Write request sizes (log2) 138system.physmem.writePktSize::5 0 # Write request sizes (log2) 139system.physmem.writePktSize::6 133077 # Write request sizes (log2) 140system.physmem.rdQLenPdf::0 139055 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::1 15611 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::2 10231 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::3 8666 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::4 6945 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::5 5399 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::6 4517 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::7 3779 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::8 3330 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::9 87 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::10 68 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::11 39 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::12 12 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::13 6 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 172system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::15 2831 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::16 3304 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::17 4365 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::18 5073 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::19 6173 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::20 6821 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::21 7850 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::22 7805 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::23 8728 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::24 8917 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::25 8948 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::26 10581 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::27 8534 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::28 8466 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::29 9640 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::30 8066 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::31 7235 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::32 6906 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::33 375 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::34 243 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::35 179 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::36 187 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::37 124 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::38 168 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::39 156 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::40 134 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::41 95 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::42 129 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::43 103 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::44 98 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::45 136 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::46 101 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::47 102 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::48 89 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::49 119 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::50 110 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::51 75 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::52 63 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::53 82 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::54 67 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::55 35 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::56 38 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::57 34 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::58 33 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::59 45 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::60 29 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::61 36 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::62 51 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::63 79 # What write queue length does an incoming req see 236system.physmem.bytesPerActivate::samples 87485 # Bytes accessed per row activation 237system.physmem.bytesPerActivate::mean 242.362371 # Bytes accessed per row activation 238system.physmem.bytesPerActivate::gmean 136.946957 # Bytes accessed per row activation 239system.physmem.bytesPerActivate::stdev 304.393854 # Bytes accessed per row activation 240system.physmem.bytesPerActivate::0-127 46305 52.93% 52.93% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::128-255 17523 20.03% 72.96% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::256-383 6069 6.94% 79.90% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::384-511 3389 3.87% 83.77% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::512-639 2483 2.84% 86.61% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::640-767 1521 1.74% 88.35% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::768-895 858 0.98% 89.33% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::896-1023 952 1.09% 90.42% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::1024-1151 8385 9.58% 100.00% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::total 87485 # Bytes accessed per row activation 250system.physmem.rdPerTurnAround::samples 6517 # Reads before turning the bus around for writes 251system.physmem.rdPerTurnAround::mean 30.342949 # Reads before turning the bus around for writes 252system.physmem.rdPerTurnAround::stdev 586.244331 # Reads before turning the bus around for writes 253system.physmem.rdPerTurnAround::0-2047 6515 99.97% 99.97% # Reads before turning the bus around for writes 254system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes 255system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::total 6517 # Reads before turning the bus around for writes 257system.physmem.wrPerTurnAround::samples 6517 # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::mean 20.493018 # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::gmean 18.920871 # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::stdev 12.293044 # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::16-19 5326 81.72% 81.72% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::20-23 466 7.15% 88.88% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::24-27 68 1.04% 89.92% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::28-31 161 2.47% 92.39% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::32-35 25 0.38% 92.77% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::36-39 129 1.98% 94.75% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::40-43 31 0.48% 95.23% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::44-47 20 0.31% 95.53% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::48-51 32 0.49% 96.03% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::52-55 18 0.28% 96.30% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::56-59 9 0.14% 96.44% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::60-63 7 0.11% 96.55% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::64-67 150 2.30% 98.85% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::68-71 6 0.09% 98.94% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::72-75 7 0.11% 99.05% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::76-79 24 0.37% 99.42% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::80-83 5 0.08% 99.49% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::92-95 4 0.06% 99.56% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::96-99 3 0.05% 99.60% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::100-103 1 0.02% 99.62% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::104-107 3 0.05% 99.66% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::108-111 1 0.02% 99.68% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::112-115 3 0.05% 99.72% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::120-123 1 0.02% 99.74% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::124-127 1 0.02% 99.75% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::128-131 9 0.14% 99.89% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::132-135 1 0.02% 99.91% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::144-147 1 0.02% 99.92% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::148-151 1 0.02% 99.94% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::152-155 1 0.02% 99.95% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::156-159 1 0.02% 99.97% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::160-163 1 0.02% 99.98% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::164-167 1 0.02% 100.00% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::total 6517 # Writes before turning the bus around for reads 295system.physmem.totQLat 4471540489 # Total ticks spent queuing 296system.physmem.totMemAccLat 8179277989 # Total ticks spent from burst creation until serviced by the DRAM 297system.physmem.totBusLat 988730000 # Total ticks spent in databus transfers 298system.physmem.avgQLat 22612.55 # Average queueing delay per DRAM burst 299system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 300system.physmem.avgMemAccLat 41362.55 # Average memory access latency per DRAM burst 301system.physmem.avgRdBW 4.41 # Average DRAM read bandwidth in MiByte/s 302system.physmem.avgWrBW 2.98 # Average achieved write bandwidth in MiByte/s 303system.physmem.avgRdBWSys 4.21 # Average system read bandwidth in MiByte/s 304system.physmem.avgWrBWSys 2.97 # Average system write bandwidth in MiByte/s 305system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 306system.physmem.busUtil 0.06 # Data bus utilization in percentage 307system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 308system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 309system.physmem.avgRdQLen 1.13 # Average read queue length when enqueuing 310system.physmem.avgWrQLen 23.95 # Average write queue length when enqueuing 311system.physmem.readRowHits 164996 # Number of row buffer hits during reads 312system.physmem.writeRowHits 78817 # Number of row buffer hits during writes 313system.physmem.readRowHitRate 83.44 # Row buffer hit rate for reads 314system.physmem.writeRowHitRate 59.01 # Row buffer hit rate for writes 315system.physmem.avgGap 8562983.95 # Average gap between requests 316system.physmem.pageHitRate 73.59 # Row buffer hit rate, read and write combined 317system.physmem_0.actEnergy 341636400 # Energy for activate commands per rank (pJ) 318system.physmem_0.preEnergy 186408750 # Energy for precharge commands per rank (pJ) 319system.physmem_0.readEnergy 815575800 # Energy for read commands per rank (pJ) 320system.physmem_0.writeEnergy 441858240 # Energy for write commands per rank (pJ) 321system.physmem_0.refreshEnergy 187573201920 # Energy for refresh commands per rank (pJ) 322system.physmem_0.actBackEnergy 85932696690 # Energy for active background per rank (pJ) 323system.physmem_0.preBackEnergy 1647711485250 # Energy for precharge background per rank (pJ) 324system.physmem_0.totalEnergy 1923002863050 # Total energy per rank (pJ) 325system.physmem_0.averagePower 669.611581 # Core power per rank (mW) 326system.physmem_0.memoryStateTime::IDLE 2740967841659 # Time in different power states 327system.physmem_0.memoryStateTime::REF 95896320000 # Time in different power states 328system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 329system.physmem_0.memoryStateTime::ACT 34954258341 # Time in different power states 330system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 331system.physmem_1.actEnergy 319750200 # Energy for activate commands per rank (pJ) 332system.physmem_1.preEnergy 174466875 # Energy for precharge commands per rank (pJ) 333system.physmem_1.readEnergy 726835200 # Energy for read commands per rank (pJ) 334system.physmem_1.writeEnergy 423565200 # Energy for write commands per rank (pJ) 335system.physmem_1.refreshEnergy 187573201920 # Energy for refresh commands per rank (pJ) 336system.physmem_1.actBackEnergy 85000293540 # Energy for active background per rank (pJ) 337system.physmem_1.preBackEnergy 1648529382750 # Energy for precharge background per rank (pJ) 338system.physmem_1.totalEnergy 1922747495685 # Total energy per rank (pJ) 339system.physmem_1.averagePower 669.522659 # Core power per rank (mW) 340system.physmem_1.memoryStateTime::IDLE 2742335596201 # Time in different power states 341system.physmem_1.memoryStateTime::REF 95896320000 # Time in different power states 342system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 343system.physmem_1.memoryStateTime::ACT 33587665799 # Time in different power states 344system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 345system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 346system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 347system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 348system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 349system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 350system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 351system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 352system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 353system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 354system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) 355system.realview.nvmem.bw_read::cpu1.inst 17 # Total read bandwidth from this memory (bytes/s) 356system.realview.nvmem.bw_read::total 24 # Total read bandwidth from this memory (bytes/s) 357system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) 358system.realview.nvmem.bw_inst_read::cpu1.inst 17 # Instruction read bandwidth from this memory (bytes/s) 359system.realview.nvmem.bw_inst_read::total 24 # Instruction read bandwidth from this memory (bytes/s) 360system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) 361system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s) 362system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s) 363system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 364system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 365system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 366system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 367system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 368system.cf0.dma_write_txs 631 # Number of DMA write transactions. 369system.cpu_clk_domain.clock 500 # Clock period in ticks 370system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 371system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 372system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 373system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 374system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 375system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 376system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 377system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 378system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 379system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 380system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 381system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 382system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 383system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 384system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 385system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 386system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 387system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 388system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 389system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 390system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 391system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 392system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 393system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 394system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 395system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 396system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 397system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 398system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 399system.cpu0.dtb.walker.walks 8797 # Table walker walks requested 400system.cpu0.dtb.walker.walksShort 8797 # Table walker walks initiated with short descriptors 401system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1607 # Level at which table walker walks with short descriptors terminate 402system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 7190 # Level at which table walker walks with short descriptors terminate 403system.cpu0.dtb.walker.walkWaitTime::samples 8797 # Table walker wait (enqueue to first request) latency 404system.cpu0.dtb.walker.walkWaitTime::0 8797 100.00% 100.00% # Table walker wait (enqueue to first request) latency 405system.cpu0.dtb.walker.walkWaitTime::total 8797 # Table walker wait (enqueue to first request) latency 406system.cpu0.dtb.walker.walkCompletionTime::samples 7279 # Table walker service (enqueue to completion) latency 407system.cpu0.dtb.walker.walkCompletionTime::mean 12032.971562 # Table walker service (enqueue to completion) latency 408system.cpu0.dtb.walker.walkCompletionTime::gmean 11059.534367 # Table walker service (enqueue to completion) latency 409system.cpu0.dtb.walker.walkCompletionTime::stdev 6527.254746 # Table walker service (enqueue to completion) latency 410system.cpu0.dtb.walker.walkCompletionTime::0-32767 7242 99.49% 99.49% # Table walker service (enqueue to completion) latency 411system.cpu0.dtb.walker.walkCompletionTime::32768-65535 32 0.44% 99.93% # Table walker service (enqueue to completion) latency 412system.cpu0.dtb.walker.walkCompletionTime::131072-163839 3 0.04% 99.97% # Table walker service (enqueue to completion) latency 413system.cpu0.dtb.walker.walkCompletionTime::163840-196607 1 0.01% 99.99% # Table walker service (enqueue to completion) latency 414system.cpu0.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency 415system.cpu0.dtb.walker.walkCompletionTime::total 7279 # Table walker service (enqueue to completion) latency 416system.cpu0.dtb.walker.walksPending::samples 1809726500 # Table walker pending requests distribution 417system.cpu0.dtb.walker.walksPending::0 1809726500 100.00% 100.00% # Table walker pending requests distribution 418system.cpu0.dtb.walker.walksPending::total 1809726500 # Table walker pending requests distribution 419system.cpu0.dtb.walker.walkPageSizes::4K 5719 78.57% 78.57% # Table walker page sizes translated 420system.cpu0.dtb.walker.walkPageSizes::1M 1560 21.43% 100.00% # Table walker page sizes translated 421system.cpu0.dtb.walker.walkPageSizes::total 7279 # Table walker page sizes translated 422system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 8797 # Table walker requests started/completed, data/inst 423system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 424system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 8797 # Table walker requests started/completed, data/inst 425system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7279 # Table walker requests started/completed, data/inst 426system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 427system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7279 # Table walker requests started/completed, data/inst 428system.cpu0.dtb.walker.walkRequestOrigin::total 16076 # Table walker requests started/completed, data/inst 429system.cpu0.dtb.inst_hits 0 # ITB inst hits 430system.cpu0.dtb.inst_misses 0 # ITB inst misses 431system.cpu0.dtb.read_hits 25745693 # DTB read hits 432system.cpu0.dtb.read_misses 7581 # DTB read misses 433system.cpu0.dtb.write_hits 19246585 # DTB write hits 434system.cpu0.dtb.write_misses 1216 # DTB write misses 435system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 436system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 437system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 438system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 439system.cpu0.dtb.flush_entries 3751 # Number of entries that have been flushed from TLB 440system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 441system.cpu0.dtb.prefetch_faults 1856 # Number of TLB faults due to prefetch 442system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 443system.cpu0.dtb.perms_faults 321 # Number of TLB faults due to permissions restrictions 444system.cpu0.dtb.read_accesses 25753274 # DTB read accesses 445system.cpu0.dtb.write_accesses 19247801 # DTB write accesses 446system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 447system.cpu0.dtb.hits 44992278 # DTB hits 448system.cpu0.dtb.misses 8797 # DTB misses 449system.cpu0.dtb.accesses 45001075 # DTB accesses 450system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 451system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 452system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 453system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 454system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 455system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 456system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 457system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 458system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 459system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 460system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 461system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 462system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 463system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 464system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 465system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 466system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 467system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 468system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 469system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 470system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 471system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 472system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 473system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 474system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 475system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 476system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 477system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 478system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 479system.cpu0.itb.walker.walks 3674 # Table walker walks requested 480system.cpu0.itb.walker.walksShort 3674 # Table walker walks initiated with short descriptors 481system.cpu0.itb.walker.walksShortTerminationLevel::Level1 320 # Level at which table walker walks with short descriptors terminate 482system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3354 # Level at which table walker walks with short descriptors terminate 483system.cpu0.itb.walker.walkWaitTime::samples 3674 # Table walker wait (enqueue to first request) latency 484system.cpu0.itb.walker.walkWaitTime::0 3674 100.00% 100.00% # Table walker wait (enqueue to first request) latency 485system.cpu0.itb.walker.walkWaitTime::total 3674 # Table walker wait (enqueue to first request) latency 486system.cpu0.itb.walker.walkCompletionTime::samples 2576 # Table walker service (enqueue to completion) latency 487system.cpu0.itb.walker.walkCompletionTime::mean 12417.119565 # Table walker service (enqueue to completion) latency 488system.cpu0.itb.walker.walkCompletionTime::gmean 11509.653289 # Table walker service (enqueue to completion) latency 489system.cpu0.itb.walker.walkCompletionTime::stdev 6255.531301 # Table walker service (enqueue to completion) latency 490system.cpu0.itb.walker.walkCompletionTime::0-16383 2268 88.04% 88.04% # Table walker service (enqueue to completion) latency 491system.cpu0.itb.walker.walkCompletionTime::16384-32767 277 10.75% 98.80% # Table walker service (enqueue to completion) latency 492system.cpu0.itb.walker.walkCompletionTime::32768-49151 28 1.09% 99.88% # Table walker service (enqueue to completion) latency 493system.cpu0.itb.walker.walkCompletionTime::49152-65535 1 0.04% 99.92% # Table walker service (enqueue to completion) latency 494system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.04% 99.96% # Table walker service (enqueue to completion) latency 495system.cpu0.itb.walker.walkCompletionTime::163840-180223 1 0.04% 100.00% # Table walker service (enqueue to completion) latency 496system.cpu0.itb.walker.walkCompletionTime::total 2576 # Table walker service (enqueue to completion) latency 497system.cpu0.itb.walker.walksPending::samples 1809154500 # Table walker pending requests distribution 498system.cpu0.itb.walker.walksPending::0 1809154500 100.00% 100.00% # Table walker pending requests distribution 499system.cpu0.itb.walker.walksPending::total 1809154500 # Table walker pending requests distribution 500system.cpu0.itb.walker.walkPageSizes::4K 2256 87.58% 87.58% # Table walker page sizes translated 501system.cpu0.itb.walker.walkPageSizes::1M 320 12.42% 100.00% # Table walker page sizes translated 502system.cpu0.itb.walker.walkPageSizes::total 2576 # Table walker page sizes translated 503system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 504system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3674 # Table walker requests started/completed, data/inst 505system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3674 # Table walker requests started/completed, data/inst 506system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 507system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2576 # Table walker requests started/completed, data/inst 508system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2576 # Table walker requests started/completed, data/inst 509system.cpu0.itb.walker.walkRequestOrigin::total 6250 # Table walker requests started/completed, data/inst 510system.cpu0.itb.inst_hits 121573780 # ITB inst hits 511system.cpu0.itb.inst_misses 3674 # ITB inst misses 512system.cpu0.itb.read_hits 0 # DTB read hits 513system.cpu0.itb.read_misses 0 # DTB read misses 514system.cpu0.itb.write_hits 0 # DTB write hits 515system.cpu0.itb.write_misses 0 # DTB write misses 516system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 517system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 518system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 519system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 520system.cpu0.itb.flush_entries 2371 # Number of entries that have been flushed from TLB 521system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 522system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 523system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 524system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 525system.cpu0.itb.read_accesses 0 # DTB read accesses 526system.cpu0.itb.write_accesses 0 # DTB write accesses 527system.cpu0.itb.inst_accesses 121577454 # ITB inst accesses 528system.cpu0.itb.hits 121573780 # DTB hits 529system.cpu0.itb.misses 3674 # DTB misses 530system.cpu0.itb.accesses 121577454 # DTB accesses 531system.cpu0.numCycles 5743639488 # number of cpu cycles simulated 532system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 533system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 534system.cpu0.kern.inst.arm 0 # number of arm instructions executed 535system.cpu0.kern.inst.quiesce 1907 # number of quiesce instructions executed 536system.cpu0.committedInsts 117757184 # Number of instructions committed 537system.cpu0.committedOps 142314769 # Number of ops (including micro ops) committed 538system.cpu0.num_int_alu_accesses 125928094 # Number of integer alu accesses 539system.cpu0.num_fp_alu_accesses 11483 # Number of float alu accesses 540system.cpu0.num_func_calls 12772213 # number of times a function call or return occured 541system.cpu0.num_conditional_control_insts 16007583 # number of instructions that are conditional controls 542system.cpu0.num_int_insts 125928094 # number of integer instructions 543system.cpu0.num_fp_insts 11483 # number of float instructions 544system.cpu0.num_int_register_reads 231704258 # number of times the integer registers were read 545system.cpu0.num_int_register_writes 87445622 # number of times the integer registers were written 546system.cpu0.num_fp_register_reads 8771 # number of times the floating registers were read 547system.cpu0.num_fp_register_writes 2716 # number of times the floating registers were written 548system.cpu0.num_cc_register_reads 515435615 # number of times the CC registers were read 549system.cpu0.num_cc_register_writes 53492348 # number of times the CC registers were written 550system.cpu0.num_mem_refs 46148278 # number of memory refs 551system.cpu0.num_load_insts 26004695 # Number of load instructions 552system.cpu0.num_store_insts 20143583 # Number of store instructions 553system.cpu0.num_idle_cycles 5456012961.442100 # Number of idle cycles 554system.cpu0.num_busy_cycles 287626526.557900 # Number of busy cycles 555system.cpu0.not_idle_fraction 0.050077 # Percentage of non-idle cycles 556system.cpu0.idle_fraction 0.949923 # Percentage of idle cycles 557system.cpu0.Branches 29545337 # Number of branches fetched 558system.cpu0.op_class::No_OpClass 2315 0.00% 0.00% # Class of executed instruction 559system.cpu0.op_class::IntAlu 99836654 68.33% 68.33% # Class of executed instruction 560system.cpu0.op_class::IntMult 112117 0.08% 68.41% # Class of executed instruction 561system.cpu0.op_class::IntDiv 0 0.00% 68.41% # Class of executed instruction 562system.cpu0.op_class::FloatAdd 0 0.00% 68.41% # Class of executed instruction 563system.cpu0.op_class::FloatCmp 0 0.00% 68.41% # Class of executed instruction 564system.cpu0.op_class::FloatCvt 0 0.00% 68.41% # Class of executed instruction 565system.cpu0.op_class::FloatMult 0 0.00% 68.41% # Class of executed instruction 566system.cpu0.op_class::FloatDiv 0 0.00% 68.41% # Class of executed instruction 567system.cpu0.op_class::FloatSqrt 0 0.00% 68.41% # Class of executed instruction 568system.cpu0.op_class::SimdAdd 0 0.00% 68.41% # Class of executed instruction 569system.cpu0.op_class::SimdAddAcc 0 0.00% 68.41% # Class of executed instruction 570system.cpu0.op_class::SimdAlu 0 0.00% 68.41% # Class of executed instruction 571system.cpu0.op_class::SimdCmp 0 0.00% 68.41% # Class of executed instruction 572system.cpu0.op_class::SimdCvt 0 0.00% 68.41% # Class of executed instruction 573system.cpu0.op_class::SimdMisc 0 0.00% 68.41% # Class of executed instruction 574system.cpu0.op_class::SimdMult 0 0.00% 68.41% # Class of executed instruction 575system.cpu0.op_class::SimdMultAcc 0 0.00% 68.41% # Class of executed instruction 576system.cpu0.op_class::SimdShift 0 0.00% 68.41% # Class of executed instruction 577system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.41% # Class of executed instruction 578system.cpu0.op_class::SimdSqrt 0 0.00% 68.41% # Class of executed instruction 579system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.41% # Class of executed instruction 580system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.41% # Class of executed instruction 581system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.41% # Class of executed instruction 582system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.41% # Class of executed instruction 583system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.41% # Class of executed instruction 584system.cpu0.op_class::SimdFloatMisc 8321 0.01% 68.41% # Class of executed instruction 585system.cpu0.op_class::SimdFloatMult 0 0.00% 68.41% # Class of executed instruction 586system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.41% # Class of executed instruction 587system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.41% # Class of executed instruction 588system.cpu0.op_class::MemRead 26004695 17.80% 86.21% # Class of executed instruction 589system.cpu0.op_class::MemWrite 20143583 13.79% 100.00% # Class of executed instruction 590system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 591system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 592system.cpu0.op_class::total 146107685 # Class of executed instruction 593system.cpu0.dcache.tags.replacements 732170 # number of replacements 594system.cpu0.dcache.tags.tagsinuse 488.694805 # Cycle average of tags in use 595system.cpu0.dcache.tags.total_refs 44080957 # Total number of references to valid blocks. 596system.cpu0.dcache.tags.sampled_refs 732682 # Sample count of references to valid blocks. 597system.cpu0.dcache.tags.avg_refs 60.163832 # Average number of references to valid blocks. 598system.cpu0.dcache.tags.warmup_cycle 1836359000 # Cycle when the warmup percentage was hit. 599system.cpu0.dcache.tags.occ_blocks::cpu0.data 488.694805 # Average occupied blocks per requestor 600system.cpu0.dcache.tags.occ_percent::cpu0.data 0.954482 # Average percentage of cache occupancy 601system.cpu0.dcache.tags.occ_percent::total 0.954482 # Average percentage of cache occupancy 602system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 603system.cpu0.dcache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id 604system.cpu0.dcache.tags.age_task_id_blocks_1024::1 306 # Occupied blocks per task id 605system.cpu0.dcache.tags.age_task_id_blocks_1024::2 99 # Occupied blocks per task id 606system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 607system.cpu0.dcache.tags.tag_accesses 90660887 # Number of tag accesses 608system.cpu0.dcache.tags.data_accesses 90660887 # Number of data accesses 609system.cpu0.dcache.ReadReq_hits::cpu0.data 24440244 # number of ReadReq hits 610system.cpu0.dcache.ReadReq_hits::total 24440244 # number of ReadReq hits 611system.cpu0.dcache.WriteReq_hits::cpu0.data 18493380 # number of WriteReq hits 612system.cpu0.dcache.WriteReq_hits::total 18493380 # number of WriteReq hits 613system.cpu0.dcache.SoftPFReq_hits::cpu0.data 326498 # number of SoftPFReq hits 614system.cpu0.dcache.SoftPFReq_hits::total 326498 # number of SoftPFReq hits 615system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 374202 # number of LoadLockedReq hits 616system.cpu0.dcache.LoadLockedReq_hits::total 374202 # number of LoadLockedReq hits 617system.cpu0.dcache.StoreCondReq_hits::cpu0.data 371573 # number of StoreCondReq hits 618system.cpu0.dcache.StoreCondReq_hits::total 371573 # number of StoreCondReq hits 619system.cpu0.dcache.demand_hits::cpu0.data 42933624 # number of demand (read+write) hits 620system.cpu0.dcache.demand_hits::total 42933624 # number of demand (read+write) hits 621system.cpu0.dcache.overall_hits::cpu0.data 43260122 # number of overall hits 622system.cpu0.dcache.overall_hits::total 43260122 # number of overall hits 623system.cpu0.dcache.ReadReq_misses::cpu0.data 418073 # number of ReadReq misses 624system.cpu0.dcache.ReadReq_misses::total 418073 # number of ReadReq misses 625system.cpu0.dcache.WriteReq_misses::cpu0.data 337261 # number of WriteReq misses 626system.cpu0.dcache.WriteReq_misses::total 337261 # number of WriteReq misses 627system.cpu0.dcache.SoftPFReq_misses::cpu0.data 133156 # number of SoftPFReq misses 628system.cpu0.dcache.SoftPFReq_misses::total 133156 # number of SoftPFReq misses 629system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 22252 # number of LoadLockedReq misses 630system.cpu0.dcache.LoadLockedReq_misses::total 22252 # number of LoadLockedReq misses 631system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19918 # number of StoreCondReq misses 632system.cpu0.dcache.StoreCondReq_misses::total 19918 # number of StoreCondReq misses 633system.cpu0.dcache.demand_misses::cpu0.data 755334 # number of demand (read+write) misses 634system.cpu0.dcache.demand_misses::total 755334 # number of demand (read+write) misses 635system.cpu0.dcache.overall_misses::cpu0.data 888490 # number of overall misses 636system.cpu0.dcache.overall_misses::total 888490 # number of overall misses 637system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5661692500 # number of ReadReq miss cycles 638system.cpu0.dcache.ReadReq_miss_latency::total 5661692500 # number of ReadReq miss cycles 639system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6946372000 # number of WriteReq miss cycles 640system.cpu0.dcache.WriteReq_miss_latency::total 6946372000 # number of WriteReq miss cycles 641system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 344716000 # number of LoadLockedReq miss cycles 642system.cpu0.dcache.LoadLockedReq_miss_latency::total 344716000 # number of LoadLockedReq miss cycles 643system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 507189500 # number of StoreCondReq miss cycles 644system.cpu0.dcache.StoreCondReq_miss_latency::total 507189500 # number of StoreCondReq miss cycles 645system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1629000 # number of StoreCondFailReq miss cycles 646system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1629000 # number of StoreCondFailReq miss cycles 647system.cpu0.dcache.demand_miss_latency::cpu0.data 12608064500 # number of demand (read+write) miss cycles 648system.cpu0.dcache.demand_miss_latency::total 12608064500 # number of demand (read+write) miss cycles 649system.cpu0.dcache.overall_miss_latency::cpu0.data 12608064500 # number of overall miss cycles 650system.cpu0.dcache.overall_miss_latency::total 12608064500 # number of overall miss cycles 651system.cpu0.dcache.ReadReq_accesses::cpu0.data 24858317 # number of ReadReq accesses(hits+misses) 652system.cpu0.dcache.ReadReq_accesses::total 24858317 # number of ReadReq accesses(hits+misses) 653system.cpu0.dcache.WriteReq_accesses::cpu0.data 18830641 # number of WriteReq accesses(hits+misses) 654system.cpu0.dcache.WriteReq_accesses::total 18830641 # number of WriteReq accesses(hits+misses) 655system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 459654 # number of SoftPFReq accesses(hits+misses) 656system.cpu0.dcache.SoftPFReq_accesses::total 459654 # number of SoftPFReq accesses(hits+misses) 657system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 396454 # number of LoadLockedReq accesses(hits+misses) 658system.cpu0.dcache.LoadLockedReq_accesses::total 396454 # number of LoadLockedReq accesses(hits+misses) 659system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 391491 # number of StoreCondReq accesses(hits+misses) 660system.cpu0.dcache.StoreCondReq_accesses::total 391491 # number of StoreCondReq accesses(hits+misses) 661system.cpu0.dcache.demand_accesses::cpu0.data 43688958 # number of demand (read+write) accesses 662system.cpu0.dcache.demand_accesses::total 43688958 # number of demand (read+write) accesses 663system.cpu0.dcache.overall_accesses::cpu0.data 44148612 # number of overall (read+write) accesses 664system.cpu0.dcache.overall_accesses::total 44148612 # number of overall (read+write) accesses 665system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016818 # miss rate for ReadReq accesses 666system.cpu0.dcache.ReadReq_miss_rate::total 0.016818 # miss rate for ReadReq accesses 667system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017910 # miss rate for WriteReq accesses 668system.cpu0.dcache.WriteReq_miss_rate::total 0.017910 # miss rate for WriteReq accesses 669system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.289687 # miss rate for SoftPFReq accesses 670system.cpu0.dcache.SoftPFReq_miss_rate::total 0.289687 # miss rate for SoftPFReq accesses 671system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056128 # miss rate for LoadLockedReq accesses 672system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056128 # miss rate for LoadLockedReq accesses 673system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.050877 # miss rate for StoreCondReq accesses 674system.cpu0.dcache.StoreCondReq_miss_rate::total 0.050877 # miss rate for StoreCondReq accesses 675system.cpu0.dcache.demand_miss_rate::cpu0.data 0.017289 # miss rate for demand accesses 676system.cpu0.dcache.demand_miss_rate::total 0.017289 # miss rate for demand accesses 677system.cpu0.dcache.overall_miss_rate::cpu0.data 0.020125 # miss rate for overall accesses 678system.cpu0.dcache.overall_miss_rate::total 0.020125 # miss rate for overall accesses 679system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13542.353847 # average ReadReq miss latency 680system.cpu0.dcache.ReadReq_avg_miss_latency::total 13542.353847 # average ReadReq miss latency 681system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20596.428286 # average WriteReq miss latency 682system.cpu0.dcache.WriteReq_avg_miss_latency::total 20596.428286 # average WriteReq miss latency 683system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15491.461442 # average LoadLockedReq miss latency 684system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15491.461442 # average LoadLockedReq miss latency 685system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25463.876895 # average StoreCondReq miss latency 686system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25463.876895 # average StoreCondReq miss latency 687system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 688system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 689system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16692.038886 # average overall miss latency 690system.cpu0.dcache.demand_avg_miss_latency::total 16692.038886 # average overall miss latency 691system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14190.440523 # average overall miss latency 692system.cpu0.dcache.overall_avg_miss_latency::total 14190.440523 # average overall miss latency 693system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 694system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 695system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 696system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 697system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 698system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 699system.cpu0.dcache.fast_writes 0 # number of fast writes performed 700system.cpu0.dcache.cache_copies 0 # number of cache copies performed 701system.cpu0.dcache.writebacks::writebacks 732170 # number of writebacks 702system.cpu0.dcache.writebacks::total 732170 # number of writebacks 703system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25278 # number of ReadReq MSHR hits 704system.cpu0.dcache.ReadReq_mshr_hits::total 25278 # number of ReadReq MSHR hits 705system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1 # number of WriteReq MSHR hits 706system.cpu0.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits 707system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15552 # number of LoadLockedReq MSHR hits 708system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15552 # number of LoadLockedReq MSHR hits 709system.cpu0.dcache.demand_mshr_hits::cpu0.data 25279 # number of demand (read+write) MSHR hits 710system.cpu0.dcache.demand_mshr_hits::total 25279 # number of demand (read+write) MSHR hits 711system.cpu0.dcache.overall_mshr_hits::cpu0.data 25279 # number of overall MSHR hits 712system.cpu0.dcache.overall_mshr_hits::total 25279 # number of overall MSHR hits 713system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 392795 # number of ReadReq MSHR misses 714system.cpu0.dcache.ReadReq_mshr_misses::total 392795 # number of ReadReq MSHR misses 715system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 337260 # number of WriteReq MSHR misses 716system.cpu0.dcache.WriteReq_mshr_misses::total 337260 # number of WriteReq MSHR misses 717system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 106103 # number of SoftPFReq MSHR misses 718system.cpu0.dcache.SoftPFReq_mshr_misses::total 106103 # number of SoftPFReq MSHR misses 719system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6700 # number of LoadLockedReq MSHR misses 720system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6700 # number of LoadLockedReq MSHR misses 721system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19918 # number of StoreCondReq MSHR misses 722system.cpu0.dcache.StoreCondReq_mshr_misses::total 19918 # number of StoreCondReq MSHR misses 723system.cpu0.dcache.demand_mshr_misses::cpu0.data 730055 # number of demand (read+write) MSHR misses 724system.cpu0.dcache.demand_mshr_misses::total 730055 # number of demand (read+write) MSHR misses 725system.cpu0.dcache.overall_mshr_misses::cpu0.data 836158 # number of overall MSHR misses 726system.cpu0.dcache.overall_mshr_misses::total 836158 # number of overall MSHR misses 727system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31819 # number of ReadReq MSHR uncacheable 728system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31819 # number of ReadReq MSHR uncacheable 729system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28499 # number of WriteReq MSHR uncacheable 730system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28499 # number of WriteReq MSHR uncacheable 731system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60318 # number of overall MSHR uncacheable misses 732system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60318 # number of overall MSHR uncacheable misses 733system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4839458000 # number of ReadReq MSHR miss cycles 734system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4839458000 # number of ReadReq MSHR miss cycles 735system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6609064500 # number of WriteReq MSHR miss cycles 736system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6609064500 # number of WriteReq MSHR miss cycles 737system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1736821000 # number of SoftPFReq MSHR miss cycles 738system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1736821000 # number of SoftPFReq MSHR miss cycles 739system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 104360500 # number of LoadLockedReq MSHR miss cycles 740system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 104360500 # number of LoadLockedReq MSHR miss cycles 741system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 487321500 # number of StoreCondReq MSHR miss cycles 742system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 487321500 # number of StoreCondReq MSHR miss cycles 743system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1579000 # number of StoreCondFailReq MSHR miss cycles 744system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1579000 # number of StoreCondFailReq MSHR miss cycles 745system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11448522500 # number of demand (read+write) MSHR miss cycles 746system.cpu0.dcache.demand_mshr_miss_latency::total 11448522500 # number of demand (read+write) MSHR miss cycles 747system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13185343500 # number of overall MSHR miss cycles 748system.cpu0.dcache.overall_mshr_miss_latency::total 13185343500 # number of overall MSHR miss cycles 749system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6629856000 # number of ReadReq MSHR uncacheable cycles 750system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6629856000 # number of ReadReq MSHR uncacheable cycles 751system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5400865000 # number of WriteReq MSHR uncacheable cycles 752system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5400865000 # number of WriteReq MSHR uncacheable cycles 753system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12030721000 # number of overall MSHR uncacheable cycles 754system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12030721000 # number of overall MSHR uncacheable cycles 755system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015801 # mshr miss rate for ReadReq accesses 756system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015801 # mshr miss rate for ReadReq accesses 757system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017910 # mshr miss rate for WriteReq accesses 758system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017910 # mshr miss rate for WriteReq accesses 759system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.230832 # mshr miss rate for SoftPFReq accesses 760system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.230832 # mshr miss rate for SoftPFReq accesses 761system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016900 # mshr miss rate for LoadLockedReq accesses 762system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016900 # mshr miss rate for LoadLockedReq accesses 763system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.050877 # mshr miss rate for StoreCondReq accesses 764system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.050877 # mshr miss rate for StoreCondReq accesses 765system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016710 # mshr miss rate for demand accesses 766system.cpu0.dcache.demand_mshr_miss_rate::total 0.016710 # mshr miss rate for demand accesses 767system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018940 # mshr miss rate for overall accesses 768system.cpu0.dcache.overall_mshr_miss_rate::total 0.018940 # mshr miss rate for overall accesses 769system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12320.569254 # average ReadReq mshr miss latency 770system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12320.569254 # average ReadReq mshr miss latency 771system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19596.348514 # average WriteReq mshr miss latency 772system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19596.348514 # average WriteReq mshr miss latency 773system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16369.197855 # average SoftPFReq mshr miss latency 774system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16369.197855 # average SoftPFReq mshr miss latency 775system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15576.194030 # average LoadLockedReq mshr miss latency 776system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15576.194030 # average LoadLockedReq mshr miss latency 777system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24466.387187 # average StoreCondReq mshr miss latency 778system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24466.387187 # average StoreCondReq mshr miss latency 779system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 780system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 781system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15681.726034 # average overall mshr miss latency 782system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15681.726034 # average overall mshr miss latency 783system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15768.961727 # average overall mshr miss latency 784system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15768.961727 # average overall mshr miss latency 785system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208361.544989 # average ReadReq mshr uncacheable latency 786system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208361.544989 # average ReadReq mshr uncacheable latency 787system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189510.684585 # average WriteReq mshr uncacheable latency 788system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189510.684585 # average WriteReq mshr uncacheable latency 789system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 199454.905667 # average overall mshr uncacheable latency 790system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199454.905667 # average overall mshr uncacheable latency 791system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 792system.cpu0.icache.tags.replacements 1146899 # number of replacements 793system.cpu0.icache.tags.tagsinuse 511.321434 # Cycle average of tags in use 794system.cpu0.icache.tags.total_refs 120426360 # Total number of references to valid blocks. 795system.cpu0.icache.tags.sampled_refs 1147411 # Sample count of references to valid blocks. 796system.cpu0.icache.tags.avg_refs 104.954859 # Average number of references to valid blocks. 797system.cpu0.icache.tags.warmup_cycle 14862010000 # Cycle when the warmup percentage was hit. 798system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.321434 # Average occupied blocks per requestor 799system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998675 # Average percentage of cache occupancy 800system.cpu0.icache.tags.occ_percent::total 0.998675 # Average percentage of cache occupancy 801system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 802system.cpu0.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id 803system.cpu0.icache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id 804system.cpu0.icache.tags.age_task_id_blocks_1024::2 223 # Occupied blocks per task id 805system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 806system.cpu0.icache.tags.tag_accesses 244294980 # Number of tag accesses 807system.cpu0.icache.tags.data_accesses 244294980 # Number of data accesses 808system.cpu0.icache.ReadReq_hits::cpu0.inst 120426360 # number of ReadReq hits 809system.cpu0.icache.ReadReq_hits::total 120426360 # number of ReadReq hits 810system.cpu0.icache.demand_hits::cpu0.inst 120426360 # number of demand (read+write) hits 811system.cpu0.icache.demand_hits::total 120426360 # number of demand (read+write) hits 812system.cpu0.icache.overall_hits::cpu0.inst 120426360 # number of overall hits 813system.cpu0.icache.overall_hits::total 120426360 # number of overall hits 814system.cpu0.icache.ReadReq_misses::cpu0.inst 1147420 # number of ReadReq misses 815system.cpu0.icache.ReadReq_misses::total 1147420 # number of ReadReq misses 816system.cpu0.icache.demand_misses::cpu0.inst 1147420 # number of demand (read+write) misses 817system.cpu0.icache.demand_misses::total 1147420 # number of demand (read+write) misses 818system.cpu0.icache.overall_misses::cpu0.inst 1147420 # number of overall misses 819system.cpu0.icache.overall_misses::total 1147420 # number of overall misses 820system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12257879000 # number of ReadReq miss cycles 821system.cpu0.icache.ReadReq_miss_latency::total 12257879000 # number of ReadReq miss cycles 822system.cpu0.icache.demand_miss_latency::cpu0.inst 12257879000 # number of demand (read+write) miss cycles 823system.cpu0.icache.demand_miss_latency::total 12257879000 # number of demand (read+write) miss cycles 824system.cpu0.icache.overall_miss_latency::cpu0.inst 12257879000 # number of overall miss cycles 825system.cpu0.icache.overall_miss_latency::total 12257879000 # number of overall miss cycles 826system.cpu0.icache.ReadReq_accesses::cpu0.inst 121573780 # number of ReadReq accesses(hits+misses) 827system.cpu0.icache.ReadReq_accesses::total 121573780 # number of ReadReq accesses(hits+misses) 828system.cpu0.icache.demand_accesses::cpu0.inst 121573780 # number of demand (read+write) accesses 829system.cpu0.icache.demand_accesses::total 121573780 # number of demand (read+write) accesses 830system.cpu0.icache.overall_accesses::cpu0.inst 121573780 # number of overall (read+write) accesses 831system.cpu0.icache.overall_accesses::total 121573780 # number of overall (read+write) accesses 832system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009438 # miss rate for ReadReq accesses 833system.cpu0.icache.ReadReq_miss_rate::total 0.009438 # miss rate for ReadReq accesses 834system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009438 # miss rate for demand accesses 835system.cpu0.icache.demand_miss_rate::total 0.009438 # miss rate for demand accesses 836system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009438 # miss rate for overall accesses 837system.cpu0.icache.overall_miss_rate::total 0.009438 # miss rate for overall accesses 838system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10682.992278 # average ReadReq miss latency 839system.cpu0.icache.ReadReq_avg_miss_latency::total 10682.992278 # average ReadReq miss latency 840system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10682.992278 # average overall miss latency 841system.cpu0.icache.demand_avg_miss_latency::total 10682.992278 # average overall miss latency 842system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10682.992278 # average overall miss latency 843system.cpu0.icache.overall_avg_miss_latency::total 10682.992278 # average overall miss latency 844system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 845system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 846system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 847system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 848system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 849system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 850system.cpu0.icache.fast_writes 0 # number of fast writes performed 851system.cpu0.icache.cache_copies 0 # number of cache copies performed 852system.cpu0.icache.writebacks::writebacks 1146899 # number of writebacks 853system.cpu0.icache.writebacks::total 1146899 # number of writebacks 854system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1147420 # number of ReadReq MSHR misses 855system.cpu0.icache.ReadReq_mshr_misses::total 1147420 # number of ReadReq MSHR misses 856system.cpu0.icache.demand_mshr_misses::cpu0.inst 1147420 # number of demand (read+write) MSHR misses 857system.cpu0.icache.demand_mshr_misses::total 1147420 # number of demand (read+write) MSHR misses 858system.cpu0.icache.overall_mshr_misses::cpu0.inst 1147420 # number of overall MSHR misses 859system.cpu0.icache.overall_mshr_misses::total 1147420 # number of overall MSHR misses 860system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable 861system.cpu0.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable 862system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses 863system.cpu0.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses 864system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11684169000 # number of ReadReq MSHR miss cycles 865system.cpu0.icache.ReadReq_mshr_miss_latency::total 11684169000 # number of ReadReq MSHR miss cycles 866system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11684169000 # number of demand (read+write) MSHR miss cycles 867system.cpu0.icache.demand_mshr_miss_latency::total 11684169000 # number of demand (read+write) MSHR miss cycles 868system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11684169000 # number of overall MSHR miss cycles 869system.cpu0.icache.overall_mshr_miss_latency::total 11684169000 # number of overall MSHR miss cycles 870system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1253876500 # number of ReadReq MSHR uncacheable cycles 871system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1253876500 # number of ReadReq MSHR uncacheable cycles 872system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1253876500 # number of overall MSHR uncacheable cycles 873system.cpu0.icache.overall_mshr_uncacheable_latency::total 1253876500 # number of overall MSHR uncacheable cycles 874system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009438 # mshr miss rate for ReadReq accesses 875system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009438 # mshr miss rate for ReadReq accesses 876system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009438 # mshr miss rate for demand accesses 877system.cpu0.icache.demand_mshr_miss_rate::total 0.009438 # mshr miss rate for demand accesses 878system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009438 # mshr miss rate for overall accesses 879system.cpu0.icache.overall_mshr_miss_rate::total 0.009438 # mshr miss rate for overall accesses 880system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10182.992278 # average ReadReq mshr miss latency 881system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10182.992278 # average ReadReq mshr miss latency 882system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10182.992278 # average overall mshr miss latency 883system.cpu0.icache.demand_avg_mshr_miss_latency::total 10182.992278 # average overall mshr miss latency 884system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10182.992278 # average overall mshr miss latency 885system.cpu0.icache.overall_avg_mshr_miss_latency::total 10182.992278 # average overall mshr miss latency 886system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138979.882509 # average ReadReq mshr uncacheable latency 887system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138979.882509 # average ReadReq mshr uncacheable latency 888system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138979.882509 # average overall mshr uncacheable latency 889system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138979.882509 # average overall mshr uncacheable latency 890system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 891system.cpu0.l2cache.prefetcher.num_hwpf_issued 1935560 # number of hwpf issued 892system.cpu0.l2cache.prefetcher.pfIdentified 1935650 # number of prefetch candidates identified 893system.cpu0.l2cache.prefetcher.pfBufferHit 78 # number of redundant prefetches already in prefetch queue 894system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 895system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 896system.cpu0.l2cache.prefetcher.pfSpanPage 245750 # number of prefetches not generated due to page crossing 897system.cpu0.l2cache.tags.replacements 273082 # number of replacements 898system.cpu0.l2cache.tags.tagsinuse 16075.027062 # Cycle average of tags in use 899system.cpu0.l2cache.tags.total_refs 3061877 # Total number of references to valid blocks. 900system.cpu0.l2cache.tags.sampled_refs 289178 # Sample count of references to valid blocks. 901system.cpu0.l2cache.tags.avg_refs 10.588209 # Average number of references to valid blocks. 902system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 903system.cpu0.l2cache.tags.occ_blocks::writebacks 14584.410184 # Average occupied blocks per requestor 904system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 2.385544 # Average occupied blocks per requestor 905system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.137322 # Average occupied blocks per requestor 906system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1488.094013 # Average occupied blocks per requestor 907system.cpu0.l2cache.tags.occ_percent::writebacks 0.890162 # Average percentage of cache occupancy 908system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000146 # Average percentage of cache occupancy 909system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000008 # Average percentage of cache occupancy 910system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.090826 # Average percentage of cache occupancy 911system.cpu0.l2cache.tags.occ_percent::total 0.981142 # Average percentage of cache occupancy 912system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1066 # Occupied blocks per task id 913system.cpu0.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id 914system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15022 # Occupied blocks per task id 915system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 17 # Occupied blocks per task id 916system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 271 # Occupied blocks per task id 917system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 320 # Occupied blocks per task id 918system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 458 # Occupied blocks per task id 919system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id 920system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 921system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id 922system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id 923system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 219 # Occupied blocks per task id 924system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3316 # Occupied blocks per task id 925system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7592 # Occupied blocks per task id 926system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3838 # Occupied blocks per task id 927system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.065063 # Percentage of cache occupancy per task id 928system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id 929system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.916870 # Percentage of cache occupancy per task id 930system.cpu0.l2cache.tags.tag_accesses 62794753 # Number of tag accesses 931system.cpu0.l2cache.tags.data_accesses 62794753 # Number of data accesses 932system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 10867 # number of ReadReq hits 933system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4767 # number of ReadReq hits 934system.cpu0.l2cache.ReadReq_hits::total 15634 # number of ReadReq hits 935system.cpu0.l2cache.WritebackDirty_hits::writebacks 501313 # number of WritebackDirty hits 936system.cpu0.l2cache.WritebackDirty_hits::total 501313 # number of WritebackDirty hits 937system.cpu0.l2cache.WritebackClean_hits::writebacks 1348863 # number of WritebackClean hits 938system.cpu0.l2cache.WritebackClean_hits::total 1348863 # number of WritebackClean hits 939system.cpu0.l2cache.ReadExReq_hits::cpu0.data 238469 # number of ReadExReq hits 940system.cpu0.l2cache.ReadExReq_hits::total 238469 # number of ReadExReq hits 941system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1100555 # number of ReadCleanReq hits 942system.cpu0.l2cache.ReadCleanReq_hits::total 1100555 # number of ReadCleanReq hits 943system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 411293 # number of ReadSharedReq hits 944system.cpu0.l2cache.ReadSharedReq_hits::total 411293 # number of ReadSharedReq hits 945system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 10867 # number of demand (read+write) hits 946system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4767 # number of demand (read+write) hits 947system.cpu0.l2cache.demand_hits::cpu0.inst 1100555 # number of demand (read+write) hits 948system.cpu0.l2cache.demand_hits::cpu0.data 649762 # number of demand (read+write) hits 949system.cpu0.l2cache.demand_hits::total 1765951 # number of demand (read+write) hits 950system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 10867 # number of overall hits 951system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4767 # number of overall hits 952system.cpu0.l2cache.overall_hits::cpu0.inst 1100555 # number of overall hits 953system.cpu0.l2cache.overall_hits::cpu0.data 649762 # number of overall hits 954system.cpu0.l2cache.overall_hits::total 1765951 # number of overall hits 955system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 177 # number of ReadReq misses 956system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 76 # number of ReadReq misses 957system.cpu0.l2cache.ReadReq_misses::total 253 # number of ReadReq misses 958system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55141 # number of UpgradeReq misses 959system.cpu0.l2cache.UpgradeReq_misses::total 55141 # number of UpgradeReq misses 960system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19907 # number of SCUpgradeReq misses 961system.cpu0.l2cache.SCUpgradeReq_misses::total 19907 # number of SCUpgradeReq misses 962system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 11 # number of SCUpgradeFailReq misses 963system.cpu0.l2cache.SCUpgradeFailReq_misses::total 11 # number of SCUpgradeFailReq misses 964system.cpu0.l2cache.ReadExReq_misses::cpu0.data 43650 # number of ReadExReq misses 965system.cpu0.l2cache.ReadExReq_misses::total 43650 # number of ReadExReq misses 966system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 46865 # number of ReadCleanReq misses 967system.cpu0.l2cache.ReadCleanReq_misses::total 46865 # number of ReadCleanReq misses 968system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 94305 # number of ReadSharedReq misses 969system.cpu0.l2cache.ReadSharedReq_misses::total 94305 # number of ReadSharedReq misses 970system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 177 # number of demand (read+write) misses 971system.cpu0.l2cache.demand_misses::cpu0.itb.walker 76 # number of demand (read+write) misses 972system.cpu0.l2cache.demand_misses::cpu0.inst 46865 # number of demand (read+write) misses 973system.cpu0.l2cache.demand_misses::cpu0.data 137955 # number of demand (read+write) misses 974system.cpu0.l2cache.demand_misses::total 185073 # number of demand (read+write) misses 975system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 177 # number of overall misses 976system.cpu0.l2cache.overall_misses::cpu0.itb.walker 76 # number of overall misses 977system.cpu0.l2cache.overall_misses::cpu0.inst 46865 # number of overall misses 978system.cpu0.l2cache.overall_misses::cpu0.data 137955 # number of overall misses 979system.cpu0.l2cache.overall_misses::total 185073 # number of overall misses 980system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 4896500 # number of ReadReq miss cycles 981system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2045000 # number of ReadReq miss cycles 982system.cpu0.l2cache.ReadReq_miss_latency::total 6941500 # number of ReadReq miss cycles 983system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 165758000 # number of UpgradeReq miss cycles 984system.cpu0.l2cache.UpgradeReq_miss_latency::total 165758000 # number of UpgradeReq miss cycles 985system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 42773000 # number of SCUpgradeReq miss cycles 986system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 42773000 # number of SCUpgradeReq miss cycles 987system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1499992 # number of SCUpgradeFailReq miss cycles 988system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1499992 # number of SCUpgradeFailReq miss cycles 989system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2791235000 # number of ReadExReq miss cycles 990system.cpu0.l2cache.ReadExReq_miss_latency::total 2791235000 # number of ReadExReq miss cycles 991system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 3308401000 # number of ReadCleanReq miss cycles 992system.cpu0.l2cache.ReadCleanReq_miss_latency::total 3308401000 # number of ReadCleanReq miss cycles 993system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3237666000 # number of ReadSharedReq miss cycles 994system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3237666000 # number of ReadSharedReq miss cycles 995system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 4896500 # number of demand (read+write) miss cycles 996system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2045000 # number of demand (read+write) miss cycles 997system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3308401000 # number of demand (read+write) miss cycles 998system.cpu0.l2cache.demand_miss_latency::cpu0.data 6028901000 # number of demand (read+write) miss cycles 999system.cpu0.l2cache.demand_miss_latency::total 9344243500 # number of demand (read+write) miss cycles 1000system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 4896500 # number of overall miss cycles 1001system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2045000 # number of overall miss cycles 1002system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3308401000 # number of overall miss cycles 1003system.cpu0.l2cache.overall_miss_latency::cpu0.data 6028901000 # number of overall miss cycles 1004system.cpu0.l2cache.overall_miss_latency::total 9344243500 # number of overall miss cycles 1005system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 11044 # number of ReadReq accesses(hits+misses) 1006system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4843 # number of ReadReq accesses(hits+misses) 1007system.cpu0.l2cache.ReadReq_accesses::total 15887 # number of ReadReq accesses(hits+misses) 1008system.cpu0.l2cache.WritebackDirty_accesses::writebacks 501313 # number of WritebackDirty accesses(hits+misses) 1009system.cpu0.l2cache.WritebackDirty_accesses::total 501313 # number of WritebackDirty accesses(hits+misses) 1010system.cpu0.l2cache.WritebackClean_accesses::writebacks 1348863 # number of WritebackClean accesses(hits+misses) 1011system.cpu0.l2cache.WritebackClean_accesses::total 1348863 # number of WritebackClean accesses(hits+misses) 1012system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55141 # number of UpgradeReq accesses(hits+misses) 1013system.cpu0.l2cache.UpgradeReq_accesses::total 55141 # number of UpgradeReq accesses(hits+misses) 1014system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 19907 # number of SCUpgradeReq accesses(hits+misses) 1015system.cpu0.l2cache.SCUpgradeReq_accesses::total 19907 # number of SCUpgradeReq accesses(hits+misses) 1016system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 11 # number of SCUpgradeFailReq accesses(hits+misses) 1017system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 11 # number of SCUpgradeFailReq accesses(hits+misses) 1018system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 282119 # number of ReadExReq accesses(hits+misses) 1019system.cpu0.l2cache.ReadExReq_accesses::total 282119 # number of ReadExReq accesses(hits+misses) 1020system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1147420 # number of ReadCleanReq accesses(hits+misses) 1021system.cpu0.l2cache.ReadCleanReq_accesses::total 1147420 # number of ReadCleanReq accesses(hits+misses) 1022system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 505598 # number of ReadSharedReq accesses(hits+misses) 1023system.cpu0.l2cache.ReadSharedReq_accesses::total 505598 # number of ReadSharedReq accesses(hits+misses) 1024system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 11044 # number of demand (read+write) accesses 1025system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4843 # number of demand (read+write) accesses 1026system.cpu0.l2cache.demand_accesses::cpu0.inst 1147420 # number of demand (read+write) accesses 1027system.cpu0.l2cache.demand_accesses::cpu0.data 787717 # number of demand (read+write) accesses 1028system.cpu0.l2cache.demand_accesses::total 1951024 # number of demand (read+write) accesses 1029system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 11044 # number of overall (read+write) accesses 1030system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4843 # number of overall (read+write) accesses 1031system.cpu0.l2cache.overall_accesses::cpu0.inst 1147420 # number of overall (read+write) accesses 1032system.cpu0.l2cache.overall_accesses::cpu0.data 787717 # number of overall (read+write) accesses 1033system.cpu0.l2cache.overall_accesses::total 1951024 # number of overall (read+write) accesses 1034system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.016027 # miss rate for ReadReq accesses 1035system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.015693 # miss rate for ReadReq accesses 1036system.cpu0.l2cache.ReadReq_miss_rate::total 0.015925 # miss rate for ReadReq accesses 1037system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses 1038system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 1039system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 1040system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1041system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1042system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1043system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.154722 # miss rate for ReadExReq accesses 1044system.cpu0.l2cache.ReadExReq_miss_rate::total 0.154722 # miss rate for ReadExReq accesses 1045system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.040844 # miss rate for ReadCleanReq accesses 1046system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.040844 # miss rate for ReadCleanReq accesses 1047system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.186522 # miss rate for ReadSharedReq accesses 1048system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.186522 # miss rate for ReadSharedReq accesses 1049system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.016027 # miss rate for demand accesses 1050system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.015693 # miss rate for demand accesses 1051system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040844 # miss rate for demand accesses 1052system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.175133 # miss rate for demand accesses 1053system.cpu0.l2cache.demand_miss_rate::total 0.094859 # miss rate for demand accesses 1054system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.016027 # miss rate for overall accesses 1055system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.015693 # miss rate for overall accesses 1056system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040844 # miss rate for overall accesses 1057system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.175133 # miss rate for overall accesses 1058system.cpu0.l2cache.overall_miss_rate::total 0.094859 # miss rate for overall accesses 1059system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 27663.841808 # average ReadReq miss latency 1060system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 26907.894737 # average ReadReq miss latency 1061system.cpu0.l2cache.ReadReq_avg_miss_latency::total 27436.758893 # average ReadReq miss latency 1062system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3006.075334 # average UpgradeReq miss latency 1063system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3006.075334 # average UpgradeReq miss latency 1064system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 2148.641181 # average SCUpgradeReq miss latency 1065system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 2148.641181 # average SCUpgradeReq miss latency 1066system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 136362.909091 # average SCUpgradeFailReq miss latency 1067system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 136362.909091 # average SCUpgradeFailReq miss latency 1068system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 63945.819015 # average ReadExReq miss latency 1069system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 63945.819015 # average ReadExReq miss latency 1070system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 70594.281447 # average ReadCleanReq miss latency 1071system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 70594.281447 # average ReadCleanReq miss latency 1072system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 34331.859392 # average ReadSharedReq miss latency 1073system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 34331.859392 # average ReadSharedReq miss latency 1074system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 27663.841808 # average overall miss latency 1075system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 26907.894737 # average overall miss latency 1076system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 70594.281447 # average overall miss latency 1077system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 43701.939038 # average overall miss latency 1078system.cpu0.l2cache.demand_avg_miss_latency::total 50489.501440 # average overall miss latency 1079system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 27663.841808 # average overall miss latency 1080system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 26907.894737 # average overall miss latency 1081system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 70594.281447 # average overall miss latency 1082system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 43701.939038 # average overall miss latency 1083system.cpu0.l2cache.overall_avg_miss_latency::total 50489.501440 # average overall miss latency 1084system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1085system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1086system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1087system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1088system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1089system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1090system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1091system.cpu0.l2cache.cache_copies 0 # number of cache copies performed 1092system.cpu0.l2cache.writebacks::writebacks 231742 # number of writebacks 1093system.cpu0.l2cache.writebacks::total 231742 # number of writebacks 1094system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1776 # number of ReadExReq MSHR hits 1095system.cpu0.l2cache.ReadExReq_mshr_hits::total 1776 # number of ReadExReq MSHR hits 1096system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 53 # number of ReadSharedReq MSHR hits 1097system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 53 # number of ReadSharedReq MSHR hits 1098system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1829 # number of demand (read+write) MSHR hits 1099system.cpu0.l2cache.demand_mshr_hits::total 1829 # number of demand (read+write) MSHR hits 1100system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1829 # number of overall MSHR hits 1101system.cpu0.l2cache.overall_mshr_hits::total 1829 # number of overall MSHR hits 1102system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 177 # number of ReadReq MSHR misses 1103system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 76 # number of ReadReq MSHR misses 1104system.cpu0.l2cache.ReadReq_mshr_misses::total 253 # number of ReadReq MSHR misses 1105system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 265136 # number of HardPFReq MSHR misses 1106system.cpu0.l2cache.HardPFReq_mshr_misses::total 265136 # number of HardPFReq MSHR misses 1107system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 55141 # number of UpgradeReq MSHR misses 1108system.cpu0.l2cache.UpgradeReq_mshr_misses::total 55141 # number of UpgradeReq MSHR misses 1109system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19907 # number of SCUpgradeReq MSHR misses 1110system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19907 # number of SCUpgradeReq MSHR misses 1111system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 11 # number of SCUpgradeFailReq MSHR misses 1112system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 11 # number of SCUpgradeFailReq MSHR misses 1113system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41874 # number of ReadExReq MSHR misses 1114system.cpu0.l2cache.ReadExReq_mshr_misses::total 41874 # number of ReadExReq MSHR misses 1115system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 46865 # number of ReadCleanReq MSHR misses 1116system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 46865 # number of ReadCleanReq MSHR misses 1117system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 94252 # number of ReadSharedReq MSHR misses 1118system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 94252 # number of ReadSharedReq MSHR misses 1119system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 177 # number of demand (read+write) MSHR misses 1120system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 76 # number of demand (read+write) MSHR misses 1121system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 46865 # number of demand (read+write) MSHR misses 1122system.cpu0.l2cache.demand_mshr_misses::cpu0.data 136126 # number of demand (read+write) MSHR misses 1123system.cpu0.l2cache.demand_mshr_misses::total 183244 # number of demand (read+write) MSHR misses 1124system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 177 # number of overall MSHR misses 1125system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 76 # number of overall MSHR misses 1126system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 46865 # number of overall MSHR misses 1127system.cpu0.l2cache.overall_mshr_misses::cpu0.data 136126 # number of overall MSHR misses 1128system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 265136 # number of overall MSHR misses 1129system.cpu0.l2cache.overall_mshr_misses::total 448380 # number of overall MSHR misses 1130system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable 1131system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31819 # number of ReadReq MSHR uncacheable 1132system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 40841 # number of ReadReq MSHR uncacheable 1133system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28499 # number of WriteReq MSHR uncacheable 1134system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28499 # number of WriteReq MSHR uncacheable 1135system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses 1136system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60318 # number of overall MSHR uncacheable misses 1137system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 69340 # number of overall MSHR uncacheable misses 1138system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 3834500 # number of ReadReq MSHR miss cycles 1139system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 1589000 # number of ReadReq MSHR miss cycles 1140system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 5423500 # number of ReadReq MSHR miss cycles 1141system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 20369501795 # number of HardPFReq MSHR miss cycles 1142system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 20369501795 # number of HardPFReq MSHR miss cycles 1143system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 1428543500 # number of UpgradeReq MSHR miss cycles 1144system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 1428543500 # number of UpgradeReq MSHR miss cycles 1145system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 338252500 # number of SCUpgradeReq MSHR miss cycles 1146system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 338252500 # number of SCUpgradeReq MSHR miss cycles 1147system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1199992 # number of SCUpgradeFailReq MSHR miss cycles 1148system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1199992 # number of SCUpgradeFailReq MSHR miss cycles 1149system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2362760500 # number of ReadExReq MSHR miss cycles 1150system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2362760500 # number of ReadExReq MSHR miss cycles 1151system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 3027211000 # number of ReadCleanReq MSHR miss cycles 1152system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 3027211000 # number of ReadCleanReq MSHR miss cycles 1153system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2665459000 # number of ReadSharedReq MSHR miss cycles 1154system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2665459000 # number of ReadSharedReq MSHR miss cycles 1155system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 3834500 # number of demand (read+write) MSHR miss cycles 1156system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 1589000 # number of demand (read+write) MSHR miss cycles 1157system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3027211000 # number of demand (read+write) MSHR miss cycles 1158system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 5028219500 # number of demand (read+write) MSHR miss cycles 1159system.cpu0.l2cache.demand_mshr_miss_latency::total 8060854000 # number of demand (read+write) MSHR miss cycles 1160system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 3834500 # number of overall MSHR miss cycles 1161system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 1589000 # number of overall MSHR miss cycles 1162system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3027211000 # number of overall MSHR miss cycles 1163system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 5028219500 # number of overall MSHR miss cycles 1164system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 20369501795 # number of overall MSHR miss cycles 1165system.cpu0.l2cache.overall_mshr_miss_latency::total 28430355795 # number of overall MSHR miss cycles 1166system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1186211500 # number of ReadReq MSHR uncacheable cycles 1167system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6374890500 # number of ReadReq MSHR uncacheable cycles 1168system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7561102000 # number of ReadReq MSHR uncacheable cycles 1169system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5187001000 # number of WriteReq MSHR uncacheable cycles 1170system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5187001000 # number of WriteReq MSHR uncacheable cycles 1171system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 1186211500 # number of overall MSHR uncacheable cycles 1172system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11561891500 # number of overall MSHR uncacheable cycles 1173system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12748103000 # number of overall MSHR uncacheable cycles 1174system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.016027 # mshr miss rate for ReadReq accesses 1175system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.015693 # mshr miss rate for ReadReq accesses 1176system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.015925 # mshr miss rate for ReadReq accesses 1177system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1178system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1179system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses 1180system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 1181system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses 1182system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1183system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1184system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1185system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.148427 # mshr miss rate for ReadExReq accesses 1186system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.148427 # mshr miss rate for ReadExReq accesses 1187system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.040844 # mshr miss rate for ReadCleanReq accesses 1188system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040844 # mshr miss rate for ReadCleanReq accesses 1189system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.186417 # mshr miss rate for ReadSharedReq accesses 1190system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.186417 # mshr miss rate for ReadSharedReq accesses 1191system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.016027 # mshr miss rate for demand accesses 1192system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.015693 # mshr miss rate for demand accesses 1193system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.040844 # mshr miss rate for demand accesses 1194system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.172811 # mshr miss rate for demand accesses 1195system.cpu0.l2cache.demand_mshr_miss_rate::total 0.093922 # mshr miss rate for demand accesses 1196system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.016027 # mshr miss rate for overall accesses 1197system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.015693 # mshr miss rate for overall accesses 1198system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.040844 # mshr miss rate for overall accesses 1199system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.172811 # mshr miss rate for overall accesses 1200system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1201system.cpu0.l2cache.overall_mshr_miss_rate::total 0.229818 # mshr miss rate for overall accesses 1202system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 21663.841808 # average ReadReq mshr miss latency 1203system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 20907.894737 # average ReadReq mshr miss latency 1204system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 21436.758893 # average ReadReq mshr miss latency 1205system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 76826.616510 # average HardPFReq mshr miss latency 1206system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 76826.616510 # average HardPFReq mshr miss latency 1207system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 25907.101794 # average UpgradeReq mshr miss latency 1208system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 25907.101794 # average UpgradeReq mshr miss latency 1209system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16991.636108 # average SCUpgradeReq mshr miss latency 1210system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16991.636108 # average SCUpgradeReq mshr miss latency 1211system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 109090.181818 # average SCUpgradeFailReq mshr miss latency 1212system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 109090.181818 # average SCUpgradeFailReq mshr miss latency 1213system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 56425.478817 # average ReadExReq mshr miss latency 1214system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 56425.478817 # average ReadExReq mshr miss latency 1215system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 64594.281447 # average ReadCleanReq mshr miss latency 1216system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64594.281447 # average ReadCleanReq mshr miss latency 1217system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28280.131987 # average ReadSharedReq mshr miss latency 1218system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28280.131987 # average ReadSharedReq mshr miss latency 1219system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 21663.841808 # average overall mshr miss latency 1220system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 20907.894737 # average overall mshr miss latency 1221system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 64594.281447 # average overall mshr miss latency 1222system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 36937.980254 # average overall mshr miss latency 1223system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 43989.729541 # average overall mshr miss latency 1224system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 21663.841808 # average overall mshr miss latency 1225system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 20907.894737 # average overall mshr miss latency 1226system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 64594.281447 # average overall mshr miss latency 1227system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 36937.980254 # average overall mshr miss latency 1228system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 76826.616510 # average overall mshr miss latency 1229system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 63406.833032 # average overall mshr miss latency 1230system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509 # average ReadReq mshr uncacheable latency 1231system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200348.549609 # average ReadReq mshr uncacheable latency 1232system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 185135.084841 # average ReadReq mshr uncacheable latency 1233system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182006.421278 # average WriteReq mshr uncacheable latency 1234system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 182006.421278 # average WriteReq mshr uncacheable latency 1235system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509 # average overall mshr uncacheable latency 1236system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 191682.275606 # average overall mshr uncacheable latency 1237system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 183849.192385 # average overall mshr uncacheable latency 1238system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1239system.cpu0.toL2Bus.snoop_filter.tot_requests 3903345 # Total number of requests made to the snoop filter. 1240system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1968246 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1241system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 28892 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1242system.cpu0.toL2Bus.snoop_filter.tot_snoops 321222 # Total number of snoops made to the snoop filter. 1243system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 317069 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1244system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4153 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1245system.cpu0.toL2Bus.trans_dist::ReadReq 63874 # Transaction distribution 1246system.cpu0.toL2Bus.trans_dist::ReadResp 1765403 # Transaction distribution 1247system.cpu0.toL2Bus.trans_dist::WriteReq 28499 # Transaction distribution 1248system.cpu0.toL2Bus.trans_dist::WriteResp 28499 # Transaction distribution 1249system.cpu0.toL2Bus.trans_dist::WritebackDirty 733576 # Transaction distribution 1250system.cpu0.toL2Bus.trans_dist::WritebackClean 1348863 # Transaction distribution 1251system.cpu0.toL2Bus.trans_dist::CleanEvict 190188 # Transaction distribution 1252system.cpu0.toL2Bus.trans_dist::HardPFReq 312390 # Transaction distribution 1253system.cpu0.toL2Bus.trans_dist::UpgradeReq 85764 # Transaction distribution 1254system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42077 # Transaction distribution 1255system.cpu0.toL2Bus.trans_dist::UpgradeResp 112758 # Transaction distribution 1256system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 45 # Transaction distribution 1257system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 84 # Transaction distribution 1258system.cpu0.toL2Bus.trans_dist::ReadExReq 301102 # Transaction distribution 1259system.cpu0.toL2Bus.trans_dist::ReadExResp 297729 # Transaction distribution 1260system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1147420 # Transaction distribution 1261system.cpu0.toL2Bus.trans_dist::ReadSharedReq 574776 # Transaction distribution 1262system.cpu0.toL2Bus.trans_dist::InvalidateReq 3316 # Transaction distribution 1263system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3438002 # Packet count per connected master and slave (bytes) 1264system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2673168 # Packet count per connected master and slave (bytes) 1265system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11871 # Packet count per connected master and slave (bytes) 1266system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 27031 # Packet count per connected master and slave (bytes) 1267system.cpu0.toL2Bus.pkt_count::total 6150072 # Packet count per connected master and slave (bytes) 1268system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 145478520 # Cumulative packet size per connected master and slave (bytes) 1269system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 101119646 # Cumulative packet size per connected master and slave (bytes) 1270system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 19372 # Cumulative packet size per connected master and slave (bytes) 1271system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 44176 # Cumulative packet size per connected master and slave (bytes) 1272system.cpu0.toL2Bus.pkt_size::total 246661714 # Cumulative packet size per connected master and slave (bytes) 1273system.cpu0.toL2Bus.snoops 988213 # Total snoops (count) 1274system.cpu0.toL2Bus.snoop_fanout::samples 2981714 # Request fanout histogram 1275system.cpu0.toL2Bus.snoop_fanout::mean 0.123543 # Request fanout histogram 1276system.cpu0.toL2Bus.snoop_fanout::stdev 0.333265 # Request fanout histogram 1277system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1278system.cpu0.toL2Bus.snoop_fanout::0 2617497 87.78% 87.78% # Request fanout histogram 1279system.cpu0.toL2Bus.snoop_fanout::1 360064 12.08% 99.86% # Request fanout histogram 1280system.cpu0.toL2Bus.snoop_fanout::2 4153 0.14% 100.00% # Request fanout histogram 1281system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1282system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1283system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1284system.cpu0.toL2Bus.snoop_fanout::total 2981714 # Request fanout histogram 1285system.cpu0.toL2Bus.reqLayer0.occupancy 3884130992 # Layer occupancy (ticks) 1286system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1287system.cpu0.toL2Bus.snoopLayer0.occupancy 115184885 # Layer occupancy (ticks) 1288system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1289system.cpu0.toL2Bus.respLayer0.occupancy 1730152000 # Layer occupancy (ticks) 1290system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1291system.cpu0.toL2Bus.respLayer1.occupancy 1265237983 # Layer occupancy (ticks) 1292system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1293system.cpu0.toL2Bus.respLayer2.occupancy 7028000 # Layer occupancy (ticks) 1294system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1295system.cpu0.toL2Bus.respLayer3.occupancy 15993487 # Layer occupancy (ticks) 1296system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1297system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1298system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1299system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1300system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1301system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1302system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1303system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1304system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1305system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1306system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1307system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1308system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1309system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1310system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1311system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1312system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1313system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1314system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1315system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1316system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1317system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1318system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1319system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1320system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1321system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1322system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1323system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1324system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1325system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1326system.cpu1.dtb.walker.walks 2355 # Table walker walks requested 1327system.cpu1.dtb.walker.walksShort 2355 # Table walker walks initiated with short descriptors 1328system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 481 # Level at which table walker walks with short descriptors terminate 1329system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1874 # Level at which table walker walks with short descriptors terminate 1330system.cpu1.dtb.walker.walkWaitTime::samples 2355 # Table walker wait (enqueue to first request) latency 1331system.cpu1.dtb.walker.walkWaitTime::0 2355 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1332system.cpu1.dtb.walker.walkWaitTime::total 2355 # Table walker wait (enqueue to first request) latency 1333system.cpu1.dtb.walker.walkCompletionTime::samples 1709 # Table walker service (enqueue to completion) latency 1334system.cpu1.dtb.walker.walkCompletionTime::mean 11678.466940 # Table walker service (enqueue to completion) latency 1335system.cpu1.dtb.walker.walkCompletionTime::gmean 11002.721261 # Table walker service (enqueue to completion) latency 1336system.cpu1.dtb.walker.walkCompletionTime::stdev 5695.537695 # Table walker service (enqueue to completion) latency 1337system.cpu1.dtb.walker.walkCompletionTime::0-16383 1565 91.57% 91.57% # Table walker service (enqueue to completion) latency 1338system.cpu1.dtb.walker.walkCompletionTime::16384-32767 135 7.90% 99.47% # Table walker service (enqueue to completion) latency 1339system.cpu1.dtb.walker.walkCompletionTime::32768-49151 5 0.29% 99.77% # Table walker service (enqueue to completion) latency 1340system.cpu1.dtb.walker.walkCompletionTime::49152-65535 3 0.18% 99.94% # Table walker service (enqueue to completion) latency 1341system.cpu1.dtb.walker.walkCompletionTime::147456-163839 1 0.06% 100.00% # Table walker service (enqueue to completion) latency 1342system.cpu1.dtb.walker.walkCompletionTime::total 1709 # Table walker service (enqueue to completion) latency 1343system.cpu1.dtb.walker.walksPending::samples -1207257828 # Table walker pending requests distribution 1344system.cpu1.dtb.walker.walksPending::0 -1207257828 100.00% 100.00% # Table walker pending requests distribution 1345system.cpu1.dtb.walker.walksPending::total -1207257828 # Table walker pending requests distribution 1346system.cpu1.dtb.walker.walkPageSizes::4K 1228 71.85% 71.85% # Table walker page sizes translated 1347system.cpu1.dtb.walker.walkPageSizes::1M 481 28.15% 100.00% # Table walker page sizes translated 1348system.cpu1.dtb.walker.walkPageSizes::total 1709 # Table walker page sizes translated 1349system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 2355 # Table walker requests started/completed, data/inst 1350system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1351system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 2355 # Table walker requests started/completed, data/inst 1352system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1709 # Table walker requests started/completed, data/inst 1353system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1354system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1709 # Table walker requests started/completed, data/inst 1355system.cpu1.dtb.walker.walkRequestOrigin::total 4064 # Table walker requests started/completed, data/inst 1356system.cpu1.dtb.inst_hits 0 # ITB inst hits 1357system.cpu1.dtb.inst_misses 0 # ITB inst misses 1358system.cpu1.dtb.read_hits 3323284 # DTB read hits 1359system.cpu1.dtb.read_misses 1962 # DTB read misses 1360system.cpu1.dtb.write_hits 2909831 # DTB write hits 1361system.cpu1.dtb.write_misses 393 # DTB write misses 1362system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1363system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1364system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1365system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1366system.cpu1.dtb.flush_entries 1652 # Number of entries that have been flushed from TLB 1367system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 1368system.cpu1.dtb.prefetch_faults 231 # Number of TLB faults due to prefetch 1369system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1370system.cpu1.dtb.perms_faults 124 # Number of TLB faults due to permissions restrictions 1371system.cpu1.dtb.read_accesses 3325246 # DTB read accesses 1372system.cpu1.dtb.write_accesses 2910224 # DTB write accesses 1373system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1374system.cpu1.dtb.hits 6233115 # DTB hits 1375system.cpu1.dtb.misses 2355 # DTB misses 1376system.cpu1.dtb.accesses 6235470 # DTB accesses 1377system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1378system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1379system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1380system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1381system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1382system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1383system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1384system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1385system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1386system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1387system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1388system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1389system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1390system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1391system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1392system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1393system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1394system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1395system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1396system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1397system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1398system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1399system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1400system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1401system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1402system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1403system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1404system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1405system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1406system.cpu1.itb.walker.walks 1376 # Table walker walks requested 1407system.cpu1.itb.walker.walksShort 1376 # Table walker walks initiated with short descriptors 1408system.cpu1.itb.walker.walksShortTerminationLevel::Level1 134 # Level at which table walker walks with short descriptors terminate 1409system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1242 # Level at which table walker walks with short descriptors terminate 1410system.cpu1.itb.walker.walkWaitTime::samples 1376 # Table walker wait (enqueue to first request) latency 1411system.cpu1.itb.walker.walkWaitTime::0 1376 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1412system.cpu1.itb.walker.walkWaitTime::total 1376 # Table walker wait (enqueue to first request) latency 1413system.cpu1.itb.walker.walkCompletionTime::samples 819 # Table walker service (enqueue to completion) latency 1414system.cpu1.itb.walker.walkCompletionTime::mean 11895.604396 # Table walker service (enqueue to completion) latency 1415system.cpu1.itb.walker.walkCompletionTime::gmean 11259.508648 # Table walker service (enqueue to completion) latency 1416system.cpu1.itb.walker.walkCompletionTime::stdev 5169.477869 # Table walker service (enqueue to completion) latency 1417system.cpu1.itb.walker.walkCompletionTime::4096-8191 116 14.16% 14.16% # Table walker service (enqueue to completion) latency 1418system.cpu1.itb.walker.walkCompletionTime::8192-12287 583 71.18% 85.35% # Table walker service (enqueue to completion) latency 1419system.cpu1.itb.walker.walkCompletionTime::12288-16383 72 8.79% 94.14% # Table walker service (enqueue to completion) latency 1420system.cpu1.itb.walker.walkCompletionTime::16384-20479 8 0.98% 95.12% # Table walker service (enqueue to completion) latency 1421system.cpu1.itb.walker.walkCompletionTime::20480-24575 1 0.12% 95.24% # Table walker service (enqueue to completion) latency 1422system.cpu1.itb.walker.walkCompletionTime::24576-28671 22 2.69% 97.92% # Table walker service (enqueue to completion) latency 1423system.cpu1.itb.walker.walkCompletionTime::28672-32767 7 0.85% 98.78% # Table walker service (enqueue to completion) latency 1424system.cpu1.itb.walker.walkCompletionTime::32768-36863 1 0.12% 98.90% # Table walker service (enqueue to completion) latency 1425system.cpu1.itb.walker.walkCompletionTime::36864-40959 5 0.61% 99.51% # Table walker service (enqueue to completion) latency 1426system.cpu1.itb.walker.walkCompletionTime::40960-45055 1 0.12% 99.63% # Table walker service (enqueue to completion) latency 1427system.cpu1.itb.walker.walkCompletionTime::49152-53247 3 0.37% 100.00% # Table walker service (enqueue to completion) latency 1428system.cpu1.itb.walker.walkCompletionTime::total 819 # Table walker service (enqueue to completion) latency 1429system.cpu1.itb.walker.walksPending::samples -1208095828 # Table walker pending requests distribution 1430system.cpu1.itb.walker.walksPending::0 -1208095828 100.00% 100.00% # Table walker pending requests distribution 1431system.cpu1.itb.walker.walksPending::total -1208095828 # Table walker pending requests distribution 1432system.cpu1.itb.walker.walkPageSizes::4K 685 83.64% 83.64% # Table walker page sizes translated 1433system.cpu1.itb.walker.walkPageSizes::1M 134 16.36% 100.00% # Table walker page sizes translated 1434system.cpu1.itb.walker.walkPageSizes::total 819 # Table walker page sizes translated 1435system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1436system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1376 # Table walker requests started/completed, data/inst 1437system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1376 # Table walker requests started/completed, data/inst 1438system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1439system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 819 # Table walker requests started/completed, data/inst 1440system.cpu1.itb.walker.walkRequestOrigin_Completed::total 819 # Table walker requests started/completed, data/inst 1441system.cpu1.itb.walker.walkRequestOrigin::total 2195 # Table walker requests started/completed, data/inst 1442system.cpu1.itb.inst_hits 13877832 # ITB inst hits 1443system.cpu1.itb.inst_misses 1376 # ITB inst misses 1444system.cpu1.itb.read_hits 0 # DTB read hits 1445system.cpu1.itb.read_misses 0 # DTB read misses 1446system.cpu1.itb.write_hits 0 # DTB write hits 1447system.cpu1.itb.write_misses 0 # DTB write misses 1448system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1449system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1450system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1451system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1452system.cpu1.itb.flush_entries 883 # Number of entries that have been flushed from TLB 1453system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1454system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1455system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1456system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1457system.cpu1.itb.read_accesses 0 # DTB read accesses 1458system.cpu1.itb.write_accesses 0 # DTB write accesses 1459system.cpu1.itb.inst_accesses 13879208 # ITB inst accesses 1460system.cpu1.itb.hits 13877832 # DTB hits 1461system.cpu1.itb.misses 1376 # DTB misses 1462system.cpu1.itb.accesses 13879208 # DTB accesses 1463system.cpu1.numCycles 5742698802 # number of cpu cycles simulated 1464system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1465system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1466system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1467system.cpu1.kern.inst.quiesce 2717 # number of quiesce instructions executed 1468system.cpu1.committedInsts 13679150 # Number of instructions committed 1469system.cpu1.committedOps 16668513 # Number of ops (including micro ops) committed 1470system.cpu1.num_int_alu_accesses 15113644 # Number of integer alu accesses 1471system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses 1472system.cpu1.num_func_calls 913162 # number of times a function call or return occured 1473system.cpu1.num_conditional_control_insts 1492467 # number of instructions that are conditional controls 1474system.cpu1.num_int_insts 15113644 # number of integer instructions 1475system.cpu1.num_fp_insts 0 # number of float instructions 1476system.cpu1.num_int_register_reads 27463830 # number of times the integer registers were read 1477system.cpu1.num_int_register_writes 10666857 # number of times the integer registers were written 1478system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read 1479system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written 1480system.cpu1.num_cc_register_reads 61159895 # number of times the CC registers were read 1481system.cpu1.num_cc_register_writes 5174219 # number of times the CC registers were written 1482system.cpu1.num_mem_refs 6447631 # number of memory refs 1483system.cpu1.num_load_insts 3428751 # Number of load instructions 1484system.cpu1.num_store_insts 3018880 # Number of store instructions 1485system.cpu1.num_idle_cycles 5696160545.959164 # Number of idle cycles 1486system.cpu1.num_busy_cycles 46538256.040836 # Number of busy cycles 1487system.cpu1.not_idle_fraction 0.008104 # Percentage of non-idle cycles 1488system.cpu1.idle_fraction 0.991896 # Percentage of idle cycles 1489system.cpu1.Branches 2456488 # Number of branches fetched 1490system.cpu1.op_class::No_OpClass 24 0.00% 0.00% # Class of executed instruction 1491system.cpu1.op_class::IntAlu 10511910 61.88% 61.88% # Class of executed instruction 1492system.cpu1.op_class::IntMult 24272 0.14% 62.03% # Class of executed instruction 1493system.cpu1.op_class::IntDiv 0 0.00% 62.03% # Class of executed instruction 1494system.cpu1.op_class::FloatAdd 0 0.00% 62.03% # Class of executed instruction 1495system.cpu1.op_class::FloatCmp 0 0.00% 62.03% # Class of executed instruction 1496system.cpu1.op_class::FloatCvt 0 0.00% 62.03% # Class of executed instruction 1497system.cpu1.op_class::FloatMult 0 0.00% 62.03% # Class of executed instruction 1498system.cpu1.op_class::FloatDiv 0 0.00% 62.03% # Class of executed instruction 1499system.cpu1.op_class::FloatSqrt 0 0.00% 62.03% # Class of executed instruction 1500system.cpu1.op_class::SimdAdd 0 0.00% 62.03% # Class of executed instruction 1501system.cpu1.op_class::SimdAddAcc 0 0.00% 62.03% # Class of executed instruction 1502system.cpu1.op_class::SimdAlu 0 0.00% 62.03% # Class of executed instruction 1503system.cpu1.op_class::SimdCmp 0 0.00% 62.03% # Class of executed instruction 1504system.cpu1.op_class::SimdCvt 0 0.00% 62.03% # Class of executed instruction 1505system.cpu1.op_class::SimdMisc 0 0.00% 62.03% # Class of executed instruction 1506system.cpu1.op_class::SimdMult 0 0.00% 62.03% # Class of executed instruction 1507system.cpu1.op_class::SimdMultAcc 0 0.00% 62.03% # Class of executed instruction 1508system.cpu1.op_class::SimdShift 0 0.00% 62.03% # Class of executed instruction 1509system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.03% # Class of executed instruction 1510system.cpu1.op_class::SimdSqrt 0 0.00% 62.03% # Class of executed instruction 1511system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.03% # Class of executed instruction 1512system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.03% # Class of executed instruction 1513system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.03% # Class of executed instruction 1514system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.03% # Class of executed instruction 1515system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.03% # Class of executed instruction 1516system.cpu1.op_class::SimdFloatMisc 3188 0.02% 62.04% # Class of executed instruction 1517system.cpu1.op_class::SimdFloatMult 0 0.00% 62.04% # Class of executed instruction 1518system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.04% # Class of executed instruction 1519system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.04% # Class of executed instruction 1520system.cpu1.op_class::MemRead 3428751 20.18% 82.23% # Class of executed instruction 1521system.cpu1.op_class::MemWrite 3018880 17.77% 100.00% # Class of executed instruction 1522system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 1523system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 1524system.cpu1.op_class::total 16987025 # Class of executed instruction 1525system.cpu1.dcache.tags.replacements 147592 # number of replacements 1526system.cpu1.dcache.tags.tagsinuse 468.392474 # Cycle average of tags in use 1527system.cpu1.dcache.tags.total_refs 6004450 # Total number of references to valid blocks. 1528system.cpu1.dcache.tags.sampled_refs 147942 # Sample count of references to valid blocks. 1529system.cpu1.dcache.tags.avg_refs 40.586514 # Average number of references to valid blocks. 1530system.cpu1.dcache.tags.warmup_cycle 106294932000 # Cycle when the warmup percentage was hit. 1531system.cpu1.dcache.tags.occ_blocks::cpu1.data 468.392474 # Average occupied blocks per requestor 1532system.cpu1.dcache.tags.occ_percent::cpu1.data 0.914829 # Average percentage of cache occupancy 1533system.cpu1.dcache.tags.occ_percent::total 0.914829 # Average percentage of cache occupancy 1534system.cpu1.dcache.tags.occ_task_id_blocks::1024 350 # Occupied blocks per task id 1535system.cpu1.dcache.tags.age_task_id_blocks_1024::2 318 # Occupied blocks per task id 1536system.cpu1.dcache.tags.age_task_id_blocks_1024::3 32 # Occupied blocks per task id 1537system.cpu1.dcache.tags.occ_task_id_percent::1024 0.683594 # Percentage of cache occupancy per task id 1538system.cpu1.dcache.tags.tag_accesses 12646180 # Number of tag accesses 1539system.cpu1.dcache.tags.data_accesses 12646180 # Number of data accesses 1540system.cpu1.dcache.ReadReq_hits::cpu1.data 3055213 # number of ReadReq hits 1541system.cpu1.dcache.ReadReq_hits::total 3055213 # number of ReadReq hits 1542system.cpu1.dcache.WriteReq_hits::cpu1.data 2743263 # number of WriteReq hits 1543system.cpu1.dcache.WriteReq_hits::total 2743263 # number of WriteReq hits 1544system.cpu1.dcache.SoftPFReq_hits::cpu1.data 41902 # number of SoftPFReq hits 1545system.cpu1.dcache.SoftPFReq_hits::total 41902 # number of SoftPFReq hits 1546system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 69872 # number of LoadLockedReq hits 1547system.cpu1.dcache.LoadLockedReq_hits::total 69872 # number of LoadLockedReq hits 1548system.cpu1.dcache.StoreCondReq_hits::cpu1.data 61606 # number of StoreCondReq hits 1549system.cpu1.dcache.StoreCondReq_hits::total 61606 # number of StoreCondReq hits 1550system.cpu1.dcache.demand_hits::cpu1.data 5798476 # number of demand (read+write) hits 1551system.cpu1.dcache.demand_hits::total 5798476 # number of demand (read+write) hits 1552system.cpu1.dcache.overall_hits::cpu1.data 5840378 # number of overall hits 1553system.cpu1.dcache.overall_hits::total 5840378 # number of overall hits 1554system.cpu1.dcache.ReadReq_misses::cpu1.data 112221 # number of ReadReq misses 1555system.cpu1.dcache.ReadReq_misses::total 112221 # number of ReadReq misses 1556system.cpu1.dcache.WriteReq_misses::cpu1.data 79294 # number of WriteReq misses 1557system.cpu1.dcache.WriteReq_misses::total 79294 # number of WriteReq misses 1558system.cpu1.dcache.SoftPFReq_misses::cpu1.data 24421 # number of SoftPFReq misses 1559system.cpu1.dcache.SoftPFReq_misses::total 24421 # number of SoftPFReq misses 1560system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16601 # number of LoadLockedReq misses 1561system.cpu1.dcache.LoadLockedReq_misses::total 16601 # number of LoadLockedReq misses 1562system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23085 # number of StoreCondReq misses 1563system.cpu1.dcache.StoreCondReq_misses::total 23085 # number of StoreCondReq misses 1564system.cpu1.dcache.demand_misses::cpu1.data 191515 # number of demand (read+write) misses 1565system.cpu1.dcache.demand_misses::total 191515 # number of demand (read+write) misses 1566system.cpu1.dcache.overall_misses::cpu1.data 215936 # number of overall misses 1567system.cpu1.dcache.overall_misses::total 215936 # number of overall misses 1568system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1751790500 # number of ReadReq miss cycles 1569system.cpu1.dcache.ReadReq_miss_latency::total 1751790500 # number of ReadReq miss cycles 1570system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2724343500 # number of WriteReq miss cycles 1571system.cpu1.dcache.WriteReq_miss_latency::total 2724343500 # number of WriteReq miss cycles 1572system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 320772500 # number of LoadLockedReq miss cycles 1573system.cpu1.dcache.LoadLockedReq_miss_latency::total 320772500 # number of LoadLockedReq miss cycles 1574system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 629240500 # number of StoreCondReq miss cycles 1575system.cpu1.dcache.StoreCondReq_miss_latency::total 629240500 # number of StoreCondReq miss cycles 1576system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3762500 # number of StoreCondFailReq miss cycles 1577system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3762500 # number of StoreCondFailReq miss cycles 1578system.cpu1.dcache.demand_miss_latency::cpu1.data 4476134000 # number of demand (read+write) miss cycles 1579system.cpu1.dcache.demand_miss_latency::total 4476134000 # number of demand (read+write) miss cycles 1580system.cpu1.dcache.overall_miss_latency::cpu1.data 4476134000 # number of overall miss cycles 1581system.cpu1.dcache.overall_miss_latency::total 4476134000 # number of overall miss cycles 1582system.cpu1.dcache.ReadReq_accesses::cpu1.data 3167434 # number of ReadReq accesses(hits+misses) 1583system.cpu1.dcache.ReadReq_accesses::total 3167434 # number of ReadReq accesses(hits+misses) 1584system.cpu1.dcache.WriteReq_accesses::cpu1.data 2822557 # number of WriteReq accesses(hits+misses) 1585system.cpu1.dcache.WriteReq_accesses::total 2822557 # number of WriteReq accesses(hits+misses) 1586system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 66323 # number of SoftPFReq accesses(hits+misses) 1587system.cpu1.dcache.SoftPFReq_accesses::total 66323 # number of SoftPFReq accesses(hits+misses) 1588system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 86473 # number of LoadLockedReq accesses(hits+misses) 1589system.cpu1.dcache.LoadLockedReq_accesses::total 86473 # number of LoadLockedReq accesses(hits+misses) 1590system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 84691 # number of StoreCondReq accesses(hits+misses) 1591system.cpu1.dcache.StoreCondReq_accesses::total 84691 # number of StoreCondReq accesses(hits+misses) 1592system.cpu1.dcache.demand_accesses::cpu1.data 5989991 # number of demand (read+write) accesses 1593system.cpu1.dcache.demand_accesses::total 5989991 # number of demand (read+write) accesses 1594system.cpu1.dcache.overall_accesses::cpu1.data 6056314 # number of overall (read+write) accesses 1595system.cpu1.dcache.overall_accesses::total 6056314 # number of overall (read+write) accesses 1596system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035430 # miss rate for ReadReq accesses 1597system.cpu1.dcache.ReadReq_miss_rate::total 0.035430 # miss rate for ReadReq accesses 1598system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.028093 # miss rate for WriteReq accesses 1599system.cpu1.dcache.WriteReq_miss_rate::total 0.028093 # miss rate for WriteReq accesses 1600system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.368213 # miss rate for SoftPFReq accesses 1601system.cpu1.dcache.SoftPFReq_miss_rate::total 0.368213 # miss rate for SoftPFReq accesses 1602system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.191979 # miss rate for LoadLockedReq accesses 1603system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.191979 # miss rate for LoadLockedReq accesses 1604system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.272579 # miss rate for StoreCondReq accesses 1605system.cpu1.dcache.StoreCondReq_miss_rate::total 0.272579 # miss rate for StoreCondReq accesses 1606system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031973 # miss rate for demand accesses 1607system.cpu1.dcache.demand_miss_rate::total 0.031973 # miss rate for demand accesses 1608system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035655 # miss rate for overall accesses 1609system.cpu1.dcache.overall_miss_rate::total 0.035655 # miss rate for overall accesses 1610system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15610.184368 # average ReadReq miss latency 1611system.cpu1.dcache.ReadReq_avg_miss_latency::total 15610.184368 # average ReadReq miss latency 1612system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34357.498676 # average WriteReq miss latency 1613system.cpu1.dcache.WriteReq_avg_miss_latency::total 34357.498676 # average WriteReq miss latency 1614system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19322.480573 # average LoadLockedReq miss latency 1615system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19322.480573 # average LoadLockedReq miss latency 1616system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27257.548191 # average StoreCondReq miss latency 1617system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27257.548191 # average StoreCondReq miss latency 1618system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1619system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1620system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23372.237162 # average overall miss latency 1621system.cpu1.dcache.demand_avg_miss_latency::total 23372.237162 # average overall miss latency 1622system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20728.984514 # average overall miss latency 1623system.cpu1.dcache.overall_avg_miss_latency::total 20728.984514 # average overall miss latency 1624system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1625system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1626system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1627system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1628system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1629system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1630system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1631system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1632system.cpu1.dcache.writebacks::writebacks 147592 # number of writebacks 1633system.cpu1.dcache.writebacks::total 147592 # number of writebacks 1634system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 221 # number of ReadReq MSHR hits 1635system.cpu1.dcache.ReadReq_mshr_hits::total 221 # number of ReadReq MSHR hits 1636system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 11676 # number of LoadLockedReq MSHR hits 1637system.cpu1.dcache.LoadLockedReq_mshr_hits::total 11676 # number of LoadLockedReq MSHR hits 1638system.cpu1.dcache.demand_mshr_hits::cpu1.data 221 # number of demand (read+write) MSHR hits 1639system.cpu1.dcache.demand_mshr_hits::total 221 # number of demand (read+write) MSHR hits 1640system.cpu1.dcache.overall_mshr_hits::cpu1.data 221 # number of overall MSHR hits 1641system.cpu1.dcache.overall_mshr_hits::total 221 # number of overall MSHR hits 1642system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 112000 # number of ReadReq MSHR misses 1643system.cpu1.dcache.ReadReq_mshr_misses::total 112000 # number of ReadReq MSHR misses 1644system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 79294 # number of WriteReq MSHR misses 1645system.cpu1.dcache.WriteReq_mshr_misses::total 79294 # number of WriteReq MSHR misses 1646system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 23950 # number of SoftPFReq MSHR misses 1647system.cpu1.dcache.SoftPFReq_mshr_misses::total 23950 # number of SoftPFReq MSHR misses 1648system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4925 # number of LoadLockedReq MSHR misses 1649system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4925 # number of LoadLockedReq MSHR misses 1650system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23085 # number of StoreCondReq MSHR misses 1651system.cpu1.dcache.StoreCondReq_mshr_misses::total 23085 # number of StoreCondReq MSHR misses 1652system.cpu1.dcache.demand_mshr_misses::cpu1.data 191294 # number of demand (read+write) MSHR misses 1653system.cpu1.dcache.demand_mshr_misses::total 191294 # number of demand (read+write) MSHR misses 1654system.cpu1.dcache.overall_mshr_misses::cpu1.data 215244 # number of overall MSHR misses 1655system.cpu1.dcache.overall_mshr_misses::total 215244 # number of overall MSHR misses 1656system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3081 # number of ReadReq MSHR uncacheable 1657system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3081 # number of ReadReq MSHR uncacheable 1658system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2423 # number of WriteReq MSHR uncacheable 1659system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2423 # number of WriteReq MSHR uncacheable 1660system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5504 # number of overall MSHR uncacheable misses 1661system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5504 # number of overall MSHR uncacheable misses 1662system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1626671000 # number of ReadReq MSHR miss cycles 1663system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1626671000 # number of ReadReq MSHR miss cycles 1664system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2645049500 # number of WriteReq MSHR miss cycles 1665system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2645049500 # number of WriteReq MSHR miss cycles 1666system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 437326000 # number of SoftPFReq MSHR miss cycles 1667system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 437326000 # number of SoftPFReq MSHR miss cycles 1668system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 90573500 # number of LoadLockedReq MSHR miss cycles 1669system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 90573500 # number of LoadLockedReq MSHR miss cycles 1670system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 606189500 # number of StoreCondReq MSHR miss cycles 1671system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 606189500 # number of StoreCondReq MSHR miss cycles 1672system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3728500 # number of StoreCondFailReq MSHR miss cycles 1673system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3728500 # number of StoreCondFailReq MSHR miss cycles 1674system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4271720500 # number of demand (read+write) MSHR miss cycles 1675system.cpu1.dcache.demand_mshr_miss_latency::total 4271720500 # number of demand (read+write) MSHR miss cycles 1676system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4709046500 # number of overall MSHR miss cycles 1677system.cpu1.dcache.overall_mshr_miss_latency::total 4709046500 # number of overall MSHR miss cycles 1678system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 439448500 # number of ReadReq MSHR uncacheable cycles 1679system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 439448500 # number of ReadReq MSHR uncacheable cycles 1680system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 303112500 # number of WriteReq MSHR uncacheable cycles 1681system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 303112500 # number of WriteReq MSHR uncacheable cycles 1682system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 742561000 # number of overall MSHR uncacheable cycles 1683system.cpu1.dcache.overall_mshr_uncacheable_latency::total 742561000 # number of overall MSHR uncacheable cycles 1684system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035360 # mshr miss rate for ReadReq accesses 1685system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035360 # mshr miss rate for ReadReq accesses 1686system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028093 # mshr miss rate for WriteReq accesses 1687system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028093 # mshr miss rate for WriteReq accesses 1688system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.361112 # mshr miss rate for SoftPFReq accesses 1689system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.361112 # mshr miss rate for SoftPFReq accesses 1690system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.056954 # mshr miss rate for LoadLockedReq accesses 1691system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.056954 # mshr miss rate for LoadLockedReq accesses 1692system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.272579 # mshr miss rate for StoreCondReq accesses 1693system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.272579 # mshr miss rate for StoreCondReq accesses 1694system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031936 # mshr miss rate for demand accesses 1695system.cpu1.dcache.demand_mshr_miss_rate::total 0.031936 # mshr miss rate for demand accesses 1696system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035540 # mshr miss rate for overall accesses 1697system.cpu1.dcache.overall_mshr_miss_rate::total 0.035540 # mshr miss rate for overall accesses 1698system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14523.848214 # average ReadReq mshr miss latency 1699system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14523.848214 # average ReadReq mshr miss latency 1700system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33357.498676 # average WriteReq mshr miss latency 1701system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33357.498676 # average WriteReq mshr miss latency 1702system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18259.958246 # average SoftPFReq mshr miss latency 1703system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 18259.958246 # average SoftPFReq mshr miss latency 1704system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18390.558376 # average LoadLockedReq mshr miss latency 1705system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18390.558376 # average LoadLockedReq mshr miss latency 1706system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26259.021009 # average StoreCondReq mshr miss latency 1707system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26259.021009 # average StoreCondReq mshr miss latency 1708system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1709system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1710system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22330.655954 # average overall mshr miss latency 1711system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22330.655954 # average overall mshr miss latency 1712system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21877.713200 # average overall mshr miss latency 1713system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21877.713200 # average overall mshr miss latency 1714system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 142631.775398 # average ReadReq mshr uncacheable latency 1715system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 142631.775398 # average ReadReq mshr uncacheable latency 1716system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 125098.018985 # average WriteReq mshr uncacheable latency 1717system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 125098.018985 # average WriteReq mshr uncacheable latency 1718system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 134912.972384 # average overall mshr uncacheable latency 1719system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 134912.972384 # average overall mshr uncacheable latency 1720system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1721system.cpu1.icache.tags.replacements 463636 # number of replacements 1722system.cpu1.icache.tags.tagsinuse 498.311121 # Cycle average of tags in use 1723system.cpu1.icache.tags.total_refs 13413679 # Total number of references to valid blocks. 1724system.cpu1.icache.tags.sampled_refs 464148 # Sample count of references to valid blocks. 1725system.cpu1.icache.tags.avg_refs 28.899573 # Average number of references to valid blocks. 1726system.cpu1.icache.tags.warmup_cycle 106195496500 # Cycle when the warmup percentage was hit. 1727system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.311121 # Average occupied blocks per requestor 1728system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973264 # Average percentage of cache occupancy 1729system.cpu1.icache.tags.occ_percent::total 0.973264 # Average percentage of cache occupancy 1730system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1731system.cpu1.icache.tags.age_task_id_blocks_1024::2 387 # Occupied blocks per task id 1732system.cpu1.icache.tags.age_task_id_blocks_1024::3 118 # Occupied blocks per task id 1733system.cpu1.icache.tags.age_task_id_blocks_1024::4 7 # Occupied blocks per task id 1734system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1735system.cpu1.icache.tags.tag_accesses 28219802 # Number of tag accesses 1736system.cpu1.icache.tags.data_accesses 28219802 # Number of data accesses 1737system.cpu1.icache.ReadReq_hits::cpu1.inst 13413679 # number of ReadReq hits 1738system.cpu1.icache.ReadReq_hits::total 13413679 # number of ReadReq hits 1739system.cpu1.icache.demand_hits::cpu1.inst 13413679 # number of demand (read+write) hits 1740system.cpu1.icache.demand_hits::total 13413679 # number of demand (read+write) hits 1741system.cpu1.icache.overall_hits::cpu1.inst 13413679 # number of overall hits 1742system.cpu1.icache.overall_hits::total 13413679 # number of overall hits 1743system.cpu1.icache.ReadReq_misses::cpu1.inst 464148 # number of ReadReq misses 1744system.cpu1.icache.ReadReq_misses::total 464148 # number of ReadReq misses 1745system.cpu1.icache.demand_misses::cpu1.inst 464148 # number of demand (read+write) misses 1746system.cpu1.icache.demand_misses::total 464148 # number of demand (read+write) misses 1747system.cpu1.icache.overall_misses::cpu1.inst 464148 # number of overall misses 1748system.cpu1.icache.overall_misses::total 464148 # number of overall misses 1749system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4215419500 # number of ReadReq miss cycles 1750system.cpu1.icache.ReadReq_miss_latency::total 4215419500 # number of ReadReq miss cycles 1751system.cpu1.icache.demand_miss_latency::cpu1.inst 4215419500 # number of demand (read+write) miss cycles 1752system.cpu1.icache.demand_miss_latency::total 4215419500 # number of demand (read+write) miss cycles 1753system.cpu1.icache.overall_miss_latency::cpu1.inst 4215419500 # number of overall miss cycles 1754system.cpu1.icache.overall_miss_latency::total 4215419500 # number of overall miss cycles 1755system.cpu1.icache.ReadReq_accesses::cpu1.inst 13877827 # number of ReadReq accesses(hits+misses) 1756system.cpu1.icache.ReadReq_accesses::total 13877827 # number of ReadReq accesses(hits+misses) 1757system.cpu1.icache.demand_accesses::cpu1.inst 13877827 # number of demand (read+write) accesses 1758system.cpu1.icache.demand_accesses::total 13877827 # number of demand (read+write) accesses 1759system.cpu1.icache.overall_accesses::cpu1.inst 13877827 # number of overall (read+write) accesses 1760system.cpu1.icache.overall_accesses::total 13877827 # number of overall (read+write) accesses 1761system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.033445 # miss rate for ReadReq accesses 1762system.cpu1.icache.ReadReq_miss_rate::total 0.033445 # miss rate for ReadReq accesses 1763system.cpu1.icache.demand_miss_rate::cpu1.inst 0.033445 # miss rate for demand accesses 1764system.cpu1.icache.demand_miss_rate::total 0.033445 # miss rate for demand accesses 1765system.cpu1.icache.overall_miss_rate::cpu1.inst 0.033445 # miss rate for overall accesses 1766system.cpu1.icache.overall_miss_rate::total 0.033445 # miss rate for overall accesses 1767system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9082.058955 # average ReadReq miss latency 1768system.cpu1.icache.ReadReq_avg_miss_latency::total 9082.058955 # average ReadReq miss latency 1769system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9082.058955 # average overall miss latency 1770system.cpu1.icache.demand_avg_miss_latency::total 9082.058955 # average overall miss latency 1771system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9082.058955 # average overall miss latency 1772system.cpu1.icache.overall_avg_miss_latency::total 9082.058955 # average overall miss latency 1773system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1774system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1775system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1776system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1777system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1778system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1779system.cpu1.icache.fast_writes 0 # number of fast writes performed 1780system.cpu1.icache.cache_copies 0 # number of cache copies performed 1781system.cpu1.icache.writebacks::writebacks 463636 # number of writebacks 1782system.cpu1.icache.writebacks::total 463636 # number of writebacks 1783system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 464148 # number of ReadReq MSHR misses 1784system.cpu1.icache.ReadReq_mshr_misses::total 464148 # number of ReadReq MSHR misses 1785system.cpu1.icache.demand_mshr_misses::cpu1.inst 464148 # number of demand (read+write) MSHR misses 1786system.cpu1.icache.demand_mshr_misses::total 464148 # number of demand (read+write) MSHR misses 1787system.cpu1.icache.overall_mshr_misses::cpu1.inst 464148 # number of overall MSHR misses 1788system.cpu1.icache.overall_mshr_misses::total 464148 # number of overall MSHR misses 1789system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable 1790system.cpu1.icache.ReadReq_mshr_uncacheable::total 177 # number of ReadReq MSHR uncacheable 1791system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses 1792system.cpu1.icache.overall_mshr_uncacheable_misses::total 177 # number of overall MSHR uncacheable misses 1793system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3983345500 # number of ReadReq MSHR miss cycles 1794system.cpu1.icache.ReadReq_mshr_miss_latency::total 3983345500 # number of ReadReq MSHR miss cycles 1795system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3983345500 # number of demand (read+write) MSHR miss cycles 1796system.cpu1.icache.demand_mshr_miss_latency::total 3983345500 # number of demand (read+write) MSHR miss cycles 1797system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3983345500 # number of overall MSHR miss cycles 1798system.cpu1.icache.overall_mshr_miss_latency::total 3983345500 # number of overall MSHR miss cycles 1799system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 23546500 # number of ReadReq MSHR uncacheable cycles 1800system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 23546500 # number of ReadReq MSHR uncacheable cycles 1801system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 23546500 # number of overall MSHR uncacheable cycles 1802system.cpu1.icache.overall_mshr_uncacheable_latency::total 23546500 # number of overall MSHR uncacheable cycles 1803system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.033445 # mshr miss rate for ReadReq accesses 1804system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.033445 # mshr miss rate for ReadReq accesses 1805system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.033445 # mshr miss rate for demand accesses 1806system.cpu1.icache.demand_mshr_miss_rate::total 0.033445 # mshr miss rate for demand accesses 1807system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.033445 # mshr miss rate for overall accesses 1808system.cpu1.icache.overall_mshr_miss_rate::total 0.033445 # mshr miss rate for overall accesses 1809system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8582.058955 # average ReadReq mshr miss latency 1810system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8582.058955 # average ReadReq mshr miss latency 1811system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8582.058955 # average overall mshr miss latency 1812system.cpu1.icache.demand_avg_mshr_miss_latency::total 8582.058955 # average overall mshr miss latency 1813system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8582.058955 # average overall mshr miss latency 1814system.cpu1.icache.overall_avg_mshr_miss_latency::total 8582.058955 # average overall mshr miss latency 1815system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 133031.073446 # average ReadReq mshr uncacheable latency 1816system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 133031.073446 # average ReadReq mshr uncacheable latency 1817system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 133031.073446 # average overall mshr uncacheable latency 1818system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 133031.073446 # average overall mshr uncacheable latency 1819system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1820system.cpu1.l2cache.prefetcher.num_hwpf_issued 118070 # number of hwpf issued 1821system.cpu1.l2cache.prefetcher.pfIdentified 118078 # number of prefetch candidates identified 1822system.cpu1.l2cache.prefetcher.pfBufferHit 7 # number of redundant prefetches already in prefetch queue 1823system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1824system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1825system.cpu1.l2cache.prefetcher.pfSpanPage 50218 # number of prefetches not generated due to page crossing 1826system.cpu1.l2cache.tags.replacements 30957 # number of replacements 1827system.cpu1.l2cache.tags.tagsinuse 14956.632857 # Cycle average of tags in use 1828system.cpu1.l2cache.tags.total_refs 1041724 # Total number of references to valid blocks. 1829system.cpu1.l2cache.tags.sampled_refs 46098 # Sample count of references to valid blocks. 1830system.cpu1.l2cache.tags.avg_refs 22.598030 # Average number of references to valid blocks. 1831system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1832system.cpu1.l2cache.tags.occ_blocks::writebacks 14500.509333 # Average occupied blocks per requestor 1833system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 1.321768 # Average occupied blocks per requestor 1834system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.084166 # Average occupied blocks per requestor 1835system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 452.717591 # Average occupied blocks per requestor 1836system.cpu1.l2cache.tags.occ_percent::writebacks 0.885041 # Average percentage of cache occupancy 1837system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000081 # Average percentage of cache occupancy 1838system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000127 # Average percentage of cache occupancy 1839system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.027632 # Average percentage of cache occupancy 1840system.cpu1.l2cache.tags.occ_percent::total 0.912880 # Average percentage of cache occupancy 1841system.cpu1.l2cache.tags.occ_task_id_blocks::1022 931 # Occupied blocks per task id 1842system.cpu1.l2cache.tags.occ_task_id_blocks::1023 37 # Occupied blocks per task id 1843system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14173 # Occupied blocks per task id 1844system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 2 # Occupied blocks per task id 1845system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 38 # Occupied blocks per task id 1846system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 891 # Occupied blocks per task id 1847system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id 1848system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 32 # Occupied blocks per task id 1849system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 396 # Occupied blocks per task id 1850system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1648 # Occupied blocks per task id 1851system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 12129 # Occupied blocks per task id 1852system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.056824 # Percentage of cache occupancy per task id 1853system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002258 # Percentage of cache occupancy per task id 1854system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.865051 # Percentage of cache occupancy per task id 1855system.cpu1.l2cache.tags.tag_accesses 21133576 # Number of tag accesses 1856system.cpu1.l2cache.tags.data_accesses 21133576 # Number of data accesses 1857system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 2455 # number of ReadReq hits 1858system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1470 # number of ReadReq hits 1859system.cpu1.l2cache.ReadReq_hits::total 3925 # number of ReadReq hits 1860system.cpu1.l2cache.WritebackDirty_hits::writebacks 91545 # number of WritebackDirty hits 1861system.cpu1.l2cache.WritebackDirty_hits::total 91545 # number of WritebackDirty hits 1862system.cpu1.l2cache.WritebackClean_hits::writebacks 509576 # number of WritebackClean hits 1863system.cpu1.l2cache.WritebackClean_hits::total 509576 # number of WritebackClean hits 1864system.cpu1.l2cache.ReadExReq_hits::cpu1.data 18096 # number of ReadExReq hits 1865system.cpu1.l2cache.ReadExReq_hits::total 18096 # number of ReadExReq hits 1866system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 455478 # number of ReadCleanReq hits 1867system.cpu1.l2cache.ReadCleanReq_hits::total 455478 # number of ReadCleanReq hits 1868system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 77072 # number of ReadSharedReq hits 1869system.cpu1.l2cache.ReadSharedReq_hits::total 77072 # number of ReadSharedReq hits 1870system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 2455 # number of demand (read+write) hits 1871system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1470 # number of demand (read+write) hits 1872system.cpu1.l2cache.demand_hits::cpu1.inst 455478 # number of demand (read+write) hits 1873system.cpu1.l2cache.demand_hits::cpu1.data 95168 # number of demand (read+write) hits 1874system.cpu1.l2cache.demand_hits::total 554571 # number of demand (read+write) hits 1875system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 2455 # number of overall hits 1876system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1470 # number of overall hits 1877system.cpu1.l2cache.overall_hits::cpu1.inst 455478 # number of overall hits 1878system.cpu1.l2cache.overall_hits::cpu1.data 95168 # number of overall hits 1879system.cpu1.l2cache.overall_hits::total 554571 # number of overall hits 1880system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 345 # number of ReadReq misses 1881system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 297 # number of ReadReq misses 1882system.cpu1.l2cache.ReadReq_misses::total 642 # number of ReadReq misses 1883system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28981 # number of UpgradeReq misses 1884system.cpu1.l2cache.UpgradeReq_misses::total 28981 # number of UpgradeReq misses 1885system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23084 # number of SCUpgradeReq misses 1886system.cpu1.l2cache.SCUpgradeReq_misses::total 23084 # number of SCUpgradeReq misses 1887system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 1 # number of SCUpgradeFailReq misses 1888system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses 1889system.cpu1.l2cache.ReadExReq_misses::cpu1.data 32217 # number of ReadExReq misses 1890system.cpu1.l2cache.ReadExReq_misses::total 32217 # number of ReadExReq misses 1891system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 8670 # number of ReadCleanReq misses 1892system.cpu1.l2cache.ReadCleanReq_misses::total 8670 # number of ReadCleanReq misses 1893system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 63803 # number of ReadSharedReq misses 1894system.cpu1.l2cache.ReadSharedReq_misses::total 63803 # number of ReadSharedReq misses 1895system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 345 # number of demand (read+write) misses 1896system.cpu1.l2cache.demand_misses::cpu1.itb.walker 297 # number of demand (read+write) misses 1897system.cpu1.l2cache.demand_misses::cpu1.inst 8670 # number of demand (read+write) misses 1898system.cpu1.l2cache.demand_misses::cpu1.data 96020 # number of demand (read+write) misses 1899system.cpu1.l2cache.demand_misses::total 105332 # number of demand (read+write) misses 1900system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 345 # number of overall misses 1901system.cpu1.l2cache.overall_misses::cpu1.itb.walker 297 # number of overall misses 1902system.cpu1.l2cache.overall_misses::cpu1.inst 8670 # number of overall misses 1903system.cpu1.l2cache.overall_misses::cpu1.data 96020 # number of overall misses 1904system.cpu1.l2cache.overall_misses::total 105332 # number of overall misses 1905system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 7035000 # number of ReadReq miss cycles 1906system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5940500 # number of ReadReq miss cycles 1907system.cpu1.l2cache.ReadReq_miss_latency::total 12975500 # number of ReadReq miss cycles 1908system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 66105500 # number of UpgradeReq miss cycles 1909system.cpu1.l2cache.UpgradeReq_miss_latency::total 66105500 # number of UpgradeReq miss cycles 1910system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 54747500 # number of SCUpgradeReq miss cycles 1911system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 54747500 # number of SCUpgradeReq miss cycles 1912system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 3677500 # number of SCUpgradeFailReq miss cycles 1913system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 3677500 # number of SCUpgradeFailReq miss cycles 1914system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1649546500 # number of ReadExReq miss cycles 1915system.cpu1.l2cache.ReadExReq_miss_latency::total 1649546500 # number of ReadExReq miss cycles 1916system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 528187000 # number of ReadCleanReq miss cycles 1917system.cpu1.l2cache.ReadCleanReq_miss_latency::total 528187000 # number of ReadCleanReq miss cycles 1918system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1437865000 # number of ReadSharedReq miss cycles 1919system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1437865000 # number of ReadSharedReq miss cycles 1920system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 7035000 # number of demand (read+write) miss cycles 1921system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5940500 # number of demand (read+write) miss cycles 1922system.cpu1.l2cache.demand_miss_latency::cpu1.inst 528187000 # number of demand (read+write) miss cycles 1923system.cpu1.l2cache.demand_miss_latency::cpu1.data 3087411500 # number of demand (read+write) miss cycles 1924system.cpu1.l2cache.demand_miss_latency::total 3628574000 # number of demand (read+write) miss cycles 1925system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 7035000 # number of overall miss cycles 1926system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5940500 # number of overall miss cycles 1927system.cpu1.l2cache.overall_miss_latency::cpu1.inst 528187000 # number of overall miss cycles 1928system.cpu1.l2cache.overall_miss_latency::cpu1.data 3087411500 # number of overall miss cycles 1929system.cpu1.l2cache.overall_miss_latency::total 3628574000 # number of overall miss cycles 1930system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 2800 # number of ReadReq accesses(hits+misses) 1931system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1767 # number of ReadReq accesses(hits+misses) 1932system.cpu1.l2cache.ReadReq_accesses::total 4567 # number of ReadReq accesses(hits+misses) 1933system.cpu1.l2cache.WritebackDirty_accesses::writebacks 91545 # number of WritebackDirty accesses(hits+misses) 1934system.cpu1.l2cache.WritebackDirty_accesses::total 91545 # number of WritebackDirty accesses(hits+misses) 1935system.cpu1.l2cache.WritebackClean_accesses::writebacks 509576 # number of WritebackClean accesses(hits+misses) 1936system.cpu1.l2cache.WritebackClean_accesses::total 509576 # number of WritebackClean accesses(hits+misses) 1937system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28981 # number of UpgradeReq accesses(hits+misses) 1938system.cpu1.l2cache.UpgradeReq_accesses::total 28981 # number of UpgradeReq accesses(hits+misses) 1939system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23084 # number of SCUpgradeReq accesses(hits+misses) 1940system.cpu1.l2cache.SCUpgradeReq_accesses::total 23084 # number of SCUpgradeReq accesses(hits+misses) 1941system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 1 # number of SCUpgradeFailReq accesses(hits+misses) 1942system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) 1943system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 50313 # number of ReadExReq accesses(hits+misses) 1944system.cpu1.l2cache.ReadExReq_accesses::total 50313 # number of ReadExReq accesses(hits+misses) 1945system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 464148 # number of ReadCleanReq accesses(hits+misses) 1946system.cpu1.l2cache.ReadCleanReq_accesses::total 464148 # number of ReadCleanReq accesses(hits+misses) 1947system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 140875 # number of ReadSharedReq accesses(hits+misses) 1948system.cpu1.l2cache.ReadSharedReq_accesses::total 140875 # number of ReadSharedReq accesses(hits+misses) 1949system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 2800 # number of demand (read+write) accesses 1950system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 1767 # number of demand (read+write) accesses 1951system.cpu1.l2cache.demand_accesses::cpu1.inst 464148 # number of demand (read+write) accesses 1952system.cpu1.l2cache.demand_accesses::cpu1.data 191188 # number of demand (read+write) accesses 1953system.cpu1.l2cache.demand_accesses::total 659903 # number of demand (read+write) accesses 1954system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 2800 # number of overall (read+write) accesses 1955system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 1767 # number of overall (read+write) accesses 1956system.cpu1.l2cache.overall_accesses::cpu1.inst 464148 # number of overall (read+write) accesses 1957system.cpu1.l2cache.overall_accesses::cpu1.data 191188 # number of overall (read+write) accesses 1958system.cpu1.l2cache.overall_accesses::total 659903 # number of overall (read+write) accesses 1959system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.123214 # miss rate for ReadReq accesses 1960system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.168081 # miss rate for ReadReq accesses 1961system.cpu1.l2cache.ReadReq_miss_rate::total 0.140574 # miss rate for ReadReq accesses 1962system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 1963system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 1964system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 1965system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1966system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 1967system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1968system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.640332 # miss rate for ReadExReq accesses 1969system.cpu1.l2cache.ReadExReq_miss_rate::total 0.640332 # miss rate for ReadExReq accesses 1970system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.018679 # miss rate for ReadCleanReq accesses 1971system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.018679 # miss rate for ReadCleanReq accesses 1972system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.452905 # miss rate for ReadSharedReq accesses 1973system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.452905 # miss rate for ReadSharedReq accesses 1974system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.123214 # miss rate for demand accesses 1975system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.168081 # miss rate for demand accesses 1976system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.018679 # miss rate for demand accesses 1977system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.502228 # miss rate for demand accesses 1978system.cpu1.l2cache.demand_miss_rate::total 0.159617 # miss rate for demand accesses 1979system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.123214 # miss rate for overall accesses 1980system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.168081 # miss rate for overall accesses 1981system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.018679 # miss rate for overall accesses 1982system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.502228 # miss rate for overall accesses 1983system.cpu1.l2cache.overall_miss_rate::total 0.159617 # miss rate for overall accesses 1984system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20391.304348 # average ReadReq miss latency 1985system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20001.683502 # average ReadReq miss latency 1986system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20211.059190 # average ReadReq miss latency 1987system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 2280.994445 # average UpgradeReq miss latency 1988system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 2280.994445 # average UpgradeReq miss latency 1989system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 2371.664356 # average SCUpgradeReq miss latency 1990system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 2371.664356 # average SCUpgradeReq miss latency 1991system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 3677500 # average SCUpgradeFailReq miss latency 1992system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 3677500 # average SCUpgradeFailReq miss latency 1993system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 51201.120526 # average ReadExReq miss latency 1994system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 51201.120526 # average ReadExReq miss latency 1995system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 60921.222607 # average ReadCleanReq miss latency 1996system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 60921.222607 # average ReadCleanReq miss latency 1997system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22536.009279 # average ReadSharedReq miss latency 1998system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22536.009279 # average ReadSharedReq miss latency 1999system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20391.304348 # average overall miss latency 2000system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20001.683502 # average overall miss latency 2001system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 60921.222607 # average overall miss latency 2002system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 32153.837742 # average overall miss latency 2003system.cpu1.l2cache.demand_avg_miss_latency::total 34448.923404 # average overall miss latency 2004system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20391.304348 # average overall miss latency 2005system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20001.683502 # average overall miss latency 2006system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 60921.222607 # average overall miss latency 2007system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 32153.837742 # average overall miss latency 2008system.cpu1.l2cache.overall_avg_miss_latency::total 34448.923404 # average overall miss latency 2009system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2010system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2011system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 2012system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2013system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2014system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2015system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 2016system.cpu1.l2cache.cache_copies 0 # number of cache copies performed 2017system.cpu1.l2cache.writebacks::writebacks 25761 # number of writebacks 2018system.cpu1.l2cache.writebacks::total 25761 # number of writebacks 2019system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 70 # number of ReadExReq MSHR hits 2020system.cpu1.l2cache.ReadExReq_mshr_hits::total 70 # number of ReadExReq MSHR hits 2021system.cpu1.l2cache.demand_mshr_hits::cpu1.data 70 # number of demand (read+write) MSHR hits 2022system.cpu1.l2cache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits 2023system.cpu1.l2cache.overall_mshr_hits::cpu1.data 70 # number of overall MSHR hits 2024system.cpu1.l2cache.overall_mshr_hits::total 70 # number of overall MSHR hits 2025system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 345 # number of ReadReq MSHR misses 2026system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 297 # number of ReadReq MSHR misses 2027system.cpu1.l2cache.ReadReq_mshr_misses::total 642 # number of ReadReq MSHR misses 2028system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 20837 # number of HardPFReq MSHR misses 2029system.cpu1.l2cache.HardPFReq_mshr_misses::total 20837 # number of HardPFReq MSHR misses 2030system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 28981 # number of UpgradeReq MSHR misses 2031system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28981 # number of UpgradeReq MSHR misses 2032system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23084 # number of SCUpgradeReq MSHR misses 2033system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23084 # number of SCUpgradeReq MSHR misses 2034system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 1 # number of SCUpgradeFailReq MSHR misses 2035system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses 2036system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 32147 # number of ReadExReq MSHR misses 2037system.cpu1.l2cache.ReadExReq_mshr_misses::total 32147 # number of ReadExReq MSHR misses 2038system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 8670 # number of ReadCleanReq MSHR misses 2039system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 8670 # number of ReadCleanReq MSHR misses 2040system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 63803 # number of ReadSharedReq MSHR misses 2041system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 63803 # number of ReadSharedReq MSHR misses 2042system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 345 # number of demand (read+write) MSHR misses 2043system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 297 # number of demand (read+write) MSHR misses 2044system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 8670 # number of demand (read+write) MSHR misses 2045system.cpu1.l2cache.demand_mshr_misses::cpu1.data 95950 # number of demand (read+write) MSHR misses 2046system.cpu1.l2cache.demand_mshr_misses::total 105262 # number of demand (read+write) MSHR misses 2047system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 345 # number of overall MSHR misses 2048system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 297 # number of overall MSHR misses 2049system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 8670 # number of overall MSHR misses 2050system.cpu1.l2cache.overall_mshr_misses::cpu1.data 95950 # number of overall MSHR misses 2051system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 20837 # number of overall MSHR misses 2052system.cpu1.l2cache.overall_mshr_misses::total 126099 # number of overall MSHR misses 2053system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable 2054system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 3081 # number of ReadReq MSHR uncacheable 2055system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 3258 # number of ReadReq MSHR uncacheable 2056system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2423 # number of WriteReq MSHR uncacheable 2057system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2423 # number of WriteReq MSHR uncacheable 2058system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses 2059system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5504 # number of overall MSHR uncacheable misses 2060system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5681 # number of overall MSHR uncacheable misses 2061system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4965000 # number of ReadReq MSHR miss cycles 2062system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 4158500 # number of ReadReq MSHR miss cycles 2063system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 9123500 # number of ReadReq MSHR miss cycles 2064system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 915724625 # number of HardPFReq MSHR miss cycles 2065system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 915724625 # number of HardPFReq MSHR miss cycles 2066system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 582445000 # number of UpgradeReq MSHR miss cycles 2067system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 582445000 # number of UpgradeReq MSHR miss cycles 2068system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 432971000 # number of SCUpgradeReq MSHR miss cycles 2069system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 432971000 # number of SCUpgradeReq MSHR miss cycles 2070system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 3473500 # number of SCUpgradeFailReq MSHR miss cycles 2071system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 3473500 # number of SCUpgradeFailReq MSHR miss cycles 2072system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1449025500 # number of ReadExReq MSHR miss cycles 2073system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1449025500 # number of ReadExReq MSHR miss cycles 2074system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 476167000 # number of ReadCleanReq MSHR miss cycles 2075system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 476167000 # number of ReadCleanReq MSHR miss cycles 2076system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1055047000 # number of ReadSharedReq MSHR miss cycles 2077system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1055047000 # number of ReadSharedReq MSHR miss cycles 2078system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 4965000 # number of demand (read+write) MSHR miss cycles 2079system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4158500 # number of demand (read+write) MSHR miss cycles 2080system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 476167000 # number of demand (read+write) MSHR miss cycles 2081system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2504072500 # number of demand (read+write) MSHR miss cycles 2082system.cpu1.l2cache.demand_mshr_miss_latency::total 2989363000 # number of demand (read+write) MSHR miss cycles 2083system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 4965000 # number of overall MSHR miss cycles 2084system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4158500 # number of overall MSHR miss cycles 2085system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 476167000 # number of overall MSHR miss cycles 2086system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2504072500 # number of overall MSHR miss cycles 2087system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 915724625 # number of overall MSHR miss cycles 2088system.cpu1.l2cache.overall_mshr_miss_latency::total 3905087625 # number of overall MSHR miss cycles 2089system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 22219000 # number of ReadReq MSHR uncacheable cycles 2090system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 414452000 # number of ReadReq MSHR uncacheable cycles 2091system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 436671000 # number of ReadReq MSHR uncacheable cycles 2092system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 284931500 # number of WriteReq MSHR uncacheable cycles 2093system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 284931500 # number of WriteReq MSHR uncacheable cycles 2094system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 22219000 # number of overall MSHR uncacheable cycles 2095system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 699383500 # number of overall MSHR uncacheable cycles 2096system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 721602500 # number of overall MSHR uncacheable cycles 2097system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.123214 # mshr miss rate for ReadReq accesses 2098system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.168081 # mshr miss rate for ReadReq accesses 2099system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.140574 # mshr miss rate for ReadReq accesses 2100system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2101system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2102system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 2103system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 2104system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses 2105system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 2106system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2107system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 2108system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.638940 # mshr miss rate for ReadExReq accesses 2109system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.638940 # mshr miss rate for ReadExReq accesses 2110system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.018679 # mshr miss rate for ReadCleanReq accesses 2111system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.018679 # mshr miss rate for ReadCleanReq accesses 2112system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.452905 # mshr miss rate for ReadSharedReq accesses 2113system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.452905 # mshr miss rate for ReadSharedReq accesses 2114system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.123214 # mshr miss rate for demand accesses 2115system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.168081 # mshr miss rate for demand accesses 2116system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.018679 # mshr miss rate for demand accesses 2117system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.501862 # mshr miss rate for demand accesses 2118system.cpu1.l2cache.demand_mshr_miss_rate::total 0.159511 # mshr miss rate for demand accesses 2119system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.123214 # mshr miss rate for overall accesses 2120system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.168081 # mshr miss rate for overall accesses 2121system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.018679 # mshr miss rate for overall accesses 2122system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.501862 # mshr miss rate for overall accesses 2123system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2124system.cpu1.l2cache.overall_mshr_miss_rate::total 0.191087 # mshr miss rate for overall accesses 2125system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14391.304348 # average ReadReq mshr miss latency 2126system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14001.683502 # average ReadReq mshr miss latency 2127system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14211.059190 # average ReadReq mshr miss latency 2128system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43947.047320 # average HardPFReq mshr miss latency 2129system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 43947.047320 # average HardPFReq mshr miss latency 2130system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20097.477658 # average UpgradeReq mshr miss latency 2131system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20097.477658 # average UpgradeReq mshr miss latency 2132system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18756.324727 # average SCUpgradeReq mshr miss latency 2133system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18756.324727 # average SCUpgradeReq mshr miss latency 2134system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 3473500 # average SCUpgradeFailReq mshr miss latency 2135system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 3473500 # average SCUpgradeFailReq mshr miss latency 2136system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 45074.983669 # average ReadExReq mshr miss latency 2137system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 45074.983669 # average ReadExReq mshr miss latency 2138system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 54921.222607 # average ReadCleanReq mshr miss latency 2139system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 54921.222607 # average ReadCleanReq mshr miss latency 2140system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16536.009279 # average ReadSharedReq mshr miss latency 2141system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16536.009279 # average ReadSharedReq mshr miss latency 2142system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14391.304348 # average overall mshr miss latency 2143system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14001.683502 # average overall mshr miss latency 2144system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 54921.222607 # average overall mshr miss latency 2145system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 26097.681084 # average overall mshr miss latency 2146system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 28399.260892 # average overall mshr miss latency 2147system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14391.304348 # average overall mshr miss latency 2148system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14001.683502 # average overall mshr miss latency 2149system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 54921.222607 # average overall mshr miss latency 2150system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 26097.681084 # average overall mshr miss latency 2151system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43947.047320 # average overall mshr miss latency 2152system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 30968.426593 # average overall mshr miss latency 2153system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 125531.073446 # average ReadReq mshr uncacheable latency 2154system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 134518.662772 # average ReadReq mshr uncacheable latency 2155system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 134030.386740 # average ReadReq mshr uncacheable latency 2156system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117594.510937 # average WriteReq mshr uncacheable latency 2157system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 117594.510937 # average WriteReq mshr uncacheable latency 2158system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 125531.073446 # average overall mshr uncacheable latency 2159system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 127068.223110 # average overall mshr uncacheable latency 2160system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 127020.330928 # average overall mshr uncacheable latency 2161system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 2162system.cpu1.toL2Bus.snoop_filter.tot_requests 1323663 # Total number of requests made to the snoop filter. 2163system.cpu1.toL2Bus.snoop_filter.hit_single_requests 668360 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2164system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 10107 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2165system.cpu1.toL2Bus.snoop_filter.tot_snoops 169443 # Total number of snoops made to the snoop filter. 2166system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 166760 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2167system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2683 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2168system.cpu1.toL2Bus.trans_dist::ReadReq 10105 # Transaction distribution 2169system.cpu1.toL2Bus.trans_dist::ReadResp 652363 # Transaction distribution 2170system.cpu1.toL2Bus.trans_dist::WriteReq 2423 # Transaction distribution 2171system.cpu1.toL2Bus.trans_dist::WriteResp 2423 # Transaction distribution 2172system.cpu1.toL2Bus.trans_dist::WritebackDirty 118404 # Transaction distribution 2173system.cpu1.toL2Bus.trans_dist::WritebackClean 509576 # Transaction distribution 2174system.cpu1.toL2Bus.trans_dist::CleanEvict 86260 # Transaction distribution 2175system.cpu1.toL2Bus.trans_dist::HardPFReq 25020 # Transaction distribution 2176system.cpu1.toL2Bus.trans_dist::UpgradeReq 70278 # Transaction distribution 2177system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 40907 # Transaction distribution 2178system.cpu1.toL2Bus.trans_dist::UpgradeResp 84739 # Transaction distribution 2179system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 51 # Transaction distribution 2180system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 84 # Transaction distribution 2181system.cpu1.toL2Bus.trans_dist::ReadExReq 57602 # Transaction distribution 2182system.cpu1.toL2Bus.trans_dist::ReadExResp 55059 # Transaction distribution 2183system.cpu1.toL2Bus.trans_dist::ReadCleanReq 464148 # Transaction distribution 2184system.cpu1.toL2Bus.trans_dist::ReadSharedReq 215012 # Transaction distribution 2185system.cpu1.toL2Bus.trans_dist::InvalidateReq 32 # Transaction distribution 2186system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1383984 # Packet count per connected master and slave (bytes) 2187system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 718041 # Packet count per connected master and slave (bytes) 2188system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 4385 # Packet count per connected master and slave (bytes) 2189system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 7029 # Packet count per connected master and slave (bytes) 2190system.cpu1.toL2Bus.pkt_count::total 2113439 # Packet count per connected master and slave (bytes) 2191system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 58847556 # Cumulative packet size per connected master and slave (bytes) 2192system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24276952 # Cumulative packet size per connected master and slave (bytes) 2193system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7068 # Cumulative packet size per connected master and slave (bytes) 2194system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 11200 # Cumulative packet size per connected master and slave (bytes) 2195system.cpu1.toL2Bus.pkt_size::total 83142776 # Cumulative packet size per connected master and slave (bytes) 2196system.cpu1.toL2Bus.snoops 355785 # Total snoops (count) 2197system.cpu1.toL2Bus.snoop_fanout::samples 998697 # Request fanout histogram 2198system.cpu1.toL2Bus.snoop_fanout::mean 0.187513 # Request fanout histogram 2199system.cpu1.toL2Bus.snoop_fanout::stdev 0.397146 # Request fanout histogram 2200system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2201system.cpu1.toL2Bus.snoop_fanout::0 814111 81.52% 81.52% # Request fanout histogram 2202system.cpu1.toL2Bus.snoop_fanout::1 181903 18.21% 99.73% # Request fanout histogram 2203system.cpu1.toL2Bus.snoop_fanout::2 2683 0.27% 100.00% # Request fanout histogram 2204system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2205system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2206system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2207system.cpu1.toL2Bus.snoop_fanout::total 998697 # Request fanout histogram 2208system.cpu1.toL2Bus.reqLayer0.occupancy 1278018500 # Layer occupancy (ticks) 2209system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 2210system.cpu1.toL2Bus.snoopLayer0.occupancy 79432929 # Layer occupancy (ticks) 2211system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2212system.cpu1.toL2Bus.respLayer0.occupancy 696399000 # Layer occupancy (ticks) 2213system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2214system.cpu1.toL2Bus.respLayer1.occupancy 317143500 # Layer occupancy (ticks) 2215system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2216system.cpu1.toL2Bus.respLayer2.occupancy 2618000 # Layer occupancy (ticks) 2217system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2218system.cpu1.toL2Bus.respLayer3.occupancy 4229000 # Layer occupancy (ticks) 2219system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2220system.iobus.trans_dist::ReadReq 31021 # Transaction distribution 2221system.iobus.trans_dist::ReadResp 31021 # Transaction distribution 2222system.iobus.trans_dist::WriteReq 59425 # Transaction distribution 2223system.iobus.trans_dist::WriteResp 59425 # Transaction distribution 2224system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56620 # Packet count per connected master and slave (bytes) 2225system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 2226system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 2227system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 2228system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 2229system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 2230system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 2231system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2232system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2233system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2234system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 2235system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 2236system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 2237system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 2238system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 2239system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 2240system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 2241system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 2242system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 2243system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 2244system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 2245system.iobus.pkt_count_system.bridge.master::total 107934 # Packet count per connected master and slave (bytes) 2246system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes) 2247system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes) 2248system.iobus.pkt_count::total 180892 # Packet count per connected master and slave (bytes) 2249system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71564 # Cumulative packet size per connected master and slave (bytes) 2250system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 2251system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 2252system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 2253system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 2254system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 2255system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 2256system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2257system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2258system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2259system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 2260system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2261system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2262system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 2263system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 2264system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2265system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 2266system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 2267system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 2268system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 2269system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 2270system.iobus.pkt_size_system.bridge.master::total 162814 # Cumulative packet size per connected master and slave (bytes) 2271system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes) 2272system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes) 2273system.iobus.pkt_size::total 2484086 # Cumulative packet size per connected master and slave (bytes) 2274system.iobus.reqLayer0.occupancy 48741500 # Layer occupancy (ticks) 2275system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2276system.iobus.reqLayer1.occupancy 106500 # Layer occupancy (ticks) 2277system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2278system.iobus.reqLayer2.occupancy 32500 # Layer occupancy (ticks) 2279system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2280system.iobus.reqLayer3.occupancy 16000 # Layer occupancy (ticks) 2281system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2282system.iobus.reqLayer6.occupancy 93000 # Layer occupancy (ticks) 2283system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 2284system.iobus.reqLayer7.occupancy 609500 # Layer occupancy (ticks) 2285system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 2286system.iobus.reqLayer10.occupancy 23500 # Layer occupancy (ticks) 2287system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2288system.iobus.reqLayer13.occupancy 12000 # Layer occupancy (ticks) 2289system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2290system.iobus.reqLayer14.occupancy 11500 # Layer occupancy (ticks) 2291system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2292system.iobus.reqLayer15.occupancy 11500 # Layer occupancy (ticks) 2293system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 2294system.iobus.reqLayer16.occupancy 48500 # Layer occupancy (ticks) 2295system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2296system.iobus.reqLayer17.occupancy 11500 # Layer occupancy (ticks) 2297system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 2298system.iobus.reqLayer18.occupancy 11500 # Layer occupancy (ticks) 2299system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 2300system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) 2301system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 2302system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) 2303system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 2304system.iobus.reqLayer21.occupancy 12000 # Layer occupancy (ticks) 2305system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 2306system.iobus.reqLayer23.occupancy 6155500 # Layer occupancy (ticks) 2307system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2308system.iobus.reqLayer24.occupancy 165000 # Layer occupancy (ticks) 2309system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2310system.iobus.reqLayer25.occupancy 32044000 # Layer occupancy (ticks) 2311system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2312system.iobus.reqLayer26.occupancy 119500 # Layer occupancy (ticks) 2313system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 2314system.iobus.reqLayer27.occupancy 186329030 # Layer occupancy (ticks) 2315system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 2316system.iobus.reqLayer28.occupancy 37500 # Layer occupancy (ticks) 2317system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 2318system.iobus.respLayer0.occupancy 84733000 # Layer occupancy (ticks) 2319system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2320system.iobus.respLayer3.occupancy 36782000 # Layer occupancy (ticks) 2321system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2322system.iocache.tags.replacements 36461 # number of replacements 2323system.iocache.tags.tagsinuse 14.380003 # Cycle average of tags in use 2324system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 2325system.iocache.tags.sampled_refs 36477 # Sample count of references to valid blocks. 2326system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 2327system.iocache.tags.warmup_cycle 290757542000 # Cycle when the warmup percentage was hit. 2328system.iocache.tags.occ_blocks::realview.ide 14.380003 # Average occupied blocks per requestor 2329system.iocache.tags.occ_percent::realview.ide 0.898750 # Average percentage of cache occupancy 2330system.iocache.tags.occ_percent::total 0.898750 # Average percentage of cache occupancy 2331system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2332system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2333system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2334system.iocache.tags.tag_accesses 328311 # Number of tag accesses 2335system.iocache.tags.data_accesses 328311 # Number of data accesses 2336system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses 2337system.iocache.ReadReq_misses::total 255 # number of ReadReq misses 2338system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 2339system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 2340system.iocache.demand_misses::realview.ide 255 # number of demand (read+write) misses 2341system.iocache.demand_misses::total 255 # number of demand (read+write) misses 2342system.iocache.overall_misses::realview.ide 255 # number of overall misses 2343system.iocache.overall_misses::total 255 # number of overall misses 2344system.iocache.ReadReq_miss_latency::realview.ide 32882376 # number of ReadReq miss cycles 2345system.iocache.ReadReq_miss_latency::total 32882376 # number of ReadReq miss cycles 2346system.iocache.WriteLineReq_miss_latency::realview.ide 4738851654 # number of WriteLineReq miss cycles 2347system.iocache.WriteLineReq_miss_latency::total 4738851654 # number of WriteLineReq miss cycles 2348system.iocache.demand_miss_latency::realview.ide 32882376 # number of demand (read+write) miss cycles 2349system.iocache.demand_miss_latency::total 32882376 # number of demand (read+write) miss cycles 2350system.iocache.overall_miss_latency::realview.ide 32882376 # number of overall miss cycles 2351system.iocache.overall_miss_latency::total 32882376 # number of overall miss cycles 2352system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) 2353system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) 2354system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 2355system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) 2356system.iocache.demand_accesses::realview.ide 255 # number of demand (read+write) accesses 2357system.iocache.demand_accesses::total 255 # number of demand (read+write) accesses 2358system.iocache.overall_accesses::realview.ide 255 # number of overall (read+write) accesses 2359system.iocache.overall_accesses::total 255 # number of overall (read+write) accesses 2360system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2361system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2362system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 2363system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 2364system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2365system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2366system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2367system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2368system.iocache.ReadReq_avg_miss_latency::realview.ide 128950.494118 # average ReadReq miss latency 2369system.iocache.ReadReq_avg_miss_latency::total 128950.494118 # average ReadReq miss latency 2370system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130820.772250 # average WriteLineReq miss latency 2371system.iocache.WriteLineReq_avg_miss_latency::total 130820.772250 # average WriteLineReq miss latency 2372system.iocache.demand_avg_miss_latency::realview.ide 128950.494118 # average overall miss latency 2373system.iocache.demand_avg_miss_latency::total 128950.494118 # average overall miss latency 2374system.iocache.overall_avg_miss_latency::realview.ide 128950.494118 # average overall miss latency 2375system.iocache.overall_avg_miss_latency::total 128950.494118 # average overall miss latency 2376system.iocache.blocked_cycles::no_mshrs 818 # number of cycles access was blocked 2377system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2378system.iocache.blocked::no_mshrs 99 # number of cycles access was blocked 2379system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2380system.iocache.avg_blocked_cycles::no_mshrs 8.262626 # average number of cycles each access was blocked 2381system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2382system.iocache.fast_writes 0 # number of fast writes performed 2383system.iocache.cache_copies 0 # number of cache copies performed 2384system.iocache.writebacks::writebacks 36206 # number of writebacks 2385system.iocache.writebacks::total 36206 # number of writebacks 2386system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses 2387system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses 2388system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses 2389system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses 2390system.iocache.demand_mshr_misses::realview.ide 255 # number of demand (read+write) MSHR misses 2391system.iocache.demand_mshr_misses::total 255 # number of demand (read+write) MSHR misses 2392system.iocache.overall_mshr_misses::realview.ide 255 # number of overall MSHR misses 2393system.iocache.overall_mshr_misses::total 255 # number of overall MSHR misses 2394system.iocache.ReadReq_mshr_miss_latency::realview.ide 20132376 # number of ReadReq MSHR miss cycles 2395system.iocache.ReadReq_mshr_miss_latency::total 20132376 # number of ReadReq MSHR miss cycles 2396system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2927651654 # number of WriteLineReq MSHR miss cycles 2397system.iocache.WriteLineReq_mshr_miss_latency::total 2927651654 # number of WriteLineReq MSHR miss cycles 2398system.iocache.demand_mshr_miss_latency::realview.ide 20132376 # number of demand (read+write) MSHR miss cycles 2399system.iocache.demand_mshr_miss_latency::total 20132376 # number of demand (read+write) MSHR miss cycles 2400system.iocache.overall_mshr_miss_latency::realview.ide 20132376 # number of overall MSHR miss cycles 2401system.iocache.overall_mshr_miss_latency::total 20132376 # number of overall MSHR miss cycles 2402system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2403system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2404system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 2405system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 2406system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2407system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2408system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2409system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 2410system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 78950.494118 # average ReadReq mshr miss latency 2411system.iocache.ReadReq_avg_mshr_miss_latency::total 78950.494118 # average ReadReq mshr miss latency 2412system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80820.772250 # average WriteLineReq mshr miss latency 2413system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80820.772250 # average WriteLineReq mshr miss latency 2414system.iocache.demand_avg_mshr_miss_latency::realview.ide 78950.494118 # average overall mshr miss latency 2415system.iocache.demand_avg_mshr_miss_latency::total 78950.494118 # average overall mshr miss latency 2416system.iocache.overall_avg_mshr_miss_latency::realview.ide 78950.494118 # average overall mshr miss latency 2417system.iocache.overall_avg_mshr_miss_latency::total 78950.494118 # average overall mshr miss latency 2418system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2419system.l2c.tags.replacements 123906 # number of replacements 2420system.l2c.tags.tagsinuse 62994.829806 # Cycle average of tags in use 2421system.l2c.tags.total_refs 421817 # Total number of references to valid blocks. 2422system.l2c.tags.sampled_refs 187980 # Sample count of references to valid blocks. 2423system.l2c.tags.avg_refs 2.243946 # Average number of references to valid blocks. 2424system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2425system.l2c.tags.occ_blocks::writebacks 13459.681359 # Average occupied blocks per requestor 2426system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.946988 # Average occupied blocks per requestor 2427system.l2c.tags.occ_blocks::cpu0.itb.walker 0.042686 # Average occupied blocks per requestor 2428system.l2c.tags.occ_blocks::cpu0.inst 7381.464495 # Average occupied blocks per requestor 2429system.l2c.tags.occ_blocks::cpu0.data 2783.395152 # Average occupied blocks per requestor 2430system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 35774.545550 # Average occupied blocks per requestor 2431system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.954481 # Average occupied blocks per requestor 2432system.l2c.tags.occ_blocks::cpu1.inst 1451.828957 # Average occupied blocks per requestor 2433system.l2c.tags.occ_blocks::cpu1.data 405.858901 # Average occupied blocks per requestor 2434system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1734.111238 # Average occupied blocks per requestor 2435system.l2c.tags.occ_percent::writebacks 0.205378 # Average percentage of cache occupancy 2436system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000045 # Average percentage of cache occupancy 2437system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy 2438system.l2c.tags.occ_percent::cpu0.inst 0.112632 # Average percentage of cache occupancy 2439system.l2c.tags.occ_percent::cpu0.data 0.042471 # Average percentage of cache occupancy 2440system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.545876 # Average percentage of cache occupancy 2441system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy 2442system.l2c.tags.occ_percent::cpu1.inst 0.022153 # Average percentage of cache occupancy 2443system.l2c.tags.occ_percent::cpu1.data 0.006193 # Average percentage of cache occupancy 2444system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.026460 # Average percentage of cache occupancy 2445system.l2c.tags.occ_percent::total 0.961225 # Average percentage of cache occupancy 2446system.l2c.tags.occ_task_id_blocks::1022 31889 # Occupied blocks per task id 2447system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id 2448system.l2c.tags.occ_task_id_blocks::1024 32181 # Occupied blocks per task id 2449system.l2c.tags.age_task_id_blocks_1022::1 4 # Occupied blocks per task id 2450system.l2c.tags.age_task_id_blocks_1022::2 315 # Occupied blocks per task id 2451system.l2c.tags.age_task_id_blocks_1022::3 5132 # Occupied blocks per task id 2452system.l2c.tags.age_task_id_blocks_1022::4 26438 # Occupied blocks per task id 2453system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id 2454system.l2c.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id 2455system.l2c.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id 2456system.l2c.tags.age_task_id_blocks_1024::2 384 # Occupied blocks per task id 2457system.l2c.tags.age_task_id_blocks_1024::3 2392 # Occupied blocks per task id 2458system.l2c.tags.age_task_id_blocks_1024::4 29385 # Occupied blocks per task id 2459system.l2c.tags.occ_task_id_percent::1022 0.486588 # Percentage of cache occupancy per task id 2460system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id 2461system.l2c.tags.occ_task_id_percent::1024 0.491043 # Percentage of cache occupancy per task id 2462system.l2c.tags.tag_accesses 5837673 # Number of tag accesses 2463system.l2c.tags.data_accesses 5837673 # Number of data accesses 2464system.l2c.WritebackDirty_hits::writebacks 257503 # number of WritebackDirty hits 2465system.l2c.WritebackDirty_hits::total 257503 # number of WritebackDirty hits 2466system.l2c.UpgradeReq_hits::cpu0.data 32214 # number of UpgradeReq hits 2467system.l2c.UpgradeReq_hits::cpu1.data 1943 # number of UpgradeReq hits 2468system.l2c.UpgradeReq_hits::total 34157 # number of UpgradeReq hits 2469system.l2c.SCUpgradeReq_hits::cpu0.data 2130 # number of SCUpgradeReq hits 2470system.l2c.SCUpgradeReq_hits::cpu1.data 884 # number of SCUpgradeReq hits 2471system.l2c.SCUpgradeReq_hits::total 3014 # number of SCUpgradeReq hits 2472system.l2c.ReadExReq_hits::cpu0.data 4062 # number of ReadExReq hits 2473system.l2c.ReadExReq_hits::cpu1.data 1324 # number of ReadExReq hits 2474system.l2c.ReadExReq_hits::total 5386 # number of ReadExReq hits 2475system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 98 # number of ReadSharedReq hits 2476system.l2c.ReadSharedReq_hits::cpu0.itb.walker 71 # number of ReadSharedReq hits 2477system.l2c.ReadSharedReq_hits::cpu0.inst 29368 # number of ReadSharedReq hits 2478system.l2c.ReadSharedReq_hits::cpu0.data 46989 # number of ReadSharedReq hits 2479system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 47574 # number of ReadSharedReq hits 2480system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 22 # number of ReadSharedReq hits 2481system.l2c.ReadSharedReq_hits::cpu1.itb.walker 20 # number of ReadSharedReq hits 2482system.l2c.ReadSharedReq_hits::cpu1.inst 6299 # number of ReadSharedReq hits 2483system.l2c.ReadSharedReq_hits::cpu1.data 4989 # number of ReadSharedReq hits 2484system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 3377 # number of ReadSharedReq hits 2485system.l2c.ReadSharedReq_hits::total 138807 # number of ReadSharedReq hits 2486system.l2c.demand_hits::cpu0.dtb.walker 98 # number of demand (read+write) hits 2487system.l2c.demand_hits::cpu0.itb.walker 71 # number of demand (read+write) hits 2488system.l2c.demand_hits::cpu0.inst 29368 # number of demand (read+write) hits 2489system.l2c.demand_hits::cpu0.data 51051 # number of demand (read+write) hits 2490system.l2c.demand_hits::cpu0.l2cache.prefetcher 47574 # number of demand (read+write) hits 2491system.l2c.demand_hits::cpu1.dtb.walker 22 # number of demand (read+write) hits 2492system.l2c.demand_hits::cpu1.itb.walker 20 # number of demand (read+write) hits 2493system.l2c.demand_hits::cpu1.inst 6299 # number of demand (read+write) hits 2494system.l2c.demand_hits::cpu1.data 6313 # number of demand (read+write) hits 2495system.l2c.demand_hits::cpu1.l2cache.prefetcher 3377 # number of demand (read+write) hits 2496system.l2c.demand_hits::total 144193 # number of demand (read+write) hits 2497system.l2c.overall_hits::cpu0.dtb.walker 98 # number of overall hits 2498system.l2c.overall_hits::cpu0.itb.walker 71 # number of overall hits 2499system.l2c.overall_hits::cpu0.inst 29368 # number of overall hits 2500system.l2c.overall_hits::cpu0.data 51051 # number of overall hits 2501system.l2c.overall_hits::cpu0.l2cache.prefetcher 47574 # number of overall hits 2502system.l2c.overall_hits::cpu1.dtb.walker 22 # number of overall hits 2503system.l2c.overall_hits::cpu1.itb.walker 20 # number of overall hits 2504system.l2c.overall_hits::cpu1.inst 6299 # number of overall hits 2505system.l2c.overall_hits::cpu1.data 6313 # number of overall hits 2506system.l2c.overall_hits::cpu1.l2cache.prefetcher 3377 # number of overall hits 2507system.l2c.overall_hits::total 144193 # number of overall hits 2508system.l2c.UpgradeReq_misses::cpu0.data 9379 # number of UpgradeReq misses 2509system.l2c.UpgradeReq_misses::cpu1.data 2248 # number of UpgradeReq misses 2510system.l2c.UpgradeReq_misses::total 11627 # number of UpgradeReq misses 2511system.l2c.SCUpgradeReq_misses::cpu0.data 589 # number of SCUpgradeReq misses 2512system.l2c.SCUpgradeReq_misses::cpu1.data 1277 # number of SCUpgradeReq misses 2513system.l2c.SCUpgradeReq_misses::total 1866 # number of SCUpgradeReq misses 2514system.l2c.ReadExReq_misses::cpu0.data 11187 # number of ReadExReq misses 2515system.l2c.ReadExReq_misses::cpu1.data 7836 # number of ReadExReq misses 2516system.l2c.ReadExReq_misses::total 19023 # number of ReadExReq misses 2517system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 7 # number of ReadSharedReq misses 2518system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2 # number of ReadSharedReq misses 2519system.l2c.ReadSharedReq_misses::cpu0.inst 17497 # number of ReadSharedReq misses 2520system.l2c.ReadSharedReq_misses::cpu0.data 8847 # number of ReadSharedReq misses 2521system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 134641 # number of ReadSharedReq misses 2522system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1 # number of ReadSharedReq misses 2523system.l2c.ReadSharedReq_misses::cpu1.inst 2371 # number of ReadSharedReq misses 2524system.l2c.ReadSharedReq_misses::cpu1.data 788 # number of ReadSharedReq misses 2525system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 5392 # number of ReadSharedReq misses 2526system.l2c.ReadSharedReq_misses::total 169546 # number of ReadSharedReq misses 2527system.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses 2528system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses 2529system.l2c.demand_misses::cpu0.inst 17497 # number of demand (read+write) misses 2530system.l2c.demand_misses::cpu0.data 20034 # number of demand (read+write) misses 2531system.l2c.demand_misses::cpu0.l2cache.prefetcher 134641 # number of demand (read+write) misses 2532system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses 2533system.l2c.demand_misses::cpu1.inst 2371 # number of demand (read+write) misses 2534system.l2c.demand_misses::cpu1.data 8624 # number of demand (read+write) misses 2535system.l2c.demand_misses::cpu1.l2cache.prefetcher 5392 # number of demand (read+write) misses 2536system.l2c.demand_misses::total 188569 # number of demand (read+write) misses 2537system.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses 2538system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses 2539system.l2c.overall_misses::cpu0.inst 17497 # number of overall misses 2540system.l2c.overall_misses::cpu0.data 20034 # number of overall misses 2541system.l2c.overall_misses::cpu0.l2cache.prefetcher 134641 # number of overall misses 2542system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses 2543system.l2c.overall_misses::cpu1.inst 2371 # number of overall misses 2544system.l2c.overall_misses::cpu1.data 8624 # number of overall misses 2545system.l2c.overall_misses::cpu1.l2cache.prefetcher 5392 # number of overall misses 2546system.l2c.overall_misses::total 188569 # number of overall misses 2547system.l2c.UpgradeReq_miss_latency::cpu0.data 29891000 # number of UpgradeReq miss cycles 2548system.l2c.UpgradeReq_miss_latency::cpu1.data 5943500 # number of UpgradeReq miss cycles 2549system.l2c.UpgradeReq_miss_latency::total 35834500 # number of UpgradeReq miss cycles 2550system.l2c.SCUpgradeReq_miss_latency::cpu0.data 4589000 # number of SCUpgradeReq miss cycles 2551system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1770500 # number of SCUpgradeReq miss cycles 2552system.l2c.SCUpgradeReq_miss_latency::total 6359500 # number of SCUpgradeReq miss cycles 2553system.l2c.ReadExReq_miss_latency::cpu0.data 1626887000 # number of ReadExReq miss cycles 2554system.l2c.ReadExReq_miss_latency::cpu1.data 1026108000 # number of ReadExReq miss cycles 2555system.l2c.ReadExReq_miss_latency::total 2652995000 # number of ReadExReq miss cycles 2556system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 948500 # number of ReadSharedReq miss cycles 2557system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 272000 # number of ReadSharedReq miss cycles 2558system.l2c.ReadSharedReq_miss_latency::cpu0.inst 2300069500 # number of ReadSharedReq miss cycles 2559system.l2c.ReadSharedReq_miss_latency::cpu0.data 1205085500 # number of ReadSharedReq miss cycles 2560system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 19535280293 # number of ReadSharedReq miss cycles 2561system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 132500 # number of ReadSharedReq miss cycles 2562system.l2c.ReadSharedReq_miss_latency::cpu1.inst 317997500 # number of ReadSharedReq miss cycles 2563system.l2c.ReadSharedReq_miss_latency::cpu1.data 116823500 # number of ReadSharedReq miss cycles 2564system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 839508015 # number of ReadSharedReq miss cycles 2565system.l2c.ReadSharedReq_miss_latency::total 24316117308 # number of ReadSharedReq miss cycles 2566system.l2c.demand_miss_latency::cpu0.dtb.walker 948500 # number of demand (read+write) miss cycles 2567system.l2c.demand_miss_latency::cpu0.itb.walker 272000 # number of demand (read+write) miss cycles 2568system.l2c.demand_miss_latency::cpu0.inst 2300069500 # number of demand (read+write) miss cycles 2569system.l2c.demand_miss_latency::cpu0.data 2831972500 # number of demand (read+write) miss cycles 2570system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 19535280293 # number of demand (read+write) miss cycles 2571system.l2c.demand_miss_latency::cpu1.dtb.walker 132500 # number of demand (read+write) miss cycles 2572system.l2c.demand_miss_latency::cpu1.inst 317997500 # number of demand (read+write) miss cycles 2573system.l2c.demand_miss_latency::cpu1.data 1142931500 # number of demand (read+write) miss cycles 2574system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 839508015 # number of demand (read+write) miss cycles 2575system.l2c.demand_miss_latency::total 26969112308 # number of demand (read+write) miss cycles 2576system.l2c.overall_miss_latency::cpu0.dtb.walker 948500 # number of overall miss cycles 2577system.l2c.overall_miss_latency::cpu0.itb.walker 272000 # number of overall miss cycles 2578system.l2c.overall_miss_latency::cpu0.inst 2300069500 # number of overall miss cycles 2579system.l2c.overall_miss_latency::cpu0.data 2831972500 # number of overall miss cycles 2580system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 19535280293 # number of overall miss cycles 2581system.l2c.overall_miss_latency::cpu1.dtb.walker 132500 # number of overall miss cycles 2582system.l2c.overall_miss_latency::cpu1.inst 317997500 # number of overall miss cycles 2583system.l2c.overall_miss_latency::cpu1.data 1142931500 # number of overall miss cycles 2584system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 839508015 # number of overall miss cycles 2585system.l2c.overall_miss_latency::total 26969112308 # number of overall miss cycles 2586system.l2c.WritebackDirty_accesses::writebacks 257503 # number of WritebackDirty accesses(hits+misses) 2587system.l2c.WritebackDirty_accesses::total 257503 # number of WritebackDirty accesses(hits+misses) 2588system.l2c.UpgradeReq_accesses::cpu0.data 41593 # number of UpgradeReq accesses(hits+misses) 2589system.l2c.UpgradeReq_accesses::cpu1.data 4191 # number of UpgradeReq accesses(hits+misses) 2590system.l2c.UpgradeReq_accesses::total 45784 # number of UpgradeReq accesses(hits+misses) 2591system.l2c.SCUpgradeReq_accesses::cpu0.data 2719 # number of SCUpgradeReq accesses(hits+misses) 2592system.l2c.SCUpgradeReq_accesses::cpu1.data 2161 # number of SCUpgradeReq accesses(hits+misses) 2593system.l2c.SCUpgradeReq_accesses::total 4880 # number of SCUpgradeReq accesses(hits+misses) 2594system.l2c.ReadExReq_accesses::cpu0.data 15249 # number of ReadExReq accesses(hits+misses) 2595system.l2c.ReadExReq_accesses::cpu1.data 9160 # number of ReadExReq accesses(hits+misses) 2596system.l2c.ReadExReq_accesses::total 24409 # number of ReadExReq accesses(hits+misses) 2597system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 105 # number of ReadSharedReq accesses(hits+misses) 2598system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 73 # number of ReadSharedReq accesses(hits+misses) 2599system.l2c.ReadSharedReq_accesses::cpu0.inst 46865 # number of ReadSharedReq accesses(hits+misses) 2600system.l2c.ReadSharedReq_accesses::cpu0.data 55836 # number of ReadSharedReq accesses(hits+misses) 2601system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 182215 # number of ReadSharedReq accesses(hits+misses) 2602system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 23 # number of ReadSharedReq accesses(hits+misses) 2603system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 20 # number of ReadSharedReq accesses(hits+misses) 2604system.l2c.ReadSharedReq_accesses::cpu1.inst 8670 # number of ReadSharedReq accesses(hits+misses) 2605system.l2c.ReadSharedReq_accesses::cpu1.data 5777 # number of ReadSharedReq accesses(hits+misses) 2606system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 8769 # number of ReadSharedReq accesses(hits+misses) 2607system.l2c.ReadSharedReq_accesses::total 308353 # number of ReadSharedReq accesses(hits+misses) 2608system.l2c.demand_accesses::cpu0.dtb.walker 105 # number of demand (read+write) accesses 2609system.l2c.demand_accesses::cpu0.itb.walker 73 # number of demand (read+write) accesses 2610system.l2c.demand_accesses::cpu0.inst 46865 # number of demand (read+write) accesses 2611system.l2c.demand_accesses::cpu0.data 71085 # number of demand (read+write) accesses 2612system.l2c.demand_accesses::cpu0.l2cache.prefetcher 182215 # number of demand (read+write) accesses 2613system.l2c.demand_accesses::cpu1.dtb.walker 23 # number of demand (read+write) accesses 2614system.l2c.demand_accesses::cpu1.itb.walker 20 # number of demand (read+write) accesses 2615system.l2c.demand_accesses::cpu1.inst 8670 # number of demand (read+write) accesses 2616system.l2c.demand_accesses::cpu1.data 14937 # number of demand (read+write) accesses 2617system.l2c.demand_accesses::cpu1.l2cache.prefetcher 8769 # number of demand (read+write) accesses 2618system.l2c.demand_accesses::total 332762 # number of demand (read+write) accesses 2619system.l2c.overall_accesses::cpu0.dtb.walker 105 # number of overall (read+write) accesses 2620system.l2c.overall_accesses::cpu0.itb.walker 73 # number of overall (read+write) accesses 2621system.l2c.overall_accesses::cpu0.inst 46865 # number of overall (read+write) accesses 2622system.l2c.overall_accesses::cpu0.data 71085 # number of overall (read+write) accesses 2623system.l2c.overall_accesses::cpu0.l2cache.prefetcher 182215 # number of overall (read+write) accesses 2624system.l2c.overall_accesses::cpu1.dtb.walker 23 # number of overall (read+write) accesses 2625system.l2c.overall_accesses::cpu1.itb.walker 20 # number of overall (read+write) accesses 2626system.l2c.overall_accesses::cpu1.inst 8670 # number of overall (read+write) accesses 2627system.l2c.overall_accesses::cpu1.data 14937 # number of overall (read+write) accesses 2628system.l2c.overall_accesses::cpu1.l2cache.prefetcher 8769 # number of overall (read+write) accesses 2629system.l2c.overall_accesses::total 332762 # number of overall (read+write) accesses 2630system.l2c.UpgradeReq_miss_rate::cpu0.data 0.225495 # miss rate for UpgradeReq accesses 2631system.l2c.UpgradeReq_miss_rate::cpu1.data 0.536387 # miss rate for UpgradeReq accesses 2632system.l2c.UpgradeReq_miss_rate::total 0.253953 # miss rate for UpgradeReq accesses 2633system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.216624 # miss rate for SCUpgradeReq accesses 2634system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.590930 # miss rate for SCUpgradeReq accesses 2635system.l2c.SCUpgradeReq_miss_rate::total 0.382377 # miss rate for SCUpgradeReq accesses 2636system.l2c.ReadExReq_miss_rate::cpu0.data 0.733622 # miss rate for ReadExReq accesses 2637system.l2c.ReadExReq_miss_rate::cpu1.data 0.855459 # miss rate for ReadExReq accesses 2638system.l2c.ReadExReq_miss_rate::total 0.779344 # miss rate for ReadExReq accesses 2639system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.066667 # miss rate for ReadSharedReq accesses 2640system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.027397 # miss rate for ReadSharedReq accesses 2641system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.373349 # miss rate for ReadSharedReq accesses 2642system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.158446 # miss rate for ReadSharedReq accesses 2643system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.738913 # miss rate for ReadSharedReq accesses 2644system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.043478 # miss rate for ReadSharedReq accesses 2645system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.273472 # miss rate for ReadSharedReq accesses 2646system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.136403 # miss rate for ReadSharedReq accesses 2647system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.614893 # miss rate for ReadSharedReq accesses 2648system.l2c.ReadSharedReq_miss_rate::total 0.549844 # miss rate for ReadSharedReq accesses 2649system.l2c.demand_miss_rate::cpu0.dtb.walker 0.066667 # miss rate for demand accesses 2650system.l2c.demand_miss_rate::cpu0.itb.walker 0.027397 # miss rate for demand accesses 2651system.l2c.demand_miss_rate::cpu0.inst 0.373349 # miss rate for demand accesses 2652system.l2c.demand_miss_rate::cpu0.data 0.281832 # miss rate for demand accesses 2653system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.738913 # miss rate for demand accesses 2654system.l2c.demand_miss_rate::cpu1.dtb.walker 0.043478 # miss rate for demand accesses 2655system.l2c.demand_miss_rate::cpu1.inst 0.273472 # miss rate for demand accesses 2656system.l2c.demand_miss_rate::cpu1.data 0.577358 # miss rate for demand accesses 2657system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.614893 # miss rate for demand accesses 2658system.l2c.demand_miss_rate::total 0.566678 # miss rate for demand accesses 2659system.l2c.overall_miss_rate::cpu0.dtb.walker 0.066667 # miss rate for overall accesses 2660system.l2c.overall_miss_rate::cpu0.itb.walker 0.027397 # miss rate for overall accesses 2661system.l2c.overall_miss_rate::cpu0.inst 0.373349 # miss rate for overall accesses 2662system.l2c.overall_miss_rate::cpu0.data 0.281832 # miss rate for overall accesses 2663system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.738913 # miss rate for overall accesses 2664system.l2c.overall_miss_rate::cpu1.dtb.walker 0.043478 # miss rate for overall accesses 2665system.l2c.overall_miss_rate::cpu1.inst 0.273472 # miss rate for overall accesses 2666system.l2c.overall_miss_rate::cpu1.data 0.577358 # miss rate for overall accesses 2667system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.614893 # miss rate for overall accesses 2668system.l2c.overall_miss_rate::total 0.566678 # miss rate for overall accesses 2669system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3187.013541 # average UpgradeReq miss latency 2670system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2643.905694 # average UpgradeReq miss latency 2671system.l2c.UpgradeReq_avg_miss_latency::total 3082.007397 # average UpgradeReq miss latency 2672system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 7791.171477 # average SCUpgradeReq miss latency 2673system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1386.452623 # average SCUpgradeReq miss latency 2674system.l2c.SCUpgradeReq_avg_miss_latency::total 3408.092176 # average SCUpgradeReq miss latency 2675system.l2c.ReadExReq_avg_miss_latency::cpu0.data 145426.566550 # average ReadExReq miss latency 2676system.l2c.ReadExReq_avg_miss_latency::cpu1.data 130947.932619 # average ReadExReq miss latency 2677system.l2c.ReadExReq_avg_miss_latency::total 139462.492772 # average ReadExReq miss latency 2678system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 135500 # average ReadSharedReq miss latency 2679system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 136000 # average ReadSharedReq miss latency 2680system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 131455.078013 # average ReadSharedReq miss latency 2681system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 136214.027354 # average ReadSharedReq miss latency 2682system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 145091.616172 # average ReadSharedReq miss latency 2683system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 132500 # average ReadSharedReq miss latency 2684system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 134119.569802 # average ReadSharedReq miss latency 2685system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 148253.172589 # average ReadSharedReq miss latency 2686system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 155695.106639 # average ReadSharedReq miss latency 2687system.l2c.ReadSharedReq_avg_miss_latency::total 143418.997251 # average ReadSharedReq miss latency 2688system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 135500 # average overall miss latency 2689system.l2c.demand_avg_miss_latency::cpu0.itb.walker 136000 # average overall miss latency 2690system.l2c.demand_avg_miss_latency::cpu0.inst 131455.078013 # average overall miss latency 2691system.l2c.demand_avg_miss_latency::cpu0.data 141358.315863 # average overall miss latency 2692system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 145091.616172 # average overall miss latency 2693system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 132500 # average overall miss latency 2694system.l2c.demand_avg_miss_latency::cpu1.inst 134119.569802 # average overall miss latency 2695system.l2c.demand_avg_miss_latency::cpu1.data 132529.162801 # average overall miss latency 2696system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 155695.106639 # average overall miss latency 2697system.l2c.demand_avg_miss_latency::total 143019.861738 # average overall miss latency 2698system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 135500 # average overall miss latency 2699system.l2c.overall_avg_miss_latency::cpu0.itb.walker 136000 # average overall miss latency 2700system.l2c.overall_avg_miss_latency::cpu0.inst 131455.078013 # average overall miss latency 2701system.l2c.overall_avg_miss_latency::cpu0.data 141358.315863 # average overall miss latency 2702system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 145091.616172 # average overall miss latency 2703system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 132500 # average overall miss latency 2704system.l2c.overall_avg_miss_latency::cpu1.inst 134119.569802 # average overall miss latency 2705system.l2c.overall_avg_miss_latency::cpu1.data 132529.162801 # average overall miss latency 2706system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 155695.106639 # average overall miss latency 2707system.l2c.overall_avg_miss_latency::total 143019.861738 # average overall miss latency 2708system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2709system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2710system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 2711system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2712system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2713system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2714system.l2c.fast_writes 0 # number of fast writes performed 2715system.l2c.cache_copies 0 # number of cache copies performed 2716system.l2c.writebacks::writebacks 96871 # number of writebacks 2717system.l2c.writebacks::total 96871 # number of writebacks 2718system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 5 # number of ReadSharedReq MSHR hits 2719system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 10 # number of ReadSharedReq MSHR hits 2720system.l2c.ReadSharedReq_mshr_hits::total 15 # number of ReadSharedReq MSHR hits 2721system.l2c.demand_mshr_hits::cpu0.inst 5 # number of demand (read+write) MSHR hits 2722system.l2c.demand_mshr_hits::cpu1.inst 10 # number of demand (read+write) MSHR hits 2723system.l2c.demand_mshr_hits::total 15 # number of demand (read+write) MSHR hits 2724system.l2c.overall_mshr_hits::cpu0.inst 5 # number of overall MSHR hits 2725system.l2c.overall_mshr_hits::cpu1.inst 10 # number of overall MSHR hits 2726system.l2c.overall_mshr_hits::total 15 # number of overall MSHR hits 2727system.l2c.CleanEvict_mshr_misses::writebacks 2791 # number of CleanEvict MSHR misses 2728system.l2c.CleanEvict_mshr_misses::total 2791 # number of CleanEvict MSHR misses 2729system.l2c.UpgradeReq_mshr_misses::cpu0.data 9379 # number of UpgradeReq MSHR misses 2730system.l2c.UpgradeReq_mshr_misses::cpu1.data 2248 # number of UpgradeReq MSHR misses 2731system.l2c.UpgradeReq_mshr_misses::total 11627 # number of UpgradeReq MSHR misses 2732system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 589 # number of SCUpgradeReq MSHR misses 2733system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1277 # number of SCUpgradeReq MSHR misses 2734system.l2c.SCUpgradeReq_mshr_misses::total 1866 # number of SCUpgradeReq MSHR misses 2735system.l2c.ReadExReq_mshr_misses::cpu0.data 11187 # number of ReadExReq MSHR misses 2736system.l2c.ReadExReq_mshr_misses::cpu1.data 7836 # number of ReadExReq MSHR misses 2737system.l2c.ReadExReq_mshr_misses::total 19023 # number of ReadExReq MSHR misses 2738system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 7 # number of ReadSharedReq MSHR misses 2739system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 2 # number of ReadSharedReq MSHR misses 2740system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 17492 # number of ReadSharedReq MSHR misses 2741system.l2c.ReadSharedReq_mshr_misses::cpu0.data 8847 # number of ReadSharedReq MSHR misses 2742system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 134641 # number of ReadSharedReq MSHR misses 2743system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadSharedReq MSHR misses 2744system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2361 # number of ReadSharedReq MSHR misses 2745system.l2c.ReadSharedReq_mshr_misses::cpu1.data 788 # number of ReadSharedReq MSHR misses 2746system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 5392 # number of ReadSharedReq MSHR misses 2747system.l2c.ReadSharedReq_mshr_misses::total 169531 # number of ReadSharedReq MSHR misses 2748system.l2c.demand_mshr_misses::cpu0.dtb.walker 7 # number of demand (read+write) MSHR misses 2749system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses 2750system.l2c.demand_mshr_misses::cpu0.inst 17492 # number of demand (read+write) MSHR misses 2751system.l2c.demand_mshr_misses::cpu0.data 20034 # number of demand (read+write) MSHR misses 2752system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 134641 # number of demand (read+write) MSHR misses 2753system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses 2754system.l2c.demand_mshr_misses::cpu1.inst 2361 # number of demand (read+write) MSHR misses 2755system.l2c.demand_mshr_misses::cpu1.data 8624 # number of demand (read+write) MSHR misses 2756system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 5392 # number of demand (read+write) MSHR misses 2757system.l2c.demand_mshr_misses::total 188554 # number of demand (read+write) MSHR misses 2758system.l2c.overall_mshr_misses::cpu0.dtb.walker 7 # number of overall MSHR misses 2759system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses 2760system.l2c.overall_mshr_misses::cpu0.inst 17492 # number of overall MSHR misses 2761system.l2c.overall_mshr_misses::cpu0.data 20034 # number of overall MSHR misses 2762system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 134641 # number of overall MSHR misses 2763system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses 2764system.l2c.overall_mshr_misses::cpu1.inst 2361 # number of overall MSHR misses 2765system.l2c.overall_mshr_misses::cpu1.data 8624 # number of overall MSHR misses 2766system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 5392 # number of overall MSHR misses 2767system.l2c.overall_mshr_misses::total 188554 # number of overall MSHR misses 2768system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable 2769system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31819 # number of ReadReq MSHR uncacheable 2770system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable 2771system.l2c.ReadReq_mshr_uncacheable::cpu1.data 3078 # number of ReadReq MSHR uncacheable 2772system.l2c.ReadReq_mshr_uncacheable::total 44096 # number of ReadReq MSHR uncacheable 2773system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28499 # number of WriteReq MSHR uncacheable 2774system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2423 # number of WriteReq MSHR uncacheable 2775system.l2c.WriteReq_mshr_uncacheable::total 30922 # number of WriteReq MSHR uncacheable 2776system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses 2777system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60318 # number of overall MSHR uncacheable misses 2778system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses 2779system.l2c.overall_mshr_uncacheable_misses::cpu1.data 5501 # number of overall MSHR uncacheable misses 2780system.l2c.overall_mshr_uncacheable_misses::total 75018 # number of overall MSHR uncacheable misses 2781system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 706950000 # number of UpgradeReq MSHR miss cycles 2782system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 168753500 # number of UpgradeReq MSHR miss cycles 2783system.l2c.UpgradeReq_mshr_miss_latency::total 875703500 # number of UpgradeReq MSHR miss cycles 2784system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 45541000 # number of SCUpgradeReq MSHR miss cycles 2785system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 97962500 # number of SCUpgradeReq MSHR miss cycles 2786system.l2c.SCUpgradeReq_mshr_miss_latency::total 143503500 # number of SCUpgradeReq MSHR miss cycles 2787system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1515017000 # number of ReadExReq MSHR miss cycles 2788system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 947748000 # number of ReadExReq MSHR miss cycles 2789system.l2c.ReadExReq_mshr_miss_latency::total 2462765000 # number of ReadExReq MSHR miss cycles 2790system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 878500 # number of ReadSharedReq MSHR miss cycles 2791system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 252000 # number of ReadSharedReq MSHR miss cycles 2792system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 2124790500 # number of ReadSharedReq MSHR miss cycles 2793system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1116615500 # number of ReadSharedReq MSHR miss cycles 2794system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 18188870293 # number of ReadSharedReq MSHR miss cycles 2795system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 122500 # number of ReadSharedReq MSHR miss cycles 2796system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 293429500 # number of ReadSharedReq MSHR miss cycles 2797system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 108943500 # number of ReadSharedReq MSHR miss cycles 2798system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 785588015 # number of ReadSharedReq MSHR miss cycles 2799system.l2c.ReadSharedReq_mshr_miss_latency::total 22619490308 # number of ReadSharedReq MSHR miss cycles 2800system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 878500 # number of demand (read+write) MSHR miss cycles 2801system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 252000 # number of demand (read+write) MSHR miss cycles 2802system.l2c.demand_mshr_miss_latency::cpu0.inst 2124790500 # number of demand (read+write) MSHR miss cycles 2803system.l2c.demand_mshr_miss_latency::cpu0.data 2631632500 # number of demand (read+write) MSHR miss cycles 2804system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 18188870293 # number of demand (read+write) MSHR miss cycles 2805system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 122500 # number of demand (read+write) MSHR miss cycles 2806system.l2c.demand_mshr_miss_latency::cpu1.inst 293429500 # number of demand (read+write) MSHR miss cycles 2807system.l2c.demand_mshr_miss_latency::cpu1.data 1056691500 # number of demand (read+write) MSHR miss cycles 2808system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 785588015 # number of demand (read+write) MSHR miss cycles 2809system.l2c.demand_mshr_miss_latency::total 25082255308 # number of demand (read+write) MSHR miss cycles 2810system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 878500 # number of overall MSHR miss cycles 2811system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 252000 # number of overall MSHR miss cycles 2812system.l2c.overall_mshr_miss_latency::cpu0.inst 2124790500 # number of overall MSHR miss cycles 2813system.l2c.overall_mshr_miss_latency::cpu0.data 2631632500 # number of overall MSHR miss cycles 2814system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 18188870293 # number of overall MSHR miss cycles 2815system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 122500 # number of overall MSHR miss cycles 2816system.l2c.overall_mshr_miss_latency::cpu1.inst 293429500 # number of overall MSHR miss cycles 2817system.l2c.overall_mshr_miss_latency::cpu1.data 1056691500 # number of overall MSHR miss cycles 2818system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 785588015 # number of overall MSHR miss cycles 2819system.l2c.overall_mshr_miss_latency::total 25082255308 # number of overall MSHR miss cycles 2820system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 1023815000 # number of ReadReq MSHR uncacheable cycles 2821system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5802133000 # number of ReadReq MSHR uncacheable cycles 2822system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 19032500 # number of ReadReq MSHR uncacheable cycles 2823system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 358998500 # number of ReadReq MSHR uncacheable cycles 2824system.l2c.ReadReq_mshr_uncacheable_latency::total 7203979000 # number of ReadReq MSHR uncacheable cycles 2825system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4702508000 # number of WriteReq MSHR uncacheable cycles 2826system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 243698500 # number of WriteReq MSHR uncacheable cycles 2827system.l2c.WriteReq_mshr_uncacheable_latency::total 4946206500 # number of WriteReq MSHR uncacheable cycles 2828system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 1023815000 # number of overall MSHR uncacheable cycles 2829system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10504641000 # number of overall MSHR uncacheable cycles 2830system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 19032500 # number of overall MSHR uncacheable cycles 2831system.l2c.overall_mshr_uncacheable_latency::cpu1.data 602697000 # number of overall MSHR uncacheable cycles 2832system.l2c.overall_mshr_uncacheable_latency::total 12150185500 # number of overall MSHR uncacheable cycles 2833system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 2834system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 2835system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.225495 # mshr miss rate for UpgradeReq accesses 2836system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.536387 # mshr miss rate for UpgradeReq accesses 2837system.l2c.UpgradeReq_mshr_miss_rate::total 0.253953 # mshr miss rate for UpgradeReq accesses 2838system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.216624 # mshr miss rate for SCUpgradeReq accesses 2839system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.590930 # mshr miss rate for SCUpgradeReq accesses 2840system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.382377 # mshr miss rate for SCUpgradeReq accesses 2841system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.733622 # mshr miss rate for ReadExReq accesses 2842system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.855459 # mshr miss rate for ReadExReq accesses 2843system.l2c.ReadExReq_mshr_miss_rate::total 0.779344 # mshr miss rate for ReadExReq accesses 2844system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.066667 # mshr miss rate for ReadSharedReq accesses 2845system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.027397 # mshr miss rate for ReadSharedReq accesses 2846system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.373242 # mshr miss rate for ReadSharedReq accesses 2847system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.158446 # mshr miss rate for ReadSharedReq accesses 2848system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.738913 # mshr miss rate for ReadSharedReq accesses 2849system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.043478 # mshr miss rate for ReadSharedReq accesses 2850system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.272318 # mshr miss rate for ReadSharedReq accesses 2851system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.136403 # mshr miss rate for ReadSharedReq accesses 2852system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.614893 # mshr miss rate for ReadSharedReq accesses 2853system.l2c.ReadSharedReq_mshr_miss_rate::total 0.549795 # mshr miss rate for ReadSharedReq accesses 2854system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.066667 # mshr miss rate for demand accesses 2855system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.027397 # mshr miss rate for demand accesses 2856system.l2c.demand_mshr_miss_rate::cpu0.inst 0.373242 # mshr miss rate for demand accesses 2857system.l2c.demand_mshr_miss_rate::cpu0.data 0.281832 # mshr miss rate for demand accesses 2858system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.738913 # mshr miss rate for demand accesses 2859system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.043478 # mshr miss rate for demand accesses 2860system.l2c.demand_mshr_miss_rate::cpu1.inst 0.272318 # mshr miss rate for demand accesses 2861system.l2c.demand_mshr_miss_rate::cpu1.data 0.577358 # mshr miss rate for demand accesses 2862system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.614893 # mshr miss rate for demand accesses 2863system.l2c.demand_mshr_miss_rate::total 0.566633 # mshr miss rate for demand accesses 2864system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.066667 # mshr miss rate for overall accesses 2865system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.027397 # mshr miss rate for overall accesses 2866system.l2c.overall_mshr_miss_rate::cpu0.inst 0.373242 # mshr miss rate for overall accesses 2867system.l2c.overall_mshr_miss_rate::cpu0.data 0.281832 # mshr miss rate for overall accesses 2868system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.738913 # mshr miss rate for overall accesses 2869system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.043478 # mshr miss rate for overall accesses 2870system.l2c.overall_mshr_miss_rate::cpu1.inst 0.272318 # mshr miss rate for overall accesses 2871system.l2c.overall_mshr_miss_rate::cpu1.data 0.577358 # mshr miss rate for overall accesses 2872system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.614893 # mshr miss rate for overall accesses 2873system.l2c.overall_mshr_miss_rate::total 0.566633 # mshr miss rate for overall accesses 2874system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 75375.839642 # average UpgradeReq mshr miss latency 2875system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 75068.282918 # average UpgradeReq mshr miss latency 2876system.l2c.UpgradeReq_avg_mshr_miss_latency::total 75316.375677 # average UpgradeReq mshr miss latency 2877system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 77319.185059 # average SCUpgradeReq mshr miss latency 2878system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76712.999217 # average SCUpgradeReq mshr miss latency 2879system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76904.340836 # average SCUpgradeReq mshr miss latency 2880system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 135426.566550 # average ReadExReq mshr miss latency 2881system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 120947.932619 # average ReadExReq mshr miss latency 2882system.l2c.ReadExReq_avg_mshr_miss_latency::total 129462.492772 # average ReadExReq mshr miss latency 2883system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 125500 # average ReadSharedReq mshr miss latency 2884system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 126000 # average ReadSharedReq mshr miss latency 2885system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 121472.130117 # average ReadSharedReq mshr miss latency 2886system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 126214.027354 # average ReadSharedReq mshr miss latency 2887system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135091.616172 # average ReadSharedReq mshr miss latency 2888system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 122500 # average ReadSharedReq mshr miss latency 2889system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124281.872088 # average ReadSharedReq mshr miss latency 2890system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 138253.172589 # average ReadSharedReq mshr miss latency 2891system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 145695.106639 # average ReadSharedReq mshr miss latency 2892system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 133423.918387 # average ReadSharedReq mshr miss latency 2893system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 125500 # average overall mshr miss latency 2894system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 126000 # average overall mshr miss latency 2895system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121472.130117 # average overall mshr miss latency 2896system.l2c.demand_avg_mshr_miss_latency::cpu0.data 131358.315863 # average overall mshr miss latency 2897system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135091.616172 # average overall mshr miss latency 2898system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 122500 # average overall mshr miss latency 2899system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124281.872088 # average overall mshr miss latency 2900system.l2c.demand_avg_mshr_miss_latency::cpu1.data 122529.162801 # average overall mshr miss latency 2901system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 145695.106639 # average overall mshr miss latency 2902system.l2c.demand_avg_mshr_miss_latency::total 133024.254633 # average overall mshr miss latency 2903system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 125500 # average overall mshr miss latency 2904system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 126000 # average overall mshr miss latency 2905system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121472.130117 # average overall mshr miss latency 2906system.l2c.overall_avg_mshr_miss_latency::cpu0.data 131358.315863 # average overall mshr miss latency 2907system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135091.616172 # average overall mshr miss latency 2908system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 122500 # average overall mshr miss latency 2909system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124281.872088 # average overall mshr miss latency 2910system.l2c.overall_avg_mshr_miss_latency::cpu1.data 122529.162801 # average overall mshr miss latency 2911system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 145695.106639 # average overall mshr miss latency 2912system.l2c.overall_avg_mshr_miss_latency::total 133024.254633 # average overall mshr miss latency 2913system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113479.827089 # average ReadReq mshr uncacheable latency 2914system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182348.062478 # average ReadReq mshr uncacheable latency 2915system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 107528.248588 # average ReadReq mshr uncacheable latency 2916system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116633.690708 # average ReadReq mshr uncacheable latency 2917system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 163370.351052 # average ReadReq mshr uncacheable latency 2918system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165006.070388 # average WriteReq mshr uncacheable latency 2919system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 100577.177053 # average WriteReq mshr uncacheable latency 2920system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159957.522153 # average WriteReq mshr uncacheable latency 2921system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113479.827089 # average overall mshr uncacheable latency 2922system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 174154.332040 # average overall mshr uncacheable latency 2923system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 107528.248588 # average overall mshr uncacheable latency 2924system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 109561.352481 # average overall mshr uncacheable latency 2925system.l2c.overall_avg_mshr_uncacheable_latency::total 161963.602069 # average overall mshr uncacheable latency 2926system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 2927system.membus.trans_dist::ReadReq 44096 # Transaction distribution 2928system.membus.trans_dist::ReadResp 213882 # Transaction distribution 2929system.membus.trans_dist::WriteReq 30922 # Transaction distribution 2930system.membus.trans_dist::WriteResp 30922 # Transaction distribution 2931system.membus.trans_dist::WritebackDirty 133077 # Transaction distribution 2932system.membus.trans_dist::CleanEvict 14603 # Transaction distribution 2933system.membus.trans_dist::UpgradeReq 73616 # Transaction distribution 2934system.membus.trans_dist::SCUpgradeReq 39905 # Transaction distribution 2935system.membus.trans_dist::UpgradeResp 13581 # Transaction distribution 2936system.membus.trans_dist::SCUpgradeFailReq 8 # Transaction distribution 2937system.membus.trans_dist::ReadExReq 39514 # Transaction distribution 2938system.membus.trans_dist::ReadExResp 18935 # Transaction distribution 2939system.membus.trans_dist::ReadSharedReq 169786 # Transaction distribution 2940system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 2941system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution 2942system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107934 # Packet count per connected master and slave (bytes) 2943system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) 2944system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13766 # Packet count per connected master and slave (bytes) 2945system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 664049 # Packet count per connected master and slave (bytes) 2946system.membus.pkt_count_system.l2c.mem_side::total 785783 # Packet count per connected master and slave (bytes) 2947system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108937 # Packet count per connected master and slave (bytes) 2948system.membus.pkt_count_system.iocache.mem_side::total 108937 # Packet count per connected master and slave (bytes) 2949system.membus.pkt_count::total 894720 # Packet count per connected master and slave (bytes) 2950system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162814 # Cumulative packet size per connected master and slave (bytes) 2951system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) 2952system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27532 # Cumulative packet size per connected master and slave (bytes) 2953system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18296972 # Cumulative packet size per connected master and slave (bytes) 2954system.membus.pkt_size_system.l2c.mem_side::total 18487386 # Cumulative packet size per connected master and slave (bytes) 2955system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) 2956system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) 2957system.membus.pkt_size::total 20805530 # Cumulative packet size per connected master and slave (bytes) 2958system.membus.snoops 121102 # Total snoops (count) 2959system.membus.snoop_fanout::samples 582015 # Request fanout histogram 2960system.membus.snoop_fanout::mean 1 # Request fanout histogram 2961system.membus.snoop_fanout::stdev 0 # Request fanout histogram 2962system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2963system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 2964system.membus.snoop_fanout::1 582015 100.00% 100.00% # Request fanout histogram 2965system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 2966system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2967system.membus.snoop_fanout::min_value 1 # Request fanout histogram 2968system.membus.snoop_fanout::max_value 1 # Request fanout histogram 2969system.membus.snoop_fanout::total 582015 # Request fanout histogram 2970system.membus.reqLayer0.occupancy 88274000 # Layer occupancy (ticks) 2971system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 2972system.membus.reqLayer1.occupancy 19000 # Layer occupancy (ticks) 2973system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 2974system.membus.reqLayer2.occupancy 11368000 # Layer occupancy (ticks) 2975system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 2976system.membus.reqLayer5.occupancy 966740692 # Layer occupancy (ticks) 2977system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 2978system.membus.respLayer2.occupancy 1134075509 # Layer occupancy (ticks) 2979system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 2980system.membus.respLayer3.occupancy 64085297 # Layer occupancy (ticks) 2981system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 2982system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 2983system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 2984system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 2985system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 2986system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 2987system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 2988system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 2989system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 2990system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 2991system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 2992system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 2993system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 2994system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 2995system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 2996system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 2997system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 2998system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 2999system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 3000system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 3001system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 3002system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 3003system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 3004system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 3005system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 3006system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 3007system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 3008system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 3009system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 3010system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 3011system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 3012system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3013system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3014system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 3015system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3016system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 3017system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 3018system.realview.ethernet.droppedPackets 0 # number of packets dropped 3019system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 3020system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 3021system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 3022system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 3023system.toL2Bus.snoop_filter.tot_requests 961177 # Total number of requests made to the snoop filter. 3024system.toL2Bus.snoop_filter.hit_single_requests 518872 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3025system.toL2Bus.snoop_filter.hit_multi_requests 139554 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3026system.toL2Bus.snoop_filter.tot_snoops 20662 # Total number of snoops made to the snoop filter. 3027system.toL2Bus.snoop_filter.hit_single_snoops 19793 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3028system.toL2Bus.snoop_filter.hit_multi_snoops 869 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3029system.toL2Bus.trans_dist::ReadReq 44099 # Transaction distribution 3030system.toL2Bus.trans_dist::ReadResp 468456 # Transaction distribution 3031system.toL2Bus.trans_dist::WriteReq 30922 # Transaction distribution 3032system.toL2Bus.trans_dist::WriteResp 30922 # Transaction distribution 3033system.toL2Bus.trans_dist::WritebackDirty 390602 # Transaction distribution 3034system.toL2Bus.trans_dist::CleanEvict 84323 # Transaction distribution 3035system.toL2Bus.trans_dist::UpgradeReq 107685 # Transaction distribution 3036system.toL2Bus.trans_dist::SCUpgradeReq 42919 # Transaction distribution 3037system.toL2Bus.trans_dist::UpgradeResp 150604 # Transaction distribution 3038system.toL2Bus.trans_dist::SCUpgradeFailReq 84 # Transaction distribution 3039system.toL2Bus.trans_dist::UpgradeFailResp 84 # Transaction distribution 3040system.toL2Bus.trans_dist::ReadExReq 50476 # Transaction distribution 3041system.toL2Bus.trans_dist::ReadExResp 50476 # Transaction distribution 3042system.toL2Bus.trans_dist::ReadSharedReq 424372 # Transaction distribution 3043system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution 3044system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1224412 # Packet count per connected master and slave (bytes) 3045system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 249093 # Packet count per connected master and slave (bytes) 3046system.toL2Bus.pkt_count::total 1473505 # Packet count per connected master and slave (bytes) 3047system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34296330 # Cumulative packet size per connected master and slave (bytes) 3048system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 3743120 # Cumulative packet size per connected master and slave (bytes) 3049system.toL2Bus.pkt_size::total 38039450 # Cumulative packet size per connected master and slave (bytes) 3050system.toL2Bus.snoops 438983 # Total snoops (count) 3051system.toL2Bus.snoop_fanout::samples 897187 # Request fanout histogram 3052system.toL2Bus.snoop_fanout::mean 0.337621 # Request fanout histogram 3053system.toL2Bus.snoop_fanout::stdev 0.474943 # Request fanout histogram 3054system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3055system.toL2Bus.snoop_fanout::0 595147 66.33% 66.33% # Request fanout histogram 3056system.toL2Bus.snoop_fanout::1 301171 33.57% 99.90% # Request fanout histogram 3057system.toL2Bus.snoop_fanout::2 869 0.10% 100.00% # Request fanout histogram 3058system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3059system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 3060system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 3061system.toL2Bus.snoop_fanout::total 897187 # Request fanout histogram 3062system.toL2Bus.reqLayer0.occupancy 864296758 # Layer occupancy (ticks) 3063system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 3064system.toL2Bus.snoopLayer0.occupancy 360622 # Layer occupancy (ticks) 3065system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3066system.toL2Bus.respLayer0.occupancy 647366860 # Layer occupancy (ticks) 3067system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3068system.toL2Bus.respLayer1.occupancy 201908331 # Layer occupancy (ticks) 3069system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3070 3071---------- End Simulation Statistics ---------- 3072