stats.txt revision 10892:bd37e25fb3b7
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.868721 # Number of seconds simulated 4sim_ticks 2868720569000 # Number of ticks simulated 5final_tick 2868720569000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 718623 # Simulator instruction rate (inst/s) 8host_op_rate 869205 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 15661016649 # Simulator tick rate (ticks/s) 10host_mem_usage 645712 # Number of bytes of host memory used 11host_seconds 183.18 # Real time elapsed on the host 12sim_insts 131634295 # Number of instructions simulated 13sim_ops 159217322 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 1149540 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 1292388 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 8590592 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.inst 151892 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.data 585104 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.l2cache.prefetcher 399936 # Number of bytes read from this memory 25system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 26system.physmem.bytes_read::total 12171052 # Number of bytes read from this memory 27system.physmem.bytes_inst_read::cpu0.inst 1149540 # Number of instructions bytes read from this memory 28system.physmem.bytes_inst_read::cpu1.inst 151892 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::total 1301432 # Number of instructions bytes read from this memory 30system.physmem.bytes_written::writebacks 8736704 # Number of bytes written to this memory 31system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory 32system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory 33system.physmem.bytes_written::total 8754268 # Number of bytes written to this memory 34system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.inst 26415 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.data 20713 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.l2cache.prefetcher 134228 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.inst 2528 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.data 9162 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.l2cache.prefetcher 6249 # Number of read requests responded to by this memory 43system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 44system.physmem.num_reads::total 199320 # Number of read requests responded to by this memory 45system.physmem.num_writes::writebacks 136511 # Number of write requests responded to by this memory 46system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory 47system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory 48system.physmem.num_writes::total 140902 # Number of write requests responded to by this memory 49system.physmem.bw_read::cpu0.dtb.walker 156 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu0.inst 400715 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.data 450510 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.l2cache.prefetcher 2994573 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu1.dtb.walker 22 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu1.inst 52948 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu1.data 203960 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.l2cache.prefetcher 139413 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::realview.ide 335 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::total 4242676 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_inst_read::cpu0.inst 400715 # Instruction read bandwidth from this memory (bytes/s) 61system.physmem.bw_inst_read::cpu1.inst 52948 # Instruction read bandwidth from this memory (bytes/s) 62system.physmem.bw_inst_read::total 453663 # Instruction read bandwidth from this memory (bytes/s) 63system.physmem.bw_write::writebacks 3045505 # Write bandwidth from this memory (bytes/s) 64system.physmem.bw_write::cpu0.data 6109 # Write bandwidth from this memory (bytes/s) 65system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) 66system.physmem.bw_write::total 3051628 # Write bandwidth from this memory (bytes/s) 67system.physmem.bw_total::writebacks 3045505 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::cpu0.dtb.walker 156 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) 70system.physmem.bw_total::cpu0.inst 400715 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu0.data 456619 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.l2cache.prefetcher 2994573 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu1.dtb.walker 22 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu1.inst 52948 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu1.data 203974 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu1.l2cache.prefetcher 139413 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::realview.ide 335 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::total 7294304 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.readReqs 199320 # Number of read requests accepted 80system.physmem.writeReqs 140902 # Number of write requests accepted 81system.physmem.readBursts 199320 # Number of DRAM read bursts, including those serviced by the write queue 82system.physmem.writeBursts 140902 # Number of DRAM write bursts, including those merged in the write queue 83system.physmem.bytesReadDRAM 12746944 # Total number of bytes read from DRAM 84system.physmem.bytesReadWrQ 9536 # Total number of bytes read from write queue 85system.physmem.bytesWritten 8766656 # Total number of bytes written to DRAM 86system.physmem.bytesReadSys 12171052 # Total read bytes from the system interface side 87system.physmem.bytesWrittenSys 8754268 # Total written bytes from the system interface side 88system.physmem.servicedByWrQ 149 # Number of DRAM read bursts serviced by the write queue 89system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one 90system.physmem.neitherReadNorWriteReqs 49030 # Number of requests that are neither read nor write 91system.physmem.perBankRdBursts::0 12070 # Per bank write bursts 92system.physmem.perBankRdBursts::1 11831 # Per bank write bursts 93system.physmem.perBankRdBursts::2 12274 # Per bank write bursts 94system.physmem.perBankRdBursts::3 12388 # Per bank write bursts 95system.physmem.perBankRdBursts::4 20676 # Per bank write bursts 96system.physmem.perBankRdBursts::5 12594 # Per bank write bursts 97system.physmem.perBankRdBursts::6 12033 # Per bank write bursts 98system.physmem.perBankRdBursts::7 12197 # Per bank write bursts 99system.physmem.perBankRdBursts::8 12580 # Per bank write bursts 100system.physmem.perBankRdBursts::9 12376 # Per bank write bursts 101system.physmem.perBankRdBursts::10 11749 # Per bank write bursts 102system.physmem.perBankRdBursts::11 11049 # Per bank write bursts 103system.physmem.perBankRdBursts::12 11595 # Per bank write bursts 104system.physmem.perBankRdBursts::13 11646 # Per bank write bursts 105system.physmem.perBankRdBursts::14 10943 # Per bank write bursts 106system.physmem.perBankRdBursts::15 11170 # Per bank write bursts 107system.physmem.perBankWrBursts::0 8793 # Per bank write bursts 108system.physmem.perBankWrBursts::1 8761 # Per bank write bursts 109system.physmem.perBankWrBursts::2 9161 # Per bank write bursts 110system.physmem.perBankWrBursts::3 8988 # Per bank write bursts 111system.physmem.perBankWrBursts::4 8395 # Per bank write bursts 112system.physmem.perBankWrBursts::5 9123 # Per bank write bursts 113system.physmem.perBankWrBursts::6 8851 # Per bank write bursts 114system.physmem.perBankWrBursts::7 8630 # Per bank write bursts 115system.physmem.perBankWrBursts::8 9078 # Per bank write bursts 116system.physmem.perBankWrBursts::9 8912 # Per bank write bursts 117system.physmem.perBankWrBursts::10 8485 # Per bank write bursts 118system.physmem.perBankWrBursts::11 8089 # Per bank write bursts 119system.physmem.perBankWrBursts::12 8403 # Per bank write bursts 120system.physmem.perBankWrBursts::13 8019 # Per bank write bursts 121system.physmem.perBankWrBursts::14 7666 # Per bank write bursts 122system.physmem.perBankWrBursts::15 7625 # Per bank write bursts 123system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 124system.physmem.numWrRetry 43 # Number of times write queue was full causing retry 125system.physmem.totGap 2868720108500 # Total gap between requests 126system.physmem.readPktSize::0 0 # Read request sizes (log2) 127system.physmem.readPktSize::1 0 # Read request sizes (log2) 128system.physmem.readPktSize::2 9731 # Read request sizes (log2) 129system.physmem.readPktSize::3 28 # Read request sizes (log2) 130system.physmem.readPktSize::4 0 # Read request sizes (log2) 131system.physmem.readPktSize::5 0 # Read request sizes (log2) 132system.physmem.readPktSize::6 189561 # Read request sizes (log2) 133system.physmem.writePktSize::0 0 # Write request sizes (log2) 134system.physmem.writePktSize::1 0 # Write request sizes (log2) 135system.physmem.writePktSize::2 4391 # Write request sizes (log2) 136system.physmem.writePktSize::3 0 # Write request sizes (log2) 137system.physmem.writePktSize::4 0 # Write request sizes (log2) 138system.physmem.writePktSize::5 0 # Write request sizes (log2) 139system.physmem.writePktSize::6 136511 # Write request sizes (log2) 140system.physmem.rdQLenPdf::0 138723 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::1 15961 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::2 10493 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::3 8947 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::4 7139 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::5 5591 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::6 4693 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::7 3946 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::8 3444 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::9 97 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::10 69 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::11 37 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::12 18 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::13 8 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::14 3 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 172system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::15 2740 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::16 3251 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::17 4887 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::18 5950 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::19 6428 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::20 6725 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::21 6970 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::22 8417 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::23 8666 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::24 9995 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::25 9375 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::26 9280 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::27 8482 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::28 8751 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::29 10022 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::30 8140 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::31 7549 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::32 7221 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::33 312 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::34 261 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::35 257 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::36 214 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::37 148 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::38 179 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::39 159 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::40 188 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::41 159 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::42 161 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::43 129 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::44 140 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::45 117 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::46 153 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::47 129 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::48 139 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::49 101 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::50 89 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::51 101 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::52 88 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::53 97 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::54 62 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::55 114 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::56 81 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::57 62 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::58 71 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::59 71 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::60 77 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::61 62 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::62 90 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::63 131 # What write queue length does an incoming req see 236system.physmem.bytesPerActivate::samples 88863 # Bytes accessed per row activation 237system.physmem.bytesPerActivate::mean 242.097791 # Bytes accessed per row activation 238system.physmem.bytesPerActivate::gmean 137.224347 # Bytes accessed per row activation 239system.physmem.bytesPerActivate::stdev 303.120448 # Bytes accessed per row activation 240system.physmem.bytesPerActivate::0-127 46751 52.61% 52.61% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::128-255 18086 20.35% 72.96% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::256-383 6032 6.79% 79.75% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::384-511 3695 4.16% 83.91% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::512-639 2426 2.73% 86.64% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::640-767 1553 1.75% 88.39% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::768-895 1048 1.18% 89.57% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::896-1023 926 1.04% 90.61% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::1024-1151 8346 9.39% 100.00% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::total 88863 # Bytes accessed per row activation 250system.physmem.rdPerTurnAround::samples 6835 # Reads before turning the bus around for writes 251system.physmem.rdPerTurnAround::mean 29.139722 # Reads before turning the bus around for writes 252system.physmem.rdPerTurnAround::stdev 544.203282 # Reads before turning the bus around for writes 253system.physmem.rdPerTurnAround::0-2047 6833 99.97% 99.97% # Reads before turning the bus around for writes 254system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes 255system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::total 6835 # Reads before turning the bus around for writes 257system.physmem.wrPerTurnAround::samples 6835 # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::mean 20.040819 # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::gmean 18.588322 # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::stdev 11.942463 # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::16-19 5790 84.71% 84.71% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::20-23 288 4.21% 88.92% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::24-27 181 2.65% 91.57% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::28-31 61 0.89% 92.47% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::32-35 66 0.97% 93.43% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::36-39 161 2.36% 95.79% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::40-43 22 0.32% 96.11% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::44-47 10 0.15% 96.25% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::48-51 10 0.15% 96.40% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::52-55 9 0.13% 96.53% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::56-59 9 0.13% 96.66% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::60-63 11 0.16% 96.83% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::64-67 163 2.38% 99.21% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::68-71 7 0.10% 99.31% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::72-75 5 0.07% 99.39% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::76-79 8 0.12% 99.50% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::80-83 6 0.09% 99.59% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::84-87 1 0.01% 99.60% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::88-91 3 0.04% 99.65% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::100-103 1 0.01% 99.66% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::124-127 1 0.01% 99.68% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::128-131 13 0.19% 99.87% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::132-135 2 0.03% 99.90% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::156-159 1 0.01% 99.91% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::164-167 4 0.06% 99.97% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::176-179 2 0.03% 100.00% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::total 6835 # Writes before turning the bus around for reads 288system.physmem.totQLat 4713712824 # Total ticks spent queuing 289system.physmem.totMemAccLat 8448169074 # Total ticks spent from burst creation until serviced by the DRAM 290system.physmem.totBusLat 995855000 # Total ticks spent in databus transfers 291system.physmem.avgQLat 23666.66 # Average queueing delay per DRAM burst 292system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 293system.physmem.avgMemAccLat 42416.66 # Average memory access latency per DRAM burst 294system.physmem.avgRdBW 4.44 # Average DRAM read bandwidth in MiByte/s 295system.physmem.avgWrBW 3.06 # Average achieved write bandwidth in MiByte/s 296system.physmem.avgRdBWSys 4.24 # Average system read bandwidth in MiByte/s 297system.physmem.avgWrBWSys 3.05 # Average system write bandwidth in MiByte/s 298system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 299system.physmem.busUtil 0.06 # Data bus utilization in percentage 300system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 301system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 302system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing 303system.physmem.avgWrQLen 27.14 # Average write queue length when enqueuing 304system.physmem.readRowHits 166377 # Number of row buffer hits during reads 305system.physmem.writeRowHits 80909 # Number of row buffer hits during writes 306system.physmem.readRowHitRate 83.53 # Row buffer hit rate for reads 307system.physmem.writeRowHitRate 59.06 # Row buffer hit rate for writes 308system.physmem.avgGap 8431906.54 # Average gap between requests 309system.physmem.pageHitRate 73.56 # Row buffer hit rate, read and write combined 310system.physmem_0.actEnergy 348886440 # Energy for activate commands per rank (pJ) 311system.physmem_0.preEnergy 190364625 # Energy for precharge commands per rank (pJ) 312system.physmem_0.readEnergy 827283600 # Energy for read commands per rank (pJ) 313system.physmem_0.writeEnergy 458148960 # Energy for write commands per rank (pJ) 314system.physmem_0.refreshEnergy 187370795040 # Energy for refresh commands per rank (pJ) 315system.physmem_0.actBackEnergy 84523956795 # Energy for active background per rank (pJ) 316system.physmem_0.preBackEnergy 1647087865500 # Energy for precharge background per rank (pJ) 317system.physmem_0.totalEnergy 1920807300960 # Total energy per rank (pJ) 318system.physmem_0.averagePower 669.569582 # Core power per rank (mW) 319system.physmem_0.memoryStateTime::IDLE 2739939393002 # Time in different power states 320system.physmem_0.memoryStateTime::REF 95792840000 # Time in different power states 321system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 322system.physmem_0.memoryStateTime::ACT 32988240498 # Time in different power states 323system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 324system.physmem_1.actEnergy 322917840 # Energy for activate commands per rank (pJ) 325system.physmem_1.preEnergy 176195250 # Energy for precharge commands per rank (pJ) 326system.physmem_1.readEnergy 726242400 # Energy for read commands per rank (pJ) 327system.physmem_1.writeEnergy 429474960 # Energy for write commands per rank (pJ) 328system.physmem_1.refreshEnergy 187370795040 # Energy for refresh commands per rank (pJ) 329system.physmem_1.actBackEnergy 83768933655 # Energy for active background per rank (pJ) 330system.physmem_1.preBackEnergy 1647750166500 # Energy for precharge background per rank (pJ) 331system.physmem_1.totalEnergy 1920544725645 # Total energy per rank (pJ) 332system.physmem_1.averagePower 669.478051 # Core power per rank (mW) 333system.physmem_1.memoryStateTime::IDLE 2741046257852 # Time in different power states 334system.physmem_1.memoryStateTime::REF 95792840000 # Time in different power states 335system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 336system.physmem_1.memoryStateTime::ACT 31880394648 # Time in different power states 337system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 338system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 339system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 340system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 341system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 342system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 343system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 344system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 345system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 346system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 347system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) 348system.realview.nvmem.bw_read::cpu1.inst 17 # Total read bandwidth from this memory (bytes/s) 349system.realview.nvmem.bw_read::total 24 # Total read bandwidth from this memory (bytes/s) 350system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) 351system.realview.nvmem.bw_inst_read::cpu1.inst 17 # Instruction read bandwidth from this memory (bytes/s) 352system.realview.nvmem.bw_inst_read::total 24 # Instruction read bandwidth from this memory (bytes/s) 353system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) 354system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s) 355system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s) 356system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 357system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 358system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 359system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 360system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 361system.cf0.dma_write_txs 631 # Number of DMA write transactions. 362system.cpu_clk_domain.clock 500 # Clock period in ticks 363system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 364system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 365system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 366system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 367system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 368system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 369system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 370system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 371system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 372system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 373system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 374system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 375system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 376system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 377system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 378system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 379system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 380system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 381system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 382system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 383system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 384system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 385system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 386system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 387system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 388system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 389system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 390system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 391system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 392system.cpu0.dtb.walker.walks 7828 # Table walker walks requested 393system.cpu0.dtb.walker.walksShort 7828 # Table walker walks initiated with short descriptors 394system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1457 # Level at which table walker walks with short descriptors terminate 395system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6371 # Level at which table walker walks with short descriptors terminate 396system.cpu0.dtb.walker.walkWaitTime::samples 7828 # Table walker wait (enqueue to first request) latency 397system.cpu0.dtb.walker.walkWaitTime::0 7828 100.00% 100.00% # Table walker wait (enqueue to first request) latency 398system.cpu0.dtb.walker.walkWaitTime::total 7828 # Table walker wait (enqueue to first request) latency 399system.cpu0.dtb.walker.walkCompletionTime::samples 6434 # Table walker service (enqueue to completion) latency 400system.cpu0.dtb.walker.walkCompletionTime::mean 10362.060926 # Table walker service (enqueue to completion) latency 401system.cpu0.dtb.walker.walkCompletionTime::gmean 9317.145265 # Table walker service (enqueue to completion) latency 402system.cpu0.dtb.walker.walkCompletionTime::stdev 5859.670820 # Table walker service (enqueue to completion) latency 403system.cpu0.dtb.walker.walkCompletionTime::0-16383 6278 97.58% 97.58% # Table walker service (enqueue to completion) latency 404system.cpu0.dtb.walker.walkCompletionTime::16384-32767 144 2.24% 99.81% # Table walker service (enqueue to completion) latency 405system.cpu0.dtb.walker.walkCompletionTime::32768-49151 7 0.11% 99.92% # Table walker service (enqueue to completion) latency 406system.cpu0.dtb.walker.walkCompletionTime::81920-98303 4 0.06% 99.98% # Table walker service (enqueue to completion) latency 407system.cpu0.dtb.walker.walkCompletionTime::212992-229375 1 0.02% 100.00% # Table walker service (enqueue to completion) latency 408system.cpu0.dtb.walker.walkCompletionTime::total 6434 # Table walker service (enqueue to completion) latency 409system.cpu0.dtb.walker.walksPending::samples 1109412500 # Table walker pending requests distribution 410system.cpu0.dtb.walker.walksPending::0 1109412500 100.00% 100.00% # Table walker pending requests distribution 411system.cpu0.dtb.walker.walksPending::total 1109412500 # Table walker pending requests distribution 412system.cpu0.dtb.walker.walkPageSizes::4K 5016 77.96% 77.96% # Table walker page sizes translated 413system.cpu0.dtb.walker.walkPageSizes::1M 1418 22.04% 100.00% # Table walker page sizes translated 414system.cpu0.dtb.walker.walkPageSizes::total 6434 # Table walker page sizes translated 415system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7828 # Table walker requests started/completed, data/inst 416system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 417system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7828 # Table walker requests started/completed, data/inst 418system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6434 # Table walker requests started/completed, data/inst 419system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 420system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6434 # Table walker requests started/completed, data/inst 421system.cpu0.dtb.walker.walkRequestOrigin::total 14262 # Table walker requests started/completed, data/inst 422system.cpu0.dtb.inst_hits 0 # ITB inst hits 423system.cpu0.dtb.inst_misses 0 # ITB inst misses 424system.cpu0.dtb.read_hits 22804186 # DTB read hits 425system.cpu0.dtb.read_misses 6713 # DTB read misses 426system.cpu0.dtb.write_hits 17553531 # DTB write hits 427system.cpu0.dtb.write_misses 1115 # DTB write misses 428system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 429system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 430system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 431system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 432system.cpu0.dtb.flush_entries 3455 # Number of entries that have been flushed from TLB 433system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 434system.cpu0.dtb.prefetch_faults 1817 # Number of TLB faults due to prefetch 435system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 436system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions 437system.cpu0.dtb.read_accesses 22810899 # DTB read accesses 438system.cpu0.dtb.write_accesses 17554646 # DTB write accesses 439system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 440system.cpu0.dtb.hits 40357717 # DTB hits 441system.cpu0.dtb.misses 7828 # DTB misses 442system.cpu0.dtb.accesses 40365545 # DTB accesses 443system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 444system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 445system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 446system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 447system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 448system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 449system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 450system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 451system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 452system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 453system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 454system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 455system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 456system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 457system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 458system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 459system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 460system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 461system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 462system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 463system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 464system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 465system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 466system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 467system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 468system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 469system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 470system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 471system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 472system.cpu0.itb.walker.walks 3348 # Table walker walks requested 473system.cpu0.itb.walker.walksShort 3348 # Table walker walks initiated with short descriptors 474system.cpu0.itb.walker.walksShortTerminationLevel::Level1 298 # Level at which table walker walks with short descriptors terminate 475system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3050 # Level at which table walker walks with short descriptors terminate 476system.cpu0.itb.walker.walkWaitTime::samples 3348 # Table walker wait (enqueue to first request) latency 477system.cpu0.itb.walker.walkWaitTime::0 3348 100.00% 100.00% # Table walker wait (enqueue to first request) latency 478system.cpu0.itb.walker.walkWaitTime::total 3348 # Table walker wait (enqueue to first request) latency 479system.cpu0.itb.walker.walkCompletionTime::samples 2332 # Table walker service (enqueue to completion) latency 480system.cpu0.itb.walker.walkCompletionTime::mean 10683.319039 # Table walker service (enqueue to completion) latency 481system.cpu0.itb.walker.walkCompletionTime::gmean 9538.524469 # Table walker service (enqueue to completion) latency 482system.cpu0.itb.walker.walkCompletionTime::stdev 5751.182189 # Table walker service (enqueue to completion) latency 483system.cpu0.itb.walker.walkCompletionTime::0-8191 887 38.04% 38.04% # Table walker service (enqueue to completion) latency 484system.cpu0.itb.walker.walkCompletionTime::8192-16383 1322 56.69% 94.73% # Table walker service (enqueue to completion) latency 485system.cpu0.itb.walker.walkCompletionTime::16384-24575 85 3.64% 98.37% # Table walker service (enqueue to completion) latency 486system.cpu0.itb.walker.walkCompletionTime::24576-32767 28 1.20% 99.57% # Table walker service (enqueue to completion) latency 487system.cpu0.itb.walker.walkCompletionTime::32768-40959 7 0.30% 99.87% # Table walker service (enqueue to completion) latency 488system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.91% # Table walker service (enqueue to completion) latency 489system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 99.96% # Table walker service (enqueue to completion) latency 490system.cpu0.itb.walker.walkCompletionTime::114688-122879 1 0.04% 100.00% # Table walker service (enqueue to completion) latency 491system.cpu0.itb.walker.walkCompletionTime::total 2332 # Table walker service (enqueue to completion) latency 492system.cpu0.itb.walker.walksPending::samples 1109040500 # Table walker pending requests distribution 493system.cpu0.itb.walker.walksPending::0 1109040500 100.00% 100.00% # Table walker pending requests distribution 494system.cpu0.itb.walker.walksPending::total 1109040500 # Table walker pending requests distribution 495system.cpu0.itb.walker.walkPageSizes::4K 2034 87.22% 87.22% # Table walker page sizes translated 496system.cpu0.itb.walker.walkPageSizes::1M 298 12.78% 100.00% # Table walker page sizes translated 497system.cpu0.itb.walker.walkPageSizes::total 2332 # Table walker page sizes translated 498system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 499system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3348 # Table walker requests started/completed, data/inst 500system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3348 # Table walker requests started/completed, data/inst 501system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 502system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2332 # Table walker requests started/completed, data/inst 503system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2332 # Table walker requests started/completed, data/inst 504system.cpu0.itb.walker.walkRequestOrigin::total 5680 # Table walker requests started/completed, data/inst 505system.cpu0.itb.inst_hits 108563333 # ITB inst hits 506system.cpu0.itb.inst_misses 3348 # ITB inst misses 507system.cpu0.itb.read_hits 0 # DTB read hits 508system.cpu0.itb.read_misses 0 # DTB read misses 509system.cpu0.itb.write_hits 0 # DTB write hits 510system.cpu0.itb.write_misses 0 # DTB write misses 511system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 512system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 513system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 514system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 515system.cpu0.itb.flush_entries 2150 # Number of entries that have been flushed from TLB 516system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 517system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 518system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 519system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 520system.cpu0.itb.read_accesses 0 # DTB read accesses 521system.cpu0.itb.write_accesses 0 # DTB write accesses 522system.cpu0.itb.inst_accesses 108566681 # ITB inst accesses 523system.cpu0.itb.hits 108563333 # DTB hits 524system.cpu0.itb.misses 3348 # DTB misses 525system.cpu0.itb.accesses 108566681 # DTB accesses 526system.cpu0.numCycles 5737441138 # number of cpu cycles simulated 527system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 528system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 529system.cpu0.committedInsts 105480509 # Number of instructions committed 530system.cpu0.committedOps 127164191 # Number of ops (including micro ops) committed 531system.cpu0.num_int_alu_accesses 112285314 # Number of integer alu accesses 532system.cpu0.num_fp_alu_accesses 9820 # Number of float alu accesses 533system.cpu0.num_func_calls 10414111 # number of times a function call or return occured 534system.cpu0.num_conditional_control_insts 14574473 # number of instructions that are conditional controls 535system.cpu0.num_int_insts 112285314 # number of integer instructions 536system.cpu0.num_fp_insts 9820 # number of float instructions 537system.cpu0.num_int_register_reads 205015592 # number of times the integer registers were read 538system.cpu0.num_int_register_writes 77505457 # number of times the integer registers were written 539system.cpu0.num_fp_register_reads 7560 # number of times the floating registers were read 540system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written 541system.cpu0.num_cc_register_reads 459494635 # number of times the CC registers were read 542system.cpu0.num_cc_register_writes 48916829 # number of times the CC registers were written 543system.cpu0.num_mem_refs 41493426 # number of memory refs 544system.cpu0.num_load_insts 23055800 # Number of load instructions 545system.cpu0.num_store_insts 18437626 # Number of store instructions 546system.cpu0.num_idle_cycles 5489199817.904087 # Number of idle cycles 547system.cpu0.num_busy_cycles 248241320.095913 # Number of busy cycles 548system.cpu0.not_idle_fraction 0.043267 # Percentage of non-idle cycles 549system.cpu0.idle_fraction 0.956733 # Percentage of idle cycles 550system.cpu0.Branches 25703635 # Number of branches fetched 551system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction 552system.cpu0.op_class::IntAlu 88750967 68.09% 68.09% # Class of executed instruction 553system.cpu0.op_class::IntMult 92819 0.07% 68.16% # Class of executed instruction 554system.cpu0.op_class::IntDiv 0 0.00% 68.16% # Class of executed instruction 555system.cpu0.op_class::FloatAdd 0 0.00% 68.16% # Class of executed instruction 556system.cpu0.op_class::FloatCmp 0 0.00% 68.16% # Class of executed instruction 557system.cpu0.op_class::FloatCvt 0 0.00% 68.16% # Class of executed instruction 558system.cpu0.op_class::FloatMult 0 0.00% 68.16% # Class of executed instruction 559system.cpu0.op_class::FloatDiv 0 0.00% 68.16% # Class of executed instruction 560system.cpu0.op_class::FloatSqrt 0 0.00% 68.16% # Class of executed instruction 561system.cpu0.op_class::SimdAdd 0 0.00% 68.16% # Class of executed instruction 562system.cpu0.op_class::SimdAddAcc 0 0.00% 68.16% # Class of executed instruction 563system.cpu0.op_class::SimdAlu 0 0.00% 68.16% # Class of executed instruction 564system.cpu0.op_class::SimdCmp 0 0.00% 68.16% # Class of executed instruction 565system.cpu0.op_class::SimdCvt 0 0.00% 68.16% # Class of executed instruction 566system.cpu0.op_class::SimdMisc 0 0.00% 68.16% # Class of executed instruction 567system.cpu0.op_class::SimdMult 0 0.00% 68.16% # Class of executed instruction 568system.cpu0.op_class::SimdMultAcc 0 0.00% 68.16% # Class of executed instruction 569system.cpu0.op_class::SimdShift 0 0.00% 68.16% # Class of executed instruction 570system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.16% # Class of executed instruction 571system.cpu0.op_class::SimdSqrt 0 0.00% 68.16% # Class of executed instruction 572system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.16% # Class of executed instruction 573system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.16% # Class of executed instruction 574system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.16% # Class of executed instruction 575system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.16% # Class of executed instruction 576system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.16% # Class of executed instruction 577system.cpu0.op_class::SimdFloatMisc 8217 0.01% 68.17% # Class of executed instruction 578system.cpu0.op_class::SimdFloatMult 0 0.00% 68.17% # Class of executed instruction 579system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.17% # Class of executed instruction 580system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.17% # Class of executed instruction 581system.cpu0.op_class::MemRead 23055800 17.69% 85.86% # Class of executed instruction 582system.cpu0.op_class::MemWrite 18437626 14.14% 100.00% # Class of executed instruction 583system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 584system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 585system.cpu0.op_class::total 130347702 # Class of executed instruction 586system.cpu0.kern.inst.arm 0 # number of arm instructions executed 587system.cpu0.kern.inst.quiesce 1862 # number of quiesce instructions executed 588system.cpu0.dcache.tags.replacements 694931 # number of replacements 589system.cpu0.dcache.tags.tagsinuse 494.123274 # Cycle average of tags in use 590system.cpu0.dcache.tags.total_refs 39503506 # Total number of references to valid blocks. 591system.cpu0.dcache.tags.sampled_refs 695443 # Sample count of references to valid blocks. 592system.cpu0.dcache.tags.avg_refs 56.803370 # Average number of references to valid blocks. 593system.cpu0.dcache.tags.warmup_cycle 1135131000 # Cycle when the warmup percentage was hit. 594system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.123274 # Average occupied blocks per requestor 595system.cpu0.dcache.tags.occ_percent::cpu0.data 0.965085 # Average percentage of cache occupancy 596system.cpu0.dcache.tags.occ_percent::total 0.965085 # Average percentage of cache occupancy 597system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 598system.cpu0.dcache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id 599system.cpu0.dcache.tags.age_task_id_blocks_1024::1 319 # Occupied blocks per task id 600system.cpu0.dcache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id 601system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 602system.cpu0.dcache.tags.tag_accesses 81393420 # Number of tag accesses 603system.cpu0.dcache.tags.data_accesses 81393420 # Number of data accesses 604system.cpu0.dcache.ReadReq_hits::cpu0.data 21551304 # number of ReadReq hits 605system.cpu0.dcache.ReadReq_hits::total 21551304 # number of ReadReq hits 606system.cpu0.dcache.WriteReq_hits::cpu0.data 16831338 # number of WriteReq hits 607system.cpu0.dcache.WriteReq_hits::total 16831338 # number of WriteReq hits 608system.cpu0.dcache.SoftPFReq_hits::cpu0.data 318322 # number of SoftPFReq hits 609system.cpu0.dcache.SoftPFReq_hits::total 318322 # number of SoftPFReq hits 610system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365658 # number of LoadLockedReq hits 611system.cpu0.dcache.LoadLockedReq_hits::total 365658 # number of LoadLockedReq hits 612system.cpu0.dcache.StoreCondReq_hits::cpu0.data 362750 # number of StoreCondReq hits 613system.cpu0.dcache.StoreCondReq_hits::total 362750 # number of StoreCondReq hits 614system.cpu0.dcache.demand_hits::cpu0.data 38382642 # number of demand (read+write) hits 615system.cpu0.dcache.demand_hits::total 38382642 # number of demand (read+write) hits 616system.cpu0.dcache.overall_hits::cpu0.data 38700964 # number of overall hits 617system.cpu0.dcache.overall_hits::total 38700964 # number of overall hits 618system.cpu0.dcache.ReadReq_misses::cpu0.data 398253 # number of ReadReq misses 619system.cpu0.dcache.ReadReq_misses::total 398253 # number of ReadReq misses 620system.cpu0.dcache.WriteReq_misses::cpu0.data 324071 # number of WriteReq misses 621system.cpu0.dcache.WriteReq_misses::total 324071 # number of WriteReq misses 622system.cpu0.dcache.SoftPFReq_misses::cpu0.data 128299 # number of SoftPFReq misses 623system.cpu0.dcache.SoftPFReq_misses::total 128299 # number of SoftPFReq misses 624system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21791 # number of LoadLockedReq misses 625system.cpu0.dcache.LoadLockedReq_misses::total 21791 # number of LoadLockedReq misses 626system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19751 # number of StoreCondReq misses 627system.cpu0.dcache.StoreCondReq_misses::total 19751 # number of StoreCondReq misses 628system.cpu0.dcache.demand_misses::cpu0.data 722324 # number of demand (read+write) misses 629system.cpu0.dcache.demand_misses::total 722324 # number of demand (read+write) misses 630system.cpu0.dcache.overall_misses::cpu0.data 850623 # number of overall misses 631system.cpu0.dcache.overall_misses::total 850623 # number of overall misses 632system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5056802000 # number of ReadReq miss cycles 633system.cpu0.dcache.ReadReq_miss_latency::total 5056802000 # number of ReadReq miss cycles 634system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5106772500 # number of WriteReq miss cycles 635system.cpu0.dcache.WriteReq_miss_latency::total 5106772500 # number of WriteReq miss cycles 636system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 332740500 # number of LoadLockedReq miss cycles 637system.cpu0.dcache.LoadLockedReq_miss_latency::total 332740500 # number of LoadLockedReq miss cycles 638system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 437773500 # number of StoreCondReq miss cycles 639system.cpu0.dcache.StoreCondReq_miss_latency::total 437773500 # number of StoreCondReq miss cycles 640system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1801500 # number of StoreCondFailReq miss cycles 641system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1801500 # number of StoreCondFailReq miss cycles 642system.cpu0.dcache.demand_miss_latency::cpu0.data 10163574500 # number of demand (read+write) miss cycles 643system.cpu0.dcache.demand_miss_latency::total 10163574500 # number of demand (read+write) miss cycles 644system.cpu0.dcache.overall_miss_latency::cpu0.data 10163574500 # number of overall miss cycles 645system.cpu0.dcache.overall_miss_latency::total 10163574500 # number of overall miss cycles 646system.cpu0.dcache.ReadReq_accesses::cpu0.data 21949557 # number of ReadReq accesses(hits+misses) 647system.cpu0.dcache.ReadReq_accesses::total 21949557 # number of ReadReq accesses(hits+misses) 648system.cpu0.dcache.WriteReq_accesses::cpu0.data 17155409 # number of WriteReq accesses(hits+misses) 649system.cpu0.dcache.WriteReq_accesses::total 17155409 # number of WriteReq accesses(hits+misses) 650system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446621 # number of SoftPFReq accesses(hits+misses) 651system.cpu0.dcache.SoftPFReq_accesses::total 446621 # number of SoftPFReq accesses(hits+misses) 652system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 387449 # number of LoadLockedReq accesses(hits+misses) 653system.cpu0.dcache.LoadLockedReq_accesses::total 387449 # number of LoadLockedReq accesses(hits+misses) 654system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 382501 # number of StoreCondReq accesses(hits+misses) 655system.cpu0.dcache.StoreCondReq_accesses::total 382501 # number of StoreCondReq accesses(hits+misses) 656system.cpu0.dcache.demand_accesses::cpu0.data 39104966 # number of demand (read+write) accesses 657system.cpu0.dcache.demand_accesses::total 39104966 # number of demand (read+write) accesses 658system.cpu0.dcache.overall_accesses::cpu0.data 39551587 # number of overall (read+write) accesses 659system.cpu0.dcache.overall_accesses::total 39551587 # number of overall (read+write) accesses 660system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.018144 # miss rate for ReadReq accesses 661system.cpu0.dcache.ReadReq_miss_rate::total 0.018144 # miss rate for ReadReq accesses 662system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018890 # miss rate for WriteReq accesses 663system.cpu0.dcache.WriteReq_miss_rate::total 0.018890 # miss rate for WriteReq accesses 664system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.287266 # miss rate for SoftPFReq accesses 665system.cpu0.dcache.SoftPFReq_miss_rate::total 0.287266 # miss rate for SoftPFReq accesses 666system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056242 # miss rate for LoadLockedReq accesses 667system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056242 # miss rate for LoadLockedReq accesses 668system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051636 # miss rate for StoreCondReq accesses 669system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051636 # miss rate for StoreCondReq accesses 670system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018471 # miss rate for demand accesses 671system.cpu0.dcache.demand_miss_rate::total 0.018471 # miss rate for demand accesses 672system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021507 # miss rate for overall accesses 673system.cpu0.dcache.overall_miss_rate::total 0.021507 # miss rate for overall accesses 674system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12697.461162 # average ReadReq miss latency 675system.cpu0.dcache.ReadReq_avg_miss_latency::total 12697.461162 # average ReadReq miss latency 676system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15758.190335 # average WriteReq miss latency 677system.cpu0.dcache.WriteReq_avg_miss_latency::total 15758.190335 # average WriteReq miss latency 678system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15269.629664 # average LoadLockedReq miss latency 679system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15269.629664 # average LoadLockedReq miss latency 680system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22164.624576 # average StoreCondReq miss latency 681system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22164.624576 # average StoreCondReq miss latency 682system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 683system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 684system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14070.658735 # average overall miss latency 685system.cpu0.dcache.demand_avg_miss_latency::total 14070.658735 # average overall miss latency 686system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 11948.389004 # average overall miss latency 687system.cpu0.dcache.overall_avg_miss_latency::total 11948.389004 # average overall miss latency 688system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 689system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 690system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 691system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 692system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 693system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 694system.cpu0.dcache.fast_writes 0 # number of fast writes performed 695system.cpu0.dcache.cache_copies 0 # number of cache copies performed 696system.cpu0.dcache.writebacks::writebacks 507088 # number of writebacks 697system.cpu0.dcache.writebacks::total 507088 # number of writebacks 698system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25317 # number of ReadReq MSHR hits 699system.cpu0.dcache.ReadReq_mshr_hits::total 25317 # number of ReadReq MSHR hits 700system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15125 # number of LoadLockedReq MSHR hits 701system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15125 # number of LoadLockedReq MSHR hits 702system.cpu0.dcache.demand_mshr_hits::cpu0.data 25317 # number of demand (read+write) MSHR hits 703system.cpu0.dcache.demand_mshr_hits::total 25317 # number of demand (read+write) MSHR hits 704system.cpu0.dcache.overall_mshr_hits::cpu0.data 25317 # number of overall MSHR hits 705system.cpu0.dcache.overall_mshr_hits::total 25317 # number of overall MSHR hits 706system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 372936 # number of ReadReq MSHR misses 707system.cpu0.dcache.ReadReq_mshr_misses::total 372936 # number of ReadReq MSHR misses 708system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 324071 # number of WriteReq MSHR misses 709system.cpu0.dcache.WriteReq_mshr_misses::total 324071 # number of WriteReq MSHR misses 710system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 100997 # number of SoftPFReq MSHR misses 711system.cpu0.dcache.SoftPFReq_mshr_misses::total 100997 # number of SoftPFReq MSHR misses 712system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6666 # number of LoadLockedReq MSHR misses 713system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6666 # number of LoadLockedReq MSHR misses 714system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19751 # number of StoreCondReq MSHR misses 715system.cpu0.dcache.StoreCondReq_mshr_misses::total 19751 # number of StoreCondReq MSHR misses 716system.cpu0.dcache.demand_mshr_misses::cpu0.data 697007 # number of demand (read+write) MSHR misses 717system.cpu0.dcache.demand_mshr_misses::total 697007 # number of demand (read+write) MSHR misses 718system.cpu0.dcache.overall_mshr_misses::cpu0.data 798004 # number of overall MSHR misses 719system.cpu0.dcache.overall_mshr_misses::total 798004 # number of overall MSHR misses 720system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 21110 # number of ReadReq MSHR uncacheable 721system.cpu0.dcache.ReadReq_mshr_uncacheable::total 21110 # number of ReadReq MSHR uncacheable 722system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 19686 # number of WriteReq MSHR uncacheable 723system.cpu0.dcache.WriteReq_mshr_uncacheable::total 19686 # number of WriteReq MSHR uncacheable 724system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 40796 # number of overall MSHR uncacheable misses 725system.cpu0.dcache.overall_mshr_uncacheable_misses::total 40796 # number of overall MSHR uncacheable misses 726system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4291277500 # number of ReadReq MSHR miss cycles 727system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4291277500 # number of ReadReq MSHR miss cycles 728system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4782701500 # number of WriteReq MSHR miss cycles 729system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4782701500 # number of WriteReq MSHR miss cycles 730system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1606991500 # number of SoftPFReq MSHR miss cycles 731system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1606991500 # number of SoftPFReq MSHR miss cycles 732system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 101428000 # number of LoadLockedReq MSHR miss cycles 733system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 101428000 # number of LoadLockedReq MSHR miss cycles 734system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 418075500 # number of StoreCondReq MSHR miss cycles 735system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 418075500 # number of StoreCondReq MSHR miss cycles 736system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1748500 # number of StoreCondFailReq MSHR miss cycles 737system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1748500 # number of StoreCondFailReq MSHR miss cycles 738system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9073979000 # number of demand (read+write) MSHR miss cycles 739system.cpu0.dcache.demand_mshr_miss_latency::total 9073979000 # number of demand (read+write) MSHR miss cycles 740system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10680970500 # number of overall MSHR miss cycles 741system.cpu0.dcache.overall_mshr_miss_latency::total 10680970500 # number of overall MSHR miss cycles 742system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4433767500 # number of ReadReq MSHR uncacheable cycles 743system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4433767500 # number of ReadReq MSHR uncacheable cycles 744system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3394597500 # number of WriteReq MSHR uncacheable cycles 745system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3394597500 # number of WriteReq MSHR uncacheable cycles 746system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7828365000 # number of overall MSHR uncacheable cycles 747system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7828365000 # number of overall MSHR uncacheable cycles 748system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016991 # mshr miss rate for ReadReq accesses 749system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016991 # mshr miss rate for ReadReq accesses 750system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018890 # mshr miss rate for WriteReq accesses 751system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018890 # mshr miss rate for WriteReq accesses 752system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.226136 # mshr miss rate for SoftPFReq accesses 753system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.226136 # mshr miss rate for SoftPFReq accesses 754system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017205 # mshr miss rate for LoadLockedReq accesses 755system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.017205 # mshr miss rate for LoadLockedReq accesses 756system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051636 # mshr miss rate for StoreCondReq accesses 757system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051636 # mshr miss rate for StoreCondReq accesses 758system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.017824 # mshr miss rate for demand accesses 759system.cpu0.dcache.demand_mshr_miss_rate::total 0.017824 # mshr miss rate for demand accesses 760system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020176 # mshr miss rate for overall accesses 761system.cpu0.dcache.overall_mshr_miss_rate::total 0.020176 # mshr miss rate for overall accesses 762system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11506.739762 # average ReadReq mshr miss latency 763system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11506.739762 # average ReadReq mshr miss latency 764system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 14758.190335 # average WriteReq mshr miss latency 765system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14758.190335 # average WriteReq mshr miss latency 766system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15911.279543 # average SoftPFReq mshr miss latency 767system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15911.279543 # average SoftPFReq mshr miss latency 768system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15215.721572 # average LoadLockedReq mshr miss latency 769system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15215.721572 # average LoadLockedReq mshr miss latency 770system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21167.307984 # average StoreCondReq mshr miss latency 771system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21167.307984 # average StoreCondReq mshr miss latency 772system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 773system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 774system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13018.490489 # average overall mshr miss latency 775system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13018.490489 # average overall mshr miss latency 776system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13384.607721 # average overall mshr miss latency 777system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13384.607721 # average overall mshr miss latency 778system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210031.620085 # average ReadReq mshr uncacheable latency 779system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 210031.620085 # average ReadReq mshr uncacheable latency 780system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 172437.138068 # average WriteReq mshr uncacheable latency 781system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 172437.138068 # average WriteReq mshr uncacheable latency 782system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 191890.503971 # average overall mshr uncacheable latency 783system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 191890.503971 # average overall mshr uncacheable latency 784system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 785system.cpu0.icache.tags.replacements 1106064 # number of replacements 786system.cpu0.icache.tags.tagsinuse 511.455953 # Cycle average of tags in use 787system.cpu0.icache.tags.total_refs 107456748 # Total number of references to valid blocks. 788system.cpu0.icache.tags.sampled_refs 1106576 # Sample count of references to valid blocks. 789system.cpu0.icache.tags.avg_refs 97.107427 # Average number of references to valid blocks. 790system.cpu0.icache.tags.warmup_cycle 13496677000 # Cycle when the warmup percentage was hit. 791system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.455953 # Average occupied blocks per requestor 792system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998937 # Average percentage of cache occupancy 793system.cpu0.icache.tags.occ_percent::total 0.998937 # Average percentage of cache occupancy 794system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 795system.cpu0.icache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id 796system.cpu0.icache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id 797system.cpu0.icache.tags.age_task_id_blocks_1024::2 214 # Occupied blocks per task id 798system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 799system.cpu0.icache.tags.tag_accesses 218233251 # Number of tag accesses 800system.cpu0.icache.tags.data_accesses 218233251 # Number of data accesses 801system.cpu0.icache.ReadReq_hits::cpu0.inst 107456748 # number of ReadReq hits 802system.cpu0.icache.ReadReq_hits::total 107456748 # number of ReadReq hits 803system.cpu0.icache.demand_hits::cpu0.inst 107456748 # number of demand (read+write) hits 804system.cpu0.icache.demand_hits::total 107456748 # number of demand (read+write) hits 805system.cpu0.icache.overall_hits::cpu0.inst 107456748 # number of overall hits 806system.cpu0.icache.overall_hits::total 107456748 # number of overall hits 807system.cpu0.icache.ReadReq_misses::cpu0.inst 1106585 # number of ReadReq misses 808system.cpu0.icache.ReadReq_misses::total 1106585 # number of ReadReq misses 809system.cpu0.icache.demand_misses::cpu0.inst 1106585 # number of demand (read+write) misses 810system.cpu0.icache.demand_misses::total 1106585 # number of demand (read+write) misses 811system.cpu0.icache.overall_misses::cpu0.inst 1106585 # number of overall misses 812system.cpu0.icache.overall_misses::total 1106585 # number of overall misses 813system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10879255500 # number of ReadReq miss cycles 814system.cpu0.icache.ReadReq_miss_latency::total 10879255500 # number of ReadReq miss cycles 815system.cpu0.icache.demand_miss_latency::cpu0.inst 10879255500 # number of demand (read+write) miss cycles 816system.cpu0.icache.demand_miss_latency::total 10879255500 # number of demand (read+write) miss cycles 817system.cpu0.icache.overall_miss_latency::cpu0.inst 10879255500 # number of overall miss cycles 818system.cpu0.icache.overall_miss_latency::total 10879255500 # number of overall miss cycles 819system.cpu0.icache.ReadReq_accesses::cpu0.inst 108563333 # number of ReadReq accesses(hits+misses) 820system.cpu0.icache.ReadReq_accesses::total 108563333 # number of ReadReq accesses(hits+misses) 821system.cpu0.icache.demand_accesses::cpu0.inst 108563333 # number of demand (read+write) accesses 822system.cpu0.icache.demand_accesses::total 108563333 # number of demand (read+write) accesses 823system.cpu0.icache.overall_accesses::cpu0.inst 108563333 # number of overall (read+write) accesses 824system.cpu0.icache.overall_accesses::total 108563333 # number of overall (read+write) accesses 825system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010193 # miss rate for ReadReq accesses 826system.cpu0.icache.ReadReq_miss_rate::total 0.010193 # miss rate for ReadReq accesses 827system.cpu0.icache.demand_miss_rate::cpu0.inst 0.010193 # miss rate for demand accesses 828system.cpu0.icache.demand_miss_rate::total 0.010193 # miss rate for demand accesses 829system.cpu0.icache.overall_miss_rate::cpu0.inst 0.010193 # miss rate for overall accesses 830system.cpu0.icache.overall_miss_rate::total 0.010193 # miss rate for overall accesses 831system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9831.378069 # average ReadReq miss latency 832system.cpu0.icache.ReadReq_avg_miss_latency::total 9831.378069 # average ReadReq miss latency 833system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9831.378069 # average overall miss latency 834system.cpu0.icache.demand_avg_miss_latency::total 9831.378069 # average overall miss latency 835system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9831.378069 # average overall miss latency 836system.cpu0.icache.overall_avg_miss_latency::total 9831.378069 # average overall miss latency 837system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 838system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 839system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 840system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 841system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 842system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 843system.cpu0.icache.fast_writes 0 # number of fast writes performed 844system.cpu0.icache.cache_copies 0 # number of cache copies performed 845system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1106585 # number of ReadReq MSHR misses 846system.cpu0.icache.ReadReq_mshr_misses::total 1106585 # number of ReadReq MSHR misses 847system.cpu0.icache.demand_mshr_misses::cpu0.inst 1106585 # number of demand (read+write) MSHR misses 848system.cpu0.icache.demand_mshr_misses::total 1106585 # number of demand (read+write) MSHR misses 849system.cpu0.icache.overall_mshr_misses::cpu0.inst 1106585 # number of overall MSHR misses 850system.cpu0.icache.overall_mshr_misses::total 1106585 # number of overall MSHR misses 851system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable 852system.cpu0.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable 853system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses 854system.cpu0.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses 855system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10325963000 # number of ReadReq MSHR miss cycles 856system.cpu0.icache.ReadReq_mshr_miss_latency::total 10325963000 # number of ReadReq MSHR miss cycles 857system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10325963000 # number of demand (read+write) MSHR miss cycles 858system.cpu0.icache.demand_mshr_miss_latency::total 10325963000 # number of demand (read+write) MSHR miss cycles 859system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10325963000 # number of overall MSHR miss cycles 860system.cpu0.icache.overall_mshr_miss_latency::total 10325963000 # number of overall MSHR miss cycles 861system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 800795500 # number of ReadReq MSHR uncacheable cycles 862system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 800795500 # number of ReadReq MSHR uncacheable cycles 863system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 800795500 # number of overall MSHR uncacheable cycles 864system.cpu0.icache.overall_mshr_uncacheable_latency::total 800795500 # number of overall MSHR uncacheable cycles 865system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010193 # mshr miss rate for ReadReq accesses 866system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010193 # mshr miss rate for ReadReq accesses 867system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010193 # mshr miss rate for demand accesses 868system.cpu0.icache.demand_mshr_miss_rate::total 0.010193 # mshr miss rate for demand accesses 869system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.010193 # mshr miss rate for overall accesses 870system.cpu0.icache.overall_mshr_miss_rate::total 0.010193 # mshr miss rate for overall accesses 871system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9331.378069 # average ReadReq mshr miss latency 872system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9331.378069 # average ReadReq mshr miss latency 873system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9331.378069 # average overall mshr miss latency 874system.cpu0.icache.demand_avg_mshr_miss_latency::total 9331.378069 # average overall mshr miss latency 875system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9331.378069 # average overall mshr miss latency 876system.cpu0.icache.overall_avg_mshr_miss_latency::total 9331.378069 # average overall mshr miss latency 877system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88760.308136 # average ReadReq mshr uncacheable latency 878system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88760.308136 # average ReadReq mshr uncacheable latency 879system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88760.308136 # average overall mshr uncacheable latency 880system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88760.308136 # average overall mshr uncacheable latency 881system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 882system.cpu0.l2cache.prefetcher.num_hwpf_issued 1850657 # number of hwpf issued 883system.cpu0.l2cache.prefetcher.pfIdentified 1850711 # number of prefetch candidates identified 884system.cpu0.l2cache.prefetcher.pfBufferHit 45 # number of redundant prefetches already in prefetch queue 885system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 886system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 887system.cpu0.l2cache.prefetcher.pfSpanPage 237577 # number of prefetches not generated due to page crossing 888system.cpu0.l2cache.tags.replacements 266648 # number of replacements 889system.cpu0.l2cache.tags.tagsinuse 16090.167348 # Cycle average of tags in use 890system.cpu0.l2cache.tags.total_refs 3241094 # Total number of references to valid blocks. 891system.cpu0.l2cache.tags.sampled_refs 282873 # Sample count of references to valid blocks. 892system.cpu0.l2cache.tags.avg_refs 11.457771 # Average number of references to valid blocks. 893system.cpu0.l2cache.tags.warmup_cycle 2844827650500 # Cycle when the warmup percentage was hit. 894system.cpu0.l2cache.tags.occ_blocks::writebacks 7840.907632 # Average occupied blocks per requestor 895system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 1.369036 # Average occupied blocks per requestor 896system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.138555 # Average occupied blocks per requestor 897system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4562.781634 # Average occupied blocks per requestor 898system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1957.525775 # Average occupied blocks per requestor 899system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1727.444715 # Average occupied blocks per requestor 900system.cpu0.l2cache.tags.occ_percent::writebacks 0.478571 # Average percentage of cache occupancy 901system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000084 # Average percentage of cache occupancy 902system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000008 # Average percentage of cache occupancy 903system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.278490 # Average percentage of cache occupancy 904system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.119478 # Average percentage of cache occupancy 905system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.105435 # Average percentage of cache occupancy 906system.cpu0.l2cache.tags.occ_percent::total 0.982066 # Average percentage of cache occupancy 907system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1088 # Occupied blocks per task id 908system.cpu0.l2cache.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id 909system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15130 # Occupied blocks per task id 910system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 11 # Occupied blocks per task id 911system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 286 # Occupied blocks per task id 912system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 359 # Occupied blocks per task id 913system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 432 # Occupied blocks per task id 914system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id 915system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id 916system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id 917system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 118 # Occupied blocks per task id 918system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3231 # Occupied blocks per task id 919system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7855 # Occupied blocks per task id 920system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3884 # Occupied blocks per task id 921system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.066406 # Percentage of cache occupancy per task id 922system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000427 # Percentage of cache occupancy per task id 923system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.923462 # Percentage of cache occupancy per task id 924system.cpu0.l2cache.tags.tag_accesses 60109727 # Number of tag accesses 925system.cpu0.l2cache.tags.data_accesses 60109727 # Number of data accesses 926system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 8002 # number of ReadReq hits 927system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3594 # number of ReadReq hits 928system.cpu0.l2cache.ReadReq_hits::total 11596 # number of ReadReq hits 929system.cpu0.l2cache.Writeback_hits::writebacks 507087 # number of Writeback hits 930system.cpu0.l2cache.Writeback_hits::total 507087 # number of Writeback hits 931system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28350 # number of UpgradeReq hits 932system.cpu0.l2cache.UpgradeReq_hits::total 28350 # number of UpgradeReq hits 933system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1666 # number of SCUpgradeReq hits 934system.cpu0.l2cache.SCUpgradeReq_hits::total 1666 # number of SCUpgradeReq hits 935system.cpu0.l2cache.ReadExReq_hits::cpu0.data 228036 # number of ReadExReq hits 936system.cpu0.l2cache.ReadExReq_hits::total 228036 # number of ReadExReq hits 937system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1059903 # number of ReadCleanReq hits 938system.cpu0.l2cache.ReadCleanReq_hits::total 1059903 # number of ReadCleanReq hits 939system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 386161 # number of ReadSharedReq hits 940system.cpu0.l2cache.ReadSharedReq_hits::total 386161 # number of ReadSharedReq hits 941system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 8002 # number of demand (read+write) hits 942system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3594 # number of demand (read+write) hits 943system.cpu0.l2cache.demand_hits::cpu0.inst 1059903 # number of demand (read+write) hits 944system.cpu0.l2cache.demand_hits::cpu0.data 614197 # number of demand (read+write) hits 945system.cpu0.l2cache.demand_hits::total 1685696 # number of demand (read+write) hits 946system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 8002 # number of overall hits 947system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3594 # number of overall hits 948system.cpu0.l2cache.overall_hits::cpu0.inst 1059903 # number of overall hits 949system.cpu0.l2cache.overall_hits::cpu0.data 614197 # number of overall hits 950system.cpu0.l2cache.overall_hits::total 1685696 # number of overall hits 951system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 229 # number of ReadReq misses 952system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 110 # number of ReadReq misses 953system.cpu0.l2cache.ReadReq_misses::total 339 # number of ReadReq misses 954system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26033 # number of UpgradeReq misses 955system.cpu0.l2cache.UpgradeReq_misses::total 26033 # number of UpgradeReq misses 956system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18081 # number of SCUpgradeReq misses 957system.cpu0.l2cache.SCUpgradeReq_misses::total 18081 # number of SCUpgradeReq misses 958system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 4 # number of SCUpgradeFailReq misses 959system.cpu0.l2cache.SCUpgradeFailReq_misses::total 4 # number of SCUpgradeFailReq misses 960system.cpu0.l2cache.ReadExReq_misses::cpu0.data 41652 # number of ReadExReq misses 961system.cpu0.l2cache.ReadExReq_misses::total 41652 # number of ReadExReq misses 962system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 46682 # number of ReadCleanReq misses 963system.cpu0.l2cache.ReadCleanReq_misses::total 46682 # number of ReadCleanReq misses 964system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 94438 # number of ReadSharedReq misses 965system.cpu0.l2cache.ReadSharedReq_misses::total 94438 # number of ReadSharedReq misses 966system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 229 # number of demand (read+write) misses 967system.cpu0.l2cache.demand_misses::cpu0.itb.walker 110 # number of demand (read+write) misses 968system.cpu0.l2cache.demand_misses::cpu0.inst 46682 # number of demand (read+write) misses 969system.cpu0.l2cache.demand_misses::cpu0.data 136090 # number of demand (read+write) misses 970system.cpu0.l2cache.demand_misses::total 183111 # number of demand (read+write) misses 971system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 229 # number of overall misses 972system.cpu0.l2cache.overall_misses::cpu0.itb.walker 110 # number of overall misses 973system.cpu0.l2cache.overall_misses::cpu0.inst 46682 # number of overall misses 974system.cpu0.l2cache.overall_misses::cpu0.data 136090 # number of overall misses 975system.cpu0.l2cache.overall_misses::total 183111 # number of overall misses 976system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 5419000 # number of ReadReq miss cycles 977system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2507000 # number of ReadReq miss cycles 978system.cpu0.l2cache.ReadReq_miss_latency::total 7926000 # number of ReadReq miss cycles 979system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 480959500 # number of UpgradeReq miss cycles 980system.cpu0.l2cache.UpgradeReq_miss_latency::total 480959500 # number of UpgradeReq miss cycles 981system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 368223000 # number of SCUpgradeReq miss cycles 982system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 368223000 # number of SCUpgradeReq miss cycles 983system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1666996 # number of SCUpgradeFailReq miss cycles 984system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1666996 # number of SCUpgradeFailReq miss cycles 985system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 1951085500 # number of ReadExReq miss cycles 986system.cpu0.l2cache.ReadExReq_miss_latency::total 1951085500 # number of ReadExReq miss cycles 987system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 2317097000 # number of ReadCleanReq miss cycles 988system.cpu0.l2cache.ReadCleanReq_miss_latency::total 2317097000 # number of ReadCleanReq miss cycles 989system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 2767769000 # number of ReadSharedReq miss cycles 990system.cpu0.l2cache.ReadSharedReq_miss_latency::total 2767769000 # number of ReadSharedReq miss cycles 991system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 5419000 # number of demand (read+write) miss cycles 992system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2507000 # number of demand (read+write) miss cycles 993system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2317097000 # number of demand (read+write) miss cycles 994system.cpu0.l2cache.demand_miss_latency::cpu0.data 4718854500 # number of demand (read+write) miss cycles 995system.cpu0.l2cache.demand_miss_latency::total 7043877500 # number of demand (read+write) miss cycles 996system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 5419000 # number of overall miss cycles 997system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2507000 # number of overall miss cycles 998system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2317097000 # number of overall miss cycles 999system.cpu0.l2cache.overall_miss_latency::cpu0.data 4718854500 # number of overall miss cycles 1000system.cpu0.l2cache.overall_miss_latency::total 7043877500 # number of overall miss cycles 1001system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 8231 # number of ReadReq accesses(hits+misses) 1002system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3704 # number of ReadReq accesses(hits+misses) 1003system.cpu0.l2cache.ReadReq_accesses::total 11935 # number of ReadReq accesses(hits+misses) 1004system.cpu0.l2cache.Writeback_accesses::writebacks 507087 # number of Writeback accesses(hits+misses) 1005system.cpu0.l2cache.Writeback_accesses::total 507087 # number of Writeback accesses(hits+misses) 1006system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 54383 # number of UpgradeReq accesses(hits+misses) 1007system.cpu0.l2cache.UpgradeReq_accesses::total 54383 # number of UpgradeReq accesses(hits+misses) 1008system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 19747 # number of SCUpgradeReq accesses(hits+misses) 1009system.cpu0.l2cache.SCUpgradeReq_accesses::total 19747 # number of SCUpgradeReq accesses(hits+misses) 1010system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 4 # number of SCUpgradeFailReq accesses(hits+misses) 1011system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 4 # number of SCUpgradeFailReq accesses(hits+misses) 1012system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269688 # number of ReadExReq accesses(hits+misses) 1013system.cpu0.l2cache.ReadExReq_accesses::total 269688 # number of ReadExReq accesses(hits+misses) 1014system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1106585 # number of ReadCleanReq accesses(hits+misses) 1015system.cpu0.l2cache.ReadCleanReq_accesses::total 1106585 # number of ReadCleanReq accesses(hits+misses) 1016system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 480599 # number of ReadSharedReq accesses(hits+misses) 1017system.cpu0.l2cache.ReadSharedReq_accesses::total 480599 # number of ReadSharedReq accesses(hits+misses) 1018system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 8231 # number of demand (read+write) accesses 1019system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3704 # number of demand (read+write) accesses 1020system.cpu0.l2cache.demand_accesses::cpu0.inst 1106585 # number of demand (read+write) accesses 1021system.cpu0.l2cache.demand_accesses::cpu0.data 750287 # number of demand (read+write) accesses 1022system.cpu0.l2cache.demand_accesses::total 1868807 # number of demand (read+write) accesses 1023system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 8231 # number of overall (read+write) accesses 1024system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3704 # number of overall (read+write) accesses 1025system.cpu0.l2cache.overall_accesses::cpu0.inst 1106585 # number of overall (read+write) accesses 1026system.cpu0.l2cache.overall_accesses::cpu0.data 750287 # number of overall (read+write) accesses 1027system.cpu0.l2cache.overall_accesses::total 1868807 # number of overall (read+write) accesses 1028system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.027822 # miss rate for ReadReq accesses 1029system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.029698 # miss rate for ReadReq accesses 1030system.cpu0.l2cache.ReadReq_miss_rate::total 0.028404 # miss rate for ReadReq accesses 1031system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.478697 # miss rate for UpgradeReq accesses 1032system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.478697 # miss rate for UpgradeReq accesses 1033system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.915633 # miss rate for SCUpgradeReq accesses 1034system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.915633 # miss rate for SCUpgradeReq accesses 1035system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1036system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1037system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.154445 # miss rate for ReadExReq accesses 1038system.cpu0.l2cache.ReadExReq_miss_rate::total 0.154445 # miss rate for ReadExReq accesses 1039system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.042186 # miss rate for ReadCleanReq accesses 1040system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.042186 # miss rate for ReadCleanReq accesses 1041system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.196501 # miss rate for ReadSharedReq accesses 1042system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.196501 # miss rate for ReadSharedReq accesses 1043system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.027822 # miss rate for demand accesses 1044system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.029698 # miss rate for demand accesses 1045system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.042186 # miss rate for demand accesses 1046system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.181384 # miss rate for demand accesses 1047system.cpu0.l2cache.demand_miss_rate::total 0.097983 # miss rate for demand accesses 1048system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.027822 # miss rate for overall accesses 1049system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.029698 # miss rate for overall accesses 1050system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.042186 # miss rate for overall accesses 1051system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.181384 # miss rate for overall accesses 1052system.cpu0.l2cache.overall_miss_rate::total 0.097983 # miss rate for overall accesses 1053system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 23663.755459 # average ReadReq miss latency 1054system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22790.909091 # average ReadReq miss latency 1055system.cpu0.l2cache.ReadReq_avg_miss_latency::total 23380.530973 # average ReadReq miss latency 1056system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18474.993278 # average UpgradeReq miss latency 1057system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18474.993278 # average UpgradeReq miss latency 1058system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20365.189978 # average SCUpgradeReq miss latency 1059system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20365.189978 # average SCUpgradeReq miss latency 1060system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 416749 # average SCUpgradeFailReq miss latency 1061system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 416749 # average SCUpgradeFailReq miss latency 1062system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 46842.540574 # average ReadExReq miss latency 1063system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 46842.540574 # average ReadExReq miss latency 1064system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 49635.769676 # average ReadCleanReq miss latency 1065system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 49635.769676 # average ReadCleanReq miss latency 1066system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 29307.789237 # average ReadSharedReq miss latency 1067system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 29307.789237 # average ReadSharedReq miss latency 1068system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 23663.755459 # average overall miss latency 1069system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22790.909091 # average overall miss latency 1070system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 49635.769676 # average overall miss latency 1071system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 34674.513190 # average overall miss latency 1072system.cpu0.l2cache.demand_avg_miss_latency::total 38467.800951 # average overall miss latency 1073system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 23663.755459 # average overall miss latency 1074system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22790.909091 # average overall miss latency 1075system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 49635.769676 # average overall miss latency 1076system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 34674.513190 # average overall miss latency 1077system.cpu0.l2cache.overall_avg_miss_latency::total 38467.800951 # average overall miss latency 1078system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1079system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1080system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1081system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1082system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1083system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1084system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1085system.cpu0.l2cache.cache_copies 0 # number of cache copies performed 1086system.cpu0.l2cache.writebacks::writebacks 195259 # number of writebacks 1087system.cpu0.l2cache.writebacks::total 195259 # number of writebacks 1088system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1202 # number of ReadExReq MSHR hits 1089system.cpu0.l2cache.ReadExReq_mshr_hits::total 1202 # number of ReadExReq MSHR hits 1090system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 29 # number of ReadSharedReq MSHR hits 1091system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 29 # number of ReadSharedReq MSHR hits 1092system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1231 # number of demand (read+write) MSHR hits 1093system.cpu0.l2cache.demand_mshr_hits::total 1231 # number of demand (read+write) MSHR hits 1094system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1231 # number of overall MSHR hits 1095system.cpu0.l2cache.overall_mshr_hits::total 1231 # number of overall MSHR hits 1096system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 229 # number of ReadReq MSHR misses 1097system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 110 # number of ReadReq MSHR misses 1098system.cpu0.l2cache.ReadReq_mshr_misses::total 339 # number of ReadReq MSHR misses 1099system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks 8231 # number of CleanEvict MSHR misses 1100system.cpu0.l2cache.CleanEvict_mshr_misses::total 8231 # number of CleanEvict MSHR misses 1101system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 244881 # number of HardPFReq MSHR misses 1102system.cpu0.l2cache.HardPFReq_mshr_misses::total 244881 # number of HardPFReq MSHR misses 1103system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 26033 # number of UpgradeReq MSHR misses 1104system.cpu0.l2cache.UpgradeReq_mshr_misses::total 26033 # number of UpgradeReq MSHR misses 1105system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 18081 # number of SCUpgradeReq MSHR misses 1106system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 18081 # number of SCUpgradeReq MSHR misses 1107system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 4 # number of SCUpgradeFailReq MSHR misses 1108system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 4 # number of SCUpgradeFailReq MSHR misses 1109system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 40450 # number of ReadExReq MSHR misses 1110system.cpu0.l2cache.ReadExReq_mshr_misses::total 40450 # number of ReadExReq MSHR misses 1111system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 46682 # number of ReadCleanReq MSHR misses 1112system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 46682 # number of ReadCleanReq MSHR misses 1113system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 94409 # number of ReadSharedReq MSHR misses 1114system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 94409 # number of ReadSharedReq MSHR misses 1115system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 229 # number of demand (read+write) MSHR misses 1116system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 110 # number of demand (read+write) MSHR misses 1117system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 46682 # number of demand (read+write) MSHR misses 1118system.cpu0.l2cache.demand_mshr_misses::cpu0.data 134859 # number of demand (read+write) MSHR misses 1119system.cpu0.l2cache.demand_mshr_misses::total 181880 # number of demand (read+write) MSHR misses 1120system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 229 # number of overall MSHR misses 1121system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 110 # number of overall MSHR misses 1122system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 46682 # number of overall MSHR misses 1123system.cpu0.l2cache.overall_mshr_misses::cpu0.data 134859 # number of overall MSHR misses 1124system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 244881 # number of overall MSHR misses 1125system.cpu0.l2cache.overall_mshr_misses::total 426761 # number of overall MSHR misses 1126system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable 1127system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 21110 # number of ReadReq MSHR uncacheable 1128system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 30132 # number of ReadReq MSHR uncacheable 1129system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 19686 # number of WriteReq MSHR uncacheable 1130system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 19686 # number of WriteReq MSHR uncacheable 1131system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses 1132system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 40796 # number of overall MSHR uncacheable misses 1133system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 49818 # number of overall MSHR uncacheable misses 1134system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 4045000 # number of ReadReq MSHR miss cycles 1135system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 1847000 # number of ReadReq MSHR miss cycles 1136system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 5892000 # number of ReadReq MSHR miss cycles 1137system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13903852400 # number of HardPFReq MSHR miss cycles 1138system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 13903852400 # number of HardPFReq MSHR miss cycles 1139system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 522651500 # number of UpgradeReq MSHR miss cycles 1140system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 522651500 # number of UpgradeReq MSHR miss cycles 1141system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 269507500 # number of SCUpgradeReq MSHR miss cycles 1142system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 269507500 # number of SCUpgradeReq MSHR miss cycles 1143system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1348996 # number of SCUpgradeFailReq MSHR miss cycles 1144system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1348996 # number of SCUpgradeFailReq MSHR miss cycles 1145system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1589383000 # number of ReadExReq MSHR miss cycles 1146system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1589383000 # number of ReadExReq MSHR miss cycles 1147system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 2037005000 # number of ReadCleanReq MSHR miss cycles 1148system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 2037005000 # number of ReadCleanReq MSHR miss cycles 1149system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2197124000 # number of ReadSharedReq MSHR miss cycles 1150system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2197124000 # number of ReadSharedReq MSHR miss cycles 1151system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 4045000 # number of demand (read+write) MSHR miss cycles 1152system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 1847000 # number of demand (read+write) MSHR miss cycles 1153system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2037005000 # number of demand (read+write) MSHR miss cycles 1154system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3786507000 # number of demand (read+write) MSHR miss cycles 1155system.cpu0.l2cache.demand_mshr_miss_latency::total 5829404000 # number of demand (read+write) MSHR miss cycles 1156system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 4045000 # number of overall MSHR miss cycles 1157system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 1847000 # number of overall MSHR miss cycles 1158system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2037005000 # number of overall MSHR miss cycles 1159system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3786507000 # number of overall MSHR miss cycles 1160system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13903852400 # number of overall MSHR miss cycles 1161system.cpu0.l2cache.overall_mshr_miss_latency::total 19733256400 # number of overall MSHR miss cycles 1162system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 733130500 # number of ReadReq MSHR uncacheable cycles 1163system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4264886500 # number of ReadReq MSHR uncacheable cycles 1164system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4998017000 # number of ReadReq MSHR uncacheable cycles 1165system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3246952500 # number of WriteReq MSHR uncacheable cycles 1166system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3246952500 # number of WriteReq MSHR uncacheable cycles 1167system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 733130500 # number of overall MSHR uncacheable cycles 1168system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 7511839000 # number of overall MSHR uncacheable cycles 1169system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 8244969500 # number of overall MSHR uncacheable cycles 1170system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.027822 # mshr miss rate for ReadReq accesses 1171system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.029698 # mshr miss rate for ReadReq accesses 1172system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.028404 # mshr miss rate for ReadReq accesses 1173system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 1174system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 1175system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1176system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1177system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.478697 # mshr miss rate for UpgradeReq accesses 1178system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.478697 # mshr miss rate for UpgradeReq accesses 1179system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.915633 # mshr miss rate for SCUpgradeReq accesses 1180system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.915633 # mshr miss rate for SCUpgradeReq accesses 1181system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1182system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1183system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.149988 # mshr miss rate for ReadExReq accesses 1184system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.149988 # mshr miss rate for ReadExReq accesses 1185system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.042186 # mshr miss rate for ReadCleanReq accesses 1186system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.042186 # mshr miss rate for ReadCleanReq accesses 1187system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.196440 # mshr miss rate for ReadSharedReq accesses 1188system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.196440 # mshr miss rate for ReadSharedReq accesses 1189system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.027822 # mshr miss rate for demand accesses 1190system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.029698 # mshr miss rate for demand accesses 1191system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.042186 # mshr miss rate for demand accesses 1192system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.179743 # mshr miss rate for demand accesses 1193system.cpu0.l2cache.demand_mshr_miss_rate::total 0.097324 # mshr miss rate for demand accesses 1194system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.027822 # mshr miss rate for overall accesses 1195system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.029698 # mshr miss rate for overall accesses 1196system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.042186 # mshr miss rate for overall accesses 1197system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.179743 # mshr miss rate for overall accesses 1198system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1199system.cpu0.l2cache.overall_mshr_miss_rate::total 0.228360 # mshr miss rate for overall accesses 1200system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 17663.755459 # average ReadReq mshr miss latency 1201system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16790.909091 # average ReadReq mshr miss latency 1202system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 17380.530973 # average ReadReq mshr miss latency 1203system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56777.995843 # average HardPFReq mshr miss latency 1204system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 56777.995843 # average HardPFReq mshr miss latency 1205system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20076.499059 # average UpgradeReq mshr miss latency 1206system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20076.499059 # average UpgradeReq mshr miss latency 1207system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14905.563852 # average SCUpgradeReq mshr miss latency 1208system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14905.563852 # average SCUpgradeReq mshr miss latency 1209system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 337249 # average SCUpgradeFailReq mshr miss latency 1210system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 337249 # average SCUpgradeFailReq mshr miss latency 1211system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 39292.533993 # average ReadExReq mshr miss latency 1212system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 39292.533993 # average ReadExReq mshr miss latency 1213system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 43635.769676 # average ReadCleanReq mshr miss latency 1214system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 43635.769676 # average ReadCleanReq mshr miss latency 1215system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 23272.399877 # average ReadSharedReq mshr miss latency 1216system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 23272.399877 # average ReadSharedReq mshr miss latency 1217system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 17663.755459 # average overall mshr miss latency 1218system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16790.909091 # average overall mshr miss latency 1219system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 43635.769676 # average overall mshr miss latency 1220system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28077.525415 # average overall mshr miss latency 1221system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 32050.824720 # average overall mshr miss latency 1222system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 17663.755459 # average overall mshr miss latency 1223system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16790.909091 # average overall mshr miss latency 1224system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 43635.769676 # average overall mshr miss latency 1225system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28077.525415 # average overall mshr miss latency 1226system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56777.995843 # average overall mshr miss latency 1227system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46239.596402 # average overall mshr miss latency 1228system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 81260.308136 # average ReadReq mshr uncacheable latency 1229system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 202031.572714 # average ReadReq mshr uncacheable latency 1230system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 165870.735431 # average ReadReq mshr uncacheable latency 1231system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164937.138068 # average WriteReq mshr uncacheable latency 1232system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 164937.138068 # average WriteReq mshr uncacheable latency 1233system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 81260.308136 # average overall mshr uncacheable latency 1234system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 184131.753113 # average overall mshr uncacheable latency 1235system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 165501.816612 # average overall mshr uncacheable latency 1236system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1237system.cpu0.toL2Bus.trans_dist::ReadReq 64679 # Transaction distribution 1238system.cpu0.toL2Bus.trans_dist::ReadResp 1685922 # Transaction distribution 1239system.cpu0.toL2Bus.trans_dist::WriteReq 30913 # Transaction distribution 1240system.cpu0.toL2Bus.trans_dist::WriteResp 19686 # Transaction distribution 1241system.cpu0.toL2Bus.trans_dist::Writeback 869596 # Transaction distribution 1242system.cpu0.toL2Bus.trans_dist::CleanEvict 1383128 # Transaction distribution 1243system.cpu0.toL2Bus.trans_dist::HardPFReq 312557 # Transaction distribution 1244system.cpu0.toL2Bus.trans_dist::UpgradeReq 88259 # Transaction distribution 1245system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42246 # Transaction distribution 1246system.cpu0.toL2Bus.trans_dist::UpgradeResp 111569 # Transaction distribution 1247system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 44 # Transaction distribution 1248system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 93 # Transaction distribution 1249system.cpu0.toL2Bus.trans_dist::ReadExReq 298532 # Transaction distribution 1250system.cpu0.toL2Bus.trans_dist::ReadExResp 285304 # Transaction distribution 1251system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1106585 # Transaction distribution 1252system.cpu0.toL2Bus.trans_dist::ReadSharedReq 579491 # Transaction distribution 1253system.cpu0.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution 1254system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3316089 # Packet count per connected master and slave (bytes) 1255system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2519725 # Packet count per connected master and slave (bytes) 1256system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10102 # Packet count per connected master and slave (bytes) 1257system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 22430 # Packet count per connected master and slave (bytes) 1258system.cpu0.toL2Bus.pkt_count::total 5868346 # Packet count per connected master and slave (bytes) 1259system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 70857528 # Cumulative packet size per connected master and slave (bytes) 1260system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 84663704 # Cumulative packet size per connected master and slave (bytes) 1261system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 14816 # Cumulative packet size per connected master and slave (bytes) 1262system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 32924 # Cumulative packet size per connected master and slave (bytes) 1263system.cpu0.toL2Bus.pkt_size::total 155568972 # Cumulative packet size per connected master and slave (bytes) 1264system.cpu0.toL2Bus.snoops 1147635 # Total snoops (count) 1265system.cpu0.toL2Bus.snoop_fanout::samples 4840235 # Request fanout histogram 1266system.cpu0.toL2Bus.snoop_fanout::mean 1.218671 # Request fanout histogram 1267system.cpu0.toL2Bus.snoop_fanout::stdev 0.413345 # Request fanout histogram 1268system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1269system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1270system.cpu0.toL2Bus.snoop_fanout::1 3781818 78.13% 78.13% # Request fanout histogram 1271system.cpu0.toL2Bus.snoop_fanout::2 1058417 21.87% 100.00% # Request fanout histogram 1272system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1273system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 1274system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1275system.cpu0.toL2Bus.snoop_fanout::total 4840235 # Request fanout histogram 1276system.cpu0.toL2Bus.reqLayer0.occupancy 2418139995 # Layer occupancy (ticks) 1277system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1278system.cpu0.toL2Bus.snoopLayer0.occupancy 114234000 # Layer occupancy (ticks) 1279system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1280system.cpu0.toL2Bus.respLayer0.occupancy 1668899500 # Layer occupancy (ticks) 1281system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1282system.cpu0.toL2Bus.respLayer1.occupancy 1193519480 # Layer occupancy (ticks) 1283system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1284system.cpu0.toL2Bus.respLayer2.occupancy 6398000 # Layer occupancy (ticks) 1285system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1286system.cpu0.toL2Bus.respLayer3.occupancy 14203990 # Layer occupancy (ticks) 1287system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1288system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1289system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1290system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1291system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1292system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1293system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1294system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1295system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1296system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1297system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1298system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1299system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1300system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1301system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1302system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1303system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1304system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1305system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1306system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1307system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1308system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1309system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1310system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1311system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1312system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1313system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1314system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1315system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1316system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1317system.cpu1.dtb.walker.walks 3364 # Table walker walks requested 1318system.cpu1.dtb.walker.walksShort 3364 # Table walker walks initiated with short descriptors 1319system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 665 # Level at which table walker walks with short descriptors terminate 1320system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2699 # Level at which table walker walks with short descriptors terminate 1321system.cpu1.dtb.walker.walkWaitTime::samples 3364 # Table walker wait (enqueue to first request) latency 1322system.cpu1.dtb.walker.walkWaitTime::0 3364 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1323system.cpu1.dtb.walker.walkWaitTime::total 3364 # Table walker wait (enqueue to first request) latency 1324system.cpu1.dtb.walker.walkCompletionTime::samples 2594 # Table walker service (enqueue to completion) latency 1325system.cpu1.dtb.walker.walkCompletionTime::mean 10057.247494 # Table walker service (enqueue to completion) latency 1326system.cpu1.dtb.walker.walkCompletionTime::gmean 9203.479719 # Table walker service (enqueue to completion) latency 1327system.cpu1.dtb.walker.walkCompletionTime::stdev 5035.039152 # Table walker service (enqueue to completion) latency 1328system.cpu1.dtb.walker.walkCompletionTime::0-8191 1036 39.94% 39.94% # Table walker service (enqueue to completion) latency 1329system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1440 55.51% 95.45% # Table walker service (enqueue to completion) latency 1330system.cpu1.dtb.walker.walkCompletionTime::16384-24575 55 2.12% 97.57% # Table walker service (enqueue to completion) latency 1331system.cpu1.dtb.walker.walkCompletionTime::24576-32767 56 2.16% 99.73% # Table walker service (enqueue to completion) latency 1332system.cpu1.dtb.walker.walkCompletionTime::40960-49151 6 0.23% 99.96% # Table walker service (enqueue to completion) latency 1333system.cpu1.dtb.walker.walkCompletionTime::90112-98303 1 0.04% 100.00% # Table walker service (enqueue to completion) latency 1334system.cpu1.dtb.walker.walkCompletionTime::total 2594 # Table walker service (enqueue to completion) latency 1335system.cpu1.dtb.walker.walksPending::samples 1650887468 # Table walker pending requests distribution 1336system.cpu1.dtb.walker.walksPending::0 1650887468 100.00% 100.00% # Table walker pending requests distribution 1337system.cpu1.dtb.walker.walksPending::total 1650887468 # Table walker pending requests distribution 1338system.cpu1.dtb.walker.walkPageSizes::4K 1937 74.67% 74.67% # Table walker page sizes translated 1339system.cpu1.dtb.walker.walkPageSizes::1M 657 25.33% 100.00% # Table walker page sizes translated 1340system.cpu1.dtb.walker.walkPageSizes::total 2594 # Table walker page sizes translated 1341system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3364 # Table walker requests started/completed, data/inst 1342system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1343system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3364 # Table walker requests started/completed, data/inst 1344system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2594 # Table walker requests started/completed, data/inst 1345system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1346system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2594 # Table walker requests started/completed, data/inst 1347system.cpu1.dtb.walker.walkRequestOrigin::total 5958 # Table walker requests started/completed, data/inst 1348system.cpu1.dtb.inst_hits 0 # ITB inst hits 1349system.cpu1.dtb.inst_misses 0 # ITB inst misses 1350system.cpu1.dtb.read_hits 6310579 # DTB read hits 1351system.cpu1.dtb.read_misses 2859 # DTB read misses 1352system.cpu1.dtb.write_hits 4631996 # DTB write hits 1353system.cpu1.dtb.write_misses 505 # DTB write misses 1354system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1355system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1356system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1357system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1358system.cpu1.dtb.flush_entries 2036 # Number of entries that have been flushed from TLB 1359system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 1360system.cpu1.dtb.prefetch_faults 323 # Number of TLB faults due to prefetch 1361system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1362system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions 1363system.cpu1.dtb.read_accesses 6313438 # DTB read accesses 1364system.cpu1.dtb.write_accesses 4632501 # DTB write accesses 1365system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1366system.cpu1.dtb.hits 10942575 # DTB hits 1367system.cpu1.dtb.misses 3364 # DTB misses 1368system.cpu1.dtb.accesses 10945939 # DTB accesses 1369system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1370system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1371system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1372system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1373system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1374system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1375system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1376system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1377system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1378system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1379system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1380system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1381system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1382system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1383system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1384system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1385system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1386system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1387system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1388system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1389system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1390system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1391system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1392system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1393system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1394system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1395system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1396system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1397system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1398system.cpu1.itb.walker.walks 1746 # Table walker walks requested 1399system.cpu1.itb.walker.walksShort 1746 # Table walker walks initiated with short descriptors 1400system.cpu1.itb.walker.walksShortTerminationLevel::Level1 168 # Level at which table walker walks with short descriptors terminate 1401system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1578 # Level at which table walker walks with short descriptors terminate 1402system.cpu1.itb.walker.walkWaitTime::samples 1746 # Table walker wait (enqueue to first request) latency 1403system.cpu1.itb.walker.walkWaitTime::0 1746 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1404system.cpu1.itb.walker.walkWaitTime::total 1746 # Table walker wait (enqueue to first request) latency 1405system.cpu1.itb.walker.walkCompletionTime::samples 1107 # Table walker service (enqueue to completion) latency 1406system.cpu1.itb.walker.walkCompletionTime::mean 10738.482385 # Table walker service (enqueue to completion) latency 1407system.cpu1.itb.walker.walkCompletionTime::gmean 9680.648713 # Table walker service (enqueue to completion) latency 1408system.cpu1.itb.walker.walkCompletionTime::stdev 5669.589944 # Table walker service (enqueue to completion) latency 1409system.cpu1.itb.walker.walkCompletionTime::4096-8191 351 31.71% 31.71% # Table walker service (enqueue to completion) latency 1410system.cpu1.itb.walker.walkCompletionTime::8192-12287 484 43.72% 75.43% # Table walker service (enqueue to completion) latency 1411system.cpu1.itb.walker.walkCompletionTime::12288-16383 202 18.25% 93.68% # Table walker service (enqueue to completion) latency 1412system.cpu1.itb.walker.walkCompletionTime::16384-20479 20 1.81% 95.48% # Table walker service (enqueue to completion) latency 1413system.cpu1.itb.walker.walkCompletionTime::20480-24575 1 0.09% 95.57% # Table walker service (enqueue to completion) latency 1414system.cpu1.itb.walker.walkCompletionTime::24576-28671 23 2.08% 97.65% # Table walker service (enqueue to completion) latency 1415system.cpu1.itb.walker.walkCompletionTime::28672-32767 15 1.36% 99.01% # Table walker service (enqueue to completion) latency 1416system.cpu1.itb.walker.walkCompletionTime::32768-36863 5 0.45% 99.46% # Table walker service (enqueue to completion) latency 1417system.cpu1.itb.walker.walkCompletionTime::40960-45055 6 0.54% 100.00% # Table walker service (enqueue to completion) latency 1418system.cpu1.itb.walker.walkCompletionTime::total 1107 # Table walker service (enqueue to completion) latency 1419system.cpu1.itb.walker.walksPending::samples 1650350468 # Table walker pending requests distribution 1420system.cpu1.itb.walker.walksPending::0 1650350468 100.00% 100.00% # Table walker pending requests distribution 1421system.cpu1.itb.walker.walksPending::total 1650350468 # Table walker pending requests distribution 1422system.cpu1.itb.walker.walkPageSizes::4K 939 84.82% 84.82% # Table walker page sizes translated 1423system.cpu1.itb.walker.walkPageSizes::1M 168 15.18% 100.00% # Table walker page sizes translated 1424system.cpu1.itb.walker.walkPageSizes::total 1107 # Table walker page sizes translated 1425system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1426system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1746 # Table walker requests started/completed, data/inst 1427system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1746 # Table walker requests started/completed, data/inst 1428system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1429system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1107 # Table walker requests started/completed, data/inst 1430system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1107 # Table walker requests started/completed, data/inst 1431system.cpu1.itb.walker.walkRequestOrigin::total 2853 # Table walker requests started/completed, data/inst 1432system.cpu1.itb.inst_hits 27093131 # ITB inst hits 1433system.cpu1.itb.inst_misses 1746 # ITB inst misses 1434system.cpu1.itb.read_hits 0 # DTB read hits 1435system.cpu1.itb.read_misses 0 # DTB read misses 1436system.cpu1.itb.write_hits 0 # DTB write hits 1437system.cpu1.itb.write_misses 0 # DTB write misses 1438system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1439system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1440system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1441system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1442system.cpu1.itb.flush_entries 1148 # Number of entries that have been flushed from TLB 1443system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1444system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1445system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1446system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1447system.cpu1.itb.read_accesses 0 # DTB read accesses 1448system.cpu1.itb.write_accesses 0 # DTB write accesses 1449system.cpu1.itb.inst_accesses 27094877 # ITB inst accesses 1450system.cpu1.itb.hits 27093131 # DTB hits 1451system.cpu1.itb.misses 1746 # DTB misses 1452system.cpu1.itb.accesses 27094877 # DTB accesses 1453system.cpu1.numCycles 5736521358 # number of cpu cycles simulated 1454system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1455system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1456system.cpu1.committedInsts 26153786 # Number of instructions committed 1457system.cpu1.committedOps 32053131 # Number of ops (including micro ops) committed 1458system.cpu1.num_int_alu_accesses 28968286 # Number of integer alu accesses 1459system.cpu1.num_fp_alu_accesses 1857 # Number of float alu accesses 1460system.cpu1.num_func_calls 3299674 # number of times a function call or return occured 1461system.cpu1.num_conditional_control_insts 2947168 # number of instructions that are conditional controls 1462system.cpu1.num_int_insts 28968286 # number of integer instructions 1463system.cpu1.num_fp_insts 1857 # number of float instructions 1464system.cpu1.num_int_register_reads 54552282 # number of times the integer registers were read 1465system.cpu1.num_int_register_writes 20759353 # number of times the integer registers were written 1466system.cpu1.num_fp_register_reads 1341 # number of times the floating registers were read 1467system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written 1468system.cpu1.num_cc_register_reads 117965505 # number of times the CC registers were read 1469system.cpu1.num_cc_register_writes 9826508 # number of times the CC registers were written 1470system.cpu1.num_mem_refs 11178844 # number of memory refs 1471system.cpu1.num_load_insts 6422284 # Number of load instructions 1472system.cpu1.num_store_insts 4756560 # Number of store instructions 1473system.cpu1.num_idle_cycles 5660914446.273914 # Number of idle cycles 1474system.cpu1.num_busy_cycles 75606911.726086 # Number of busy cycles 1475system.cpu1.not_idle_fraction 0.013180 # Percentage of non-idle cycles 1476system.cpu1.idle_fraction 0.986820 # Percentage of idle cycles 1477system.cpu1.Branches 6348758 # Number of branches fetched 1478system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction 1479system.cpu1.op_class::IntAlu 21763864 65.97% 65.97% # Class of executed instruction 1480system.cpu1.op_class::IntMult 43243 0.13% 66.10% # Class of executed instruction 1481system.cpu1.op_class::IntDiv 0 0.00% 66.10% # Class of executed instruction 1482system.cpu1.op_class::FloatAdd 0 0.00% 66.10% # Class of executed instruction 1483system.cpu1.op_class::FloatCmp 0 0.00% 66.10% # Class of executed instruction 1484system.cpu1.op_class::FloatCvt 0 0.00% 66.10% # Class of executed instruction 1485system.cpu1.op_class::FloatMult 0 0.00% 66.10% # Class of executed instruction 1486system.cpu1.op_class::FloatDiv 0 0.00% 66.10% # Class of executed instruction 1487system.cpu1.op_class::FloatSqrt 0 0.00% 66.10% # Class of executed instruction 1488system.cpu1.op_class::SimdAdd 0 0.00% 66.10% # Class of executed instruction 1489system.cpu1.op_class::SimdAddAcc 0 0.00% 66.10% # Class of executed instruction 1490system.cpu1.op_class::SimdAlu 0 0.00% 66.10% # Class of executed instruction 1491system.cpu1.op_class::SimdCmp 0 0.00% 66.10% # Class of executed instruction 1492system.cpu1.op_class::SimdCvt 0 0.00% 66.10% # Class of executed instruction 1493system.cpu1.op_class::SimdMisc 0 0.00% 66.10% # Class of executed instruction 1494system.cpu1.op_class::SimdMult 0 0.00% 66.10% # Class of executed instruction 1495system.cpu1.op_class::SimdMultAcc 0 0.00% 66.10% # Class of executed instruction 1496system.cpu1.op_class::SimdShift 0 0.00% 66.10% # Class of executed instruction 1497system.cpu1.op_class::SimdShiftAcc 0 0.00% 66.10% # Class of executed instruction 1498system.cpu1.op_class::SimdSqrt 0 0.00% 66.10% # Class of executed instruction 1499system.cpu1.op_class::SimdFloatAdd 0 0.00% 66.10% # Class of executed instruction 1500system.cpu1.op_class::SimdFloatAlu 0 0.00% 66.10% # Class of executed instruction 1501system.cpu1.op_class::SimdFloatCmp 0 0.00% 66.10% # Class of executed instruction 1502system.cpu1.op_class::SimdFloatCvt 0 0.00% 66.10% # Class of executed instruction 1503system.cpu1.op_class::SimdFloatDiv 0 0.00% 66.10% # Class of executed instruction 1504system.cpu1.op_class::SimdFloatMisc 3315 0.01% 66.11% # Class of executed instruction 1505system.cpu1.op_class::SimdFloatMult 0 0.00% 66.11% # Class of executed instruction 1506system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 66.11% # Class of executed instruction 1507system.cpu1.op_class::SimdFloatSqrt 0 0.00% 66.11% # Class of executed instruction 1508system.cpu1.op_class::MemRead 6422284 19.47% 85.58% # Class of executed instruction 1509system.cpu1.op_class::MemWrite 4756560 14.42% 100.00% # Class of executed instruction 1510system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 1511system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 1512system.cpu1.op_class::total 32989332 # Class of executed instruction 1513system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1514system.cpu1.kern.inst.quiesce 2773 # number of quiesce instructions executed 1515system.cpu1.dcache.tags.replacements 185916 # number of replacements 1516system.cpu1.dcache.tags.tagsinuse 465.807736 # Cycle average of tags in use 1517system.cpu1.dcache.tags.total_refs 10656106 # Total number of references to valid blocks. 1518system.cpu1.dcache.tags.sampled_refs 186281 # Sample count of references to valid blocks. 1519system.cpu1.dcache.tags.avg_refs 57.204471 # Average number of references to valid blocks. 1520system.cpu1.dcache.tags.warmup_cycle 104850302500 # Cycle when the warmup percentage was hit. 1521system.cpu1.dcache.tags.occ_blocks::cpu1.data 465.807736 # Average occupied blocks per requestor 1522system.cpu1.dcache.tags.occ_percent::cpu1.data 0.909781 # Average percentage of cache occupancy 1523system.cpu1.dcache.tags.occ_percent::total 0.909781 # Average percentage of cache occupancy 1524system.cpu1.dcache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id 1525system.cpu1.dcache.tags.age_task_id_blocks_1024::2 299 # Occupied blocks per task id 1526system.cpu1.dcache.tags.age_task_id_blocks_1024::3 66 # Occupied blocks per task id 1527system.cpu1.dcache.tags.occ_task_id_percent::1024 0.712891 # Percentage of cache occupancy per task id 1528system.cpu1.dcache.tags.tag_accesses 22064450 # Number of tag accesses 1529system.cpu1.dcache.tags.data_accesses 22064450 # Number of data accesses 1530system.cpu1.dcache.ReadReq_hits::cpu1.data 5988472 # number of ReadReq hits 1531system.cpu1.dcache.ReadReq_hits::total 5988472 # number of ReadReq hits 1532system.cpu1.dcache.WriteReq_hits::cpu1.data 4434786 # number of WriteReq hits 1533system.cpu1.dcache.WriteReq_hits::total 4434786 # number of WriteReq hits 1534system.cpu1.dcache.SoftPFReq_hits::cpu1.data 48931 # number of SoftPFReq hits 1535system.cpu1.dcache.SoftPFReq_hits::total 48931 # number of SoftPFReq hits 1536system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78766 # number of LoadLockedReq hits 1537system.cpu1.dcache.LoadLockedReq_hits::total 78766 # number of LoadLockedReq hits 1538system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70801 # number of StoreCondReq hits 1539system.cpu1.dcache.StoreCondReq_hits::total 70801 # number of StoreCondReq hits 1540system.cpu1.dcache.demand_hits::cpu1.data 10423258 # number of demand (read+write) hits 1541system.cpu1.dcache.demand_hits::total 10423258 # number of demand (read+write) hits 1542system.cpu1.dcache.overall_hits::cpu1.data 10472189 # number of overall hits 1543system.cpu1.dcache.overall_hits::total 10472189 # number of overall hits 1544system.cpu1.dcache.ReadReq_misses::cpu1.data 133050 # number of ReadReq misses 1545system.cpu1.dcache.ReadReq_misses::total 133050 # number of ReadReq misses 1546system.cpu1.dcache.WriteReq_misses::cpu1.data 91601 # number of WriteReq misses 1547system.cpu1.dcache.WriteReq_misses::total 91601 # number of WriteReq misses 1548system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30372 # number of SoftPFReq misses 1549system.cpu1.dcache.SoftPFReq_misses::total 30372 # number of SoftPFReq misses 1550system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17242 # number of LoadLockedReq misses 1551system.cpu1.dcache.LoadLockedReq_misses::total 17242 # number of LoadLockedReq misses 1552system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23381 # number of StoreCondReq misses 1553system.cpu1.dcache.StoreCondReq_misses::total 23381 # number of StoreCondReq misses 1554system.cpu1.dcache.demand_misses::cpu1.data 224651 # number of demand (read+write) misses 1555system.cpu1.dcache.demand_misses::total 224651 # number of demand (read+write) misses 1556system.cpu1.dcache.overall_misses::cpu1.data 255023 # number of overall misses 1557system.cpu1.dcache.overall_misses::total 255023 # number of overall misses 1558system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1943965500 # number of ReadReq miss cycles 1559system.cpu1.dcache.ReadReq_miss_latency::total 1943965500 # number of ReadReq miss cycles 1560system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2376775500 # number of WriteReq miss cycles 1561system.cpu1.dcache.WriteReq_miss_latency::total 2376775500 # number of WriteReq miss cycles 1562system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 323304000 # number of LoadLockedReq miss cycles 1563system.cpu1.dcache.LoadLockedReq_miss_latency::total 323304000 # number of LoadLockedReq miss cycles 1564system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 547906000 # number of StoreCondReq miss cycles 1565system.cpu1.dcache.StoreCondReq_miss_latency::total 547906000 # number of StoreCondReq miss cycles 1566system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2312500 # number of StoreCondFailReq miss cycles 1567system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2312500 # number of StoreCondFailReq miss cycles 1568system.cpu1.dcache.demand_miss_latency::cpu1.data 4320741000 # number of demand (read+write) miss cycles 1569system.cpu1.dcache.demand_miss_latency::total 4320741000 # number of demand (read+write) miss cycles 1570system.cpu1.dcache.overall_miss_latency::cpu1.data 4320741000 # number of overall miss cycles 1571system.cpu1.dcache.overall_miss_latency::total 4320741000 # number of overall miss cycles 1572system.cpu1.dcache.ReadReq_accesses::cpu1.data 6121522 # number of ReadReq accesses(hits+misses) 1573system.cpu1.dcache.ReadReq_accesses::total 6121522 # number of ReadReq accesses(hits+misses) 1574system.cpu1.dcache.WriteReq_accesses::cpu1.data 4526387 # number of WriteReq accesses(hits+misses) 1575system.cpu1.dcache.WriteReq_accesses::total 4526387 # number of WriteReq accesses(hits+misses) 1576system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79303 # number of SoftPFReq accesses(hits+misses) 1577system.cpu1.dcache.SoftPFReq_accesses::total 79303 # number of SoftPFReq accesses(hits+misses) 1578system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96008 # number of LoadLockedReq accesses(hits+misses) 1579system.cpu1.dcache.LoadLockedReq_accesses::total 96008 # number of LoadLockedReq accesses(hits+misses) 1580system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94182 # number of StoreCondReq accesses(hits+misses) 1581system.cpu1.dcache.StoreCondReq_accesses::total 94182 # number of StoreCondReq accesses(hits+misses) 1582system.cpu1.dcache.demand_accesses::cpu1.data 10647909 # number of demand (read+write) accesses 1583system.cpu1.dcache.demand_accesses::total 10647909 # number of demand (read+write) accesses 1584system.cpu1.dcache.overall_accesses::cpu1.data 10727212 # number of overall (read+write) accesses 1585system.cpu1.dcache.overall_accesses::total 10727212 # number of overall (read+write) accesses 1586system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.021735 # miss rate for ReadReq accesses 1587system.cpu1.dcache.ReadReq_miss_rate::total 0.021735 # miss rate for ReadReq accesses 1588system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.020237 # miss rate for WriteReq accesses 1589system.cpu1.dcache.WriteReq_miss_rate::total 0.020237 # miss rate for WriteReq accesses 1590system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.382987 # miss rate for SoftPFReq accesses 1591system.cpu1.dcache.SoftPFReq_miss_rate::total 0.382987 # miss rate for SoftPFReq accesses 1592system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.179589 # miss rate for LoadLockedReq accesses 1593system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.179589 # miss rate for LoadLockedReq accesses 1594system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.248253 # miss rate for StoreCondReq accesses 1595system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248253 # miss rate for StoreCondReq accesses 1596system.cpu1.dcache.demand_miss_rate::cpu1.data 0.021098 # miss rate for demand accesses 1597system.cpu1.dcache.demand_miss_rate::total 0.021098 # miss rate for demand accesses 1598system.cpu1.dcache.overall_miss_rate::cpu1.data 0.023773 # miss rate for overall accesses 1599system.cpu1.dcache.overall_miss_rate::total 0.023773 # miss rate for overall accesses 1600system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14610.789177 # average ReadReq miss latency 1601system.cpu1.dcache.ReadReq_avg_miss_latency::total 14610.789177 # average ReadReq miss latency 1602system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25947.047521 # average WriteReq miss latency 1603system.cpu1.dcache.WriteReq_avg_miss_latency::total 25947.047521 # average WriteReq miss latency 1604system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18750.956966 # average LoadLockedReq miss latency 1605system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18750.956966 # average LoadLockedReq miss latency 1606system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23433.813780 # average StoreCondReq miss latency 1607system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23433.813780 # average StoreCondReq miss latency 1608system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1609system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1610system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19233.126049 # average overall miss latency 1611system.cpu1.dcache.demand_avg_miss_latency::total 19233.126049 # average overall miss latency 1612system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16942.554201 # average overall miss latency 1613system.cpu1.dcache.overall_avg_miss_latency::total 16942.554201 # average overall miss latency 1614system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1615system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1616system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1617system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1618system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1619system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1620system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1621system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1622system.cpu1.dcache.writebacks::writebacks 116022 # number of writebacks 1623system.cpu1.dcache.writebacks::total 116022 # number of writebacks 1624system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 266 # number of ReadReq MSHR hits 1625system.cpu1.dcache.ReadReq_mshr_hits::total 266 # number of ReadReq MSHR hits 1626system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12054 # number of LoadLockedReq MSHR hits 1627system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12054 # number of LoadLockedReq MSHR hits 1628system.cpu1.dcache.demand_mshr_hits::cpu1.data 266 # number of demand (read+write) MSHR hits 1629system.cpu1.dcache.demand_mshr_hits::total 266 # number of demand (read+write) MSHR hits 1630system.cpu1.dcache.overall_mshr_hits::cpu1.data 266 # number of overall MSHR hits 1631system.cpu1.dcache.overall_mshr_hits::total 266 # number of overall MSHR hits 1632system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 132784 # number of ReadReq MSHR misses 1633system.cpu1.dcache.ReadReq_mshr_misses::total 132784 # number of ReadReq MSHR misses 1634system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 91601 # number of WriteReq MSHR misses 1635system.cpu1.dcache.WriteReq_mshr_misses::total 91601 # number of WriteReq MSHR misses 1636system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29597 # number of SoftPFReq MSHR misses 1637system.cpu1.dcache.SoftPFReq_mshr_misses::total 29597 # number of SoftPFReq MSHR misses 1638system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5188 # number of LoadLockedReq MSHR misses 1639system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5188 # number of LoadLockedReq MSHR misses 1640system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23381 # number of StoreCondReq MSHR misses 1641system.cpu1.dcache.StoreCondReq_mshr_misses::total 23381 # number of StoreCondReq MSHR misses 1642system.cpu1.dcache.demand_mshr_misses::cpu1.data 224385 # number of demand (read+write) MSHR misses 1643system.cpu1.dcache.demand_mshr_misses::total 224385 # number of demand (read+write) MSHR misses 1644system.cpu1.dcache.overall_mshr_misses::cpu1.data 253982 # number of overall MSHR misses 1645system.cpu1.dcache.overall_mshr_misses::total 253982 # number of overall MSHR misses 1646system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 13773 # number of ReadReq MSHR uncacheable 1647system.cpu1.dcache.ReadReq_mshr_uncacheable::total 13773 # number of ReadReq MSHR uncacheable 1648system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11227 # number of WriteReq MSHR uncacheable 1649system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11227 # number of WriteReq MSHR uncacheable 1650system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 25000 # number of overall MSHR uncacheable misses 1651system.cpu1.dcache.overall_mshr_uncacheable_misses::total 25000 # number of overall MSHR uncacheable misses 1652system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1804303500 # number of ReadReq MSHR miss cycles 1653system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1804303500 # number of ReadReq MSHR miss cycles 1654system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2285174500 # number of WriteReq MSHR miss cycles 1655system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2285174500 # number of WriteReq MSHR miss cycles 1656system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 494107000 # number of SoftPFReq MSHR miss cycles 1657system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 494107000 # number of SoftPFReq MSHR miss cycles 1658system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 90251000 # number of LoadLockedReq MSHR miss cycles 1659system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 90251000 # number of LoadLockedReq MSHR miss cycles 1660system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 524565000 # number of StoreCondReq MSHR miss cycles 1661system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 524565000 # number of StoreCondReq MSHR miss cycles 1662system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2272500 # number of StoreCondFailReq MSHR miss cycles 1663system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2272500 # number of StoreCondFailReq MSHR miss cycles 1664system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4089478000 # number of demand (read+write) MSHR miss cycles 1665system.cpu1.dcache.demand_mshr_miss_latency::total 4089478000 # number of demand (read+write) MSHR miss cycles 1666system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4583585000 # number of overall MSHR miss cycles 1667system.cpu1.dcache.overall_mshr_miss_latency::total 4583585000 # number of overall MSHR miss cycles 1668system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2232716000 # number of ReadReq MSHR uncacheable cycles 1669system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2232716000 # number of ReadReq MSHR uncacheable cycles 1670system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1768357000 # number of WriteReq MSHR uncacheable cycles 1671system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1768357000 # number of WriteReq MSHR uncacheable cycles 1672system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4001073000 # number of overall MSHR uncacheable cycles 1673system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4001073000 # number of overall MSHR uncacheable cycles 1674system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.021691 # mshr miss rate for ReadReq accesses 1675system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.021691 # mshr miss rate for ReadReq accesses 1676system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.020237 # mshr miss rate for WriteReq accesses 1677system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.020237 # mshr miss rate for WriteReq accesses 1678system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.373214 # mshr miss rate for SoftPFReq accesses 1679system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.373214 # mshr miss rate for SoftPFReq accesses 1680system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.054037 # mshr miss rate for LoadLockedReq accesses 1681system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054037 # mshr miss rate for LoadLockedReq accesses 1682system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248253 # mshr miss rate for StoreCondReq accesses 1683system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248253 # mshr miss rate for StoreCondReq accesses 1684system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.021073 # mshr miss rate for demand accesses 1685system.cpu1.dcache.demand_mshr_miss_rate::total 0.021073 # mshr miss rate for demand accesses 1686system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.023676 # mshr miss rate for overall accesses 1687system.cpu1.dcache.overall_mshr_miss_rate::total 0.023676 # mshr miss rate for overall accesses 1688system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13588.259881 # average ReadReq mshr miss latency 1689system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13588.259881 # average ReadReq mshr miss latency 1690system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24947.047521 # average WriteReq mshr miss latency 1691system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24947.047521 # average WriteReq mshr miss latency 1692system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16694.496064 # average SoftPFReq mshr miss latency 1693system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16694.496064 # average SoftPFReq mshr miss latency 1694system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17396.106399 # average LoadLockedReq mshr miss latency 1695system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17396.106399 # average LoadLockedReq mshr miss latency 1696system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22435.524571 # average StoreCondReq mshr miss latency 1697system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22435.524571 # average StoreCondReq mshr miss latency 1698system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1699system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1700system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18225.273525 # average overall mshr miss latency 1701system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18225.273525 # average overall mshr miss latency 1702system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18046.889150 # average overall mshr miss latency 1703system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18046.889150 # average overall mshr miss latency 1704system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 162108.182676 # average ReadReq mshr uncacheable latency 1705system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162108.182676 # average ReadReq mshr uncacheable latency 1706system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 157509.307918 # average WriteReq mshr uncacheable latency 1707system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 157509.307918 # average WriteReq mshr uncacheable latency 1708system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 160042.920000 # average overall mshr uncacheable latency 1709system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 160042.920000 # average overall mshr uncacheable latency 1710system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1711system.cpu1.icache.tags.replacements 505537 # number of replacements 1712system.cpu1.icache.tags.tagsinuse 498.573002 # Cycle average of tags in use 1713system.cpu1.icache.tags.total_refs 26587077 # Total number of references to valid blocks. 1714system.cpu1.icache.tags.sampled_refs 506049 # Sample count of references to valid blocks. 1715system.cpu1.icache.tags.avg_refs 52.538543 # Average number of references to valid blocks. 1716system.cpu1.icache.tags.warmup_cycle 84702248000 # Cycle when the warmup percentage was hit. 1717system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.573002 # Average occupied blocks per requestor 1718system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973775 # Average percentage of cache occupancy 1719system.cpu1.icache.tags.occ_percent::total 0.973775 # Average percentage of cache occupancy 1720system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1721system.cpu1.icache.tags.age_task_id_blocks_1024::2 392 # Occupied blocks per task id 1722system.cpu1.icache.tags.age_task_id_blocks_1024::3 117 # Occupied blocks per task id 1723system.cpu1.icache.tags.age_task_id_blocks_1024::4 3 # Occupied blocks per task id 1724system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1725system.cpu1.icache.tags.tag_accesses 54692301 # Number of tag accesses 1726system.cpu1.icache.tags.data_accesses 54692301 # Number of data accesses 1727system.cpu1.icache.ReadReq_hits::cpu1.inst 26587077 # number of ReadReq hits 1728system.cpu1.icache.ReadReq_hits::total 26587077 # number of ReadReq hits 1729system.cpu1.icache.demand_hits::cpu1.inst 26587077 # number of demand (read+write) hits 1730system.cpu1.icache.demand_hits::total 26587077 # number of demand (read+write) hits 1731system.cpu1.icache.overall_hits::cpu1.inst 26587077 # number of overall hits 1732system.cpu1.icache.overall_hits::total 26587077 # number of overall hits 1733system.cpu1.icache.ReadReq_misses::cpu1.inst 506049 # number of ReadReq misses 1734system.cpu1.icache.ReadReq_misses::total 506049 # number of ReadReq misses 1735system.cpu1.icache.demand_misses::cpu1.inst 506049 # number of demand (read+write) misses 1736system.cpu1.icache.demand_misses::total 506049 # number of demand (read+write) misses 1737system.cpu1.icache.overall_misses::cpu1.inst 506049 # number of overall misses 1738system.cpu1.icache.overall_misses::total 506049 # number of overall misses 1739system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4455517000 # number of ReadReq miss cycles 1740system.cpu1.icache.ReadReq_miss_latency::total 4455517000 # number of ReadReq miss cycles 1741system.cpu1.icache.demand_miss_latency::cpu1.inst 4455517000 # number of demand (read+write) miss cycles 1742system.cpu1.icache.demand_miss_latency::total 4455517000 # number of demand (read+write) miss cycles 1743system.cpu1.icache.overall_miss_latency::cpu1.inst 4455517000 # number of overall miss cycles 1744system.cpu1.icache.overall_miss_latency::total 4455517000 # number of overall miss cycles 1745system.cpu1.icache.ReadReq_accesses::cpu1.inst 27093126 # number of ReadReq accesses(hits+misses) 1746system.cpu1.icache.ReadReq_accesses::total 27093126 # number of ReadReq accesses(hits+misses) 1747system.cpu1.icache.demand_accesses::cpu1.inst 27093126 # number of demand (read+write) accesses 1748system.cpu1.icache.demand_accesses::total 27093126 # number of demand (read+write) accesses 1749system.cpu1.icache.overall_accesses::cpu1.inst 27093126 # number of overall (read+write) accesses 1750system.cpu1.icache.overall_accesses::total 27093126 # number of overall (read+write) accesses 1751system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.018678 # miss rate for ReadReq accesses 1752system.cpu1.icache.ReadReq_miss_rate::total 0.018678 # miss rate for ReadReq accesses 1753system.cpu1.icache.demand_miss_rate::cpu1.inst 0.018678 # miss rate for demand accesses 1754system.cpu1.icache.demand_miss_rate::total 0.018678 # miss rate for demand accesses 1755system.cpu1.icache.overall_miss_rate::cpu1.inst 0.018678 # miss rate for overall accesses 1756system.cpu1.icache.overall_miss_rate::total 0.018678 # miss rate for overall accesses 1757system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8804.516954 # average ReadReq miss latency 1758system.cpu1.icache.ReadReq_avg_miss_latency::total 8804.516954 # average ReadReq miss latency 1759system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8804.516954 # average overall miss latency 1760system.cpu1.icache.demand_avg_miss_latency::total 8804.516954 # average overall miss latency 1761system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8804.516954 # average overall miss latency 1762system.cpu1.icache.overall_avg_miss_latency::total 8804.516954 # average overall miss latency 1763system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1764system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1765system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1766system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1767system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1768system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1769system.cpu1.icache.fast_writes 0 # number of fast writes performed 1770system.cpu1.icache.cache_copies 0 # number of cache copies performed 1771system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 506049 # number of ReadReq MSHR misses 1772system.cpu1.icache.ReadReq_mshr_misses::total 506049 # number of ReadReq MSHR misses 1773system.cpu1.icache.demand_mshr_misses::cpu1.inst 506049 # number of demand (read+write) MSHR misses 1774system.cpu1.icache.demand_mshr_misses::total 506049 # number of demand (read+write) MSHR misses 1775system.cpu1.icache.overall_mshr_misses::cpu1.inst 506049 # number of overall MSHR misses 1776system.cpu1.icache.overall_mshr_misses::total 506049 # number of overall MSHR misses 1777system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable 1778system.cpu1.icache.ReadReq_mshr_uncacheable::total 177 # number of ReadReq MSHR uncacheable 1779system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses 1780system.cpu1.icache.overall_mshr_uncacheable_misses::total 177 # number of overall MSHR uncacheable misses 1781system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4202492500 # number of ReadReq MSHR miss cycles 1782system.cpu1.icache.ReadReq_mshr_miss_latency::total 4202492500 # number of ReadReq MSHR miss cycles 1783system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4202492500 # number of demand (read+write) MSHR miss cycles 1784system.cpu1.icache.demand_mshr_miss_latency::total 4202492500 # number of demand (read+write) MSHR miss cycles 1785system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4202492500 # number of overall MSHR miss cycles 1786system.cpu1.icache.overall_mshr_miss_latency::total 4202492500 # number of overall MSHR miss cycles 1787system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 15340000 # number of ReadReq MSHR uncacheable cycles 1788system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 15340000 # number of ReadReq MSHR uncacheable cycles 1789system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 15340000 # number of overall MSHR uncacheable cycles 1790system.cpu1.icache.overall_mshr_uncacheable_latency::total 15340000 # number of overall MSHR uncacheable cycles 1791system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.018678 # mshr miss rate for ReadReq accesses 1792system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.018678 # mshr miss rate for ReadReq accesses 1793system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.018678 # mshr miss rate for demand accesses 1794system.cpu1.icache.demand_mshr_miss_rate::total 0.018678 # mshr miss rate for demand accesses 1795system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.018678 # mshr miss rate for overall accesses 1796system.cpu1.icache.overall_mshr_miss_rate::total 0.018678 # mshr miss rate for overall accesses 1797system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8304.516954 # average ReadReq mshr miss latency 1798system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8304.516954 # average ReadReq mshr miss latency 1799system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8304.516954 # average overall mshr miss latency 1800system.cpu1.icache.demand_avg_mshr_miss_latency::total 8304.516954 # average overall mshr miss latency 1801system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8304.516954 # average overall mshr miss latency 1802system.cpu1.icache.overall_avg_mshr_miss_latency::total 8304.516954 # average overall mshr miss latency 1803system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 86666.666667 # average ReadReq mshr uncacheable latency 1804system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 86666.666667 # average ReadReq mshr uncacheable latency 1805system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 86666.666667 # average overall mshr uncacheable latency 1806system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 86666.666667 # average overall mshr uncacheable latency 1807system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1808system.cpu1.l2cache.prefetcher.num_hwpf_issued 199458 # number of hwpf issued 1809system.cpu1.l2cache.prefetcher.pfIdentified 199458 # number of prefetch candidates identified 1810system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 1811system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1812system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1813system.cpu1.l2cache.prefetcher.pfSpanPage 58862 # number of prefetches not generated due to page crossing 1814system.cpu1.l2cache.tags.replacements 46506 # number of replacements 1815system.cpu1.l2cache.tags.tagsinuse 15029.734126 # Cycle average of tags in use 1816system.cpu1.l2cache.tags.total_refs 1265349 # Total number of references to valid blocks. 1817system.cpu1.l2cache.tags.sampled_refs 61182 # Sample count of references to valid blocks. 1818system.cpu1.l2cache.tags.avg_refs 20.681720 # Average number of references to valid blocks. 1819system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1820system.cpu1.l2cache.tags.occ_blocks::writebacks 8657.593794 # Average occupied blocks per requestor 1821system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.281679 # Average occupied blocks per requestor 1822system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.079815 # Average occupied blocks per requestor 1823system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3148.961374 # Average occupied blocks per requestor 1824system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2173.187241 # Average occupied blocks per requestor 1825system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1044.630222 # Average occupied blocks per requestor 1826system.cpu1.l2cache.tags.occ_percent::writebacks 0.528418 # Average percentage of cache occupancy 1827system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000200 # Average percentage of cache occupancy 1828system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000127 # Average percentage of cache occupancy 1829system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.192197 # Average percentage of cache occupancy 1830system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.132641 # Average percentage of cache occupancy 1831system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.063759 # Average percentage of cache occupancy 1832system.cpu1.l2cache.tags.occ_percent::total 0.917342 # Average percentage of cache occupancy 1833system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1197 # Occupied blocks per task id 1834system.cpu1.l2cache.tags.occ_task_id_blocks::1023 19 # Occupied blocks per task id 1835system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13460 # Occupied blocks per task id 1836system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 6 # Occupied blocks per task id 1837system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 35 # Occupied blocks per task id 1838system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1156 # Occupied blocks per task id 1839system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id 1840system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id 1841system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id 1842system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 274 # Occupied blocks per task id 1843system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1596 # Occupied blocks per task id 1844system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 11590 # Occupied blocks per task id 1845system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.073059 # Percentage of cache occupancy per task id 1846system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001160 # Percentage of cache occupancy per task id 1847system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.821533 # Percentage of cache occupancy per task id 1848system.cpu1.l2cache.tags.tag_accesses 23794594 # Number of tag accesses 1849system.cpu1.l2cache.tags.data_accesses 23794594 # Number of data accesses 1850system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3091 # number of ReadReq hits 1851system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1709 # number of ReadReq hits 1852system.cpu1.l2cache.ReadReq_hits::total 4800 # number of ReadReq hits 1853system.cpu1.l2cache.Writeback_hits::writebacks 116022 # number of Writeback hits 1854system.cpu1.l2cache.Writeback_hits::total 116022 # number of Writeback hits 1855system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1472 # number of UpgradeReq hits 1856system.cpu1.l2cache.UpgradeReq_hits::total 1472 # number of UpgradeReq hits 1857system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 842 # number of SCUpgradeReq hits 1858system.cpu1.l2cache.SCUpgradeReq_hits::total 842 # number of SCUpgradeReq hits 1859system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27319 # number of ReadExReq hits 1860system.cpu1.l2cache.ReadExReq_hits::total 27319 # number of ReadExReq hits 1861system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 492294 # number of ReadCleanReq hits 1862system.cpu1.l2cache.ReadCleanReq_hits::total 492294 # number of ReadCleanReq hits 1863system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 99296 # number of ReadSharedReq hits 1864system.cpu1.l2cache.ReadSharedReq_hits::total 99296 # number of ReadSharedReq hits 1865system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3091 # number of demand (read+write) hits 1866system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1709 # number of demand (read+write) hits 1867system.cpu1.l2cache.demand_hits::cpu1.inst 492294 # number of demand (read+write) hits 1868system.cpu1.l2cache.demand_hits::cpu1.data 126615 # number of demand (read+write) hits 1869system.cpu1.l2cache.demand_hits::total 623709 # number of demand (read+write) hits 1870system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3091 # number of overall hits 1871system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1709 # number of overall hits 1872system.cpu1.l2cache.overall_hits::cpu1.inst 492294 # number of overall hits 1873system.cpu1.l2cache.overall_hits::cpu1.data 126615 # number of overall hits 1874system.cpu1.l2cache.overall_hits::total 623709 # number of overall hits 1875system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 314 # number of ReadReq misses 1876system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 266 # number of ReadReq misses 1877system.cpu1.l2cache.ReadReq_misses::total 580 # number of ReadReq misses 1878system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28095 # number of UpgradeReq misses 1879system.cpu1.l2cache.UpgradeReq_misses::total 28095 # number of UpgradeReq misses 1880system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22537 # number of SCUpgradeReq misses 1881system.cpu1.l2cache.SCUpgradeReq_misses::total 22537 # number of SCUpgradeReq misses 1882system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 2 # number of SCUpgradeFailReq misses 1883system.cpu1.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses 1884system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34715 # number of ReadExReq misses 1885system.cpu1.l2cache.ReadExReq_misses::total 34715 # number of ReadExReq misses 1886system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 13755 # number of ReadCleanReq misses 1887system.cpu1.l2cache.ReadCleanReq_misses::total 13755 # number of ReadCleanReq misses 1888system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 68273 # number of ReadSharedReq misses 1889system.cpu1.l2cache.ReadSharedReq_misses::total 68273 # number of ReadSharedReq misses 1890system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 314 # number of demand (read+write) misses 1891system.cpu1.l2cache.demand_misses::cpu1.itb.walker 266 # number of demand (read+write) misses 1892system.cpu1.l2cache.demand_misses::cpu1.inst 13755 # number of demand (read+write) misses 1893system.cpu1.l2cache.demand_misses::cpu1.data 102988 # number of demand (read+write) misses 1894system.cpu1.l2cache.demand_misses::total 117323 # number of demand (read+write) misses 1895system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 314 # number of overall misses 1896system.cpu1.l2cache.overall_misses::cpu1.itb.walker 266 # number of overall misses 1897system.cpu1.l2cache.overall_misses::cpu1.inst 13755 # number of overall misses 1898system.cpu1.l2cache.overall_misses::cpu1.data 102988 # number of overall misses 1899system.cpu1.l2cache.overall_misses::total 117323 # number of overall misses 1900system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 6334500 # number of ReadReq miss cycles 1901system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5311000 # number of ReadReq miss cycles 1902system.cpu1.l2cache.ReadReq_miss_latency::total 11645500 # number of ReadReq miss cycles 1903system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 538209000 # number of UpgradeReq miss cycles 1904system.cpu1.l2cache.UpgradeReq_miss_latency::total 538209000 # number of UpgradeReq miss cycles 1905system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 450797500 # number of SCUpgradeReq miss cycles 1906system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 450797500 # number of SCUpgradeReq miss cycles 1907system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2212500 # number of SCUpgradeFailReq miss cycles 1908system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2212500 # number of SCUpgradeFailReq miss cycles 1909system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1336972500 # number of ReadExReq miss cycles 1910system.cpu1.l2cache.ReadExReq_miss_latency::total 1336972500 # number of ReadExReq miss cycles 1911system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 492390500 # number of ReadCleanReq miss cycles 1912system.cpu1.l2cache.ReadCleanReq_miss_latency::total 492390500 # number of ReadCleanReq miss cycles 1913system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1491495000 # number of ReadSharedReq miss cycles 1914system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1491495000 # number of ReadSharedReq miss cycles 1915system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 6334500 # number of demand (read+write) miss cycles 1916system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5311000 # number of demand (read+write) miss cycles 1917system.cpu1.l2cache.demand_miss_latency::cpu1.inst 492390500 # number of demand (read+write) miss cycles 1918system.cpu1.l2cache.demand_miss_latency::cpu1.data 2828467500 # number of demand (read+write) miss cycles 1919system.cpu1.l2cache.demand_miss_latency::total 3332503500 # number of demand (read+write) miss cycles 1920system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 6334500 # number of overall miss cycles 1921system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5311000 # number of overall miss cycles 1922system.cpu1.l2cache.overall_miss_latency::cpu1.inst 492390500 # number of overall miss cycles 1923system.cpu1.l2cache.overall_miss_latency::cpu1.data 2828467500 # number of overall miss cycles 1924system.cpu1.l2cache.overall_miss_latency::total 3332503500 # number of overall miss cycles 1925system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3405 # number of ReadReq accesses(hits+misses) 1926system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1975 # number of ReadReq accesses(hits+misses) 1927system.cpu1.l2cache.ReadReq_accesses::total 5380 # number of ReadReq accesses(hits+misses) 1928system.cpu1.l2cache.Writeback_accesses::writebacks 116022 # number of Writeback accesses(hits+misses) 1929system.cpu1.l2cache.Writeback_accesses::total 116022 # number of Writeback accesses(hits+misses) 1930system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29567 # number of UpgradeReq accesses(hits+misses) 1931system.cpu1.l2cache.UpgradeReq_accesses::total 29567 # number of UpgradeReq accesses(hits+misses) 1932system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23379 # number of SCUpgradeReq accesses(hits+misses) 1933system.cpu1.l2cache.SCUpgradeReq_accesses::total 23379 # number of SCUpgradeReq accesses(hits+misses) 1934system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 2 # number of SCUpgradeFailReq accesses(hits+misses) 1935system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) 1936system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 62034 # number of ReadExReq accesses(hits+misses) 1937system.cpu1.l2cache.ReadExReq_accesses::total 62034 # number of ReadExReq accesses(hits+misses) 1938system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 506049 # number of ReadCleanReq accesses(hits+misses) 1939system.cpu1.l2cache.ReadCleanReq_accesses::total 506049 # number of ReadCleanReq accesses(hits+misses) 1940system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 167569 # number of ReadSharedReq accesses(hits+misses) 1941system.cpu1.l2cache.ReadSharedReq_accesses::total 167569 # number of ReadSharedReq accesses(hits+misses) 1942system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3405 # number of demand (read+write) accesses 1943system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 1975 # number of demand (read+write) accesses 1944system.cpu1.l2cache.demand_accesses::cpu1.inst 506049 # number of demand (read+write) accesses 1945system.cpu1.l2cache.demand_accesses::cpu1.data 229603 # number of demand (read+write) accesses 1946system.cpu1.l2cache.demand_accesses::total 741032 # number of demand (read+write) accesses 1947system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3405 # number of overall (read+write) accesses 1948system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 1975 # number of overall (read+write) accesses 1949system.cpu1.l2cache.overall_accesses::cpu1.inst 506049 # number of overall (read+write) accesses 1950system.cpu1.l2cache.overall_accesses::cpu1.data 229603 # number of overall (read+write) accesses 1951system.cpu1.l2cache.overall_accesses::total 741032 # number of overall (read+write) accesses 1952system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.092217 # miss rate for ReadReq accesses 1953system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.134684 # miss rate for ReadReq accesses 1954system.cpu1.l2cache.ReadReq_miss_rate::total 0.107807 # miss rate for ReadReq accesses 1955system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.950215 # miss rate for UpgradeReq accesses 1956system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.950215 # miss rate for UpgradeReq accesses 1957system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.963985 # miss rate for SCUpgradeReq accesses 1958system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.963985 # miss rate for SCUpgradeReq accesses 1959system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 1960system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1961system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.559612 # miss rate for ReadExReq accesses 1962system.cpu1.l2cache.ReadExReq_miss_rate::total 0.559612 # miss rate for ReadExReq accesses 1963system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.027181 # miss rate for ReadCleanReq accesses 1964system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.027181 # miss rate for ReadCleanReq accesses 1965system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.407432 # miss rate for ReadSharedReq accesses 1966system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.407432 # miss rate for ReadSharedReq accesses 1967system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.092217 # miss rate for demand accesses 1968system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.134684 # miss rate for demand accesses 1969system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.027181 # miss rate for demand accesses 1970system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.448548 # miss rate for demand accesses 1971system.cpu1.l2cache.demand_miss_rate::total 0.158324 # miss rate for demand accesses 1972system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.092217 # miss rate for overall accesses 1973system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.134684 # miss rate for overall accesses 1974system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.027181 # miss rate for overall accesses 1975system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.448548 # miss rate for overall accesses 1976system.cpu1.l2cache.overall_miss_rate::total 0.158324 # miss rate for overall accesses 1977system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20173.566879 # average ReadReq miss latency 1978system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19966.165414 # average ReadReq miss latency 1979system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20078.448276 # average ReadReq miss latency 1980system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 19156.753871 # average UpgradeReq miss latency 1981system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 19156.753871 # average UpgradeReq miss latency 1982system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20002.551360 # average SCUpgradeReq miss latency 1983system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20002.551360 # average SCUpgradeReq miss latency 1984system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 1106250 # average SCUpgradeFailReq miss latency 1985system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 1106250 # average SCUpgradeFailReq miss latency 1986system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 38512.818666 # average ReadExReq miss latency 1987system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 38512.818666 # average ReadExReq miss latency 1988system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 35797.201018 # average ReadCleanReq miss latency 1989system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 35797.201018 # average ReadCleanReq miss latency 1990system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 21846.044556 # average ReadSharedReq miss latency 1991system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 21846.044556 # average ReadSharedReq miss latency 1992system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20173.566879 # average overall miss latency 1993system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 19966.165414 # average overall miss latency 1994system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 35797.201018 # average overall miss latency 1995system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 27464.049210 # average overall miss latency 1996system.cpu1.l2cache.demand_avg_miss_latency::total 28404.520000 # average overall miss latency 1997system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20173.566879 # average overall miss latency 1998system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 19966.165414 # average overall miss latency 1999system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 35797.201018 # average overall miss latency 2000system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 27464.049210 # average overall miss latency 2001system.cpu1.l2cache.overall_avg_miss_latency::total 28404.520000 # average overall miss latency 2002system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2003system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2004system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 2005system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2006system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2007system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2008system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 2009system.cpu1.l2cache.cache_copies 0 # number of cache copies performed 2010system.cpu1.l2cache.writebacks::writebacks 30696 # number of writebacks 2011system.cpu1.l2cache.writebacks::total 30696 # number of writebacks 2012system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 90 # number of ReadExReq MSHR hits 2013system.cpu1.l2cache.ReadExReq_mshr_hits::total 90 # number of ReadExReq MSHR hits 2014system.cpu1.l2cache.demand_mshr_hits::cpu1.data 90 # number of demand (read+write) MSHR hits 2015system.cpu1.l2cache.demand_mshr_hits::total 90 # number of demand (read+write) MSHR hits 2016system.cpu1.l2cache.overall_mshr_hits::cpu1.data 90 # number of overall MSHR hits 2017system.cpu1.l2cache.overall_mshr_hits::total 90 # number of overall MSHR hits 2018system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 314 # number of ReadReq MSHR misses 2019system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 266 # number of ReadReq MSHR misses 2020system.cpu1.l2cache.ReadReq_mshr_misses::total 580 # number of ReadReq MSHR misses 2021system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks 2031 # number of CleanEvict MSHR misses 2022system.cpu1.l2cache.CleanEvict_mshr_misses::total 2031 # number of CleanEvict MSHR misses 2023system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 23725 # number of HardPFReq MSHR misses 2024system.cpu1.l2cache.HardPFReq_mshr_misses::total 23725 # number of HardPFReq MSHR misses 2025system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 28095 # number of UpgradeReq MSHR misses 2026system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28095 # number of UpgradeReq MSHR misses 2027system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22537 # number of SCUpgradeReq MSHR misses 2028system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22537 # number of SCUpgradeReq MSHR misses 2029system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 2 # number of SCUpgradeFailReq MSHR misses 2030system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses 2031system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34625 # number of ReadExReq MSHR misses 2032system.cpu1.l2cache.ReadExReq_mshr_misses::total 34625 # number of ReadExReq MSHR misses 2033system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 13755 # number of ReadCleanReq MSHR misses 2034system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 13755 # number of ReadCleanReq MSHR misses 2035system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 68273 # number of ReadSharedReq MSHR misses 2036system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 68273 # number of ReadSharedReq MSHR misses 2037system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 314 # number of demand (read+write) MSHR misses 2038system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 266 # number of demand (read+write) MSHR misses 2039system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 13755 # number of demand (read+write) MSHR misses 2040system.cpu1.l2cache.demand_mshr_misses::cpu1.data 102898 # number of demand (read+write) MSHR misses 2041system.cpu1.l2cache.demand_mshr_misses::total 117233 # number of demand (read+write) MSHR misses 2042system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 314 # number of overall MSHR misses 2043system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 266 # number of overall MSHR misses 2044system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 13755 # number of overall MSHR misses 2045system.cpu1.l2cache.overall_mshr_misses::cpu1.data 102898 # number of overall MSHR misses 2046system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 23725 # number of overall MSHR misses 2047system.cpu1.l2cache.overall_mshr_misses::total 140958 # number of overall MSHR misses 2048system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable 2049system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 13773 # number of ReadReq MSHR uncacheable 2050system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 13950 # number of ReadReq MSHR uncacheable 2051system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 11227 # number of WriteReq MSHR uncacheable 2052system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 11227 # number of WriteReq MSHR uncacheable 2053system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses 2054system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 25000 # number of overall MSHR uncacheable misses 2055system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 25177 # number of overall MSHR uncacheable misses 2056system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4450500 # number of ReadReq MSHR miss cycles 2057system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3715000 # number of ReadReq MSHR miss cycles 2058system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 8165500 # number of ReadReq MSHR miss cycles 2059system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 839425646 # number of HardPFReq MSHR miss cycles 2060system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 839425646 # number of HardPFReq MSHR miss cycles 2061system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 455073500 # number of UpgradeReq MSHR miss cycles 2062system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 455073500 # number of UpgradeReq MSHR miss cycles 2063system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 349086500 # number of SCUpgradeReq MSHR miss cycles 2064system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 349086500 # number of SCUpgradeReq MSHR miss cycles 2065system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1972500 # number of SCUpgradeFailReq MSHR miss cycles 2066system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1972500 # number of SCUpgradeFailReq MSHR miss cycles 2067system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1119618000 # number of ReadExReq MSHR miss cycles 2068system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1119618000 # number of ReadExReq MSHR miss cycles 2069system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 409860500 # number of ReadCleanReq MSHR miss cycles 2070system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 409860500 # number of ReadCleanReq MSHR miss cycles 2071system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1081857000 # number of ReadSharedReq MSHR miss cycles 2072system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1081857000 # number of ReadSharedReq MSHR miss cycles 2073system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 4450500 # number of demand (read+write) MSHR miss cycles 2074system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3715000 # number of demand (read+write) MSHR miss cycles 2075system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 409860500 # number of demand (read+write) MSHR miss cycles 2076system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2201475000 # number of demand (read+write) MSHR miss cycles 2077system.cpu1.l2cache.demand_mshr_miss_latency::total 2619501000 # number of demand (read+write) MSHR miss cycles 2078system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 4450500 # number of overall MSHR miss cycles 2079system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3715000 # number of overall MSHR miss cycles 2080system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 409860500 # number of overall MSHR miss cycles 2081system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2201475000 # number of overall MSHR miss cycles 2082system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 839425646 # number of overall MSHR miss cycles 2083system.cpu1.l2cache.overall_mshr_miss_latency::total 3458926646 # number of overall MSHR miss cycles 2084system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 14012500 # number of ReadReq MSHR uncacheable cycles 2085system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2122532000 # number of ReadReq MSHR uncacheable cycles 2086system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2136544500 # number of ReadReq MSHR uncacheable cycles 2087system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 1684154500 # number of WriteReq MSHR uncacheable cycles 2088system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 1684154500 # number of WriteReq MSHR uncacheable cycles 2089system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 14012500 # number of overall MSHR uncacheable cycles 2090system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3806686500 # number of overall MSHR uncacheable cycles 2091system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3820699000 # number of overall MSHR uncacheable cycles 2092system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.092217 # mshr miss rate for ReadReq accesses 2093system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.134684 # mshr miss rate for ReadReq accesses 2094system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.107807 # mshr miss rate for ReadReq accesses 2095system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 2096system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 2097system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2098system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2099system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.950215 # mshr miss rate for UpgradeReq accesses 2100system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.950215 # mshr miss rate for UpgradeReq accesses 2101system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.963985 # mshr miss rate for SCUpgradeReq accesses 2102system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.963985 # mshr miss rate for SCUpgradeReq accesses 2103system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2104system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 2105system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.558162 # mshr miss rate for ReadExReq accesses 2106system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.558162 # mshr miss rate for ReadExReq accesses 2107system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.027181 # mshr miss rate for ReadCleanReq accesses 2108system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.027181 # mshr miss rate for ReadCleanReq accesses 2109system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.407432 # mshr miss rate for ReadSharedReq accesses 2110system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.407432 # mshr miss rate for ReadSharedReq accesses 2111system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.092217 # mshr miss rate for demand accesses 2112system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.134684 # mshr miss rate for demand accesses 2113system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.027181 # mshr miss rate for demand accesses 2114system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.448156 # mshr miss rate for demand accesses 2115system.cpu1.l2cache.demand_mshr_miss_rate::total 0.158202 # mshr miss rate for demand accesses 2116system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.092217 # mshr miss rate for overall accesses 2117system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.134684 # mshr miss rate for overall accesses 2118system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.027181 # mshr miss rate for overall accesses 2119system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.448156 # mshr miss rate for overall accesses 2120system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2121system.cpu1.l2cache.overall_mshr_miss_rate::total 0.190219 # mshr miss rate for overall accesses 2122system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14173.566879 # average ReadReq mshr miss latency 2123system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13966.165414 # average ReadReq mshr miss latency 2124system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14078.448276 # average ReadReq mshr miss latency 2125system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35381.481391 # average HardPFReq mshr miss latency 2126system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 35381.481391 # average HardPFReq mshr miss latency 2127system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16197.668624 # average UpgradeReq mshr miss latency 2128system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16197.668624 # average UpgradeReq mshr miss latency 2129system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15489.483960 # average SCUpgradeReq mshr miss latency 2130system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15489.483960 # average SCUpgradeReq mshr miss latency 2131system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 986250 # average SCUpgradeFailReq mshr miss latency 2132system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 986250 # average SCUpgradeFailReq mshr miss latency 2133system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32335.537906 # average ReadExReq mshr miss latency 2134system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32335.537906 # average ReadExReq mshr miss latency 2135system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29797.201018 # average ReadCleanReq mshr miss latency 2136system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29797.201018 # average ReadCleanReq mshr miss latency 2137system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 15846.044556 # average ReadSharedReq mshr miss latency 2138system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 15846.044556 # average ReadSharedReq mshr miss latency 2139system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14173.566879 # average overall mshr miss latency 2140system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13966.165414 # average overall mshr miss latency 2141system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29797.201018 # average overall mshr miss latency 2142system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21394.730704 # average overall mshr miss latency 2143system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 22344.399614 # average overall mshr miss latency 2144system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14173.566879 # average overall mshr miss latency 2145system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13966.165414 # average overall mshr miss latency 2146system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29797.201018 # average overall mshr miss latency 2147system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21394.730704 # average overall mshr miss latency 2148system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35381.481391 # average overall mshr miss latency 2149system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 24538.704054 # average overall mshr miss latency 2150system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 79166.666667 # average ReadReq mshr uncacheable latency 2151system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 154108.182676 # average ReadReq mshr uncacheable latency 2152system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 153157.311828 # average ReadReq mshr uncacheable latency 2153system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 150009.307918 # average WriteReq mshr uncacheable latency 2154system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 150009.307918 # average WriteReq mshr uncacheable latency 2155system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 79166.666667 # average overall mshr uncacheable latency 2156system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 152267.460000 # average overall mshr uncacheable latency 2157system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 151753.544902 # average overall mshr uncacheable latency 2158system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 2159system.cpu1.toL2Bus.trans_dist::ReadReq 53469 # Transaction distribution 2160system.cpu1.toL2Bus.trans_dist::ReadResp 734633 # Transaction distribution 2161system.cpu1.toL2Bus.trans_dist::WriteReq 30913 # Transaction distribution 2162system.cpu1.toL2Bus.trans_dist::WriteResp 11227 # Transaction distribution 2163system.cpu1.toL2Bus.trans_dist::Writeback 478531 # Transaction distribution 2164system.cpu1.toL2Bus.trans_dist::CleanEvict 680350 # Transaction distribution 2165system.cpu1.toL2Bus.trans_dist::HardPFReq 29761 # Transaction distribution 2166system.cpu1.toL2Bus.trans_dist::UpgradeReq 73690 # Transaction distribution 2167system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41411 # Transaction distribution 2168system.cpu1.toL2Bus.trans_dist::UpgradeResp 85868 # Transaction distribution 2169system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 55 # Transaction distribution 2170system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 93 # Transaction distribution 2171system.cpu1.toL2Bus.trans_dist::ReadExReq 84408 # Transaction distribution 2172system.cpu1.toL2Bus.trans_dist::ReadExResp 66733 # Transaction distribution 2173system.cpu1.toL2Bus.trans_dist::ReadCleanReq 506049 # Transaction distribution 2174system.cpu1.toL2Bus.trans_dist::ReadSharedReq 504061 # Transaction distribution 2175system.cpu1.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution 2176system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1509072 # Packet count per connected master and slave (bytes) 2177system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 874243 # Packet count per connected master and slave (bytes) 2178system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5299 # Packet count per connected master and slave (bytes) 2179system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9468 # Packet count per connected master and slave (bytes) 2180system.cpu1.toL2Bus.pkt_count::total 2398082 # Packet count per connected master and slave (bytes) 2181system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 32387844 # Cumulative packet size per connected master and slave (bytes) 2182system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24934344 # Cumulative packet size per connected master and slave (bytes) 2183system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7900 # Cumulative packet size per connected master and slave (bytes) 2184system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 13620 # Cumulative packet size per connected master and slave (bytes) 2185system.cpu1.toL2Bus.pkt_size::total 57343708 # Cumulative packet size per connected master and slave (bytes) 2186system.cpu1.toL2Bus.snoops 1094784 # Total snoops (count) 2187system.cpu1.toL2Bus.snoop_fanout::samples 2530004 # Request fanout histogram 2188system.cpu1.toL2Bus.snoop_fanout::mean 1.405048 # Request fanout histogram 2189system.cpu1.toL2Bus.snoop_fanout::stdev 0.490902 # Request fanout histogram 2190system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2191system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 2192system.cpu1.toL2Bus.snoop_fanout::1 1505230 59.50% 59.50% # Request fanout histogram 2193system.cpu1.toL2Bus.snoop_fanout::2 1024774 40.50% 100.00% # Request fanout histogram 2194system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2195system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 2196system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2197system.cpu1.toL2Bus.snoop_fanout::total 2530004 # Request fanout histogram 2198system.cpu1.toL2Bus.reqLayer0.occupancy 878944000 # Layer occupancy (ticks) 2199system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 2200system.cpu1.toL2Bus.snoopLayer0.occupancy 80122000 # Layer occupancy (ticks) 2201system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2202system.cpu1.toL2Bus.respLayer0.occupancy 759250500 # Layer occupancy (ticks) 2203system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2204system.cpu1.toL2Bus.respLayer1.occupancy 390308000 # Layer occupancy (ticks) 2205system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2206system.cpu1.toL2Bus.respLayer2.occupancy 3324000 # Layer occupancy (ticks) 2207system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2208system.cpu1.toL2Bus.respLayer3.occupancy 6063998 # Layer occupancy (ticks) 2209system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2210system.iobus.trans_dist::ReadReq 31015 # Transaction distribution 2211system.iobus.trans_dist::ReadResp 31015 # Transaction distribution 2212system.iobus.trans_dist::WriteReq 59422 # Transaction distribution 2213system.iobus.trans_dist::WriteResp 59422 # Transaction distribution 2214system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes) 2215system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 2216system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 2217system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 2218system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 2219system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 2220system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 2221system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2222system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2223system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2224system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 2225system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 2226system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 2227system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 2228system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 2229system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 2230system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 2231system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 2232system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 2233system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 2234system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 2235system.iobus.pkt_count_system.bridge.master::total 107916 # Packet count per connected master and slave (bytes) 2236system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes) 2237system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes) 2238system.iobus.pkt_count::total 180874 # Packet count per connected master and slave (bytes) 2239system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes) 2240system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 2241system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 2242system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 2243system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 2244system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 2245system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 2246system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2247system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2248system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2249system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 2250system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2251system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2252system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 2253system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 2254system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2255system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 2256system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 2257system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 2258system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 2259system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 2260system.iobus.pkt_size_system.bridge.master::total 162796 # Cumulative packet size per connected master and slave (bytes) 2261system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes) 2262system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes) 2263system.iobus.pkt_size::total 2484068 # Cumulative packet size per connected master and slave (bytes) 2264system.iobus.reqLayer0.occupancy 40091000 # Layer occupancy (ticks) 2265system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2266system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) 2267system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2268system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) 2269system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2270system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) 2271system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2272system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) 2273system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 2274system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) 2275system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 2276system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) 2277system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2278system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 2279system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2280system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 2281system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2282system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 2283system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 2284system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) 2285system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2286system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 2287system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 2288system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) 2289system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 2290system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) 2291system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 2292system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) 2293system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 2294system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 2295system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 2296system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) 2297system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2298system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) 2299system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2300system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) 2301system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2302system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) 2303system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 2304system.iobus.reqLayer27.occupancy 187549442 # Layer occupancy (ticks) 2305system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 2306system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 2307system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 2308system.iobus.respLayer0.occupancy 84718000 # Layer occupancy (ticks) 2309system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2310system.iobus.respLayer3.occupancy 36782000 # Layer occupancy (ticks) 2311system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2312system.iocache.tags.replacements 36445 # number of replacements 2313system.iocache.tags.tagsinuse 14.390664 # Cycle average of tags in use 2314system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 2315system.iocache.tags.sampled_refs 36461 # Sample count of references to valid blocks. 2316system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 2317system.iocache.tags.warmup_cycle 288350117000 # Cycle when the warmup percentage was hit. 2318system.iocache.tags.occ_blocks::realview.ide 14.390664 # Average occupied blocks per requestor 2319system.iocache.tags.occ_percent::realview.ide 0.899417 # Average percentage of cache occupancy 2320system.iocache.tags.occ_percent::total 0.899417 # Average percentage of cache occupancy 2321system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2322system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2323system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2324system.iocache.tags.tag_accesses 328311 # Number of tag accesses 2325system.iocache.tags.data_accesses 328311 # Number of data accesses 2326system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses 2327system.iocache.ReadReq_misses::total 255 # number of ReadReq misses 2328system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 2329system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 2330system.iocache.demand_misses::realview.ide 255 # number of demand (read+write) misses 2331system.iocache.demand_misses::total 255 # number of demand (read+write) misses 2332system.iocache.overall_misses::realview.ide 255 # number of overall misses 2333system.iocache.overall_misses::total 255 # number of overall misses 2334system.iocache.ReadReq_miss_latency::realview.ide 32656876 # number of ReadReq miss cycles 2335system.iocache.ReadReq_miss_latency::total 32656876 # number of ReadReq miss cycles 2336system.iocache.WriteLineReq_miss_latency::realview.ide 4281964566 # number of WriteLineReq miss cycles 2337system.iocache.WriteLineReq_miss_latency::total 4281964566 # number of WriteLineReq miss cycles 2338system.iocache.demand_miss_latency::realview.ide 32656876 # number of demand (read+write) miss cycles 2339system.iocache.demand_miss_latency::total 32656876 # number of demand (read+write) miss cycles 2340system.iocache.overall_miss_latency::realview.ide 32656876 # number of overall miss cycles 2341system.iocache.overall_miss_latency::total 32656876 # number of overall miss cycles 2342system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) 2343system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) 2344system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 2345system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) 2346system.iocache.demand_accesses::realview.ide 255 # number of demand (read+write) accesses 2347system.iocache.demand_accesses::total 255 # number of demand (read+write) accesses 2348system.iocache.overall_accesses::realview.ide 255 # number of overall (read+write) accesses 2349system.iocache.overall_accesses::total 255 # number of overall (read+write) accesses 2350system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2351system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2352system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 2353system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 2354system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2355system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2356system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2357system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2358system.iocache.ReadReq_avg_miss_latency::realview.ide 128066.180392 # average ReadReq miss latency 2359system.iocache.ReadReq_avg_miss_latency::total 128066.180392 # average ReadReq miss latency 2360system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118207.944070 # average WriteLineReq miss latency 2361system.iocache.WriteLineReq_avg_miss_latency::total 118207.944070 # average WriteLineReq miss latency 2362system.iocache.demand_avg_miss_latency::realview.ide 128066.180392 # average overall miss latency 2363system.iocache.demand_avg_miss_latency::total 128066.180392 # average overall miss latency 2364system.iocache.overall_avg_miss_latency::realview.ide 128066.180392 # average overall miss latency 2365system.iocache.overall_avg_miss_latency::total 128066.180392 # average overall miss latency 2366system.iocache.blocked_cycles::no_mshrs 265 # number of cycles access was blocked 2367system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2368system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked 2369system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2370system.iocache.avg_blocked_cycles::no_mshrs 132.500000 # average number of cycles each access was blocked 2371system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2372system.iocache.fast_writes 0 # number of fast writes performed 2373system.iocache.cache_copies 0 # number of cache copies performed 2374system.iocache.writebacks::writebacks 36190 # number of writebacks 2375system.iocache.writebacks::total 36190 # number of writebacks 2376system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses 2377system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses 2378system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses 2379system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses 2380system.iocache.demand_mshr_misses::realview.ide 255 # number of demand (read+write) MSHR misses 2381system.iocache.demand_mshr_misses::total 255 # number of demand (read+write) MSHR misses 2382system.iocache.overall_mshr_misses::realview.ide 255 # number of overall MSHR misses 2383system.iocache.overall_mshr_misses::total 255 # number of overall MSHR misses 2384system.iocache.ReadReq_mshr_miss_latency::realview.ide 19906876 # number of ReadReq MSHR miss cycles 2385system.iocache.ReadReq_mshr_miss_latency::total 19906876 # number of ReadReq MSHR miss cycles 2386system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2470764566 # number of WriteLineReq MSHR miss cycles 2387system.iocache.WriteLineReq_mshr_miss_latency::total 2470764566 # number of WriteLineReq MSHR miss cycles 2388system.iocache.demand_mshr_miss_latency::realview.ide 19906876 # number of demand (read+write) MSHR miss cycles 2389system.iocache.demand_mshr_miss_latency::total 19906876 # number of demand (read+write) MSHR miss cycles 2390system.iocache.overall_mshr_miss_latency::realview.ide 19906876 # number of overall MSHR miss cycles 2391system.iocache.overall_mshr_miss_latency::total 19906876 # number of overall MSHR miss cycles 2392system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2393system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2394system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 2395system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 2396system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2397system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2398system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2399system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 2400system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 78066.180392 # average ReadReq mshr miss latency 2401system.iocache.ReadReq_avg_mshr_miss_latency::total 78066.180392 # average ReadReq mshr miss latency 2402system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68207.944070 # average WriteLineReq mshr miss latency 2403system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68207.944070 # average WriteLineReq mshr miss latency 2404system.iocache.demand_avg_mshr_miss_latency::realview.ide 78066.180392 # average overall mshr miss latency 2405system.iocache.demand_avg_mshr_miss_latency::total 78066.180392 # average overall mshr miss latency 2406system.iocache.overall_avg_mshr_miss_latency::realview.ide 78066.180392 # average overall mshr miss latency 2407system.iocache.overall_avg_mshr_miss_latency::total 78066.180392 # average overall mshr miss latency 2408system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2409system.l2c.tags.replacements 130439 # number of replacements 2410system.l2c.tags.tagsinuse 63983.082008 # Cycle average of tags in use 2411system.l2c.tags.total_refs 387954 # Total number of references to valid blocks. 2412system.l2c.tags.sampled_refs 194793 # Sample count of references to valid blocks. 2413system.l2c.tags.avg_refs 1.991622 # Average number of references to valid blocks. 2414system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2415system.l2c.tags.occ_blocks::writebacks 12138.175325 # Average occupied blocks per requestor 2416system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.910023 # Average occupied blocks per requestor 2417system.l2c.tags.occ_blocks::cpu0.itb.walker 0.041062 # Average occupied blocks per requestor 2418system.l2c.tags.occ_blocks::cpu0.inst 7215.667264 # Average occupied blocks per requestor 2419system.l2c.tags.occ_blocks::cpu0.data 2903.196215 # Average occupied blocks per requestor 2420system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37504.021978 # Average occupied blocks per requestor 2421system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.955808 # Average occupied blocks per requestor 2422system.l2c.tags.occ_blocks::cpu1.inst 1528.247767 # Average occupied blocks per requestor 2423system.l2c.tags.occ_blocks::cpu1.data 561.168860 # Average occupied blocks per requestor 2424system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2127.697705 # Average occupied blocks per requestor 2425system.l2c.tags.occ_percent::writebacks 0.185214 # Average percentage of cache occupancy 2426system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000060 # Average percentage of cache occupancy 2427system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy 2428system.l2c.tags.occ_percent::cpu0.inst 0.110102 # Average percentage of cache occupancy 2429system.l2c.tags.occ_percent::cpu0.data 0.044299 # Average percentage of cache occupancy 2430system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.572266 # Average percentage of cache occupancy 2431system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy 2432system.l2c.tags.occ_percent::cpu1.inst 0.023319 # Average percentage of cache occupancy 2433system.l2c.tags.occ_percent::cpu1.data 0.008563 # Average percentage of cache occupancy 2434system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.032466 # Average percentage of cache occupancy 2435system.l2c.tags.occ_percent::total 0.976304 # Average percentage of cache occupancy 2436system.l2c.tags.occ_task_id_blocks::1022 32301 # Occupied blocks per task id 2437system.l2c.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id 2438system.l2c.tags.occ_task_id_blocks::1024 32046 # Occupied blocks per task id 2439system.l2c.tags.age_task_id_blocks_1022::2 164 # Occupied blocks per task id 2440system.l2c.tags.age_task_id_blocks_1022::3 4667 # Occupied blocks per task id 2441system.l2c.tags.age_task_id_blocks_1022::4 27470 # Occupied blocks per task id 2442system.l2c.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id 2443system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id 2444system.l2c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id 2445system.l2c.tags.age_task_id_blocks_1024::2 231 # Occupied blocks per task id 2446system.l2c.tags.age_task_id_blocks_1024::3 1924 # Occupied blocks per task id 2447system.l2c.tags.age_task_id_blocks_1024::4 29877 # Occupied blocks per task id 2448system.l2c.tags.occ_task_id_percent::1022 0.492874 # Percentage of cache occupancy per task id 2449system.l2c.tags.occ_task_id_percent::1023 0.000107 # Percentage of cache occupancy per task id 2450system.l2c.tags.occ_task_id_percent::1024 0.488983 # Percentage of cache occupancy per task id 2451system.l2c.tags.tag_accesses 5300600 # Number of tag accesses 2452system.l2c.tags.data_accesses 5300600 # Number of data accesses 2453system.l2c.Writeback_hits::writebacks 225955 # number of Writeback hits 2454system.l2c.Writeback_hits::total 225955 # number of Writeback hits 2455system.l2c.UpgradeReq_hits::cpu0.data 2137 # number of UpgradeReq hits 2456system.l2c.UpgradeReq_hits::cpu1.data 661 # number of UpgradeReq hits 2457system.l2c.UpgradeReq_hits::total 2798 # number of UpgradeReq hits 2458system.l2c.SCUpgradeReq_hits::cpu0.data 135 # number of SCUpgradeReq hits 2459system.l2c.SCUpgradeReq_hits::cpu1.data 145 # number of SCUpgradeReq hits 2460system.l2c.SCUpgradeReq_hits::total 280 # number of SCUpgradeReq hits 2461system.l2c.ReadExReq_hits::cpu0.data 3821 # number of ReadExReq hits 2462system.l2c.ReadExReq_hits::cpu1.data 1461 # number of ReadExReq hits 2463system.l2c.ReadExReq_hits::total 5282 # number of ReadExReq hits 2464system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 91 # number of ReadSharedReq hits 2465system.l2c.ReadSharedReq_hits::cpu0.itb.walker 51 # number of ReadSharedReq hits 2466system.l2c.ReadSharedReq_hits::cpu0.inst 29278 # number of ReadSharedReq hits 2467system.l2c.ReadSharedReq_hits::cpu0.data 45470 # number of ReadSharedReq hits 2468system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 44948 # number of ReadSharedReq hits 2469system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 27 # number of ReadSharedReq hits 2470system.l2c.ReadSharedReq_hits::cpu1.itb.walker 27 # number of ReadSharedReq hits 2471system.l2c.ReadSharedReq_hits::cpu1.inst 11381 # number of ReadSharedReq hits 2472system.l2c.ReadSharedReq_hits::cpu1.data 8374 # number of ReadSharedReq hits 2473system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 5310 # number of ReadSharedReq hits 2474system.l2c.ReadSharedReq_hits::total 144957 # number of ReadSharedReq hits 2475system.l2c.demand_hits::cpu0.dtb.walker 91 # number of demand (read+write) hits 2476system.l2c.demand_hits::cpu0.itb.walker 51 # number of demand (read+write) hits 2477system.l2c.demand_hits::cpu0.inst 29278 # number of demand (read+write) hits 2478system.l2c.demand_hits::cpu0.data 49291 # number of demand (read+write) hits 2479system.l2c.demand_hits::cpu0.l2cache.prefetcher 44948 # number of demand (read+write) hits 2480system.l2c.demand_hits::cpu1.dtb.walker 27 # number of demand (read+write) hits 2481system.l2c.demand_hits::cpu1.itb.walker 27 # number of demand (read+write) hits 2482system.l2c.demand_hits::cpu1.inst 11381 # number of demand (read+write) hits 2483system.l2c.demand_hits::cpu1.data 9835 # number of demand (read+write) hits 2484system.l2c.demand_hits::cpu1.l2cache.prefetcher 5310 # number of demand (read+write) hits 2485system.l2c.demand_hits::total 150239 # number of demand (read+write) hits 2486system.l2c.overall_hits::cpu0.dtb.walker 91 # number of overall hits 2487system.l2c.overall_hits::cpu0.itb.walker 51 # number of overall hits 2488system.l2c.overall_hits::cpu0.inst 29278 # number of overall hits 2489system.l2c.overall_hits::cpu0.data 49291 # number of overall hits 2490system.l2c.overall_hits::cpu0.l2cache.prefetcher 44948 # number of overall hits 2491system.l2c.overall_hits::cpu1.dtb.walker 27 # number of overall hits 2492system.l2c.overall_hits::cpu1.itb.walker 27 # number of overall hits 2493system.l2c.overall_hits::cpu1.inst 11381 # number of overall hits 2494system.l2c.overall_hits::cpu1.data 9835 # number of overall hits 2495system.l2c.overall_hits::cpu1.l2cache.prefetcher 5310 # number of overall hits 2496system.l2c.overall_hits::total 150239 # number of overall hits 2497system.l2c.UpgradeReq_misses::cpu0.data 8391 # number of UpgradeReq misses 2498system.l2c.UpgradeReq_misses::cpu1.data 2650 # number of UpgradeReq misses 2499system.l2c.UpgradeReq_misses::total 11041 # number of UpgradeReq misses 2500system.l2c.SCUpgradeReq_misses::cpu0.data 492 # number of SCUpgradeReq misses 2501system.l2c.SCUpgradeReq_misses::cpu1.data 1207 # number of SCUpgradeReq misses 2502system.l2c.SCUpgradeReq_misses::total 1699 # number of SCUpgradeReq misses 2503system.l2c.ReadExReq_misses::cpu0.data 11580 # number of ReadExReq misses 2504system.l2c.ReadExReq_misses::cpu1.data 8214 # number of ReadExReq misses 2505system.l2c.ReadExReq_misses::total 19794 # number of ReadExReq misses 2506system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 7 # number of ReadSharedReq misses 2507system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2 # number of ReadSharedReq misses 2508system.l2c.ReadSharedReq_misses::cpu0.inst 17402 # number of ReadSharedReq misses 2509system.l2c.ReadSharedReq_misses::cpu0.data 8820 # number of ReadSharedReq misses 2510system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 134398 # number of ReadSharedReq misses 2511system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1 # number of ReadSharedReq misses 2512system.l2c.ReadSharedReq_misses::cpu1.inst 2367 # number of ReadSharedReq misses 2513system.l2c.ReadSharedReq_misses::cpu1.data 942 # number of ReadSharedReq misses 2514system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 6249 # number of ReadSharedReq misses 2515system.l2c.ReadSharedReq_misses::total 170188 # number of ReadSharedReq misses 2516system.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses 2517system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses 2518system.l2c.demand_misses::cpu0.inst 17402 # number of demand (read+write) misses 2519system.l2c.demand_misses::cpu0.data 20400 # number of demand (read+write) misses 2520system.l2c.demand_misses::cpu0.l2cache.prefetcher 134398 # number of demand (read+write) misses 2521system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses 2522system.l2c.demand_misses::cpu1.inst 2367 # number of demand (read+write) misses 2523system.l2c.demand_misses::cpu1.data 9156 # number of demand (read+write) misses 2524system.l2c.demand_misses::cpu1.l2cache.prefetcher 6249 # number of demand (read+write) misses 2525system.l2c.demand_misses::total 189982 # number of demand (read+write) misses 2526system.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses 2527system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses 2528system.l2c.overall_misses::cpu0.inst 17402 # number of overall misses 2529system.l2c.overall_misses::cpu0.data 20400 # number of overall misses 2530system.l2c.overall_misses::cpu0.l2cache.prefetcher 134398 # number of overall misses 2531system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses 2532system.l2c.overall_misses::cpu1.inst 2367 # number of overall misses 2533system.l2c.overall_misses::cpu1.data 9156 # number of overall misses 2534system.l2c.overall_misses::cpu1.l2cache.prefetcher 6249 # number of overall misses 2535system.l2c.overall_misses::total 189982 # number of overall misses 2536system.l2c.UpgradeReq_miss_latency::cpu0.data 8210000 # number of UpgradeReq miss cycles 2537system.l2c.UpgradeReq_miss_latency::cpu1.data 2280000 # number of UpgradeReq miss cycles 2538system.l2c.UpgradeReq_miss_latency::total 10490000 # number of UpgradeReq miss cycles 2539system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1358000 # number of SCUpgradeReq miss cycles 2540system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1106500 # 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number of ReadSharedReq miss cycles 2551system.l2c.ReadSharedReq_miss_latency::cpu1.inst 194012000 # number of ReadSharedReq miss cycles 2552system.l2c.ReadSharedReq_miss_latency::cpu1.data 84119500 # number of ReadSharedReq miss cycles 2553system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 729023182 # number of ReadSharedReq miss cycles 2554system.l2c.ReadSharedReq_miss_latency::total 16261208649 # number of ReadSharedReq miss cycles 2555system.l2c.demand_miss_latency::cpu0.dtb.walker 606500 # number of demand (read+write) miss cycles 2556system.l2c.demand_miss_latency::cpu0.itb.walker 166000 # number of demand (read+write) miss cycles 2557system.l2c.demand_miss_latency::cpu0.inst 1402771500 # number of demand (read+write) miss cycles 2558system.l2c.demand_miss_latency::cpu0.data 1781756500 # number of demand (read+write) miss cycles 2559system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 13087577967 # number of demand (read+write) miss cycles 2560system.l2c.demand_miss_latency::cpu1.dtb.walker 82500 # number of demand (read+write) miss cycles 2561system.l2c.demand_miss_latency::cpu1.inst 194012000 # number of demand (read+write) miss cycles 2562system.l2c.demand_miss_latency::cpu1.data 750151000 # number of demand (read+write) miss cycles 2563system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 729023182 # number of demand (read+write) miss cycles 2564system.l2c.demand_miss_latency::total 17946147149 # number of demand (read+write) miss cycles 2565system.l2c.overall_miss_latency::cpu0.dtb.walker 606500 # number of overall miss cycles 2566system.l2c.overall_miss_latency::cpu0.itb.walker 166000 # number of overall miss cycles 2567system.l2c.overall_miss_latency::cpu0.inst 1402771500 # number of overall miss cycles 2568system.l2c.overall_miss_latency::cpu0.data 1781756500 # number of overall miss cycles 2569system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 13087577967 # number of overall miss cycles 2570system.l2c.overall_miss_latency::cpu1.dtb.walker 82500 # number of overall miss cycles 2571system.l2c.overall_miss_latency::cpu1.inst 194012000 # number of overall miss cycles 2572system.l2c.overall_miss_latency::cpu1.data 750151000 # number of overall miss cycles 2573system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 729023182 # number of overall miss cycles 2574system.l2c.overall_miss_latency::total 17946147149 # number of overall miss cycles 2575system.l2c.Writeback_accesses::writebacks 225955 # number of Writeback accesses(hits+misses) 2576system.l2c.Writeback_accesses::total 225955 # number of Writeback accesses(hits+misses) 2577system.l2c.UpgradeReq_accesses::cpu0.data 10528 # number of UpgradeReq accesses(hits+misses) 2578system.l2c.UpgradeReq_accesses::cpu1.data 3311 # number of UpgradeReq accesses(hits+misses) 2579system.l2c.UpgradeReq_accesses::total 13839 # number of UpgradeReq accesses(hits+misses) 2580system.l2c.SCUpgradeReq_accesses::cpu0.data 627 # number of SCUpgradeReq accesses(hits+misses) 2581system.l2c.SCUpgradeReq_accesses::cpu1.data 1352 # number of SCUpgradeReq accesses(hits+misses) 2582system.l2c.SCUpgradeReq_accesses::total 1979 # number of SCUpgradeReq accesses(hits+misses) 2583system.l2c.ReadExReq_accesses::cpu0.data 15401 # number of ReadExReq accesses(hits+misses) 2584system.l2c.ReadExReq_accesses::cpu1.data 9675 # number of ReadExReq accesses(hits+misses) 2585system.l2c.ReadExReq_accesses::total 25076 # number of ReadExReq accesses(hits+misses) 2586system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 98 # number of ReadSharedReq accesses(hits+misses) 2587system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 53 # number of ReadSharedReq accesses(hits+misses) 2588system.l2c.ReadSharedReq_accesses::cpu0.inst 46680 # number of ReadSharedReq accesses(hits+misses) 2589system.l2c.ReadSharedReq_accesses::cpu0.data 54290 # number of ReadSharedReq accesses(hits+misses) 2590system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 179346 # number of ReadSharedReq accesses(hits+misses) 2591system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 28 # number of ReadSharedReq accesses(hits+misses) 2592system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 27 # number of ReadSharedReq accesses(hits+misses) 2593system.l2c.ReadSharedReq_accesses::cpu1.inst 13748 # number of ReadSharedReq accesses(hits+misses) 2594system.l2c.ReadSharedReq_accesses::cpu1.data 9316 # number of ReadSharedReq accesses(hits+misses) 2595system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 11559 # number of ReadSharedReq accesses(hits+misses) 2596system.l2c.ReadSharedReq_accesses::total 315145 # number of ReadSharedReq accesses(hits+misses) 2597system.l2c.demand_accesses::cpu0.dtb.walker 98 # number of demand (read+write) accesses 2598system.l2c.demand_accesses::cpu0.itb.walker 53 # number of demand (read+write) accesses 2599system.l2c.demand_accesses::cpu0.inst 46680 # number of demand (read+write) accesses 2600system.l2c.demand_accesses::cpu0.data 69691 # number of demand (read+write) accesses 2601system.l2c.demand_accesses::cpu0.l2cache.prefetcher 179346 # number of demand (read+write) accesses 2602system.l2c.demand_accesses::cpu1.dtb.walker 28 # number of demand (read+write) accesses 2603system.l2c.demand_accesses::cpu1.itb.walker 27 # number of demand (read+write) accesses 2604system.l2c.demand_accesses::cpu1.inst 13748 # number of demand (read+write) accesses 2605system.l2c.demand_accesses::cpu1.data 18991 # number of demand (read+write) accesses 2606system.l2c.demand_accesses::cpu1.l2cache.prefetcher 11559 # number of demand (read+write) accesses 2607system.l2c.demand_accesses::total 340221 # number of demand (read+write) accesses 2608system.l2c.overall_accesses::cpu0.dtb.walker 98 # number of overall (read+write) accesses 2609system.l2c.overall_accesses::cpu0.itb.walker 53 # number of overall (read+write) accesses 2610system.l2c.overall_accesses::cpu0.inst 46680 # number of overall (read+write) accesses 2611system.l2c.overall_accesses::cpu0.data 69691 # number of overall (read+write) accesses 2612system.l2c.overall_accesses::cpu0.l2cache.prefetcher 179346 # number of overall (read+write) accesses 2613system.l2c.overall_accesses::cpu1.dtb.walker 28 # number of overall (read+write) accesses 2614system.l2c.overall_accesses::cpu1.itb.walker 27 # number of overall (read+write) accesses 2615system.l2c.overall_accesses::cpu1.inst 13748 # number of overall (read+write) accesses 2616system.l2c.overall_accesses::cpu1.data 18991 # number of overall (read+write) accesses 2617system.l2c.overall_accesses::cpu1.l2cache.prefetcher 11559 # number of overall (read+write) accesses 2618system.l2c.overall_accesses::total 340221 # number of overall (read+write) accesses 2619system.l2c.UpgradeReq_miss_rate::cpu0.data 0.797017 # miss rate for UpgradeReq accesses 2620system.l2c.UpgradeReq_miss_rate::cpu1.data 0.800362 # miss rate for UpgradeReq accesses 2621system.l2c.UpgradeReq_miss_rate::total 0.797818 # miss rate for UpgradeReq accesses 2622system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.784689 # miss rate for SCUpgradeReq accesses 2623system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.892751 # miss rate for SCUpgradeReq accesses 2624system.l2c.SCUpgradeReq_miss_rate::total 0.858514 # miss rate for SCUpgradeReq accesses 2625system.l2c.ReadExReq_miss_rate::cpu0.data 0.751899 # miss rate for ReadExReq accesses 2626system.l2c.ReadExReq_miss_rate::cpu1.data 0.848992 # miss rate for ReadExReq accesses 2627system.l2c.ReadExReq_miss_rate::total 0.789360 # miss rate for ReadExReq accesses 2628system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.071429 # miss rate for ReadSharedReq accesses 2629system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.037736 # miss rate for ReadSharedReq accesses 2630system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.372793 # miss rate for ReadSharedReq accesses 2631system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.162461 # miss rate for ReadSharedReq accesses 2632system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.749378 # miss rate for ReadSharedReq accesses 2633system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.035714 # miss rate for ReadSharedReq accesses 2634system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.172170 # miss rate for ReadSharedReq accesses 2635system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.101116 # miss rate for ReadSharedReq accesses 2636system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.540618 # miss rate for ReadSharedReq accesses 2637system.l2c.ReadSharedReq_miss_rate::total 0.540031 # miss rate for ReadSharedReq accesses 2638system.l2c.demand_miss_rate::cpu0.dtb.walker 0.071429 # miss rate for demand accesses 2639system.l2c.demand_miss_rate::cpu0.itb.walker 0.037736 # miss rate for demand accesses 2640system.l2c.demand_miss_rate::cpu0.inst 0.372793 # miss rate for demand accesses 2641system.l2c.demand_miss_rate::cpu0.data 0.292721 # miss rate for demand accesses 2642system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.749378 # miss rate for demand accesses 2643system.l2c.demand_miss_rate::cpu1.dtb.walker 0.035714 # miss rate for demand accesses 2644system.l2c.demand_miss_rate::cpu1.inst 0.172170 # miss rate for demand accesses 2645system.l2c.demand_miss_rate::cpu1.data 0.482123 # miss rate for demand accesses 2646system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.540618 # miss rate for demand accesses 2647system.l2c.demand_miss_rate::total 0.558408 # miss rate for demand accesses 2648system.l2c.overall_miss_rate::cpu0.dtb.walker 0.071429 # miss rate for overall accesses 2649system.l2c.overall_miss_rate::cpu0.itb.walker 0.037736 # miss rate for overall accesses 2650system.l2c.overall_miss_rate::cpu0.inst 0.372793 # miss rate for overall accesses 2651system.l2c.overall_miss_rate::cpu0.data 0.292721 # miss rate for overall accesses 2652system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.749378 # miss rate for overall accesses 2653system.l2c.overall_miss_rate::cpu1.dtb.walker 0.035714 # miss rate for overall accesses 2654system.l2c.overall_miss_rate::cpu1.inst 0.172170 # miss rate for overall accesses 2655system.l2c.overall_miss_rate::cpu1.data 0.482123 # miss rate for overall accesses 2656system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.540618 # miss rate for overall accesses 2657system.l2c.overall_miss_rate::total 0.558408 # miss rate for overall accesses 2658system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 978.429269 # average UpgradeReq miss latency 2659system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 860.377358 # average UpgradeReq miss latency 2660system.l2c.UpgradeReq_avg_miss_latency::total 950.095100 # average UpgradeReq miss latency 2661system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2760.162602 # average SCUpgradeReq miss latency 2662system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 916.735708 # average SCUpgradeReq miss latency 2663system.l2c.SCUpgradeReq_avg_miss_latency::total 1450.559152 # average SCUpgradeReq miss latency 2664system.l2c.ReadExReq_avg_miss_latency::cpu0.data 87988.514680 # average ReadExReq miss latency 2665system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81084.915997 # average ReadExReq miss latency 2666system.l2c.ReadExReq_avg_miss_latency::total 85123.699101 # average ReadExReq miss latency 2667system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 86642.857143 # average ReadSharedReq miss latency 2668system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 83000 # average ReadSharedReq miss latency 2669system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 80609.786231 # average ReadSharedReq miss latency 2670system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 86490.873016 # average ReadSharedReq miss latency 2671system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 97379.261351 # average ReadSharedReq miss latency 2672system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 82500 # average ReadSharedReq miss latency 2673system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 81965.356992 # average ReadSharedReq miss latency 2674system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 89298.832272 # average ReadSharedReq miss latency 2675system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 116662.375100 # average ReadSharedReq miss latency 2676system.l2c.ReadSharedReq_avg_miss_latency::total 95548.503120 # average ReadSharedReq miss latency 2677system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 86642.857143 # average overall miss latency 2678system.l2c.demand_avg_miss_latency::cpu0.itb.walker 83000 # average overall miss latency 2679system.l2c.demand_avg_miss_latency::cpu0.inst 80609.786231 # average overall miss latency 2680system.l2c.demand_avg_miss_latency::cpu0.data 87341.004902 # average overall miss latency 2681system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 97379.261351 # average overall miss latency 2682system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 82500 # average overall miss latency 2683system.l2c.demand_avg_miss_latency::cpu1.inst 81965.356992 # average overall miss latency 2684system.l2c.demand_avg_miss_latency::cpu1.data 81929.991263 # average overall miss latency 2685system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 116662.375100 # average overall miss latency 2686system.l2c.demand_avg_miss_latency::total 94462.355113 # average overall miss latency 2687system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 86642.857143 # average overall miss latency 2688system.l2c.overall_avg_miss_latency::cpu0.itb.walker 83000 # average overall miss latency 2689system.l2c.overall_avg_miss_latency::cpu0.inst 80609.786231 # average overall miss latency 2690system.l2c.overall_avg_miss_latency::cpu0.data 87341.004902 # average overall miss latency 2691system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 97379.261351 # average overall miss latency 2692system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 82500 # average overall miss latency 2693system.l2c.overall_avg_miss_latency::cpu1.inst 81965.356992 # average overall miss latency 2694system.l2c.overall_avg_miss_latency::cpu1.data 81929.991263 # average overall miss latency 2695system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 116662.375100 # average overall miss latency 2696system.l2c.overall_avg_miss_latency::total 94462.355113 # average overall miss latency 2697system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2698system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2699system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 2700system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2701system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2702system.l2c.avg_blocked_cycles::no_targets nan # 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number of overall MSHR hits 2716system.l2c.CleanEvict_mshr_misses::writebacks 3050 # number of CleanEvict MSHR misses 2717system.l2c.CleanEvict_mshr_misses::total 3050 # number of CleanEvict MSHR misses 2718system.l2c.UpgradeReq_mshr_misses::cpu0.data 8391 # number of UpgradeReq MSHR misses 2719system.l2c.UpgradeReq_mshr_misses::cpu1.data 2650 # number of UpgradeReq MSHR misses 2720system.l2c.UpgradeReq_mshr_misses::total 11041 # number of UpgradeReq MSHR misses 2721system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 492 # number of SCUpgradeReq MSHR misses 2722system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1207 # number of SCUpgradeReq MSHR misses 2723system.l2c.SCUpgradeReq_mshr_misses::total 1699 # number of SCUpgradeReq MSHR misses 2724system.l2c.ReadExReq_mshr_misses::cpu0.data 11580 # number of ReadExReq MSHR misses 2725system.l2c.ReadExReq_mshr_misses::cpu1.data 8214 # number of ReadExReq MSHR misses 2726system.l2c.ReadExReq_mshr_misses::total 19794 # number of ReadExReq MSHR misses 2727system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 7 # number of ReadSharedReq MSHR misses 2728system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 2 # number of ReadSharedReq MSHR misses 2729system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 17400 # number of ReadSharedReq MSHR misses 2730system.l2c.ReadSharedReq_mshr_misses::cpu0.data 8820 # number of ReadSharedReq MSHR misses 2731system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 134398 # number of ReadSharedReq MSHR misses 2732system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadSharedReq MSHR misses 2733system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2363 # number of ReadSharedReq MSHR misses 2734system.l2c.ReadSharedReq_mshr_misses::cpu1.data 942 # number of ReadSharedReq MSHR misses 2735system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 6249 # number of ReadSharedReq MSHR misses 2736system.l2c.ReadSharedReq_mshr_misses::total 170182 # number of ReadSharedReq MSHR misses 2737system.l2c.demand_mshr_misses::cpu0.dtb.walker 7 # number of demand (read+write) MSHR misses 2738system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses 2739system.l2c.demand_mshr_misses::cpu0.inst 17400 # number of demand (read+write) MSHR misses 2740system.l2c.demand_mshr_misses::cpu0.data 20400 # number of demand (read+write) MSHR misses 2741system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 134398 # number of demand (read+write) MSHR misses 2742system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses 2743system.l2c.demand_mshr_misses::cpu1.inst 2363 # number of demand (read+write) MSHR misses 2744system.l2c.demand_mshr_misses::cpu1.data 9156 # number of demand (read+write) MSHR misses 2745system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 6249 # number of demand (read+write) MSHR misses 2746system.l2c.demand_mshr_misses::total 189976 # number of demand (read+write) MSHR misses 2747system.l2c.overall_mshr_misses::cpu0.dtb.walker 7 # number of overall MSHR misses 2748system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses 2749system.l2c.overall_mshr_misses::cpu0.inst 17400 # number of overall MSHR misses 2750system.l2c.overall_mshr_misses::cpu0.data 20400 # number of overall MSHR misses 2751system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 134398 # number of overall MSHR misses 2752system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses 2753system.l2c.overall_mshr_misses::cpu1.inst 2363 # number of overall MSHR misses 2754system.l2c.overall_mshr_misses::cpu1.data 9156 # number of overall MSHR misses 2755system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 6249 # number of overall MSHR misses 2756system.l2c.overall_mshr_misses::total 189976 # number of overall MSHR misses 2757system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable 2758system.l2c.ReadReq_mshr_uncacheable::cpu0.data 21110 # number of ReadReq MSHR uncacheable 2759system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable 2760system.l2c.ReadReq_mshr_uncacheable::cpu1.data 13769 # number of ReadReq MSHR uncacheable 2761system.l2c.ReadReq_mshr_uncacheable::total 44078 # number of ReadReq MSHR uncacheable 2762system.l2c.WriteReq_mshr_uncacheable::cpu0.data 19686 # number of WriteReq MSHR uncacheable 2763system.l2c.WriteReq_mshr_uncacheable::cpu1.data 11227 # number of WriteReq MSHR uncacheable 2764system.l2c.WriteReq_mshr_uncacheable::total 30913 # number of WriteReq MSHR uncacheable 2765system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses 2766system.l2c.overall_mshr_uncacheable_misses::cpu0.data 40796 # number of overall MSHR uncacheable misses 2767system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses 2768system.l2c.overall_mshr_uncacheable_misses::cpu1.data 24996 # number of overall MSHR uncacheable misses 2769system.l2c.overall_mshr_uncacheable_misses::total 74991 # number of overall MSHR uncacheable misses 2770system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 174583000 # number of UpgradeReq MSHR miss cycles 2771system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 55064000 # number of UpgradeReq MSHR miss cycles 2772system.l2c.UpgradeReq_mshr_miss_latency::total 229647000 # number of UpgradeReq MSHR miss cycles 2773system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 10311000 # number of SCUpgradeReq MSHR miss cycles 2774system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 25083500 # number of SCUpgradeReq MSHR miss cycles 2775system.l2c.SCUpgradeReq_mshr_miss_latency::total 35394500 # number of SCUpgradeReq MSHR miss cycles 2776system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 903107000 # number of ReadExReq MSHR miss cycles 2777system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 583891500 # number of ReadExReq MSHR miss cycles 2778system.l2c.ReadExReq_mshr_miss_latency::total 1486998500 # number of ReadExReq MSHR miss cycles 2779system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 536500 # number of ReadSharedReq MSHR miss cycles 2780system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 146000 # number of ReadSharedReq MSHR miss cycles 2781system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1228508000 # number of ReadSharedReq MSHR miss cycles 2782system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 674649500 # number of ReadSharedReq MSHR miss cycles 2783system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 11743597967 # number of ReadSharedReq MSHR miss cycles 2784system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 72500 # number of ReadSharedReq MSHR miss cycles 2785system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 170183500 # number of ReadSharedReq MSHR miss cycles 2786system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 74699500 # number of ReadSharedReq MSHR miss cycles 2787system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 666533182 # number of ReadSharedReq MSHR miss cycles 2788system.l2c.ReadSharedReq_mshr_miss_latency::total 14558926649 # number of ReadSharedReq MSHR miss cycles 2789system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 536500 # number of demand (read+write) MSHR miss cycles 2790system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 146000 # number of demand (read+write) MSHR miss cycles 2791system.l2c.demand_mshr_miss_latency::cpu0.inst 1228508000 # number of demand (read+write) MSHR miss cycles 2792system.l2c.demand_mshr_miss_latency::cpu0.data 1577756500 # number of demand (read+write) MSHR miss cycles 2793system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 11743597967 # number of demand (read+write) MSHR miss cycles 2794system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 72500 # number of demand (read+write) MSHR miss cycles 2795system.l2c.demand_mshr_miss_latency::cpu1.inst 170183500 # number of demand (read+write) MSHR miss cycles 2796system.l2c.demand_mshr_miss_latency::cpu1.data 658591000 # number of demand (read+write) MSHR miss cycles 2797system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 666533182 # number of demand (read+write) MSHR miss cycles 2798system.l2c.demand_mshr_miss_latency::total 16045925149 # number of demand (read+write) MSHR miss cycles 2799system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 536500 # number of overall MSHR miss cycles 2800system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 146000 # number of overall MSHR miss cycles 2801system.l2c.overall_mshr_miss_latency::cpu0.inst 1228508000 # number of overall MSHR miss cycles 2802system.l2c.overall_mshr_miss_latency::cpu0.data 1577756500 # number of overall MSHR miss cycles 2803system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 11743597967 # number of overall MSHR miss cycles 2804system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 72500 # number of overall MSHR miss cycles 2805system.l2c.overall_mshr_miss_latency::cpu1.inst 170183500 # number of overall MSHR miss cycles 2806system.l2c.overall_mshr_miss_latency::cpu1.data 658591000 # number of overall MSHR miss cycles 2807system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 666533182 # number of overall MSHR miss cycles 2808system.l2c.overall_mshr_miss_latency::total 16045925149 # number of overall MSHR miss cycles 2809system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 570734000 # number of ReadReq MSHR uncacheable cycles 2810system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3884897500 # number of ReadReq MSHR uncacheable cycles 2811system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 10826500 # number of ReadReq MSHR uncacheable cycles 2812system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1874631500 # number of ReadReq MSHR uncacheable cycles 2813system.l2c.ReadReq_mshr_uncacheable_latency::total 6341089500 # number of ReadReq MSHR uncacheable cycles 2814system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2912289500 # number of WriteReq MSHR uncacheable cycles 2815system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1493293500 # number of WriteReq MSHR uncacheable cycles 2816system.l2c.WriteReq_mshr_uncacheable_latency::total 4405583000 # number of WriteReq MSHR uncacheable cycles 2817system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 570734000 # number of overall MSHR uncacheable cycles 2818system.l2c.overall_mshr_uncacheable_latency::cpu0.data 6797187000 # number of overall MSHR uncacheable cycles 2819system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 10826500 # number of overall MSHR uncacheable cycles 2820system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3367925000 # number of overall MSHR uncacheable cycles 2821system.l2c.overall_mshr_uncacheable_latency::total 10746672500 # number of overall MSHR uncacheable cycles 2822system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 2823system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 2824system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.797017 # mshr miss rate for UpgradeReq accesses 2825system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.800362 # mshr miss rate for UpgradeReq accesses 2826system.l2c.UpgradeReq_mshr_miss_rate::total 0.797818 # mshr miss rate for UpgradeReq accesses 2827system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.784689 # mshr miss rate for SCUpgradeReq accesses 2828system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.892751 # mshr miss rate for SCUpgradeReq accesses 2829system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.858514 # mshr miss rate for SCUpgradeReq accesses 2830system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.751899 # mshr miss rate for ReadExReq accesses 2831system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.848992 # mshr miss rate for ReadExReq accesses 2832system.l2c.ReadExReq_mshr_miss_rate::total 0.789360 # mshr miss rate for ReadExReq accesses 2833system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.071429 # mshr miss rate for ReadSharedReq accesses 2834system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.037736 # mshr miss rate for ReadSharedReq accesses 2835system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.372751 # mshr miss rate for ReadSharedReq accesses 2836system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.162461 # mshr miss rate for ReadSharedReq accesses 2837system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.749378 # mshr miss rate for ReadSharedReq accesses 2838system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.035714 # mshr miss rate for ReadSharedReq accesses 2839system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.171880 # mshr miss rate for ReadSharedReq accesses 2840system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.101116 # mshr miss rate for ReadSharedReq accesses 2841system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.540618 # mshr miss rate for ReadSharedReq accesses 2842system.l2c.ReadSharedReq_mshr_miss_rate::total 0.540012 # mshr miss rate for ReadSharedReq accesses 2843system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.071429 # mshr miss rate for demand accesses 2844system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.037736 # mshr miss rate for demand accesses 2845system.l2c.demand_mshr_miss_rate::cpu0.inst 0.372751 # mshr miss rate for demand accesses 2846system.l2c.demand_mshr_miss_rate::cpu0.data 0.292721 # mshr miss rate for demand accesses 2847system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.749378 # mshr miss rate for demand accesses 2848system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.035714 # mshr miss rate for demand accesses 2849system.l2c.demand_mshr_miss_rate::cpu1.inst 0.171880 # mshr miss rate for demand accesses 2850system.l2c.demand_mshr_miss_rate::cpu1.data 0.482123 # mshr miss rate for demand accesses 2851system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.540618 # mshr miss rate for demand accesses 2852system.l2c.demand_mshr_miss_rate::total 0.558390 # mshr miss rate for demand accesses 2853system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.071429 # mshr miss rate for overall accesses 2854system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.037736 # mshr miss rate for overall accesses 2855system.l2c.overall_mshr_miss_rate::cpu0.inst 0.372751 # mshr miss rate for overall accesses 2856system.l2c.overall_mshr_miss_rate::cpu0.data 0.292721 # mshr miss rate for overall accesses 2857system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.749378 # mshr miss rate for overall accesses 2858system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.035714 # mshr miss rate for overall accesses 2859system.l2c.overall_mshr_miss_rate::cpu1.inst 0.171880 # mshr miss rate for overall accesses 2860system.l2c.overall_mshr_miss_rate::cpu1.data 0.482123 # mshr miss rate for overall accesses 2861system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.540618 # mshr miss rate for overall accesses 2862system.l2c.overall_mshr_miss_rate::total 0.558390 # mshr miss rate for overall accesses 2863system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20805.982600 # average UpgradeReq mshr miss latency 2864system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20778.867925 # average UpgradeReq mshr miss latency 2865system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20799.474685 # average UpgradeReq mshr miss latency 2866system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20957.317073 # average SCUpgradeReq mshr miss latency 2867system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20781.690141 # average SCUpgradeReq mshr miss latency 2868system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20832.548558 # average SCUpgradeReq mshr miss latency 2869system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 77988.514680 # average ReadExReq mshr miss latency 2870system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71084.915997 # average ReadExReq mshr miss latency 2871system.l2c.ReadExReq_avg_mshr_miss_latency::total 75123.699101 # average ReadExReq mshr miss latency 2872system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 76642.857143 # average ReadSharedReq mshr miss latency 2873system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 73000 # average ReadSharedReq mshr miss latency 2874system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 70603.908046 # average ReadSharedReq mshr miss latency 2875system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 76490.873016 # average ReadSharedReq mshr miss latency 2876system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87379.261351 # average ReadSharedReq mshr miss latency 2877system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 72500 # average ReadSharedReq mshr miss latency 2878system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 72020.101566 # average ReadSharedReq mshr miss latency 2879system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 79298.832272 # average ReadSharedReq mshr miss latency 2880system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 106662.375100 # average ReadSharedReq mshr miss latency 2881system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 85549.157073 # average ReadSharedReq mshr miss latency 2882system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 76642.857143 # average overall mshr miss latency 2883system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 73000 # average overall mshr miss latency 2884system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 70603.908046 # average overall mshr miss latency 2885system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77341.004902 # average overall mshr miss latency 2886system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87379.261351 # average overall mshr miss latency 2887system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 72500 # average overall mshr miss latency 2888system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72020.101566 # average overall mshr miss latency 2889system.l2c.demand_avg_mshr_miss_latency::cpu1.data 71929.991263 # average overall mshr miss latency 2890system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 106662.375100 # average overall mshr miss latency 2891system.l2c.demand_avg_mshr_miss_latency::total 84462.906625 # average overall mshr miss latency 2892system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 76642.857143 # average overall mshr miss latency 2893system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 73000 # average overall mshr miss latency 2894system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 70603.908046 # average overall mshr miss latency 2895system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77341.004902 # average overall mshr miss latency 2896system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87379.261351 # average overall mshr miss latency 2897system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 72500 # average overall mshr miss latency 2898system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72020.101566 # average overall mshr miss latency 2899system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71929.991263 # average overall mshr miss latency 2900system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 106662.375100 # average overall mshr miss latency 2901system.l2c.overall_avg_mshr_miss_latency::total 84462.906625 # average overall mshr miss latency 2902system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63260.252716 # average ReadReq mshr uncacheable latency 2903system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 184031.146376 # average ReadReq mshr uncacheable latency 2904system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 61166.666667 # average ReadReq mshr uncacheable latency 2905system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 136148.703610 # average ReadReq mshr uncacheable latency 2906system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 143860.644766 # average ReadReq mshr uncacheable latency 2907system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 147937.087270 # average WriteReq mshr uncacheable latency 2908system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 133009.129776 # average WriteReq mshr uncacheable latency 2909system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 142515.543622 # average WriteReq mshr uncacheable latency 2910system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63260.252716 # average overall mshr uncacheable latency 2911system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 166614.055300 # average overall mshr uncacheable latency 2912system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 61166.666667 # average overall mshr uncacheable latency 2913system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 134738.558169 # average overall mshr uncacheable latency 2914system.l2c.overall_avg_mshr_uncacheable_latency::total 143306.163406 # average overall mshr uncacheable latency 2915system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 2916system.membus.trans_dist::ReadReq 44078 # Transaction distribution 2917system.membus.trans_dist::ReadResp 214515 # Transaction distribution 2918system.membus.trans_dist::WriteReq 30913 # Transaction distribution 2919system.membus.trans_dist::WriteResp 30913 # Transaction distribution 2920system.membus.trans_dist::Writeback 136511 # Transaction distribution 2921system.membus.trans_dist::CleanEvict 15728 # Transaction distribution 2922system.membus.trans_dist::UpgradeReq 75283 # Transaction distribution 2923system.membus.trans_dist::SCUpgradeReq 40251 # Transaction distribution 2924system.membus.trans_dist::UpgradeResp 12822 # Transaction distribution 2925system.membus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution 2926system.membus.trans_dist::ReadExReq 40262 # Transaction distribution 2927system.membus.trans_dist::ReadExResp 19712 # Transaction distribution 2928system.membus.trans_dist::ReadSharedReq 170437 # Transaction distribution 2929system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 2930system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution 2931system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107916 # Packet count per connected master and slave (bytes) 2932system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) 2933system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13732 # Packet count per connected master and slave (bytes) 2934system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 672670 # Packet count per connected master and slave (bytes) 2935system.membus.pkt_count_system.l2c.mem_side::total 794352 # Packet count per connected master and slave (bytes) 2936system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108921 # Packet count per connected master and slave (bytes) 2937system.membus.pkt_count_system.iocache.mem_side::total 108921 # Packet count per connected master and slave (bytes) 2938system.membus.pkt_count::total 903273 # Packet count per connected master and slave (bytes) 2939system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162796 # Cumulative packet size per connected master and slave (bytes) 2940system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) 2941system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27464 # Cumulative packet size per connected master and slave (bytes) 2942system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18608200 # Cumulative packet size per connected master and slave (bytes) 2943system.membus.pkt_size_system.l2c.mem_side::total 18798528 # Cumulative packet size per connected master and slave (bytes) 2944system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) 2945system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) 2946system.membus.pkt_size::total 21115648 # Cumulative packet size per connected master and slave (bytes) 2947system.membus.snoops 123870 # Total snoops (count) 2948system.membus.snoop_fanout::samples 589976 # Request fanout histogram 2949system.membus.snoop_fanout::mean 1 # Request fanout histogram 2950system.membus.snoop_fanout::stdev 0 # Request fanout histogram 2951system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2952system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 2953system.membus.snoop_fanout::1 589976 100.00% 100.00% # Request fanout histogram 2954system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 2955system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2956system.membus.snoop_fanout::min_value 1 # Request fanout histogram 2957system.membus.snoop_fanout::max_value 1 # Request fanout histogram 2958system.membus.snoop_fanout::total 589976 # Request fanout histogram 2959system.membus.reqLayer0.occupancy 88273000 # Layer occupancy (ticks) 2960system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 2961system.membus.reqLayer1.occupancy 19000 # Layer occupancy (ticks) 2962system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 2963system.membus.reqLayer2.occupancy 11464500 # Layer occupancy (ticks) 2964system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 2965system.membus.reqLayer5.occupancy 1021914451 # Layer occupancy (ticks) 2966system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 2967system.membus.respLayer2.occupancy 1141120383 # Layer occupancy (ticks) 2968system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 2969system.membus.respLayer3.occupancy 64390592 # Layer occupancy (ticks) 2970system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 2971system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 2972system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 2973system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 2974system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 2975system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 2976system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 2977system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 2978system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 2979system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 2980system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 2981system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 2982system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 2983system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 2984system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 2985system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 2986system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 2987system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 2988system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 2989system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 2990system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 2991system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 2992system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 2993system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 2994system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 2995system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 2996system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 2997system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 2998system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 2999system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 3000system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 3001system.realview.ethernet.droppedPackets 0 # number of packets dropped 3002system.toL2Bus.trans_dist::ReadReq 44082 # Transaction distribution 3003system.toL2Bus.trans_dist::ReadResp 479204 # Transaction distribution 3004system.toL2Bus.trans_dist::WriteReq 30913 # Transaction distribution 3005system.toL2Bus.trans_dist::WriteResp 30913 # Transaction distribution 3006system.toL2Bus.trans_dist::Writeback 362509 # Transaction distribution 3007system.toL2Bus.trans_dist::CleanEvict 82484 # Transaction distribution 3008system.toL2Bus.trans_dist::UpgradeReq 77999 # Transaction distribution 3009system.toL2Bus.trans_dist::SCUpgradeReq 40531 # Transaction distribution 3010system.toL2Bus.trans_dist::UpgradeResp 118530 # Transaction distribution 3011system.toL2Bus.trans_dist::SCUpgradeFailReq 93 # Transaction distribution 3012system.toL2Bus.trans_dist::UpgradeFailResp 93 # Transaction distribution 3013system.toL2Bus.trans_dist::ReadExReq 51218 # Transaction distribution 3014system.toL2Bus.trans_dist::ReadExResp 51218 # Transaction distribution 3015system.toL2Bus.trans_dist::ReadSharedReq 435137 # Transaction distribution 3016system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution 3017system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1069100 # Packet count per connected master and slave (bytes) 3018system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 319954 # Packet count per connected master and slave (bytes) 3019system.toL2Bus.pkt_count::total 1389054 # Packet count per connected master and slave (bytes) 3020system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 31596740 # Cumulative packet size per connected master and slave (bytes) 3021system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4900924 # Cumulative packet size per connected master and slave (bytes) 3022system.toL2Bus.pkt_size::total 36497664 # Cumulative packet size per connected master and slave (bytes) 3023system.toL2Bus.snoops 452334 # Total snoops (count) 3024system.toL2Bus.snoop_fanout::samples 1194337 # Request fanout histogram 3025system.toL2Bus.snoop_fanout::mean 1.170309 # Request fanout histogram 3026system.toL2Bus.snoop_fanout::stdev 0.375904 # Request fanout histogram 3027system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3028system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 3029system.toL2Bus.snoop_fanout::1 990931 82.97% 82.97% # Request fanout histogram 3030system.toL2Bus.snoop_fanout::2 203406 17.03% 100.00% # Request fanout histogram 3031system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3032system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 3033system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 3034system.toL2Bus.snoop_fanout::total 1194337 # Request fanout histogram 3035system.toL2Bus.reqLayer0.occupancy 799819351 # Layer occupancy (ticks) 3036system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 3037system.toL2Bus.snoopLayer0.occupancy 360000 # Layer occupancy (ticks) 3038system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3039system.toL2Bus.respLayer0.occupancy 609335323 # Layer occupancy (ticks) 3040system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3041system.toL2Bus.respLayer1.occupancy 239074701 # Layer occupancy (ticks) 3042system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3043 3044---------- End Simulation Statistics ---------- 3045