stats.txt revision 10628:c9b7e0c69f88
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.868319 # Number of seconds simulated 4sim_ticks 2868318696500 # Number of ticks simulated 5final_tick 2868318696500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 534652 # Simulator instruction rate (inst/s) 8host_op_rate 646675 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 11631340017 # Simulator tick rate (ticks/s) 10host_mem_usage 586476 # Number of bytes of host memory used 11host_seconds 246.60 # Real time elapsed on the host 12sim_insts 131846562 # Number of instructions simulated 13sim_ops 159471778 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 1173796 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 1283584 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 8628800 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.inst 156308 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.data 605472 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.l2cache.prefetcher 378048 # Number of bytes read from this memory 25system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 26system.physmem.bytes_read::total 12227608 # Number of bytes read from this memory 27system.physmem.bytes_inst_read::cpu0.inst 1173796 # Number of instructions bytes read from this memory 28system.physmem.bytes_inst_read::cpu1.inst 156308 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::total 1330104 # Number of instructions bytes read from this memory 30system.physmem.bytes_written::writebacks 8654400 # Number of bytes written to this memory 31system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory 32system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory 33system.physmem.bytes_written::total 8672144 # Number of bytes written to this memory 34system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.inst 26794 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.data 20582 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.l2cache.prefetcher 134825 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.inst 2597 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.data 9484 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.l2cache.prefetcher 5907 # Number of read requests responded to by this memory 43system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 44system.physmem.num_reads::total 200214 # Number of read requests responded to by this memory 45system.physmem.num_writes::writebacks 135225 # Number of write requests responded to by this memory 46system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory 47system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory 48system.physmem.num_writes::total 139661 # Number of write requests responded to by this memory 49system.physmem.bw_read::cpu0.dtb.walker 156 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu0.inst 409228 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.data 447504 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.l2cache.prefetcher 3008313 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu1.dtb.walker 22 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu1.inst 54495 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu1.data 211090 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.l2cache.prefetcher 131801 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::realview.ide 335 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::total 4262988 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_inst_read::cpu0.inst 409228 # Instruction read bandwidth from this memory (bytes/s) 61system.physmem.bw_inst_read::cpu1.inst 54495 # Instruction read bandwidth from this memory (bytes/s) 62system.physmem.bw_inst_read::total 463723 # Instruction read bandwidth from this memory (bytes/s) 63system.physmem.bw_write::writebacks 3017238 # Write bandwidth from this memory (bytes/s) 64system.physmem.bw_write::cpu0.data 6172 # Write bandwidth from this memory (bytes/s) 65system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) 66system.physmem.bw_write::total 3023424 # Write bandwidth from this memory (bytes/s) 67system.physmem.bw_total::writebacks 3017238 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::cpu0.dtb.walker 156 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) 70system.physmem.bw_total::cpu0.inst 409228 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu0.data 453676 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.l2cache.prefetcher 3008313 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu1.dtb.walker 22 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu1.inst 54495 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu1.data 211103 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu1.l2cache.prefetcher 131801 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::realview.ide 335 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::total 7286412 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.readReqs 200214 # Number of read requests accepted 80system.physmem.writeReqs 175885 # Number of write requests accepted 81system.physmem.readBursts 200214 # Number of DRAM read bursts, including those serviced by the write queue 82system.physmem.writeBursts 175885 # Number of DRAM write bursts, including those merged in the write queue 83system.physmem.bytesReadDRAM 12804096 # Total number of bytes read from DRAM 84system.physmem.bytesReadWrQ 9600 # Total number of bytes read from write queue 85system.physmem.bytesWritten 10892544 # Total number of bytes written to DRAM 86system.physmem.bytesReadSys 12227608 # Total read bytes from the system interface side 87system.physmem.bytesWrittenSys 10990480 # Total written bytes from the system interface side 88system.physmem.servicedByWrQ 150 # Number of DRAM read bursts serviced by the write queue 89system.physmem.mergedWrBursts 5671 # Number of DRAM write bursts merged with an existing one 90system.physmem.neitherReadNorWriteReqs 13850 # Number of requests that are neither read nor write 91system.physmem.perBankRdBursts::0 12188 # Per bank write bursts 92system.physmem.perBankRdBursts::1 12046 # Per bank write bursts 93system.physmem.perBankRdBursts::2 12591 # Per bank write bursts 94system.physmem.perBankRdBursts::3 12330 # Per bank write bursts 95system.physmem.perBankRdBursts::4 20750 # Per bank write bursts 96system.physmem.perBankRdBursts::5 12582 # Per bank write bursts 97system.physmem.perBankRdBursts::6 12043 # Per bank write bursts 98system.physmem.perBankRdBursts::7 12246 # Per bank write bursts 99system.physmem.perBankRdBursts::8 12442 # Per bank write bursts 100system.physmem.perBankRdBursts::9 12402 # Per bank write bursts 101system.physmem.perBankRdBursts::10 11722 # Per bank write bursts 102system.physmem.perBankRdBursts::11 11146 # Per bank write bursts 103system.physmem.perBankRdBursts::12 11467 # Per bank write bursts 104system.physmem.perBankRdBursts::13 11916 # Per bank write bursts 105system.physmem.perBankRdBursts::14 10852 # Per bank write bursts 106system.physmem.perBankRdBursts::15 11341 # Per bank write bursts 107system.physmem.perBankWrBursts::0 10835 # Per bank write bursts 108system.physmem.perBankWrBursts::1 11264 # Per bank write bursts 109system.physmem.perBankWrBursts::2 11493 # Per bank write bursts 110system.physmem.perBankWrBursts::3 10899 # Per bank write bursts 111system.physmem.perBankWrBursts::4 10487 # Per bank write bursts 112system.physmem.perBankWrBursts::5 11152 # Per bank write bursts 113system.physmem.perBankWrBursts::6 11024 # Per bank write bursts 114system.physmem.perBankWrBursts::7 10595 # Per bank write bursts 115system.physmem.perBankWrBursts::8 10782 # Per bank write bursts 116system.physmem.perBankWrBursts::9 10958 # Per bank write bursts 117system.physmem.perBankWrBursts::10 10716 # Per bank write bursts 118system.physmem.perBankWrBursts::11 10408 # Per bank write bursts 119system.physmem.perBankWrBursts::12 10444 # Per bank write bursts 120system.physmem.perBankWrBursts::13 9906 # Per bank write bursts 121system.physmem.perBankWrBursts::14 9416 # Per bank write bursts 122system.physmem.perBankWrBursts::15 9817 # Per bank write bursts 123system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 124system.physmem.numWrRetry 1 # Number of times write queue was full causing retry 125system.physmem.totGap 2868318254500 # Total gap between requests 126system.physmem.readPktSize::0 0 # Read request sizes (log2) 127system.physmem.readPktSize::1 0 # Read request sizes (log2) 128system.physmem.readPktSize::2 9742 # Read request sizes (log2) 129system.physmem.readPktSize::3 28 # Read request sizes (log2) 130system.physmem.readPktSize::4 0 # Read request sizes (log2) 131system.physmem.readPktSize::5 0 # Read request sizes (log2) 132system.physmem.readPktSize::6 190444 # Read request sizes (log2) 133system.physmem.writePktSize::0 0 # Write request sizes (log2) 134system.physmem.writePktSize::1 0 # Write request sizes (log2) 135system.physmem.writePktSize::2 4436 # Write request sizes (log2) 136system.physmem.writePktSize::3 0 # Write request sizes (log2) 137system.physmem.writePktSize::4 0 # Write request sizes (log2) 138system.physmem.writePktSize::5 0 # Write request sizes (log2) 139system.physmem.writePktSize::6 171449 # Write request sizes (log2) 140system.physmem.rdQLenPdf::0 138850 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::1 16077 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::2 10399 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::3 9072 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::4 7297 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::5 5697 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::6 4782 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::7 4036 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::8 3549 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::9 129 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::10 88 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::11 52 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::12 20 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::13 8 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::14 3 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 172system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::15 2909 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::16 4636 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::17 6298 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::18 8259 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::19 9096 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::20 10239 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::21 10826 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::22 11796 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::23 11771 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::24 12530 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::25 11837 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::26 11533 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::27 10810 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::28 10665 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::29 8741 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::30 8334 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::31 8094 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::32 7730 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::33 533 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::34 391 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::35 344 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::36 288 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::37 237 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::38 218 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::39 213 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::40 197 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::41 169 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::42 169 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::43 151 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::44 144 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::45 133 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::46 120 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::47 110 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::48 106 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::49 107 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::50 93 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::51 83 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::52 65 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::53 60 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::54 46 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::55 26 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::56 22 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::57 23 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::58 15 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::59 13 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::60 8 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::61 5 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::62 4 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see 236system.physmem.bytesPerActivate::samples 90415 # Bytes accessed per row activation 237system.physmem.bytesPerActivate::mean 262.086778 # Bytes accessed per row activation 238system.physmem.bytesPerActivate::gmean 144.561031 # Bytes accessed per row activation 239system.physmem.bytesPerActivate::stdev 323.181928 # Bytes accessed per row activation 240system.physmem.bytesPerActivate::0-127 46335 51.25% 51.25% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::128-255 17813 19.70% 70.95% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::256-383 6067 6.71% 77.66% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::384-511 3600 3.98% 81.64% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::512-639 2534 2.80% 84.44% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::640-767 1568 1.73% 86.18% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::768-895 1031 1.14% 87.32% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::896-1023 985 1.09% 88.41% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::1024-1151 10482 11.59% 100.00% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::total 90415 # Bytes accessed per row activation 250system.physmem.rdPerTurnAround::samples 7120 # Reads before turning the bus around for writes 251system.physmem.rdPerTurnAround::mean 28.098736 # Reads before turning the bus around for writes 252system.physmem.rdPerTurnAround::stdev 516.724228 # Reads before turning the bus around for writes 253system.physmem.rdPerTurnAround::0-2047 7117 99.96% 99.96% # Reads before turning the bus around for writes 254system.physmem.rdPerTurnAround::2048-4095 2 0.03% 99.99% # Reads before turning the bus around for writes 255system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::total 7120 # Reads before turning the bus around for writes 257system.physmem.wrPerTurnAround::samples 7120 # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::mean 23.903933 # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::gmean 20.122109 # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::stdev 22.073987 # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::16-19 5764 80.96% 80.96% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::20-23 237 3.33% 84.28% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::24-27 43 0.60% 84.89% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::28-31 234 3.29% 88.17% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::32-35 121 1.70% 89.87% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::36-39 62 0.87% 90.74% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::40-43 31 0.44% 91.18% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::44-47 36 0.51% 91.69% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::48-51 117 1.64% 93.33% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::52-55 18 0.25% 93.58% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::56-59 25 0.35% 93.93% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::60-63 16 0.22% 94.16% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::64-67 40 0.56% 94.72% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::68-71 10 0.14% 94.86% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::72-75 17 0.24% 95.10% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::76-79 28 0.39% 95.49% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::80-83 58 0.81% 96.31% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::84-87 14 0.20% 96.50% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::88-91 7 0.10% 96.60% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::92-95 6 0.08% 96.69% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::96-99 88 1.24% 97.92% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::100-103 4 0.06% 97.98% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::104-107 12 0.17% 98.15% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::108-111 1 0.01% 98.16% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::112-115 15 0.21% 98.37% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::116-119 6 0.08% 98.46% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::120-123 14 0.20% 98.65% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::124-127 9 0.13% 98.78% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::128-131 35 0.49% 99.27% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::132-135 6 0.08% 99.35% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::136-139 1 0.01% 99.37% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::140-143 4 0.06% 99.42% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::144-147 8 0.11% 99.54% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::148-151 2 0.03% 99.56% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::152-155 3 0.04% 99.61% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::156-159 1 0.01% 99.62% # Writes before turning the bus around for reads 297system.physmem.wrPerTurnAround::160-163 8 0.11% 99.73% # Writes before turning the bus around for reads 298system.physmem.wrPerTurnAround::164-167 2 0.03% 99.76% # Writes before turning the bus around for reads 299system.physmem.wrPerTurnAround::168-171 1 0.01% 99.78% # Writes before turning the bus around for reads 300system.physmem.wrPerTurnAround::172-175 1 0.01% 99.79% # Writes before turning the bus around for reads 301system.physmem.wrPerTurnAround::176-179 4 0.06% 99.85% # Writes before turning the bus around for reads 302system.physmem.wrPerTurnAround::180-183 1 0.01% 99.86% # Writes before turning the bus around for reads 303system.physmem.wrPerTurnAround::184-187 1 0.01% 99.87% # Writes before turning the bus around for reads 304system.physmem.wrPerTurnAround::196-199 1 0.01% 99.89% # Writes before turning the bus around for reads 305system.physmem.wrPerTurnAround::200-203 1 0.01% 99.90% # Writes before turning the bus around for reads 306system.physmem.wrPerTurnAround::208-211 1 0.01% 99.92% # Writes before turning the bus around for reads 307system.physmem.wrPerTurnAround::224-227 3 0.04% 99.96% # Writes before turning the bus around for reads 308system.physmem.wrPerTurnAround::228-231 3 0.04% 100.00% # Writes before turning the bus around for reads 309system.physmem.wrPerTurnAround::total 7120 # Writes before turning the bus around for reads 310system.physmem.totQLat 4855930250 # Total ticks spent queuing 311system.physmem.totMemAccLat 8607130250 # Total ticks spent from burst creation until serviced by the DRAM 312system.physmem.totBusLat 1000320000 # Total ticks spent in databus transfers 313system.physmem.avgQLat 24271.88 # Average queueing delay per DRAM burst 314system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 315system.physmem.avgMemAccLat 43021.88 # Average memory access latency per DRAM burst 316system.physmem.avgRdBW 4.46 # Average DRAM read bandwidth in MiByte/s 317system.physmem.avgWrBW 3.80 # Average achieved write bandwidth in MiByte/s 318system.physmem.avgRdBWSys 4.26 # Average system read bandwidth in MiByte/s 319system.physmem.avgWrBWSys 3.83 # Average system write bandwidth in MiByte/s 320system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 321system.physmem.busUtil 0.06 # Data bus utilization in percentage 322system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 323system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 324system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing 325system.physmem.avgWrQLen 22.69 # Average write queue length when enqueuing 326system.physmem.readRowHits 167229 # Number of row buffer hits during reads 327system.physmem.writeRowHits 112615 # Number of row buffer hits during writes 328system.physmem.readRowHitRate 83.59 # Row buffer hit rate for reads 329system.physmem.writeRowHitRate 66.16 # Row buffer hit rate for writes 330system.physmem.avgGap 7626497.96 # Average gap between requests 331system.physmem.pageHitRate 75.58 # Row buffer hit rate, read and write combined 332system.physmem_0.actEnergy 354707640 # Energy for activate commands per rank (pJ) 333system.physmem_0.preEnergy 193540875 # Energy for precharge commands per rank (pJ) 334system.physmem_0.readEnergy 832845000 # Energy for read commands per rank (pJ) 335system.physmem_0.writeEnergy 568613520 # Energy for write commands per rank (pJ) 336system.physmem_0.refreshEnergy 187344349920 # Energy for refresh commands per rank (pJ) 337system.physmem_0.actBackEnergy 84727272375 # Energy for active background per rank (pJ) 338system.physmem_0.preBackEnergy 1646666587500 # Energy for precharge background per rank (pJ) 339system.physmem_0.totalEnergy 1920687916830 # Total energy per rank (pJ) 340system.physmem_0.averagePower 669.622475 # Core power per rank (mW) 341system.physmem_0.memoryStateTime::IDLE 2739235632500 # Time in different power states 342system.physmem_0.memoryStateTime::REF 95779320000 # Time in different power states 343system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 344system.physmem_0.memoryStateTime::ACT 33303656000 # Time in different power states 345system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 346system.physmem_1.actEnergy 328829760 # Energy for activate commands per rank (pJ) 347system.physmem_1.preEnergy 179421000 # Energy for precharge commands per rank (pJ) 348system.physmem_1.readEnergy 727646400 # Energy for read commands per rank (pJ) 349system.physmem_1.writeEnergy 534256560 # Energy for write commands per rank (pJ) 350system.physmem_1.refreshEnergy 187344349920 # Energy for refresh commands per rank (pJ) 351system.physmem_1.actBackEnergy 83962556955 # Energy for active background per rank (pJ) 352system.physmem_1.preBackEnergy 1647337390500 # Energy for precharge background per rank (pJ) 353system.physmem_1.totalEnergy 1920414451095 # Total energy per rank (pJ) 354system.physmem_1.averagePower 669.527135 # Core power per rank (mW) 355system.physmem_1.memoryStateTime::IDLE 2740355751000 # Time in different power states 356system.physmem_1.memoryStateTime::REF 95779320000 # Time in different power states 357system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 358system.physmem_1.memoryStateTime::ACT 32179536500 # Time in different power states 359system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 360system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 361system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 362system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 363system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 364system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 365system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 366system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 367system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 368system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 369system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) 370system.realview.nvmem.bw_read::cpu1.inst 17 # Total read bandwidth from this memory (bytes/s) 371system.realview.nvmem.bw_read::total 24 # Total read bandwidth from this memory (bytes/s) 372system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) 373system.realview.nvmem.bw_inst_read::cpu1.inst 17 # Instruction read bandwidth from this memory (bytes/s) 374system.realview.nvmem.bw_inst_read::total 24 # Instruction read bandwidth from this memory (bytes/s) 375system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) 376system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s) 377system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s) 378system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 379system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 380system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 381system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 382system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 383system.cf0.dma_write_txs 631 # Number of DMA write transactions. 384system.cpu_clk_domain.clock 500 # Clock period in ticks 385system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 386system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 387system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 388system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 389system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 390system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 391system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 392system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 393system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 394system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 395system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 396system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 397system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 398system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 399system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 400system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 401system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 402system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 403system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 404system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 405system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 406system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 407system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 408system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 409system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 410system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 411system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 412system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 413system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 414system.cpu0.dtb.walker.walks 7749 # Table walker walks requested 415system.cpu0.dtb.walker.walksShort 7749 # Table walker walks initiated with short descriptors 416system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1459 # Level at which table walker walks with short descriptors terminate 417system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6290 # Level at which table walker walks with short descriptors terminate 418system.cpu0.dtb.walker.walkWaitTime::samples 7749 # Table walker wait (enqueue to first request) latency 419system.cpu0.dtb.walker.walkWaitTime::0 7749 100.00% 100.00% # Table walker wait (enqueue to first request) latency 420system.cpu0.dtb.walker.walkWaitTime::total 7749 # Table walker wait (enqueue to first request) latency 421system.cpu0.dtb.walker.walkCompletionTime::samples 6355 # Table walker service (enqueue to completion) latency 422system.cpu0.dtb.walker.walkCompletionTime::mean 8363.375452 # Table walker service (enqueue to completion) latency 423system.cpu0.dtb.walker.walkCompletionTime::gmean 7097.000757 # Table walker service (enqueue to completion) latency 424system.cpu0.dtb.walker.walkCompletionTime::stdev 5454.838397 # Table walker service (enqueue to completion) latency 425system.cpu0.dtb.walker.walkCompletionTime::0-16383 6203 97.61% 97.61% # Table walker service (enqueue to completion) latency 426system.cpu0.dtb.walker.walkCompletionTime::16384-32767 142 2.23% 99.84% # Table walker service (enqueue to completion) latency 427system.cpu0.dtb.walker.walkCompletionTime::32768-49151 6 0.09% 99.94% # Table walker service (enqueue to completion) latency 428system.cpu0.dtb.walker.walkCompletionTime::81920-98303 3 0.05% 99.98% # Table walker service (enqueue to completion) latency 429system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.02% 100.00% # Table walker service (enqueue to completion) latency 430system.cpu0.dtb.walker.walkCompletionTime::total 6355 # Table walker service (enqueue to completion) latency 431system.cpu0.dtb.walker.walksPending::samples 987959000 # Table walker pending requests distribution 432system.cpu0.dtb.walker.walksPending::0 987959000 100.00% 100.00% # Table walker pending requests distribution 433system.cpu0.dtb.walker.walksPending::total 987959000 # Table walker pending requests distribution 434system.cpu0.dtb.walker.walkPageSizes::4K 4935 77.66% 77.66% # Table walker page sizes translated 435system.cpu0.dtb.walker.walkPageSizes::1M 1420 22.34% 100.00% # Table walker page sizes translated 436system.cpu0.dtb.walker.walkPageSizes::total 6355 # Table walker page sizes translated 437system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7749 # Table walker requests started/completed, data/inst 438system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 439system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7749 # Table walker requests started/completed, data/inst 440system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6355 # Table walker requests started/completed, data/inst 441system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 442system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6355 # Table walker requests started/completed, data/inst 443system.cpu0.dtb.walker.walkRequestOrigin::total 14104 # Table walker requests started/completed, data/inst 444system.cpu0.dtb.inst_hits 0 # ITB inst hits 445system.cpu0.dtb.inst_misses 0 # ITB inst misses 446system.cpu0.dtb.read_hits 19044092 # DTB read hits 447system.cpu0.dtb.read_misses 6608 # DTB read misses 448system.cpu0.dtb.write_hits 15688894 # DTB write hits 449system.cpu0.dtb.write_misses 1141 # DTB write misses 450system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 451system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 452system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 453system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 454system.cpu0.dtb.flush_entries 3442 # Number of entries that have been flushed from TLB 455system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 456system.cpu0.dtb.prefetch_faults 1734 # Number of TLB faults due to prefetch 457system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 458system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions 459system.cpu0.dtb.read_accesses 19050700 # DTB read accesses 460system.cpu0.dtb.write_accesses 15690035 # DTB write accesses 461system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 462system.cpu0.dtb.hits 34732986 # DTB hits 463system.cpu0.dtb.misses 7749 # DTB misses 464system.cpu0.dtb.accesses 34740735 # DTB accesses 465system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 466system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 467system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 468system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 469system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 470system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 471system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 472system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 473system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 474system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 475system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 476system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 477system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 478system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 479system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 480system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 481system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 482system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 483system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 484system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 485system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 486system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 487system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 488system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 489system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 490system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 491system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 492system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 493system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 494system.cpu0.itb.walker.walks 3348 # Table walker walks requested 495system.cpu0.itb.walker.walksShort 3348 # Table walker walks initiated with short descriptors 496system.cpu0.itb.walker.walksShortTerminationLevel::Level1 298 # Level at which table walker walks with short descriptors terminate 497system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3050 # Level at which table walker walks with short descriptors terminate 498system.cpu0.itb.walker.walkWaitTime::samples 3348 # Table walker wait (enqueue to first request) latency 499system.cpu0.itb.walker.walkWaitTime::0 3348 100.00% 100.00% # Table walker wait (enqueue to first request) latency 500system.cpu0.itb.walker.walkWaitTime::total 3348 # Table walker wait (enqueue to first request) latency 501system.cpu0.itb.walker.walkCompletionTime::samples 2332 # Table walker service (enqueue to completion) latency 502system.cpu0.itb.walker.walkCompletionTime::mean 8781.732419 # Table walker service (enqueue to completion) latency 503system.cpu0.itb.walker.walkCompletionTime::gmean 7396.194245 # Table walker service (enqueue to completion) latency 504system.cpu0.itb.walker.walkCompletionTime::stdev 5559.104899 # Table walker service (enqueue to completion) latency 505system.cpu0.itb.walker.walkCompletionTime::0-8191 1469 62.99% 62.99% # Table walker service (enqueue to completion) latency 506system.cpu0.itb.walker.walkCompletionTime::8192-16383 817 35.03% 98.03% # Table walker service (enqueue to completion) latency 507system.cpu0.itb.walker.walkCompletionTime::16384-24575 4 0.17% 98.20% # Table walker service (enqueue to completion) latency 508system.cpu0.itb.walker.walkCompletionTime::24576-32767 39 1.67% 99.87% # Table walker service (enqueue to completion) latency 509system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.91% # Table walker service (enqueue to completion) latency 510system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.04% 99.96% # Table walker service (enqueue to completion) latency 511system.cpu0.itb.walker.walkCompletionTime::106496-114687 1 0.04% 100.00% # Table walker service (enqueue to completion) latency 512system.cpu0.itb.walker.walkCompletionTime::total 2332 # Table walker service (enqueue to completion) latency 513system.cpu0.itb.walker.walksPending::samples 987617000 # Table walker pending requests distribution 514system.cpu0.itb.walker.walksPending::0 987617000 100.00% 100.00% # Table walker pending requests distribution 515system.cpu0.itb.walker.walksPending::total 987617000 # Table walker pending requests distribution 516system.cpu0.itb.walker.walkPageSizes::4K 2034 87.22% 87.22% # Table walker page sizes translated 517system.cpu0.itb.walker.walkPageSizes::1M 298 12.78% 100.00% # Table walker page sizes translated 518system.cpu0.itb.walker.walkPageSizes::total 2332 # Table walker page sizes translated 519system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 520system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3348 # Table walker requests started/completed, data/inst 521system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3348 # Table walker requests started/completed, data/inst 522system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 523system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2332 # Table walker requests started/completed, data/inst 524system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2332 # Table walker requests started/completed, data/inst 525system.cpu0.itb.walker.walkRequestOrigin::total 5680 # Table walker requests started/completed, data/inst 526system.cpu0.itb.inst_hits 91510827 # ITB inst hits 527system.cpu0.itb.inst_misses 3348 # ITB inst misses 528system.cpu0.itb.read_hits 0 # DTB read hits 529system.cpu0.itb.read_misses 0 # DTB read misses 530system.cpu0.itb.write_hits 0 # DTB write hits 531system.cpu0.itb.write_misses 0 # DTB write misses 532system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 533system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 534system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 535system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 536system.cpu0.itb.flush_entries 2150 # Number of entries that have been flushed from TLB 537system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 538system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 539system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 540system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 541system.cpu0.itb.read_accesses 0 # DTB read accesses 542system.cpu0.itb.write_accesses 0 # DTB write accesses 543system.cpu0.itb.inst_accesses 91514175 # ITB inst accesses 544system.cpu0.itb.hits 91510827 # DTB hits 545system.cpu0.itb.misses 3348 # DTB misses 546system.cpu0.itb.accesses 91514175 # DTB accesses 547system.cpu0.numCycles 5736637393 # number of cpu cycles simulated 548system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 549system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 550system.cpu0.committedInsts 89363678 # Number of instructions committed 551system.cpu0.committedOps 107297883 # Number of ops (including micro ops) committed 552system.cpu0.num_int_alu_accesses 94350928 # Number of integer alu accesses 553system.cpu0.num_fp_alu_accesses 9820 # Number of float alu accesses 554system.cpu0.num_func_calls 6606472 # number of times a function call or return occured 555system.cpu0.num_conditional_control_insts 12627044 # number of instructions that are conditional controls 556system.cpu0.num_int_insts 94350928 # number of integer instructions 557system.cpu0.num_fp_insts 9820 # number of float instructions 558system.cpu0.num_int_register_reads 169124164 # number of times the integer registers were read 559system.cpu0.num_int_register_writes 64348180 # number of times the integer registers were written 560system.cpu0.num_fp_register_reads 7560 # number of times the floating registers were read 561system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written 562system.cpu0.num_cc_register_reads 385798415 # number of times the CC registers were read 563system.cpu0.num_cc_register_writes 43074064 # number of times the CC registers were written 564system.cpu0.num_mem_refs 35866705 # number of memory refs 565system.cpu0.num_load_insts 19295047 # Number of load instructions 566system.cpu0.num_store_insts 16571658 # Number of store instructions 567system.cpu0.num_idle_cycles 5512519658.266078 # Number of idle cycles 568system.cpu0.num_busy_cycles 224117734.733922 # Number of busy cycles 569system.cpu0.not_idle_fraction 0.039068 # Percentage of non-idle cycles 570system.cpu0.idle_fraction 0.960932 # Percentage of idle cycles 571system.cpu0.Branches 19970568 # Number of branches fetched 572system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction 573system.cpu0.op_class::IntAlu 73557669 67.15% 67.15% # Class of executed instruction 574system.cpu0.op_class::IntMult 108302 0.10% 67.25% # Class of executed instruction 575system.cpu0.op_class::IntDiv 0 0.00% 67.25% # Class of executed instruction 576system.cpu0.op_class::FloatAdd 0 0.00% 67.25% # Class of executed instruction 577system.cpu0.op_class::FloatCmp 0 0.00% 67.25% # Class of executed instruction 578system.cpu0.op_class::FloatCvt 0 0.00% 67.25% # Class of executed instruction 579system.cpu0.op_class::FloatMult 0 0.00% 67.25% # Class of executed instruction 580system.cpu0.op_class::FloatDiv 0 0.00% 67.25% # Class of executed instruction 581system.cpu0.op_class::FloatSqrt 0 0.00% 67.25% # Class of executed instruction 582system.cpu0.op_class::SimdAdd 0 0.00% 67.25% # Class of executed instruction 583system.cpu0.op_class::SimdAddAcc 0 0.00% 67.25% # Class of executed instruction 584system.cpu0.op_class::SimdAlu 0 0.00% 67.25% # Class of executed instruction 585system.cpu0.op_class::SimdCmp 0 0.00% 67.25% # Class of executed instruction 586system.cpu0.op_class::SimdCvt 0 0.00% 67.25% # Class of executed instruction 587system.cpu0.op_class::SimdMisc 0 0.00% 67.25% # Class of executed instruction 588system.cpu0.op_class::SimdMult 0 0.00% 67.25% # Class of executed instruction 589system.cpu0.op_class::SimdMultAcc 0 0.00% 67.25% # Class of executed instruction 590system.cpu0.op_class::SimdShift 0 0.00% 67.25% # Class of executed instruction 591system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.25% # Class of executed instruction 592system.cpu0.op_class::SimdSqrt 0 0.00% 67.25% # Class of executed instruction 593system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.25% # Class of executed instruction 594system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.25% # Class of executed instruction 595system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.25% # Class of executed instruction 596system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.25% # Class of executed instruction 597system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.25% # Class of executed instruction 598system.cpu0.op_class::SimdFloatMisc 8177 0.01% 67.26% # Class of executed instruction 599system.cpu0.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction 600system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction 601system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction 602system.cpu0.op_class::MemRead 19295047 17.61% 84.87% # Class of executed instruction 603system.cpu0.op_class::MemWrite 16571658 15.13% 100.00% # Class of executed instruction 604system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 605system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 606system.cpu0.op_class::total 109543126 # Class of executed instruction 607system.cpu0.kern.inst.arm 0 # number of arm instructions executed 608system.cpu0.kern.inst.quiesce 1879 # number of quiesce instructions executed 609system.cpu0.dcache.tags.replacements 690539 # number of replacements 610system.cpu0.dcache.tags.tagsinuse 487.185772 # Cycle average of tags in use 611system.cpu0.dcache.tags.total_refs 33864824 # Total number of references to valid blocks. 612system.cpu0.dcache.tags.sampled_refs 691051 # Sample count of references to valid blocks. 613system.cpu0.dcache.tags.avg_refs 49.004812 # Average number of references to valid blocks. 614system.cpu0.dcache.tags.warmup_cycle 1015908000 # Cycle when the warmup percentage was hit. 615system.cpu0.dcache.tags.occ_blocks::cpu0.data 487.185772 # Average occupied blocks per requestor 616system.cpu0.dcache.tags.occ_percent::cpu0.data 0.951535 # Average percentage of cache occupancy 617system.cpu0.dcache.tags.occ_percent::total 0.951535 # Average percentage of cache occupancy 618system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 619system.cpu0.dcache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id 620system.cpu0.dcache.tags.age_task_id_blocks_1024::1 275 # Occupied blocks per task id 621system.cpu0.dcache.tags.age_task_id_blocks_1024::2 126 # Occupied blocks per task id 622system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 623system.cpu0.dcache.tags.tag_accesses 70103571 # Number of tag accesses 624system.cpu0.dcache.tags.data_accesses 70103571 # Number of data accesses 625system.cpu0.dcache.ReadReq_hits::cpu0.data 17785791 # number of ReadReq hits 626system.cpu0.dcache.ReadReq_hits::total 17785791 # number of ReadReq hits 627system.cpu0.dcache.WriteReq_hits::cpu0.data 14958877 # number of WriteReq hits 628system.cpu0.dcache.WriteReq_hits::total 14958877 # number of WriteReq hits 629system.cpu0.dcache.SoftPFReq_hits::cpu0.data 318525 # number of SoftPFReq hits 630system.cpu0.dcache.SoftPFReq_hits::total 318525 # number of SoftPFReq hits 631system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 364927 # number of LoadLockedReq hits 632system.cpu0.dcache.LoadLockedReq_hits::total 364927 # number of LoadLockedReq hits 633system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361705 # number of StoreCondReq hits 634system.cpu0.dcache.StoreCondReq_hits::total 361705 # number of StoreCondReq hits 635system.cpu0.dcache.demand_hits::cpu0.data 32744668 # number of demand (read+write) hits 636system.cpu0.dcache.demand_hits::total 32744668 # number of demand (read+write) hits 637system.cpu0.dcache.overall_hits::cpu0.data 33063193 # number of overall hits 638system.cpu0.dcache.overall_hits::total 33063193 # number of overall hits 639system.cpu0.dcache.ReadReq_misses::cpu0.data 394905 # number of ReadReq misses 640system.cpu0.dcache.ReadReq_misses::total 394905 # number of ReadReq misses 641system.cpu0.dcache.WriteReq_misses::cpu0.data 324481 # number of WriteReq misses 642system.cpu0.dcache.WriteReq_misses::total 324481 # number of WriteReq misses 643system.cpu0.dcache.SoftPFReq_misses::cpu0.data 127732 # number of SoftPFReq misses 644system.cpu0.dcache.SoftPFReq_misses::total 127732 # number of SoftPFReq misses 645system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21710 # number of LoadLockedReq misses 646system.cpu0.dcache.LoadLockedReq_misses::total 21710 # number of LoadLockedReq misses 647system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20007 # number of StoreCondReq misses 648system.cpu0.dcache.StoreCondReq_misses::total 20007 # number of StoreCondReq misses 649system.cpu0.dcache.demand_misses::cpu0.data 719386 # number of demand (read+write) misses 650system.cpu0.dcache.demand_misses::total 719386 # number of demand (read+write) misses 651system.cpu0.dcache.overall_misses::cpu0.data 847118 # number of overall misses 652system.cpu0.dcache.overall_misses::total 847118 # number of overall misses 653system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4990872752 # number of ReadReq miss cycles 654system.cpu0.dcache.ReadReq_miss_latency::total 4990872752 # number of ReadReq miss cycles 655system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4944330313 # number of WriteReq miss cycles 656system.cpu0.dcache.WriteReq_miss_latency::total 4944330313 # number of WriteReq miss cycles 657system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 327573000 # number of LoadLockedReq miss cycles 658system.cpu0.dcache.LoadLockedReq_miss_latency::total 327573000 # number of LoadLockedReq miss cycles 659system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 444426745 # number of StoreCondReq miss cycles 660system.cpu0.dcache.StoreCondReq_miss_latency::total 444426745 # number of StoreCondReq miss cycles 661system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1572500 # number of StoreCondFailReq miss cycles 662system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1572500 # number of StoreCondFailReq miss cycles 663system.cpu0.dcache.demand_miss_latency::cpu0.data 9935203065 # number of demand (read+write) miss cycles 664system.cpu0.dcache.demand_miss_latency::total 9935203065 # number of demand (read+write) miss cycles 665system.cpu0.dcache.overall_miss_latency::cpu0.data 9935203065 # number of overall miss cycles 666system.cpu0.dcache.overall_miss_latency::total 9935203065 # number of overall miss cycles 667system.cpu0.dcache.ReadReq_accesses::cpu0.data 18180696 # number of ReadReq accesses(hits+misses) 668system.cpu0.dcache.ReadReq_accesses::total 18180696 # number of ReadReq accesses(hits+misses) 669system.cpu0.dcache.WriteReq_accesses::cpu0.data 15283358 # number of WriteReq accesses(hits+misses) 670system.cpu0.dcache.WriteReq_accesses::total 15283358 # number of WriteReq accesses(hits+misses) 671system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446257 # number of SoftPFReq accesses(hits+misses) 672system.cpu0.dcache.SoftPFReq_accesses::total 446257 # number of SoftPFReq accesses(hits+misses) 673system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386637 # number of LoadLockedReq accesses(hits+misses) 674system.cpu0.dcache.LoadLockedReq_accesses::total 386637 # number of LoadLockedReq accesses(hits+misses) 675system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381712 # number of StoreCondReq accesses(hits+misses) 676system.cpu0.dcache.StoreCondReq_accesses::total 381712 # number of StoreCondReq accesses(hits+misses) 677system.cpu0.dcache.demand_accesses::cpu0.data 33464054 # number of demand (read+write) accesses 678system.cpu0.dcache.demand_accesses::total 33464054 # number of demand (read+write) accesses 679system.cpu0.dcache.overall_accesses::cpu0.data 33910311 # number of overall (read+write) accesses 680system.cpu0.dcache.overall_accesses::total 33910311 # number of overall (read+write) accesses 681system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.021721 # miss rate for ReadReq accesses 682system.cpu0.dcache.ReadReq_miss_rate::total 0.021721 # miss rate for ReadReq accesses 683system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.021231 # miss rate for WriteReq accesses 684system.cpu0.dcache.WriteReq_miss_rate::total 0.021231 # miss rate for WriteReq accesses 685system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.286230 # miss rate for SoftPFReq accesses 686system.cpu0.dcache.SoftPFReq_miss_rate::total 0.286230 # miss rate for SoftPFReq accesses 687system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056151 # miss rate for LoadLockedReq accesses 688system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056151 # miss rate for LoadLockedReq accesses 689system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.052414 # miss rate for StoreCondReq accesses 690system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052414 # miss rate for StoreCondReq accesses 691system.cpu0.dcache.demand_miss_rate::cpu0.data 0.021497 # miss rate for demand accesses 692system.cpu0.dcache.demand_miss_rate::total 0.021497 # miss rate for demand accesses 693system.cpu0.dcache.overall_miss_rate::cpu0.data 0.024981 # miss rate for overall accesses 694system.cpu0.dcache.overall_miss_rate::total 0.024981 # miss rate for overall accesses 695system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12638.160449 # average ReadReq miss latency 696system.cpu0.dcache.ReadReq_avg_miss_latency::total 12638.160449 # average ReadReq miss latency 697system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15237.657407 # average WriteReq miss latency 698system.cpu0.dcache.WriteReq_avg_miss_latency::total 15237.657407 # average WriteReq miss latency 699system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15088.576693 # average LoadLockedReq miss latency 700system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15088.576693 # average LoadLockedReq miss latency 701system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22213.562503 # average StoreCondReq miss latency 702system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22213.562503 # average StoreCondReq miss latency 703system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 704system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 705system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13810.670579 # average overall miss latency 706system.cpu0.dcache.demand_avg_miss_latency::total 13810.670579 # average overall miss latency 707system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 11728.239826 # average overall miss latency 708system.cpu0.dcache.overall_avg_miss_latency::total 11728.239826 # average overall miss latency 709system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 710system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 711system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 712system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 713system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 714system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 715system.cpu0.dcache.fast_writes 0 # number of fast writes performed 716system.cpu0.dcache.cache_copies 0 # number of cache copies performed 717system.cpu0.dcache.writebacks::writebacks 504116 # number of writebacks 718system.cpu0.dcache.writebacks::total 504116 # number of writebacks 719system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25128 # number of ReadReq MSHR hits 720system.cpu0.dcache.ReadReq_mshr_hits::total 25128 # number of ReadReq MSHR hits 721system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15248 # number of LoadLockedReq MSHR hits 722system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15248 # number of LoadLockedReq MSHR hits 723system.cpu0.dcache.demand_mshr_hits::cpu0.data 25128 # number of demand (read+write) MSHR hits 724system.cpu0.dcache.demand_mshr_hits::total 25128 # number of demand (read+write) MSHR hits 725system.cpu0.dcache.overall_mshr_hits::cpu0.data 25128 # number of overall MSHR hits 726system.cpu0.dcache.overall_mshr_hits::total 25128 # number of overall MSHR hits 727system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 369777 # number of ReadReq MSHR misses 728system.cpu0.dcache.ReadReq_mshr_misses::total 369777 # number of ReadReq MSHR misses 729system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 324481 # number of WriteReq MSHR misses 730system.cpu0.dcache.WriteReq_mshr_misses::total 324481 # number of WriteReq MSHR misses 731system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 100470 # number of SoftPFReq MSHR misses 732system.cpu0.dcache.SoftPFReq_mshr_misses::total 100470 # number of SoftPFReq MSHR misses 733system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6462 # number of LoadLockedReq MSHR misses 734system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6462 # number of LoadLockedReq MSHR misses 735system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20007 # number of StoreCondReq MSHR misses 736system.cpu0.dcache.StoreCondReq_mshr_misses::total 20007 # number of StoreCondReq MSHR misses 737system.cpu0.dcache.demand_mshr_misses::cpu0.data 694258 # number of demand (read+write) MSHR misses 738system.cpu0.dcache.demand_mshr_misses::total 694258 # number of demand (read+write) MSHR misses 739system.cpu0.dcache.overall_mshr_misses::cpu0.data 794728 # number of overall MSHR misses 740system.cpu0.dcache.overall_mshr_misses::total 794728 # number of overall MSHR misses 741system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3859056498 # number of ReadReq MSHR miss cycles 742system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3859056498 # number of ReadReq MSHR miss cycles 743system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4283066685 # number of WriteReq MSHR miss cycles 744system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4283066685 # number of WriteReq MSHR miss cycles 745system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1502769500 # number of SoftPFReq MSHR miss cycles 746system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1502769500 # number of SoftPFReq MSHR miss cycles 747system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 90797250 # number of LoadLockedReq MSHR miss cycles 748system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 90797250 # number of LoadLockedReq MSHR miss cycles 749system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 403751255 # number of StoreCondReq MSHR miss cycles 750system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 403751255 # number of StoreCondReq MSHR miss cycles 751system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1480500 # number of StoreCondFailReq MSHR miss cycles 752system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1480500 # number of StoreCondFailReq MSHR miss cycles 753system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8142123183 # number of demand (read+write) MSHR miss cycles 754system.cpu0.dcache.demand_mshr_miss_latency::total 8142123183 # number of demand (read+write) MSHR miss cycles 755system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 9644892683 # number of overall MSHR miss cycles 756system.cpu0.dcache.overall_mshr_miss_latency::total 9644892683 # number of overall MSHR miss cycles 757system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5991645999 # number of ReadReq MSHR uncacheable cycles 758system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5991645999 # number of ReadReq MSHR uncacheable cycles 759system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4628507500 # number of WriteReq MSHR uncacheable cycles 760system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4628507500 # number of WriteReq MSHR uncacheable cycles 761system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10620153499 # number of overall MSHR uncacheable cycles 762system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10620153499 # number of overall MSHR uncacheable cycles 763system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.020339 # mshr miss rate for ReadReq accesses 764system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.020339 # mshr miss rate for ReadReq accesses 765system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.021231 # mshr miss rate for WriteReq accesses 766system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021231 # mshr miss rate for WriteReq accesses 767system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225139 # mshr miss rate for SoftPFReq accesses 768system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225139 # mshr miss rate for SoftPFReq accesses 769system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016713 # mshr miss rate for LoadLockedReq accesses 770system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016713 # mshr miss rate for LoadLockedReq accesses 771system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052414 # mshr miss rate for StoreCondReq accesses 772system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052414 # mshr miss rate for StoreCondReq accesses 773system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.020746 # mshr miss rate for demand accesses 774system.cpu0.dcache.demand_mshr_miss_rate::total 0.020746 # mshr miss rate for demand accesses 775system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.023436 # mshr miss rate for overall accesses 776system.cpu0.dcache.overall_mshr_miss_rate::total 0.023436 # mshr miss rate for overall accesses 777system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10436.172336 # average ReadReq mshr miss latency 778system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10436.172336 # average ReadReq mshr miss latency 779system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 13199.745702 # average WriteReq mshr miss latency 780system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 13199.745702 # average WriteReq mshr miss latency 781system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 14957.395242 # average SoftPFReq mshr miss latency 782system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14957.395242 # average SoftPFReq mshr miss latency 783system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14050.951718 # average LoadLockedReq mshr miss latency 784system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14050.951718 # average LoadLockedReq mshr miss latency 785system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20180.499575 # average StoreCondReq mshr miss latency 786system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20180.499575 # average StoreCondReq mshr miss latency 787system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 788system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 789system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 11727.806065 # average overall mshr miss latency 790system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11727.806065 # average overall mshr miss latency 791system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 12136.092705 # average overall mshr miss latency 792system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12136.092705 # average overall mshr miss latency 793system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 794system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 795system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 796system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 797system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 798system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 799system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 800system.cpu0.icache.tags.replacements 1099798 # number of replacements 801system.cpu0.icache.tags.tagsinuse 511.479276 # Cycle average of tags in use 802system.cpu0.icache.tags.total_refs 90410508 # Total number of references to valid blocks. 803system.cpu0.icache.tags.sampled_refs 1100310 # Sample count of references to valid blocks. 804system.cpu0.icache.tags.avg_refs 82.168214 # Average number of references to valid blocks. 805system.cpu0.icache.tags.warmup_cycle 13323414750 # Cycle when the warmup percentage was hit. 806system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.479276 # Average occupied blocks per requestor 807system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998983 # Average percentage of cache occupancy 808system.cpu0.icache.tags.occ_percent::total 0.998983 # Average percentage of cache occupancy 809system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 810system.cpu0.icache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id 811system.cpu0.icache.tags.age_task_id_blocks_1024::1 206 # Occupied blocks per task id 812system.cpu0.icache.tags.age_task_id_blocks_1024::2 215 # Occupied blocks per task id 813system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 814system.cpu0.icache.tags.tag_accesses 184121973 # Number of tag accesses 815system.cpu0.icache.tags.data_accesses 184121973 # Number of data accesses 816system.cpu0.icache.ReadReq_hits::cpu0.inst 90410508 # number of ReadReq hits 817system.cpu0.icache.ReadReq_hits::total 90410508 # number of ReadReq hits 818system.cpu0.icache.demand_hits::cpu0.inst 90410508 # number of demand (read+write) hits 819system.cpu0.icache.demand_hits::total 90410508 # number of demand (read+write) hits 820system.cpu0.icache.overall_hits::cpu0.inst 90410508 # number of overall hits 821system.cpu0.icache.overall_hits::total 90410508 # number of overall hits 822system.cpu0.icache.ReadReq_misses::cpu0.inst 1100319 # number of ReadReq misses 823system.cpu0.icache.ReadReq_misses::total 1100319 # number of ReadReq misses 824system.cpu0.icache.demand_misses::cpu0.inst 1100319 # number of demand (read+write) misses 825system.cpu0.icache.demand_misses::total 1100319 # number of demand (read+write) misses 826system.cpu0.icache.overall_misses::cpu0.inst 1100319 # number of overall misses 827system.cpu0.icache.overall_misses::total 1100319 # number of overall misses 828system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10739818993 # number of ReadReq miss cycles 829system.cpu0.icache.ReadReq_miss_latency::total 10739818993 # number of ReadReq miss cycles 830system.cpu0.icache.demand_miss_latency::cpu0.inst 10739818993 # number of demand (read+write) miss cycles 831system.cpu0.icache.demand_miss_latency::total 10739818993 # number of demand (read+write) miss cycles 832system.cpu0.icache.overall_miss_latency::cpu0.inst 10739818993 # number of overall miss cycles 833system.cpu0.icache.overall_miss_latency::total 10739818993 # number of overall miss cycles 834system.cpu0.icache.ReadReq_accesses::cpu0.inst 91510827 # number of ReadReq accesses(hits+misses) 835system.cpu0.icache.ReadReq_accesses::total 91510827 # number of ReadReq accesses(hits+misses) 836system.cpu0.icache.demand_accesses::cpu0.inst 91510827 # number of demand (read+write) accesses 837system.cpu0.icache.demand_accesses::total 91510827 # number of demand (read+write) accesses 838system.cpu0.icache.overall_accesses::cpu0.inst 91510827 # number of overall (read+write) accesses 839system.cpu0.icache.overall_accesses::total 91510827 # number of overall (read+write) accesses 840system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.012024 # miss rate for ReadReq accesses 841system.cpu0.icache.ReadReq_miss_rate::total 0.012024 # miss rate for ReadReq accesses 842system.cpu0.icache.demand_miss_rate::cpu0.inst 0.012024 # miss rate for demand accesses 843system.cpu0.icache.demand_miss_rate::total 0.012024 # miss rate for demand accesses 844system.cpu0.icache.overall_miss_rate::cpu0.inst 0.012024 # miss rate for overall accesses 845system.cpu0.icache.overall_miss_rate::total 0.012024 # miss rate for overall accesses 846system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9760.641226 # average ReadReq miss latency 847system.cpu0.icache.ReadReq_avg_miss_latency::total 9760.641226 # average ReadReq miss latency 848system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9760.641226 # average overall miss latency 849system.cpu0.icache.demand_avg_miss_latency::total 9760.641226 # average overall miss latency 850system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9760.641226 # average overall miss latency 851system.cpu0.icache.overall_avg_miss_latency::total 9760.641226 # average overall miss latency 852system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 853system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 854system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 855system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 856system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 857system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 858system.cpu0.icache.fast_writes 0 # number of fast writes performed 859system.cpu0.icache.cache_copies 0 # number of cache copies performed 860system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1100319 # number of ReadReq MSHR misses 861system.cpu0.icache.ReadReq_mshr_misses::total 1100319 # number of ReadReq MSHR misses 862system.cpu0.icache.demand_mshr_misses::cpu0.inst 1100319 # number of demand (read+write) MSHR misses 863system.cpu0.icache.demand_mshr_misses::total 1100319 # number of demand (read+write) MSHR misses 864system.cpu0.icache.overall_mshr_misses::cpu0.inst 1100319 # number of overall MSHR misses 865system.cpu0.icache.overall_mshr_misses::total 1100319 # number of overall MSHR misses 866system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9082830507 # number of ReadReq MSHR miss cycles 867system.cpu0.icache.ReadReq_mshr_miss_latency::total 9082830507 # number of ReadReq MSHR miss cycles 868system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9082830507 # number of demand (read+write) MSHR miss cycles 869system.cpu0.icache.demand_mshr_miss_latency::total 9082830507 # number of demand (read+write) MSHR miss cycles 870system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9082830507 # number of overall MSHR miss cycles 871system.cpu0.icache.overall_mshr_miss_latency::total 9082830507 # number of overall MSHR miss cycles 872system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 719096500 # number of ReadReq MSHR uncacheable cycles 873system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 719096500 # number of ReadReq MSHR uncacheable cycles 874system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 719096500 # number of overall MSHR uncacheable cycles 875system.cpu0.icache.overall_mshr_uncacheable_latency::total 719096500 # number of overall MSHR uncacheable cycles 876system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.012024 # mshr miss rate for ReadReq accesses 877system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.012024 # mshr miss rate for ReadReq accesses 878system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.012024 # mshr miss rate for demand accesses 879system.cpu0.icache.demand_mshr_miss_rate::total 0.012024 # mshr miss rate for demand accesses 880system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.012024 # mshr miss rate for overall accesses 881system.cpu0.icache.overall_mshr_miss_rate::total 0.012024 # mshr miss rate for overall accesses 882system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8254.724773 # average ReadReq mshr miss latency 883system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8254.724773 # average ReadReq mshr miss latency 884system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8254.724773 # average overall mshr miss latency 885system.cpu0.icache.demand_avg_mshr_miss_latency::total 8254.724773 # average overall mshr miss latency 886system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8254.724773 # average overall mshr miss latency 887system.cpu0.icache.overall_avg_mshr_miss_latency::total 8254.724773 # average overall mshr miss latency 888system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 889system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 890system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 891system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 892system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 893system.cpu0.l2cache.prefetcher.num_hwpf_issued 1853283 # number of hwpf issued 894system.cpu0.l2cache.prefetcher.pfIdentified 1853292 # number of prefetch candidates identified 895system.cpu0.l2cache.prefetcher.pfBufferHit 7 # number of redundant prefetches already in prefetch queue 896system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 897system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 898system.cpu0.l2cache.prefetcher.pfSpanPage 238164 # number of prefetches not generated due to page crossing 899system.cpu0.l2cache.tags.replacements 268426 # number of replacements 900system.cpu0.l2cache.tags.tagsinuse 16093.899190 # Cycle average of tags in use 901system.cpu0.l2cache.tags.total_refs 1968322 # Total number of references to valid blocks. 902system.cpu0.l2cache.tags.sampled_refs 284663 # Sample count of references to valid blocks. 903system.cpu0.l2cache.tags.avg_refs 6.914569 # Average number of references to valid blocks. 904system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 905system.cpu0.l2cache.tags.occ_blocks::writebacks 7921.036071 # Average occupied blocks per requestor 906system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 2.357121 # Average occupied blocks per requestor 907system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.109776 # Average occupied blocks per requestor 908system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4473.771805 # Average occupied blocks per requestor 909system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1953.197848 # Average occupied blocks per requestor 910system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1743.426570 # Average occupied blocks per requestor 911system.cpu0.l2cache.tags.occ_percent::writebacks 0.483462 # Average percentage of cache occupancy 912system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000144 # Average percentage of cache occupancy 913system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000007 # Average percentage of cache occupancy 914system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.273057 # Average percentage of cache occupancy 915system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.119214 # Average percentage of cache occupancy 916system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.106410 # Average percentage of cache occupancy 917system.cpu0.l2cache.tags.occ_percent::total 0.982294 # Average percentage of cache occupancy 918system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1127 # Occupied blocks per task id 919system.cpu0.l2cache.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id 920system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15106 # Occupied blocks per task id 921system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id 922system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 288 # Occupied blocks per task id 923system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 418 # Occupied blocks per task id 924system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 412 # Occupied blocks per task id 925system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 926system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id 927system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id 928system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 118 # Occupied blocks per task id 929system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3213 # Occupied blocks per task id 930system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7809 # Occupied blocks per task id 931system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3908 # Occupied blocks per task id 932system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.068787 # Percentage of cache occupancy per task id 933system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000244 # Percentage of cache occupancy per task id 934system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.921997 # Percentage of cache occupancy per task id 935system.cpu0.l2cache.tags.tag_accesses 39654154 # Number of tag accesses 936system.cpu0.l2cache.tags.data_accesses 39654154 # Number of data accesses 937system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7774 # number of ReadReq hits 938system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3610 # number of ReadReq hits 939system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1053168 # number of ReadReq hits 940system.cpu0.l2cache.ReadReq_hits::cpu0.data 381762 # number of ReadReq hits 941system.cpu0.l2cache.ReadReq_hits::total 1446314 # number of ReadReq hits 942system.cpu0.l2cache.Writeback_hits::writebacks 504114 # number of Writeback hits 943system.cpu0.l2cache.Writeback_hits::total 504114 # number of Writeback hits 944system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28406 # number of UpgradeReq hits 945system.cpu0.l2cache.UpgradeReq_hits::total 28406 # number of UpgradeReq hits 946system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1700 # number of SCUpgradeReq hits 947system.cpu0.l2cache.SCUpgradeReq_hits::total 1700 # number of SCUpgradeReq hits 948system.cpu0.l2cache.ReadExReq_hits::cpu0.data 227802 # number of ReadExReq hits 949system.cpu0.l2cache.ReadExReq_hits::total 227802 # number of ReadExReq hits 950system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7774 # number of demand (read+write) hits 951system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3610 # number of demand (read+write) hits 952system.cpu0.l2cache.demand_hits::cpu0.inst 1053168 # number of demand (read+write) hits 953system.cpu0.l2cache.demand_hits::cpu0.data 609564 # number of demand (read+write) hits 954system.cpu0.l2cache.demand_hits::total 1674116 # number of demand (read+write) hits 955system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7774 # number of overall hits 956system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3610 # number of overall hits 957system.cpu0.l2cache.overall_hits::cpu0.inst 1053168 # number of overall hits 958system.cpu0.l2cache.overall_hits::cpu0.data 609564 # number of overall hits 959system.cpu0.l2cache.overall_hits::total 1674116 # number of overall hits 960system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 215 # number of ReadReq misses 961system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 122 # number of ReadReq misses 962system.cpu0.l2cache.ReadReq_misses::cpu0.inst 47151 # number of ReadReq misses 963system.cpu0.l2cache.ReadReq_misses::cpu0.data 94947 # number of ReadReq misses 964system.cpu0.l2cache.ReadReq_misses::total 142435 # number of ReadReq misses 965system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26586 # number of UpgradeReq misses 966system.cpu0.l2cache.UpgradeReq_misses::total 26586 # number of UpgradeReq misses 967system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18299 # number of SCUpgradeReq misses 968system.cpu0.l2cache.SCUpgradeReq_misses::total 18299 # number of SCUpgradeReq misses 969system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 8 # number of SCUpgradeFailReq misses 970system.cpu0.l2cache.SCUpgradeFailReq_misses::total 8 # number of SCUpgradeFailReq misses 971system.cpu0.l2cache.ReadExReq_misses::cpu0.data 41687 # number of ReadExReq misses 972system.cpu0.l2cache.ReadExReq_misses::total 41687 # number of ReadExReq misses 973system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 215 # number of demand (read+write) misses 974system.cpu0.l2cache.demand_misses::cpu0.itb.walker 122 # number of demand (read+write) misses 975system.cpu0.l2cache.demand_misses::cpu0.inst 47151 # number of demand (read+write) misses 976system.cpu0.l2cache.demand_misses::cpu0.data 136634 # number of demand (read+write) misses 977system.cpu0.l2cache.demand_misses::total 184122 # number of demand (read+write) misses 978system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 215 # number of overall misses 979system.cpu0.l2cache.overall_misses::cpu0.itb.walker 122 # number of overall misses 980system.cpu0.l2cache.overall_misses::cpu0.inst 47151 # number of overall misses 981system.cpu0.l2cache.overall_misses::cpu0.data 136634 # number of overall misses 982system.cpu0.l2cache.overall_misses::total 184122 # number of overall misses 983system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 4899750 # number of ReadReq miss cycles 984system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2713500 # number of ReadReq miss cycles 985system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 2213649997 # number of ReadReq miss cycles 986system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2684439955 # number of ReadReq miss cycles 987system.cpu0.l2cache.ReadReq_miss_latency::total 4905703202 # number of ReadReq miss cycles 988system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 458226521 # number of UpgradeReq miss cycles 989system.cpu0.l2cache.UpgradeReq_miss_latency::total 458226521 # number of UpgradeReq miss cycles 990system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 356750783 # number of SCUpgradeReq miss cycles 991system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 356750783 # number of SCUpgradeReq miss cycles 992system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1434495 # number of SCUpgradeFailReq miss cycles 993system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1434495 # number of SCUpgradeFailReq miss cycles 994system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 1789174823 # number of ReadExReq miss cycles 995system.cpu0.l2cache.ReadExReq_miss_latency::total 1789174823 # number of ReadExReq miss cycles 996system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 4899750 # number of demand (read+write) miss cycles 997system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2713500 # number of demand (read+write) miss cycles 998system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2213649997 # number of demand (read+write) miss cycles 999system.cpu0.l2cache.demand_miss_latency::cpu0.data 4473614778 # number of demand (read+write) miss cycles 1000system.cpu0.l2cache.demand_miss_latency::total 6694878025 # number of demand (read+write) miss cycles 1001system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 4899750 # number of overall miss cycles 1002system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2713500 # number of overall miss cycles 1003system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2213649997 # number of overall miss cycles 1004system.cpu0.l2cache.overall_miss_latency::cpu0.data 4473614778 # number of overall miss cycles 1005system.cpu0.l2cache.overall_miss_latency::total 6694878025 # number of overall miss cycles 1006system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 7989 # number of ReadReq accesses(hits+misses) 1007system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3732 # number of ReadReq accesses(hits+misses) 1008system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1100319 # number of ReadReq accesses(hits+misses) 1009system.cpu0.l2cache.ReadReq_accesses::cpu0.data 476709 # number of ReadReq accesses(hits+misses) 1010system.cpu0.l2cache.ReadReq_accesses::total 1588749 # number of ReadReq accesses(hits+misses) 1011system.cpu0.l2cache.Writeback_accesses::writebacks 504114 # number of Writeback accesses(hits+misses) 1012system.cpu0.l2cache.Writeback_accesses::total 504114 # number of Writeback accesses(hits+misses) 1013system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 54992 # number of UpgradeReq accesses(hits+misses) 1014system.cpu0.l2cache.UpgradeReq_accesses::total 54992 # number of UpgradeReq accesses(hits+misses) 1015system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 19999 # number of SCUpgradeReq accesses(hits+misses) 1016system.cpu0.l2cache.SCUpgradeReq_accesses::total 19999 # number of SCUpgradeReq accesses(hits+misses) 1017system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 8 # number of SCUpgradeFailReq accesses(hits+misses) 1018system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 8 # number of SCUpgradeFailReq accesses(hits+misses) 1019system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269489 # number of ReadExReq accesses(hits+misses) 1020system.cpu0.l2cache.ReadExReq_accesses::total 269489 # number of ReadExReq accesses(hits+misses) 1021system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 7989 # number of demand (read+write) accesses 1022system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3732 # number of demand (read+write) accesses 1023system.cpu0.l2cache.demand_accesses::cpu0.inst 1100319 # number of demand (read+write) accesses 1024system.cpu0.l2cache.demand_accesses::cpu0.data 746198 # number of demand (read+write) accesses 1025system.cpu0.l2cache.demand_accesses::total 1858238 # number of demand (read+write) accesses 1026system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 7989 # number of overall (read+write) accesses 1027system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3732 # number of overall (read+write) accesses 1028system.cpu0.l2cache.overall_accesses::cpu0.inst 1100319 # number of overall (read+write) accesses 1029system.cpu0.l2cache.overall_accesses::cpu0.data 746198 # number of overall (read+write) accesses 1030system.cpu0.l2cache.overall_accesses::total 1858238 # number of overall (read+write) accesses 1031system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.026912 # miss rate for ReadReq accesses 1032system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.032690 # miss rate for ReadReq accesses 1033system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.042852 # miss rate for ReadReq accesses 1034system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.199172 # miss rate for ReadReq accesses 1035system.cpu0.l2cache.ReadReq_miss_rate::total 0.089652 # miss rate for ReadReq accesses 1036system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.483452 # miss rate for UpgradeReq accesses 1037system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.483452 # miss rate for UpgradeReq accesses 1038system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.914996 # miss rate for SCUpgradeReq accesses 1039system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.914996 # miss rate for SCUpgradeReq accesses 1040system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1041system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1042system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.154689 # miss rate for ReadExReq accesses 1043system.cpu0.l2cache.ReadExReq_miss_rate::total 0.154689 # miss rate for ReadExReq accesses 1044system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.026912 # miss rate for demand accesses 1045system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.032690 # miss rate for demand accesses 1046system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.042852 # miss rate for demand accesses 1047system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.183107 # miss rate for demand accesses 1048system.cpu0.l2cache.demand_miss_rate::total 0.099084 # miss rate for demand accesses 1049system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.026912 # miss rate for overall accesses 1050system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.032690 # miss rate for overall accesses 1051system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.042852 # miss rate for overall accesses 1052system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.183107 # miss rate for overall accesses 1053system.cpu0.l2cache.overall_miss_rate::total 0.099084 # miss rate for overall accesses 1054system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 22789.534884 # average ReadReq miss latency 1055system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22241.803279 # average ReadReq miss latency 1056system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 46948.102840 # average ReadReq miss latency 1057system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 28273.036062 # average ReadReq miss latency 1058system.cpu0.l2cache.ReadReq_avg_miss_latency::total 34441.697630 # average ReadReq miss latency 1059system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 17235.632325 # average UpgradeReq miss latency 1060system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17235.632325 # average UpgradeReq miss latency 1061system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19495.643642 # average SCUpgradeReq miss latency 1062system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19495.643642 # average SCUpgradeReq miss latency 1063system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 179311.875000 # average SCUpgradeFailReq miss latency 1064system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 179311.875000 # average SCUpgradeFailReq miss latency 1065system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 42919.251157 # average ReadExReq miss latency 1066system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 42919.251157 # average ReadExReq miss latency 1067system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 22789.534884 # average overall miss latency 1068system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22241.803279 # average overall miss latency 1069system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 46948.102840 # average overall miss latency 1070system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 32741.592708 # average overall miss latency 1071system.cpu0.l2cache.demand_avg_miss_latency::total 36361.097669 # average overall miss latency 1072system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 22789.534884 # average overall miss latency 1073system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22241.803279 # average overall miss latency 1074system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 46948.102840 # average overall miss latency 1075system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 32741.592708 # average overall miss latency 1076system.cpu0.l2cache.overall_avg_miss_latency::total 36361.097669 # average overall miss latency 1077system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1078system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1079system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1080system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1081system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1082system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1083system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1084system.cpu0.l2cache.cache_copies 0 # number of cache copies performed 1085system.cpu0.l2cache.writebacks::writebacks 196247 # number of writebacks 1086system.cpu0.l2cache.writebacks::total 196247 # number of writebacks 1087system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 32 # number of ReadReq MSHR hits 1088system.cpu0.l2cache.ReadReq_mshr_hits::total 32 # number of ReadReq MSHR hits 1089system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1210 # number of ReadExReq MSHR hits 1090system.cpu0.l2cache.ReadExReq_mshr_hits::total 1210 # number of ReadExReq MSHR hits 1091system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1242 # number of demand (read+write) MSHR hits 1092system.cpu0.l2cache.demand_mshr_hits::total 1242 # number of demand (read+write) MSHR hits 1093system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1242 # number of overall MSHR hits 1094system.cpu0.l2cache.overall_mshr_hits::total 1242 # number of overall MSHR hits 1095system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 215 # number of ReadReq MSHR misses 1096system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 122 # number of ReadReq MSHR misses 1097system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 47151 # number of ReadReq MSHR misses 1098system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 94915 # number of ReadReq MSHR misses 1099system.cpu0.l2cache.ReadReq_mshr_misses::total 142403 # number of ReadReq MSHR misses 1100system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 246323 # number of HardPFReq MSHR misses 1101system.cpu0.l2cache.HardPFReq_mshr_misses::total 246323 # number of HardPFReq MSHR misses 1102system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 26586 # number of UpgradeReq MSHR misses 1103system.cpu0.l2cache.UpgradeReq_mshr_misses::total 26586 # number of UpgradeReq MSHR misses 1104system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 18299 # number of SCUpgradeReq MSHR misses 1105system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 18299 # number of SCUpgradeReq MSHR misses 1106system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 8 # number of SCUpgradeFailReq MSHR misses 1107system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 8 # number of SCUpgradeFailReq MSHR misses 1108system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 40477 # number of ReadExReq MSHR misses 1109system.cpu0.l2cache.ReadExReq_mshr_misses::total 40477 # number of ReadExReq MSHR misses 1110system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 215 # number of demand (read+write) MSHR misses 1111system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 122 # number of demand (read+write) MSHR misses 1112system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 47151 # number of demand (read+write) MSHR misses 1113system.cpu0.l2cache.demand_mshr_misses::cpu0.data 135392 # number of demand (read+write) MSHR misses 1114system.cpu0.l2cache.demand_mshr_misses::total 182880 # number of demand (read+write) MSHR misses 1115system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 215 # number of overall MSHR misses 1116system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 122 # number of overall MSHR misses 1117system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 47151 # number of overall MSHR misses 1118system.cpu0.l2cache.overall_mshr_misses::cpu0.data 135392 # number of overall MSHR misses 1119system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 246323 # number of overall MSHR misses 1120system.cpu0.l2cache.overall_mshr_misses::total 429203 # number of overall MSHR misses 1121system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 3394250 # number of ReadReq MSHR miss cycles 1122system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 1859500 # number of ReadReq MSHR miss cycles 1123system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 1877090003 # number of ReadReq MSHR miss cycles 1124system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 2013208709 # number of ReadReq MSHR miss cycles 1125system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 3895552462 # number of ReadReq MSHR miss cycles 1126system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13906201830 # number of HardPFReq MSHR miss cycles 1127system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 13906201830 # number of HardPFReq MSHR miss cycles 1128system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 448274629 # number of UpgradeReq MSHR miss cycles 1129system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 448274629 # number of UpgradeReq MSHR miss cycles 1130system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 246009723 # number of SCUpgradeReq MSHR miss cycles 1131system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 246009723 # number of SCUpgradeReq MSHR miss cycles 1132system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1112495 # number of SCUpgradeFailReq MSHR miss cycles 1133system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1112495 # number of SCUpgradeFailReq MSHR miss cycles 1134system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1381066645 # number of ReadExReq MSHR miss cycles 1135system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1381066645 # number of ReadExReq MSHR miss cycles 1136system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 3394250 # number of demand (read+write) MSHR miss cycles 1137system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 1859500 # number of demand (read+write) MSHR miss cycles 1138system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 1877090003 # number of demand (read+write) MSHR miss cycles 1139system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3394275354 # number of demand (read+write) MSHR miss cycles 1140system.cpu0.l2cache.demand_mshr_miss_latency::total 5276619107 # number of demand (read+write) MSHR miss cycles 1141system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 3394250 # number of overall MSHR miss cycles 1142system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 1859500 # number of overall MSHR miss cycles 1143system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 1877090003 # number of overall MSHR miss cycles 1144system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3394275354 # number of overall MSHR miss cycles 1145system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13906201830 # number of overall MSHR miss cycles 1146system.cpu0.l2cache.overall_mshr_miss_latency::total 19182820937 # number of overall MSHR miss cycles 1147system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 647209500 # number of ReadReq MSHR uncacheable cycles 1148system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5743013251 # number of ReadReq MSHR uncacheable cycles 1149system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6390222751 # number of ReadReq MSHR uncacheable cycles 1150system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 4419325000 # number of WriteReq MSHR uncacheable cycles 1151system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4419325000 # number of WriteReq MSHR uncacheable cycles 1152system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 647209500 # number of overall MSHR uncacheable cycles 1153system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10162338251 # number of overall MSHR uncacheable cycles 1154system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 10809547751 # number of overall MSHR uncacheable cycles 1155system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.026912 # mshr miss rate for ReadReq accesses 1156system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.032690 # mshr miss rate for ReadReq accesses 1157system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.042852 # mshr miss rate for ReadReq accesses 1158system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.199105 # mshr miss rate for ReadReq accesses 1159system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.089632 # mshr miss rate for ReadReq accesses 1160system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1161system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1162system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.483452 # mshr miss rate for UpgradeReq accesses 1163system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.483452 # mshr miss rate for UpgradeReq accesses 1164system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.914996 # mshr miss rate for SCUpgradeReq accesses 1165system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.914996 # mshr miss rate for SCUpgradeReq accesses 1166system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1167system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1168system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.150199 # mshr miss rate for ReadExReq accesses 1169system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.150199 # mshr miss rate for ReadExReq accesses 1170system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.026912 # mshr miss rate for demand accesses 1171system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.032690 # mshr miss rate for demand accesses 1172system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.042852 # mshr miss rate for demand accesses 1173system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.181442 # mshr miss rate for demand accesses 1174system.cpu0.l2cache.demand_mshr_miss_rate::total 0.098416 # mshr miss rate for demand accesses 1175system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.026912 # mshr miss rate for overall accesses 1176system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.032690 # mshr miss rate for overall accesses 1177system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.042852 # mshr miss rate for overall accesses 1178system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.181442 # mshr miss rate for overall accesses 1179system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1180system.cpu0.l2cache.overall_mshr_miss_rate::total 0.230973 # mshr miss rate for overall accesses 1181system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 15787.209302 # average ReadReq mshr miss latency 1182system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15241.803279 # average ReadReq mshr miss latency 1183system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 39810.184365 # average ReadReq mshr miss latency 1184system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 21210.648570 # average ReadReq mshr miss latency 1185system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 27355.831422 # average ReadReq mshr miss latency 1186system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56455.149661 # average HardPFReq mshr miss latency 1187system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 56455.149661 # average HardPFReq mshr miss latency 1188system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16861.304032 # average UpgradeReq mshr miss latency 1189system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16861.304032 # average UpgradeReq mshr miss latency 1190system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13443.888901 # average SCUpgradeReq mshr miss latency 1191system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13443.888901 # average SCUpgradeReq mshr miss latency 1192system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 139061.875000 # average SCUpgradeFailReq mshr miss latency 1193system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 139061.875000 # average SCUpgradeFailReq mshr miss latency 1194system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 34119.787657 # average ReadExReq mshr miss latency 1195system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 34119.787657 # average ReadExReq mshr miss latency 1196system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 15787.209302 # average overall mshr miss latency 1197system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15241.803279 # average overall mshr miss latency 1198system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 39810.184365 # average overall mshr miss latency 1199system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 25069.984593 # average overall mshr miss latency 1200system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 28852.904128 # average overall mshr miss latency 1201system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 15787.209302 # average overall mshr miss latency 1202system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15241.803279 # average overall mshr miss latency 1203system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 39810.184365 # average overall mshr miss latency 1204system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 25069.984593 # average overall mshr miss latency 1205system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56455.149661 # average overall mshr miss latency 1206system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 44694.051386 # average overall mshr miss latency 1207system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1208system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1209system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1210system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1211system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1212system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1213system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1214system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1215system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1216system.cpu0.toL2Bus.trans_dist::ReadReq 1737767 # Transaction distribution 1217system.cpu0.toL2Bus.trans_dist::ReadResp 1686227 # Transaction distribution 1218system.cpu0.toL2Bus.trans_dist::WriteReq 27891 # Transaction distribution 1219system.cpu0.toL2Bus.trans_dist::WriteResp 27891 # Transaction distribution 1220system.cpu0.toL2Bus.trans_dist::Writeback 504114 # Transaction distribution 1221system.cpu0.toL2Bus.trans_dist::HardPFReq 316054 # Transaction distribution 1222system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution 1223system.cpu0.toL2Bus.trans_dist::UpgradeReq 89164 # Transaction distribution 1224system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42476 # Transaction distribution 1225system.cpu0.toL2Bus.trans_dist::UpgradeResp 112407 # Transaction distribution 1226system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 43 # Transaction distribution 1227system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 81 # Transaction distribution 1228system.cpu0.toL2Bus.trans_dist::ReadExReq 298764 # Transaction distribution 1229system.cpu0.toL2Bus.trans_dist::ReadExResp 285064 # Transaction distribution 1230system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2218682 # Packet count per connected master and slave (bytes) 1231system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2366147 # Packet count per connected master and slave (bytes) 1232system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10130 # Packet count per connected master and slave (bytes) 1233system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 22028 # Packet count per connected master and slave (bytes) 1234system.cpu0.toL2Bus.pkt_count::total 4616987 # Packet count per connected master and slave (bytes) 1235system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 70456504 # Cumulative packet size per connected master and slave (bytes) 1236system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 84324454 # Cumulative packet size per connected master and slave (bytes) 1237system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 14928 # Cumulative packet size per connected master and slave (bytes) 1238system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 31956 # Cumulative packet size per connected master and slave (bytes) 1239system.cpu0.toL2Bus.pkt_size::total 154827842 # Cumulative packet size per connected master and slave (bytes) 1240system.cpu0.toL2Bus.snoops 648932 # Total snoops (count) 1241system.cpu0.toL2Bus.snoop_fanout::samples 2984532 # Request fanout histogram 1242system.cpu0.toL2Bus.snoop_fanout::mean 5.180419 # Request fanout histogram 1243system.cpu0.toL2Bus.snoop_fanout::stdev 0.384536 # Request fanout histogram 1244system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1245system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1246system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1247system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1248system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1249system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 1250system.cpu0.toL2Bus.snoop_fanout::5 2446067 81.96% 81.96% # Request fanout histogram 1251system.cpu0.toL2Bus.snoop_fanout::6 538465 18.04% 100.00% # Request fanout histogram 1252system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1253system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1254system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 1255system.cpu0.toL2Bus.snoop_fanout::total 2984532 # Request fanout histogram 1256system.cpu0.toL2Bus.reqLayer0.occupancy 1775358935 # Layer occupancy (ticks) 1257system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1258system.cpu0.toL2Bus.snoopLayer0.occupancy 115165999 # Layer occupancy (ticks) 1259system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1260system.cpu0.toL2Bus.respLayer0.occupancy 1664866493 # Layer occupancy (ticks) 1261system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1262system.cpu0.toL2Bus.respLayer1.occupancy 1209535062 # Layer occupancy (ticks) 1263system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1264system.cpu0.toL2Bus.respLayer2.occupancy 6398000 # Layer occupancy (ticks) 1265system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1266system.cpu0.toL2Bus.respLayer3.occupancy 14039749 # Layer occupancy (ticks) 1267system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1268system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1269system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1270system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1271system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1272system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1273system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1274system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1275system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1276system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1277system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1278system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1279system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1280system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1281system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1282system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1283system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1284system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1285system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1286system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1287system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1288system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1289system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1290system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1291system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1292system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1293system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1294system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1295system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1296system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1297system.cpu1.dtb.walker.walks 3332 # Table walker walks requested 1298system.cpu1.dtb.walker.walksShort 3332 # Table walker walks initiated with short descriptors 1299system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 642 # Level at which table walker walks with short descriptors terminate 1300system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2690 # Level at which table walker walks with short descriptors terminate 1301system.cpu1.dtb.walker.walkWaitTime::samples 3332 # Table walker wait (enqueue to first request) latency 1302system.cpu1.dtb.walker.walkWaitTime::0 3332 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1303system.cpu1.dtb.walker.walkWaitTime::total 3332 # Table walker wait (enqueue to first request) latency 1304system.cpu1.dtb.walker.walkCompletionTime::samples 2562 # Table walker service (enqueue to completion) latency 1305system.cpu1.dtb.walker.walkCompletionTime::mean 8324.355972 # Table walker service (enqueue to completion) latency 1306system.cpu1.dtb.walker.walkCompletionTime::gmean 7260.502547 # Table walker service (enqueue to completion) latency 1307system.cpu1.dtb.walker.walkCompletionTime::stdev 4990.324891 # Table walker service (enqueue to completion) latency 1308system.cpu1.dtb.walker.walkCompletionTime::0-8191 2067 80.68% 80.68% # Table walker service (enqueue to completion) latency 1309system.cpu1.dtb.walker.walkCompletionTime::8192-16383 375 14.64% 95.32% # Table walker service (enqueue to completion) latency 1310system.cpu1.dtb.walker.walkCompletionTime::16384-24575 62 2.42% 97.74% # Table walker service (enqueue to completion) latency 1311system.cpu1.dtb.walker.walkCompletionTime::24576-32767 50 1.95% 99.69% # Table walker service (enqueue to completion) latency 1312system.cpu1.dtb.walker.walkCompletionTime::32768-40959 4 0.16% 99.84% # Table walker service (enqueue to completion) latency 1313system.cpu1.dtb.walker.walkCompletionTime::40960-49151 3 0.12% 99.96% # Table walker service (enqueue to completion) latency 1314system.cpu1.dtb.walker.walkCompletionTime::81920-90111 1 0.04% 100.00% # Table walker service (enqueue to completion) latency 1315system.cpu1.dtb.walker.walkCompletionTime::total 2562 # Table walker service (enqueue to completion) latency 1316system.cpu1.dtb.walker.walksPending::samples 1455144968 # Table walker pending requests distribution 1317system.cpu1.dtb.walker.walksPending::0 1455144968 100.00% 100.00% # Table walker pending requests distribution 1318system.cpu1.dtb.walker.walksPending::total 1455144968 # Table walker pending requests distribution 1319system.cpu1.dtb.walker.walkPageSizes::4K 1928 75.25% 75.25% # Table walker page sizes translated 1320system.cpu1.dtb.walker.walkPageSizes::1M 634 24.75% 100.00% # Table walker page sizes translated 1321system.cpu1.dtb.walker.walkPageSizes::total 2562 # Table walker page sizes translated 1322system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3332 # Table walker requests started/completed, data/inst 1323system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1324system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3332 # Table walker requests started/completed, data/inst 1325system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2562 # Table walker requests started/completed, data/inst 1326system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1327system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2562 # Table walker requests started/completed, data/inst 1328system.cpu1.dtb.walker.walkRequestOrigin::total 5894 # Table walker requests started/completed, data/inst 1329system.cpu1.dtb.inst_hits 0 # ITB inst hits 1330system.cpu1.dtb.inst_misses 0 # ITB inst misses 1331system.cpu1.dtb.read_hits 10115566 # DTB read hits 1332system.cpu1.dtb.read_misses 2828 # DTB read misses 1333system.cpu1.dtb.write_hits 6544640 # DTB write hits 1334system.cpu1.dtb.write_misses 504 # DTB write misses 1335system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1336system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1337system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1338system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1339system.cpu1.dtb.flush_entries 2029 # Number of entries that have been flushed from TLB 1340system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 1341system.cpu1.dtb.prefetch_faults 346 # Number of TLB faults due to prefetch 1342system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1343system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions 1344system.cpu1.dtb.read_accesses 10118394 # DTB read accesses 1345system.cpu1.dtb.write_accesses 6545144 # DTB write accesses 1346system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1347system.cpu1.dtb.hits 16660206 # DTB hits 1348system.cpu1.dtb.misses 3332 # DTB misses 1349system.cpu1.dtb.accesses 16663538 # DTB accesses 1350system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1351system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1352system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1353system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1354system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1355system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1356system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1357system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1358system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1359system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1360system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1361system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1362system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1363system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1364system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1365system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1366system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1367system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1368system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1369system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1370system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1371system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1372system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1373system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1374system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1375system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1376system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1377system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1378system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1379system.cpu1.itb.walker.walks 1746 # Table walker walks requested 1380system.cpu1.itb.walker.walksShort 1746 # Table walker walks initiated with short descriptors 1381system.cpu1.itb.walker.walksShortTerminationLevel::Level1 168 # Level at which table walker walks with short descriptors terminate 1382system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1578 # Level at which table walker walks with short descriptors terminate 1383system.cpu1.itb.walker.walkWaitTime::samples 1746 # Table walker wait (enqueue to first request) latency 1384system.cpu1.itb.walker.walkWaitTime::0 1746 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1385system.cpu1.itb.walker.walkWaitTime::total 1746 # Table walker wait (enqueue to first request) latency 1386system.cpu1.itb.walker.walkCompletionTime::samples 1107 # Table walker service (enqueue to completion) latency 1387system.cpu1.itb.walker.walkCompletionTime::mean 8955.736224 # Table walker service (enqueue to completion) latency 1388system.cpu1.itb.walker.walkCompletionTime::gmean 7685.889357 # Table walker service (enqueue to completion) latency 1389system.cpu1.itb.walker.walkCompletionTime::stdev 5645.921496 # Table walker service (enqueue to completion) latency 1390system.cpu1.itb.walker.walkCompletionTime::0-4095 191 17.25% 17.25% # Table walker service (enqueue to completion) latency 1391system.cpu1.itb.walker.walkCompletionTime::4096-8191 643 58.08% 75.34% # Table walker service (enqueue to completion) latency 1392system.cpu1.itb.walker.walkCompletionTime::12288-16383 217 19.60% 94.94% # Table walker service (enqueue to completion) latency 1393system.cpu1.itb.walker.walkCompletionTime::16384-20479 1 0.09% 95.03% # Table walker service (enqueue to completion) latency 1394system.cpu1.itb.walker.walkCompletionTime::20480-24575 3 0.27% 95.30% # Table walker service (enqueue to completion) latency 1395system.cpu1.itb.walker.walkCompletionTime::24576-28671 27 2.44% 97.74% # Table walker service (enqueue to completion) latency 1396system.cpu1.itb.walker.walkCompletionTime::28672-32767 19 1.72% 99.46% # Table walker service (enqueue to completion) latency 1397system.cpu1.itb.walker.walkCompletionTime::36864-40959 3 0.27% 99.73% # Table walker service (enqueue to completion) latency 1398system.cpu1.itb.walker.walkCompletionTime::40960-45055 3 0.27% 100.00% # Table walker service (enqueue to completion) latency 1399system.cpu1.itb.walker.walkCompletionTime::total 1107 # Table walker service (enqueue to completion) latency 1400system.cpu1.itb.walker.walksPending::samples 1454651968 # Table walker pending requests distribution 1401system.cpu1.itb.walker.walksPending::0 1454651968 100.00% 100.00% # Table walker pending requests distribution 1402system.cpu1.itb.walker.walksPending::total 1454651968 # Table walker pending requests distribution 1403system.cpu1.itb.walker.walkPageSizes::4K 939 84.82% 84.82% # Table walker page sizes translated 1404system.cpu1.itb.walker.walkPageSizes::1M 168 15.18% 100.00% # Table walker page sizes translated 1405system.cpu1.itb.walker.walkPageSizes::total 1107 # Table walker page sizes translated 1406system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1407system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1746 # Table walker requests started/completed, data/inst 1408system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1746 # Table walker requests started/completed, data/inst 1409system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1410system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1107 # Table walker requests started/completed, data/inst 1411system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1107 # Table walker requests started/completed, data/inst 1412system.cpu1.itb.walker.walkRequestOrigin::total 2853 # Table walker requests started/completed, data/inst 1413system.cpu1.itb.inst_hits 44359905 # ITB inst hits 1414system.cpu1.itb.inst_misses 1746 # ITB inst misses 1415system.cpu1.itb.read_hits 0 # DTB read hits 1416system.cpu1.itb.read_misses 0 # DTB read misses 1417system.cpu1.itb.write_hits 0 # DTB write hits 1418system.cpu1.itb.write_misses 0 # DTB write misses 1419system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1420system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1421system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1422system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1423system.cpu1.itb.flush_entries 1148 # Number of entries that have been flushed from TLB 1424system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1425system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1426system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1427system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1428system.cpu1.itb.read_accesses 0 # DTB read accesses 1429system.cpu1.itb.write_accesses 0 # DTB write accesses 1430system.cpu1.itb.inst_accesses 44361651 # ITB inst accesses 1431system.cpu1.itb.hits 44359905 # DTB hits 1432system.cpu1.itb.misses 1746 # DTB misses 1433system.cpu1.itb.accesses 44361651 # DTB accesses 1434system.cpu1.numCycles 5735725430 # number of cpu cycles simulated 1435system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1436system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1437system.cpu1.committedInsts 42482884 # Number of instructions committed 1438system.cpu1.committedOps 52173895 # Number of ops (including micro ops) committed 1439system.cpu1.num_int_alu_accesses 47161467 # Number of integer alu accesses 1440system.cpu1.num_fp_alu_accesses 1857 # Number of float alu accesses 1441system.cpu1.num_func_calls 7121857 # number of times a function call or return occured 1442system.cpu1.num_conditional_control_insts 4915281 # number of instructions that are conditional controls 1443system.cpu1.num_int_insts 47161467 # number of integer instructions 1444system.cpu1.num_fp_insts 1857 # number of float instructions 1445system.cpu1.num_int_register_reads 90906541 # number of times the integer registers were read 1446system.cpu1.num_int_register_writes 34070734 # number of times the integer registers were written 1447system.cpu1.num_fp_register_reads 1341 # number of times the floating registers were read 1448system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written 1449system.cpu1.num_cc_register_reads 192636366 # number of times the CC registers were read 1450system.cpu1.num_cc_register_writes 15749934 # number of times the CC registers were written 1451system.cpu1.num_mem_refs 16924073 # number of memory refs 1452system.cpu1.num_load_insts 10229886 # Number of load instructions 1453system.cpu1.num_store_insts 6694187 # Number of store instructions 1454system.cpu1.num_idle_cycles 5637554126.704413 # Number of idle cycles 1455system.cpu1.num_busy_cycles 98171303.295587 # Number of busy cycles 1456system.cpu1.not_idle_fraction 0.017116 # Percentage of non-idle cycles 1457system.cpu1.idle_fraction 0.982884 # Percentage of idle cycles 1458system.cpu1.Branches 12116511 # Number of branches fetched 1459system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction 1460system.cpu1.op_class::IntAlu 37117349 68.64% 68.64% # Class of executed instruction 1461system.cpu1.op_class::IntMult 29132 0.05% 68.70% # Class of executed instruction 1462system.cpu1.op_class::IntDiv 0 0.00% 68.70% # Class of executed instruction 1463system.cpu1.op_class::FloatAdd 0 0.00% 68.70% # Class of executed instruction 1464system.cpu1.op_class::FloatCmp 0 0.00% 68.70% # Class of executed instruction 1465system.cpu1.op_class::FloatCvt 0 0.00% 68.70% # Class of executed instruction 1466system.cpu1.op_class::FloatMult 0 0.00% 68.70% # Class of executed instruction 1467system.cpu1.op_class::FloatDiv 0 0.00% 68.70% # Class of executed instruction 1468system.cpu1.op_class::FloatSqrt 0 0.00% 68.70% # Class of executed instruction 1469system.cpu1.op_class::SimdAdd 0 0.00% 68.70% # Class of executed instruction 1470system.cpu1.op_class::SimdAddAcc 0 0.00% 68.70% # Class of executed instruction 1471system.cpu1.op_class::SimdAlu 0 0.00% 68.70% # Class of executed instruction 1472system.cpu1.op_class::SimdCmp 0 0.00% 68.70% # Class of executed instruction 1473system.cpu1.op_class::SimdCvt 0 0.00% 68.70% # Class of executed instruction 1474system.cpu1.op_class::SimdMisc 0 0.00% 68.70% # Class of executed instruction 1475system.cpu1.op_class::SimdMult 0 0.00% 68.70% # Class of executed instruction 1476system.cpu1.op_class::SimdMultAcc 0 0.00% 68.70% # Class of executed instruction 1477system.cpu1.op_class::SimdShift 0 0.00% 68.70% # Class of executed instruction 1478system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.70% # Class of executed instruction 1479system.cpu1.op_class::SimdSqrt 0 0.00% 68.70% # Class of executed instruction 1480system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.70% # Class of executed instruction 1481system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.70% # Class of executed instruction 1482system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.70% # Class of executed instruction 1483system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.70% # Class of executed instruction 1484system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.70% # Class of executed instruction 1485system.cpu1.op_class::SimdFloatMisc 3361 0.01% 68.70% # Class of executed instruction 1486system.cpu1.op_class::SimdFloatMult 0 0.00% 68.70% # Class of executed instruction 1487system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.70% # Class of executed instruction 1488system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.70% # Class of executed instruction 1489system.cpu1.op_class::MemRead 10229886 18.92% 87.62% # Class of executed instruction 1490system.cpu1.op_class::MemWrite 6694187 12.38% 100.00% # Class of executed instruction 1491system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 1492system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 1493system.cpu1.op_class::total 54073981 # Class of executed instruction 1494system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1495system.cpu1.kern.inst.quiesce 2789 # number of quiesce instructions executed 1496system.cpu1.dcache.tags.replacements 191058 # number of replacements 1497system.cpu1.dcache.tags.tagsinuse 472.360308 # Cycle average of tags in use 1498system.cpu1.dcache.tags.total_refs 16390617 # Total number of references to valid blocks. 1499system.cpu1.dcache.tags.sampled_refs 191421 # Sample count of references to valid blocks. 1500system.cpu1.dcache.tags.avg_refs 85.626013 # Average number of references to valid blocks. 1501system.cpu1.dcache.tags.warmup_cycle 104654883500 # Cycle when the warmup percentage was hit. 1502system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.360308 # Average occupied blocks per requestor 1503system.cpu1.dcache.tags.occ_percent::cpu1.data 0.922579 # Average percentage of cache occupancy 1504system.cpu1.dcache.tags.occ_percent::total 0.922579 # Average percentage of cache occupancy 1505system.cpu1.dcache.tags.occ_task_id_blocks::1024 363 # Occupied blocks per task id 1506system.cpu1.dcache.tags.age_task_id_blocks_1024::2 312 # Occupied blocks per task id 1507system.cpu1.dcache.tags.age_task_id_blocks_1024::3 51 # Occupied blocks per task id 1508system.cpu1.dcache.tags.occ_task_id_percent::1024 0.708984 # Percentage of cache occupancy per task id 1509system.cpu1.dcache.tags.tag_accesses 33541448 # Number of tag accesses 1510system.cpu1.dcache.tags.data_accesses 33541448 # Number of data accesses 1511system.cpu1.dcache.ReadReq_hits::cpu1.data 9797337 # number of ReadReq hits 1512system.cpu1.dcache.ReadReq_hits::total 9797337 # number of ReadReq hits 1513system.cpu1.dcache.WriteReq_hits::cpu1.data 6353174 # number of WriteReq hits 1514system.cpu1.dcache.WriteReq_hits::total 6353174 # number of WriteReq hits 1515system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49731 # number of SoftPFReq hits 1516system.cpu1.dcache.SoftPFReq_hits::total 49731 # number of SoftPFReq hits 1517system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 79655 # number of LoadLockedReq hits 1518system.cpu1.dcache.LoadLockedReq_hits::total 79655 # number of LoadLockedReq hits 1519system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71640 # number of StoreCondReq hits 1520system.cpu1.dcache.StoreCondReq_hits::total 71640 # number of StoreCondReq hits 1521system.cpu1.dcache.demand_hits::cpu1.data 16150511 # number of demand (read+write) hits 1522system.cpu1.dcache.demand_hits::total 16150511 # number of demand (read+write) hits 1523system.cpu1.dcache.overall_hits::cpu1.data 16200242 # number of overall hits 1524system.cpu1.dcache.overall_hits::total 16200242 # number of overall hits 1525system.cpu1.dcache.ReadReq_misses::cpu1.data 137366 # number of ReadReq misses 1526system.cpu1.dcache.ReadReq_misses::total 137366 # number of ReadReq misses 1527system.cpu1.dcache.WriteReq_misses::cpu1.data 93147 # number of WriteReq misses 1528system.cpu1.dcache.WriteReq_misses::total 93147 # number of WriteReq misses 1529system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30426 # number of SoftPFReq misses 1530system.cpu1.dcache.SoftPFReq_misses::total 30426 # number of SoftPFReq misses 1531system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17223 # number of LoadLockedReq misses 1532system.cpu1.dcache.LoadLockedReq_misses::total 17223 # number of LoadLockedReq misses 1533system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23379 # number of StoreCondReq misses 1534system.cpu1.dcache.StoreCondReq_misses::total 23379 # number of StoreCondReq misses 1535system.cpu1.dcache.demand_misses::cpu1.data 230513 # number of demand (read+write) misses 1536system.cpu1.dcache.demand_misses::total 230513 # number of demand (read+write) misses 1537system.cpu1.dcache.overall_misses::cpu1.data 260939 # number of overall misses 1538system.cpu1.dcache.overall_misses::total 260939 # number of overall misses 1539system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1997360003 # number of ReadReq miss cycles 1540system.cpu1.dcache.ReadReq_miss_latency::total 1997360003 # number of ReadReq miss cycles 1541system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2352005341 # number of WriteReq miss cycles 1542system.cpu1.dcache.WriteReq_miss_latency::total 2352005341 # number of WriteReq miss cycles 1543system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 320800000 # number of LoadLockedReq miss cycles 1544system.cpu1.dcache.LoadLockedReq_miss_latency::total 320800000 # number of LoadLockedReq miss cycles 1545system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 539390293 # number of StoreCondReq miss cycles 1546system.cpu1.dcache.StoreCondReq_miss_latency::total 539390293 # number of StoreCondReq miss cycles 1547system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1691000 # number of StoreCondFailReq miss cycles 1548system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1691000 # number of StoreCondFailReq miss cycles 1549system.cpu1.dcache.demand_miss_latency::cpu1.data 4349365344 # number of demand (read+write) miss cycles 1550system.cpu1.dcache.demand_miss_latency::total 4349365344 # number of demand (read+write) miss cycles 1551system.cpu1.dcache.overall_miss_latency::cpu1.data 4349365344 # number of overall miss cycles 1552system.cpu1.dcache.overall_miss_latency::total 4349365344 # number of overall miss cycles 1553system.cpu1.dcache.ReadReq_accesses::cpu1.data 9934703 # number of ReadReq accesses(hits+misses) 1554system.cpu1.dcache.ReadReq_accesses::total 9934703 # number of ReadReq accesses(hits+misses) 1555system.cpu1.dcache.WriteReq_accesses::cpu1.data 6446321 # number of WriteReq accesses(hits+misses) 1556system.cpu1.dcache.WriteReq_accesses::total 6446321 # number of WriteReq accesses(hits+misses) 1557system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80157 # number of SoftPFReq accesses(hits+misses) 1558system.cpu1.dcache.SoftPFReq_accesses::total 80157 # number of SoftPFReq accesses(hits+misses) 1559system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96878 # number of LoadLockedReq accesses(hits+misses) 1560system.cpu1.dcache.LoadLockedReq_accesses::total 96878 # number of LoadLockedReq accesses(hits+misses) 1561system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 95019 # number of StoreCondReq accesses(hits+misses) 1562system.cpu1.dcache.StoreCondReq_accesses::total 95019 # number of StoreCondReq accesses(hits+misses) 1563system.cpu1.dcache.demand_accesses::cpu1.data 16381024 # number of demand (read+write) accesses 1564system.cpu1.dcache.demand_accesses::total 16381024 # number of demand (read+write) accesses 1565system.cpu1.dcache.overall_accesses::cpu1.data 16461181 # number of overall (read+write) accesses 1566system.cpu1.dcache.overall_accesses::total 16461181 # number of overall (read+write) accesses 1567system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.013827 # miss rate for ReadReq accesses 1568system.cpu1.dcache.ReadReq_miss_rate::total 0.013827 # miss rate for ReadReq accesses 1569system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.014450 # miss rate for WriteReq accesses 1570system.cpu1.dcache.WriteReq_miss_rate::total 0.014450 # miss rate for WriteReq accesses 1571system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.379580 # miss rate for SoftPFReq accesses 1572system.cpu1.dcache.SoftPFReq_miss_rate::total 0.379580 # miss rate for SoftPFReq accesses 1573system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.177780 # miss rate for LoadLockedReq accesses 1574system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.177780 # miss rate for LoadLockedReq accesses 1575system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.246046 # miss rate for StoreCondReq accesses 1576system.cpu1.dcache.StoreCondReq_miss_rate::total 0.246046 # miss rate for StoreCondReq accesses 1577system.cpu1.dcache.demand_miss_rate::cpu1.data 0.014072 # miss rate for demand accesses 1578system.cpu1.dcache.demand_miss_rate::total 0.014072 # miss rate for demand accesses 1579system.cpu1.dcache.overall_miss_rate::cpu1.data 0.015852 # miss rate for overall accesses 1580system.cpu1.dcache.overall_miss_rate::total 0.015852 # miss rate for overall accesses 1581system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14540.424872 # average ReadReq miss latency 1582system.cpu1.dcache.ReadReq_avg_miss_latency::total 14540.424872 # average ReadReq miss latency 1583system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25250.467981 # average WriteReq miss latency 1584system.cpu1.dcache.WriteReq_avg_miss_latency::total 25250.467981 # average WriteReq miss latency 1585system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18626.255588 # average LoadLockedReq miss latency 1586system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18626.255588 # average LoadLockedReq miss latency 1587system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23071.572480 # average StoreCondReq miss latency 1588system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23071.572480 # average StoreCondReq miss latency 1589system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1590system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1591system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18868.199815 # average overall miss latency 1592system.cpu1.dcache.demand_avg_miss_latency::total 18868.199815 # average overall miss latency 1593system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16668.130651 # average overall miss latency 1594system.cpu1.dcache.overall_avg_miss_latency::total 16668.130651 # average overall miss latency 1595system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1596system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1597system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1598system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1599system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1600system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1601system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1602system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1603system.cpu1.dcache.writebacks::writebacks 118649 # number of writebacks 1604system.cpu1.dcache.writebacks::total 118649 # number of writebacks 1605system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 239 # number of ReadReq MSHR hits 1606system.cpu1.dcache.ReadReq_mshr_hits::total 239 # number of ReadReq MSHR hits 1607system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12076 # number of LoadLockedReq MSHR hits 1608system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12076 # number of LoadLockedReq MSHR hits 1609system.cpu1.dcache.demand_mshr_hits::cpu1.data 239 # number of demand (read+write) MSHR hits 1610system.cpu1.dcache.demand_mshr_hits::total 239 # number of demand (read+write) MSHR hits 1611system.cpu1.dcache.overall_mshr_hits::cpu1.data 239 # number of overall MSHR hits 1612system.cpu1.dcache.overall_mshr_hits::total 239 # number of overall MSHR hits 1613system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 137127 # number of ReadReq MSHR misses 1614system.cpu1.dcache.ReadReq_mshr_misses::total 137127 # number of ReadReq MSHR misses 1615system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 93147 # number of WriteReq MSHR misses 1616system.cpu1.dcache.WriteReq_mshr_misses::total 93147 # number of WriteReq MSHR misses 1617system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29658 # number of SoftPFReq MSHR misses 1618system.cpu1.dcache.SoftPFReq_mshr_misses::total 29658 # number of SoftPFReq MSHR misses 1619system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5147 # number of LoadLockedReq MSHR misses 1620system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5147 # number of LoadLockedReq MSHR misses 1621system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23379 # number of StoreCondReq MSHR misses 1622system.cpu1.dcache.StoreCondReq_mshr_misses::total 23379 # number of StoreCondReq MSHR misses 1623system.cpu1.dcache.demand_mshr_misses::cpu1.data 230274 # number of demand (read+write) MSHR misses 1624system.cpu1.dcache.demand_mshr_misses::total 230274 # number of demand (read+write) MSHR misses 1625system.cpu1.dcache.overall_mshr_misses::cpu1.data 259932 # number of overall MSHR misses 1626system.cpu1.dcache.overall_mshr_misses::total 259932 # number of overall MSHR misses 1627system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1715737747 # number of ReadReq MSHR miss cycles 1628system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1715737747 # number of ReadReq MSHR miss cycles 1629system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2159697659 # number of WriteReq MSHR miss cycles 1630system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2159697659 # number of WriteReq MSHR miss cycles 1631system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 467259500 # number of SoftPFReq MSHR miss cycles 1632system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 467259500 # number of SoftPFReq MSHR miss cycles 1633system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 82226250 # number of LoadLockedReq MSHR miss cycles 1634system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 82226250 # number of LoadLockedReq MSHR miss cycles 1635system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 491497707 # number of StoreCondReq MSHR miss cycles 1636system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 491497707 # number of StoreCondReq MSHR miss cycles 1637system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1621000 # number of StoreCondFailReq MSHR miss cycles 1638system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1621000 # number of StoreCondFailReq MSHR miss cycles 1639system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3875435406 # number of demand (read+write) MSHR miss cycles 1640system.cpu1.dcache.demand_mshr_miss_latency::total 3875435406 # number of demand (read+write) MSHR miss cycles 1641system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4342694906 # number of overall MSHR miss cycles 1642system.cpu1.dcache.overall_mshr_miss_latency::total 4342694906 # number of overall MSHR miss cycles 1643system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 525084500 # number of ReadReq MSHR uncacheable cycles 1644system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 525084500 # number of ReadReq MSHR uncacheable cycles 1645system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 379956000 # number of WriteReq MSHR uncacheable cycles 1646system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 379956000 # number of WriteReq MSHR uncacheable cycles 1647system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 905040500 # number of overall MSHR uncacheable cycles 1648system.cpu1.dcache.overall_mshr_uncacheable_latency::total 905040500 # number of overall MSHR uncacheable cycles 1649system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013803 # mshr miss rate for ReadReq accesses 1650system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.013803 # mshr miss rate for ReadReq accesses 1651system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014450 # mshr miss rate for WriteReq accesses 1652system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014450 # mshr miss rate for WriteReq accesses 1653system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.369999 # mshr miss rate for SoftPFReq accesses 1654system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.369999 # mshr miss rate for SoftPFReq accesses 1655system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.053129 # mshr miss rate for LoadLockedReq accesses 1656system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.053129 # mshr miss rate for LoadLockedReq accesses 1657system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.246046 # mshr miss rate for StoreCondReq accesses 1658system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.246046 # mshr miss rate for StoreCondReq accesses 1659system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014057 # mshr miss rate for demand accesses 1660system.cpu1.dcache.demand_mshr_miss_rate::total 0.014057 # mshr miss rate for demand accesses 1661system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.015791 # mshr miss rate for overall accesses 1662system.cpu1.dcache.overall_mshr_miss_rate::total 0.015791 # mshr miss rate for overall accesses 1663system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12512.034443 # average ReadReq mshr miss latency 1664system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12512.034443 # average ReadReq mshr miss latency 1665system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23185.906782 # average WriteReq mshr miss latency 1666system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23185.906782 # average WriteReq mshr miss latency 1667system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15754.922786 # average SoftPFReq mshr miss latency 1668system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15754.922786 # average SoftPFReq mshr miss latency 1669system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15975.568292 # average LoadLockedReq mshr miss latency 1670system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15975.568292 # average LoadLockedReq mshr miss latency 1671system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21023.042346 # average StoreCondReq mshr miss latency 1672system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21023.042346 # average StoreCondReq mshr miss latency 1673system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1674system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1675system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16829.669898 # average overall mshr miss latency 1676system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16829.669898 # average overall mshr miss latency 1677system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16707.042250 # average overall mshr miss latency 1678system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16707.042250 # average overall mshr miss latency 1679system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1680system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1681system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1682system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1683system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1684system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1685system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1686system.cpu1.icache.tags.replacements 526723 # number of replacements 1687system.cpu1.icache.tags.tagsinuse 498.608741 # Cycle average of tags in use 1688system.cpu1.icache.tags.total_refs 43832665 # Total number of references to valid blocks. 1689system.cpu1.icache.tags.sampled_refs 527235 # Sample count of references to valid blocks. 1690system.cpu1.icache.tags.avg_refs 83.136865 # Average number of references to valid blocks. 1691system.cpu1.icache.tags.warmup_cycle 84507534000 # Cycle when the warmup percentage was hit. 1692system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.608741 # Average occupied blocks per requestor 1693system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973845 # Average percentage of cache occupancy 1694system.cpu1.icache.tags.occ_percent::total 0.973845 # Average percentage of cache occupancy 1695system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1696system.cpu1.icache.tags.age_task_id_blocks_1024::2 387 # Occupied blocks per task id 1697system.cpu1.icache.tags.age_task_id_blocks_1024::3 122 # Occupied blocks per task id 1698system.cpu1.icache.tags.age_task_id_blocks_1024::4 3 # Occupied blocks per task id 1699system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1700system.cpu1.icache.tags.tag_accesses 89247035 # Number of tag accesses 1701system.cpu1.icache.tags.data_accesses 89247035 # Number of data accesses 1702system.cpu1.icache.ReadReq_hits::cpu1.inst 43832665 # number of ReadReq hits 1703system.cpu1.icache.ReadReq_hits::total 43832665 # number of ReadReq hits 1704system.cpu1.icache.demand_hits::cpu1.inst 43832665 # number of demand (read+write) hits 1705system.cpu1.icache.demand_hits::total 43832665 # number of demand (read+write) hits 1706system.cpu1.icache.overall_hits::cpu1.inst 43832665 # number of overall hits 1707system.cpu1.icache.overall_hits::total 43832665 # number of overall hits 1708system.cpu1.icache.ReadReq_misses::cpu1.inst 527235 # number of ReadReq misses 1709system.cpu1.icache.ReadReq_misses::total 527235 # number of ReadReq misses 1710system.cpu1.icache.demand_misses::cpu1.inst 527235 # number of demand (read+write) misses 1711system.cpu1.icache.demand_misses::total 527235 # number of demand (read+write) misses 1712system.cpu1.icache.overall_misses::cpu1.inst 527235 # number of overall misses 1713system.cpu1.icache.overall_misses::total 527235 # number of overall misses 1714system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4617960760 # number of ReadReq miss cycles 1715system.cpu1.icache.ReadReq_miss_latency::total 4617960760 # number of ReadReq miss cycles 1716system.cpu1.icache.demand_miss_latency::cpu1.inst 4617960760 # number of demand (read+write) miss cycles 1717system.cpu1.icache.demand_miss_latency::total 4617960760 # number of demand (read+write) miss cycles 1718system.cpu1.icache.overall_miss_latency::cpu1.inst 4617960760 # number of overall miss cycles 1719system.cpu1.icache.overall_miss_latency::total 4617960760 # number of overall miss cycles 1720system.cpu1.icache.ReadReq_accesses::cpu1.inst 44359900 # number of ReadReq accesses(hits+misses) 1721system.cpu1.icache.ReadReq_accesses::total 44359900 # number of ReadReq accesses(hits+misses) 1722system.cpu1.icache.demand_accesses::cpu1.inst 44359900 # number of demand (read+write) accesses 1723system.cpu1.icache.demand_accesses::total 44359900 # number of demand (read+write) accesses 1724system.cpu1.icache.overall_accesses::cpu1.inst 44359900 # number of overall (read+write) accesses 1725system.cpu1.icache.overall_accesses::total 44359900 # number of overall (read+write) accesses 1726system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011885 # miss rate for ReadReq accesses 1727system.cpu1.icache.ReadReq_miss_rate::total 0.011885 # miss rate for ReadReq accesses 1728system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011885 # miss rate for demand accesses 1729system.cpu1.icache.demand_miss_rate::total 0.011885 # miss rate for demand accesses 1730system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011885 # miss rate for overall accesses 1731system.cpu1.icache.overall_miss_rate::total 0.011885 # miss rate for overall accesses 1732system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8758.828151 # average ReadReq miss latency 1733system.cpu1.icache.ReadReq_avg_miss_latency::total 8758.828151 # average ReadReq miss latency 1734system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8758.828151 # average overall miss latency 1735system.cpu1.icache.demand_avg_miss_latency::total 8758.828151 # average overall miss latency 1736system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8758.828151 # average overall miss latency 1737system.cpu1.icache.overall_avg_miss_latency::total 8758.828151 # average overall miss latency 1738system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1739system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1740system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1741system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1742system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1743system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1744system.cpu1.icache.fast_writes 0 # number of fast writes performed 1745system.cpu1.icache.cache_copies 0 # number of cache copies performed 1746system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 527235 # number of ReadReq MSHR misses 1747system.cpu1.icache.ReadReq_mshr_misses::total 527235 # number of ReadReq MSHR misses 1748system.cpu1.icache.demand_mshr_misses::cpu1.inst 527235 # number of demand (read+write) MSHR misses 1749system.cpu1.icache.demand_mshr_misses::total 527235 # number of demand (read+write) MSHR misses 1750system.cpu1.icache.overall_mshr_misses::cpu1.inst 527235 # number of overall MSHR misses 1751system.cpu1.icache.overall_mshr_misses::total 527235 # number of overall MSHR misses 1752system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3826248740 # number of ReadReq MSHR miss cycles 1753system.cpu1.icache.ReadReq_mshr_miss_latency::total 3826248740 # number of ReadReq MSHR miss cycles 1754system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3826248740 # number of demand (read+write) MSHR miss cycles 1755system.cpu1.icache.demand_mshr_miss_latency::total 3826248740 # number of demand (read+write) MSHR miss cycles 1756system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3826248740 # number of overall MSHR miss cycles 1757system.cpu1.icache.overall_mshr_miss_latency::total 3826248740 # number of overall MSHR miss cycles 1758system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13994500 # number of ReadReq MSHR uncacheable cycles 1759system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 13994500 # number of ReadReq MSHR uncacheable cycles 1760system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 13994500 # number of overall MSHR uncacheable cycles 1761system.cpu1.icache.overall_mshr_uncacheable_latency::total 13994500 # number of overall MSHR uncacheable cycles 1762system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011885 # mshr miss rate for ReadReq accesses 1763system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011885 # mshr miss rate for ReadReq accesses 1764system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011885 # mshr miss rate for demand accesses 1765system.cpu1.icache.demand_mshr_miss_rate::total 0.011885 # mshr miss rate for demand accesses 1766system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011885 # mshr miss rate for overall accesses 1767system.cpu1.icache.overall_mshr_miss_rate::total 0.011885 # mshr miss rate for overall accesses 1768system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7257.197910 # average ReadReq mshr miss latency 1769system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7257.197910 # average ReadReq mshr miss latency 1770system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7257.197910 # average overall mshr miss latency 1771system.cpu1.icache.demand_avg_mshr_miss_latency::total 7257.197910 # average overall mshr miss latency 1772system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7257.197910 # average overall mshr miss latency 1773system.cpu1.icache.overall_avg_mshr_miss_latency::total 7257.197910 # average overall mshr miss latency 1774system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1775system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1776system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1777system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1778system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1779system.cpu1.l2cache.prefetcher.num_hwpf_issued 199846 # number of hwpf issued 1780system.cpu1.l2cache.prefetcher.pfIdentified 199846 # number of prefetch candidates identified 1781system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 1782system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1783system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1784system.cpu1.l2cache.prefetcher.pfSpanPage 59474 # number of prefetches not generated due to page crossing 1785system.cpu1.l2cache.tags.replacements 47689 # number of replacements 1786system.cpu1.l2cache.tags.tagsinuse 15083.724459 # Cycle average of tags in use 1787system.cpu1.l2cache.tags.total_refs 731618 # Total number of references to valid blocks. 1788system.cpu1.l2cache.tags.sampled_refs 62301 # Sample count of references to valid blocks. 1789system.cpu1.l2cache.tags.avg_refs 11.743279 # Average number of references to valid blocks. 1790system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1791system.cpu1.l2cache.tags.occ_blocks::writebacks 8757.920968 # Average occupied blocks per requestor 1792system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.140482 # Average occupied blocks per requestor 1793system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.100736 # Average occupied blocks per requestor 1794system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3269.623984 # Average occupied blocks per requestor 1795system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2111.182929 # Average occupied blocks per requestor 1796system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 939.755359 # Average occupied blocks per requestor 1797system.cpu1.l2cache.tags.occ_percent::writebacks 0.534541 # Average percentage of cache occupancy 1798system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000192 # Average percentage of cache occupancy 1799system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000128 # Average percentage of cache occupancy 1800system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.199562 # Average percentage of cache occupancy 1801system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.128856 # Average percentage of cache occupancy 1802system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.057358 # Average percentage of cache occupancy 1803system.cpu1.l2cache.tags.occ_percent::total 0.920637 # Average percentage of cache occupancy 1804system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1198 # Occupied blocks per task id 1805system.cpu1.l2cache.tags.occ_task_id_blocks::1023 23 # Occupied blocks per task id 1806system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13391 # Occupied blocks per task id 1807system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 29 # Occupied blocks per task id 1808system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1169 # Occupied blocks per task id 1809system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id 1810system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 18 # Occupied blocks per task id 1811system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 282 # Occupied blocks per task id 1812system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1514 # Occupied blocks per task id 1813system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 11595 # Occupied blocks per task id 1814system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.073120 # Percentage of cache occupancy per task id 1815system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001404 # Percentage of cache occupancy per task id 1816system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.817322 # Percentage of cache occupancy per task id 1817system.cpu1.l2cache.tags.tag_accesses 15244499 # Number of tag accesses 1818system.cpu1.l2cache.tags.data_accesses 15244499 # Number of data accesses 1819system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3091 # number of ReadReq hits 1820system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1729 # number of ReadReq hits 1821system.cpu1.l2cache.ReadReq_hits::cpu1.inst 513133 # number of ReadReq hits 1822system.cpu1.l2cache.ReadReq_hits::cpu1.data 102720 # number of ReadReq hits 1823system.cpu1.l2cache.ReadReq_hits::total 620673 # number of ReadReq hits 1824system.cpu1.l2cache.Writeback_hits::writebacks 118649 # number of Writeback hits 1825system.cpu1.l2cache.Writeback_hits::total 118649 # number of Writeback hits 1826system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1485 # number of UpgradeReq hits 1827system.cpu1.l2cache.UpgradeReq_hits::total 1485 # number of UpgradeReq hits 1828system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 867 # number of SCUpgradeReq hits 1829system.cpu1.l2cache.SCUpgradeReq_hits::total 867 # number of SCUpgradeReq hits 1830system.cpu1.l2cache.ReadExReq_hits::cpu1.data 28139 # number of ReadExReq hits 1831system.cpu1.l2cache.ReadExReq_hits::total 28139 # number of ReadExReq hits 1832system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3091 # number of demand (read+write) hits 1833system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1729 # number of demand (read+write) hits 1834system.cpu1.l2cache.demand_hits::cpu1.inst 513133 # number of demand (read+write) hits 1835system.cpu1.l2cache.demand_hits::cpu1.data 130859 # number of demand (read+write) hits 1836system.cpu1.l2cache.demand_hits::total 648812 # number of demand (read+write) hits 1837system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3091 # number of overall hits 1838system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1729 # number of overall hits 1839system.cpu1.l2cache.overall_hits::cpu1.inst 513133 # number of overall hits 1840system.cpu1.l2cache.overall_hits::cpu1.data 130859 # number of overall hits 1841system.cpu1.l2cache.overall_hits::total 648812 # number of overall hits 1842system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 321 # number of ReadReq misses 1843system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 276 # number of ReadReq misses 1844system.cpu1.l2cache.ReadReq_misses::cpu1.inst 14102 # number of ReadReq misses 1845system.cpu1.l2cache.ReadReq_misses::cpu1.data 69212 # number of ReadReq misses 1846system.cpu1.l2cache.ReadReq_misses::total 83911 # number of ReadReq misses 1847system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28339 # number of UpgradeReq misses 1848system.cpu1.l2cache.UpgradeReq_misses::total 28339 # number of UpgradeReq misses 1849system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22509 # number of SCUpgradeReq misses 1850system.cpu1.l2cache.SCUpgradeReq_misses::total 22509 # number of SCUpgradeReq misses 1851system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 3 # number of SCUpgradeFailReq misses 1852system.cpu1.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses 1853system.cpu1.l2cache.ReadExReq_misses::cpu1.data 35184 # number of ReadExReq misses 1854system.cpu1.l2cache.ReadExReq_misses::total 35184 # number of ReadExReq misses 1855system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 321 # number of demand (read+write) misses 1856system.cpu1.l2cache.demand_misses::cpu1.itb.walker 276 # number of demand (read+write) misses 1857system.cpu1.l2cache.demand_misses::cpu1.inst 14102 # number of demand (read+write) misses 1858system.cpu1.l2cache.demand_misses::cpu1.data 104396 # number of demand (read+write) misses 1859system.cpu1.l2cache.demand_misses::total 119095 # number of demand (read+write) misses 1860system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 321 # number of overall misses 1861system.cpu1.l2cache.overall_misses::cpu1.itb.walker 276 # number of overall misses 1862system.cpu1.l2cache.overall_misses::cpu1.inst 14102 # number of overall misses 1863system.cpu1.l2cache.overall_misses::cpu1.data 104396 # number of overall misses 1864system.cpu1.l2cache.overall_misses::total 119095 # number of overall misses 1865system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 6369000 # number of ReadReq miss cycles 1866system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5421000 # number of ReadReq miss cycles 1867system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 483830740 # number of ReadReq miss cycles 1868system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1476489366 # number of ReadReq miss cycles 1869system.cpu1.l2cache.ReadReq_miss_latency::total 1972110106 # number of ReadReq miss cycles 1870system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 522569379 # number of UpgradeReq miss cycles 1871system.cpu1.l2cache.UpgradeReq_miss_latency::total 522569379 # number of UpgradeReq miss cycles 1872system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 435248439 # number of SCUpgradeReq miss cycles 1873system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 435248439 # number of SCUpgradeReq miss cycles 1874system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1586000 # number of SCUpgradeFailReq miss cycles 1875system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1586000 # number of SCUpgradeFailReq miss cycles 1876system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1289152696 # number of ReadExReq miss cycles 1877system.cpu1.l2cache.ReadExReq_miss_latency::total 1289152696 # number of ReadExReq miss cycles 1878system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 6369000 # number of demand (read+write) miss cycles 1879system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5421000 # number of demand (read+write) miss cycles 1880system.cpu1.l2cache.demand_miss_latency::cpu1.inst 483830740 # number of demand (read+write) miss cycles 1881system.cpu1.l2cache.demand_miss_latency::cpu1.data 2765642062 # number of demand (read+write) miss cycles 1882system.cpu1.l2cache.demand_miss_latency::total 3261262802 # number of demand (read+write) miss cycles 1883system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 6369000 # number of overall miss cycles 1884system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5421000 # number of overall miss cycles 1885system.cpu1.l2cache.overall_miss_latency::cpu1.inst 483830740 # number of overall miss cycles 1886system.cpu1.l2cache.overall_miss_latency::cpu1.data 2765642062 # number of overall miss cycles 1887system.cpu1.l2cache.overall_miss_latency::total 3261262802 # number of overall miss cycles 1888system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3412 # number of ReadReq accesses(hits+misses) 1889system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2005 # number of ReadReq accesses(hits+misses) 1890system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 527235 # number of ReadReq accesses(hits+misses) 1891system.cpu1.l2cache.ReadReq_accesses::cpu1.data 171932 # number of ReadReq accesses(hits+misses) 1892system.cpu1.l2cache.ReadReq_accesses::total 704584 # number of ReadReq accesses(hits+misses) 1893system.cpu1.l2cache.Writeback_accesses::writebacks 118649 # number of Writeback accesses(hits+misses) 1894system.cpu1.l2cache.Writeback_accesses::total 118649 # number of Writeback accesses(hits+misses) 1895system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29824 # number of UpgradeReq accesses(hits+misses) 1896system.cpu1.l2cache.UpgradeReq_accesses::total 29824 # number of UpgradeReq accesses(hits+misses) 1897system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23376 # number of SCUpgradeReq accesses(hits+misses) 1898system.cpu1.l2cache.SCUpgradeReq_accesses::total 23376 # number of SCUpgradeReq accesses(hits+misses) 1899system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 3 # number of SCUpgradeFailReq accesses(hits+misses) 1900system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses) 1901system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63323 # number of ReadExReq accesses(hits+misses) 1902system.cpu1.l2cache.ReadExReq_accesses::total 63323 # number of ReadExReq accesses(hits+misses) 1903system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3412 # number of demand (read+write) accesses 1904system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2005 # number of demand (read+write) accesses 1905system.cpu1.l2cache.demand_accesses::cpu1.inst 527235 # number of demand (read+write) accesses 1906system.cpu1.l2cache.demand_accesses::cpu1.data 235255 # number of demand (read+write) accesses 1907system.cpu1.l2cache.demand_accesses::total 767907 # number of demand (read+write) accesses 1908system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3412 # number of overall (read+write) accesses 1909system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2005 # number of overall (read+write) accesses 1910system.cpu1.l2cache.overall_accesses::cpu1.inst 527235 # number of overall (read+write) accesses 1911system.cpu1.l2cache.overall_accesses::cpu1.data 235255 # number of overall (read+write) accesses 1912system.cpu1.l2cache.overall_accesses::total 767907 # number of overall (read+write) accesses 1913system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.094080 # miss rate for ReadReq accesses 1914system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.137656 # miss rate for ReadReq accesses 1915system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.026747 # miss rate for ReadReq accesses 1916system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.402554 # miss rate for ReadReq accesses 1917system.cpu1.l2cache.ReadReq_miss_rate::total 0.119093 # miss rate for ReadReq accesses 1918system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.950208 # miss rate for UpgradeReq accesses 1919system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.950208 # miss rate for UpgradeReq accesses 1920system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.962911 # miss rate for SCUpgradeReq accesses 1921system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.962911 # miss rate for SCUpgradeReq accesses 1922system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 1923system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1924system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.555627 # miss rate for ReadExReq accesses 1925system.cpu1.l2cache.ReadExReq_miss_rate::total 0.555627 # miss rate for ReadExReq accesses 1926system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.094080 # miss rate for demand accesses 1927system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.137656 # miss rate for demand accesses 1928system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026747 # miss rate for demand accesses 1929system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.443757 # miss rate for demand accesses 1930system.cpu1.l2cache.demand_miss_rate::total 0.155090 # miss rate for demand accesses 1931system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.094080 # miss rate for overall accesses 1932system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.137656 # miss rate for overall accesses 1933system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026747 # miss rate for overall accesses 1934system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.443757 # miss rate for overall accesses 1935system.cpu1.l2cache.overall_miss_rate::total 0.155090 # miss rate for overall accesses 1936system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 19841.121495 # average ReadReq miss latency 1937system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19641.304348 # average ReadReq miss latency 1938system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 34309.370302 # average ReadReq miss latency 1939system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 21332.852193 # average ReadReq miss latency 1940system.cpu1.l2cache.ReadReq_avg_miss_latency::total 23502.402617 # average ReadReq miss latency 1941system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18439.937154 # average UpgradeReq miss latency 1942system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18439.937154 # average UpgradeReq miss latency 1943system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19336.640411 # average SCUpgradeReq miss latency 1944system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19336.640411 # average SCUpgradeReq miss latency 1945system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 528666.666667 # average SCUpgradeFailReq miss latency 1946system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 528666.666667 # average SCUpgradeFailReq miss latency 1947system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 36640.310823 # average ReadExReq miss latency 1948system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 36640.310823 # average ReadExReq miss latency 1949system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 19841.121495 # average overall miss latency 1950system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 19641.304348 # average overall miss latency 1951system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 34309.370302 # average overall miss latency 1952system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 26491.839362 # average overall miss latency 1953system.cpu1.l2cache.demand_avg_miss_latency::total 27383.708821 # average overall miss latency 1954system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 19841.121495 # average overall miss latency 1955system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 19641.304348 # average overall miss latency 1956system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 34309.370302 # average overall miss latency 1957system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 26491.839362 # average overall miss latency 1958system.cpu1.l2cache.overall_avg_miss_latency::total 27383.708821 # average overall miss latency 1959system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1960system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1961system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1962system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1963system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1964system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1965system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 1966system.cpu1.l2cache.cache_copies 0 # number of cache copies performed 1967system.cpu1.l2cache.writebacks::writebacks 31472 # number of writebacks 1968system.cpu1.l2cache.writebacks::total 31472 # number of writebacks 1969system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 76 # number of ReadExReq MSHR hits 1970system.cpu1.l2cache.ReadExReq_mshr_hits::total 76 # number of ReadExReq MSHR hits 1971system.cpu1.l2cache.demand_mshr_hits::cpu1.data 76 # number of demand (read+write) MSHR hits 1972system.cpu1.l2cache.demand_mshr_hits::total 76 # number of demand (read+write) MSHR hits 1973system.cpu1.l2cache.overall_mshr_hits::cpu1.data 76 # number of overall MSHR hits 1974system.cpu1.l2cache.overall_mshr_hits::total 76 # number of overall MSHR hits 1975system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 321 # number of ReadReq MSHR misses 1976system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 276 # number of ReadReq MSHR misses 1977system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 14102 # number of ReadReq MSHR misses 1978system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 69212 # number of ReadReq MSHR misses 1979system.cpu1.l2cache.ReadReq_mshr_misses::total 83911 # number of ReadReq MSHR misses 1980system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 24018 # number of HardPFReq MSHR misses 1981system.cpu1.l2cache.HardPFReq_mshr_misses::total 24018 # number of HardPFReq MSHR misses 1982system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 28339 # number of UpgradeReq MSHR misses 1983system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28339 # number of UpgradeReq MSHR misses 1984system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22509 # number of SCUpgradeReq MSHR misses 1985system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22509 # number of SCUpgradeReq MSHR misses 1986system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 3 # number of SCUpgradeFailReq MSHR misses 1987system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses 1988system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 35108 # number of ReadExReq MSHR misses 1989system.cpu1.l2cache.ReadExReq_mshr_misses::total 35108 # number of ReadExReq MSHR misses 1990system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 321 # number of demand (read+write) MSHR misses 1991system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 276 # number of demand (read+write) MSHR misses 1992system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 14102 # number of demand (read+write) MSHR misses 1993system.cpu1.l2cache.demand_mshr_misses::cpu1.data 104320 # number of demand (read+write) MSHR misses 1994system.cpu1.l2cache.demand_mshr_misses::total 119019 # number of demand (read+write) MSHR misses 1995system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 321 # number of overall MSHR misses 1996system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 276 # number of overall MSHR misses 1997system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 14102 # number of overall MSHR misses 1998system.cpu1.l2cache.overall_mshr_misses::cpu1.data 104320 # number of overall MSHR misses 1999system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 24018 # number of overall MSHR misses 2000system.cpu1.l2cache.overall_mshr_misses::total 143037 # number of overall MSHR misses 2001system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4122000 # number of ReadReq MSHR miss cycles 2002system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3489000 # number of ReadReq MSHR miss cycles 2003system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 384250260 # number of ReadReq MSHR miss cycles 2004system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 991800372 # number of ReadReq MSHR miss cycles 2005system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1383661632 # number of ReadReq MSHR miss cycles 2006system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 814752860 # number of HardPFReq MSHR miss cycles 2007system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 814752860 # number of HardPFReq MSHR miss cycles 2008system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 402368047 # number of UpgradeReq MSHR miss cycles 2009system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 402368047 # number of UpgradeReq MSHR miss cycles 2010system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 306023777 # number of SCUpgradeReq MSHR miss cycles 2011system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 306023777 # number of SCUpgradeReq MSHR miss cycles 2012system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1341000 # number of SCUpgradeFailReq MSHR miss cycles 2013system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1341000 # number of SCUpgradeFailReq MSHR miss cycles 2014system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1031661014 # number of ReadExReq MSHR miss cycles 2015system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1031661014 # number of ReadExReq MSHR miss cycles 2016system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 4122000 # number of demand (read+write) MSHR miss cycles 2017system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3489000 # number of demand (read+write) MSHR miss cycles 2018system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 384250260 # number of demand (read+write) MSHR miss cycles 2019system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2023461386 # number of demand (read+write) MSHR miss cycles 2020system.cpu1.l2cache.demand_mshr_miss_latency::total 2415322646 # number of demand (read+write) MSHR miss cycles 2021system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 4122000 # number of overall MSHR miss cycles 2022system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3489000 # number of overall MSHR miss cycles 2023system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 384250260 # number of overall MSHR miss cycles 2024system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2023461386 # number of overall MSHR miss cycles 2025system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 814752860 # number of overall MSHR miss cycles 2026system.cpu1.l2cache.overall_mshr_miss_latency::total 3230075506 # number of overall MSHR miss cycles 2027system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12590000 # number of ReadReq MSHR uncacheable cycles 2028system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 494236499 # number of ReadReq MSHR uncacheable cycles 2029system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 506826499 # number of ReadReq MSHR uncacheable cycles 2030system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 356773500 # number of WriteReq MSHR uncacheable cycles 2031system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 356773500 # number of WriteReq MSHR uncacheable cycles 2032system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 12590000 # number of overall MSHR uncacheable cycles 2033system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 851009999 # number of overall MSHR uncacheable cycles 2034system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 863599999 # number of overall MSHR uncacheable cycles 2035system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.094080 # mshr miss rate for ReadReq accesses 2036system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.137656 # mshr miss rate for ReadReq accesses 2037system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.026747 # mshr miss rate for ReadReq accesses 2038system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.402554 # mshr miss rate for ReadReq accesses 2039system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.119093 # mshr miss rate for ReadReq accesses 2040system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2041system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2042system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.950208 # mshr miss rate for UpgradeReq accesses 2043system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.950208 # mshr miss rate for UpgradeReq accesses 2044system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.962911 # mshr miss rate for SCUpgradeReq accesses 2045system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.962911 # mshr miss rate for SCUpgradeReq accesses 2046system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2047system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 2048system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.554427 # mshr miss rate for ReadExReq accesses 2049system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.554427 # mshr miss rate for ReadExReq accesses 2050system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.094080 # mshr miss rate for demand accesses 2051system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.137656 # mshr miss rate for demand accesses 2052system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.026747 # mshr miss rate for demand accesses 2053system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.443434 # mshr miss rate for demand accesses 2054system.cpu1.l2cache.demand_mshr_miss_rate::total 0.154991 # mshr miss rate for demand accesses 2055system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.094080 # mshr miss rate for overall accesses 2056system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.137656 # mshr miss rate for overall accesses 2057system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.026747 # mshr miss rate for overall accesses 2058system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.443434 # mshr miss rate for overall accesses 2059system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2060system.cpu1.l2cache.overall_mshr_miss_rate::total 0.186269 # mshr miss rate for overall accesses 2061system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 12841.121495 # average ReadReq mshr miss latency 2062system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 12641.304348 # average ReadReq mshr miss latency 2063system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 27247.926535 # average ReadReq mshr miss latency 2064system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 14329.890366 # average ReadReq mshr miss latency 2065system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16489.633445 # average ReadReq mshr miss latency 2066system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33922.593888 # average HardPFReq mshr miss latency 2067system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 33922.593888 # average HardPFReq mshr miss latency 2068system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14198.385511 # average UpgradeReq mshr miss latency 2069system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14198.385511 # average UpgradeReq mshr miss latency 2070system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13595.618508 # average SCUpgradeReq mshr miss latency 2071system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13595.618508 # average SCUpgradeReq mshr miss latency 2072system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 447000 # average SCUpgradeFailReq mshr miss latency 2073system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 447000 # average SCUpgradeFailReq mshr miss latency 2074system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 29385.354164 # average ReadExReq mshr miss latency 2075system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 29385.354164 # average ReadExReq mshr miss latency 2076system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 12841.121495 # average overall mshr miss latency 2077system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 12641.304348 # average overall mshr miss latency 2078system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27247.926535 # average overall mshr miss latency 2079system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 19396.677396 # average overall mshr miss latency 2080system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 20293.588805 # average overall mshr miss latency 2081system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 12841.121495 # average overall mshr miss latency 2082system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 12641.304348 # average overall mshr miss latency 2083system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27247.926535 # average overall mshr miss latency 2084system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 19396.677396 # average overall mshr miss latency 2085system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33922.593888 # average overall mshr miss latency 2086system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 22582.097681 # average overall mshr miss latency 2087system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2088system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2089system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2090system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2091system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2092system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2093system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2094system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2095system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 2096system.cpu1.toL2Bus.trans_dist::ReadReq 1051189 # Transaction distribution 2097system.cpu1.toL2Bus.trans_dist::ReadResp 750269 # Transaction distribution 2098system.cpu1.toL2Bus.trans_dist::WriteReq 3091 # Transaction distribution 2099system.cpu1.toL2Bus.trans_dist::WriteResp 3091 # Transaction distribution 2100system.cpu1.toL2Bus.trans_dist::Writeback 118649 # Transaction distribution 2101system.cpu1.toL2Bus.trans_dist::HardPFReq 33325 # Transaction distribution 2102system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution 2103system.cpu1.toL2Bus.trans_dist::UpgradeReq 74679 # Transaction distribution 2104system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41637 # Transaction distribution 2105system.cpu1.toL2Bus.trans_dist::UpgradeResp 85827 # Transaction distribution 2106system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 49 # Transaction distribution 2107system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 81 # Transaction distribution 2108system.cpu1.toL2Bus.trans_dist::ReadExReq 85544 # Transaction distribution 2109system.cpu1.toL2Bus.trans_dist::ReadExResp 68027 # Transaction distribution 2110system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1054824 # Packet count per connected master and slave (bytes) 2111system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 784590 # Packet count per connected master and slave (bytes) 2112system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5329 # Packet count per connected master and slave (bytes) 2113system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9434 # Packet count per connected master and slave (bytes) 2114system.cpu1.toL2Bus.pkt_count::total 1854177 # Packet count per connected master and slave (bytes) 2115system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 33743748 # Cumulative packet size per connected master and slave (bytes) 2116system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25394480 # Cumulative packet size per connected master and slave (bytes) 2117system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8020 # Cumulative packet size per connected master and slave (bytes) 2118system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 13648 # Cumulative packet size per connected master and slave (bytes) 2119system.cpu1.toL2Bus.pkt_size::total 59159896 # Cumulative packet size per connected master and slave (bytes) 2120system.cpu1.toL2Bus.snoops 572639 # Total snoops (count) 2121system.cpu1.toL2Bus.snoop_fanout::samples 1437265 # Request fanout histogram 2122system.cpu1.toL2Bus.snoop_fanout::mean 5.343414 # Request fanout histogram 2123system.cpu1.toL2Bus.snoop_fanout::stdev 0.474848 # Request fanout histogram 2124system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2125system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 2126system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 2127system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 2128system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 2129system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 2130system.cpu1.toL2Bus.snoop_fanout::5 943688 65.66% 65.66% # Request fanout histogram 2131system.cpu1.toL2Bus.snoop_fanout::6 493577 34.34% 100.00% # Request fanout histogram 2132system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2133system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 2134system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 2135system.cpu1.toL2Bus.snoop_fanout::total 1437265 # Request fanout histogram 2136system.cpu1.toL2Bus.reqLayer0.occupancy 595732734 # Layer occupancy (ticks) 2137system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 2138system.cpu1.toL2Bus.snoopLayer0.occupancy 80038500 # Layer occupancy (ticks) 2139system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2140system.cpu1.toL2Bus.respLayer0.occupancy 791497760 # Layer occupancy (ticks) 2141system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2142system.cpu1.toL2Bus.respLayer1.occupancy 388635637 # Layer occupancy (ticks) 2143system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2144system.cpu1.toL2Bus.respLayer2.occupancy 3324000 # Layer occupancy (ticks) 2145system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2146system.cpu1.toL2Bus.respLayer3.occupancy 6022000 # Layer occupancy (ticks) 2147system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2148system.iobus.trans_dist::ReadReq 31024 # Transaction distribution 2149system.iobus.trans_dist::ReadResp 31024 # Transaction distribution 2150system.iobus.trans_dist::WriteReq 59440 # Transaction distribution 2151system.iobus.trans_dist::WriteResp 23216 # Transaction distribution 2152system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 2153system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes) 2154system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 2155system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 2156system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 2157system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 2158system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 2159system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 2160system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2161system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2162system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2163system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 2164system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 2165system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 2166system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 2167system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 2168system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 2169system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 2170system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 2171system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 2172system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 2173system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 2174system.iobus.pkt_count_system.bridge.master::total 107970 # Packet count per connected master and slave (bytes) 2175system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes) 2176system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes) 2177system.iobus.pkt_count::total 180928 # Packet count per connected master and slave (bytes) 2178system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71600 # Cumulative packet size per connected master and slave (bytes) 2179system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 2180system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 2181system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 2182system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 2183system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 2184system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 2185system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2186system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2187system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2188system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 2189system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2190system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2191system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 2192system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 2193system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2194system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 2195system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 2196system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 2197system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 2198system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 2199system.iobus.pkt_size_system.bridge.master::total 162850 # Cumulative packet size per connected master and slave (bytes) 2200system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes) 2201system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes) 2202system.iobus.pkt_size::total 2484122 # Cumulative packet size per connected master and slave (bytes) 2203system.iobus.reqLayer0.occupancy 40136000 # Layer occupancy (ticks) 2204system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2205system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) 2206system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2207system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) 2208system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2209system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) 2210system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2211system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) 2212system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 2213system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) 2214system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 2215system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) 2216system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2217system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 2218system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2219system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 2220system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2221system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 2222system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 2223system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) 2224system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2225system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 2226system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 2227system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) 2228system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 2229system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) 2230system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 2231system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) 2232system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 2233system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 2234system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 2235system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) 2236system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2237system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) 2238system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2239system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) 2240system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2241system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) 2242system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 2243system.iobus.reqLayer27.occupancy 347109131 # Layer occupancy (ticks) 2244system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 2245system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 2246system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 2247system.iobus.respLayer0.occupancy 84754000 # Layer occupancy (ticks) 2248system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2249system.iobus.respLayer3.occupancy 36846525 # Layer occupancy (ticks) 2250system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2251system.iocache.tags.replacements 36445 # number of replacements 2252system.iocache.tags.tagsinuse 14.387294 # Cycle average of tags in use 2253system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 2254system.iocache.tags.sampled_refs 36461 # Sample count of references to valid blocks. 2255system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 2256system.iocache.tags.warmup_cycle 287959539000 # Cycle when the warmup percentage was hit. 2257system.iocache.tags.occ_blocks::realview.ide 14.387294 # Average occupied blocks per requestor 2258system.iocache.tags.occ_percent::realview.ide 0.899206 # Average percentage of cache occupancy 2259system.iocache.tags.occ_percent::total 0.899206 # Average percentage of cache occupancy 2260system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2261system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2262system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2263system.iocache.tags.tag_accesses 328311 # Number of tag accesses 2264system.iocache.tags.data_accesses 328311 # Number of data accesses 2265system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses 2266system.iocache.ReadReq_misses::total 255 # number of ReadReq misses 2267system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses 2268system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses 2269system.iocache.demand_misses::realview.ide 255 # number of demand (read+write) misses 2270system.iocache.demand_misses::total 255 # number of demand (read+write) misses 2271system.iocache.overall_misses::realview.ide 255 # number of overall misses 2272system.iocache.overall_misses::total 255 # number of overall misses 2273system.iocache.ReadReq_miss_latency::realview.ide 31782377 # number of ReadReq miss cycles 2274system.iocache.ReadReq_miss_latency::total 31782377 # number of ReadReq miss cycles 2275system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9599974229 # number of WriteInvalidateReq miss cycles 2276system.iocache.WriteInvalidateReq_miss_latency::total 9599974229 # number of WriteInvalidateReq miss cycles 2277system.iocache.demand_miss_latency::realview.ide 31782377 # number of demand (read+write) miss cycles 2278system.iocache.demand_miss_latency::total 31782377 # number of demand (read+write) miss cycles 2279system.iocache.overall_miss_latency::realview.ide 31782377 # number of overall miss cycles 2280system.iocache.overall_miss_latency::total 31782377 # number of overall miss cycles 2281system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) 2282system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) 2283system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) 2284system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) 2285system.iocache.demand_accesses::realview.ide 255 # number of demand (read+write) accesses 2286system.iocache.demand_accesses::total 255 # number of demand (read+write) accesses 2287system.iocache.overall_accesses::realview.ide 255 # number of overall (read+write) accesses 2288system.iocache.overall_accesses::total 255 # number of overall (read+write) accesses 2289system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2290system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2291system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses 2292system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 2293system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2294system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2295system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2296system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2297system.iocache.ReadReq_avg_miss_latency::realview.ide 124636.772549 # average ReadReq miss latency 2298system.iocache.ReadReq_avg_miss_latency::total 124636.772549 # average ReadReq miss latency 2299system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265016.956410 # average WriteInvalidateReq miss latency 2300system.iocache.WriteInvalidateReq_avg_miss_latency::total 265016.956410 # average WriteInvalidateReq miss latency 2301system.iocache.demand_avg_miss_latency::realview.ide 124636.772549 # average overall miss latency 2302system.iocache.demand_avg_miss_latency::total 124636.772549 # average overall miss latency 2303system.iocache.overall_avg_miss_latency::realview.ide 124636.772549 # average overall miss latency 2304system.iocache.overall_avg_miss_latency::total 124636.772549 # average overall miss latency 2305system.iocache.blocked_cycles::no_mshrs 55555 # number of cycles access was blocked 2306system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2307system.iocache.blocked::no_mshrs 7160 # number of cycles access was blocked 2308system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2309system.iocache.avg_blocked_cycles::no_mshrs 7.759078 # average number of cycles each access was blocked 2310system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2311system.iocache.fast_writes 0 # number of fast writes performed 2312system.iocache.cache_copies 0 # number of cache copies performed 2313system.iocache.writebacks::writebacks 36190 # number of writebacks 2314system.iocache.writebacks::total 36190 # number of writebacks 2315system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses 2316system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses 2317system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses 2318system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses 2319system.iocache.demand_mshr_misses::realview.ide 255 # number of demand (read+write) MSHR misses 2320system.iocache.demand_mshr_misses::total 255 # number of demand (read+write) MSHR misses 2321system.iocache.overall_mshr_misses::realview.ide 255 # number of overall MSHR misses 2322system.iocache.overall_mshr_misses::total 255 # number of overall MSHR misses 2323system.iocache.ReadReq_mshr_miss_latency::realview.ide 18521377 # number of ReadReq MSHR miss cycles 2324system.iocache.ReadReq_mshr_miss_latency::total 18521377 # number of ReadReq MSHR miss cycles 2325system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7716276279 # number of WriteInvalidateReq MSHR miss cycles 2326system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7716276279 # number of WriteInvalidateReq MSHR miss cycles 2327system.iocache.demand_mshr_miss_latency::realview.ide 18521377 # number of demand (read+write) MSHR miss cycles 2328system.iocache.demand_mshr_miss_latency::total 18521377 # number of demand (read+write) MSHR miss cycles 2329system.iocache.overall_mshr_miss_latency::realview.ide 18521377 # number of overall MSHR miss cycles 2330system.iocache.overall_mshr_miss_latency::total 18521377 # number of overall MSHR miss cycles 2331system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2332system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2333system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses 2334system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 2335system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2336system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2337system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2338system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 2339system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72632.850980 # average ReadReq mshr miss latency 2340system.iocache.ReadReq_avg_mshr_miss_latency::total 72632.850980 # average ReadReq mshr miss latency 2341system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213015.577490 # average WriteInvalidateReq mshr miss latency 2342system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213015.577490 # average WriteInvalidateReq mshr miss latency 2343system.iocache.demand_avg_mshr_miss_latency::realview.ide 72632.850980 # average overall mshr miss latency 2344system.iocache.demand_avg_mshr_miss_latency::total 72632.850980 # average overall mshr miss latency 2345system.iocache.overall_avg_mshr_miss_latency::realview.ide 72632.850980 # average overall mshr miss latency 2346system.iocache.overall_avg_mshr_miss_latency::total 72632.850980 # average overall mshr miss latency 2347system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2348system.l2c.tags.replacements 130735 # number of replacements 2349system.l2c.tags.tagsinuse 63966.604731 # Cycle average of tags in use 2350system.l2c.tags.total_refs 343053 # Total number of references to valid blocks. 2351system.l2c.tags.sampled_refs 195063 # Sample count of references to valid blocks. 2352system.l2c.tags.avg_refs 1.758678 # Average number of references to valid blocks. 2353system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2354system.l2c.tags.occ_blocks::writebacks 12083.139597 # Average occupied blocks per requestor 2355system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.938906 # Average occupied blocks per requestor 2356system.l2c.tags.occ_blocks::cpu0.itb.walker 1.007553 # Average occupied blocks per requestor 2357system.l2c.tags.occ_blocks::cpu0.inst 6678.027236 # Average occupied blocks per requestor 2358system.l2c.tags.occ_blocks::cpu0.data 2760.487108 # Average occupied blocks per requestor 2359system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 38360.306045 # Average occupied blocks per requestor 2360system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.955640 # Average occupied blocks per requestor 2361system.l2c.tags.occ_blocks::cpu1.inst 1552.248405 # Average occupied blocks per requestor 2362system.l2c.tags.occ_blocks::cpu1.data 535.801693 # Average occupied blocks per requestor 2363system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1990.692549 # Average occupied blocks per requestor 2364system.l2c.tags.occ_percent::writebacks 0.184374 # Average percentage of cache occupancy 2365system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000060 # Average percentage of cache occupancy 2366system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy 2367system.l2c.tags.occ_percent::cpu0.inst 0.101899 # Average percentage of cache occupancy 2368system.l2c.tags.occ_percent::cpu0.data 0.042122 # Average percentage of cache occupancy 2369system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.585332 # Average percentage of cache occupancy 2370system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy 2371system.l2c.tags.occ_percent::cpu1.inst 0.023685 # Average percentage of cache occupancy 2372system.l2c.tags.occ_percent::cpu1.data 0.008176 # Average percentage of cache occupancy 2373system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.030376 # Average percentage of cache occupancy 2374system.l2c.tags.occ_percent::total 0.976053 # Average percentage of cache occupancy 2375system.l2c.tags.occ_task_id_blocks::1022 32989 # Occupied blocks per task id 2376system.l2c.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id 2377system.l2c.tags.occ_task_id_blocks::1024 31331 # Occupied blocks per task id 2378system.l2c.tags.age_task_id_blocks_1022::2 170 # Occupied blocks per task id 2379system.l2c.tags.age_task_id_blocks_1022::3 4524 # Occupied blocks per task id 2380system.l2c.tags.age_task_id_blocks_1022::4 28295 # Occupied blocks per task id 2381system.l2c.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id 2382system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id 2383system.l2c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id 2384system.l2c.tags.age_task_id_blocks_1024::2 254 # Occupied blocks per task id 2385system.l2c.tags.age_task_id_blocks_1024::3 1895 # Occupied blocks per task id 2386system.l2c.tags.age_task_id_blocks_1024::4 29170 # Occupied blocks per task id 2387system.l2c.tags.occ_task_id_percent::1022 0.503372 # Percentage of cache occupancy per task id 2388system.l2c.tags.occ_task_id_percent::1023 0.000122 # Percentage of cache occupancy per task id 2389system.l2c.tags.occ_task_id_percent::1024 0.478073 # Percentage of cache occupancy per task id 2390system.l2c.tags.tag_accesses 4931105 # Number of tag accesses 2391system.l2c.tags.data_accesses 4931105 # Number of data accesses 2392system.l2c.ReadReq_hits::cpu0.dtb.walker 82 # number of ReadReq hits 2393system.l2c.ReadReq_hits::cpu0.itb.walker 63 # number of ReadReq hits 2394system.l2c.ReadReq_hits::cpu0.inst 29372 # number of ReadReq hits 2395system.l2c.ReadReq_hits::cpu0.data 45566 # number of ReadReq hits 2396system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 45492 # number of ReadReq hits 2397system.l2c.ReadReq_hits::cpu1.dtb.walker 34 # number of ReadReq hits 2398system.l2c.ReadReq_hits::cpu1.itb.walker 41 # number of ReadReq hits 2399system.l2c.ReadReq_hits::cpu1.inst 11667 # number of ReadReq hits 2400system.l2c.ReadReq_hits::cpu1.data 8537 # number of ReadReq hits 2401system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 5785 # number of ReadReq hits 2402system.l2c.ReadReq_hits::total 146639 # number of ReadReq hits 2403system.l2c.Writeback_hits::writebacks 227719 # number of Writeback hits 2404system.l2c.Writeback_hits::total 227719 # number of Writeback hits 2405system.l2c.UpgradeReq_hits::cpu0.data 2362 # number of UpgradeReq hits 2406system.l2c.UpgradeReq_hits::cpu1.data 770 # number of UpgradeReq hits 2407system.l2c.UpgradeReq_hits::total 3132 # number of UpgradeReq hits 2408system.l2c.SCUpgradeReq_hits::cpu0.data 164 # number of SCUpgradeReq hits 2409system.l2c.SCUpgradeReq_hits::cpu1.data 164 # number of SCUpgradeReq hits 2410system.l2c.SCUpgradeReq_hits::total 328 # number of SCUpgradeReq hits 2411system.l2c.ReadExReq_hits::cpu0.data 3862 # number of ReadExReq hits 2412system.l2c.ReadExReq_hits::cpu1.data 1497 # number of ReadExReq hits 2413system.l2c.ReadExReq_hits::total 5359 # number of ReadExReq hits 2414system.l2c.demand_hits::cpu0.dtb.walker 82 # number of demand (read+write) hits 2415system.l2c.demand_hits::cpu0.itb.walker 63 # number of demand (read+write) hits 2416system.l2c.demand_hits::cpu0.inst 29372 # number of demand (read+write) hits 2417system.l2c.demand_hits::cpu0.data 49428 # number of demand (read+write) hits 2418system.l2c.demand_hits::cpu0.l2cache.prefetcher 45492 # number of demand (read+write) hits 2419system.l2c.demand_hits::cpu1.dtb.walker 34 # number of demand (read+write) hits 2420system.l2c.demand_hits::cpu1.itb.walker 41 # number of demand (read+write) hits 2421system.l2c.demand_hits::cpu1.inst 11667 # number of demand (read+write) hits 2422system.l2c.demand_hits::cpu1.data 10034 # number of demand (read+write) hits 2423system.l2c.demand_hits::cpu1.l2cache.prefetcher 5785 # number of demand (read+write) hits 2424system.l2c.demand_hits::total 151998 # number of demand (read+write) hits 2425system.l2c.overall_hits::cpu0.dtb.walker 82 # number of overall hits 2426system.l2c.overall_hits::cpu0.itb.walker 63 # number of overall hits 2427system.l2c.overall_hits::cpu0.inst 29372 # number of overall hits 2428system.l2c.overall_hits::cpu0.data 49428 # number of overall hits 2429system.l2c.overall_hits::cpu0.l2cache.prefetcher 45492 # number of overall hits 2430system.l2c.overall_hits::cpu1.dtb.walker 34 # number of overall hits 2431system.l2c.overall_hits::cpu1.itb.walker 41 # number of overall hits 2432system.l2c.overall_hits::cpu1.inst 11667 # number of overall hits 2433system.l2c.overall_hits::cpu1.data 10034 # number of overall hits 2434system.l2c.overall_hits::cpu1.l2cache.prefetcher 5785 # number of overall hits 2435system.l2c.overall_hits::total 151998 # number of overall hits 2436system.l2c.ReadReq_misses::cpu0.dtb.walker 7 # number of ReadReq misses 2437system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses 2438system.l2c.ReadReq_misses::cpu0.inst 17779 # number of ReadReq misses 2439system.l2c.ReadReq_misses::cpu0.data 8894 # number of ReadReq misses 2440system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 134996 # number of ReadReq misses 2441system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses 2442system.l2c.ReadReq_misses::cpu1.inst 2435 # number of ReadReq misses 2443system.l2c.ReadReq_misses::cpu1.data 924 # number of ReadReq misses 2444system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 5907 # number of ReadReq misses 2445system.l2c.ReadReq_misses::total 170945 # number of ReadReq misses 2446system.l2c.UpgradeReq_misses::cpu0.data 8889 # number of UpgradeReq misses 2447system.l2c.UpgradeReq_misses::cpu1.data 2898 # number of UpgradeReq misses 2448system.l2c.UpgradeReq_misses::total 11787 # number of UpgradeReq misses 2449system.l2c.SCUpgradeReq_misses::cpu0.data 758 # number of SCUpgradeReq misses 2450system.l2c.SCUpgradeReq_misses::cpu1.data 1209 # number of SCUpgradeReq misses 2451system.l2c.SCUpgradeReq_misses::total 1967 # number of SCUpgradeReq misses 2452system.l2c.ReadExReq_misses::cpu0.data 11387 # number of ReadExReq misses 2453system.l2c.ReadExReq_misses::cpu1.data 8562 # number of ReadExReq misses 2454system.l2c.ReadExReq_misses::total 19949 # number of ReadExReq misses 2455system.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses 2456system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses 2457system.l2c.demand_misses::cpu0.inst 17779 # number of demand (read+write) misses 2458system.l2c.demand_misses::cpu0.data 20281 # number of demand (read+write) misses 2459system.l2c.demand_misses::cpu0.l2cache.prefetcher 134996 # number of demand (read+write) misses 2460system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses 2461system.l2c.demand_misses::cpu1.inst 2435 # number of demand (read+write) misses 2462system.l2c.demand_misses::cpu1.data 9486 # number of demand (read+write) misses 2463system.l2c.demand_misses::cpu1.l2cache.prefetcher 5907 # number of demand (read+write) misses 2464system.l2c.demand_misses::total 190894 # number of demand (read+write) misses 2465system.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses 2466system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses 2467system.l2c.overall_misses::cpu0.inst 17779 # number of overall misses 2468system.l2c.overall_misses::cpu0.data 20281 # number of overall misses 2469system.l2c.overall_misses::cpu0.l2cache.prefetcher 134996 # number of overall misses 2470system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses 2471system.l2c.overall_misses::cpu1.inst 2435 # number of overall misses 2472system.l2c.overall_misses::cpu1.data 9486 # number of overall misses 2473system.l2c.overall_misses::cpu1.l2cache.prefetcher 5907 # number of overall misses 2474system.l2c.overall_misses::total 190894 # number of overall misses 2475system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 494750 # number of ReadReq miss cycles 2476system.l2c.ReadReq_miss_latency::cpu0.itb.walker 149500 # number of ReadReq miss cycles 2477system.l2c.ReadReq_miss_latency::cpu0.inst 1299838245 # number of ReadReq miss cycles 2478system.l2c.ReadReq_miss_latency::cpu0.data 708631748 # number of ReadReq miss cycles 2479system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 13069199153 # number of ReadReq miss cycles 2480system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 75000 # number of ReadReq miss cycles 2481system.l2c.ReadReq_miss_latency::cpu1.inst 182647247 # number of ReadReq miss cycles 2482system.l2c.ReadReq_miss_latency::cpu1.data 78676500 # number of ReadReq miss cycles 2483system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 680911899 # number of ReadReq miss cycles 2484system.l2c.ReadReq_miss_latency::total 16020624042 # number of ReadReq miss cycles 2485system.l2c.UpgradeReq_miss_latency::cpu0.data 5423319 # number of UpgradeReq miss cycles 2486system.l2c.UpgradeReq_miss_latency::cpu1.data 2108409 # number of UpgradeReq miss cycles 2487system.l2c.UpgradeReq_miss_latency::total 7531728 # number of UpgradeReq miss cycles 2488system.l2c.SCUpgradeReq_miss_latency::cpu0.data 679977 # number of SCUpgradeReq miss cycles 2489system.l2c.SCUpgradeReq_miss_latency::cpu1.data 605974 # number of SCUpgradeReq miss cycles 2490system.l2c.SCUpgradeReq_miss_latency::total 1285951 # number of SCUpgradeReq miss cycles 2491system.l2c.ReadExReq_miss_latency::cpu0.data 888864663 # number of ReadExReq miss cycles 2492system.l2c.ReadExReq_miss_latency::cpu1.data 627516972 # number of ReadExReq miss cycles 2493system.l2c.ReadExReq_miss_latency::total 1516381635 # number of ReadExReq miss cycles 2494system.l2c.demand_miss_latency::cpu0.dtb.walker 494750 # number of demand (read+write) miss cycles 2495system.l2c.demand_miss_latency::cpu0.itb.walker 149500 # number of demand (read+write) miss cycles 2496system.l2c.demand_miss_latency::cpu0.inst 1299838245 # number of demand (read+write) miss cycles 2497system.l2c.demand_miss_latency::cpu0.data 1597496411 # number of demand (read+write) miss cycles 2498system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 13069199153 # number of demand (read+write) miss cycles 2499system.l2c.demand_miss_latency::cpu1.dtb.walker 75000 # number of demand (read+write) miss cycles 2500system.l2c.demand_miss_latency::cpu1.inst 182647247 # number of demand (read+write) miss cycles 2501system.l2c.demand_miss_latency::cpu1.data 706193472 # number of demand (read+write) miss cycles 2502system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 680911899 # number of demand (read+write) miss cycles 2503system.l2c.demand_miss_latency::total 17537005677 # number of demand (read+write) miss cycles 2504system.l2c.overall_miss_latency::cpu0.dtb.walker 494750 # number of overall miss cycles 2505system.l2c.overall_miss_latency::cpu0.itb.walker 149500 # number of overall miss cycles 2506system.l2c.overall_miss_latency::cpu0.inst 1299838245 # number of overall miss cycles 2507system.l2c.overall_miss_latency::cpu0.data 1597496411 # number of overall miss cycles 2508system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 13069199153 # number of overall miss cycles 2509system.l2c.overall_miss_latency::cpu1.dtb.walker 75000 # number of overall miss cycles 2510system.l2c.overall_miss_latency::cpu1.inst 182647247 # number of overall miss cycles 2511system.l2c.overall_miss_latency::cpu1.data 706193472 # number of overall miss cycles 2512system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 680911899 # number of overall miss cycles 2513system.l2c.overall_miss_latency::total 17537005677 # number of overall miss cycles 2514system.l2c.ReadReq_accesses::cpu0.dtb.walker 89 # number of ReadReq accesses(hits+misses) 2515system.l2c.ReadReq_accesses::cpu0.itb.walker 65 # number of ReadReq accesses(hits+misses) 2516system.l2c.ReadReq_accesses::cpu0.inst 47151 # number of ReadReq accesses(hits+misses) 2517system.l2c.ReadReq_accesses::cpu0.data 54460 # number of ReadReq accesses(hits+misses) 2518system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 180488 # number of ReadReq accesses(hits+misses) 2519system.l2c.ReadReq_accesses::cpu1.dtb.walker 35 # number of ReadReq accesses(hits+misses) 2520system.l2c.ReadReq_accesses::cpu1.itb.walker 41 # number of ReadReq accesses(hits+misses) 2521system.l2c.ReadReq_accesses::cpu1.inst 14102 # number of ReadReq accesses(hits+misses) 2522system.l2c.ReadReq_accesses::cpu1.data 9461 # number of ReadReq accesses(hits+misses) 2523system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 11692 # number of ReadReq accesses(hits+misses) 2524system.l2c.ReadReq_accesses::total 317584 # number of ReadReq accesses(hits+misses) 2525system.l2c.Writeback_accesses::writebacks 227719 # number of Writeback accesses(hits+misses) 2526system.l2c.Writeback_accesses::total 227719 # number of Writeback accesses(hits+misses) 2527system.l2c.UpgradeReq_accesses::cpu0.data 11251 # number of UpgradeReq accesses(hits+misses) 2528system.l2c.UpgradeReq_accesses::cpu1.data 3668 # number of UpgradeReq accesses(hits+misses) 2529system.l2c.UpgradeReq_accesses::total 14919 # number of UpgradeReq accesses(hits+misses) 2530system.l2c.SCUpgradeReq_accesses::cpu0.data 922 # number of SCUpgradeReq accesses(hits+misses) 2531system.l2c.SCUpgradeReq_accesses::cpu1.data 1373 # number of SCUpgradeReq accesses(hits+misses) 2532system.l2c.SCUpgradeReq_accesses::total 2295 # number of SCUpgradeReq accesses(hits+misses) 2533system.l2c.ReadExReq_accesses::cpu0.data 15249 # number of ReadExReq accesses(hits+misses) 2534system.l2c.ReadExReq_accesses::cpu1.data 10059 # number of ReadExReq accesses(hits+misses) 2535system.l2c.ReadExReq_accesses::total 25308 # number of ReadExReq accesses(hits+misses) 2536system.l2c.demand_accesses::cpu0.dtb.walker 89 # number of demand (read+write) accesses 2537system.l2c.demand_accesses::cpu0.itb.walker 65 # number of demand (read+write) accesses 2538system.l2c.demand_accesses::cpu0.inst 47151 # number of demand (read+write) accesses 2539system.l2c.demand_accesses::cpu0.data 69709 # number of demand (read+write) accesses 2540system.l2c.demand_accesses::cpu0.l2cache.prefetcher 180488 # number of demand (read+write) accesses 2541system.l2c.demand_accesses::cpu1.dtb.walker 35 # number of demand (read+write) accesses 2542system.l2c.demand_accesses::cpu1.itb.walker 41 # number of demand (read+write) accesses 2543system.l2c.demand_accesses::cpu1.inst 14102 # number of demand (read+write) accesses 2544system.l2c.demand_accesses::cpu1.data 19520 # number of demand (read+write) accesses 2545system.l2c.demand_accesses::cpu1.l2cache.prefetcher 11692 # number of demand (read+write) accesses 2546system.l2c.demand_accesses::total 342892 # number of demand (read+write) accesses 2547system.l2c.overall_accesses::cpu0.dtb.walker 89 # number of overall (read+write) accesses 2548system.l2c.overall_accesses::cpu0.itb.walker 65 # number of overall (read+write) accesses 2549system.l2c.overall_accesses::cpu0.inst 47151 # number of overall (read+write) accesses 2550system.l2c.overall_accesses::cpu0.data 69709 # number of overall (read+write) accesses 2551system.l2c.overall_accesses::cpu0.l2cache.prefetcher 180488 # number of overall (read+write) accesses 2552system.l2c.overall_accesses::cpu1.dtb.walker 35 # number of overall (read+write) accesses 2553system.l2c.overall_accesses::cpu1.itb.walker 41 # number of overall (read+write) accesses 2554system.l2c.overall_accesses::cpu1.inst 14102 # number of overall (read+write) accesses 2555system.l2c.overall_accesses::cpu1.data 19520 # number of overall (read+write) accesses 2556system.l2c.overall_accesses::cpu1.l2cache.prefetcher 11692 # number of overall (read+write) accesses 2557system.l2c.overall_accesses::total 342892 # number of overall (read+write) accesses 2558system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.078652 # miss rate for ReadReq accesses 2559system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.030769 # miss rate for ReadReq accesses 2560system.l2c.ReadReq_miss_rate::cpu0.inst 0.377065 # miss rate for ReadReq accesses 2561system.l2c.ReadReq_miss_rate::cpu0.data 0.163313 # miss rate for ReadReq accesses 2562system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.747950 # miss rate for ReadReq accesses 2563system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.028571 # miss rate for ReadReq accesses 2564system.l2c.ReadReq_miss_rate::cpu1.inst 0.172671 # miss rate for ReadReq accesses 2565system.l2c.ReadReq_miss_rate::cpu1.data 0.097664 # miss rate for ReadReq accesses 2566system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.505217 # miss rate for ReadReq accesses 2567system.l2c.ReadReq_miss_rate::total 0.538267 # miss rate for ReadReq accesses 2568system.l2c.UpgradeReq_miss_rate::cpu0.data 0.790063 # miss rate for UpgradeReq accesses 2569system.l2c.UpgradeReq_miss_rate::cpu1.data 0.790076 # miss rate for UpgradeReq accesses 2570system.l2c.UpgradeReq_miss_rate::total 0.790066 # miss rate for UpgradeReq accesses 2571system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.822126 # miss rate for SCUpgradeReq accesses 2572system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.880554 # miss rate for SCUpgradeReq accesses 2573system.l2c.SCUpgradeReq_miss_rate::total 0.857081 # miss rate for SCUpgradeReq accesses 2574system.l2c.ReadExReq_miss_rate::cpu0.data 0.746737 # miss rate for ReadExReq accesses 2575system.l2c.ReadExReq_miss_rate::cpu1.data 0.851178 # miss rate for ReadExReq accesses 2576system.l2c.ReadExReq_miss_rate::total 0.788249 # miss rate for ReadExReq accesses 2577system.l2c.demand_miss_rate::cpu0.dtb.walker 0.078652 # miss rate for demand accesses 2578system.l2c.demand_miss_rate::cpu0.itb.walker 0.030769 # miss rate for demand accesses 2579system.l2c.demand_miss_rate::cpu0.inst 0.377065 # miss rate for demand accesses 2580system.l2c.demand_miss_rate::cpu0.data 0.290938 # miss rate for demand accesses 2581system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.747950 # miss rate for demand accesses 2582system.l2c.demand_miss_rate::cpu1.dtb.walker 0.028571 # miss rate for demand accesses 2583system.l2c.demand_miss_rate::cpu1.inst 0.172671 # miss rate for demand accesses 2584system.l2c.demand_miss_rate::cpu1.data 0.485963 # miss rate for demand accesses 2585system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.505217 # miss rate for demand accesses 2586system.l2c.demand_miss_rate::total 0.556718 # miss rate for demand accesses 2587system.l2c.overall_miss_rate::cpu0.dtb.walker 0.078652 # miss rate for overall accesses 2588system.l2c.overall_miss_rate::cpu0.itb.walker 0.030769 # miss rate for overall accesses 2589system.l2c.overall_miss_rate::cpu0.inst 0.377065 # miss rate for overall accesses 2590system.l2c.overall_miss_rate::cpu0.data 0.290938 # miss rate for overall accesses 2591system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.747950 # miss rate for overall accesses 2592system.l2c.overall_miss_rate::cpu1.dtb.walker 0.028571 # miss rate for overall accesses 2593system.l2c.overall_miss_rate::cpu1.inst 0.172671 # miss rate for overall accesses 2594system.l2c.overall_miss_rate::cpu1.data 0.485963 # miss rate for overall accesses 2595system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.505217 # miss rate for overall accesses 2596system.l2c.overall_miss_rate::total 0.556718 # miss rate for overall accesses 2597system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 70678.571429 # average ReadReq miss latency 2598system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 74750 # average ReadReq miss latency 2599system.l2c.ReadReq_avg_miss_latency::cpu0.inst 73110.874909 # average ReadReq miss latency 2600system.l2c.ReadReq_avg_miss_latency::cpu0.data 79675.258376 # average ReadReq miss latency 2601system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 96811.751111 # average ReadReq miss latency 2602system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 75000 # average ReadReq miss latency 2603system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75009.136345 # average ReadReq miss latency 2604system.l2c.ReadReq_avg_miss_latency::cpu1.data 85147.727273 # average ReadReq miss latency 2605system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 115272.033012 # average ReadReq miss latency 2606system.l2c.ReadReq_avg_miss_latency::total 93718.003112 # average ReadReq miss latency 2607system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 610.115761 # average UpgradeReq miss latency 2608system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 727.539337 # average UpgradeReq miss latency 2609system.l2c.UpgradeReq_avg_miss_latency::total 638.986002 # average UpgradeReq miss latency 2610system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 897.067282 # average SCUpgradeReq miss latency 2611system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 501.219189 # average SCUpgradeReq miss latency 2612system.l2c.SCUpgradeReq_avg_miss_latency::total 653.762583 # average SCUpgradeReq miss latency 2613system.l2c.ReadExReq_avg_miss_latency::cpu0.data 78059.599807 # average ReadExReq miss latency 2614system.l2c.ReadExReq_avg_miss_latency::cpu1.data 73290.933427 # average ReadExReq miss latency 2615system.l2c.ReadExReq_avg_miss_latency::total 76012.914682 # average ReadExReq miss latency 2616system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 70678.571429 # average overall miss latency 2617system.l2c.demand_avg_miss_latency::cpu0.itb.walker 74750 # average overall miss latency 2618system.l2c.demand_avg_miss_latency::cpu0.inst 73110.874909 # average overall miss latency 2619system.l2c.demand_avg_miss_latency::cpu0.data 78768.128347 # average overall miss latency 2620system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 96811.751111 # average overall miss latency 2621system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 75000 # average overall miss latency 2622system.l2c.demand_avg_miss_latency::cpu1.inst 75009.136345 # average overall miss latency 2623system.l2c.demand_avg_miss_latency::cpu1.data 74445.864643 # average overall miss latency 2624system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 115272.033012 # average overall miss latency 2625system.l2c.demand_avg_miss_latency::total 91867.767855 # average overall miss latency 2626system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 70678.571429 # average overall miss latency 2627system.l2c.overall_avg_miss_latency::cpu0.itb.walker 74750 # average overall miss latency 2628system.l2c.overall_avg_miss_latency::cpu0.inst 73110.874909 # average overall miss latency 2629system.l2c.overall_avg_miss_latency::cpu0.data 78768.128347 # average overall miss latency 2630system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 96811.751111 # average overall miss latency 2631system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 75000 # average overall miss latency 2632system.l2c.overall_avg_miss_latency::cpu1.inst 75009.136345 # average overall miss latency 2633system.l2c.overall_avg_miss_latency::cpu1.data 74445.864643 # average overall miss latency 2634system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 115272.033012 # average overall miss latency 2635system.l2c.overall_avg_miss_latency::total 91867.767855 # average overall miss latency 2636system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2637system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2638system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 2639system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2640system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2641system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2642system.l2c.fast_writes 0 # number of fast writes performed 2643system.l2c.cache_copies 0 # number of cache copies performed 2644system.l2c.writebacks::writebacks 99035 # number of writebacks 2645system.l2c.writebacks::total 99035 # number of writebacks 2646system.l2c.ReadReq_mshr_hits::cpu1.inst 3 # number of ReadReq MSHR hits 2647system.l2c.ReadReq_mshr_hits::cpu1.data 1 # number of ReadReq MSHR hits 2648system.l2c.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits 2649system.l2c.demand_mshr_hits::cpu1.inst 3 # number of demand (read+write) MSHR hits 2650system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits 2651system.l2c.demand_mshr_hits::total 4 # number of demand (read+write) MSHR hits 2652system.l2c.overall_mshr_hits::cpu1.inst 3 # number of overall MSHR hits 2653system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits 2654system.l2c.overall_mshr_hits::total 4 # number of overall MSHR hits 2655system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 7 # number of ReadReq MSHR misses 2656system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses 2657system.l2c.ReadReq_mshr_misses::cpu0.inst 17779 # number of ReadReq MSHR misses 2658system.l2c.ReadReq_mshr_misses::cpu0.data 8894 # number of ReadReq MSHR misses 2659system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 134996 # number of ReadReq MSHR misses 2660system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadReq MSHR misses 2661system.l2c.ReadReq_mshr_misses::cpu1.inst 2432 # number of ReadReq MSHR misses 2662system.l2c.ReadReq_mshr_misses::cpu1.data 923 # number of ReadReq MSHR misses 2663system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 5907 # number of ReadReq MSHR misses 2664system.l2c.ReadReq_mshr_misses::total 170941 # number of ReadReq MSHR misses 2665system.l2c.UpgradeReq_mshr_misses::cpu0.data 8889 # number of UpgradeReq MSHR misses 2666system.l2c.UpgradeReq_mshr_misses::cpu1.data 2898 # number of UpgradeReq MSHR misses 2667system.l2c.UpgradeReq_mshr_misses::total 11787 # number of UpgradeReq MSHR misses 2668system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 758 # number of SCUpgradeReq MSHR misses 2669system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1209 # number of SCUpgradeReq MSHR misses 2670system.l2c.SCUpgradeReq_mshr_misses::total 1967 # number of SCUpgradeReq MSHR misses 2671system.l2c.ReadExReq_mshr_misses::cpu0.data 11387 # number of ReadExReq MSHR misses 2672system.l2c.ReadExReq_mshr_misses::cpu1.data 8562 # number of ReadExReq MSHR misses 2673system.l2c.ReadExReq_mshr_misses::total 19949 # number of ReadExReq MSHR misses 2674system.l2c.demand_mshr_misses::cpu0.dtb.walker 7 # number of demand (read+write) MSHR misses 2675system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses 2676system.l2c.demand_mshr_misses::cpu0.inst 17779 # number of demand (read+write) MSHR misses 2677system.l2c.demand_mshr_misses::cpu0.data 20281 # number of demand (read+write) MSHR misses 2678system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 134996 # number of demand (read+write) MSHR misses 2679system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses 2680system.l2c.demand_mshr_misses::cpu1.inst 2432 # number of demand (read+write) MSHR misses 2681system.l2c.demand_mshr_misses::cpu1.data 9485 # number of demand (read+write) MSHR misses 2682system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 5907 # number of demand (read+write) MSHR misses 2683system.l2c.demand_mshr_misses::total 190890 # number of demand (read+write) MSHR misses 2684system.l2c.overall_mshr_misses::cpu0.dtb.walker 7 # number of overall MSHR misses 2685system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses 2686system.l2c.overall_mshr_misses::cpu0.inst 17779 # number of overall MSHR misses 2687system.l2c.overall_mshr_misses::cpu0.data 20281 # number of overall MSHR misses 2688system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 134996 # number of overall MSHR misses 2689system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses 2690system.l2c.overall_mshr_misses::cpu1.inst 2432 # number of overall MSHR misses 2691system.l2c.overall_mshr_misses::cpu1.data 9485 # number of overall MSHR misses 2692system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 5907 # number of overall MSHR misses 2693system.l2c.overall_mshr_misses::total 190890 # number of overall MSHR misses 2694system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 408750 # number of ReadReq MSHR miss cycles 2695system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 125000 # number of ReadReq MSHR miss cycles 2696system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 1075716745 # number of ReadReq MSHR miss cycles 2697system.l2c.ReadReq_mshr_miss_latency::cpu0.data 597785248 # number of ReadReq MSHR miss cycles 2698system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 11388842153 # number of ReadReq MSHR miss cycles 2699system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 62500 # number of ReadReq MSHR miss cycles 2700system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 151904497 # number of ReadReq MSHR miss cycles 2701system.l2c.ReadReq_mshr_miss_latency::cpu1.data 67178000 # number of ReadReq MSHR miss cycles 2702system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 608475899 # number of ReadReq MSHR miss cycles 2703system.l2c.ReadReq_mshr_miss_latency::total 13890498792 # number of ReadReq MSHR miss cycles 2704system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 90106352 # number of UpgradeReq MSHR miss cycles 2705system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 29086385 # number of UpgradeReq MSHR miss cycles 2706system.l2c.UpgradeReq_mshr_miss_latency::total 119192737 # number of UpgradeReq MSHR miss cycles 2707system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 7710755 # number of SCUpgradeReq MSHR miss cycles 2708system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 12095707 # number of SCUpgradeReq MSHR miss cycles 2709system.l2c.SCUpgradeReq_mshr_miss_latency::total 19806462 # number of SCUpgradeReq MSHR miss cycles 2710system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 746306335 # number of ReadExReq MSHR miss cycles 2711system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 519227026 # number of ReadExReq MSHR miss cycles 2712system.l2c.ReadExReq_mshr_miss_latency::total 1265533361 # number of ReadExReq MSHR miss cycles 2713system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 408750 # number of demand (read+write) MSHR miss cycles 2714system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 125000 # number of demand (read+write) MSHR miss cycles 2715system.l2c.demand_mshr_miss_latency::cpu0.inst 1075716745 # number of demand (read+write) MSHR miss cycles 2716system.l2c.demand_mshr_miss_latency::cpu0.data 1344091583 # number of demand (read+write) MSHR miss cycles 2717system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 11388842153 # number of demand (read+write) MSHR miss cycles 2718system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 62500 # number of demand (read+write) MSHR miss cycles 2719system.l2c.demand_mshr_miss_latency::cpu1.inst 151904497 # number of demand (read+write) MSHR miss cycles 2720system.l2c.demand_mshr_miss_latency::cpu1.data 586405026 # number of demand (read+write) MSHR miss cycles 2721system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 608475899 # number of demand (read+write) MSHR miss cycles 2722system.l2c.demand_mshr_miss_latency::total 15156032153 # number of demand (read+write) MSHR miss cycles 2723system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 408750 # number of overall MSHR miss cycles 2724system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 125000 # number of overall MSHR miss cycles 2725system.l2c.overall_mshr_miss_latency::cpu0.inst 1075716745 # number of overall MSHR miss cycles 2726system.l2c.overall_mshr_miss_latency::cpu0.data 1344091583 # number of overall MSHR miss cycles 2727system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 11388842153 # number of overall MSHR miss cycles 2728system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 62500 # number of overall MSHR miss cycles 2729system.l2c.overall_mshr_miss_latency::cpu1.inst 151904497 # number of overall MSHR miss cycles 2730system.l2c.overall_mshr_miss_latency::cpu1.data 586405026 # number of overall MSHR miss cycles 2731system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 608475899 # number of overall MSHR miss cycles 2732system.l2c.overall_mshr_miss_latency::total 15156032153 # number of overall MSHR miss cycles 2733system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 476665000 # number of ReadReq MSHR uncacheable cycles 2734system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5183212748 # number of ReadReq MSHR uncacheable cycles 2735system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 9260500 # number of ReadReq MSHR uncacheable cycles 2736system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 424539000 # number of ReadReq MSHR uncacheable cycles 2737system.l2c.ReadReq_mshr_uncacheable_latency::total 6093677248 # number of ReadReq MSHR uncacheable cycles 2738system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 3944737000 # number of WriteReq MSHR uncacheable cycles 2739system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 304049000 # number of WriteReq MSHR uncacheable cycles 2740system.l2c.WriteReq_mshr_uncacheable_latency::total 4248786000 # number of WriteReq MSHR uncacheable cycles 2741system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 476665000 # number of overall MSHR uncacheable cycles 2742system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9127949748 # number of overall MSHR uncacheable cycles 2743system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 9260500 # number of overall MSHR uncacheable cycles 2744system.l2c.overall_mshr_uncacheable_latency::cpu1.data 728588000 # number of overall MSHR uncacheable cycles 2745system.l2c.overall_mshr_uncacheable_latency::total 10342463248 # number of overall MSHR uncacheable cycles 2746system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.078652 # mshr miss rate for ReadReq accesses 2747system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.030769 # mshr miss rate for ReadReq accesses 2748system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.377065 # mshr miss rate for ReadReq accesses 2749system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.163313 # mshr miss rate for ReadReq accesses 2750system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.747950 # mshr miss rate for ReadReq accesses 2751system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.028571 # mshr miss rate for ReadReq accesses 2752system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.172458 # mshr miss rate for ReadReq accesses 2753system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.097558 # mshr miss rate for ReadReq accesses 2754system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.505217 # mshr miss rate for ReadReq accesses 2755system.l2c.ReadReq_mshr_miss_rate::total 0.538254 # mshr miss rate for ReadReq accesses 2756system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.790063 # mshr miss rate for UpgradeReq accesses 2757system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.790076 # mshr miss rate for UpgradeReq accesses 2758system.l2c.UpgradeReq_mshr_miss_rate::total 0.790066 # mshr miss rate for UpgradeReq accesses 2759system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.822126 # mshr miss rate for SCUpgradeReq accesses 2760system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.880554 # mshr miss rate for SCUpgradeReq accesses 2761system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.857081 # mshr miss rate for SCUpgradeReq accesses 2762system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.746737 # mshr miss rate for ReadExReq accesses 2763system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.851178 # mshr miss rate for ReadExReq accesses 2764system.l2c.ReadExReq_mshr_miss_rate::total 0.788249 # mshr miss rate for ReadExReq accesses 2765system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.078652 # mshr miss rate for demand accesses 2766system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.030769 # mshr miss rate for demand accesses 2767system.l2c.demand_mshr_miss_rate::cpu0.inst 0.377065 # mshr miss rate for demand accesses 2768system.l2c.demand_mshr_miss_rate::cpu0.data 0.290938 # mshr miss rate for demand accesses 2769system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.747950 # mshr miss rate for demand accesses 2770system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.028571 # mshr miss rate for demand accesses 2771system.l2c.demand_mshr_miss_rate::cpu1.inst 0.172458 # mshr miss rate for demand accesses 2772system.l2c.demand_mshr_miss_rate::cpu1.data 0.485912 # mshr miss rate for demand accesses 2773system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.505217 # mshr miss rate for demand accesses 2774system.l2c.demand_mshr_miss_rate::total 0.556706 # mshr miss rate for demand accesses 2775system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.078652 # mshr miss rate for overall accesses 2776system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.030769 # mshr miss rate for overall accesses 2777system.l2c.overall_mshr_miss_rate::cpu0.inst 0.377065 # mshr miss rate for overall accesses 2778system.l2c.overall_mshr_miss_rate::cpu0.data 0.290938 # mshr miss rate for overall accesses 2779system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.747950 # mshr miss rate for overall accesses 2780system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.028571 # mshr miss rate for overall accesses 2781system.l2c.overall_mshr_miss_rate::cpu1.inst 0.172458 # mshr miss rate for overall accesses 2782system.l2c.overall_mshr_miss_rate::cpu1.data 0.485912 # mshr miss rate for overall accesses 2783system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.505217 # mshr miss rate for overall accesses 2784system.l2c.overall_mshr_miss_rate::total 0.556706 # mshr miss rate for overall accesses 2785system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 58392.857143 # average ReadReq mshr miss latency 2786system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency 2787system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60504.907194 # average ReadReq mshr miss latency 2788system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 67212.193389 # average ReadReq mshr miss latency 2789system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 84364.293409 # average ReadReq mshr miss latency 2790system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average ReadReq mshr miss latency 2791system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62460.730674 # average ReadReq mshr miss latency 2792system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 72782.231853 # average ReadReq mshr miss latency 2793system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 103009.293889 # average ReadReq mshr miss latency 2794system.l2c.ReadReq_avg_mshr_miss_latency::total 81259.023827 # average ReadReq mshr miss latency 2795system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10136.837890 # average UpgradeReq mshr miss latency 2796system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10036.709800 # average UpgradeReq mshr miss latency 2797system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10112.219988 # average UpgradeReq mshr miss latency 2798system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10172.500000 # average SCUpgradeReq mshr miss latency 2799system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10004.720430 # average SCUpgradeReq mshr miss latency 2800system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10069.375699 # average SCUpgradeReq mshr miss latency 2801system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 65540.206815 # average ReadExReq mshr miss latency 2802system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 60643.193880 # average ReadExReq mshr miss latency 2803system.l2c.ReadExReq_avg_mshr_miss_latency::total 63438.436062 # average ReadExReq mshr miss latency 2804system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 58392.857143 # average overall mshr miss latency 2805system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency 2806system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60504.907194 # average overall mshr miss latency 2807system.l2c.demand_avg_mshr_miss_latency::cpu0.data 66273.437355 # average overall mshr miss latency 2808system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 84364.293409 # average overall mshr miss latency 2809system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency 2810system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62460.730674 # average overall mshr miss latency 2811system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61824.462414 # average overall mshr miss latency 2812system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 103009.293889 # average overall mshr miss latency 2813system.l2c.demand_avg_mshr_miss_latency::total 79396.679517 # average overall mshr miss latency 2814system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 58392.857143 # average overall mshr miss latency 2815system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency 2816system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60504.907194 # average overall mshr miss latency 2817system.l2c.overall_avg_mshr_miss_latency::cpu0.data 66273.437355 # average overall mshr miss latency 2818system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 84364.293409 # average overall mshr miss latency 2819system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency 2820system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62460.730674 # average overall mshr miss latency 2821system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61824.462414 # average overall mshr miss latency 2822system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 103009.293889 # average overall mshr miss latency 2823system.l2c.overall_avg_mshr_miss_latency::total 79396.679517 # average overall mshr miss latency 2824system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 2825system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 2826system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2827system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2828system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2829system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 2830system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2831system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2832system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 2833system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 2834system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2835system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2836system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2837system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 2838system.membus.trans_dist::ReadReq 215303 # Transaction distribution 2839system.membus.trans_dist::ReadResp 215303 # Transaction distribution 2840system.membus.trans_dist::WriteReq 30982 # Transaction distribution 2841system.membus.trans_dist::WriteResp 30982 # Transaction distribution 2842system.membus.trans_dist::Writeback 135225 # Transaction distribution 2843system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 2844system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 2845system.membus.trans_dist::UpgradeReq 76008 # Transaction distribution 2846system.membus.trans_dist::SCUpgradeReq 40410 # Transaction distribution 2847system.membus.trans_dist::UpgradeResp 13867 # Transaction distribution 2848system.membus.trans_dist::SCUpgradeFailReq 5 # Transaction distribution 2849system.membus.trans_dist::ReadExReq 40350 # Transaction distribution 2850system.membus.trans_dist::ReadExResp 19836 # Transaction distribution 2851system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107970 # Packet count per connected master and slave (bytes) 2852system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) 2853system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13762 # Packet count per connected master and slave (bytes) 2854system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 659440 # Packet count per connected master and slave (bytes) 2855system.membus.pkt_count_system.l2c.mem_side::total 781206 # Packet count per connected master and slave (bytes) 2856system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108908 # Packet count per connected master and slave (bytes) 2857system.membus.pkt_count_system.iocache.mem_side::total 108908 # Packet count per connected master and slave (bytes) 2858system.membus.pkt_count::total 890114 # Packet count per connected master and slave (bytes) 2859system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162850 # Cumulative packet size per connected master and slave (bytes) 2860system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) 2861system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27524 # Cumulative packet size per connected master and slave (bytes) 2862system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18582632 # Cumulative packet size per connected master and slave (bytes) 2863system.membus.pkt_size_system.l2c.mem_side::total 18773074 # Cumulative packet size per connected master and slave (bytes) 2864system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) 2865system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) 2866system.membus.pkt_size::total 23408530 # Cumulative packet size per connected master and slave (bytes) 2867system.membus.snoops 123675 # Total snoops (count) 2868system.membus.snoop_fanout::samples 499419 # Request fanout histogram 2869system.membus.snoop_fanout::mean 1 # Request fanout histogram 2870system.membus.snoop_fanout::stdev 0 # Request fanout histogram 2871system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2872system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 2873system.membus.snoop_fanout::1 499419 100.00% 100.00% # Request fanout histogram 2874system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 2875system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2876system.membus.snoop_fanout::min_value 1 # Request fanout histogram 2877system.membus.snoop_fanout::max_value 1 # Request fanout histogram 2878system.membus.snoop_fanout::total 499419 # Request fanout histogram 2879system.membus.reqLayer0.occupancy 88165000 # Layer occupancy (ticks) 2880system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 2881system.membus.reqLayer1.occupancy 18500 # Layer occupancy (ticks) 2882system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 2883system.membus.reqLayer2.occupancy 11453500 # Layer occupancy (ticks) 2884system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 2885system.membus.reqLayer5.occupancy 1828859499 # Layer occupancy (ticks) 2886system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) 2887system.membus.respLayer2.occupancy 1931425684 # Layer occupancy (ticks) 2888system.membus.respLayer2.utilization 0.1 # Layer utilization (%) 2889system.membus.respLayer3.occupancy 38544475 # Layer occupancy (ticks) 2890system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 2891system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 2892system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 2893system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 2894system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 2895system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 2896system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 2897system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 2898system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 2899system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 2900system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 2901system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 2902system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 2903system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 2904system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 2905system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 2906system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 2907system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 2908system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 2909system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 2910system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 2911system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 2912system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 2913system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 2914system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 2915system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 2916system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 2917system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 2918system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 2919system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 2920system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 2921system.realview.ethernet.droppedPackets 0 # number of packets dropped 2922system.toL2Bus.trans_dist::ReadReq 482729 # Transaction distribution 2923system.toL2Bus.trans_dist::ReadResp 482714 # Transaction distribution 2924system.toL2Bus.trans_dist::WriteReq 30982 # Transaction distribution 2925system.toL2Bus.trans_dist::WriteResp 30982 # Transaction distribution 2926system.toL2Bus.trans_dist::Writeback 227719 # Transaction distribution 2927system.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution 2928system.toL2Bus.trans_dist::UpgradeReq 79027 # Transaction distribution 2929system.toL2Bus.trans_dist::SCUpgradeReq 40738 # Transaction distribution 2930system.toL2Bus.trans_dist::UpgradeResp 119765 # Transaction distribution 2931system.toL2Bus.trans_dist::SCUpgradeFailReq 81 # Transaction distribution 2932system.toL2Bus.trans_dist::UpgradeFailResp 81 # Transaction distribution 2933system.toL2Bus.trans_dist::ReadExReq 51496 # Transaction distribution 2934system.toL2Bus.trans_dist::ReadExResp 51496 # Transaction distribution 2935system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1065854 # Packet count per connected master and slave (bytes) 2936system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 282098 # Packet count per connected master and slave (bytes) 2937system.toL2Bus.pkt_count::total 1347952 # Packet count per connected master and slave (bytes) 2938system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 31837086 # Cumulative packet size per connected master and slave (bytes) 2939system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4944756 # Cumulative packet size per connected master and slave (bytes) 2940system.toL2Bus.pkt_size::total 36781842 # Cumulative packet size per connected master and slave (bytes) 2941system.toL2Bus.snoops 286323 # Total snoops (count) 2942system.toL2Bus.snoop_fanout::samples 873908 # Request fanout histogram 2943system.toL2Bus.snoop_fanout::mean 1.041744 # Request fanout histogram 2944system.toL2Bus.snoop_fanout::stdev 0.200003 # Request fanout histogram 2945system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2946system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 2947system.toL2Bus.snoop_fanout::1 837428 95.83% 95.83% # Request fanout histogram 2948system.toL2Bus.snoop_fanout::2 36480 4.17% 100.00% # Request fanout histogram 2949system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2950system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 2951system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2952system.toL2Bus.snoop_fanout::total 873908 # Request fanout histogram 2953system.toL2Bus.reqLayer0.occupancy 1446151615 # Layer occupancy (ticks) 2954system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 2955system.toL2Bus.snoopLayer0.occupancy 1080000 # Layer occupancy (ticks) 2956system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2957system.toL2Bus.respLayer0.occupancy 1735034184 # Layer occupancy (ticks) 2958system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 2959system.toL2Bus.respLayer1.occupancy 618323353 # Layer occupancy (ticks) 2960system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2961 2962---------- End Simulation Statistics ---------- 2963