stats.txt revision 8528
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.669611 # Number of seconds simulated 4sim_ticks 2669611225000 # Number of ticks simulated 5sim_freq 1000000000000 # Frequency of simulated ticks 6host_inst_rate 491804 # Simulator instruction rate (inst/s) 7host_tick_rate 16743499108 # Simulator tick rate (ticks/s) 8host_mem_usage 418920 # Number of bytes of host memory used 9host_seconds 159.44 # Real time elapsed on the host 10sim_insts 78413959 # Number of instructions simulated 11system.l2c.replacements 127749 # number of replacements 12system.l2c.tagsinuse 26172.513439 # Cycle average of tags in use 13system.l2c.total_refs 1540412 # Total number of references to valid blocks. 14system.l2c.sampled_refs 157158 # Sample count of references to valid blocks. 15system.l2c.avg_refs 9.801677 # Average number of references to valid blocks. 16system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 17system.l2c.occ_blocks::0 6351.465954 # Average occupied blocks per context 18system.l2c.occ_blocks::1 4614.904109 # Average occupied blocks per context 19system.l2c.occ_blocks::2 15206.143377 # Average occupied blocks per context 20system.l2c.occ_percent::0 0.096916 # Average percentage of cache occupancy 21system.l2c.occ_percent::1 0.070418 # Average percentage of cache occupancy 22system.l2c.occ_percent::2 0.232027 # Average percentage of cache occupancy 23system.l2c.ReadReq_hits::0 562859 # number of ReadReq hits 24system.l2c.ReadReq_hits::1 656143 # number of ReadReq hits 25system.l2c.ReadReq_hits::2 11798 # number of ReadReq hits 26system.l2c.ReadReq_hits::total 1230800 # number of ReadReq hits 27system.l2c.Writeback_hits::0 589400 # number of Writeback hits 28system.l2c.Writeback_hits::total 589400 # number of Writeback hits 29system.l2c.UpgradeReq_hits::0 1143 # number of UpgradeReq hits 30system.l2c.UpgradeReq_hits::1 692 # number of UpgradeReq hits 31system.l2c.UpgradeReq_hits::total 1835 # number of UpgradeReq hits 32system.l2c.SCUpgradeReq_hits::0 168 # number of SCUpgradeReq hits 33system.l2c.SCUpgradeReq_hits::1 186 # number of SCUpgradeReq hits 34system.l2c.SCUpgradeReq_hits::total 354 # number of SCUpgradeReq hits 35system.l2c.ReadExReq_hits::0 42506 # number of ReadExReq hits 36system.l2c.ReadExReq_hits::1 58554 # number of ReadExReq hits 37system.l2c.ReadExReq_hits::total 101060 # number of ReadExReq hits 38system.l2c.demand_hits::0 605365 # number of demand (read+write) hits 39system.l2c.demand_hits::1 714697 # number of demand (read+write) hits 40system.l2c.demand_hits::2 11798 # number of demand (read+write) hits 41system.l2c.demand_hits::total 1331860 # number of demand (read+write) hits 42system.l2c.overall_hits::0 605365 # number of overall hits 43system.l2c.overall_hits::1 714697 # number of overall hits 44system.l2c.overall_hits::2 11798 # number of overall hits 45system.l2c.overall_hits::total 1331860 # number of overall hits 46system.l2c.ReadReq_misses::0 18655 # number of ReadReq misses 47system.l2c.ReadReq_misses::1 16034 # number of ReadReq misses 48system.l2c.ReadReq_misses::2 50 # number of ReadReq misses 49system.l2c.ReadReq_misses::total 34739 # number of ReadReq misses 50system.l2c.UpgradeReq_misses::0 3515 # number of UpgradeReq misses 51system.l2c.UpgradeReq_misses::1 5223 # number of UpgradeReq misses 52system.l2c.UpgradeReq_misses::total 8738 # number of UpgradeReq misses 53system.l2c.SCUpgradeReq_misses::0 546 # number of SCUpgradeReq misses 54system.l2c.SCUpgradeReq_misses::1 614 # number of SCUpgradeReq misses 55system.l2c.SCUpgradeReq_misses::total 1160 # number of SCUpgradeReq misses 56system.l2c.ReadExReq_misses::0 97324 # number of ReadExReq misses 57system.l2c.ReadExReq_misses::1 51524 # number of ReadExReq misses 58system.l2c.ReadExReq_misses::total 148848 # number of ReadExReq misses 59system.l2c.demand_misses::0 115979 # number of demand (read+write) misses 60system.l2c.demand_misses::1 67558 # number of demand (read+write) misses 61system.l2c.demand_misses::2 50 # number of demand (read+write) misses 62system.l2c.demand_misses::total 183587 # number of demand (read+write) misses 63system.l2c.overall_misses::0 115979 # number of overall misses 64system.l2c.overall_misses::1 67558 # number of overall misses 65system.l2c.overall_misses::2 50 # number of overall misses 66system.l2c.overall_misses::total 183587 # number of overall misses 67system.l2c.ReadReq_miss_latency 1812504500 # number of ReadReq miss cycles 68system.l2c.UpgradeReq_miss_latency 56471000 # number of UpgradeReq miss cycles 69system.l2c.SCUpgradeReq_miss_latency 6300000 # number of SCUpgradeReq miss cycles 70system.l2c.ReadExReq_miss_latency 7751543000 # number of ReadExReq miss cycles 71system.l2c.demand_miss_latency 9564047500 # number of demand (read+write) miss cycles 72system.l2c.overall_miss_latency 9564047500 # number of overall miss cycles 73system.l2c.ReadReq_accesses::0 581514 # number of ReadReq accesses(hits+misses) 74system.l2c.ReadReq_accesses::1 672177 # number of ReadReq accesses(hits+misses) 75system.l2c.ReadReq_accesses::2 11848 # number of ReadReq accesses(hits+misses) 76system.l2c.ReadReq_accesses::total 1265539 # number of ReadReq accesses(hits+misses) 77system.l2c.Writeback_accesses::0 589400 # number of Writeback accesses(hits+misses) 78system.l2c.Writeback_accesses::total 589400 # number of Writeback accesses(hits+misses) 79system.l2c.UpgradeReq_accesses::0 4658 # number of UpgradeReq accesses(hits+misses) 80system.l2c.UpgradeReq_accesses::1 5915 # number of UpgradeReq accesses(hits+misses) 81system.l2c.UpgradeReq_accesses::total 10573 # number of UpgradeReq accesses(hits+misses) 82system.l2c.SCUpgradeReq_accesses::0 714 # number of SCUpgradeReq accesses(hits+misses) 83system.l2c.SCUpgradeReq_accesses::1 800 # number of SCUpgradeReq accesses(hits+misses) 84system.l2c.SCUpgradeReq_accesses::total 1514 # number of SCUpgradeReq accesses(hits+misses) 85system.l2c.ReadExReq_accesses::0 139830 # number of ReadExReq accesses(hits+misses) 86system.l2c.ReadExReq_accesses::1 110078 # number of ReadExReq accesses(hits+misses) 87system.l2c.ReadExReq_accesses::total 249908 # number of ReadExReq accesses(hits+misses) 88system.l2c.demand_accesses::0 721344 # number of demand (read+write) accesses 89system.l2c.demand_accesses::1 782255 # number of demand (read+write) accesses 90system.l2c.demand_accesses::2 11848 # number of demand (read+write) accesses 91system.l2c.demand_accesses::total 1515447 # number of demand (read+write) accesses 92system.l2c.overall_accesses::0 721344 # number of overall (read+write) accesses 93system.l2c.overall_accesses::1 782255 # number of overall (read+write) accesses 94system.l2c.overall_accesses::2 11848 # number of overall (read+write) accesses 95system.l2c.overall_accesses::total 1515447 # number of overall (read+write) accesses 96system.l2c.ReadReq_miss_rate::0 0.032080 # miss rate for ReadReq accesses 97system.l2c.ReadReq_miss_rate::1 0.023854 # miss rate for ReadReq accesses 98system.l2c.ReadReq_miss_rate::2 0.004220 # miss rate for ReadReq accesses 99system.l2c.ReadReq_miss_rate::total 0.060154 # miss rate for ReadReq accesses 100system.l2c.UpgradeReq_miss_rate::0 0.754616 # miss rate for UpgradeReq accesses 101system.l2c.UpgradeReq_miss_rate::1 0.883009 # miss rate for UpgradeReq accesses 102system.l2c.SCUpgradeReq_miss_rate::0 0.764706 # miss rate for SCUpgradeReq accesses 103system.l2c.SCUpgradeReq_miss_rate::1 0.767500 # miss rate for SCUpgradeReq accesses 104system.l2c.ReadExReq_miss_rate::0 0.696017 # miss rate for ReadExReq accesses 105system.l2c.ReadExReq_miss_rate::1 0.468068 # miss rate for ReadExReq accesses 106system.l2c.demand_miss_rate::0 0.160782 # miss rate for demand accesses 107system.l2c.demand_miss_rate::1 0.086363 # miss rate for demand accesses 108system.l2c.demand_miss_rate::2 0.004220 # miss rate for demand accesses 109system.l2c.demand_miss_rate::total 0.251365 # miss rate for demand accesses 110system.l2c.overall_miss_rate::0 0.160782 # miss rate for overall accesses 111system.l2c.overall_miss_rate::1 0.086363 # miss rate for overall accesses 112system.l2c.overall_miss_rate::2 0.004220 # miss rate for overall accesses 113system.l2c.overall_miss_rate::total 0.251365 # miss rate for overall accesses 114system.l2c.ReadReq_avg_miss_latency::0 97159.179845 # average ReadReq miss latency 115system.l2c.ReadReq_avg_miss_latency::1 113041.318448 # average ReadReq miss latency 116system.l2c.ReadReq_avg_miss_latency::2 36250090 # average ReadReq miss latency 117system.l2c.ReadReq_avg_miss_latency::total 36460290.498293 # average ReadReq miss latency 118system.l2c.UpgradeReq_avg_miss_latency::0 16065.718350 # average UpgradeReq miss latency 119system.l2c.UpgradeReq_avg_miss_latency::1 10811.985449 # average UpgradeReq miss latency 120system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency 121system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency 122system.l2c.SCUpgradeReq_avg_miss_latency::0 11538.461538 # average SCUpgradeReq miss latency 123system.l2c.SCUpgradeReq_avg_miss_latency::1 10260.586319 # average SCUpgradeReq miss latency 124system.l2c.SCUpgradeReq_avg_miss_latency::2 inf # average SCUpgradeReq miss latency 125system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency 126system.l2c.ReadExReq_avg_miss_latency::0 79646.777773 # average ReadExReq miss latency 127system.l2c.ReadExReq_avg_miss_latency::1 150445.287633 # average ReadExReq miss latency 128system.l2c.ReadExReq_avg_miss_latency::2 inf # average ReadExReq miss latency 129system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency 130system.l2c.demand_avg_miss_latency::0 82463.614103 # average overall miss latency 131system.l2c.demand_avg_miss_latency::1 141567.949022 # average overall miss latency 132system.l2c.demand_avg_miss_latency::2 191280950 # average overall miss latency 133system.l2c.demand_avg_miss_latency::total 191504981.563124 # average overall miss latency 134system.l2c.overall_avg_miss_latency::0 82463.614103 # average overall miss latency 135system.l2c.overall_avg_miss_latency::1 141567.949022 # average overall miss latency 136system.l2c.overall_avg_miss_latency::2 191280950 # average overall miss latency 137system.l2c.overall_avg_miss_latency::total 191504981.563124 # average overall miss latency 138system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 139system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 140system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 141system.l2c.blocked::no_targets 0 # number of cycles access was blocked 142system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 143system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 144system.l2c.fast_writes 0 # number of fast writes performed 145system.l2c.cache_copies 0 # number of cache copies performed 146system.l2c.writebacks 111955 # number of writebacks 147system.l2c.ReadReq_mshr_hits 9 # number of ReadReq MSHR hits 148system.l2c.demand_mshr_hits 9 # number of demand (read+write) MSHR hits 149system.l2c.overall_mshr_hits 9 # number of overall MSHR hits 150system.l2c.ReadReq_mshr_misses 34730 # number of ReadReq MSHR misses 151system.l2c.UpgradeReq_mshr_misses 8738 # number of UpgradeReq MSHR misses 152system.l2c.SCUpgradeReq_mshr_misses 1160 # number of SCUpgradeReq MSHR misses 153system.l2c.ReadExReq_mshr_misses 148848 # number of ReadExReq MSHR misses 154system.l2c.demand_mshr_misses 183578 # number of demand (read+write) MSHR misses 155system.l2c.overall_mshr_misses 183578 # number of overall MSHR misses 156system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 157system.l2c.ReadReq_mshr_miss_latency 1395310000 # number of ReadReq MSHR miss cycles 158system.l2c.UpgradeReq_mshr_miss_latency 350593500 # number of UpgradeReq MSHR miss cycles 159system.l2c.SCUpgradeReq_mshr_miss_latency 46546000 # number of SCUpgradeReq MSHR miss cycles 160system.l2c.ReadExReq_mshr_miss_latency 5965367000 # number of ReadExReq MSHR miss cycles 161system.l2c.demand_mshr_miss_latency 7360677000 # number of demand (read+write) MSHR miss cycles 162system.l2c.overall_mshr_miss_latency 7360677000 # number of overall MSHR miss cycles 163system.l2c.ReadReq_mshr_uncacheable_latency 131926671000 # number of ReadReq MSHR uncacheable cycles 164system.l2c.WriteReq_mshr_uncacheable_latency 31372379500 # number of WriteReq MSHR uncacheable cycles 165system.l2c.overall_mshr_uncacheable_latency 163299050500 # number of overall MSHR uncacheable cycles 166system.l2c.ReadReq_mshr_miss_rate::0 0.059723 # mshr miss rate for ReadReq accesses 167system.l2c.ReadReq_mshr_miss_rate::1 0.051668 # mshr miss rate for ReadReq accesses 168system.l2c.ReadReq_mshr_miss_rate::2 2.931296 # mshr miss rate for ReadReq accesses 169system.l2c.ReadReq_mshr_miss_rate::total 3.042688 # mshr miss rate for ReadReq accesses 170system.l2c.UpgradeReq_mshr_miss_rate::0 1.875912 # mshr miss rate for UpgradeReq accesses 171system.l2c.UpgradeReq_mshr_miss_rate::1 1.477261 # mshr miss rate for UpgradeReq accesses 172system.l2c.UpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for UpgradeReq accesses 173system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses 174system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.624650 # mshr miss rate for SCUpgradeReq accesses 175system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.450000 # mshr miss rate for SCUpgradeReq accesses 176system.l2c.SCUpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for SCUpgradeReq accesses 177system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses 178system.l2c.ReadExReq_mshr_miss_rate::0 1.064493 # mshr miss rate for ReadExReq accesses 179system.l2c.ReadExReq_mshr_miss_rate::1 1.352205 # mshr miss rate for ReadExReq accesses 180system.l2c.ReadExReq_mshr_miss_rate::2 inf # mshr miss rate for ReadExReq accesses 181system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses 182system.l2c.demand_mshr_miss_rate::0 0.254494 # mshr miss rate for demand accesses 183system.l2c.demand_mshr_miss_rate::1 0.234678 # mshr miss rate for demand accesses 184system.l2c.demand_mshr_miss_rate::2 15.494429 # mshr miss rate for demand accesses 185system.l2c.demand_mshr_miss_rate::total 15.983602 # mshr miss rate for demand accesses 186system.l2c.overall_mshr_miss_rate::0 0.254494 # mshr miss rate for overall accesses 187system.l2c.overall_mshr_miss_rate::1 0.234678 # mshr miss rate for overall accesses 188system.l2c.overall_mshr_miss_rate::2 15.494429 # mshr miss rate for overall accesses 189system.l2c.overall_mshr_miss_rate::total 15.983602 # mshr miss rate for overall accesses 190system.l2c.ReadReq_avg_mshr_miss_latency 40175.928592 # average ReadReq mshr miss latency 191system.l2c.UpgradeReq_avg_mshr_miss_latency 40122.854200 # average UpgradeReq mshr miss latency 192system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40125.862069 # average SCUpgradeReq mshr miss latency 193system.l2c.ReadExReq_avg_mshr_miss_latency 40076.903956 # average ReadExReq mshr miss latency 194system.l2c.demand_avg_mshr_miss_latency 40095.637822 # average overall mshr miss latency 195system.l2c.overall_avg_mshr_miss_latency 40095.637822 # average overall mshr miss latency 196system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency 197system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency 198system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency 199system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated 200system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 201system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 202system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 203system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 204system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 205system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 206system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 207system.cf0.dma_write_txs 0 # Number of DMA write transactions. 208system.cpu0.dtb.inst_hits 0 # ITB inst hits 209system.cpu0.dtb.inst_misses 0 # ITB inst misses 210system.cpu0.dtb.read_hits 7857580 # DTB read hits 211system.cpu0.dtb.read_misses 1898 # DTB read misses 212system.cpu0.dtb.write_hits 6224259 # DTB write hits 213system.cpu0.dtb.write_misses 1143 # DTB write misses 214system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 215system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 216system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 217system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 218system.cpu0.dtb.flush_entries 1404 # Number of entries that have been flushed from TLB 219system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 220system.cpu0.dtb.prefetch_faults 79 # Number of TLB faults due to prefetch 221system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 222system.cpu0.dtb.perms_faults 191 # Number of TLB faults due to permissions restrictions 223system.cpu0.dtb.read_accesses 7859478 # DTB read accesses 224system.cpu0.dtb.write_accesses 6225402 # DTB write accesses 225system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 226system.cpu0.dtb.hits 14081839 # DTB hits 227system.cpu0.dtb.misses 3041 # DTB misses 228system.cpu0.dtb.accesses 14084880 # DTB accesses 229system.cpu0.itb.inst_hits 35747911 # ITB inst hits 230system.cpu0.itb.inst_misses 1204 # ITB inst misses 231system.cpu0.itb.read_hits 0 # DTB read hits 232system.cpu0.itb.read_misses 0 # DTB read misses 233system.cpu0.itb.write_hits 0 # DTB write hits 234system.cpu0.itb.write_misses 0 # DTB write misses 235system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 236system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 237system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 238system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 239system.cpu0.itb.flush_entries 1262 # Number of entries that have been flushed from TLB 240system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 241system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 242system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 243system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 244system.cpu0.itb.read_accesses 0 # DTB read accesses 245system.cpu0.itb.write_accesses 0 # DTB write accesses 246system.cpu0.itb.inst_accesses 35749115 # ITB inst accesses 247system.cpu0.itb.hits 35747911 # DTB hits 248system.cpu0.itb.misses 1204 # DTB misses 249system.cpu0.itb.accesses 35749115 # DTB accesses 250system.cpu0.numCycles 5337805216 # number of cpu cycles simulated 251system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 252system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 253system.cpu0.num_insts 43969024 # Number of instructions executed 254system.cpu0.num_int_alu_accesses 39881498 # Number of integer alu accesses 255system.cpu0.num_fp_alu_accesses 4107 # Number of float alu accesses 256system.cpu0.num_func_calls 977479 # number of times a function call or return occured 257system.cpu0.num_conditional_control_insts 4512711 # number of instructions that are conditional controls 258system.cpu0.num_int_insts 39881498 # number of integer instructions 259system.cpu0.num_fp_insts 4107 # number of float instructions 260system.cpu0.num_int_register_reads 225043856 # number of times the integer registers were read 261system.cpu0.num_int_register_writes 43158045 # number of times the integer registers were written 262system.cpu0.num_fp_register_reads 3851 # number of times the floating registers were read 263system.cpu0.num_fp_register_writes 256 # number of times the floating registers were written 264system.cpu0.num_mem_refs 14677999 # number of memory refs 265system.cpu0.num_load_insts 8148547 # Number of load instructions 266system.cpu0.num_store_insts 6529452 # Number of store instructions 267system.cpu0.num_idle_cycles 5107410781.564784 # Number of idle cycles 268system.cpu0.num_busy_cycles 230394434.435216 # Number of busy cycles 269system.cpu0.not_idle_fraction 0.043163 # Percentage of non-idle cycles 270system.cpu0.idle_fraction 0.956837 # Percentage of idle cycles 271system.cpu0.kern.inst.arm 0 # number of arm instructions executed 272system.cpu0.kern.inst.quiesce 38525 # number of quiesce instructions executed 273system.cpu0.icache.replacements 380069 # number of replacements 274system.cpu0.icache.tagsinuse 510.849663 # Cycle average of tags in use 275system.cpu0.icache.total_refs 35367311 # Total number of references to valid blocks. 276system.cpu0.icache.sampled_refs 380581 # Sample count of references to valid blocks. 277system.cpu0.icache.avg_refs 92.929786 # Average number of references to valid blocks. 278system.cpu0.icache.warmup_cycle 74921716000 # Cycle when the warmup percentage was hit. 279system.cpu0.icache.occ_blocks::0 510.849663 # Average occupied blocks per context 280system.cpu0.icache.occ_percent::0 0.997753 # Average percentage of cache occupancy 281system.cpu0.icache.ReadReq_hits::0 35367311 # number of ReadReq hits 282system.cpu0.icache.ReadReq_hits::total 35367311 # number of ReadReq hits 283system.cpu0.icache.demand_hits::0 35367311 # number of demand (read+write) hits 284system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits 285system.cpu0.icache.demand_hits::total 35367311 # number of demand (read+write) hits 286system.cpu0.icache.overall_hits::0 35367311 # number of overall hits 287system.cpu0.icache.overall_hits::1 0 # number of overall hits 288system.cpu0.icache.overall_hits::total 35367311 # number of overall hits 289system.cpu0.icache.ReadReq_misses::0 380583 # number of ReadReq misses 290system.cpu0.icache.ReadReq_misses::total 380583 # number of ReadReq misses 291system.cpu0.icache.demand_misses::0 380583 # number of demand (read+write) misses 292system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses 293system.cpu0.icache.demand_misses::total 380583 # number of demand (read+write) misses 294system.cpu0.icache.overall_misses::0 380583 # number of overall misses 295system.cpu0.icache.overall_misses::1 0 # number of overall misses 296system.cpu0.icache.overall_misses::total 380583 # number of overall misses 297system.cpu0.icache.ReadReq_miss_latency 5651439000 # number of ReadReq miss cycles 298system.cpu0.icache.demand_miss_latency 5651439000 # number of demand (read+write) miss cycles 299system.cpu0.icache.overall_miss_latency 5651439000 # number of overall miss cycles 300system.cpu0.icache.ReadReq_accesses::0 35747894 # number of ReadReq accesses(hits+misses) 301system.cpu0.icache.ReadReq_accesses::total 35747894 # number of ReadReq accesses(hits+misses) 302system.cpu0.icache.demand_accesses::0 35747894 # number of demand (read+write) accesses 303system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses 304system.cpu0.icache.demand_accesses::total 35747894 # number of demand (read+write) accesses 305system.cpu0.icache.overall_accesses::0 35747894 # number of overall (read+write) accesses 306system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses 307system.cpu0.icache.overall_accesses::total 35747894 # number of overall (read+write) accesses 308system.cpu0.icache.ReadReq_miss_rate::0 0.010646 # miss rate for ReadReq accesses 309system.cpu0.icache.demand_miss_rate::0 0.010646 # miss rate for demand accesses 310system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses 311system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses 312system.cpu0.icache.overall_miss_rate::0 0.010646 # miss rate for overall accesses 313system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses 314system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses 315system.cpu0.icache.ReadReq_avg_miss_latency::0 14849.425749 # average ReadReq miss latency 316system.cpu0.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency 317system.cpu0.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency 318system.cpu0.icache.demand_avg_miss_latency::0 14849.425749 # average overall miss latency 319system.cpu0.icache.demand_avg_miss_latency::1 inf # average overall miss latency 320system.cpu0.icache.demand_avg_miss_latency::total inf # average overall miss latency 321system.cpu0.icache.overall_avg_miss_latency::0 14849.425749 # average overall miss latency 322system.cpu0.icache.overall_avg_miss_latency::1 inf # average overall miss latency 323system.cpu0.icache.overall_avg_miss_latency::total inf # average overall miss latency 324system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 325system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 326system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 327system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 328system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 329system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 330system.cpu0.icache.fast_writes 0 # number of fast writes performed 331system.cpu0.icache.cache_copies 0 # number of cache copies performed 332system.cpu0.icache.writebacks 12960 # number of writebacks 333system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 334system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits 335system.cpu0.icache.ReadReq_mshr_misses 380583 # number of ReadReq MSHR misses 336system.cpu0.icache.demand_mshr_misses 380583 # number of demand (read+write) MSHR misses 337system.cpu0.icache.overall_mshr_misses 380583 # number of overall MSHR misses 338system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 339system.cpu0.icache.ReadReq_mshr_miss_latency 4509188500 # number of ReadReq MSHR miss cycles 340system.cpu0.icache.demand_mshr_miss_latency 4509188500 # number of demand (read+write) MSHR miss cycles 341system.cpu0.icache.overall_mshr_miss_latency 4509188500 # number of overall MSHR miss cycles 342system.cpu0.icache.ReadReq_mshr_uncacheable_latency 351814000 # number of ReadReq MSHR uncacheable cycles 343system.cpu0.icache.overall_mshr_uncacheable_latency 351814000 # number of overall MSHR uncacheable cycles 344system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.010646 # mshr miss rate for ReadReq accesses 345system.cpu0.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses 346system.cpu0.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses 347system.cpu0.icache.demand_mshr_miss_rate::0 0.010646 # mshr miss rate for demand accesses 348system.cpu0.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses 349system.cpu0.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses 350system.cpu0.icache.overall_mshr_miss_rate::0 0.010646 # mshr miss rate for overall accesses 351system.cpu0.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses 352system.cpu0.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses 353system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11848.108034 # average ReadReq mshr miss latency 354system.cpu0.icache.demand_avg_mshr_miss_latency 11848.108034 # average overall mshr miss latency 355system.cpu0.icache.overall_avg_mshr_miss_latency 11848.108034 # average overall mshr miss latency 356system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency 357system.cpu0.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency 358system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated 359system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 360system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 361system.cpu0.dcache.replacements 334596 # number of replacements 362system.cpu0.dcache.tagsinuse 450.118381 # Cycle average of tags in use 363system.cpu0.dcache.total_refs 12875674 # Total number of references to valid blocks. 364system.cpu0.dcache.sampled_refs 335004 # Sample count of references to valid blocks. 365system.cpu0.dcache.avg_refs 38.434389 # Average number of references to valid blocks. 366system.cpu0.dcache.warmup_cycle 663204000 # Cycle when the warmup percentage was hit. 367system.cpu0.dcache.occ_blocks::0 450.118381 # Average occupied blocks per context 368system.cpu0.dcache.occ_percent::0 0.879137 # Average percentage of cache occupancy 369system.cpu0.dcache.ReadReq_hits::0 7428609 # number of ReadReq hits 370system.cpu0.dcache.ReadReq_hits::total 7428609 # number of ReadReq hits 371system.cpu0.dcache.WriteReq_hits::0 5172633 # number of WriteReq hits 372system.cpu0.dcache.WriteReq_hits::total 5172633 # number of WriteReq hits 373system.cpu0.dcache.LoadLockedReq_hits::0 126778 # number of LoadLockedReq hits 374system.cpu0.dcache.LoadLockedReq_hits::total 126778 # number of LoadLockedReq hits 375system.cpu0.dcache.StoreCondReq_hits::0 127996 # number of StoreCondReq hits 376system.cpu0.dcache.StoreCondReq_hits::total 127996 # number of StoreCondReq hits 377system.cpu0.dcache.demand_hits::0 12601242 # number of demand (read+write) hits 378system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits 379system.cpu0.dcache.demand_hits::total 12601242 # number of demand (read+write) hits 380system.cpu0.dcache.overall_hits::0 12601242 # number of overall hits 381system.cpu0.dcache.overall_hits::1 0 # number of overall hits 382system.cpu0.dcache.overall_hits::total 12601242 # number of overall hits 383system.cpu0.dcache.ReadReq_misses::0 217330 # number of ReadReq misses 384system.cpu0.dcache.ReadReq_misses::total 217330 # number of ReadReq misses 385system.cpu0.dcache.WriteReq_misses::0 155538 # number of WriteReq misses 386system.cpu0.dcache.WriteReq_misses::total 155538 # number of WriteReq misses 387system.cpu0.dcache.LoadLockedReq_misses::0 9456 # number of LoadLockedReq misses 388system.cpu0.dcache.LoadLockedReq_misses::total 9456 # number of LoadLockedReq misses 389system.cpu0.dcache.StoreCondReq_misses::0 8189 # number of StoreCondReq misses 390system.cpu0.dcache.StoreCondReq_misses::total 8189 # number of StoreCondReq misses 391system.cpu0.dcache.demand_misses::0 372868 # number of demand (read+write) misses 392system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses 393system.cpu0.dcache.demand_misses::total 372868 # number of demand (read+write) misses 394system.cpu0.dcache.overall_misses::0 372868 # number of overall misses 395system.cpu0.dcache.overall_misses::1 0 # number of overall misses 396system.cpu0.dcache.overall_misses::total 372868 # number of overall misses 397system.cpu0.dcache.ReadReq_miss_latency 3330686000 # number of ReadReq miss cycles 398system.cpu0.dcache.WriteReq_miss_latency 6317758500 # number of WriteReq miss cycles 399system.cpu0.dcache.LoadLockedReq_miss_latency 100249000 # number of LoadLockedReq miss cycles 400system.cpu0.dcache.StoreCondReq_miss_latency 70240000 # number of StoreCondReq miss cycles 401system.cpu0.dcache.demand_miss_latency 9648444500 # number of demand (read+write) miss cycles 402system.cpu0.dcache.overall_miss_latency 9648444500 # number of overall miss cycles 403system.cpu0.dcache.ReadReq_accesses::0 7645939 # number of ReadReq accesses(hits+misses) 404system.cpu0.dcache.ReadReq_accesses::total 7645939 # number of ReadReq accesses(hits+misses) 405system.cpu0.dcache.WriteReq_accesses::0 5328171 # number of WriteReq accesses(hits+misses) 406system.cpu0.dcache.WriteReq_accesses::total 5328171 # number of WriteReq accesses(hits+misses) 407system.cpu0.dcache.LoadLockedReq_accesses::0 136234 # number of LoadLockedReq accesses(hits+misses) 408system.cpu0.dcache.LoadLockedReq_accesses::total 136234 # number of LoadLockedReq accesses(hits+misses) 409system.cpu0.dcache.StoreCondReq_accesses::0 136185 # number of StoreCondReq accesses(hits+misses) 410system.cpu0.dcache.StoreCondReq_accesses::total 136185 # number of StoreCondReq accesses(hits+misses) 411system.cpu0.dcache.demand_accesses::0 12974110 # number of demand (read+write) accesses 412system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses 413system.cpu0.dcache.demand_accesses::total 12974110 # number of demand (read+write) accesses 414system.cpu0.dcache.overall_accesses::0 12974110 # number of overall (read+write) accesses 415system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses 416system.cpu0.dcache.overall_accesses::total 12974110 # number of overall (read+write) accesses 417system.cpu0.dcache.ReadReq_miss_rate::0 0.028424 # miss rate for ReadReq accesses 418system.cpu0.dcache.WriteReq_miss_rate::0 0.029192 # miss rate for WriteReq accesses 419system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.069410 # miss rate for LoadLockedReq accesses 420system.cpu0.dcache.StoreCondReq_miss_rate::0 0.060131 # miss rate for StoreCondReq accesses 421system.cpu0.dcache.demand_miss_rate::0 0.028739 # miss rate for demand accesses 422system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses 423system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses 424system.cpu0.dcache.overall_miss_rate::0 0.028739 # miss rate for overall accesses 425system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses 426system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses 427system.cpu0.dcache.ReadReq_avg_miss_latency::0 15325.477385 # average ReadReq miss latency 428system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency 429system.cpu0.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency 430system.cpu0.dcache.WriteReq_avg_miss_latency::0 40618.745901 # average WriteReq miss latency 431system.cpu0.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency 432system.cpu0.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency 433system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 10601.628596 # average LoadLockedReq miss latency 434system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency 435system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency 436system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 8577.359873 # average StoreCondReq miss latency 437system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency 438system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency 439system.cpu0.dcache.demand_avg_miss_latency::0 25876.300728 # average overall miss latency 440system.cpu0.dcache.demand_avg_miss_latency::1 inf # average overall miss latency 441system.cpu0.dcache.demand_avg_miss_latency::total inf # average overall miss latency 442system.cpu0.dcache.overall_avg_miss_latency::0 25876.300728 # average overall miss latency 443system.cpu0.dcache.overall_avg_miss_latency::1 inf # average overall miss latency 444system.cpu0.dcache.overall_avg_miss_latency::total inf # average overall miss latency 445system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 446system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 447system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 448system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 449system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 450system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 451system.cpu0.dcache.fast_writes 0 # number of fast writes performed 452system.cpu0.dcache.cache_copies 0 # number of cache copies performed 453system.cpu0.dcache.writebacks 294891 # number of writebacks 454system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 455system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits 456system.cpu0.dcache.ReadReq_mshr_misses 217330 # number of ReadReq MSHR misses 457system.cpu0.dcache.WriteReq_mshr_misses 155538 # number of WriteReq MSHR misses 458system.cpu0.dcache.LoadLockedReq_mshr_misses 9456 # number of LoadLockedReq MSHR misses 459system.cpu0.dcache.StoreCondReq_mshr_misses 8184 # number of StoreCondReq MSHR misses 460system.cpu0.dcache.demand_mshr_misses 372868 # number of demand (read+write) MSHR misses 461system.cpu0.dcache.overall_mshr_misses 372868 # number of overall MSHR misses 462system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 463system.cpu0.dcache.ReadReq_mshr_miss_latency 2678673500 # number of ReadReq MSHR miss cycles 464system.cpu0.dcache.WriteReq_mshr_miss_latency 5851029000 # number of WriteReq MSHR miss cycles 465system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 71881000 # number of LoadLockedReq MSHR miss cycles 466system.cpu0.dcache.StoreCondReq_mshr_miss_latency 45691000 # number of StoreCondReq MSHR miss cycles 467system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency 1000 # number of StoreCondFailReq MSHR miss cycles 468system.cpu0.dcache.demand_mshr_miss_latency 8529702500 # number of demand (read+write) MSHR miss cycles 469system.cpu0.dcache.overall_mshr_miss_latency 8529702500 # number of overall MSHR miss cycles 470system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 9171180500 # number of ReadReq MSHR uncacheable cycles 471system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 40129379500 # number of WriteReq MSHR uncacheable cycles 472system.cpu0.dcache.overall_mshr_uncacheable_latency 49300560000 # number of overall MSHR uncacheable cycles 473system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.028424 # mshr miss rate for ReadReq accesses 474system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses 475system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses 476system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.029192 # mshr miss rate for WriteReq accesses 477system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses 478system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses 479system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.069410 # mshr miss rate for LoadLockedReq accesses 480system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses 481system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses 482system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.060095 # mshr miss rate for StoreCondReq accesses 483system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses 484system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses 485system.cpu0.dcache.demand_mshr_miss_rate::0 0.028739 # mshr miss rate for demand accesses 486system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses 487system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses 488system.cpu0.dcache.overall_mshr_miss_rate::0 0.028739 # mshr miss rate for overall accesses 489system.cpu0.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses 490system.cpu0.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses 491system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 12325.373855 # average ReadReq mshr miss latency 492system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 37618.003318 # average WriteReq mshr miss latency 493system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 7601.628596 # average LoadLockedReq mshr miss latency 494system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 5582.966764 # average StoreCondReq mshr miss latency 495system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency inf # average StoreCondFailReq mshr miss latency 496system.cpu0.dcache.demand_avg_mshr_miss_latency 22875.930624 # average overall mshr miss latency 497system.cpu0.dcache.overall_avg_mshr_miss_latency 22875.930624 # average overall mshr miss latency 498system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency 499system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency 500system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency 501system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 502system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 503system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 504system.cpu1.dtb.inst_hits 0 # ITB inst hits 505system.cpu1.dtb.inst_misses 0 # ITB inst misses 506system.cpu1.dtb.read_hits 7762496 # DTB read hits 507system.cpu1.dtb.read_misses 5432 # DTB read misses 508system.cpu1.dtb.write_hits 5411648 # DTB write hits 509system.cpu1.dtb.write_misses 1096 # DTB write misses 510system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 511system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 512system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 513system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 514system.cpu1.dtb.flush_entries 2346 # Number of entries that have been flushed from TLB 515system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 516system.cpu1.dtb.prefetch_faults 166 # Number of TLB faults due to prefetch 517system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 518system.cpu1.dtb.perms_faults 261 # Number of TLB faults due to permissions restrictions 519system.cpu1.dtb.read_accesses 7767928 # DTB read accesses 520system.cpu1.dtb.write_accesses 5412744 # DTB write accesses 521system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 522system.cpu1.dtb.hits 13174144 # DTB hits 523system.cpu1.dtb.misses 6528 # DTB misses 524system.cpu1.dtb.accesses 13180672 # DTB accesses 525system.cpu1.itb.inst_hits 26848280 # ITB inst hits 526system.cpu1.itb.inst_misses 3154 # ITB inst misses 527system.cpu1.itb.read_hits 0 # DTB read hits 528system.cpu1.itb.read_misses 0 # DTB read misses 529system.cpu1.itb.write_hits 0 # DTB write hits 530system.cpu1.itb.write_misses 0 # DTB write misses 531system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 532system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 533system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 534system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 535system.cpu1.itb.flush_entries 1544 # Number of entries that have been flushed from TLB 536system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 537system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 538system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 539system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 540system.cpu1.itb.read_accesses 0 # DTB read accesses 541system.cpu1.itb.write_accesses 0 # DTB write accesses 542system.cpu1.itb.inst_accesses 26851434 # ITB inst accesses 543system.cpu1.itb.hits 26848280 # DTB hits 544system.cpu1.itb.misses 3154 # DTB misses 545system.cpu1.itb.accesses 26851434 # DTB accesses 546system.cpu1.numCycles 5339222450 # number of cpu cycles simulated 547system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 548system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 549system.cpu1.num_insts 34444935 # Number of instructions executed 550system.cpu1.num_int_alu_accesses 31033253 # Number of integer alu accesses 551system.cpu1.num_fp_alu_accesses 5714 # Number of float alu accesses 552system.cpu1.num_func_calls 1093852 # number of times a function call or return occured 553system.cpu1.num_conditional_control_insts 3362553 # number of instructions that are conditional controls 554system.cpu1.num_int_insts 31033253 # number of integer instructions 555system.cpu1.num_fp_insts 5714 # number of float instructions 556system.cpu1.num_int_register_reads 181157193 # number of times the integer registers were read 557system.cpu1.num_int_register_writes 32585304 # number of times the integer registers were written 558system.cpu1.num_fp_register_reads 3770 # number of times the floating registers were read 559system.cpu1.num_fp_register_writes 1948 # number of times the floating registers were written 560system.cpu1.num_mem_refs 13796843 # number of memory refs 561system.cpu1.num_load_insts 8139019 # Number of load instructions 562system.cpu1.num_store_insts 5657824 # Number of store instructions 563system.cpu1.num_idle_cycles 4950307250.068146 # Number of idle cycles 564system.cpu1.num_busy_cycles 388915199.931854 # Number of busy cycles 565system.cpu1.not_idle_fraction 0.072841 # Percentage of non-idle cycles 566system.cpu1.idle_fraction 0.927159 # Percentage of idle cycles 567system.cpu1.kern.inst.arm 0 # number of arm instructions executed 568system.cpu1.kern.inst.quiesce 53838 # number of quiesce instructions executed 569system.cpu1.icache.replacements 508221 # number of replacements 570system.cpu1.icache.tagsinuse 497.375159 # Cycle average of tags in use 571system.cpu1.icache.total_refs 26339543 # Total number of references to valid blocks. 572system.cpu1.icache.sampled_refs 508733 # Sample count of references to valid blocks. 573system.cpu1.icache.avg_refs 51.774788 # Average number of references to valid blocks. 574system.cpu1.icache.warmup_cycle 191336880000 # Cycle when the warmup percentage was hit. 575system.cpu1.icache.occ_blocks::0 497.375159 # Average occupied blocks per context 576system.cpu1.icache.occ_percent::0 0.971436 # Average percentage of cache occupancy 577system.cpu1.icache.ReadReq_hits::0 26339543 # number of ReadReq hits 578system.cpu1.icache.ReadReq_hits::total 26339543 # number of ReadReq hits 579system.cpu1.icache.demand_hits::0 26339543 # number of demand (read+write) hits 580system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits 581system.cpu1.icache.demand_hits::total 26339543 # number of demand (read+write) hits 582system.cpu1.icache.overall_hits::0 26339543 # number of overall hits 583system.cpu1.icache.overall_hits::1 0 # number of overall hits 584system.cpu1.icache.overall_hits::total 26339543 # number of overall hits 585system.cpu1.icache.ReadReq_misses::0 508733 # number of ReadReq misses 586system.cpu1.icache.ReadReq_misses::total 508733 # number of ReadReq misses 587system.cpu1.icache.demand_misses::0 508733 # number of demand (read+write) misses 588system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses 589system.cpu1.icache.demand_misses::total 508733 # number of demand (read+write) misses 590system.cpu1.icache.overall_misses::0 508733 # number of overall misses 591system.cpu1.icache.overall_misses::1 0 # number of overall misses 592system.cpu1.icache.overall_misses::total 508733 # number of overall misses 593system.cpu1.icache.ReadReq_miss_latency 7436442000 # number of ReadReq miss cycles 594system.cpu1.icache.demand_miss_latency 7436442000 # number of demand (read+write) miss cycles 595system.cpu1.icache.overall_miss_latency 7436442000 # number of overall miss cycles 596system.cpu1.icache.ReadReq_accesses::0 26848276 # number of ReadReq accesses(hits+misses) 597system.cpu1.icache.ReadReq_accesses::total 26848276 # number of ReadReq accesses(hits+misses) 598system.cpu1.icache.demand_accesses::0 26848276 # number of demand (read+write) accesses 599system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses 600system.cpu1.icache.demand_accesses::total 26848276 # number of demand (read+write) accesses 601system.cpu1.icache.overall_accesses::0 26848276 # number of overall (read+write) accesses 602system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses 603system.cpu1.icache.overall_accesses::total 26848276 # number of overall (read+write) accesses 604system.cpu1.icache.ReadReq_miss_rate::0 0.018948 # miss rate for ReadReq accesses 605system.cpu1.icache.demand_miss_rate::0 0.018948 # miss rate for demand accesses 606system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses 607system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses 608system.cpu1.icache.overall_miss_rate::0 0.018948 # miss rate for overall accesses 609system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses 610system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses 611system.cpu1.icache.ReadReq_avg_miss_latency::0 14617.573462 # average ReadReq miss latency 612system.cpu1.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency 613system.cpu1.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency 614system.cpu1.icache.demand_avg_miss_latency::0 14617.573462 # average overall miss latency 615system.cpu1.icache.demand_avg_miss_latency::1 inf # average overall miss latency 616system.cpu1.icache.demand_avg_miss_latency::total inf # average overall miss latency 617system.cpu1.icache.overall_avg_miss_latency::0 14617.573462 # average overall miss latency 618system.cpu1.icache.overall_avg_miss_latency::1 inf # average overall miss latency 619system.cpu1.icache.overall_avg_miss_latency::total inf # average overall miss latency 620system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 621system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 622system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 623system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 624system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 625system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 626system.cpu1.icache.fast_writes 0 # number of fast writes performed 627system.cpu1.icache.cache_copies 0 # number of cache copies performed 628system.cpu1.icache.writebacks 27998 # number of writebacks 629system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 630system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits 631system.cpu1.icache.ReadReq_mshr_misses 508733 # number of ReadReq MSHR misses 632system.cpu1.icache.demand_mshr_misses 508733 # number of demand (read+write) MSHR misses 633system.cpu1.icache.overall_mshr_misses 508733 # number of overall MSHR misses 634system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 635system.cpu1.icache.ReadReq_mshr_miss_latency 5908060000 # number of ReadReq MSHR miss cycles 636system.cpu1.icache.demand_mshr_miss_latency 5908060000 # number of demand (read+write) MSHR miss cycles 637system.cpu1.icache.overall_mshr_miss_latency 5908060000 # number of overall MSHR miss cycles 638system.cpu1.icache.ReadReq_mshr_uncacheable_latency 5250000 # number of ReadReq MSHR uncacheable cycles 639system.cpu1.icache.overall_mshr_uncacheable_latency 5250000 # number of overall MSHR uncacheable cycles 640system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.018948 # mshr miss rate for ReadReq accesses 641system.cpu1.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses 642system.cpu1.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses 643system.cpu1.icache.demand_mshr_miss_rate::0 0.018948 # mshr miss rate for demand accesses 644system.cpu1.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses 645system.cpu1.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses 646system.cpu1.icache.overall_mshr_miss_rate::0 0.018948 # mshr miss rate for overall accesses 647system.cpu1.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses 648system.cpu1.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses 649system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11613.282409 # average ReadReq mshr miss latency 650system.cpu1.icache.demand_avg_mshr_miss_latency 11613.282409 # average overall mshr miss latency 651system.cpu1.icache.overall_avg_mshr_miss_latency 11613.282409 # average overall mshr miss latency 652system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency 653system.cpu1.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency 654system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated 655system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 656system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 657system.cpu1.dcache.replacements 295754 # number of replacements 658system.cpu1.dcache.tagsinuse 467.166427 # Cycle average of tags in use 659system.cpu1.dcache.total_refs 11737107 # Total number of references to valid blocks. 660system.cpu1.dcache.sampled_refs 296266 # Sample count of references to valid blocks. 661system.cpu1.dcache.avg_refs 39.616787 # Average number of references to valid blocks. 662system.cpu1.dcache.warmup_cycle 75924171000 # Cycle when the warmup percentage was hit. 663system.cpu1.dcache.occ_blocks::0 467.166427 # Average occupied blocks per context 664system.cpu1.dcache.occ_percent::0 0.912434 # Average percentage of cache occupancy 665system.cpu1.dcache.ReadReq_hits::0 6345290 # number of ReadReq hits 666system.cpu1.dcache.ReadReq_hits::total 6345290 # number of ReadReq hits 667system.cpu1.dcache.WriteReq_hits::0 5152610 # number of WriteReq hits 668system.cpu1.dcache.WriteReq_hits::total 5152610 # number of WriteReq hits 669system.cpu1.dcache.LoadLockedReq_hits::0 104795 # number of LoadLockedReq hits 670system.cpu1.dcache.LoadLockedReq_hits::total 104795 # number of LoadLockedReq hits 671system.cpu1.dcache.StoreCondReq_hits::0 106403 # number of StoreCondReq hits 672system.cpu1.dcache.StoreCondReq_hits::total 106403 # number of StoreCondReq hits 673system.cpu1.dcache.demand_hits::0 11497900 # number of demand (read+write) hits 674system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits 675system.cpu1.dcache.demand_hits::total 11497900 # number of demand (read+write) hits 676system.cpu1.dcache.overall_hits::0 11497900 # number of overall hits 677system.cpu1.dcache.overall_hits::1 0 # number of overall hits 678system.cpu1.dcache.overall_hits::total 11497900 # number of overall hits 679system.cpu1.dcache.ReadReq_misses::0 188245 # number of ReadReq misses 680system.cpu1.dcache.ReadReq_misses::total 188245 # number of ReadReq misses 681system.cpu1.dcache.WriteReq_misses::0 137493 # number of WriteReq misses 682system.cpu1.dcache.WriteReq_misses::total 137493 # number of WriteReq misses 683system.cpu1.dcache.LoadLockedReq_misses::0 11557 # number of LoadLockedReq misses 684system.cpu1.dcache.LoadLockedReq_misses::total 11557 # number of LoadLockedReq misses 685system.cpu1.dcache.StoreCondReq_misses::0 9906 # number of StoreCondReq misses 686system.cpu1.dcache.StoreCondReq_misses::total 9906 # number of StoreCondReq misses 687system.cpu1.dcache.demand_misses::0 325738 # number of demand (read+write) misses 688system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses 689system.cpu1.dcache.demand_misses::total 325738 # number of demand (read+write) misses 690system.cpu1.dcache.overall_misses::0 325738 # number of overall misses 691system.cpu1.dcache.overall_misses::1 0 # number of overall misses 692system.cpu1.dcache.overall_misses::total 325738 # number of overall misses 693system.cpu1.dcache.ReadReq_miss_latency 2729023500 # number of ReadReq miss cycles 694system.cpu1.dcache.WriteReq_miss_latency 4123985000 # number of WriteReq miss cycles 695system.cpu1.dcache.LoadLockedReq_miss_latency 131721000 # number of LoadLockedReq miss cycles 696system.cpu1.dcache.StoreCondReq_miss_latency 82493000 # number of StoreCondReq miss cycles 697system.cpu1.dcache.demand_miss_latency 6853008500 # number of demand (read+write) miss cycles 698system.cpu1.dcache.overall_miss_latency 6853008500 # number of overall miss cycles 699system.cpu1.dcache.ReadReq_accesses::0 6533535 # number of ReadReq accesses(hits+misses) 700system.cpu1.dcache.ReadReq_accesses::total 6533535 # number of ReadReq accesses(hits+misses) 701system.cpu1.dcache.WriteReq_accesses::0 5290103 # number of WriteReq accesses(hits+misses) 702system.cpu1.dcache.WriteReq_accesses::total 5290103 # number of WriteReq accesses(hits+misses) 703system.cpu1.dcache.LoadLockedReq_accesses::0 116352 # number of LoadLockedReq accesses(hits+misses) 704system.cpu1.dcache.LoadLockedReq_accesses::total 116352 # number of LoadLockedReq accesses(hits+misses) 705system.cpu1.dcache.StoreCondReq_accesses::0 116309 # number of StoreCondReq accesses(hits+misses) 706system.cpu1.dcache.StoreCondReq_accesses::total 116309 # number of StoreCondReq accesses(hits+misses) 707system.cpu1.dcache.demand_accesses::0 11823638 # number of demand (read+write) accesses 708system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses 709system.cpu1.dcache.demand_accesses::total 11823638 # number of demand (read+write) accesses 710system.cpu1.dcache.overall_accesses::0 11823638 # number of overall (read+write) accesses 711system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses 712system.cpu1.dcache.overall_accesses::total 11823638 # number of overall (read+write) accesses 713system.cpu1.dcache.ReadReq_miss_rate::0 0.028812 # miss rate for ReadReq accesses 714system.cpu1.dcache.WriteReq_miss_rate::0 0.025991 # miss rate for WriteReq accesses 715system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.099328 # miss rate for LoadLockedReq accesses 716system.cpu1.dcache.StoreCondReq_miss_rate::0 0.085170 # miss rate for StoreCondReq accesses 717system.cpu1.dcache.demand_miss_rate::0 0.027550 # miss rate for demand accesses 718system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses 719system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses 720system.cpu1.dcache.overall_miss_rate::0 0.027550 # miss rate for overall accesses 721system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses 722system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses 723system.cpu1.dcache.ReadReq_avg_miss_latency::0 14497.189832 # average ReadReq miss latency 724system.cpu1.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency 725system.cpu1.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency 726system.cpu1.dcache.WriteReq_avg_miss_latency::0 29994.145156 # average WriteReq miss latency 727system.cpu1.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency 728system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency 729system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 11397.508004 # average LoadLockedReq miss latency 730system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency 731system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency 732system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 8327.579245 # average StoreCondReq miss latency 733system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency 734system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency 735system.cpu1.dcache.demand_avg_miss_latency::0 21038.406634 # average overall miss latency 736system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency 737system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency 738system.cpu1.dcache.overall_avg_miss_latency::0 21038.406634 # average overall miss latency 739system.cpu1.dcache.overall_avg_miss_latency::1 inf # average overall miss latency 740system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency 741system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 742system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 743system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 744system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 745system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 746system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 747system.cpu1.dcache.fast_writes 0 # number of fast writes performed 748system.cpu1.dcache.cache_copies 0 # number of cache copies performed 749system.cpu1.dcache.writebacks 253551 # number of writebacks 750system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 751system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits 752system.cpu1.dcache.ReadReq_mshr_misses 188245 # number of ReadReq MSHR misses 753system.cpu1.dcache.WriteReq_mshr_misses 137493 # number of WriteReq MSHR misses 754system.cpu1.dcache.LoadLockedReq_mshr_misses 11557 # number of LoadLockedReq MSHR misses 755system.cpu1.dcache.StoreCondReq_mshr_misses 9900 # number of StoreCondReq MSHR misses 756system.cpu1.dcache.demand_mshr_misses 325738 # number of demand (read+write) MSHR misses 757system.cpu1.dcache.overall_mshr_misses 325738 # number of overall MSHR misses 758system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 759system.cpu1.dcache.ReadReq_mshr_miss_latency 2164153000 # number of ReadReq MSHR miss cycles 760system.cpu1.dcache.WriteReq_mshr_miss_latency 3711466500 # number of WriteReq MSHR miss cycles 761system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 97050000 # number of LoadLockedReq MSHR miss cycles 762system.cpu1.dcache.StoreCondReq_mshr_miss_latency 52793000 # number of StoreCondReq MSHR miss cycles 763system.cpu1.dcache.demand_mshr_miss_latency 5875619500 # number of demand (read+write) MSHR miss cycles 764system.cpu1.dcache.overall_mshr_miss_latency 5875619500 # number of overall MSHR miss cycles 765system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 137931975000 # number of ReadReq MSHR uncacheable cycles 766system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 470526000 # number of WriteReq MSHR uncacheable cycles 767system.cpu1.dcache.overall_mshr_uncacheable_latency 138402501000 # number of overall MSHR uncacheable cycles 768system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.028812 # mshr miss rate for ReadReq accesses 769system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses 770system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses 771system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.025991 # mshr miss rate for WriteReq accesses 772system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses 773system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses 774system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.099328 # mshr miss rate for LoadLockedReq accesses 775system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses 776system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses 777system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.085118 # mshr miss rate for StoreCondReq accesses 778system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses 779system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses 780system.cpu1.dcache.demand_mshr_miss_rate::0 0.027550 # mshr miss rate for demand accesses 781system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses 782system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses 783system.cpu1.dcache.overall_mshr_miss_rate::0 0.027550 # mshr miss rate for overall accesses 784system.cpu1.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses 785system.cpu1.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses 786system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11496.470026 # average ReadReq mshr miss latency 787system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 26993.857869 # average WriteReq mshr miss latency 788system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 8397.508004 # average LoadLockedReq mshr miss latency 789system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 5332.626263 # average StoreCondReq mshr miss latency 790system.cpu1.dcache.demand_avg_mshr_miss_latency 18037.869392 # average overall mshr miss latency 791system.cpu1.dcache.overall_avg_mshr_miss_latency 18037.869392 # average overall mshr miss latency 792system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency 793system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency 794system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency 795system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 796system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 797system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 798system.iocache.replacements 0 # number of replacements 799system.iocache.tagsinuse 0 # Cycle average of tags in use 800system.iocache.total_refs 0 # Total number of references to valid blocks. 801system.iocache.sampled_refs 0 # Sample count of references to valid blocks. 802system.iocache.avg_refs no_value # Average number of references to valid blocks. 803system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 804system.iocache.demand_hits::0 0 # number of demand (read+write) hits 805system.iocache.demand_hits::1 0 # number of demand (read+write) hits 806system.iocache.demand_hits::total 0 # number of demand (read+write) hits 807system.iocache.overall_hits::0 0 # number of overall hits 808system.iocache.overall_hits::1 0 # number of overall hits 809system.iocache.overall_hits::total 0 # number of overall hits 810system.iocache.demand_misses::0 0 # number of demand (read+write) misses 811system.iocache.demand_misses::1 0 # number of demand (read+write) misses 812system.iocache.demand_misses::total 0 # number of demand (read+write) misses 813system.iocache.overall_misses::0 0 # number of overall misses 814system.iocache.overall_misses::1 0 # number of overall misses 815system.iocache.overall_misses::total 0 # number of overall misses 816system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles 817system.iocache.overall_miss_latency 0 # number of overall miss cycles 818system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses 819system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses 820system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses 821system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses 822system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses 823system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses 824system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses 825system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses 826system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses 827system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses 828system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses 829system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses 830system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency 831system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency 832system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency 833system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency 834system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency 835system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency 836system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 837system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 838system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 839system.iocache.blocked::no_targets 0 # number of cycles access was blocked 840system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 841system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 842system.iocache.fast_writes 0 # number of fast writes performed 843system.iocache.cache_copies 0 # number of cache copies performed 844system.iocache.writebacks 0 # number of writebacks 845system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 846system.iocache.overall_mshr_hits 0 # number of overall MSHR hits 847system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 848system.iocache.overall_mshr_misses 0 # number of overall MSHR misses 849system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 850system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 851system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 852system.iocache.ReadReq_mshr_uncacheable_latency 1342252853622 # number of ReadReq MSHR uncacheable cycles 853system.iocache.overall_mshr_uncacheable_latency 1342252853622 # number of overall MSHR uncacheable cycles 854system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses 855system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses 856system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses 857system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses 858system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses 859system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses 860system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 861system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 862system.iocache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency 863system.iocache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency 864system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated 865system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 866system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 867 868---------- End Simulation Statistics ---------- 869