simout revision 11219:b65d4e878ed2
112326Sar4jc@virginia.eduRedirecting stdout to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual/simout 212326Sar4jc@virginia.eduRedirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual/simerr 312326Sar4jc@virginia.edugem5 Simulator System. http://gem5.org 412326Sar4jc@virginia.edugem5 is copyrighted software; use the --copyright option for details. 512326Sar4jc@virginia.edu 612326Sar4jc@virginia.edugem5 compiled Nov 15 2015 15:24:37 712326Sar4jc@virginia.edugem5 started Nov 15 2015 15:29:29 812326Sar4jc@virginia.edugem5 executing on ribera.cs.wisc.edu, pid 11176 912326Sar4jc@virginia.educommand line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual 1012326Sar4jc@virginia.edu 1112326Sar4jc@virginia.eduGlobal frequency set at 1000000000000 ticks per second 1212326Sar4jc@virginia.eduinfo: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5 1312326Sar4jc@virginia.eduinfo: Using bootloader at address 0x10 1412326Sar4jc@virginia.eduinfo: Using kernel entry physical address at 0x80008000 1512326Sar4jc@virginia.eduinfo: Loading DTB file: /scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000 1612326Sar4jc@virginia.eduinfo: Entering event queue @ 0. Starting simulation... 1712326Sar4jc@virginia.eduinfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 1812326Sar4jc@virginia.eduinfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 1912326Sar4jc@virginia.eduinfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 2012326Sar4jc@virginia.eduinfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 2112326Sar4jc@virginia.eduinfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 2212326Sar4jc@virginia.eduinfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 2312326Sar4jc@virginia.eduinfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 2412326Sar4jc@virginia.eduinfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 2512326Sar4jc@virginia.eduinfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 2612326Sar4jc@virginia.eduinfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 2712326Sar4jc@virginia.eduinfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 2812326Sar4jc@virginia.eduinfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 2912326Sar4jc@virginia.eduinfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 3012309Sar4jc@virginia.eduinfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 3112309Sar4jc@virginia.eduinfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 3212309Sar4jc@virginia.eduExiting @ tick 2871819744000 because m5_exit instruction encountered 3312323Sar4jc@virginia.edu