stats.txt revision 8802:ef66a9083bc4
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.411694 # Number of seconds simulated 4sim_ticks 2411694099500 # Number of ticks simulated 5final_tick 2411694099500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 2039542 # Simulator instruction rate (inst/s) 8host_tick_rate 61821688958 # Simulator tick rate (ticks/s) 9host_mem_usage 378872 # Number of bytes of host memory used 10host_seconds 39.01 # Real time elapsed on the host 11sim_insts 79563488 # Number of instructions simulated 12system.nvmem.bytes_read 68 # Number of bytes read from this memory 13system.nvmem.bytes_inst_read 68 # Number of instructions bytes read from this memory 14system.nvmem.bytes_written 0 # Number of bytes written to this memory 15system.nvmem.num_reads 17 # Number of read requests responded to by this memory 16system.nvmem.num_writes 0 # Number of write requests responded to by this memory 17system.nvmem.num_other 0 # Number of other requests responded to by this memory 18system.nvmem.bw_read 28 # Total read bandwidth from this memory (bytes/s) 19system.nvmem.bw_inst_read 28 # Instruction read bandwidth from this memory (bytes/s) 20system.nvmem.bw_total 28 # Total bandwidth to/from this memory (bytes/s) 21system.physmem.bytes_read 123270308 # Number of bytes read from this memory 22system.physmem.bytes_inst_read 1011392 # Number of instructions bytes read from this memory 23system.physmem.bytes_written 10185232 # Number of bytes written to this memory 24system.physmem.num_reads 14146769 # Number of read requests responded to by this memory 25system.physmem.num_writes 869038 # Number of write requests responded to by this memory 26system.physmem.num_other 0 # Number of other requests responded to by this memory 27system.physmem.bw_read 51113575 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read 419370 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_write 4223269 # Write bandwidth from this memory (bytes/s) 30system.physmem.bw_total 55336844 # Total bandwidth to/from this memory (bytes/s) 31system.l2c.replacements 127720 # number of replacements 32system.l2c.tagsinuse 25547.920863 # Cycle average of tags in use 33system.l2c.total_refs 1498989 # Total number of references to valid blocks. 34system.l2c.sampled_refs 156132 # Sample count of references to valid blocks. 35system.l2c.avg_refs 9.600780 # Average number of references to valid blocks. 36system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 37system.l2c.occ_blocks::0 4404.089299 # Average occupied blocks per context 38system.l2c.occ_blocks::1 6217.918720 # Average occupied blocks per context 39system.l2c.occ_blocks::2 14925.912843 # Average occupied blocks per context 40system.l2c.occ_percent::0 0.067201 # Average percentage of cache occupancy 41system.l2c.occ_percent::1 0.094878 # Average percentage of cache occupancy 42system.l2c.occ_percent::2 0.227751 # Average percentage of cache occupancy 43system.l2c.ReadReq_hits::0 706190 # number of ReadReq hits 44system.l2c.ReadReq_hits::1 499815 # number of ReadReq hits 45system.l2c.ReadReq_hits::2 12920 # number of ReadReq hits 46system.l2c.ReadReq_hits::total 1218925 # number of ReadReq hits 47system.l2c.Writeback_hits::0 580461 # number of Writeback hits 48system.l2c.Writeback_hits::total 580461 # number of Writeback hits 49system.l2c.UpgradeReq_hits::0 776 # number of UpgradeReq hits 50system.l2c.UpgradeReq_hits::1 523 # number of UpgradeReq hits 51system.l2c.UpgradeReq_hits::total 1299 # number of UpgradeReq hits 52system.l2c.SCUpgradeReq_hits::0 147 # number of SCUpgradeReq hits 53system.l2c.SCUpgradeReq_hits::1 202 # number of SCUpgradeReq hits 54system.l2c.SCUpgradeReq_hits::total 349 # number of SCUpgradeReq hits 55system.l2c.ReadExReq_hits::0 64831 # number of ReadExReq hits 56system.l2c.ReadExReq_hits::1 37797 # number of ReadExReq hits 57system.l2c.ReadExReq_hits::total 102628 # number of ReadExReq hits 58system.l2c.demand_hits::0 771021 # number of demand (read+write) hits 59system.l2c.demand_hits::1 537612 # number of demand (read+write) hits 60system.l2c.demand_hits::2 12920 # number of demand (read+write) hits 61system.l2c.demand_hits::total 1321553 # number of demand (read+write) hits 62system.l2c.overall_hits::0 771021 # number of overall hits 63system.l2c.overall_hits::1 537612 # number of overall hits 64system.l2c.overall_hits::2 12920 # number of overall hits 65system.l2c.overall_hits::total 1321553 # number of overall hits 66system.l2c.ReadReq_misses::0 19675 # number of ReadReq misses 67system.l2c.ReadReq_misses::1 15224 # number of ReadReq misses 68system.l2c.ReadReq_misses::2 52 # number of ReadReq misses 69system.l2c.ReadReq_misses::total 34951 # number of ReadReq misses 70system.l2c.UpgradeReq_misses::0 6349 # number of UpgradeReq misses 71system.l2c.UpgradeReq_misses::1 3492 # number of UpgradeReq misses 72system.l2c.UpgradeReq_misses::total 9841 # number of UpgradeReq misses 73system.l2c.SCUpgradeReq_misses::0 791 # number of SCUpgradeReq misses 74system.l2c.SCUpgradeReq_misses::1 531 # number of SCUpgradeReq misses 75system.l2c.SCUpgradeReq_misses::total 1322 # number of SCUpgradeReq misses 76system.l2c.ReadExReq_misses::0 99048 # number of ReadExReq misses 77system.l2c.ReadExReq_misses::1 48785 # number of ReadExReq misses 78system.l2c.ReadExReq_misses::total 147833 # number of ReadExReq misses 79system.l2c.demand_misses::0 118723 # number of demand (read+write) misses 80system.l2c.demand_misses::1 64009 # number of demand (read+write) misses 81system.l2c.demand_misses::2 52 # number of demand (read+write) misses 82system.l2c.demand_misses::total 182784 # number of demand (read+write) misses 83system.l2c.overall_misses::0 118723 # number of overall misses 84system.l2c.overall_misses::1 64009 # number of overall misses 85system.l2c.overall_misses::2 52 # number of overall misses 86system.l2c.overall_misses::total 182784 # number of overall misses 87system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles 88system.l2c.overall_miss_latency 0 # number of overall miss cycles 89system.l2c.ReadReq_accesses::0 725865 # number of ReadReq accesses(hits+misses) 90system.l2c.ReadReq_accesses::1 515039 # number of ReadReq accesses(hits+misses) 91system.l2c.ReadReq_accesses::2 12972 # number of ReadReq accesses(hits+misses) 92system.l2c.ReadReq_accesses::total 1253876 # number of ReadReq accesses(hits+misses) 93system.l2c.Writeback_accesses::0 580461 # number of Writeback accesses(hits+misses) 94system.l2c.Writeback_accesses::total 580461 # number of Writeback accesses(hits+misses) 95system.l2c.UpgradeReq_accesses::0 7125 # number of UpgradeReq accesses(hits+misses) 96system.l2c.UpgradeReq_accesses::1 4015 # number of UpgradeReq accesses(hits+misses) 97system.l2c.UpgradeReq_accesses::total 11140 # number of UpgradeReq accesses(hits+misses) 98system.l2c.SCUpgradeReq_accesses::0 938 # number of SCUpgradeReq accesses(hits+misses) 99system.l2c.SCUpgradeReq_accesses::1 733 # number of SCUpgradeReq accesses(hits+misses) 100system.l2c.SCUpgradeReq_accesses::total 1671 # number of SCUpgradeReq accesses(hits+misses) 101system.l2c.ReadExReq_accesses::0 163879 # number of ReadExReq accesses(hits+misses) 102system.l2c.ReadExReq_accesses::1 86582 # number of ReadExReq accesses(hits+misses) 103system.l2c.ReadExReq_accesses::total 250461 # number of ReadExReq accesses(hits+misses) 104system.l2c.demand_accesses::0 889744 # number of demand (read+write) accesses 105system.l2c.demand_accesses::1 601621 # number of demand (read+write) accesses 106system.l2c.demand_accesses::2 12972 # number of demand (read+write) accesses 107system.l2c.demand_accesses::total 1504337 # number of demand (read+write) accesses 108system.l2c.overall_accesses::0 889744 # number of overall (read+write) accesses 109system.l2c.overall_accesses::1 601621 # number of overall (read+write) accesses 110system.l2c.overall_accesses::2 12972 # number of overall (read+write) accesses 111system.l2c.overall_accesses::total 1504337 # number of overall (read+write) accesses 112system.l2c.ReadReq_miss_rate::0 0.027106 # miss rate for ReadReq accesses 113system.l2c.ReadReq_miss_rate::1 0.029559 # miss rate for ReadReq accesses 114system.l2c.ReadReq_miss_rate::2 0.004009 # miss rate for ReadReq accesses 115system.l2c.ReadReq_miss_rate::total 0.060673 # miss rate for ReadReq accesses 116system.l2c.UpgradeReq_miss_rate::0 0.891088 # miss rate for UpgradeReq accesses 117system.l2c.UpgradeReq_miss_rate::1 0.869738 # miss rate for UpgradeReq accesses 118system.l2c.SCUpgradeReq_miss_rate::0 0.843284 # miss rate for SCUpgradeReq accesses 119system.l2c.SCUpgradeReq_miss_rate::1 0.724420 # miss rate for SCUpgradeReq accesses 120system.l2c.ReadExReq_miss_rate::0 0.604397 # miss rate for ReadExReq accesses 121system.l2c.ReadExReq_miss_rate::1 0.563454 # miss rate for ReadExReq accesses 122system.l2c.demand_miss_rate::0 0.133435 # miss rate for demand accesses 123system.l2c.demand_miss_rate::1 0.106394 # miss rate for demand accesses 124system.l2c.demand_miss_rate::2 0.004009 # miss rate for demand accesses 125system.l2c.demand_miss_rate::total 0.243838 # miss rate for demand accesses 126system.l2c.overall_miss_rate::0 0.133435 # miss rate for overall accesses 127system.l2c.overall_miss_rate::1 0.106394 # miss rate for overall accesses 128system.l2c.overall_miss_rate::2 0.004009 # miss rate for overall accesses 129system.l2c.overall_miss_rate::total 0.243838 # miss rate for overall accesses 130system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency 131system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency 132system.l2c.demand_avg_miss_latency::2 0 # average overall miss latency 133system.l2c.demand_avg_miss_latency::total 0 # average overall miss latency 134system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency 135system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency 136system.l2c.overall_avg_miss_latency::2 0 # average overall miss latency 137system.l2c.overall_avg_miss_latency::total 0 # average overall miss latency 138system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 139system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 140system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 141system.l2c.blocked::no_targets 0 # number of cycles access was blocked 142system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 143system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 144system.l2c.fast_writes 0 # number of fast writes performed 145system.l2c.cache_copies 0 # number of cache copies performed 146system.l2c.writebacks 111818 # number of writebacks 147system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 148system.l2c.overall_mshr_hits 0 # number of overall MSHR hits 149system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 150system.l2c.overall_mshr_misses 0 # number of overall MSHR misses 151system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 152system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 153system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 154system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 155system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses 156system.l2c.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses 157system.l2c.demand_mshr_miss_rate::2 0 # mshr miss rate for demand accesses 158system.l2c.demand_mshr_miss_rate::total 0 # mshr miss rate for demand accesses 159system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses 160system.l2c.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses 161system.l2c.overall_mshr_miss_rate::2 0 # mshr miss rate for overall accesses 162system.l2c.overall_mshr_miss_rate::total 0 # mshr miss rate for overall accesses 163system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 164system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 165system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 166system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated 167system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 168system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 169system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 170system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 171system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 172system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 173system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 174system.cf0.dma_write_txs 0 # Number of DMA write transactions. 175system.cpu0.dtb.inst_hits 0 # ITB inst hits 176system.cpu0.dtb.inst_misses 0 # ITB inst misses 177system.cpu0.dtb.read_hits 9339288 # DTB read hits 178system.cpu0.dtb.read_misses 5153 # DTB read misses 179system.cpu0.dtb.write_hits 6907876 # DTB write hits 180system.cpu0.dtb.write_misses 1048 # DTB write misses 181system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 182system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 183system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 184system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 185system.cpu0.dtb.flush_entries 2247 # Number of entries that have been flushed from TLB 186system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 187system.cpu0.dtb.prefetch_faults 150 # Number of TLB faults due to prefetch 188system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 189system.cpu0.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions 190system.cpu0.dtb.read_accesses 9344441 # DTB read accesses 191system.cpu0.dtb.write_accesses 6908924 # DTB write accesses 192system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 193system.cpu0.dtb.hits 16247164 # DTB hits 194system.cpu0.dtb.misses 6201 # DTB misses 195system.cpu0.dtb.accesses 16253365 # DTB accesses 196system.cpu0.itb.inst_hits 34822552 # ITB inst hits 197system.cpu0.itb.inst_misses 2978 # ITB inst misses 198system.cpu0.itb.read_hits 0 # DTB read hits 199system.cpu0.itb.read_misses 0 # DTB read misses 200system.cpu0.itb.write_hits 0 # DTB write hits 201system.cpu0.itb.write_misses 0 # DTB write misses 202system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 203system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 204system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 205system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 206system.cpu0.itb.flush_entries 1462 # Number of entries that have been flushed from TLB 207system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 208system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 209system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 210system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 211system.cpu0.itb.read_accesses 0 # DTB read accesses 212system.cpu0.itb.write_accesses 0 # DTB write accesses 213system.cpu0.itb.inst_accesses 34825530 # ITB inst accesses 214system.cpu0.itb.hits 34822552 # DTB hits 215system.cpu0.itb.misses 2978 # DTB misses 216system.cpu0.itb.accesses 34825530 # DTB accesses 217system.cpu0.numCycles 4823340800 # number of cpu cycles simulated 218system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 219system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 220system.cpu0.num_insts 44975797 # Number of instructions executed 221system.cpu0.num_int_alu_accesses 39858123 # Number of integer alu accesses 222system.cpu0.num_fp_alu_accesses 4945 # Number of float alu accesses 223system.cpu0.num_func_calls 1311755 # number of times a function call or return occured 224system.cpu0.num_conditional_control_insts 4494669 # number of instructions that are conditional controls 225system.cpu0.num_int_insts 39858123 # number of integer instructions 226system.cpu0.num_fp_insts 4945 # number of float instructions 227system.cpu0.num_int_register_reads 202125744 # number of times the integer registers were read 228system.cpu0.num_int_register_writes 42204131 # number of times the integer registers were written 229system.cpu0.num_fp_register_reads 3641 # number of times the floating registers were read 230system.cpu0.num_fp_register_writes 1308 # number of times the floating registers were written 231system.cpu0.num_mem_refs 17030946 # number of memory refs 232system.cpu0.num_load_insts 9786549 # Number of load instructions 233system.cpu0.num_store_insts 7244397 # Number of store instructions 234system.cpu0.num_idle_cycles 4777543068.852608 # Number of idle cycles 235system.cpu0.num_busy_cycles 45797731.147393 # Number of busy cycles 236system.cpu0.not_idle_fraction 0.009495 # Percentage of non-idle cycles 237system.cpu0.idle_fraction 0.990505 # Percentage of idle cycles 238system.cpu0.kern.inst.arm 0 # number of arm instructions executed 239system.cpu0.kern.inst.quiesce 59311 # number of quiesce instructions executed 240system.cpu0.icache.replacements 504460 # number of replacements 241system.cpu0.icache.tagsinuse 511.627588 # Cycle average of tags in use 242system.cpu0.icache.total_refs 34319155 # Total number of references to valid blocks. 243system.cpu0.icache.sampled_refs 504972 # Sample count of references to valid blocks. 244system.cpu0.icache.avg_refs 67.962491 # Average number of references to valid blocks. 245system.cpu0.icache.warmup_cycle 64519524000 # Cycle when the warmup percentage was hit. 246system.cpu0.icache.occ_blocks::0 511.627588 # Average occupied blocks per context 247system.cpu0.icache.occ_percent::0 0.999273 # Average percentage of cache occupancy 248system.cpu0.icache.ReadReq_hits::0 34319155 # number of ReadReq hits 249system.cpu0.icache.ReadReq_hits::total 34319155 # number of ReadReq hits 250system.cpu0.icache.demand_hits::0 34319155 # number of demand (read+write) hits 251system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits 252system.cpu0.icache.demand_hits::total 34319155 # number of demand (read+write) hits 253system.cpu0.icache.overall_hits::0 34319155 # number of overall hits 254system.cpu0.icache.overall_hits::1 0 # number of overall hits 255system.cpu0.icache.overall_hits::total 34319155 # number of overall hits 256system.cpu0.icache.ReadReq_misses::0 504973 # number of ReadReq misses 257system.cpu0.icache.ReadReq_misses::total 504973 # number of ReadReq misses 258system.cpu0.icache.demand_misses::0 504973 # number of demand (read+write) misses 259system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses 260system.cpu0.icache.demand_misses::total 504973 # number of demand (read+write) misses 261system.cpu0.icache.overall_misses::0 504973 # number of overall misses 262system.cpu0.icache.overall_misses::1 0 # number of overall misses 263system.cpu0.icache.overall_misses::total 504973 # number of overall misses 264system.cpu0.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles 265system.cpu0.icache.overall_miss_latency 0 # number of overall miss cycles 266system.cpu0.icache.ReadReq_accesses::0 34824128 # number of ReadReq accesses(hits+misses) 267system.cpu0.icache.ReadReq_accesses::total 34824128 # number of ReadReq accesses(hits+misses) 268system.cpu0.icache.demand_accesses::0 34824128 # number of demand (read+write) accesses 269system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses 270system.cpu0.icache.demand_accesses::total 34824128 # number of demand (read+write) accesses 271system.cpu0.icache.overall_accesses::0 34824128 # number of overall (read+write) accesses 272system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses 273system.cpu0.icache.overall_accesses::total 34824128 # number of overall (read+write) accesses 274system.cpu0.icache.ReadReq_miss_rate::0 0.014501 # miss rate for ReadReq accesses 275system.cpu0.icache.demand_miss_rate::0 0.014501 # miss rate for demand accesses 276system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses 277system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses 278system.cpu0.icache.overall_miss_rate::0 0.014501 # miss rate for overall accesses 279system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses 280system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses 281system.cpu0.icache.demand_avg_miss_latency::0 0 # average overall miss latency 282system.cpu0.icache.demand_avg_miss_latency::1 no_value # average overall miss latency 283system.cpu0.icache.demand_avg_miss_latency::total no_value # average overall miss latency 284system.cpu0.icache.overall_avg_miss_latency::0 0 # average overall miss latency 285system.cpu0.icache.overall_avg_miss_latency::1 no_value # average overall miss latency 286system.cpu0.icache.overall_avg_miss_latency::total no_value # average overall miss latency 287system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 288system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 289system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 290system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 291system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 292system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 293system.cpu0.icache.fast_writes 0 # number of fast writes performed 294system.cpu0.icache.cache_copies 0 # number of cache copies performed 295system.cpu0.icache.writebacks 24728 # number of writebacks 296system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 297system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits 298system.cpu0.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 299system.cpu0.icache.overall_mshr_misses 0 # number of overall MSHR misses 300system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 301system.cpu0.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 302system.cpu0.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 303system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 304system.cpu0.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses 305system.cpu0.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses 306system.cpu0.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses 307system.cpu0.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses 308system.cpu0.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses 309system.cpu0.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses 310system.cpu0.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 311system.cpu0.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 312system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 313system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated 314system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 315system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 316system.cpu0.dcache.replacements 380107 # number of replacements 317system.cpu0.dcache.tagsinuse 479.716402 # Cycle average of tags in use 318system.cpu0.dcache.total_refs 14708286 # Total number of references to valid blocks. 319system.cpu0.dcache.sampled_refs 380619 # Sample count of references to valid blocks. 320system.cpu0.dcache.avg_refs 38.643068 # Average number of references to valid blocks. 321system.cpu0.dcache.warmup_cycle 22115000 # Cycle when the warmup percentage was hit. 322system.cpu0.dcache.occ_blocks::0 479.716402 # Average occupied blocks per context 323system.cpu0.dcache.occ_percent::0 0.936946 # Average percentage of cache occupancy 324system.cpu0.dcache.ReadReq_hits::0 7803296 # number of ReadReq hits 325system.cpu0.dcache.ReadReq_hits::total 7803296 # number of ReadReq hits 326system.cpu0.dcache.WriteReq_hits::0 6534059 # number of WriteReq hits 327system.cpu0.dcache.WriteReq_hits::total 6534059 # number of WriteReq hits 328system.cpu0.dcache.LoadLockedReq_hits::0 172314 # number of LoadLockedReq hits 329system.cpu0.dcache.LoadLockedReq_hits::total 172314 # number of LoadLockedReq hits 330system.cpu0.dcache.StoreCondReq_hits::0 174866 # number of StoreCondReq hits 331system.cpu0.dcache.StoreCondReq_hits::total 174866 # number of StoreCondReq hits 332system.cpu0.dcache.demand_hits::0 14337355 # number of demand (read+write) hits 333system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits 334system.cpu0.dcache.demand_hits::total 14337355 # number of demand (read+write) hits 335system.cpu0.dcache.overall_hits::0 14337355 # number of overall hits 336system.cpu0.dcache.overall_hits::1 0 # number of overall hits 337system.cpu0.dcache.overall_hits::total 14337355 # number of overall hits 338system.cpu0.dcache.ReadReq_misses::0 237350 # number of ReadReq misses 339system.cpu0.dcache.ReadReq_misses::total 237350 # number of ReadReq misses 340system.cpu0.dcache.WriteReq_misses::0 183580 # number of WriteReq misses 341system.cpu0.dcache.WriteReq_misses::total 183580 # number of WriteReq misses 342system.cpu0.dcache.LoadLockedReq_misses::0 9878 # number of LoadLockedReq misses 343system.cpu0.dcache.LoadLockedReq_misses::total 9878 # number of LoadLockedReq misses 344system.cpu0.dcache.StoreCondReq_misses::0 7293 # number of StoreCondReq misses 345system.cpu0.dcache.StoreCondReq_misses::total 7293 # number of StoreCondReq misses 346system.cpu0.dcache.demand_misses::0 420930 # number of demand (read+write) misses 347system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses 348system.cpu0.dcache.demand_misses::total 420930 # number of demand (read+write) misses 349system.cpu0.dcache.overall_misses::0 420930 # number of overall misses 350system.cpu0.dcache.overall_misses::1 0 # number of overall misses 351system.cpu0.dcache.overall_misses::total 420930 # number of overall misses 352system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles 353system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles 354system.cpu0.dcache.ReadReq_accesses::0 8040646 # number of ReadReq accesses(hits+misses) 355system.cpu0.dcache.ReadReq_accesses::total 8040646 # number of ReadReq accesses(hits+misses) 356system.cpu0.dcache.WriteReq_accesses::0 6717639 # number of WriteReq accesses(hits+misses) 357system.cpu0.dcache.WriteReq_accesses::total 6717639 # number of WriteReq accesses(hits+misses) 358system.cpu0.dcache.LoadLockedReq_accesses::0 182192 # number of LoadLockedReq accesses(hits+misses) 359system.cpu0.dcache.LoadLockedReq_accesses::total 182192 # number of LoadLockedReq accesses(hits+misses) 360system.cpu0.dcache.StoreCondReq_accesses::0 182159 # number of StoreCondReq accesses(hits+misses) 361system.cpu0.dcache.StoreCondReq_accesses::total 182159 # number of StoreCondReq accesses(hits+misses) 362system.cpu0.dcache.demand_accesses::0 14758285 # number of demand (read+write) accesses 363system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses 364system.cpu0.dcache.demand_accesses::total 14758285 # number of demand (read+write) accesses 365system.cpu0.dcache.overall_accesses::0 14758285 # number of overall (read+write) accesses 366system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses 367system.cpu0.dcache.overall_accesses::total 14758285 # number of overall (read+write) accesses 368system.cpu0.dcache.ReadReq_miss_rate::0 0.029519 # miss rate for ReadReq accesses 369system.cpu0.dcache.WriteReq_miss_rate::0 0.027328 # miss rate for WriteReq accesses 370system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.054218 # miss rate for LoadLockedReq accesses 371system.cpu0.dcache.StoreCondReq_miss_rate::0 0.040036 # miss rate for StoreCondReq accesses 372system.cpu0.dcache.demand_miss_rate::0 0.028522 # miss rate for demand accesses 373system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses 374system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses 375system.cpu0.dcache.overall_miss_rate::0 0.028522 # miss rate for overall accesses 376system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses 377system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses 378system.cpu0.dcache.demand_avg_miss_latency::0 0 # average overall miss latency 379system.cpu0.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency 380system.cpu0.dcache.demand_avg_miss_latency::total no_value # average overall miss latency 381system.cpu0.dcache.overall_avg_miss_latency::0 0 # average overall miss latency 382system.cpu0.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency 383system.cpu0.dcache.overall_avg_miss_latency::total no_value # average overall miss latency 384system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 385system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 386system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 387system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 388system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 389system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 390system.cpu0.dcache.fast_writes 0 # number of fast writes performed 391system.cpu0.dcache.cache_copies 0 # number of cache copies performed 392system.cpu0.dcache.writebacks 339627 # number of writebacks 393system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 394system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits 395system.cpu0.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 396system.cpu0.dcache.overall_mshr_misses 0 # number of overall MSHR misses 397system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 398system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 399system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 400system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 401system.cpu0.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses 402system.cpu0.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses 403system.cpu0.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses 404system.cpu0.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses 405system.cpu0.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses 406system.cpu0.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses 407system.cpu0.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 408system.cpu0.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 409system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 410system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 411system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 412system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 413system.cpu1.dtb.inst_hits 0 # ITB inst hits 414system.cpu1.dtb.inst_misses 0 # ITB inst misses 415system.cpu1.dtb.read_hits 6258230 # DTB read hits 416system.cpu1.dtb.read_misses 2159 # DTB read misses 417system.cpu1.dtb.write_hits 4713962 # DTB write hits 418system.cpu1.dtb.write_misses 1181 # DTB write misses 419system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 420system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 421system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 422system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 423system.cpu1.dtb.flush_entries 1498 # Number of entries that have been flushed from TLB 424system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 425system.cpu1.dtb.prefetch_faults 92 # Number of TLB faults due to prefetch 426system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 427system.cpu1.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions 428system.cpu1.dtb.read_accesses 6260389 # DTB read accesses 429system.cpu1.dtb.write_accesses 4715143 # DTB write accesses 430system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 431system.cpu1.dtb.hits 10972192 # DTB hits 432system.cpu1.dtb.misses 3340 # DTB misses 433system.cpu1.dtb.accesses 10975532 # DTB accesses 434system.cpu1.itb.inst_hits 27739434 # ITB inst hits 435system.cpu1.itb.inst_misses 1388 # ITB inst misses 436system.cpu1.itb.read_hits 0 # DTB read hits 437system.cpu1.itb.read_misses 0 # DTB read misses 438system.cpu1.itb.write_hits 0 # DTB write hits 439system.cpu1.itb.write_misses 0 # DTB write misses 440system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 441system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 442system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 443system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 444system.cpu1.itb.flush_entries 1342 # Number of entries that have been flushed from TLB 445system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 446system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 447system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 448system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 449system.cpu1.itb.read_accesses 0 # DTB read accesses 450system.cpu1.itb.write_accesses 0 # DTB write accesses 451system.cpu1.itb.inst_accesses 27740822 # ITB inst accesses 452system.cpu1.itb.hits 27739434 # DTB hits 453system.cpu1.itb.misses 1388 # DTB misses 454system.cpu1.itb.accesses 27740822 # DTB accesses 455system.cpu1.numCycles 4822838236 # number of cpu cycles simulated 456system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 457system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 458system.cpu1.num_insts 34587691 # Number of instructions executed 459system.cpu1.num_int_alu_accesses 30998246 # Number of integer alu accesses 460system.cpu1.num_fp_alu_accesses 5772 # Number of float alu accesses 461system.cpu1.num_func_calls 758024 # number of times a function call or return occured 462system.cpu1.num_conditional_control_insts 3375080 # number of instructions that are conditional controls 463system.cpu1.num_int_insts 30998246 # number of integer instructions 464system.cpu1.num_fp_insts 5772 # number of float instructions 465system.cpu1.num_int_register_reads 156835040 # number of times the integer registers were read 466system.cpu1.num_int_register_writes 33469179 # number of times the integer registers were written 467system.cpu1.num_fp_register_reads 3980 # number of times the floating registers were read 468system.cpu1.num_fp_register_writes 1792 # number of times the floating registers were written 469system.cpu1.num_mem_refs 11415835 # number of memory refs 470system.cpu1.num_load_insts 6478994 # Number of load instructions 471system.cpu1.num_store_insts 4936841 # Number of store instructions 472system.cpu1.num_idle_cycles 4787960178.177661 # Number of idle cycles 473system.cpu1.num_busy_cycles 34878057.822339 # Number of busy cycles 474system.cpu1.not_idle_fraction 0.007232 # Percentage of non-idle cycles 475system.cpu1.idle_fraction 0.992768 # Percentage of idle cycles 476system.cpu1.kern.inst.arm 0 # number of arm instructions executed 477system.cpu1.kern.inst.quiesce 33011 # number of quiesce instructions executed 478system.cpu1.icache.replacements 374406 # number of replacements 479system.cpu1.icache.tagsinuse 498.143079 # Cycle average of tags in use 480system.cpu1.icache.total_refs 27365572 # Total number of references to valid blocks. 481system.cpu1.icache.sampled_refs 374918 # Sample count of references to valid blocks. 482system.cpu1.icache.avg_refs 72.990819 # Average number of references to valid blocks. 483system.cpu1.icache.warmup_cycle 69956143000 # Cycle when the warmup percentage was hit. 484system.cpu1.icache.occ_blocks::0 498.143079 # Average occupied blocks per context 485system.cpu1.icache.occ_percent::0 0.972936 # Average percentage of cache occupancy 486system.cpu1.icache.ReadReq_hits::0 27365572 # number of ReadReq hits 487system.cpu1.icache.ReadReq_hits::total 27365572 # number of ReadReq hits 488system.cpu1.icache.demand_hits::0 27365572 # number of demand (read+write) hits 489system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits 490system.cpu1.icache.demand_hits::total 27365572 # number of demand (read+write) hits 491system.cpu1.icache.overall_hits::0 27365572 # number of overall hits 492system.cpu1.icache.overall_hits::1 0 # number of overall hits 493system.cpu1.icache.overall_hits::total 27365572 # number of overall hits 494system.cpu1.icache.ReadReq_misses::0 374920 # number of ReadReq misses 495system.cpu1.icache.ReadReq_misses::total 374920 # number of ReadReq misses 496system.cpu1.icache.demand_misses::0 374920 # number of demand (read+write) misses 497system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses 498system.cpu1.icache.demand_misses::total 374920 # number of demand (read+write) misses 499system.cpu1.icache.overall_misses::0 374920 # number of overall misses 500system.cpu1.icache.overall_misses::1 0 # number of overall misses 501system.cpu1.icache.overall_misses::total 374920 # number of overall misses 502system.cpu1.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles 503system.cpu1.icache.overall_miss_latency 0 # number of overall miss cycles 504system.cpu1.icache.ReadReq_accesses::0 27740492 # number of ReadReq accesses(hits+misses) 505system.cpu1.icache.ReadReq_accesses::total 27740492 # number of ReadReq accesses(hits+misses) 506system.cpu1.icache.demand_accesses::0 27740492 # number of demand (read+write) accesses 507system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses 508system.cpu1.icache.demand_accesses::total 27740492 # number of demand (read+write) accesses 509system.cpu1.icache.overall_accesses::0 27740492 # number of overall (read+write) accesses 510system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses 511system.cpu1.icache.overall_accesses::total 27740492 # number of overall (read+write) accesses 512system.cpu1.icache.ReadReq_miss_rate::0 0.013515 # miss rate for ReadReq accesses 513system.cpu1.icache.demand_miss_rate::0 0.013515 # miss rate for demand accesses 514system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses 515system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses 516system.cpu1.icache.overall_miss_rate::0 0.013515 # miss rate for overall accesses 517system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses 518system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses 519system.cpu1.icache.demand_avg_miss_latency::0 0 # average overall miss latency 520system.cpu1.icache.demand_avg_miss_latency::1 no_value # average overall miss latency 521system.cpu1.icache.demand_avg_miss_latency::total no_value # average overall miss latency 522system.cpu1.icache.overall_avg_miss_latency::0 0 # average overall miss latency 523system.cpu1.icache.overall_avg_miss_latency::1 no_value # average overall miss latency 524system.cpu1.icache.overall_avg_miss_latency::total no_value # average overall miss latency 525system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 526system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 527system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 528system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 529system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 530system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 531system.cpu1.icache.fast_writes 0 # number of fast writes performed 532system.cpu1.icache.cache_copies 0 # number of cache copies performed 533system.cpu1.icache.writebacks 13905 # number of writebacks 534system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 535system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits 536system.cpu1.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 537system.cpu1.icache.overall_mshr_misses 0 # number of overall MSHR misses 538system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 539system.cpu1.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 540system.cpu1.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 541system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 542system.cpu1.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses 543system.cpu1.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses 544system.cpu1.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses 545system.cpu1.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses 546system.cpu1.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses 547system.cpu1.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses 548system.cpu1.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 549system.cpu1.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 550system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 551system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated 552system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 553system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 554system.cpu1.dcache.replacements 247434 # number of replacements 555system.cpu1.dcache.tagsinuse 444.903488 # Cycle average of tags in use 556system.cpu1.dcache.total_refs 9876826 # Total number of references to valid blocks. 557system.cpu1.dcache.sampled_refs 247805 # Sample count of references to valid blocks. 558system.cpu1.dcache.avg_refs 39.857251 # Average number of references to valid blocks. 559system.cpu1.dcache.warmup_cycle 69253206000 # Cycle when the warmup percentage was hit. 560system.cpu1.dcache.occ_blocks::0 444.903488 # Average occupied blocks per context 561system.cpu1.dcache.occ_percent::0 0.868952 # Average percentage of cache occupancy 562system.cpu1.dcache.ReadReq_hits::0 5955973 # number of ReadReq hits 563system.cpu1.dcache.ReadReq_hits::total 5955973 # number of ReadReq hits 564system.cpu1.dcache.WriteReq_hits::0 3777038 # number of WriteReq hits 565system.cpu1.dcache.WriteReq_hits::total 3777038 # number of WriteReq hits 566system.cpu1.dcache.LoadLockedReq_hits::0 59593 # number of LoadLockedReq hits 567system.cpu1.dcache.LoadLockedReq_hits::total 59593 # number of LoadLockedReq hits 568system.cpu1.dcache.StoreCondReq_hits::0 60090 # number of StoreCondReq hits 569system.cpu1.dcache.StoreCondReq_hits::total 60090 # number of StoreCondReq hits 570system.cpu1.dcache.demand_hits::0 9733011 # number of demand (read+write) hits 571system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits 572system.cpu1.dcache.demand_hits::total 9733011 # number of demand (read+write) hits 573system.cpu1.dcache.overall_hits::0 9733011 # number of overall hits 574system.cpu1.dcache.overall_hits::1 0 # number of overall hits 575system.cpu1.dcache.overall_hits::total 9733011 # number of overall hits 576system.cpu1.dcache.ReadReq_misses::0 165799 # number of ReadReq misses 577system.cpu1.dcache.ReadReq_misses::total 165799 # number of ReadReq misses 578system.cpu1.dcache.WriteReq_misses::0 111467 # number of WriteReq misses 579system.cpu1.dcache.WriteReq_misses::total 111467 # number of WriteReq misses 580system.cpu1.dcache.LoadLockedReq_misses::0 10725 # number of LoadLockedReq misses 581system.cpu1.dcache.LoadLockedReq_misses::total 10725 # number of LoadLockedReq misses 582system.cpu1.dcache.StoreCondReq_misses::0 10198 # number of StoreCondReq misses 583system.cpu1.dcache.StoreCondReq_misses::total 10198 # number of StoreCondReq misses 584system.cpu1.dcache.demand_misses::0 277266 # number of demand (read+write) misses 585system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses 586system.cpu1.dcache.demand_misses::total 277266 # number of demand (read+write) misses 587system.cpu1.dcache.overall_misses::0 277266 # number of overall misses 588system.cpu1.dcache.overall_misses::1 0 # number of overall misses 589system.cpu1.dcache.overall_misses::total 277266 # number of overall misses 590system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles 591system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles 592system.cpu1.dcache.ReadReq_accesses::0 6121772 # number of ReadReq accesses(hits+misses) 593system.cpu1.dcache.ReadReq_accesses::total 6121772 # number of ReadReq accesses(hits+misses) 594system.cpu1.dcache.WriteReq_accesses::0 3888505 # number of WriteReq accesses(hits+misses) 595system.cpu1.dcache.WriteReq_accesses::total 3888505 # number of WriteReq accesses(hits+misses) 596system.cpu1.dcache.LoadLockedReq_accesses::0 70318 # number of LoadLockedReq accesses(hits+misses) 597system.cpu1.dcache.LoadLockedReq_accesses::total 70318 # number of LoadLockedReq accesses(hits+misses) 598system.cpu1.dcache.StoreCondReq_accesses::0 70288 # number of StoreCondReq accesses(hits+misses) 599system.cpu1.dcache.StoreCondReq_accesses::total 70288 # number of StoreCondReq accesses(hits+misses) 600system.cpu1.dcache.demand_accesses::0 10010277 # number of demand (read+write) accesses 601system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses 602system.cpu1.dcache.demand_accesses::total 10010277 # number of demand (read+write) accesses 603system.cpu1.dcache.overall_accesses::0 10010277 # number of overall (read+write) accesses 604system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses 605system.cpu1.dcache.overall_accesses::total 10010277 # number of overall (read+write) accesses 606system.cpu1.dcache.ReadReq_miss_rate::0 0.027083 # miss rate for ReadReq accesses 607system.cpu1.dcache.WriteReq_miss_rate::0 0.028666 # miss rate for WriteReq accesses 608system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.152521 # miss rate for LoadLockedReq accesses 609system.cpu1.dcache.StoreCondReq_miss_rate::0 0.145089 # miss rate for StoreCondReq accesses 610system.cpu1.dcache.demand_miss_rate::0 0.027698 # miss rate for demand accesses 611system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses 612system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses 613system.cpu1.dcache.overall_miss_rate::0 0.027698 # miss rate for overall accesses 614system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses 615system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses 616system.cpu1.dcache.demand_avg_miss_latency::0 0 # average overall miss latency 617system.cpu1.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency 618system.cpu1.dcache.demand_avg_miss_latency::total no_value # average overall miss latency 619system.cpu1.dcache.overall_avg_miss_latency::0 0 # average overall miss latency 620system.cpu1.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency 621system.cpu1.dcache.overall_avg_miss_latency::total no_value # average overall miss latency 622system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 623system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 624system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 625system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 626system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 627system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 628system.cpu1.dcache.fast_writes 0 # number of fast writes performed 629system.cpu1.dcache.cache_copies 0 # number of cache copies performed 630system.cpu1.dcache.writebacks 202201 # number of writebacks 631system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 632system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits 633system.cpu1.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 634system.cpu1.dcache.overall_mshr_misses 0 # number of overall MSHR misses 635system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 636system.cpu1.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 637system.cpu1.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 638system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 639system.cpu1.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses 640system.cpu1.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses 641system.cpu1.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses 642system.cpu1.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses 643system.cpu1.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses 644system.cpu1.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses 645system.cpu1.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 646system.cpu1.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 647system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 648system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 649system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 650system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 651system.iocache.replacements 0 # number of replacements 652system.iocache.tagsinuse 0 # Cycle average of tags in use 653system.iocache.total_refs 0 # Total number of references to valid blocks. 654system.iocache.sampled_refs 0 # Sample count of references to valid blocks. 655system.iocache.avg_refs no_value # Average number of references to valid blocks. 656system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 657system.iocache.demand_hits::0 0 # number of demand (read+write) hits 658system.iocache.demand_hits::1 0 # number of demand (read+write) hits 659system.iocache.demand_hits::total 0 # number of demand (read+write) hits 660system.iocache.overall_hits::0 0 # number of overall hits 661system.iocache.overall_hits::1 0 # number of overall hits 662system.iocache.overall_hits::total 0 # number of overall hits 663system.iocache.demand_misses::0 0 # number of demand (read+write) misses 664system.iocache.demand_misses::1 0 # number of demand (read+write) misses 665system.iocache.demand_misses::total 0 # number of demand (read+write) misses 666system.iocache.overall_misses::0 0 # number of overall misses 667system.iocache.overall_misses::1 0 # number of overall misses 668system.iocache.overall_misses::total 0 # number of overall misses 669system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles 670system.iocache.overall_miss_latency 0 # number of overall miss cycles 671system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses 672system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses 673system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses 674system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses 675system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses 676system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses 677system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses 678system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses 679system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses 680system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses 681system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses 682system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses 683system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency 684system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency 685system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency 686system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency 687system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency 688system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency 689system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 690system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 691system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 692system.iocache.blocked::no_targets 0 # number of cycles access was blocked 693system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 694system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 695system.iocache.fast_writes 0 # number of fast writes performed 696system.iocache.cache_copies 0 # number of cache copies performed 697system.iocache.writebacks 0 # number of writebacks 698system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 699system.iocache.overall_mshr_hits 0 # number of overall MSHR hits 700system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 701system.iocache.overall_mshr_misses 0 # number of overall MSHR misses 702system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 703system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 704system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 705system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 706system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses 707system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses 708system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses 709system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses 710system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses 711system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses 712system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 713system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 714system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 715system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated 716system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 717system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 718 719---------- End Simulation Statistics ---------- 720