stats.txt revision 11589:af2f7fef4875
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.802883 # Number of seconds simulated 4sim_ticks 2802883274000 # Number of ticks simulated 5final_tick 2802883274000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 992891 # Simulator instruction rate (inst/s) 8host_op_rate 1209822 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 18955432442 # Simulator tick rate (ticks/s) 10host_mem_usage 590980 # Number of bytes of host memory used 11host_seconds 147.87 # Real time elapsed on the host 12sim_insts 146815798 # Number of instructions simulated 13sim_ops 178892721 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 1106276 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 9415076 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.inst 154452 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.data 1081616 # Number of bytes read from this memory 24system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 25system.physmem.bytes_read::total 11759020 # Number of bytes read from this memory 26system.physmem.bytes_inst_read::cpu0.inst 1106276 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::cpu1.inst 154452 # Number of instructions bytes read from this memory 28system.physmem.bytes_inst_read::total 1260728 # Number of instructions bytes read from this memory 29system.physmem.bytes_written::writebacks 8476800 # Number of bytes written to this memory 30system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory 31system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory 32system.physmem.bytes_written::total 8494364 # Number of bytes written to this memory 33system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu0.inst 25739 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.data 147630 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu1.inst 2568 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu1.data 16920 # Number of read requests responded to by this memory 40system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 41system.physmem.num_reads::total 192882 # Number of read requests responded to by this memory 42system.physmem.num_writes::writebacks 132450 # Number of write requests responded to by this memory 43system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory 44system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory 45system.physmem.num_writes::total 136841 # Number of write requests responded to by this memory 46system.physmem.bw_read::cpu0.dtb.walker 160 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::cpu0.itb.walker 46 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::cpu0.inst 394692 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu0.data 3359068 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu1.dtb.walker 23 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu1.inst 55105 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu1.data 385894 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::realview.ide 343 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::total 4195330 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_inst_read::cpu0.inst 394692 # Instruction read bandwidth from this memory (bytes/s) 56system.physmem.bw_inst_read::cpu1.inst 55105 # Instruction read bandwidth from this memory (bytes/s) 57system.physmem.bw_inst_read::total 449797 # Instruction read bandwidth from this memory (bytes/s) 58system.physmem.bw_write::writebacks 3024314 # Write bandwidth from this memory (bytes/s) 59system.physmem.bw_write::cpu0.data 6252 # Write bandwidth from this memory (bytes/s) 60system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) 61system.physmem.bw_write::total 3030581 # Write bandwidth from this memory (bytes/s) 62system.physmem.bw_total::writebacks 3024314 # Total bandwidth to/from this memory (bytes/s) 63system.physmem.bw_total::cpu0.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s) 64system.physmem.bw_total::cpu0.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::cpu0.inst 394692 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::cpu0.data 3365320 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu1.dtb.walker 23 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::cpu1.inst 55105 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::cpu1.data 385908 # Total bandwidth to/from this memory (bytes/s) 70system.physmem.bw_total::realview.ide 343 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::total 7225911 # Total bandwidth to/from this memory (bytes/s) 72system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 73system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 74system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 75system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 76system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 77system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 78system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 79system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 80system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 81system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 82system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) 83system.realview.nvmem.bw_read::cpu1.inst 17 # Total read bandwidth from this memory (bytes/s) 84system.realview.nvmem.bw_read::total 24 # Total read bandwidth from this memory (bytes/s) 85system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) 86system.realview.nvmem.bw_inst_read::cpu1.inst 17 # Instruction read bandwidth from this memory (bytes/s) 87system.realview.nvmem.bw_inst_read::total 24 # Instruction read bandwidth from this memory (bytes/s) 88system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) 89system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s) 90system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s) 91system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 92system.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 93system.bridge.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 94system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 95system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 96system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 97system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 98system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 99system.cf0.dma_write_txs 631 # Number of DMA write transactions. 100system.cpu_clk_domain.clock 500 # Clock period in ticks 101system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 102system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 103system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 104system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 105system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 106system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 107system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 108system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 109system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 110system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 111system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 112system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 113system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 114system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 115system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 116system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 117system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 118system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 119system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 120system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 121system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 122system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 123system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 124system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 125system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 126system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 127system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 128system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 129system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 130system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 131system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 132system.cpu0.dtb.walker.walks 7964 # Table walker walks requested 133system.cpu0.dtb.walker.walksShort 7964 # Table walker walks initiated with short descriptors 134system.cpu0.dtb.walker.walkWaitTime::samples 7964 # Table walker wait (enqueue to first request) latency 135system.cpu0.dtb.walker.walkWaitTime::0 7964 100.00% 100.00% # Table walker wait (enqueue to first request) latency 136system.cpu0.dtb.walker.walkWaitTime::total 7964 # Table walker wait (enqueue to first request) latency 137system.cpu0.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution 138system.cpu0.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution 139system.cpu0.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution 140system.cpu0.dtb.walker.walkPageSizes::4K 5079 77.31% 77.31% # Table walker page sizes translated 141system.cpu0.dtb.walker.walkPageSizes::1M 1491 22.69% 100.00% # Table walker page sizes translated 142system.cpu0.dtb.walker.walkPageSizes::total 6570 # Table walker page sizes translated 143system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7964 # Table walker requests started/completed, data/inst 144system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 145system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7964 # Table walker requests started/completed, data/inst 146system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6570 # Table walker requests started/completed, data/inst 147system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 148system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6570 # Table walker requests started/completed, data/inst 149system.cpu0.dtb.walker.walkRequestOrigin::total 14534 # Table walker requests started/completed, data/inst 150system.cpu0.dtb.inst_hits 0 # ITB inst hits 151system.cpu0.dtb.inst_misses 0 # ITB inst misses 152system.cpu0.dtb.read_hits 20338226 # DTB read hits 153system.cpu0.dtb.read_misses 6871 # DTB read misses 154system.cpu0.dtb.write_hits 16389726 # DTB write hits 155system.cpu0.dtb.write_misses 1093 # DTB write misses 156system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 157system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 158system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 159system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 160system.cpu0.dtb.flush_entries 3435 # Number of entries that have been flushed from TLB 161system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 162system.cpu0.dtb.prefetch_faults 1788 # Number of TLB faults due to prefetch 163system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 164system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions 165system.cpu0.dtb.read_accesses 20345097 # DTB read accesses 166system.cpu0.dtb.write_accesses 16390819 # DTB write accesses 167system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 168system.cpu0.dtb.hits 36727952 # DTB hits 169system.cpu0.dtb.misses 7964 # DTB misses 170system.cpu0.dtb.accesses 36735916 # DTB accesses 171system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 172system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 173system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 174system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 175system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 176system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 177system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 178system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 179system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 180system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 181system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 182system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 183system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 184system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 185system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 186system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 187system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 188system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 189system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 190system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 191system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 192system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 193system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 194system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 195system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 196system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 197system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 198system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 199system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 200system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 201system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 202system.cpu0.itb.walker.walks 3358 # Table walker walks requested 203system.cpu0.itb.walker.walksShort 3358 # Table walker walks initiated with short descriptors 204system.cpu0.itb.walker.walkWaitTime::samples 3358 # Table walker wait (enqueue to first request) latency 205system.cpu0.itb.walker.walkWaitTime::0 3358 100.00% 100.00% # Table walker wait (enqueue to first request) latency 206system.cpu0.itb.walker.walkWaitTime::total 3358 # Table walker wait (enqueue to first request) latency 207system.cpu0.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution 208system.cpu0.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution 209system.cpu0.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution 210system.cpu0.itb.walker.walkPageSizes::4K 2040 87.11% 87.11% # Table walker page sizes translated 211system.cpu0.itb.walker.walkPageSizes::1M 302 12.89% 100.00% # Table walker page sizes translated 212system.cpu0.itb.walker.walkPageSizes::total 2342 # Table walker page sizes translated 213system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 214system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3358 # Table walker requests started/completed, data/inst 215system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3358 # Table walker requests started/completed, data/inst 216system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 217system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2342 # Table walker requests started/completed, data/inst 218system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2342 # Table walker requests started/completed, data/inst 219system.cpu0.itb.walker.walkRequestOrigin::total 5700 # Table walker requests started/completed, data/inst 220system.cpu0.itb.inst_hits 97433318 # ITB inst hits 221system.cpu0.itb.inst_misses 3358 # ITB inst misses 222system.cpu0.itb.read_hits 0 # DTB read hits 223system.cpu0.itb.read_misses 0 # DTB read misses 224system.cpu0.itb.write_hits 0 # DTB write hits 225system.cpu0.itb.write_misses 0 # DTB write misses 226system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 227system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 228system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 229system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 230system.cpu0.itb.flush_entries 2096 # Number of entries that have been flushed from TLB 231system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 232system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 233system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 234system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 235system.cpu0.itb.read_accesses 0 # DTB read accesses 236system.cpu0.itb.write_accesses 0 # DTB write accesses 237system.cpu0.itb.inst_accesses 97436676 # ITB inst accesses 238system.cpu0.itb.hits 97433318 # DTB hits 239system.cpu0.itb.misses 3358 # DTB misses 240system.cpu0.itb.accesses 97436676 # DTB accesses 241system.cpu0.numPwrStateTransitions 3946 # Number of power state transitions 242system.cpu0.pwrStateClkGateDist::samples 1973 # Distribution of time spent in the clock gated state 243system.cpu0.pwrStateClkGateDist::mean 1390823508.162189 # Distribution of time spent in the clock gated state 244system.cpu0.pwrStateClkGateDist::stdev 23082851772.246098 # Distribution of time spent in the clock gated state 245system.cpu0.pwrStateClkGateDist::underflows 1157 58.64% 58.64% # Distribution of time spent in the clock gated state 246system.cpu0.pwrStateClkGateDist::1000-5e+10 810 41.05% 99.70% # Distribution of time spent in the clock gated state 247system.cpu0.pwrStateClkGateDist::5e+10-1e+11 1 0.05% 99.75% # Distribution of time spent in the clock gated state 248system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.80% # Distribution of time spent in the clock gated state 249system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.20% 100.00% # Distribution of time spent in the clock gated state 250system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 251system.cpu0.pwrStateClkGateDist::max_value 499983361388 # Distribution of time spent in the clock gated state 252system.cpu0.pwrStateClkGateDist::total 1973 # Distribution of time spent in the clock gated state 253system.cpu0.pwrStateResidencyTicks::ON 58788492396 # Cumulative time (in ticks) in various power states 254system.cpu0.pwrStateResidencyTicks::CLK_GATED 2744094781604 # Cumulative time (in ticks) in various power states 255system.cpu0.numCycles 5605768522 # number of cpu cycles simulated 256system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 257system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 258system.cpu0.kern.inst.arm 0 # number of arm instructions executed 259system.cpu0.kern.inst.quiesce 1973 # number of quiesce instructions executed 260system.cpu0.committedInsts 95420875 # Number of instructions committed 261system.cpu0.committedOps 115552929 # Number of ops (including micro ops) committed 262system.cpu0.num_int_alu_accesses 100755950 # Number of integer alu accesses 263system.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses 264system.cpu0.num_func_calls 8000037 # number of times a function call or return occured 265system.cpu0.num_conditional_control_insts 13203579 # number of instructions that are conditional controls 266system.cpu0.num_int_insts 100755950 # number of integer instructions 267system.cpu0.num_fp_insts 9755 # number of float instructions 268system.cpu0.num_int_register_reads 182434923 # number of times the integer registers were read 269system.cpu0.num_int_register_writes 69130439 # number of times the integer registers were written 270system.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read 271system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written 272system.cpu0.num_cc_register_reads 349948963 # number of times the CC registers were read 273system.cpu0.num_cc_register_writes 44904772 # number of times the CC registers were written 274system.cpu0.num_mem_refs 37870790 # number of memory refs 275system.cpu0.num_load_insts 20595754 # Number of load instructions 276system.cpu0.num_store_insts 17275036 # Number of store instructions 277system.cpu0.num_idle_cycles 5488191495.802790 # Number of idle cycles 278system.cpu0.num_busy_cycles 117577026.197211 # Number of busy cycles 279system.cpu0.not_idle_fraction 0.020974 # Percentage of non-idle cycles 280system.cpu0.idle_fraction 0.979026 # Percentage of idle cycles 281system.cpu0.Branches 21940702 # Number of branches fetched 282system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction 283system.cpu0.op_class::IntAlu 78882840 67.49% 67.50% # Class of executed instruction 284system.cpu0.op_class::IntMult 110618 0.09% 67.59% # Class of executed instruction 285system.cpu0.op_class::IntDiv 0 0.00% 67.59% # Class of executed instruction 286system.cpu0.op_class::FloatAdd 0 0.00% 67.59% # Class of executed instruction 287system.cpu0.op_class::FloatCmp 0 0.00% 67.59% # Class of executed instruction 288system.cpu0.op_class::FloatCvt 0 0.00% 67.59% # Class of executed instruction 289system.cpu0.op_class::FloatMult 0 0.00% 67.59% # Class of executed instruction 290system.cpu0.op_class::FloatDiv 0 0.00% 67.59% # Class of executed instruction 291system.cpu0.op_class::FloatSqrt 0 0.00% 67.59% # Class of executed instruction 292system.cpu0.op_class::SimdAdd 0 0.00% 67.59% # Class of executed instruction 293system.cpu0.op_class::SimdAddAcc 0 0.00% 67.59% # Class of executed instruction 294system.cpu0.op_class::SimdAlu 0 0.00% 67.59% # Class of executed instruction 295system.cpu0.op_class::SimdCmp 0 0.00% 67.59% # Class of executed instruction 296system.cpu0.op_class::SimdCvt 0 0.00% 67.59% # Class of executed instruction 297system.cpu0.op_class::SimdMisc 0 0.00% 67.59% # Class of executed instruction 298system.cpu0.op_class::SimdMult 0 0.00% 67.59% # Class of executed instruction 299system.cpu0.op_class::SimdMultAcc 0 0.00% 67.59% # Class of executed instruction 300system.cpu0.op_class::SimdShift 0 0.00% 67.59% # Class of executed instruction 301system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.59% # Class of executed instruction 302system.cpu0.op_class::SimdSqrt 0 0.00% 67.59% # Class of executed instruction 303system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.59% # Class of executed instruction 304system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.59% # Class of executed instruction 305system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.59% # Class of executed instruction 306system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.59% # Class of executed instruction 307system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.59% # Class of executed instruction 308system.cpu0.op_class::SimdFloatMisc 8087 0.01% 67.60% # Class of executed instruction 309system.cpu0.op_class::SimdFloatMult 0 0.00% 67.60% # Class of executed instruction 310system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.60% # Class of executed instruction 311system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.60% # Class of executed instruction 312system.cpu0.op_class::MemRead 20595754 17.62% 85.22% # Class of executed instruction 313system.cpu0.op_class::MemWrite 17275036 14.78% 100.00% # Class of executed instruction 314system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 315system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 316system.cpu0.op_class::total 116874608 # Class of executed instruction 317system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 318system.cpu0.dcache.tags.replacements 693483 # number of replacements 319system.cpu0.dcache.tags.tagsinuse 494.728102 # Cycle average of tags in use 320system.cpu0.dcache.tags.total_refs 35929530 # Total number of references to valid blocks. 321system.cpu0.dcache.tags.sampled_refs 693995 # Sample count of references to valid blocks. 322system.cpu0.dcache.tags.avg_refs 51.772030 # Average number of references to valid blocks. 323system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. 324system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.728102 # Average occupied blocks per requestor 325system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966266 # Average percentage of cache occupancy 326system.cpu0.dcache.tags.occ_percent::total 0.966266 # Average percentage of cache occupancy 327system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 328system.cpu0.dcache.tags.age_task_id_blocks_1024::0 277 # Occupied blocks per task id 329system.cpu0.dcache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id 330system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id 331system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 332system.cpu0.dcache.tags.tag_accesses 74108220 # Number of tag accesses 333system.cpu0.dcache.tags.data_accesses 74108220 # Number of data accesses 334system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 335system.cpu0.dcache.ReadReq_hits::cpu0.data 19107088 # number of ReadReq hits 336system.cpu0.dcache.ReadReq_hits::total 19107088 # number of ReadReq hits 337system.cpu0.dcache.WriteReq_hits::cpu0.data 15689092 # number of WriteReq hits 338system.cpu0.dcache.WriteReq_hits::total 15689092 # number of WriteReq hits 339system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346042 # number of SoftPFReq hits 340system.cpu0.dcache.SoftPFReq_hits::total 346042 # number of SoftPFReq hits 341system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379604 # number of LoadLockedReq hits 342system.cpu0.dcache.LoadLockedReq_hits::total 379604 # number of LoadLockedReq hits 343system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363038 # number of StoreCondReq hits 344system.cpu0.dcache.StoreCondReq_hits::total 363038 # number of StoreCondReq hits 345system.cpu0.dcache.demand_hits::cpu0.data 34796180 # number of demand (read+write) hits 346system.cpu0.dcache.demand_hits::total 34796180 # number of demand (read+write) hits 347system.cpu0.dcache.overall_hits::cpu0.data 35142222 # number of overall hits 348system.cpu0.dcache.overall_hits::total 35142222 # number of overall hits 349system.cpu0.dcache.ReadReq_misses::cpu0.data 373135 # number of ReadReq misses 350system.cpu0.dcache.ReadReq_misses::total 373135 # number of ReadReq misses 351system.cpu0.dcache.WriteReq_misses::cpu0.data 295767 # number of WriteReq misses 352system.cpu0.dcache.WriteReq_misses::total 295767 # number of WriteReq misses 353system.cpu0.dcache.SoftPFReq_misses::cpu0.data 100322 # number of SoftPFReq misses 354system.cpu0.dcache.SoftPFReq_misses::total 100322 # number of SoftPFReq misses 355system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6741 # number of LoadLockedReq misses 356system.cpu0.dcache.LoadLockedReq_misses::total 6741 # number of LoadLockedReq misses 357system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18421 # number of StoreCondReq misses 358system.cpu0.dcache.StoreCondReq_misses::total 18421 # number of StoreCondReq misses 359system.cpu0.dcache.demand_misses::cpu0.data 668902 # number of demand (read+write) misses 360system.cpu0.dcache.demand_misses::total 668902 # number of demand (read+write) misses 361system.cpu0.dcache.overall_misses::cpu0.data 769224 # number of overall misses 362system.cpu0.dcache.overall_misses::total 769224 # number of overall misses 363system.cpu0.dcache.ReadReq_accesses::cpu0.data 19480223 # number of ReadReq accesses(hits+misses) 364system.cpu0.dcache.ReadReq_accesses::total 19480223 # number of ReadReq accesses(hits+misses) 365system.cpu0.dcache.WriteReq_accesses::cpu0.data 15984859 # number of WriteReq accesses(hits+misses) 366system.cpu0.dcache.WriteReq_accesses::total 15984859 # number of WriteReq accesses(hits+misses) 367system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446364 # number of SoftPFReq accesses(hits+misses) 368system.cpu0.dcache.SoftPFReq_accesses::total 446364 # number of SoftPFReq accesses(hits+misses) 369system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386345 # number of LoadLockedReq accesses(hits+misses) 370system.cpu0.dcache.LoadLockedReq_accesses::total 386345 # number of LoadLockedReq accesses(hits+misses) 371system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381459 # number of StoreCondReq accesses(hits+misses) 372system.cpu0.dcache.StoreCondReq_accesses::total 381459 # number of StoreCondReq accesses(hits+misses) 373system.cpu0.dcache.demand_accesses::cpu0.data 35465082 # number of demand (read+write) accesses 374system.cpu0.dcache.demand_accesses::total 35465082 # number of demand (read+write) accesses 375system.cpu0.dcache.overall_accesses::cpu0.data 35911446 # number of overall (read+write) accesses 376system.cpu0.dcache.overall_accesses::total 35911446 # number of overall (read+write) accesses 377system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019155 # miss rate for ReadReq accesses 378system.cpu0.dcache.ReadReq_miss_rate::total 0.019155 # miss rate for ReadReq accesses 379system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018503 # miss rate for WriteReq accesses 380system.cpu0.dcache.WriteReq_miss_rate::total 0.018503 # miss rate for WriteReq accesses 381system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224754 # miss rate for SoftPFReq accesses 382system.cpu0.dcache.SoftPFReq_miss_rate::total 0.224754 # miss rate for SoftPFReq accesses 383system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017448 # miss rate for LoadLockedReq accesses 384system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017448 # miss rate for LoadLockedReq accesses 385system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048291 # miss rate for StoreCondReq accesses 386system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048291 # miss rate for StoreCondReq accesses 387system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018861 # miss rate for demand accesses 388system.cpu0.dcache.demand_miss_rate::total 0.018861 # miss rate for demand accesses 389system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021420 # miss rate for overall accesses 390system.cpu0.dcache.overall_miss_rate::total 0.021420 # miss rate for overall accesses 391system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 392system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 393system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 394system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 395system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 396system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 397system.cpu0.dcache.writebacks::writebacks 693483 # number of writebacks 398system.cpu0.dcache.writebacks::total 693483 # number of writebacks 399system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 400system.cpu0.icache.tags.replacements 1109362 # number of replacements 401system.cpu0.icache.tags.tagsinuse 511.809991 # Cycle average of tags in use 402system.cpu0.icache.tags.total_refs 96325777 # Total number of references to valid blocks. 403system.cpu0.icache.tags.sampled_refs 1109874 # Sample count of references to valid blocks. 404system.cpu0.icache.tags.avg_refs 86.789831 # Average number of references to valid blocks. 405system.cpu0.icache.tags.warmup_cycle 6345718500 # Cycle when the warmup percentage was hit. 406system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.809991 # Average occupied blocks per requestor 407system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999629 # Average percentage of cache occupancy 408system.cpu0.icache.tags.occ_percent::total 0.999629 # Average percentage of cache occupancy 409system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 410system.cpu0.icache.tags.age_task_id_blocks_1024::0 212 # Occupied blocks per task id 411system.cpu0.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id 412system.cpu0.icache.tags.age_task_id_blocks_1024::2 210 # Occupied blocks per task id 413system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 414system.cpu0.icache.tags.tag_accesses 195981203 # Number of tag accesses 415system.cpu0.icache.tags.data_accesses 195981203 # Number of data accesses 416system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 417system.cpu0.icache.ReadReq_hits::cpu0.inst 96325777 # number of ReadReq hits 418system.cpu0.icache.ReadReq_hits::total 96325777 # number of ReadReq hits 419system.cpu0.icache.demand_hits::cpu0.inst 96325777 # number of demand (read+write) hits 420system.cpu0.icache.demand_hits::total 96325777 # number of demand (read+write) hits 421system.cpu0.icache.overall_hits::cpu0.inst 96325777 # number of overall hits 422system.cpu0.icache.overall_hits::total 96325777 # number of overall hits 423system.cpu0.icache.ReadReq_misses::cpu0.inst 1109883 # number of ReadReq misses 424system.cpu0.icache.ReadReq_misses::total 1109883 # number of ReadReq misses 425system.cpu0.icache.demand_misses::cpu0.inst 1109883 # number of demand (read+write) misses 426system.cpu0.icache.demand_misses::total 1109883 # number of demand (read+write) misses 427system.cpu0.icache.overall_misses::cpu0.inst 1109883 # number of overall misses 428system.cpu0.icache.overall_misses::total 1109883 # number of overall misses 429system.cpu0.icache.ReadReq_accesses::cpu0.inst 97435660 # number of ReadReq accesses(hits+misses) 430system.cpu0.icache.ReadReq_accesses::total 97435660 # number of ReadReq accesses(hits+misses) 431system.cpu0.icache.demand_accesses::cpu0.inst 97435660 # number of demand (read+write) accesses 432system.cpu0.icache.demand_accesses::total 97435660 # number of demand (read+write) accesses 433system.cpu0.icache.overall_accesses::cpu0.inst 97435660 # number of overall (read+write) accesses 434system.cpu0.icache.overall_accesses::total 97435660 # number of overall (read+write) accesses 435system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011391 # miss rate for ReadReq accesses 436system.cpu0.icache.ReadReq_miss_rate::total 0.011391 # miss rate for ReadReq accesses 437system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011391 # miss rate for demand accesses 438system.cpu0.icache.demand_miss_rate::total 0.011391 # miss rate for demand accesses 439system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011391 # miss rate for overall accesses 440system.cpu0.icache.overall_miss_rate::total 0.011391 # miss rate for overall accesses 441system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 442system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 443system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 444system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 445system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 446system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 447system.cpu0.icache.writebacks::writebacks 1109362 # number of writebacks 448system.cpu0.icache.writebacks::total 1109362 # number of writebacks 449system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 450system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 451system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 452system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 453system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 454system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 455system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 456system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 457system.cpu0.l2cache.tags.replacements 249561 # number of replacements 458system.cpu0.l2cache.tags.tagsinuse 16130.656320 # Cycle average of tags in use 459system.cpu0.l2cache.tags.total_refs 2729360 # Total number of references to valid blocks. 460system.cpu0.l2cache.tags.sampled_refs 265678 # Sample count of references to valid blocks. 461system.cpu0.l2cache.tags.avg_refs 10.273188 # Average number of references to valid blocks. 462system.cpu0.l2cache.tags.warmup_cycle 1471234000 # Cycle when the warmup percentage was hit. 463system.cpu0.l2cache.tags.occ_blocks::writebacks 16129.249413 # Average occupied blocks per requestor 464system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 1.326952 # Average occupied blocks per requestor 465system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.079954 # Average occupied blocks per requestor 466system.cpu0.l2cache.tags.occ_percent::writebacks 0.984451 # Average percentage of cache occupancy 467system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000081 # Average percentage of cache occupancy 468system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000005 # Average percentage of cache occupancy 469system.cpu0.l2cache.tags.occ_percent::total 0.984537 # Average percentage of cache occupancy 470system.cpu0.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id 471system.cpu0.l2cache.tags.occ_task_id_blocks::1024 16104 # Occupied blocks per task id 472system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id 473system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 7 # Occupied blocks per task id 474system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id 475system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 154 # Occupied blocks per task id 476system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 349 # Occupied blocks per task id 477system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5522 # Occupied blocks per task id 478system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7440 # Occupied blocks per task id 479system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2639 # Occupied blocks per task id 480system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000793 # Percentage of cache occupancy per task id 481system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.982910 # Percentage of cache occupancy per task id 482system.cpu0.l2cache.tags.tag_accesses 59687833 # Number of tag accesses 483system.cpu0.l2cache.tags.data_accesses 59687833 # Number of data accesses 484system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 485system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 10176 # number of ReadReq hits 486system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4489 # number of ReadReq hits 487system.cpu0.l2cache.ReadReq_hits::total 14665 # number of ReadReq hits 488system.cpu0.l2cache.WritebackDirty_hits::writebacks 510613 # number of WritebackDirty hits 489system.cpu0.l2cache.WritebackDirty_hits::total 510613 # number of WritebackDirty hits 490system.cpu0.l2cache.WritebackClean_hits::writebacks 1264371 # number of WritebackClean hits 491system.cpu0.l2cache.WritebackClean_hits::total 1264371 # number of WritebackClean hits 492system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94352 # number of ReadExReq hits 493system.cpu0.l2cache.ReadExReq_hits::total 94352 # number of ReadExReq hits 494system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1067857 # number of ReadCleanReq hits 495system.cpu0.l2cache.ReadCleanReq_hits::total 1067857 # number of ReadCleanReq hits 496system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 352287 # number of ReadSharedReq hits 497system.cpu0.l2cache.ReadSharedReq_hits::total 352287 # number of ReadSharedReq hits 498system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 10176 # number of demand (read+write) hits 499system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4489 # number of demand (read+write) hits 500system.cpu0.l2cache.demand_hits::cpu0.inst 1067857 # number of demand (read+write) hits 501system.cpu0.l2cache.demand_hits::cpu0.data 446639 # number of demand (read+write) hits 502system.cpu0.l2cache.demand_hits::total 1529161 # number of demand (read+write) hits 503system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 10176 # number of overall hits 504system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4489 # number of overall hits 505system.cpu0.l2cache.overall_hits::cpu0.inst 1067857 # number of overall hits 506system.cpu0.l2cache.overall_hits::cpu0.data 446639 # number of overall hits 507system.cpu0.l2cache.overall_hits::total 1529161 # number of overall hits 508system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 214 # number of ReadReq misses 509system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 138 # number of ReadReq misses 510system.cpu0.l2cache.ReadReq_misses::total 352 # number of ReadReq misses 511system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26245 # number of UpgradeReq misses 512system.cpu0.l2cache.UpgradeReq_misses::total 26245 # number of UpgradeReq misses 513system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18421 # number of SCUpgradeReq misses 514system.cpu0.l2cache.SCUpgradeReq_misses::total 18421 # number of SCUpgradeReq misses 515system.cpu0.l2cache.ReadExReq_misses::cpu0.data 175170 # number of ReadExReq misses 516system.cpu0.l2cache.ReadExReq_misses::total 175170 # number of ReadExReq misses 517system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 42026 # number of ReadCleanReq misses 518system.cpu0.l2cache.ReadCleanReq_misses::total 42026 # number of ReadCleanReq misses 519system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 127911 # number of ReadSharedReq misses 520system.cpu0.l2cache.ReadSharedReq_misses::total 127911 # number of ReadSharedReq misses 521system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 214 # number of demand (read+write) misses 522system.cpu0.l2cache.demand_misses::cpu0.itb.walker 138 # number of demand (read+write) misses 523system.cpu0.l2cache.demand_misses::cpu0.inst 42026 # number of demand (read+write) misses 524system.cpu0.l2cache.demand_misses::cpu0.data 303081 # number of demand (read+write) misses 525system.cpu0.l2cache.demand_misses::total 345459 # number of demand (read+write) misses 526system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 214 # number of overall misses 527system.cpu0.l2cache.overall_misses::cpu0.itb.walker 138 # number of overall misses 528system.cpu0.l2cache.overall_misses::cpu0.inst 42026 # number of overall misses 529system.cpu0.l2cache.overall_misses::cpu0.data 303081 # number of overall misses 530system.cpu0.l2cache.overall_misses::total 345459 # number of overall misses 531system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 10390 # number of ReadReq accesses(hits+misses) 532system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4627 # number of ReadReq accesses(hits+misses) 533system.cpu0.l2cache.ReadReq_accesses::total 15017 # number of ReadReq accesses(hits+misses) 534system.cpu0.l2cache.WritebackDirty_accesses::writebacks 510613 # number of WritebackDirty accesses(hits+misses) 535system.cpu0.l2cache.WritebackDirty_accesses::total 510613 # number of WritebackDirty accesses(hits+misses) 536system.cpu0.l2cache.WritebackClean_accesses::writebacks 1264371 # number of WritebackClean accesses(hits+misses) 537system.cpu0.l2cache.WritebackClean_accesses::total 1264371 # number of WritebackClean accesses(hits+misses) 538system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26245 # number of UpgradeReq accesses(hits+misses) 539system.cpu0.l2cache.UpgradeReq_accesses::total 26245 # number of UpgradeReq accesses(hits+misses) 540system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18421 # number of SCUpgradeReq accesses(hits+misses) 541system.cpu0.l2cache.SCUpgradeReq_accesses::total 18421 # number of SCUpgradeReq accesses(hits+misses) 542system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269522 # number of ReadExReq accesses(hits+misses) 543system.cpu0.l2cache.ReadExReq_accesses::total 269522 # number of ReadExReq accesses(hits+misses) 544system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1109883 # number of ReadCleanReq accesses(hits+misses) 545system.cpu0.l2cache.ReadCleanReq_accesses::total 1109883 # number of ReadCleanReq accesses(hits+misses) 546system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 480198 # number of ReadSharedReq accesses(hits+misses) 547system.cpu0.l2cache.ReadSharedReq_accesses::total 480198 # number of ReadSharedReq accesses(hits+misses) 548system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 10390 # number of demand (read+write) accesses 549system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4627 # number of demand (read+write) accesses 550system.cpu0.l2cache.demand_accesses::cpu0.inst 1109883 # number of demand (read+write) accesses 551system.cpu0.l2cache.demand_accesses::cpu0.data 749720 # number of demand (read+write) accesses 552system.cpu0.l2cache.demand_accesses::total 1874620 # number of demand (read+write) accesses 553system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 10390 # number of overall (read+write) accesses 554system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4627 # number of overall (read+write) accesses 555system.cpu0.l2cache.overall_accesses::cpu0.inst 1109883 # number of overall (read+write) accesses 556system.cpu0.l2cache.overall_accesses::cpu0.data 749720 # number of overall (read+write) accesses 557system.cpu0.l2cache.overall_accesses::total 1874620 # number of overall (read+write) accesses 558system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.020597 # miss rate for ReadReq accesses 559system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.029825 # miss rate for ReadReq accesses 560system.cpu0.l2cache.ReadReq_miss_rate::total 0.023440 # miss rate for ReadReq accesses 561system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses 562system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 563system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 564system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 565system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.649928 # miss rate for ReadExReq accesses 566system.cpu0.l2cache.ReadExReq_miss_rate::total 0.649928 # miss rate for ReadExReq accesses 567system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.037865 # miss rate for ReadCleanReq accesses 568system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.037865 # miss rate for ReadCleanReq accesses 569system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.266371 # miss rate for ReadSharedReq accesses 570system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.266371 # miss rate for ReadSharedReq accesses 571system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.020597 # miss rate for demand accesses 572system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.029825 # miss rate for demand accesses 573system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.037865 # miss rate for demand accesses 574system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404259 # miss rate for demand accesses 575system.cpu0.l2cache.demand_miss_rate::total 0.184282 # miss rate for demand accesses 576system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.020597 # miss rate for overall accesses 577system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.029825 # miss rate for overall accesses 578system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.037865 # miss rate for overall accesses 579system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404259 # miss rate for overall accesses 580system.cpu0.l2cache.overall_miss_rate::total 0.184282 # miss rate for overall accesses 581system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 582system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 583system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 584system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 585system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 586system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 587system.cpu0.l2cache.writebacks::writebacks 192746 # number of writebacks 588system.cpu0.l2cache.writebacks::total 192746 # number of writebacks 589system.cpu0.toL2Bus.snoop_filter.tot_requests 3719480 # Total number of requests made to the snoop filter. 590system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1859901 # Number of requests hitting in the snoop filter with a single holder of the requested data. 591system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27861 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 592system.cpu0.toL2Bus.snoop_filter.tot_snoops 218561 # Total number of snoops made to the snoop filter. 593system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 215432 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 594system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 3129 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 595system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 596system.cpu0.toL2Bus.trans_dist::ReadReq 61410 # Transaction distribution 597system.cpu0.toL2Bus.trans_dist::ReadResp 1651491 # Transaction distribution 598system.cpu0.toL2Bus.trans_dist::WriteReq 28340 # Transaction distribution 599system.cpu0.toL2Bus.trans_dist::WriteResp 28340 # Transaction distribution 600system.cpu0.toL2Bus.trans_dist::WritebackDirty 510613 # Transaction distribution 601system.cpu0.toL2Bus.trans_dist::WritebackClean 1292232 # Transaction distribution 602system.cpu0.toL2Bus.trans_dist::UpgradeReq 26245 # Transaction distribution 603system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18421 # Transaction distribution 604system.cpu0.toL2Bus.trans_dist::UpgradeResp 44666 # Transaction distribution 605system.cpu0.toL2Bus.trans_dist::ReadExReq 269522 # Transaction distribution 606system.cpu0.toL2Bus.trans_dist::ReadExResp 269522 # Transaction distribution 607system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1109883 # Transaction distribution 608system.cpu0.toL2Bus.trans_dist::ReadSharedReq 480198 # Transaction distribution 609system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3347172 # Packet count per connected master and slave (bytes) 610system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2402087 # Packet count per connected master and slave (bytes) 611system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12828 # Packet count per connected master and slave (bytes) 612system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 28796 # Packet count per connected master and slave (bytes) 613system.cpu0.toL2Bus.pkt_count::total 5790883 # Packet count per connected master and slave (bytes) 614system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 142067768 # Cumulative packet size per connected master and slave (bytes) 615system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 92555520 # Cumulative packet size per connected master and slave (bytes) 616system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 25656 # Cumulative packet size per connected master and slave (bytes) 617system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 57592 # Cumulative packet size per connected master and slave (bytes) 618system.cpu0.toL2Bus.pkt_size::total 234706536 # Cumulative packet size per connected master and slave (bytes) 619system.cpu0.toL2Bus.snoops 623474 # Total snoops (count) 620system.cpu0.toL2Bus.snoopTraffic 12368448 # Total snoop traffic (bytes) 621system.cpu0.toL2Bus.snoop_fanout::samples 4317750 # Request fanout histogram 622system.cpu0.toL2Bus.snoop_fanout::mean 0.067119 # Request fanout histogram 623system.cpu0.toL2Bus.snoop_fanout::stdev 0.253107 # Request fanout histogram 624system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 625system.cpu0.toL2Bus.snoop_fanout::0 4031077 93.36% 93.36% # Request fanout histogram 626system.cpu0.toL2Bus.snoop_fanout::1 283544 6.57% 99.93% # Request fanout histogram 627system.cpu0.toL2Bus.snoop_fanout::2 3129 0.07% 100.00% # Request fanout histogram 628system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 629system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 630system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 631system.cpu0.toL2Bus.snoop_fanout::total 4317750 # Request fanout histogram 632system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 633system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 634system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 635system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 636system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 637system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 638system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 639system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 640system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 641system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 642system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 643system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 644system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 645system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 646system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 647system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 648system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 649system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 650system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 651system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 652system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 653system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 654system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 655system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 656system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 657system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 658system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 659system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 660system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 661system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 662system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 663system.cpu1.dtb.walker.walks 3359 # Table walker walks requested 664system.cpu1.dtb.walker.walksShort 3359 # Table walker walks initiated with short descriptors 665system.cpu1.dtb.walker.walkWaitTime::samples 3359 # Table walker wait (enqueue to first request) latency 666system.cpu1.dtb.walker.walkWaitTime::0 3359 100.00% 100.00% # Table walker wait (enqueue to first request) latency 667system.cpu1.dtb.walker.walkWaitTime::total 3359 # Table walker wait (enqueue to first request) latency 668system.cpu1.dtb.walker.walksPending::samples -1804201736 # Table walker pending requests distribution 669system.cpu1.dtb.walker.walksPending::0 -1804201736 100.00% 100.00% # Table walker pending requests distribution 670system.cpu1.dtb.walker.walksPending::total -1804201736 # Table walker pending requests distribution 671system.cpu1.dtb.walker.walkPageSizes::4K 1919 74.12% 74.12% # Table walker page sizes translated 672system.cpu1.dtb.walker.walkPageSizes::1M 670 25.88% 100.00% # Table walker page sizes translated 673system.cpu1.dtb.walker.walkPageSizes::total 2589 # Table walker page sizes translated 674system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3359 # Table walker requests started/completed, data/inst 675system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 676system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3359 # Table walker requests started/completed, data/inst 677system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2589 # Table walker requests started/completed, data/inst 678system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 679system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2589 # Table walker requests started/completed, data/inst 680system.cpu1.dtb.walker.walkRequestOrigin::total 5948 # Table walker requests started/completed, data/inst 681system.cpu1.dtb.inst_hits 0 # ITB inst hits 682system.cpu1.dtb.inst_misses 0 # ITB inst misses 683system.cpu1.dtb.read_hits 12172373 # DTB read hits 684system.cpu1.dtb.read_misses 2853 # DTB read misses 685system.cpu1.dtb.write_hits 7586083 # DTB write hits 686system.cpu1.dtb.write_misses 506 # DTB write misses 687system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 688system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 689system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 690system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 691system.cpu1.dtb.flush_entries 1949 # Number of entries that have been flushed from TLB 692system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 693system.cpu1.dtb.prefetch_faults 290 # Number of TLB faults due to prefetch 694system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 695system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions 696system.cpu1.dtb.read_accesses 12175226 # DTB read accesses 697system.cpu1.dtb.write_accesses 7586589 # DTB write accesses 698system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 699system.cpu1.dtb.hits 19758456 # DTB hits 700system.cpu1.dtb.misses 3359 # DTB misses 701system.cpu1.dtb.accesses 19761815 # DTB accesses 702system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 703system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 704system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 705system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 706system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 707system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 708system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 709system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 710system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 711system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 712system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 713system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 714system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 715system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 716system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 717system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 718system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 719system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 720system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 721system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 722system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 723system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 724system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 725system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 726system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 727system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 728system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 729system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 730system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 731system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 732system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 733system.cpu1.itb.walker.walks 1734 # Table walker walks requested 734system.cpu1.itb.walker.walksShort 1734 # Table walker walks initiated with short descriptors 735system.cpu1.itb.walker.walkWaitTime::samples 1734 # Table walker wait (enqueue to first request) latency 736system.cpu1.itb.walker.walkWaitTime::0 1734 100.00% 100.00% # Table walker wait (enqueue to first request) latency 737system.cpu1.itb.walker.walkWaitTime::total 1734 # Table walker wait (enqueue to first request) latency 738system.cpu1.itb.walker.walksPending::samples -1804204236 # Table walker pending requests distribution 739system.cpu1.itb.walker.walksPending::0 -1804204236 100.00% 100.00% # Table walker pending requests distribution 740system.cpu1.itb.walker.walksPending::total -1804204236 # Table walker pending requests distribution 741system.cpu1.itb.walker.walkPageSizes::4K 935 85.39% 85.39% # Table walker page sizes translated 742system.cpu1.itb.walker.walkPageSizes::1M 160 14.61% 100.00% # Table walker page sizes translated 743system.cpu1.itb.walker.walkPageSizes::total 1095 # Table walker page sizes translated 744system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 745system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1734 # Table walker requests started/completed, data/inst 746system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1734 # Table walker requests started/completed, data/inst 747system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 748system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1095 # Table walker requests started/completed, data/inst 749system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1095 # Table walker requests started/completed, data/inst 750system.cpu1.itb.walker.walkRequestOrigin::total 2829 # Table walker requests started/completed, data/inst 751system.cpu1.itb.inst_hits 53665127 # ITB inst hits 752system.cpu1.itb.inst_misses 1734 # ITB inst misses 753system.cpu1.itb.read_hits 0 # DTB read hits 754system.cpu1.itb.read_misses 0 # DTB read misses 755system.cpu1.itb.write_hits 0 # DTB write hits 756system.cpu1.itb.write_misses 0 # DTB write misses 757system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 758system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 759system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 760system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 761system.cpu1.itb.flush_entries 1072 # Number of entries that have been flushed from TLB 762system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 763system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 764system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 765system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 766system.cpu1.itb.read_accesses 0 # DTB read accesses 767system.cpu1.itb.write_accesses 0 # DTB write accesses 768system.cpu1.itb.inst_accesses 53666861 # ITB inst accesses 769system.cpu1.itb.hits 53665127 # DTB hits 770system.cpu1.itb.misses 1734 # DTB misses 771system.cpu1.itb.accesses 53666861 # DTB accesses 772system.cpu1.numPwrStateTransitions 5467 # Number of power state transitions 773system.cpu1.pwrStateClkGateDist::samples 2734 # Distribution of time spent in the clock gated state 774system.cpu1.pwrStateClkGateDist::mean 1013195942.406364 # Distribution of time spent in the clock gated state 775system.cpu1.pwrStateClkGateDist::stdev 25944771719.895676 # Distribution of time spent in the clock gated state 776system.cpu1.pwrStateClkGateDist::underflows 1955 71.51% 71.51% # Distribution of time spent in the clock gated state 777system.cpu1.pwrStateClkGateDist::1000-5e+10 774 28.31% 99.82% # Distribution of time spent in the clock gated state 778system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.07% 99.89% # Distribution of time spent in the clock gated state 779system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state 780system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state 781system.cpu1.pwrStateClkGateDist::9.5e+11-1e+12 1 0.04% 100.00% # Distribution of time spent in the clock gated state 782system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 783system.cpu1.pwrStateClkGateDist::max_value 979984970108 # Distribution of time spent in the clock gated state 784system.cpu1.pwrStateClkGateDist::total 2734 # Distribution of time spent in the clock gated state 785system.cpu1.pwrStateResidencyTicks::ON 32805567461 # Cumulative time (in ticks) in various power states 786system.cpu1.pwrStateResidencyTicks::CLK_GATED 2770077706539 # Cumulative time (in ticks) in various power states 787system.cpu1.numCycles 5605297416 # number of cpu cycles simulated 788system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 789system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 790system.cpu1.kern.inst.arm 0 # number of arm instructions executed 791system.cpu1.kern.inst.quiesce 2734 # number of quiesce instructions executed 792system.cpu1.committedInsts 51394923 # Number of instructions committed 793system.cpu1.committedOps 63339792 # Number of ops (including micro ops) committed 794system.cpu1.num_int_alu_accesses 56977163 # Number of integer alu accesses 795system.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses 796system.cpu1.num_func_calls 9170267 # number of times a function call or return occured 797system.cpu1.num_conditional_control_insts 5966436 # number of instructions that are conditional controls 798system.cpu1.num_int_insts 56977163 # number of integer instructions 799system.cpu1.num_fp_insts 1792 # number of float instructions 800system.cpu1.num_int_register_reads 110657326 # number of times the integer registers were read 801system.cpu1.num_int_register_writes 41293408 # number of times the integer registers were written 802system.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read 803system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written 804system.cpu1.num_cc_register_reads 196244999 # number of times the CC registers were read 805system.cpu1.num_cc_register_writes 18891882 # number of times the CC registers were written 806system.cpu1.num_mem_refs 20023552 # number of memory refs 807system.cpu1.num_load_insts 12287954 # Number of load instructions 808system.cpu1.num_store_insts 7735598 # Number of store instructions 809system.cpu1.num_idle_cycles 5539691771.902995 # Number of idle cycles 810system.cpu1.num_busy_cycles 65605644.097005 # Number of busy cycles 811system.cpu1.not_idle_fraction 0.011704 # Percentage of non-idle cycles 812system.cpu1.idle_fraction 0.988296 # Percentage of idle cycles 813system.cpu1.Branches 15216243 # Number of branches fetched 814system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction 815system.cpu1.op_class::IntAlu 45396317 69.36% 69.36% # Class of executed instruction 816system.cpu1.op_class::IntMult 28337 0.04% 69.40% # Class of executed instruction 817system.cpu1.op_class::IntDiv 0 0.00% 69.40% # Class of executed instruction 818system.cpu1.op_class::FloatAdd 0 0.00% 69.40% # Class of executed instruction 819system.cpu1.op_class::FloatCmp 0 0.00% 69.40% # Class of executed instruction 820system.cpu1.op_class::FloatCvt 0 0.00% 69.40% # Class of executed instruction 821system.cpu1.op_class::FloatMult 0 0.00% 69.40% # Class of executed instruction 822system.cpu1.op_class::FloatDiv 0 0.00% 69.40% # Class of executed instruction 823system.cpu1.op_class::FloatSqrt 0 0.00% 69.40% # Class of executed instruction 824system.cpu1.op_class::SimdAdd 0 0.00% 69.40% # Class of executed instruction 825system.cpu1.op_class::SimdAddAcc 0 0.00% 69.40% # Class of executed instruction 826system.cpu1.op_class::SimdAlu 0 0.00% 69.40% # Class of executed instruction 827system.cpu1.op_class::SimdCmp 0 0.00% 69.40% # Class of executed instruction 828system.cpu1.op_class::SimdCvt 0 0.00% 69.40% # Class of executed instruction 829system.cpu1.op_class::SimdMisc 0 0.00% 69.40% # Class of executed instruction 830system.cpu1.op_class::SimdMult 0 0.00% 69.40% # Class of executed instruction 831system.cpu1.op_class::SimdMultAcc 0 0.00% 69.40% # Class of executed instruction 832system.cpu1.op_class::SimdShift 0 0.00% 69.40% # Class of executed instruction 833system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.40% # Class of executed instruction 834system.cpu1.op_class::SimdSqrt 0 0.00% 69.40% # Class of executed instruction 835system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.40% # Class of executed instruction 836system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.40% # Class of executed instruction 837system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.40% # Class of executed instruction 838system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.40% # Class of executed instruction 839system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.40% # Class of executed instruction 840system.cpu1.op_class::SimdFloatMisc 3315 0.01% 69.41% # Class of executed instruction 841system.cpu1.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction 842system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction 843system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction 844system.cpu1.op_class::MemRead 12287954 18.77% 88.18% # Class of executed instruction 845system.cpu1.op_class::MemWrite 7735598 11.82% 100.00% # Class of executed instruction 846system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 847system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 848system.cpu1.op_class::total 65451587 # Class of executed instruction 849system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 850system.cpu1.dcache.tags.replacements 191903 # number of replacements 851system.cpu1.dcache.tags.tagsinuse 472.757938 # Cycle average of tags in use 852system.cpu1.dcache.tags.total_refs 19500903 # Total number of references to valid blocks. 853system.cpu1.dcache.tags.sampled_refs 192257 # Sample count of references to valid blocks. 854system.cpu1.dcache.tags.avg_refs 101.431433 # Average number of references to valid blocks. 855system.cpu1.dcache.tags.warmup_cycle 105851556000 # Cycle when the warmup percentage was hit. 856system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.757938 # Average occupied blocks per requestor 857system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923355 # Average percentage of cache occupancy 858system.cpu1.dcache.tags.occ_percent::total 0.923355 # Average percentage of cache occupancy 859system.cpu1.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id 860system.cpu1.dcache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id 861system.cpu1.dcache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id 862system.cpu1.dcache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id 863system.cpu1.dcache.tags.tag_accesses 39746590 # Number of tag accesses 864system.cpu1.dcache.tags.data_accesses 39746590 # Number of data accesses 865system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 866system.cpu1.dcache.ReadReq_hits::cpu1.data 11857228 # number of ReadReq hits 867system.cpu1.dcache.ReadReq_hits::total 11857228 # number of ReadReq hits 868system.cpu1.dcache.WriteReq_hits::cpu1.data 7396366 # number of WriteReq hits 869system.cpu1.dcache.WriteReq_hits::total 7396366 # number of WriteReq hits 870system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50103 # number of SoftPFReq hits 871system.cpu1.dcache.SoftPFReq_hits::total 50103 # number of SoftPFReq hits 872system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91426 # number of LoadLockedReq hits 873system.cpu1.dcache.LoadLockedReq_hits::total 91426 # number of LoadLockedReq hits 874system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72412 # number of StoreCondReq hits 875system.cpu1.dcache.StoreCondReq_hits::total 72412 # number of StoreCondReq hits 876system.cpu1.dcache.demand_hits::cpu1.data 19253594 # number of demand (read+write) hits 877system.cpu1.dcache.demand_hits::total 19253594 # number of demand (read+write) hits 878system.cpu1.dcache.overall_hits::cpu1.data 19303697 # number of overall hits 879system.cpu1.dcache.overall_hits::total 19303697 # number of overall hits 880system.cpu1.dcache.ReadReq_misses::cpu1.data 136574 # number of ReadReq misses 881system.cpu1.dcache.ReadReq_misses::total 136574 # number of ReadReq misses 882system.cpu1.dcache.WriteReq_misses::cpu1.data 92490 # number of WriteReq misses 883system.cpu1.dcache.WriteReq_misses::total 92490 # number of WriteReq misses 884system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30717 # number of SoftPFReq misses 885system.cpu1.dcache.SoftPFReq_misses::total 30717 # number of SoftPFReq misses 886system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5318 # number of LoadLockedReq misses 887system.cpu1.dcache.LoadLockedReq_misses::total 5318 # number of LoadLockedReq misses 888system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22549 # number of StoreCondReq misses 889system.cpu1.dcache.StoreCondReq_misses::total 22549 # number of StoreCondReq misses 890system.cpu1.dcache.demand_misses::cpu1.data 229064 # number of demand (read+write) misses 891system.cpu1.dcache.demand_misses::total 229064 # number of demand (read+write) misses 892system.cpu1.dcache.overall_misses::cpu1.data 259781 # number of overall misses 893system.cpu1.dcache.overall_misses::total 259781 # number of overall misses 894system.cpu1.dcache.ReadReq_accesses::cpu1.data 11993802 # number of ReadReq accesses(hits+misses) 895system.cpu1.dcache.ReadReq_accesses::total 11993802 # number of ReadReq accesses(hits+misses) 896system.cpu1.dcache.WriteReq_accesses::cpu1.data 7488856 # number of WriteReq accesses(hits+misses) 897system.cpu1.dcache.WriteReq_accesses::total 7488856 # number of WriteReq accesses(hits+misses) 898system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80820 # number of SoftPFReq accesses(hits+misses) 899system.cpu1.dcache.SoftPFReq_accesses::total 80820 # number of SoftPFReq accesses(hits+misses) 900system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96744 # number of LoadLockedReq accesses(hits+misses) 901system.cpu1.dcache.LoadLockedReq_accesses::total 96744 # number of LoadLockedReq accesses(hits+misses) 902system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94961 # number of StoreCondReq accesses(hits+misses) 903system.cpu1.dcache.StoreCondReq_accesses::total 94961 # number of StoreCondReq accesses(hits+misses) 904system.cpu1.dcache.demand_accesses::cpu1.data 19482658 # number of demand (read+write) accesses 905system.cpu1.dcache.demand_accesses::total 19482658 # number of demand (read+write) accesses 906system.cpu1.dcache.overall_accesses::cpu1.data 19563478 # number of overall (read+write) accesses 907system.cpu1.dcache.overall_accesses::total 19563478 # number of overall (read+write) accesses 908system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011387 # miss rate for ReadReq accesses 909system.cpu1.dcache.ReadReq_miss_rate::total 0.011387 # miss rate for ReadReq accesses 910system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012350 # miss rate for WriteReq accesses 911system.cpu1.dcache.WriteReq_miss_rate::total 0.012350 # miss rate for WriteReq accesses 912system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380067 # miss rate for SoftPFReq accesses 913system.cpu1.dcache.SoftPFReq_miss_rate::total 0.380067 # miss rate for SoftPFReq accesses 914system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054970 # miss rate for LoadLockedReq accesses 915system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054970 # miss rate for LoadLockedReq accesses 916system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237455 # miss rate for StoreCondReq accesses 917system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237455 # miss rate for StoreCondReq accesses 918system.cpu1.dcache.demand_miss_rate::cpu1.data 0.011757 # miss rate for demand accesses 919system.cpu1.dcache.demand_miss_rate::total 0.011757 # miss rate for demand accesses 920system.cpu1.dcache.overall_miss_rate::cpu1.data 0.013279 # miss rate for overall accesses 921system.cpu1.dcache.overall_miss_rate::total 0.013279 # miss rate for overall accesses 922system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 923system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 924system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 925system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 926system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 927system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 928system.cpu1.dcache.writebacks::writebacks 191903 # number of writebacks 929system.cpu1.dcache.writebacks::total 191903 # number of writebacks 930system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 931system.cpu1.icache.tags.replacements 523286 # number of replacements 932system.cpu1.icache.tags.tagsinuse 499.709347 # Cycle average of tags in use 933system.cpu1.icache.tags.total_refs 53142419 # Total number of references to valid blocks. 934system.cpu1.icache.tags.sampled_refs 523798 # Sample count of references to valid blocks. 935system.cpu1.icache.tags.avg_refs 101.455941 # Average number of references to valid blocks. 936system.cpu1.icache.tags.warmup_cycle 76931398500 # Cycle when the warmup percentage was hit. 937system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.709347 # Average occupied blocks per requestor 938system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975995 # Average percentage of cache occupancy 939system.cpu1.icache.tags.occ_percent::total 0.975995 # Average percentage of cache occupancy 940system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 941system.cpu1.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id 942system.cpu1.icache.tags.age_task_id_blocks_1024::3 35 # Occupied blocks per task id 943system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 944system.cpu1.icache.tags.tag_accesses 107856232 # Number of tag accesses 945system.cpu1.icache.tags.data_accesses 107856232 # Number of data accesses 946system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 947system.cpu1.icache.ReadReq_hits::cpu1.inst 53142419 # number of ReadReq hits 948system.cpu1.icache.ReadReq_hits::total 53142419 # number of ReadReq hits 949system.cpu1.icache.demand_hits::cpu1.inst 53142419 # number of demand (read+write) hits 950system.cpu1.icache.demand_hits::total 53142419 # number of demand (read+write) hits 951system.cpu1.icache.overall_hits::cpu1.inst 53142419 # number of overall hits 952system.cpu1.icache.overall_hits::total 53142419 # number of overall hits 953system.cpu1.icache.ReadReq_misses::cpu1.inst 523798 # number of ReadReq misses 954system.cpu1.icache.ReadReq_misses::total 523798 # number of ReadReq misses 955system.cpu1.icache.demand_misses::cpu1.inst 523798 # number of demand (read+write) misses 956system.cpu1.icache.demand_misses::total 523798 # number of demand (read+write) misses 957system.cpu1.icache.overall_misses::cpu1.inst 523798 # number of overall misses 958system.cpu1.icache.overall_misses::total 523798 # number of overall misses 959system.cpu1.icache.ReadReq_accesses::cpu1.inst 53666217 # number of ReadReq accesses(hits+misses) 960system.cpu1.icache.ReadReq_accesses::total 53666217 # number of ReadReq accesses(hits+misses) 961system.cpu1.icache.demand_accesses::cpu1.inst 53666217 # number of demand (read+write) accesses 962system.cpu1.icache.demand_accesses::total 53666217 # number of demand (read+write) accesses 963system.cpu1.icache.overall_accesses::cpu1.inst 53666217 # number of overall (read+write) accesses 964system.cpu1.icache.overall_accesses::total 53666217 # number of overall (read+write) accesses 965system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009760 # miss rate for ReadReq accesses 966system.cpu1.icache.ReadReq_miss_rate::total 0.009760 # miss rate for ReadReq accesses 967system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009760 # miss rate for demand accesses 968system.cpu1.icache.demand_miss_rate::total 0.009760 # miss rate for demand accesses 969system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009760 # miss rate for overall accesses 970system.cpu1.icache.overall_miss_rate::total 0.009760 # miss rate for overall accesses 971system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 972system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 973system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 974system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 975system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 976system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 977system.cpu1.icache.writebacks::writebacks 523286 # number of writebacks 978system.cpu1.icache.writebacks::total 523286 # number of writebacks 979system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 980system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 981system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 982system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 983system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 984system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 985system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 986system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 987system.cpu1.l2cache.tags.replacements 47270 # number of replacements 988system.cpu1.l2cache.tags.tagsinuse 15227.212087 # Cycle average of tags in use 989system.cpu1.l2cache.tags.total_refs 1184400 # Total number of references to valid blocks. 990system.cpu1.l2cache.tags.sampled_refs 62319 # Sample count of references to valid blocks. 991system.cpu1.l2cache.tags.avg_refs 19.005440 # Average number of references to valid blocks. 992system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 993system.cpu1.l2cache.tags.occ_blocks::writebacks 15223.147061 # Average occupied blocks per requestor 994system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 2.040750 # Average occupied blocks per requestor 995system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.024276 # Average occupied blocks per requestor 996system.cpu1.l2cache.tags.occ_percent::writebacks 0.929147 # Average percentage of cache occupancy 997system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000125 # Average percentage of cache occupancy 998system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000124 # Average percentage of cache occupancy 999system.cpu1.l2cache.tags.occ_percent::total 0.929395 # Average percentage of cache occupancy 1000system.cpu1.l2cache.tags.occ_task_id_blocks::1023 20 # Occupied blocks per task id 1001system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15029 # Occupied blocks per task id 1002system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id 1003system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id 1004system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id 1005system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 528 # Occupied blocks per task id 1006system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9407 # Occupied blocks per task id 1007system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 5094 # Occupied blocks per task id 1008system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001221 # Percentage of cache occupancy per task id 1009system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.917297 # Percentage of cache occupancy per task id 1010system.cpu1.l2cache.tags.tag_accesses 24496500 # Number of tag accesses 1011system.cpu1.l2cache.tags.data_accesses 24496500 # Number of data accesses 1012system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1013system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3624 # number of ReadReq hits 1014system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1921 # number of ReadReq hits 1015system.cpu1.l2cache.ReadReq_hits::total 5545 # number of ReadReq hits 1016system.cpu1.l2cache.WritebackDirty_hits::writebacks 120975 # number of WritebackDirty hits 1017system.cpu1.l2cache.WritebackDirty_hits::total 120975 # number of WritebackDirty hits 1018system.cpu1.l2cache.WritebackClean_hits::writebacks 583053 # number of WritebackClean hits 1019system.cpu1.l2cache.WritebackClean_hits::total 583053 # number of WritebackClean hits 1020system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19849 # number of ReadExReq hits 1021system.cpu1.l2cache.ReadExReq_hits::total 19849 # number of ReadExReq hits 1022system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 510459 # number of ReadCleanReq hits 1023system.cpu1.l2cache.ReadCleanReq_hits::total 510459 # number of ReadCleanReq hits 1024system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 99238 # number of ReadSharedReq hits 1025system.cpu1.l2cache.ReadSharedReq_hits::total 99238 # number of ReadSharedReq hits 1026system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3624 # number of demand (read+write) hits 1027system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1921 # number of demand (read+write) hits 1028system.cpu1.l2cache.demand_hits::cpu1.inst 510459 # number of demand (read+write) hits 1029system.cpu1.l2cache.demand_hits::cpu1.data 119087 # number of demand (read+write) hits 1030system.cpu1.l2cache.demand_hits::total 635091 # number of demand (read+write) hits 1031system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3624 # number of overall hits 1032system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1921 # number of overall hits 1033system.cpu1.l2cache.overall_hits::cpu1.inst 510459 # number of overall hits 1034system.cpu1.l2cache.overall_hits::cpu1.data 119087 # number of overall hits 1035system.cpu1.l2cache.overall_hits::total 635091 # number of overall hits 1036system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 336 # number of ReadReq misses 1037system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 270 # number of ReadReq misses 1038system.cpu1.l2cache.ReadReq_misses::total 606 # number of ReadReq misses 1039system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28875 # number of UpgradeReq misses 1040system.cpu1.l2cache.UpgradeReq_misses::total 28875 # number of UpgradeReq misses 1041system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22549 # number of SCUpgradeReq misses 1042system.cpu1.l2cache.SCUpgradeReq_misses::total 22549 # number of SCUpgradeReq misses 1043system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43766 # number of ReadExReq misses 1044system.cpu1.l2cache.ReadExReq_misses::total 43766 # number of ReadExReq misses 1045system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 13339 # number of ReadCleanReq misses 1046system.cpu1.l2cache.ReadCleanReq_misses::total 13339 # number of ReadCleanReq misses 1047system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 73371 # number of ReadSharedReq misses 1048system.cpu1.l2cache.ReadSharedReq_misses::total 73371 # number of ReadSharedReq misses 1049system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 336 # number of demand (read+write) misses 1050system.cpu1.l2cache.demand_misses::cpu1.itb.walker 270 # number of demand (read+write) misses 1051system.cpu1.l2cache.demand_misses::cpu1.inst 13339 # number of demand (read+write) misses 1052system.cpu1.l2cache.demand_misses::cpu1.data 117137 # number of demand (read+write) misses 1053system.cpu1.l2cache.demand_misses::total 131082 # number of demand (read+write) misses 1054system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 336 # number of overall misses 1055system.cpu1.l2cache.overall_misses::cpu1.itb.walker 270 # number of overall misses 1056system.cpu1.l2cache.overall_misses::cpu1.inst 13339 # number of overall misses 1057system.cpu1.l2cache.overall_misses::cpu1.data 117137 # number of overall misses 1058system.cpu1.l2cache.overall_misses::total 131082 # number of overall misses 1059system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3960 # number of ReadReq accesses(hits+misses) 1060system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2191 # number of ReadReq accesses(hits+misses) 1061system.cpu1.l2cache.ReadReq_accesses::total 6151 # number of ReadReq accesses(hits+misses) 1062system.cpu1.l2cache.WritebackDirty_accesses::writebacks 120975 # number of WritebackDirty accesses(hits+misses) 1063system.cpu1.l2cache.WritebackDirty_accesses::total 120975 # number of WritebackDirty accesses(hits+misses) 1064system.cpu1.l2cache.WritebackClean_accesses::writebacks 583053 # number of WritebackClean accesses(hits+misses) 1065system.cpu1.l2cache.WritebackClean_accesses::total 583053 # number of WritebackClean accesses(hits+misses) 1066system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28875 # number of UpgradeReq accesses(hits+misses) 1067system.cpu1.l2cache.UpgradeReq_accesses::total 28875 # number of UpgradeReq accesses(hits+misses) 1068system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22549 # number of SCUpgradeReq accesses(hits+misses) 1069system.cpu1.l2cache.SCUpgradeReq_accesses::total 22549 # number of SCUpgradeReq accesses(hits+misses) 1070system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63615 # number of ReadExReq accesses(hits+misses) 1071system.cpu1.l2cache.ReadExReq_accesses::total 63615 # number of ReadExReq accesses(hits+misses) 1072system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 523798 # number of ReadCleanReq accesses(hits+misses) 1073system.cpu1.l2cache.ReadCleanReq_accesses::total 523798 # number of ReadCleanReq accesses(hits+misses) 1074system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 172609 # number of ReadSharedReq accesses(hits+misses) 1075system.cpu1.l2cache.ReadSharedReq_accesses::total 172609 # number of ReadSharedReq accesses(hits+misses) 1076system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3960 # number of demand (read+write) accesses 1077system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2191 # number of demand (read+write) accesses 1078system.cpu1.l2cache.demand_accesses::cpu1.inst 523798 # number of demand (read+write) accesses 1079system.cpu1.l2cache.demand_accesses::cpu1.data 236224 # number of demand (read+write) accesses 1080system.cpu1.l2cache.demand_accesses::total 766173 # number of demand (read+write) accesses 1081system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3960 # number of overall (read+write) accesses 1082system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2191 # number of overall (read+write) accesses 1083system.cpu1.l2cache.overall_accesses::cpu1.inst 523798 # number of overall (read+write) accesses 1084system.cpu1.l2cache.overall_accesses::cpu1.data 236224 # number of overall (read+write) accesses 1085system.cpu1.l2cache.overall_accesses::total 766173 # number of overall (read+write) accesses 1086system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.084848 # miss rate for ReadReq accesses 1087system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.123231 # miss rate for ReadReq accesses 1088system.cpu1.l2cache.ReadReq_miss_rate::total 0.098521 # miss rate for ReadReq accesses 1089system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 1090system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 1091system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 1092system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1093system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.687982 # miss rate for ReadExReq accesses 1094system.cpu1.l2cache.ReadExReq_miss_rate::total 0.687982 # miss rate for ReadExReq accesses 1095system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.025466 # miss rate for ReadCleanReq accesses 1096system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.025466 # miss rate for ReadCleanReq accesses 1097system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.425071 # miss rate for ReadSharedReq accesses 1098system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.425071 # miss rate for ReadSharedReq accesses 1099system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.084848 # miss rate for demand accesses 1100system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.123231 # miss rate for demand accesses 1101system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.025466 # miss rate for demand accesses 1102system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.495873 # miss rate for demand accesses 1103system.cpu1.l2cache.demand_miss_rate::total 0.171087 # miss rate for demand accesses 1104system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.084848 # miss rate for overall accesses 1105system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.123231 # miss rate for overall accesses 1106system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.025466 # miss rate for overall accesses 1107system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.495873 # miss rate for overall accesses 1108system.cpu1.l2cache.overall_miss_rate::total 0.171087 # miss rate for overall accesses 1109system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1110system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1111system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1112system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1113system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1114system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1115system.cpu1.l2cache.writebacks::writebacks 32649 # number of writebacks 1116system.cpu1.l2cache.writebacks::total 32649 # number of writebacks 1117system.cpu1.toL2Bus.snoop_filter.tot_requests 1533187 # Total number of requests made to the snoop filter. 1118system.cpu1.toL2Bus.snoop_filter.hit_single_requests 773168 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1119system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11161 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1120system.cpu1.toL2Bus.snoop_filter.tot_snoops 166233 # Total number of snoops made to the snoop filter. 1121system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 164289 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1122system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1944 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1123system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1124system.cpu1.toL2Bus.trans_dist::ReadReq 12749 # Transaction distribution 1125system.cpu1.toL2Bus.trans_dist::ReadResp 709156 # Transaction distribution 1126system.cpu1.toL2Bus.trans_dist::WriteReq 2504 # Transaction distribution 1127system.cpu1.toL2Bus.trans_dist::WriteResp 2504 # Transaction distribution 1128system.cpu1.toL2Bus.trans_dist::WritebackDirty 120975 # Transaction distribution 1129system.cpu1.toL2Bus.trans_dist::WritebackClean 594214 # Transaction distribution 1130system.cpu1.toL2Bus.trans_dist::UpgradeReq 28875 # Transaction distribution 1131system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22549 # Transaction distribution 1132system.cpu1.toL2Bus.trans_dist::UpgradeResp 51424 # Transaction distribution 1133system.cpu1.toL2Bus.trans_dist::ReadExReq 63615 # Transaction distribution 1134system.cpu1.toL2Bus.trans_dist::ReadExResp 63615 # Transaction distribution 1135system.cpu1.toL2Bus.trans_dist::ReadCleanReq 523798 # Transaction distribution 1136system.cpu1.toL2Bus.trans_dist::ReadSharedReq 172609 # Transaction distribution 1137system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1571236 # Packet count per connected master and slave (bytes) 1138system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 778655 # Packet count per connected master and slave (bytes) 1139system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6616 # Packet count per connected master and slave (bytes) 1140system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 12080 # Packet count per connected master and slave (bytes) 1141system.cpu1.toL2Bus.pkt_count::total 2368587 # Packet count per connected master and slave (bytes) 1142system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 67014084 # Cumulative packet size per connected master and slave (bytes) 1143system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 27419302 # Cumulative packet size per connected master and slave (bytes) 1144system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13232 # Cumulative packet size per connected master and slave (bytes) 1145system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24160 # Cumulative packet size per connected master and slave (bytes) 1146system.cpu1.toL2Bus.pkt_size::total 94470778 # Cumulative packet size per connected master and slave (bytes) 1147system.cpu1.toL2Bus.snoops 347619 # Total snoops (count) 1148system.cpu1.toL2Bus.snoopTraffic 2342400 # Total snoop traffic (bytes) 1149system.cpu1.toL2Bus.snoop_fanout::samples 1819791 # Request fanout histogram 1150system.cpu1.toL2Bus.snoop_fanout::mean 0.108284 # Request fanout histogram 1151system.cpu1.toL2Bus.snoop_fanout::stdev 0.314158 # Request fanout histogram 1152system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1153system.cpu1.toL2Bus.snoop_fanout::0 1624681 89.28% 89.28% # Request fanout histogram 1154system.cpu1.toL2Bus.snoop_fanout::1 193166 10.61% 99.89% # Request fanout histogram 1155system.cpu1.toL2Bus.snoop_fanout::2 1944 0.11% 100.00% # Request fanout histogram 1156system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1157system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1158system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1159system.cpu1.toL2Bus.snoop_fanout::total 1819791 # Request fanout histogram 1160system.iobus.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1161system.iobus.trans_dist::ReadReq 30995 # Transaction distribution 1162system.iobus.trans_dist::ReadResp 30995 # Transaction distribution 1163system.iobus.trans_dist::WriteReq 59419 # Transaction distribution 1164system.iobus.trans_dist::WriteResp 59419 # Transaction distribution 1165system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56582 # Packet count per connected master and slave (bytes) 1166system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 1167system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 1168system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 1169system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 1170system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes) 1171system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes) 1172system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 1173system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1174system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1175system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1176system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 1177system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1178system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 1179system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 1180system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 1181system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 1182system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 1183system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 1184system.iobus.pkt_count_system.bridge.master::total 107876 # Packet count per connected master and slave (bytes) 1185system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes) 1186system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes) 1187system.iobus.pkt_count::total 180828 # Packet count per connected master and slave (bytes) 1188system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71526 # Cumulative packet size per connected master and slave (bytes) 1189system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 1190system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) 1191system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 1192system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 1193system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes) 1194system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes) 1195system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 1196system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1197system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1198system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1199system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 1200system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1201system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1202system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 1203system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 1204system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1205system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 1206system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 1207system.iobus.pkt_size_system.bridge.master::total 162766 # Cumulative packet size per connected master and slave (bytes) 1208system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) 1209system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) 1210system.iobus.pkt_size::total 2484014 # Cumulative packet size per connected master and slave (bytes) 1211system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1212system.iocache.tags.replacements 36442 # number of replacements 1213system.iocache.tags.tagsinuse 14.586086 # Cycle average of tags in use 1214system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1215system.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks. 1216system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1217system.iocache.tags.warmup_cycle 246641129509 # Cycle when the warmup percentage was hit. 1218system.iocache.tags.occ_blocks::realview.ide 14.586086 # Average occupied blocks per requestor 1219system.iocache.tags.occ_percent::realview.ide 0.911630 # Average percentage of cache occupancy 1220system.iocache.tags.occ_percent::total 0.911630 # Average percentage of cache occupancy 1221system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1222system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1223system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1224system.iocache.tags.tag_accesses 328284 # Number of tag accesses 1225system.iocache.tags.data_accesses 328284 # Number of data accesses 1226system.iocache.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1227system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses 1228system.iocache.ReadReq_misses::total 252 # number of ReadReq misses 1229system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 1230system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 1231system.iocache.demand_misses::realview.ide 36476 # number of demand (read+write) misses 1232system.iocache.demand_misses::total 36476 # number of demand (read+write) misses 1233system.iocache.overall_misses::realview.ide 36476 # number of overall misses 1234system.iocache.overall_misses::total 36476 # number of overall misses 1235system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) 1236system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) 1237system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 1238system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) 1239system.iocache.demand_accesses::realview.ide 36476 # number of demand (read+write) accesses 1240system.iocache.demand_accesses::total 36476 # number of demand (read+write) accesses 1241system.iocache.overall_accesses::realview.ide 36476 # number of overall (read+write) accesses 1242system.iocache.overall_accesses::total 36476 # number of overall (read+write) accesses 1243system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1244system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1245system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1246system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1247system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1248system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1249system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1250system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1251system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1252system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1253system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1254system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1255system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1256system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1257system.iocache.writebacks::writebacks 36190 # number of writebacks 1258system.iocache.writebacks::total 36190 # number of writebacks 1259system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1260system.l2c.tags.replacements 107708 # number of replacements 1261system.l2c.tags.tagsinuse 62491.556145 # Cycle average of tags in use 1262system.l2c.tags.total_refs 243932 # Total number of references to valid blocks. 1263system.l2c.tags.sampled_refs 168376 # Sample count of references to valid blocks. 1264system.l2c.tags.avg_refs 1.448734 # Average number of references to valid blocks. 1265system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1266system.l2c.tags.occ_blocks::writebacks 48154.057665 # Average occupied blocks per requestor 1267system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.929229 # Average occupied blocks per requestor 1268system.l2c.tags.occ_blocks::cpu0.itb.walker 0.998273 # Average occupied blocks per requestor 1269system.l2c.tags.occ_blocks::cpu0.inst 7781.790625 # Average occupied blocks per requestor 1270system.l2c.tags.occ_blocks::cpu0.data 4106.660422 # Average occupied blocks per requestor 1271system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.967503 # Average occupied blocks per requestor 1272system.l2c.tags.occ_blocks::cpu1.inst 1678.829831 # Average occupied blocks per requestor 1273system.l2c.tags.occ_blocks::cpu1.data 764.322598 # Average occupied blocks per requestor 1274system.l2c.tags.occ_percent::writebacks 0.734773 # Average percentage of cache occupancy 1275system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000060 # Average percentage of cache occupancy 1276system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy 1277system.l2c.tags.occ_percent::cpu0.inst 0.118741 # Average percentage of cache occupancy 1278system.l2c.tags.occ_percent::cpu0.data 0.062663 # Average percentage of cache occupancy 1279system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy 1280system.l2c.tags.occ_percent::cpu1.inst 0.025617 # Average percentage of cache occupancy 1281system.l2c.tags.occ_percent::cpu1.data 0.011663 # Average percentage of cache occupancy 1282system.l2c.tags.occ_percent::total 0.953545 # Average percentage of cache occupancy 1283system.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id 1284system.l2c.tags.occ_task_id_blocks::1024 60662 # Occupied blocks per task id 1285system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id 1286system.l2c.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id 1287system.l2c.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id 1288system.l2c.tags.age_task_id_blocks_1024::2 1796 # Occupied blocks per task id 1289system.l2c.tags.age_task_id_blocks_1024::3 13211 # Occupied blocks per task id 1290system.l2c.tags.age_task_id_blocks_1024::4 45580 # Occupied blocks per task id 1291system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id 1292system.l2c.tags.occ_task_id_percent::1024 0.925629 # Percentage of cache occupancy per task id 1293system.l2c.tags.tag_accesses 5178046 # Number of tag accesses 1294system.l2c.tags.data_accesses 5178046 # Number of data accesses 1295system.l2c.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1296system.l2c.WritebackDirty_hits::writebacks 225395 # number of WritebackDirty hits 1297system.l2c.WritebackDirty_hits::total 225395 # number of WritebackDirty hits 1298system.l2c.UpgradeReq_hits::cpu0.data 578 # number of UpgradeReq hits 1299system.l2c.UpgradeReq_hits::cpu1.data 107 # number of UpgradeReq hits 1300system.l2c.UpgradeReq_hits::total 685 # number of UpgradeReq hits 1301system.l2c.SCUpgradeReq_hits::cpu0.data 78 # number of SCUpgradeReq hits 1302system.l2c.SCUpgradeReq_hits::cpu1.data 52 # number of SCUpgradeReq hits 1303system.l2c.SCUpgradeReq_hits::total 130 # number of SCUpgradeReq hits 1304system.l2c.ReadExReq_hits::cpu0.data 13904 # number of ReadExReq hits 1305system.l2c.ReadExReq_hits::cpu1.data 3026 # number of ReadExReq hits 1306system.l2c.ReadExReq_hits::total 16930 # number of ReadExReq hits 1307system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 73 # number of ReadSharedReq hits 1308system.l2c.ReadSharedReq_hits::cpu0.itb.walker 78 # number of ReadSharedReq hits 1309system.l2c.ReadSharedReq_hits::cpu0.inst 25302 # number of ReadSharedReq hits 1310system.l2c.ReadSharedReq_hits::cpu0.data 75954 # number of ReadSharedReq hits 1311system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 40 # number of ReadSharedReq hits 1312system.l2c.ReadSharedReq_hits::cpu1.itb.walker 44 # number of ReadSharedReq hits 1313system.l2c.ReadSharedReq_hits::cpu1.inst 10936 # number of ReadSharedReq hits 1314system.l2c.ReadSharedReq_hits::cpu1.data 11571 # number of ReadSharedReq hits 1315system.l2c.ReadSharedReq_hits::total 123998 # number of ReadSharedReq hits 1316system.l2c.demand_hits::cpu0.dtb.walker 73 # number of demand (read+write) hits 1317system.l2c.demand_hits::cpu0.itb.walker 78 # number of demand (read+write) hits 1318system.l2c.demand_hits::cpu0.inst 25302 # number of demand (read+write) hits 1319system.l2c.demand_hits::cpu0.data 89858 # number of demand (read+write) hits 1320system.l2c.demand_hits::cpu1.dtb.walker 40 # number of demand (read+write) hits 1321system.l2c.demand_hits::cpu1.itb.walker 44 # number of demand (read+write) hits 1322system.l2c.demand_hits::cpu1.inst 10936 # number of demand (read+write) hits 1323system.l2c.demand_hits::cpu1.data 14597 # number of demand (read+write) hits 1324system.l2c.demand_hits::total 140928 # number of demand (read+write) hits 1325system.l2c.overall_hits::cpu0.dtb.walker 73 # number of overall hits 1326system.l2c.overall_hits::cpu0.itb.walker 78 # number of overall hits 1327system.l2c.overall_hits::cpu0.inst 25302 # number of overall hits 1328system.l2c.overall_hits::cpu0.data 89858 # number of overall hits 1329system.l2c.overall_hits::cpu1.dtb.walker 40 # number of overall hits 1330system.l2c.overall_hits::cpu1.itb.walker 44 # number of overall hits 1331system.l2c.overall_hits::cpu1.inst 10936 # number of overall hits 1332system.l2c.overall_hits::cpu1.data 14597 # number of overall hits 1333system.l2c.overall_hits::total 140928 # number of overall hits 1334system.l2c.UpgradeReq_misses::cpu0.data 9941 # number of UpgradeReq misses 1335system.l2c.UpgradeReq_misses::cpu1.data 3286 # number of UpgradeReq misses 1336system.l2c.UpgradeReq_misses::total 13227 # number of UpgradeReq misses 1337system.l2c.SCUpgradeReq_misses::cpu0.data 736 # number of SCUpgradeReq misses 1338system.l2c.SCUpgradeReq_misses::cpu1.data 1140 # number of SCUpgradeReq misses 1339system.l2c.SCUpgradeReq_misses::total 1876 # number of SCUpgradeReq misses 1340system.l2c.ReadExReq_misses::cpu0.data 136523 # number of ReadExReq misses 1341system.l2c.ReadExReq_misses::cpu1.data 15823 # number of ReadExReq misses 1342system.l2c.ReadExReq_misses::total 152346 # number of ReadExReq misses 1343system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 7 # number of ReadSharedReq misses 1344system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2 # number of ReadSharedReq misses 1345system.l2c.ReadSharedReq_misses::cpu0.inst 16724 # number of ReadSharedReq misses 1346system.l2c.ReadSharedReq_misses::cpu0.data 11220 # number of ReadSharedReq misses 1347system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1 # number of ReadSharedReq misses 1348system.l2c.ReadSharedReq_misses::cpu1.inst 2403 # number of ReadSharedReq misses 1349system.l2c.ReadSharedReq_misses::cpu1.data 1107 # number of ReadSharedReq misses 1350system.l2c.ReadSharedReq_misses::total 31464 # number of ReadSharedReq misses 1351system.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses 1352system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses 1353system.l2c.demand_misses::cpu0.inst 16724 # number of demand (read+write) misses 1354system.l2c.demand_misses::cpu0.data 147743 # number of demand (read+write) misses 1355system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses 1356system.l2c.demand_misses::cpu1.inst 2403 # number of demand (read+write) misses 1357system.l2c.demand_misses::cpu1.data 16930 # number of demand (read+write) misses 1358system.l2c.demand_misses::total 183810 # number of demand (read+write) misses 1359system.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses 1360system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses 1361system.l2c.overall_misses::cpu0.inst 16724 # number of overall misses 1362system.l2c.overall_misses::cpu0.data 147743 # number of overall misses 1363system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses 1364system.l2c.overall_misses::cpu1.inst 2403 # number of overall misses 1365system.l2c.overall_misses::cpu1.data 16930 # number of overall misses 1366system.l2c.overall_misses::total 183810 # number of overall misses 1367system.l2c.WritebackDirty_accesses::writebacks 225395 # number of WritebackDirty accesses(hits+misses) 1368system.l2c.WritebackDirty_accesses::total 225395 # number of WritebackDirty accesses(hits+misses) 1369system.l2c.UpgradeReq_accesses::cpu0.data 10519 # number of UpgradeReq accesses(hits+misses) 1370system.l2c.UpgradeReq_accesses::cpu1.data 3393 # number of UpgradeReq accesses(hits+misses) 1371system.l2c.UpgradeReq_accesses::total 13912 # number of UpgradeReq accesses(hits+misses) 1372system.l2c.SCUpgradeReq_accesses::cpu0.data 814 # number of SCUpgradeReq accesses(hits+misses) 1373system.l2c.SCUpgradeReq_accesses::cpu1.data 1192 # number of SCUpgradeReq accesses(hits+misses) 1374system.l2c.SCUpgradeReq_accesses::total 2006 # number of SCUpgradeReq accesses(hits+misses) 1375system.l2c.ReadExReq_accesses::cpu0.data 150427 # number of ReadExReq accesses(hits+misses) 1376system.l2c.ReadExReq_accesses::cpu1.data 18849 # number of ReadExReq accesses(hits+misses) 1377system.l2c.ReadExReq_accesses::total 169276 # number of ReadExReq accesses(hits+misses) 1378system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 80 # number of ReadSharedReq accesses(hits+misses) 1379system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 80 # number of ReadSharedReq accesses(hits+misses) 1380system.l2c.ReadSharedReq_accesses::cpu0.inst 42026 # number of ReadSharedReq accesses(hits+misses) 1381system.l2c.ReadSharedReq_accesses::cpu0.data 87174 # number of ReadSharedReq accesses(hits+misses) 1382system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 41 # number of ReadSharedReq accesses(hits+misses) 1383system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 44 # number of ReadSharedReq accesses(hits+misses) 1384system.l2c.ReadSharedReq_accesses::cpu1.inst 13339 # number of ReadSharedReq accesses(hits+misses) 1385system.l2c.ReadSharedReq_accesses::cpu1.data 12678 # number of ReadSharedReq accesses(hits+misses) 1386system.l2c.ReadSharedReq_accesses::total 155462 # number of ReadSharedReq accesses(hits+misses) 1387system.l2c.demand_accesses::cpu0.dtb.walker 80 # number of demand (read+write) accesses 1388system.l2c.demand_accesses::cpu0.itb.walker 80 # number of demand (read+write) accesses 1389system.l2c.demand_accesses::cpu0.inst 42026 # number of demand (read+write) accesses 1390system.l2c.demand_accesses::cpu0.data 237601 # number of demand (read+write) accesses 1391system.l2c.demand_accesses::cpu1.dtb.walker 41 # number of demand (read+write) accesses 1392system.l2c.demand_accesses::cpu1.itb.walker 44 # number of demand (read+write) accesses 1393system.l2c.demand_accesses::cpu1.inst 13339 # number of demand (read+write) accesses 1394system.l2c.demand_accesses::cpu1.data 31527 # number of demand (read+write) accesses 1395system.l2c.demand_accesses::total 324738 # number of demand (read+write) accesses 1396system.l2c.overall_accesses::cpu0.dtb.walker 80 # number of overall (read+write) accesses 1397system.l2c.overall_accesses::cpu0.itb.walker 80 # number of overall (read+write) accesses 1398system.l2c.overall_accesses::cpu0.inst 42026 # number of overall (read+write) accesses 1399system.l2c.overall_accesses::cpu0.data 237601 # number of overall (read+write) accesses 1400system.l2c.overall_accesses::cpu1.dtb.walker 41 # number of overall (read+write) accesses 1401system.l2c.overall_accesses::cpu1.itb.walker 44 # number of overall (read+write) accesses 1402system.l2c.overall_accesses::cpu1.inst 13339 # number of overall (read+write) accesses 1403system.l2c.overall_accesses::cpu1.data 31527 # number of overall (read+write) accesses 1404system.l2c.overall_accesses::total 324738 # number of overall (read+write) accesses 1405system.l2c.UpgradeReq_miss_rate::cpu0.data 0.945052 # miss rate for UpgradeReq accesses 1406system.l2c.UpgradeReq_miss_rate::cpu1.data 0.968464 # miss rate for UpgradeReq accesses 1407system.l2c.UpgradeReq_miss_rate::total 0.950762 # miss rate for UpgradeReq accesses 1408system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.904177 # miss rate for SCUpgradeReq accesses 1409system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.956376 # miss rate for SCUpgradeReq accesses 1410system.l2c.SCUpgradeReq_miss_rate::total 0.935194 # miss rate for SCUpgradeReq accesses 1411system.l2c.ReadExReq_miss_rate::cpu0.data 0.907570 # miss rate for ReadExReq accesses 1412system.l2c.ReadExReq_miss_rate::cpu1.data 0.839461 # miss rate for ReadExReq accesses 1413system.l2c.ReadExReq_miss_rate::total 0.899986 # miss rate for ReadExReq accesses 1414system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.087500 # miss rate for ReadSharedReq accesses 1415system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.025000 # miss rate for ReadSharedReq accesses 1416system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.397944 # miss rate for ReadSharedReq accesses 1417system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.128708 # miss rate for ReadSharedReq accesses 1418system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.024390 # miss rate for ReadSharedReq accesses 1419system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.180148 # miss rate for ReadSharedReq accesses 1420system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.087317 # miss rate for ReadSharedReq accesses 1421system.l2c.ReadSharedReq_miss_rate::total 0.202390 # miss rate for ReadSharedReq accesses 1422system.l2c.demand_miss_rate::cpu0.dtb.walker 0.087500 # miss rate for demand accesses 1423system.l2c.demand_miss_rate::cpu0.itb.walker 0.025000 # miss rate for demand accesses 1424system.l2c.demand_miss_rate::cpu0.inst 0.397944 # miss rate for demand accesses 1425system.l2c.demand_miss_rate::cpu0.data 0.621811 # miss rate for demand accesses 1426system.l2c.demand_miss_rate::cpu1.dtb.walker 0.024390 # miss rate for demand accesses 1427system.l2c.demand_miss_rate::cpu1.inst 0.180148 # miss rate for demand accesses 1428system.l2c.demand_miss_rate::cpu1.data 0.537000 # miss rate for demand accesses 1429system.l2c.demand_miss_rate::total 0.566026 # miss rate for demand accesses 1430system.l2c.overall_miss_rate::cpu0.dtb.walker 0.087500 # miss rate for overall accesses 1431system.l2c.overall_miss_rate::cpu0.itb.walker 0.025000 # miss rate for overall accesses 1432system.l2c.overall_miss_rate::cpu0.inst 0.397944 # miss rate for overall accesses 1433system.l2c.overall_miss_rate::cpu0.data 0.621811 # miss rate for overall accesses 1434system.l2c.overall_miss_rate::cpu1.dtb.walker 0.024390 # miss rate for overall accesses 1435system.l2c.overall_miss_rate::cpu1.inst 0.180148 # miss rate for overall accesses 1436system.l2c.overall_miss_rate::cpu1.data 0.537000 # miss rate for overall accesses 1437system.l2c.overall_miss_rate::total 0.566026 # miss rate for overall accesses 1438system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1439system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 1440system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 1441system.l2c.blocked::no_targets 0 # number of cycles access was blocked 1442system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1443system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1444system.l2c.writebacks::writebacks 96260 # number of writebacks 1445system.l2c.writebacks::total 96260 # number of writebacks 1446system.membus.snoop_filter.tot_requests 462665 # Total number of requests made to the snoop filter. 1447system.membus.snoop_filter.hit_single_requests 248104 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1448system.membus.snoop_filter.hit_multi_requests 501 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1449system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1450system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1451system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1452system.membus.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1453system.membus.trans_dist::ReadReq 43995 # Transaction distribution 1454system.membus.trans_dist::ReadResp 75711 # Transaction distribution 1455system.membus.trans_dist::WriteReq 30844 # Transaction distribution 1456system.membus.trans_dist::WriteResp 30844 # Transaction distribution 1457system.membus.trans_dist::WritebackDirty 132450 # Transaction distribution 1458system.membus.trans_dist::CleanEvict 8737 # Transaction distribution 1459system.membus.trans_dist::UpgradeReq 60370 # Transaction distribution 1460system.membus.trans_dist::SCUpgradeReq 40840 # Transaction distribution 1461system.membus.trans_dist::UpgradeResp 15528 # Transaction distribution 1462system.membus.trans_dist::ReadExReq 152316 # Transaction distribution 1463system.membus.trans_dist::ReadExResp 151921 # Transaction distribution 1464system.membus.trans_dist::ReadSharedReq 31716 # Transaction distribution 1465system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 1466system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution 1467system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107876 # Packet count per connected master and slave (bytes) 1468system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) 1469system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13468 # Packet count per connected master and slave (bytes) 1470system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 616948 # Packet count per connected master and slave (bytes) 1471system.membus.pkt_count_system.l2c.mem_side::total 738326 # Packet count per connected master and slave (bytes) 1472system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109394 # Packet count per connected master and slave (bytes) 1473system.membus.pkt_count_system.iocache.mem_side::total 109394 # Packet count per connected master and slave (bytes) 1474system.membus.pkt_count::total 847720 # Packet count per connected master and slave (bytes) 1475system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162766 # Cumulative packet size per connected master and slave (bytes) 1476system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) 1477system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26936 # Cumulative packet size per connected master and slave (bytes) 1478system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17953992 # Cumulative packet size per connected master and slave (bytes) 1479system.membus.pkt_size_system.l2c.mem_side::total 18143762 # Cumulative packet size per connected master and slave (bytes) 1480system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2332288 # Cumulative packet size per connected master and slave (bytes) 1481system.membus.pkt_size_system.iocache.mem_side::total 2332288 # Cumulative packet size per connected master and slave (bytes) 1482system.membus.pkt_size::total 20476050 # Cumulative packet size per connected master and slave (bytes) 1483system.membus.snoops 0 # Total snoops (count) 1484system.membus.snoopTraffic 0 # Total snoop traffic (bytes) 1485system.membus.snoop_fanout::samples 537492 # Request fanout histogram 1486system.membus.snoop_fanout::mean 0.010359 # Request fanout histogram 1487system.membus.snoop_fanout::stdev 0.101252 # Request fanout histogram 1488system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1489system.membus.snoop_fanout::0 531924 98.96% 98.96% # Request fanout histogram 1490system.membus.snoop_fanout::1 5568 1.04% 100.00% # Request fanout histogram 1491system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1492system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1493system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1494system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1495system.membus.snoop_fanout::total 537492 # Request fanout histogram 1496system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1497system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1498system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1499system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1500system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1501system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1502system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1503system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1504system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1505system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1506system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1507system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1508system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 1509system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1510system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1511system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1512system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1513system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1514system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1515system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1516system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1517system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1518system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1519system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 1520system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1521system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1522system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 1523system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1524system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1525system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 1526system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1527system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1528system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 1529system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1530system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1531system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 1532system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1533system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1534system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1535system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1536system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1537system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1538system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1539system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1540system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 1541system.realview.ethernet.droppedPackets 0 # number of packets dropped 1542system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1543system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1544system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1545system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1546system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1547system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1548system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1549system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 1550system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 1551system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 1552system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 1553system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1554system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1555system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1556system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1557system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1558system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1559system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1560system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1561system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1562system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1563system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1564system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1565system.toL2Bus.snoop_filter.tot_requests 862712 # Total number of requests made to the snoop filter. 1566system.toL2Bus.snoop_filter.hit_single_requests 444233 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1567system.toL2Bus.snoop_filter.hit_multi_requests 128693 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1568system.toL2Bus.snoop_filter.tot_snoops 9862 # Total number of snoops made to the snoop filter. 1569system.toL2Bus.snoop_filter.hit_single_snoops 9359 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1570system.toL2Bus.snoop_filter.hit_multi_snoops 503 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1571system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1572system.toL2Bus.trans_dist::ReadReq 43999 # Transaction distribution 1573system.toL2Bus.trans_dist::ReadResp 301604 # Transaction distribution 1574system.toL2Bus.trans_dist::WriteReq 30844 # Transaction distribution 1575system.toL2Bus.trans_dist::WriteResp 30844 # Transaction distribution 1576system.toL2Bus.trans_dist::WritebackDirty 225395 # Transaction distribution 1577system.toL2Bus.trans_dist::CleanEvict 64670 # Transaction distribution 1578system.toL2Bus.trans_dist::UpgradeReq 60630 # Transaction distribution 1579system.toL2Bus.trans_dist::SCUpgradeReq 40970 # Transaction distribution 1580system.toL2Bus.trans_dist::UpgradeResp 101600 # Transaction distribution 1581system.toL2Bus.trans_dist::ReadExReq 213426 # Transaction distribution 1582system.toL2Bus.trans_dist::ReadExResp 213426 # Transaction distribution 1583system.toL2Bus.trans_dist::ReadSharedReq 257605 # Transaction distribution 1584system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1162374 # Packet count per connected master and slave (bytes) 1585system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 422639 # Packet count per connected master and slave (bytes) 1586system.toL2Bus.pkt_count::total 1585013 # Packet count per connected master and slave (bytes) 1587system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34441336 # Cumulative packet size per connected master and slave (bytes) 1588system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10376426 # Cumulative packet size per connected master and slave (bytes) 1589system.toL2Bus.pkt_size::total 44817762 # Cumulative packet size per connected master and slave (bytes) 1590system.toL2Bus.snoops 113249 # Total snoops (count) 1591system.toL2Bus.snoopTraffic 6177216 # Total snoop traffic (bytes) 1592system.toL2Bus.snoop_fanout::samples 1050551 # Request fanout histogram 1593system.toL2Bus.snoop_fanout::mean 0.300796 # Request fanout histogram 1594system.toL2Bus.snoop_fanout::stdev 0.459647 # Request fanout histogram 1595system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1596system.toL2Bus.snoop_fanout::0 735052 69.97% 69.97% # Request fanout histogram 1597system.toL2Bus.snoop_fanout::1 314996 29.98% 99.95% # Request fanout histogram 1598system.toL2Bus.snoop_fanout::2 503 0.05% 100.00% # Request fanout histogram 1599system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1600system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1601system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1602system.toL2Bus.snoop_fanout::total 1050551 # Request fanout histogram 1603 1604---------- End Simulation Statistics ---------- 1605