stats.txt revision 10352:5f1f92bf76ee
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.900855 # Number of seconds simulated 4sim_ticks 900854787500 # Number of ticks simulated 5final_tick 900854787500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 875862 # Simulator instruction rate (inst/s) 8host_op_rate 1055198 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 12821864647 # Simulator tick rate (ticks/s) 10host_mem_usage 433912 # Number of bytes of host memory used 11host_seconds 70.26 # Real time elapsed on the host 12sim_insts 61537412 # Number of instructions simulated 13sim_ops 74137396 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 460108 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 6580092 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.inst 258564 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.data 2992120 # Number of bytes read from this memory 23system.physmem.bytes_read::total 49612932 # Number of bytes read from this memory 24system.physmem.bytes_inst_read::cpu0.inst 460108 # Number of instructions bytes read from this memory 25system.physmem.bytes_inst_read::cpu1.inst 258564 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::total 718672 # Number of instructions bytes read from this memory 27system.physmem.bytes_written::writebacks 4174784 # Number of bytes written to this memory 28system.physmem.bytes_written::cpu0.data 3027048 # Number of bytes written to this memory 29system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory 30system.physmem.bytes_written::total 7201872 # Number of bytes written to this memory 31system.physmem.num_reads::realview.clcd 4915200 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.inst 13417 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu0.data 102873 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu1.inst 4131 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu1.data 46770 # Number of read requests responded to by this memory 38system.physmem.num_reads::total 5082398 # Number of read requests responded to by this memory 39system.physmem.num_writes::writebacks 65231 # Number of write requests responded to by this memory 40system.physmem.num_writes::cpu0.data 756762 # Number of write requests responded to by this memory 41system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory 42system.physmem.num_writes::total 822003 # Number of write requests responded to by this memory 43system.physmem.bw_read::realview.clcd 43649210 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu0.dtb.walker 284 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::cpu0.itb.walker 213 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu0.inst 510746 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::cpu0.data 7304276 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::cpu1.inst 287021 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu1.data 3321423 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::total 55073173 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_inst_read::cpu0.inst 510746 # Instruction read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::cpu1.inst 287021 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_inst_read::total 797767 # Instruction read bandwidth from this memory (bytes/s) 54system.physmem.bw_write::writebacks 4634247 # Write bandwidth from this memory (bytes/s) 55system.physmem.bw_write::cpu0.data 3360195 # Write bandwidth from this memory (bytes/s) 56system.physmem.bw_write::cpu1.data 44 # Write bandwidth from this memory (bytes/s) 57system.physmem.bw_write::total 7994487 # Write bandwidth from this memory (bytes/s) 58system.physmem.bw_total::writebacks 4634247 # Total bandwidth to/from this memory (bytes/s) 59system.physmem.bw_total::realview.clcd 43649210 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::cpu0.dtb.walker 284 # Total bandwidth to/from this memory (bytes/s) 61system.physmem.bw_total::cpu0.itb.walker 213 # Total bandwidth to/from this memory (bytes/s) 62system.physmem.bw_total::cpu0.inst 510746 # Total bandwidth to/from this memory (bytes/s) 63system.physmem.bw_total::cpu0.data 10664471 # Total bandwidth to/from this memory (bytes/s) 64system.physmem.bw_total::cpu1.inst 287021 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::cpu1.data 3321468 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::total 63067661 # Total bandwidth to/from this memory (bytes/s) 67system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 68system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 69system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 70system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 71system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 72system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 73system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 74system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 75system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 76system.realview.nvmem.bw_read::cpu0.inst 22 # Total read bandwidth from this memory (bytes/s) 77system.realview.nvmem.bw_read::cpu1.inst 53 # Total read bandwidth from this memory (bytes/s) 78system.realview.nvmem.bw_read::total 75 # Total read bandwidth from this memory (bytes/s) 79system.realview.nvmem.bw_inst_read::cpu0.inst 22 # Instruction read bandwidth from this memory (bytes/s) 80system.realview.nvmem.bw_inst_read::cpu1.inst 53 # Instruction read bandwidth from this memory (bytes/s) 81system.realview.nvmem.bw_inst_read::total 75 # Instruction read bandwidth from this memory (bytes/s) 82system.realview.nvmem.bw_total::cpu0.inst 22 # Total bandwidth to/from this memory (bytes/s) 83system.realview.nvmem.bw_total::cpu1.inst 53 # Total bandwidth to/from this memory (bytes/s) 84system.realview.nvmem.bw_total::total 75 # Total bandwidth to/from this memory (bytes/s) 85system.membus.throughput 65740815 # Throughput (bytes/s) 86system.membus.data_through_bus 59222928 # Total data (bytes) 87system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 88system.cpu_clk_domain.clock 500 # Clock period in ticks 89system.l2c.tags.replacements 70256 # number of replacements 90system.l2c.tags.tagsinuse 51491.506872 # Cycle average of tags in use 91system.l2c.tags.total_refs 1633923 # Total number of references to valid blocks. 92system.l2c.tags.sampled_refs 135467 # Sample count of references to valid blocks. 93system.l2c.tags.avg_refs 12.061410 # Average number of references to valid blocks. 94system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 95system.l2c.tags.occ_blocks::writebacks 39155.338647 # Average occupied blocks per requestor 96system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.673377 # Average occupied blocks per requestor 97system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001056 # Average occupied blocks per requestor 98system.l2c.tags.occ_blocks::cpu0.inst 4830.605577 # Average occupied blocks per requestor 99system.l2c.tags.occ_blocks::cpu0.data 5154.208952 # Average occupied blocks per requestor 100system.l2c.tags.occ_blocks::cpu1.inst 1696.649192 # Average occupied blocks per requestor 101system.l2c.tags.occ_blocks::cpu1.data 652.030072 # Average occupied blocks per requestor 102system.l2c.tags.occ_percent::writebacks 0.597463 # Average percentage of cache occupancy 103system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000041 # Average percentage of cache occupancy 104system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy 105system.l2c.tags.occ_percent::cpu0.inst 0.073709 # Average percentage of cache occupancy 106system.l2c.tags.occ_percent::cpu0.data 0.078647 # Average percentage of cache occupancy 107system.l2c.tags.occ_percent::cpu1.inst 0.025889 # Average percentage of cache occupancy 108system.l2c.tags.occ_percent::cpu1.data 0.009949 # Average percentage of cache occupancy 109system.l2c.tags.occ_percent::total 0.785698 # Average percentage of cache occupancy 110system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id 111system.l2c.tags.occ_task_id_blocks::1024 65207 # Occupied blocks per task id 112system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id 113system.l2c.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id 114system.l2c.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id 115system.l2c.tags.age_task_id_blocks_1024::1 259 # Occupied blocks per task id 116system.l2c.tags.age_task_id_blocks_1024::2 3953 # Occupied blocks per task id 117system.l2c.tags.age_task_id_blocks_1024::3 12685 # Occupied blocks per task id 118system.l2c.tags.age_task_id_blocks_1024::4 48286 # Occupied blocks per task id 119system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id 120system.l2c.tags.occ_task_id_percent::1024 0.994980 # Percentage of cache occupancy per task id 121system.l2c.tags.tag_accesses 16963603 # Number of tag accesses 122system.l2c.tags.data_accesses 16963603 # Number of data accesses 123system.l2c.ReadReq_hits::cpu0.dtb.walker 4298 # number of ReadReq hits 124system.l2c.ReadReq_hits::cpu0.itb.walker 1596 # number of ReadReq hits 125system.l2c.ReadReq_hits::cpu0.inst 413244 # number of ReadReq hits 126system.l2c.ReadReq_hits::cpu0.data 202837 # number of ReadReq hits 127system.l2c.ReadReq_hits::cpu1.dtb.walker 4578 # number of ReadReq hits 128system.l2c.ReadReq_hits::cpu1.itb.walker 1943 # number of ReadReq hits 129system.l2c.ReadReq_hits::cpu1.inst 438543 # number of ReadReq hits 130system.l2c.ReadReq_hits::cpu1.data 146503 # number of ReadReq hits 131system.l2c.ReadReq_hits::total 1213542 # number of ReadReq hits 132system.l2c.Writeback_hits::writebacks 571726 # number of Writeback hits 133system.l2c.Writeback_hits::total 571726 # number of Writeback hits 134system.l2c.UpgradeReq_hits::cpu0.data 1266 # number of UpgradeReq hits 135system.l2c.UpgradeReq_hits::cpu1.data 397 # number of UpgradeReq hits 136system.l2c.UpgradeReq_hits::total 1663 # number of UpgradeReq hits 137system.l2c.SCUpgradeReq_hits::cpu0.data 238 # number of SCUpgradeReq hits 138system.l2c.SCUpgradeReq_hits::cpu1.data 38 # number of SCUpgradeReq hits 139system.l2c.SCUpgradeReq_hits::total 276 # number of SCUpgradeReq hits 140system.l2c.ReadExReq_hits::cpu0.data 51499 # number of ReadExReq hits 141system.l2c.ReadExReq_hits::cpu1.data 57148 # number of ReadExReq hits 142system.l2c.ReadExReq_hits::total 108647 # number of ReadExReq hits 143system.l2c.demand_hits::cpu0.dtb.walker 4298 # number of demand (read+write) hits 144system.l2c.demand_hits::cpu0.itb.walker 1596 # number of demand (read+write) hits 145system.l2c.demand_hits::cpu0.inst 413244 # number of demand (read+write) hits 146system.l2c.demand_hits::cpu0.data 254336 # number of demand (read+write) hits 147system.l2c.demand_hits::cpu1.dtb.walker 4578 # number of demand (read+write) hits 148system.l2c.demand_hits::cpu1.itb.walker 1943 # number of demand (read+write) hits 149system.l2c.demand_hits::cpu1.inst 438543 # number of demand (read+write) hits 150system.l2c.demand_hits::cpu1.data 203651 # number of demand (read+write) hits 151system.l2c.demand_hits::total 1322189 # number of demand (read+write) hits 152system.l2c.overall_hits::cpu0.dtb.walker 4298 # number of overall hits 153system.l2c.overall_hits::cpu0.itb.walker 1596 # number of overall hits 154system.l2c.overall_hits::cpu0.inst 413244 # number of overall hits 155system.l2c.overall_hits::cpu0.data 254336 # number of overall hits 156system.l2c.overall_hits::cpu1.dtb.walker 4578 # number of overall hits 157system.l2c.overall_hits::cpu1.itb.walker 1943 # number of overall hits 158system.l2c.overall_hits::cpu1.inst 438543 # number of overall hits 159system.l2c.overall_hits::cpu1.data 203651 # number of overall hits 160system.l2c.overall_hits::total 1322189 # number of overall hits 161system.l2c.ReadReq_misses::cpu0.dtb.walker 4 # number of ReadReq misses 162system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses 163system.l2c.ReadReq_misses::cpu0.inst 6774 # number of ReadReq misses 164system.l2c.ReadReq_misses::cpu0.data 9699 # number of ReadReq misses 165system.l2c.ReadReq_misses::cpu1.inst 4034 # number of ReadReq misses 166system.l2c.ReadReq_misses::cpu1.data 1828 # number of ReadReq misses 167system.l2c.ReadReq_misses::total 22342 # number of ReadReq misses 168system.l2c.UpgradeReq_misses::cpu0.data 2906 # number of UpgradeReq misses 169system.l2c.UpgradeReq_misses::cpu1.data 5033 # number of UpgradeReq misses 170system.l2c.UpgradeReq_misses::total 7939 # number of UpgradeReq misses 171system.l2c.SCUpgradeReq_misses::cpu0.data 414 # number of SCUpgradeReq misses 172system.l2c.SCUpgradeReq_misses::cpu1.data 662 # number of SCUpgradeReq misses 173system.l2c.SCUpgradeReq_misses::total 1076 # number of SCUpgradeReq misses 174system.l2c.ReadExReq_misses::cpu0.data 94027 # number of ReadExReq misses 175system.l2c.ReadExReq_misses::cpu1.data 46518 # number of ReadExReq misses 176system.l2c.ReadExReq_misses::total 140545 # number of ReadExReq misses 177system.l2c.demand_misses::cpu0.dtb.walker 4 # number of demand (read+write) misses 178system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses 179system.l2c.demand_misses::cpu0.inst 6774 # number of demand (read+write) misses 180system.l2c.demand_misses::cpu0.data 103726 # number of demand (read+write) misses 181system.l2c.demand_misses::cpu1.inst 4034 # number of demand (read+write) misses 182system.l2c.demand_misses::cpu1.data 48346 # number of demand (read+write) misses 183system.l2c.demand_misses::total 162887 # number of demand (read+write) misses 184system.l2c.overall_misses::cpu0.dtb.walker 4 # number of overall misses 185system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses 186system.l2c.overall_misses::cpu0.inst 6774 # number of overall misses 187system.l2c.overall_misses::cpu0.data 103726 # number of overall misses 188system.l2c.overall_misses::cpu1.inst 4034 # number of overall misses 189system.l2c.overall_misses::cpu1.data 48346 # number of overall misses 190system.l2c.overall_misses::total 162887 # number of overall misses 191system.l2c.ReadReq_accesses::cpu0.dtb.walker 4302 # number of ReadReq accesses(hits+misses) 192system.l2c.ReadReq_accesses::cpu0.itb.walker 1599 # number of ReadReq accesses(hits+misses) 193system.l2c.ReadReq_accesses::cpu0.inst 420018 # number of ReadReq accesses(hits+misses) 194system.l2c.ReadReq_accesses::cpu0.data 212536 # number of ReadReq accesses(hits+misses) 195system.l2c.ReadReq_accesses::cpu1.dtb.walker 4578 # number of ReadReq accesses(hits+misses) 196system.l2c.ReadReq_accesses::cpu1.itb.walker 1943 # number of ReadReq accesses(hits+misses) 197system.l2c.ReadReq_accesses::cpu1.inst 442577 # number of ReadReq accesses(hits+misses) 198system.l2c.ReadReq_accesses::cpu1.data 148331 # number of ReadReq accesses(hits+misses) 199system.l2c.ReadReq_accesses::total 1235884 # number of ReadReq accesses(hits+misses) 200system.l2c.Writeback_accesses::writebacks 571726 # number of Writeback accesses(hits+misses) 201system.l2c.Writeback_accesses::total 571726 # number of Writeback accesses(hits+misses) 202system.l2c.UpgradeReq_accesses::cpu0.data 4172 # number of UpgradeReq accesses(hits+misses) 203system.l2c.UpgradeReq_accesses::cpu1.data 5430 # number of UpgradeReq accesses(hits+misses) 204system.l2c.UpgradeReq_accesses::total 9602 # number of UpgradeReq accesses(hits+misses) 205system.l2c.SCUpgradeReq_accesses::cpu0.data 652 # number of SCUpgradeReq accesses(hits+misses) 206system.l2c.SCUpgradeReq_accesses::cpu1.data 700 # number of SCUpgradeReq accesses(hits+misses) 207system.l2c.SCUpgradeReq_accesses::total 1352 # number of SCUpgradeReq accesses(hits+misses) 208system.l2c.ReadExReq_accesses::cpu0.data 145526 # number of ReadExReq accesses(hits+misses) 209system.l2c.ReadExReq_accesses::cpu1.data 103666 # number of ReadExReq accesses(hits+misses) 210system.l2c.ReadExReq_accesses::total 249192 # number of ReadExReq accesses(hits+misses) 211system.l2c.demand_accesses::cpu0.dtb.walker 4302 # number of demand (read+write) accesses 212system.l2c.demand_accesses::cpu0.itb.walker 1599 # number of demand (read+write) accesses 213system.l2c.demand_accesses::cpu0.inst 420018 # number of demand (read+write) accesses 214system.l2c.demand_accesses::cpu0.data 358062 # number of demand (read+write) accesses 215system.l2c.demand_accesses::cpu1.dtb.walker 4578 # number of demand (read+write) accesses 216system.l2c.demand_accesses::cpu1.itb.walker 1943 # number of demand (read+write) accesses 217system.l2c.demand_accesses::cpu1.inst 442577 # number of demand (read+write) accesses 218system.l2c.demand_accesses::cpu1.data 251997 # number of demand (read+write) accesses 219system.l2c.demand_accesses::total 1485076 # number of demand (read+write) accesses 220system.l2c.overall_accesses::cpu0.dtb.walker 4302 # number of overall (read+write) accesses 221system.l2c.overall_accesses::cpu0.itb.walker 1599 # number of overall (read+write) accesses 222system.l2c.overall_accesses::cpu0.inst 420018 # number of overall (read+write) accesses 223system.l2c.overall_accesses::cpu0.data 358062 # number of overall (read+write) accesses 224system.l2c.overall_accesses::cpu1.dtb.walker 4578 # number of overall (read+write) accesses 225system.l2c.overall_accesses::cpu1.itb.walker 1943 # number of overall (read+write) accesses 226system.l2c.overall_accesses::cpu1.inst 442577 # number of overall (read+write) accesses 227system.l2c.overall_accesses::cpu1.data 251997 # number of overall (read+write) accesses 228system.l2c.overall_accesses::total 1485076 # number of overall (read+write) accesses 229system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000930 # miss rate for ReadReq accesses 230system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001876 # miss rate for ReadReq accesses 231system.l2c.ReadReq_miss_rate::cpu0.inst 0.016128 # miss rate for ReadReq accesses 232system.l2c.ReadReq_miss_rate::cpu0.data 0.045635 # miss rate for ReadReq accesses 233system.l2c.ReadReq_miss_rate::cpu1.inst 0.009115 # miss rate for ReadReq accesses 234system.l2c.ReadReq_miss_rate::cpu1.data 0.012324 # miss rate for ReadReq accesses 235system.l2c.ReadReq_miss_rate::total 0.018078 # miss rate for ReadReq accesses 236system.l2c.UpgradeReq_miss_rate::cpu0.data 0.696548 # miss rate for UpgradeReq accesses 237system.l2c.UpgradeReq_miss_rate::cpu1.data 0.926888 # miss rate for UpgradeReq accesses 238system.l2c.UpgradeReq_miss_rate::total 0.826807 # miss rate for UpgradeReq accesses 239system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.634969 # miss rate for SCUpgradeReq accesses 240system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.945714 # miss rate for SCUpgradeReq accesses 241system.l2c.SCUpgradeReq_miss_rate::total 0.795858 # miss rate for SCUpgradeReq accesses 242system.l2c.ReadExReq_miss_rate::cpu0.data 0.646118 # miss rate for ReadExReq accesses 243system.l2c.ReadExReq_miss_rate::cpu1.data 0.448730 # miss rate for ReadExReq accesses 244system.l2c.ReadExReq_miss_rate::total 0.564003 # miss rate for ReadExReq accesses 245system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000930 # miss rate for demand accesses 246system.l2c.demand_miss_rate::cpu0.itb.walker 0.001876 # miss rate for demand accesses 247system.l2c.demand_miss_rate::cpu0.inst 0.016128 # miss rate for demand accesses 248system.l2c.demand_miss_rate::cpu0.data 0.289687 # miss rate for demand accesses 249system.l2c.demand_miss_rate::cpu1.inst 0.009115 # miss rate for demand accesses 250system.l2c.demand_miss_rate::cpu1.data 0.191851 # miss rate for demand accesses 251system.l2c.demand_miss_rate::total 0.109683 # miss rate for demand accesses 252system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000930 # miss rate for overall accesses 253system.l2c.overall_miss_rate::cpu0.itb.walker 0.001876 # miss rate for overall accesses 254system.l2c.overall_miss_rate::cpu0.inst 0.016128 # miss rate for overall accesses 255system.l2c.overall_miss_rate::cpu0.data 0.289687 # miss rate for overall accesses 256system.l2c.overall_miss_rate::cpu1.inst 0.009115 # miss rate for overall accesses 257system.l2c.overall_miss_rate::cpu1.data 0.191851 # miss rate for overall accesses 258system.l2c.overall_miss_rate::total 0.109683 # miss rate for overall accesses 259system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 260system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 261system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 262system.l2c.blocked::no_targets 0 # number of cycles access was blocked 263system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 264system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 265system.l2c.fast_writes 0 # number of fast writes performed 266system.l2c.cache_copies 0 # number of cache copies performed 267system.l2c.writebacks::writebacks 65231 # number of writebacks 268system.l2c.writebacks::total 65231 # number of writebacks 269system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 270system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 271system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 272system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 273system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 274system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 275system.cf0.dma_write_txs 0 # Number of DMA write transactions. 276system.toL2Bus.throughput 156214740 # Throughput (bytes/s) 277system.toL2Bus.data_through_bus 140726796 # Total data (bytes) 278system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 279system.iobus.throughput 46301771 # Throughput (bytes/s) 280system.iobus.data_through_bus 41711172 # Total data (bytes) 281system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 282system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 283system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 284system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 285system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 286system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 287system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 288system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 289system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 290system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 291system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 292system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 293system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 294system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 295system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 296system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 297system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 298system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 299system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 300system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 301system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 302system.cpu0.dtb.inst_hits 0 # ITB inst hits 303system.cpu0.dtb.inst_misses 0 # ITB inst misses 304system.cpu0.dtb.read_hits 7391669 # DTB read hits 305system.cpu0.dtb.read_misses 1915 # DTB read misses 306system.cpu0.dtb.write_hits 6659638 # DTB write hits 307system.cpu0.dtb.write_misses 1130 # DTB write misses 308system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 309system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 310system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 311system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 312system.cpu0.dtb.flush_entries 1223 # Number of entries that have been flushed from TLB 313system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 314system.cpu0.dtb.prefetch_faults 84 # Number of TLB faults due to prefetch 315system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 316system.cpu0.dtb.perms_faults 185 # Number of TLB faults due to permissions restrictions 317system.cpu0.dtb.read_accesses 7393584 # DTB read accesses 318system.cpu0.dtb.write_accesses 6660768 # DTB write accesses 319system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 320system.cpu0.dtb.hits 14051307 # DTB hits 321system.cpu0.dtb.misses 3045 # DTB misses 322system.cpu0.dtb.accesses 14054352 # DTB accesses 323system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 324system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 325system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 326system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 327system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 328system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 329system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 330system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 331system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 332system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 333system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 334system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 335system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 336system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 337system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 338system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 339system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 340system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 341system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 342system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 343system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 344system.cpu0.itb.inst_hits 37936012 # ITB inst hits 345system.cpu0.itb.inst_misses 1207 # ITB inst misses 346system.cpu0.itb.read_hits 0 # DTB read hits 347system.cpu0.itb.read_misses 0 # DTB read misses 348system.cpu0.itb.write_hits 0 # DTB write hits 349system.cpu0.itb.write_misses 0 # DTB write misses 350system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 351system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 352system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 353system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 354system.cpu0.itb.flush_entries 848 # Number of entries that have been flushed from TLB 355system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 356system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 357system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 358system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 359system.cpu0.itb.read_accesses 0 # DTB read accesses 360system.cpu0.itb.write_accesses 0 # DTB write accesses 361system.cpu0.itb.inst_accesses 37937219 # ITB inst accesses 362system.cpu0.itb.hits 37936012 # DTB hits 363system.cpu0.itb.misses 1207 # DTB misses 364system.cpu0.itb.accesses 37937219 # DTB accesses 365system.cpu0.numCycles 1801227301 # number of cpu cycles simulated 366system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 367system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 368system.cpu0.committedInsts 37698803 # Number of instructions committed 369system.cpu0.committedOps 44946380 # Number of ops (including micro ops) committed 370system.cpu0.num_int_alu_accesses 39863943 # Number of integer alu accesses 371system.cpu0.num_fp_alu_accesses 4171 # Number of float alu accesses 372system.cpu0.num_func_calls 1205467 # number of times a function call or return occured 373system.cpu0.num_conditional_control_insts 4697957 # number of instructions that are conditional controls 374system.cpu0.num_int_insts 39863943 # number of integer instructions 375system.cpu0.num_fp_insts 4171 # number of float instructions 376system.cpu0.num_int_register_reads 70363299 # number of times the integer registers were read 377system.cpu0.num_int_register_writes 26108579 # number of times the integer registers were written 378system.cpu0.num_fp_register_reads 3915 # number of times the floating registers were read 379system.cpu0.num_fp_register_writes 256 # number of times the floating registers were written 380system.cpu0.num_cc_register_reads 134797325 # number of times the CC registers were read 381system.cpu0.num_cc_register_writes 18388517 # number of times the CC registers were written 382system.cpu0.num_mem_refs 14597479 # number of memory refs 383system.cpu0.num_load_insts 7571296 # Number of load instructions 384system.cpu0.num_store_insts 7026183 # Number of store instructions 385system.cpu0.num_idle_cycles 1756006001.161348 # Number of idle cycles 386system.cpu0.num_busy_cycles 45221299.838652 # Number of busy cycles 387system.cpu0.not_idle_fraction 0.025106 # Percentage of non-idle cycles 388system.cpu0.idle_fraction 0.974894 # Percentage of idle cycles 389system.cpu0.Branches 6054325 # Number of branches fetched 390system.cpu0.op_class::No_OpClass 13280 0.03% 0.03% # Class of executed instruction 391system.cpu0.op_class::IntAlu 30338974 67.42% 67.45% # Class of executed instruction 392system.cpu0.op_class::IntMult 51765 0.12% 67.56% # Class of executed instruction 393system.cpu0.op_class::IntDiv 0 0.00% 67.56% # Class of executed instruction 394system.cpu0.op_class::FloatAdd 0 0.00% 67.56% # Class of executed instruction 395system.cpu0.op_class::FloatCmp 0 0.00% 67.56% # Class of executed instruction 396system.cpu0.op_class::FloatCvt 0 0.00% 67.56% # Class of executed instruction 397system.cpu0.op_class::FloatMult 0 0.00% 67.56% # Class of executed instruction 398system.cpu0.op_class::FloatDiv 0 0.00% 67.56% # Class of executed instruction 399system.cpu0.op_class::FloatSqrt 0 0.00% 67.56% # Class of executed instruction 400system.cpu0.op_class::SimdAdd 0 0.00% 67.56% # Class of executed instruction 401system.cpu0.op_class::SimdAddAcc 0 0.00% 67.56% # Class of executed instruction 402system.cpu0.op_class::SimdAlu 0 0.00% 67.56% # Class of executed instruction 403system.cpu0.op_class::SimdCmp 0 0.00% 67.56% # Class of executed instruction 404system.cpu0.op_class::SimdCvt 0 0.00% 67.56% # Class of executed instruction 405system.cpu0.op_class::SimdMisc 0 0.00% 67.56% # Class of executed instruction 406system.cpu0.op_class::SimdMult 0 0.00% 67.56% # Class of executed instruction 407system.cpu0.op_class::SimdMultAcc 0 0.00% 67.56% # Class of executed instruction 408system.cpu0.op_class::SimdShift 0 0.00% 67.56% # Class of executed instruction 409system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.56% # Class of executed instruction 410system.cpu0.op_class::SimdSqrt 0 0.00% 67.56% # Class of executed instruction 411system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.56% # Class of executed instruction 412system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.56% # Class of executed instruction 413system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.56% # Class of executed instruction 414system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.56% # Class of executed instruction 415system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.56% # Class of executed instruction 416system.cpu0.op_class::SimdFloatMisc 639 0.00% 67.56% # Class of executed instruction 417system.cpu0.op_class::SimdFloatMult 0 0.00% 67.56% # Class of executed instruction 418system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.56% # Class of executed instruction 419system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.56% # Class of executed instruction 420system.cpu0.op_class::MemRead 7571296 16.82% 84.39% # Class of executed instruction 421system.cpu0.op_class::MemWrite 7026183 15.61% 100.00% # Class of executed instruction 422system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 423system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 424system.cpu0.op_class::total 45002137 # Class of executed instruction 425system.cpu0.kern.inst.arm 0 # number of arm instructions executed 426system.cpu0.kern.inst.quiesce 42773 # number of quiesce instructions executed 427system.cpu0.icache.tags.replacements 419775 # number of replacements 428system.cpu0.icache.tags.tagsinuse 511.035896 # Cycle average of tags in use 429system.cpu0.icache.tags.total_refs 37516680 # Total number of references to valid blocks. 430system.cpu0.icache.tags.sampled_refs 420287 # Sample count of references to valid blocks. 431system.cpu0.icache.tags.avg_refs 89.264431 # Average number of references to valid blocks. 432system.cpu0.icache.tags.warmup_cycle 64363581500 # Cycle when the warmup percentage was hit. 433system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.035896 # Average occupied blocks per requestor 434system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998117 # Average percentage of cache occupancy 435system.cpu0.icache.tags.occ_percent::total 0.998117 # Average percentage of cache occupancy 436system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 437system.cpu0.icache.tags.age_task_id_blocks_1024::2 508 # Occupied blocks per task id 438system.cpu0.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id 439system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 440system.cpu0.icache.tags.tag_accesses 38357256 # Number of tag accesses 441system.cpu0.icache.tags.data_accesses 38357256 # Number of data accesses 442system.cpu0.icache.ReadReq_hits::cpu0.inst 37516680 # number of ReadReq hits 443system.cpu0.icache.ReadReq_hits::total 37516680 # number of ReadReq hits 444system.cpu0.icache.demand_hits::cpu0.inst 37516680 # number of demand (read+write) hits 445system.cpu0.icache.demand_hits::total 37516680 # number of demand (read+write) hits 446system.cpu0.icache.overall_hits::cpu0.inst 37516680 # number of overall hits 447system.cpu0.icache.overall_hits::total 37516680 # number of overall hits 448system.cpu0.icache.ReadReq_misses::cpu0.inst 420288 # number of ReadReq misses 449system.cpu0.icache.ReadReq_misses::total 420288 # number of ReadReq misses 450system.cpu0.icache.demand_misses::cpu0.inst 420288 # number of demand (read+write) misses 451system.cpu0.icache.demand_misses::total 420288 # number of demand (read+write) misses 452system.cpu0.icache.overall_misses::cpu0.inst 420288 # number of overall misses 453system.cpu0.icache.overall_misses::total 420288 # number of overall misses 454system.cpu0.icache.ReadReq_accesses::cpu0.inst 37936968 # number of ReadReq accesses(hits+misses) 455system.cpu0.icache.ReadReq_accesses::total 37936968 # number of ReadReq accesses(hits+misses) 456system.cpu0.icache.demand_accesses::cpu0.inst 37936968 # number of demand (read+write) accesses 457system.cpu0.icache.demand_accesses::total 37936968 # number of demand (read+write) accesses 458system.cpu0.icache.overall_accesses::cpu0.inst 37936968 # number of overall (read+write) accesses 459system.cpu0.icache.overall_accesses::total 37936968 # number of overall (read+write) accesses 460system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011079 # miss rate for ReadReq accesses 461system.cpu0.icache.ReadReq_miss_rate::total 0.011079 # miss rate for ReadReq accesses 462system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011079 # miss rate for demand accesses 463system.cpu0.icache.demand_miss_rate::total 0.011079 # miss rate for demand accesses 464system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011079 # miss rate for overall accesses 465system.cpu0.icache.overall_miss_rate::total 0.011079 # miss rate for overall accesses 466system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 467system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 468system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 469system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 470system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 471system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 472system.cpu0.icache.fast_writes 0 # number of fast writes performed 473system.cpu0.icache.cache_copies 0 # number of cache copies performed 474system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 475system.cpu0.dcache.tags.replacements 348431 # number of replacements 476system.cpu0.dcache.tags.tagsinuse 471.119339 # Cycle average of tags in use 477system.cpu0.dcache.tags.total_refs 12834011 # Total number of references to valid blocks. 478system.cpu0.dcache.tags.sampled_refs 348738 # Sample count of references to valid blocks. 479system.cpu0.dcache.tags.avg_refs 36.801298 # Average number of references to valid blocks. 480system.cpu0.dcache.tags.warmup_cycle 22109000 # Cycle when the warmup percentage was hit. 481system.cpu0.dcache.tags.occ_blocks::cpu0.data 471.119339 # Average occupied blocks per requestor 482system.cpu0.dcache.tags.occ_percent::cpu0.data 0.920155 # Average percentage of cache occupancy 483system.cpu0.dcache.tags.occ_percent::total 0.920155 # Average percentage of cache occupancy 484system.cpu0.dcache.tags.occ_task_id_blocks::1024 307 # Occupied blocks per task id 485system.cpu0.dcache.tags.age_task_id_blocks_1024::2 307 # Occupied blocks per task id 486system.cpu0.dcache.tags.occ_task_id_percent::1024 0.599609 # Percentage of cache occupancy per task id 487system.cpu0.dcache.tags.tag_accesses 53249455 # Number of tag accesses 488system.cpu0.dcache.tags.data_accesses 53249455 # Number of data accesses 489system.cpu0.dcache.ReadReq_hits::cpu0.data 6868875 # number of ReadReq hits 490system.cpu0.dcache.ReadReq_hits::total 6868875 # number of ReadReq hits 491system.cpu0.dcache.WriteReq_hits::cpu0.data 5598061 # number of WriteReq hits 492system.cpu0.dcache.WriteReq_hits::total 5598061 # number of WriteReq hits 493system.cpu0.dcache.SoftPFReq_hits::cpu0.data 78744 # number of SoftPFReq hits 494system.cpu0.dcache.SoftPFReq_hits::total 78744 # number of SoftPFReq hits 495system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 135195 # number of LoadLockedReq hits 496system.cpu0.dcache.LoadLockedReq_hits::total 135195 # number of LoadLockedReq hits 497system.cpu0.dcache.StoreCondReq_hits::cpu0.data 136387 # number of StoreCondReq hits 498system.cpu0.dcache.StoreCondReq_hits::total 136387 # number of StoreCondReq hits 499system.cpu0.dcache.demand_hits::cpu0.data 12466936 # number of demand (read+write) hits 500system.cpu0.dcache.demand_hits::total 12466936 # number of demand (read+write) hits 501system.cpu0.dcache.overall_hits::cpu0.data 12545680 # number of overall hits 502system.cpu0.dcache.overall_hits::total 12545680 # number of overall hits 503system.cpu0.dcache.ReadReq_misses::cpu0.data 173318 # number of ReadReq misses 504system.cpu0.dcache.ReadReq_misses::total 173318 # number of ReadReq misses 505system.cpu0.dcache.WriteReq_misses::cpu0.data 159147 # number of WriteReq misses 506system.cpu0.dcache.WriteReq_misses::total 159147 # number of WriteReq misses 507system.cpu0.dcache.SoftPFReq_misses::cpu0.data 50343 # number of SoftPFReq misses 508system.cpu0.dcache.SoftPFReq_misses::total 50343 # number of SoftPFReq misses 509system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9388 # number of LoadLockedReq misses 510system.cpu0.dcache.LoadLockedReq_misses::total 9388 # number of LoadLockedReq misses 511system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7646 # number of StoreCondReq misses 512system.cpu0.dcache.StoreCondReq_misses::total 7646 # number of StoreCondReq misses 513system.cpu0.dcache.demand_misses::cpu0.data 332465 # number of demand (read+write) misses 514system.cpu0.dcache.demand_misses::total 332465 # number of demand (read+write) misses 515system.cpu0.dcache.overall_misses::cpu0.data 382808 # number of overall misses 516system.cpu0.dcache.overall_misses::total 382808 # number of overall misses 517system.cpu0.dcache.ReadReq_accesses::cpu0.data 7042193 # number of ReadReq accesses(hits+misses) 518system.cpu0.dcache.ReadReq_accesses::total 7042193 # number of ReadReq accesses(hits+misses) 519system.cpu0.dcache.WriteReq_accesses::cpu0.data 5757208 # number of WriteReq accesses(hits+misses) 520system.cpu0.dcache.WriteReq_accesses::total 5757208 # number of WriteReq accesses(hits+misses) 521system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 129087 # number of SoftPFReq accesses(hits+misses) 522system.cpu0.dcache.SoftPFReq_accesses::total 129087 # number of SoftPFReq accesses(hits+misses) 523system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 144583 # number of LoadLockedReq accesses(hits+misses) 524system.cpu0.dcache.LoadLockedReq_accesses::total 144583 # number of LoadLockedReq accesses(hits+misses) 525system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144033 # number of StoreCondReq accesses(hits+misses) 526system.cpu0.dcache.StoreCondReq_accesses::total 144033 # number of StoreCondReq accesses(hits+misses) 527system.cpu0.dcache.demand_accesses::cpu0.data 12799401 # number of demand (read+write) accesses 528system.cpu0.dcache.demand_accesses::total 12799401 # number of demand (read+write) accesses 529system.cpu0.dcache.overall_accesses::cpu0.data 12928488 # number of overall (read+write) accesses 530system.cpu0.dcache.overall_accesses::total 12928488 # number of overall (read+write) accesses 531system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.024611 # miss rate for ReadReq accesses 532system.cpu0.dcache.ReadReq_miss_rate::total 0.024611 # miss rate for ReadReq accesses 533system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027643 # miss rate for WriteReq accesses 534system.cpu0.dcache.WriteReq_miss_rate::total 0.027643 # miss rate for WriteReq accesses 535system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.389993 # miss rate for SoftPFReq accesses 536system.cpu0.dcache.SoftPFReq_miss_rate::total 0.389993 # miss rate for SoftPFReq accesses 537system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064932 # miss rate for LoadLockedReq accesses 538system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064932 # miss rate for LoadLockedReq accesses 539system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053085 # miss rate for StoreCondReq accesses 540system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053085 # miss rate for StoreCondReq accesses 541system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025975 # miss rate for demand accesses 542system.cpu0.dcache.demand_miss_rate::total 0.025975 # miss rate for demand accesses 543system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029610 # miss rate for overall accesses 544system.cpu0.dcache.overall_miss_rate::total 0.029610 # miss rate for overall accesses 545system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 546system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 547system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 548system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 549system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 550system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 551system.cpu0.dcache.fast_writes 0 # number of fast writes performed 552system.cpu0.dcache.cache_copies 0 # number of cache copies performed 553system.cpu0.dcache.writebacks::writebacks 321785 # number of writebacks 554system.cpu0.dcache.writebacks::total 321785 # number of writebacks 555system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 556system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 557system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 558system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 559system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 560system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 561system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 562system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 563system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 564system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 565system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 566system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 567system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 568system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 569system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 570system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 571system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 572system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 573system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 574system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 575system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 576system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 577system.cpu1.dtb.inst_hits 0 # ITB inst hits 578system.cpu1.dtb.inst_misses 0 # ITB inst misses 579system.cpu1.dtb.read_hits 6028686 # DTB read hits 580system.cpu1.dtb.read_misses 5403 # DTB read misses 581system.cpu1.dtb.write_hits 4781604 # DTB write hits 582system.cpu1.dtb.write_misses 1104 # DTB write misses 583system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 584system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 585system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 586system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 587system.cpu1.dtb.flush_entries 2367 # Number of entries that have been flushed from TLB 588system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 589system.cpu1.dtb.prefetch_faults 185 # Number of TLB faults due to prefetch 590system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 591system.cpu1.dtb.perms_faults 267 # Number of TLB faults due to permissions restrictions 592system.cpu1.dtb.read_accesses 6034089 # DTB read accesses 593system.cpu1.dtb.write_accesses 4782708 # DTB write accesses 594system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 595system.cpu1.dtb.hits 10810290 # DTB hits 596system.cpu1.dtb.misses 6507 # DTB misses 597system.cpu1.dtb.accesses 10816797 # DTB accesses 598system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 599system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 600system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 601system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 602system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 603system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 604system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 605system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 606system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 607system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 608system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 609system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 610system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 611system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 612system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 613system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 614system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 615system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 616system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 617system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 618system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 619system.cpu1.itb.inst_hits 24626141 # ITB inst hits 620system.cpu1.itb.inst_misses 3166 # ITB inst misses 621system.cpu1.itb.read_hits 0 # DTB read hits 622system.cpu1.itb.read_misses 0 # DTB read misses 623system.cpu1.itb.write_hits 0 # DTB write hits 624system.cpu1.itb.write_misses 0 # DTB write misses 625system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 626system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 627system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 628system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 629system.cpu1.itb.flush_entries 1581 # Number of entries that have been flushed from TLB 630system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 631system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 632system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 633system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 634system.cpu1.itb.read_accesses 0 # DTB read accesses 635system.cpu1.itb.write_accesses 0 # DTB write accesses 636system.cpu1.itb.inst_accesses 24629307 # ITB inst accesses 637system.cpu1.itb.hits 24626141 # DTB hits 638system.cpu1.itb.misses 3166 # DTB misses 639system.cpu1.itb.accesses 24629307 # DTB accesses 640system.cpu1.numCycles 1801709576 # number of cpu cycles simulated 641system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 642system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 643system.cpu1.committedInsts 23838609 # Number of instructions committed 644system.cpu1.committedOps 29191016 # Number of ops (including micro ops) committed 645system.cpu1.num_int_alu_accesses 25547086 # Number of integer alu accesses 646system.cpu1.num_fp_alu_accesses 5650 # Number of float alu accesses 647system.cpu1.num_func_calls 987842 # number of times a function call or return occured 648system.cpu1.num_conditional_control_insts 2987341 # number of instructions that are conditional controls 649system.cpu1.num_int_insts 25547086 # number of integer instructions 650system.cpu1.num_fp_insts 5650 # number of float instructions 651system.cpu1.num_int_register_reads 48277330 # number of times the integer registers were read 652system.cpu1.num_int_register_writes 17495174 # number of times the integer registers were written 653system.cpu1.num_fp_register_reads 3706 # number of times the floating registers were read 654system.cpu1.num_fp_register_writes 1948 # number of times the floating registers were written 655system.cpu1.num_cc_register_reads 86963152 # number of times the CC registers were read 656system.cpu1.num_cc_register_writes 11050350 # number of times the CC registers were written 657system.cpu1.num_mem_refs 11165955 # number of memory refs 658system.cpu1.num_load_insts 6206289 # Number of load instructions 659system.cpu1.num_store_insts 4959666 # Number of store instructions 660system.cpu1.num_idle_cycles 1771680344.893366 # Number of idle cycles 661system.cpu1.num_busy_cycles 30029231.106634 # Number of busy cycles 662system.cpu1.not_idle_fraction 0.016667 # Percentage of non-idle cycles 663system.cpu1.idle_fraction 0.983333 # Percentage of idle cycles 664system.cpu1.Branches 4459555 # Number of branches fetched 665system.cpu1.op_class::No_OpClass 15552 0.05% 0.05% # Class of executed instruction 666system.cpu1.op_class::IntAlu 18046643 61.66% 61.71% # Class of executed instruction 667system.cpu1.op_class::IntMult 40424 0.14% 61.85% # Class of executed instruction 668system.cpu1.op_class::IntDiv 0 0.00% 61.85% # Class of executed instruction 669system.cpu1.op_class::FloatAdd 0 0.00% 61.85% # Class of executed instruction 670system.cpu1.op_class::FloatCmp 0 0.00% 61.85% # Class of executed instruction 671system.cpu1.op_class::FloatCvt 0 0.00% 61.85% # Class of executed instruction 672system.cpu1.op_class::FloatMult 0 0.00% 61.85% # Class of executed instruction 673system.cpu1.op_class::FloatDiv 0 0.00% 61.85% # Class of executed instruction 674system.cpu1.op_class::FloatSqrt 0 0.00% 61.85% # Class of executed instruction 675system.cpu1.op_class::SimdAdd 0 0.00% 61.85% # Class of executed instruction 676system.cpu1.op_class::SimdAddAcc 0 0.00% 61.85% # Class of executed instruction 677system.cpu1.op_class::SimdAlu 0 0.00% 61.85% # Class of executed instruction 678system.cpu1.op_class::SimdCmp 0 0.00% 61.85% # Class of executed instruction 679system.cpu1.op_class::SimdCvt 0 0.00% 61.85% # Class of executed instruction 680system.cpu1.op_class::SimdMisc 0 0.00% 61.85% # Class of executed instruction 681system.cpu1.op_class::SimdMult 0 0.00% 61.85% # Class of executed instruction 682system.cpu1.op_class::SimdMultAcc 0 0.00% 61.85% # Class of executed instruction 683system.cpu1.op_class::SimdShift 0 0.00% 61.85% # Class of executed instruction 684system.cpu1.op_class::SimdShiftAcc 0 0.00% 61.85% # Class of executed instruction 685system.cpu1.op_class::SimdSqrt 0 0.00% 61.85% # Class of executed instruction 686system.cpu1.op_class::SimdFloatAdd 0 0.00% 61.85% # Class of executed instruction 687system.cpu1.op_class::SimdFloatAlu 0 0.00% 61.85% # Class of executed instruction 688system.cpu1.op_class::SimdFloatCmp 0 0.00% 61.85% # Class of executed instruction 689system.cpu1.op_class::SimdFloatCvt 0 0.00% 61.85% # Class of executed instruction 690system.cpu1.op_class::SimdFloatDiv 0 0.00% 61.85% # Class of executed instruction 691system.cpu1.op_class::SimdFloatMisc 1539 0.01% 61.85% # Class of executed instruction 692system.cpu1.op_class::SimdFloatMult 0 0.00% 61.85% # Class of executed instruction 693system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 61.85% # Class of executed instruction 694system.cpu1.op_class::SimdFloatSqrt 0 0.00% 61.85% # Class of executed instruction 695system.cpu1.op_class::MemRead 6206289 21.20% 83.06% # Class of executed instruction 696system.cpu1.op_class::MemWrite 4959666 16.94% 100.00% # Class of executed instruction 697system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 698system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 699system.cpu1.op_class::total 29270113 # Class of executed instruction 700system.cpu1.kern.inst.arm 0 # number of arm instructions executed 701system.cpu1.kern.inst.quiesce 48301 # number of quiesce instructions executed 702system.cpu1.icache.tags.replacements 442993 # number of replacements 703system.cpu1.icache.tags.tagsinuse 472.644505 # Cycle average of tags in use 704system.cpu1.icache.tags.total_refs 24184321 # Total number of references to valid blocks. 705system.cpu1.icache.tags.sampled_refs 443505 # Sample count of references to valid blocks. 706system.cpu1.icache.tags.avg_refs 54.529985 # Average number of references to valid blocks. 707system.cpu1.icache.tags.warmup_cycle 254679414000 # Cycle when the warmup percentage was hit. 708system.cpu1.icache.tags.occ_blocks::cpu1.inst 472.644505 # Average occupied blocks per requestor 709system.cpu1.icache.tags.occ_percent::cpu1.inst 0.923134 # Average percentage of cache occupancy 710system.cpu1.icache.tags.occ_percent::total 0.923134 # Average percentage of cache occupancy 711system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 712system.cpu1.icache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id 713system.cpu1.icache.tags.age_task_id_blocks_1024::1 50 # Occupied blocks per task id 714system.cpu1.icache.tags.age_task_id_blocks_1024::2 257 # Occupied blocks per task id 715system.cpu1.icache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id 716system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 717system.cpu1.icache.tags.tag_accesses 25071331 # Number of tag accesses 718system.cpu1.icache.tags.data_accesses 25071331 # Number of data accesses 719system.cpu1.icache.ReadReq_hits::cpu1.inst 24184321 # number of ReadReq hits 720system.cpu1.icache.ReadReq_hits::total 24184321 # number of ReadReq hits 721system.cpu1.icache.demand_hits::cpu1.inst 24184321 # number of demand (read+write) hits 722system.cpu1.icache.demand_hits::total 24184321 # number of demand (read+write) hits 723system.cpu1.icache.overall_hits::cpu1.inst 24184321 # number of overall hits 724system.cpu1.icache.overall_hits::total 24184321 # number of overall hits 725system.cpu1.icache.ReadReq_misses::cpu1.inst 443505 # number of ReadReq misses 726system.cpu1.icache.ReadReq_misses::total 443505 # number of ReadReq misses 727system.cpu1.icache.demand_misses::cpu1.inst 443505 # number of demand (read+write) misses 728system.cpu1.icache.demand_misses::total 443505 # number of demand (read+write) misses 729system.cpu1.icache.overall_misses::cpu1.inst 443505 # number of overall misses 730system.cpu1.icache.overall_misses::total 443505 # number of overall misses 731system.cpu1.icache.ReadReq_accesses::cpu1.inst 24627826 # number of ReadReq accesses(hits+misses) 732system.cpu1.icache.ReadReq_accesses::total 24627826 # number of ReadReq accesses(hits+misses) 733system.cpu1.icache.demand_accesses::cpu1.inst 24627826 # number of demand (read+write) accesses 734system.cpu1.icache.demand_accesses::total 24627826 # number of demand (read+write) accesses 735system.cpu1.icache.overall_accesses::cpu1.inst 24627826 # number of overall (read+write) accesses 736system.cpu1.icache.overall_accesses::total 24627826 # number of overall (read+write) accesses 737system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.018008 # miss rate for ReadReq accesses 738system.cpu1.icache.ReadReq_miss_rate::total 0.018008 # miss rate for ReadReq accesses 739system.cpu1.icache.demand_miss_rate::cpu1.inst 0.018008 # miss rate for demand accesses 740system.cpu1.icache.demand_miss_rate::total 0.018008 # miss rate for demand accesses 741system.cpu1.icache.overall_miss_rate::cpu1.inst 0.018008 # miss rate for overall accesses 742system.cpu1.icache.overall_miss_rate::total 0.018008 # miss rate for overall accesses 743system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 744system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 745system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 746system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 747system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 748system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 749system.cpu1.icache.fast_writes 0 # number of fast writes performed 750system.cpu1.icache.cache_copies 0 # number of cache copies performed 751system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 752system.cpu1.dcache.tags.replacements 274056 # number of replacements 753system.cpu1.dcache.tags.tagsinuse 468.122166 # Cycle average of tags in use 754system.cpu1.dcache.tags.total_refs 9407683 # Total number of references to valid blocks. 755system.cpu1.dcache.tags.sampled_refs 274568 # Sample count of references to valid blocks. 756system.cpu1.dcache.tags.avg_refs 34.263581 # Average number of references to valid blocks. 757system.cpu1.dcache.tags.warmup_cycle 94419429000 # Cycle when the warmup percentage was hit. 758system.cpu1.dcache.tags.occ_blocks::cpu1.data 468.122166 # Average occupied blocks per requestor 759system.cpu1.dcache.tags.occ_percent::cpu1.data 0.914301 # Average percentage of cache occupancy 760system.cpu1.dcache.tags.occ_percent::total 0.914301 # Average percentage of cache occupancy 761system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 762system.cpu1.dcache.tags.age_task_id_blocks_1024::0 322 # Occupied blocks per task id 763system.cpu1.dcache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id 764system.cpu1.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id 765system.cpu1.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 766system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 767system.cpu1.dcache.tags.tag_accesses 39106907 # Number of tag accesses 768system.cpu1.dcache.tags.data_accesses 39106907 # Number of data accesses 769system.cpu1.dcache.ReadReq_hits::cpu1.data 4611957 # number of ReadReq hits 770system.cpu1.dcache.ReadReq_hits::total 4611957 # number of ReadReq hits 771system.cpu1.dcache.WriteReq_hits::cpu1.data 4543395 # number of WriteReq hits 772system.cpu1.dcache.WriteReq_hits::total 4543395 # number of WriteReq hits 773system.cpu1.dcache.SoftPFReq_hits::cpu1.data 35603 # number of SoftPFReq hits 774system.cpu1.dcache.SoftPFReq_hits::total 35603 # number of SoftPFReq hits 775system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 94939 # number of LoadLockedReq hits 776system.cpu1.dcache.LoadLockedReq_hits::total 94939 # number of LoadLockedReq hits 777system.cpu1.dcache.StoreCondReq_hits::cpu1.data 95657 # number of StoreCondReq hits 778system.cpu1.dcache.StoreCondReq_hits::total 95657 # number of StoreCondReq hits 779system.cpu1.dcache.demand_hits::cpu1.data 9155352 # number of demand (read+write) hits 780system.cpu1.dcache.demand_hits::total 9155352 # number of demand (read+write) hits 781system.cpu1.dcache.overall_hits::cpu1.data 9190955 # number of overall hits 782system.cpu1.dcache.overall_hits::total 9190955 # number of overall hits 783system.cpu1.dcache.ReadReq_misses::cpu1.data 143554 # number of ReadReq misses 784system.cpu1.dcache.ReadReq_misses::total 143554 # number of ReadReq misses 785system.cpu1.dcache.WriteReq_misses::cpu1.data 130048 # number of WriteReq misses 786system.cpu1.dcache.WriteReq_misses::total 130048 # number of WriteReq misses 787system.cpu1.dcache.SoftPFReq_misses::cpu1.data 27770 # number of SoftPFReq misses 788system.cpu1.dcache.SoftPFReq_misses::total 27770 # number of SoftPFReq misses 789system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 10527 # number of LoadLockedReq misses 790system.cpu1.dcache.LoadLockedReq_misses::total 10527 # number of LoadLockedReq misses 791system.cpu1.dcache.StoreCondReq_misses::cpu1.data 9468 # number of StoreCondReq misses 792system.cpu1.dcache.StoreCondReq_misses::total 9468 # number of StoreCondReq misses 793system.cpu1.dcache.demand_misses::cpu1.data 273602 # number of demand (read+write) misses 794system.cpu1.dcache.demand_misses::total 273602 # number of demand (read+write) misses 795system.cpu1.dcache.overall_misses::cpu1.data 301372 # number of overall misses 796system.cpu1.dcache.overall_misses::total 301372 # number of overall misses 797system.cpu1.dcache.ReadReq_accesses::cpu1.data 4755511 # number of ReadReq accesses(hits+misses) 798system.cpu1.dcache.ReadReq_accesses::total 4755511 # number of ReadReq accesses(hits+misses) 799system.cpu1.dcache.WriteReq_accesses::cpu1.data 4673443 # number of WriteReq accesses(hits+misses) 800system.cpu1.dcache.WriteReq_accesses::total 4673443 # number of WriteReq accesses(hits+misses) 801system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 63373 # number of SoftPFReq accesses(hits+misses) 802system.cpu1.dcache.SoftPFReq_accesses::total 63373 # number of SoftPFReq accesses(hits+misses) 803system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 105466 # number of LoadLockedReq accesses(hits+misses) 804system.cpu1.dcache.LoadLockedReq_accesses::total 105466 # number of LoadLockedReq accesses(hits+misses) 805system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105125 # number of StoreCondReq accesses(hits+misses) 806system.cpu1.dcache.StoreCondReq_accesses::total 105125 # number of StoreCondReq accesses(hits+misses) 807system.cpu1.dcache.demand_accesses::cpu1.data 9428954 # number of demand (read+write) accesses 808system.cpu1.dcache.demand_accesses::total 9428954 # number of demand (read+write) accesses 809system.cpu1.dcache.overall_accesses::cpu1.data 9492327 # number of overall (read+write) accesses 810system.cpu1.dcache.overall_accesses::total 9492327 # number of overall (read+write) accesses 811system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.030187 # miss rate for ReadReq accesses 812system.cpu1.dcache.ReadReq_miss_rate::total 0.030187 # miss rate for ReadReq accesses 813system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027827 # miss rate for WriteReq accesses 814system.cpu1.dcache.WriteReq_miss_rate::total 0.027827 # miss rate for WriteReq accesses 815system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.438199 # miss rate for SoftPFReq accesses 816system.cpu1.dcache.SoftPFReq_miss_rate::total 0.438199 # miss rate for SoftPFReq accesses 817system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.099814 # miss rate for LoadLockedReq accesses 818system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.099814 # miss rate for LoadLockedReq accesses 819system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.090064 # miss rate for StoreCondReq accesses 820system.cpu1.dcache.StoreCondReq_miss_rate::total 0.090064 # miss rate for StoreCondReq accesses 821system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029017 # miss rate for demand accesses 822system.cpu1.dcache.demand_miss_rate::total 0.029017 # miss rate for demand accesses 823system.cpu1.dcache.overall_miss_rate::cpu1.data 0.031749 # miss rate for overall accesses 824system.cpu1.dcache.overall_miss_rate::total 0.031749 # miss rate for overall accesses 825system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 826system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 827system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 828system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 829system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 830system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 831system.cpu1.dcache.fast_writes 0 # number of fast writes performed 832system.cpu1.dcache.cache_copies 0 # number of cache copies performed 833system.cpu1.dcache.writebacks::writebacks 249941 # number of writebacks 834system.cpu1.dcache.writebacks::total 249941 # number of writebacks 835system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 836system.iocache.tags.replacements 0 # number of replacements 837system.iocache.tags.tagsinuse 0 # Cycle average of tags in use 838system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 839system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. 840system.iocache.tags.avg_refs nan # Average number of references to valid blocks. 841system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 842system.iocache.tags.tag_accesses 0 # Number of tag accesses 843system.iocache.tags.data_accesses 0 # Number of data accesses 844system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 845system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 846system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 847system.iocache.blocked::no_targets 0 # number of cycles access was blocked 848system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 849system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 850system.iocache.fast_writes 0 # number of fast writes performed 851system.iocache.cache_copies 0 # number of cache copies performed 852system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 853 854---------- End Simulation Statistics ---------- 855