stats.txt revision 10036:80e84beef3bb
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.912097 # Number of seconds simulated 4sim_ticks 912096763500 # Number of ticks simulated 5final_tick 912096763500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1859152 # Simulator instruction rate (inst/s) 8host_op_rate 2393654 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 27516397451 # Simulator tick rate (ticks/s) 10host_mem_usage 399324 # Number of bytes of host memory used 11host_seconds 33.15 # Real time elapsed on the host 12sim_insts 61625970 # Number of instructions simulated 13sim_ops 79343340 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 502180 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 6235188 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.inst 214556 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.data 3364528 # Number of bytes read from this memory 24system.physmem.bytes_read::total 49638500 # Number of bytes read from this memory 25system.physmem.bytes_inst_read::cpu0.inst 502180 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::cpu1.inst 214556 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::total 716736 # Number of instructions bytes read from this memory 28system.physmem.bytes_written::writebacks 4195776 # Number of bytes written to this memory 29system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory 30system.physmem.bytes_written::cpu1.data 3010088 # Number of bytes written to this memory 31system.physmem.bytes_written::total 7222864 # Number of bytes written to this memory 32system.physmem.num_reads::realview.clcd 4915200 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu0.inst 14065 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.data 97497 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu1.inst 3434 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu1.data 52597 # Number of read requests responded to by this memory 40system.physmem.num_reads::total 5082800 # Number of read requests responded to by this memory 41system.physmem.num_writes::writebacks 65559 # Number of write requests responded to by this memory 42system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory 43system.physmem.num_writes::cpu1.data 752522 # Number of write requests responded to by this memory 44system.physmem.num_writes::total 822331 # Number of write requests responded to by this memory 45system.physmem.bw_read::realview.clcd 43111215 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu0.dtb.walker 70 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::cpu0.itb.walker 211 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::cpu0.inst 550578 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu0.data 6836104 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu1.dtb.walker 211 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu1.inst 235234 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu1.data 3688784 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::total 54422406 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_inst_read::cpu0.inst 550578 # Instruction read bandwidth from this memory (bytes/s) 55system.physmem.bw_inst_read::cpu1.inst 235234 # Instruction read bandwidth from this memory (bytes/s) 56system.physmem.bw_inst_read::total 785811 # Instruction read bandwidth from this memory (bytes/s) 57system.physmem.bw_write::writebacks 4600144 # Write bandwidth from this memory (bytes/s) 58system.physmem.bw_write::cpu0.data 18638 # Write bandwidth from this memory (bytes/s) 59system.physmem.bw_write::cpu1.data 3300185 # Write bandwidth from this memory (bytes/s) 60system.physmem.bw_write::total 7918967 # Write bandwidth from this memory (bytes/s) 61system.physmem.bw_total::writebacks 4600144 # Total bandwidth to/from this memory (bytes/s) 62system.physmem.bw_total::realview.clcd 43111215 # Total bandwidth to/from this memory (bytes/s) 63system.physmem.bw_total::cpu0.dtb.walker 70 # Total bandwidth to/from this memory (bytes/s) 64system.physmem.bw_total::cpu0.itb.walker 211 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::cpu0.inst 550578 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::cpu0.data 6854742 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu1.dtb.walker 211 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::cpu1.inst 235234 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::cpu1.data 6988969 # Total bandwidth to/from this memory (bytes/s) 70system.physmem.bw_total::total 62341372 # Total bandwidth to/from this memory (bytes/s) 71system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 72system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 73system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 74system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 75system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 76system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 77system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 78system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 79system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 80system.realview.nvmem.bw_read::cpu0.inst 22 # Total read bandwidth from this memory (bytes/s) 81system.realview.nvmem.bw_read::cpu1.inst 53 # Total read bandwidth from this memory (bytes/s) 82system.realview.nvmem.bw_read::total 75 # Total read bandwidth from this memory (bytes/s) 83system.realview.nvmem.bw_inst_read::cpu0.inst 22 # Instruction read bandwidth from this memory (bytes/s) 84system.realview.nvmem.bw_inst_read::cpu1.inst 53 # Instruction read bandwidth from this memory (bytes/s) 85system.realview.nvmem.bw_inst_read::total 75 # Instruction read bandwidth from this memory (bytes/s) 86system.realview.nvmem.bw_total::cpu0.inst 22 # Total bandwidth to/from this memory (bytes/s) 87system.realview.nvmem.bw_total::cpu1.inst 53 # Total bandwidth to/from this memory (bytes/s) 88system.realview.nvmem.bw_total::total 75 # Total bandwidth to/from this memory (bytes/s) 89system.membus.throughput 64986577 # Throughput (bytes/s) 90system.membus.data_through_bus 59274047 # Total data (bytes) 91system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 92system.cpu_clk_domain.clock 500 # Clock period in ticks 93system.l2c.tags.replacements 70658 # number of replacements 94system.l2c.tags.tagsinuse 51560.149653 # Cycle average of tags in use 95system.l2c.tags.total_refs 1623339 # Total number of references to valid blocks. 96system.l2c.tags.sampled_refs 135810 # Sample count of references to valid blocks. 97system.l2c.tags.avg_refs 11.953015 # Average number of references to valid blocks. 98system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 99system.l2c.tags.occ_blocks::writebacks 39278.694978 # Average occupied blocks per requestor 100system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000049 # Average occupied blocks per requestor 101system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001108 # Average occupied blocks per requestor 102system.l2c.tags.occ_blocks::cpu0.inst 4358.955639 # Average occupied blocks per requestor 103system.l2c.tags.occ_blocks::cpu0.data 2482.445004 # Average occupied blocks per requestor 104system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.678940 # Average occupied blocks per requestor 105system.l2c.tags.occ_blocks::cpu1.inst 2126.451282 # Average occupied blocks per requestor 106system.l2c.tags.occ_blocks::cpu1.data 3310.922653 # Average occupied blocks per requestor 107system.l2c.tags.occ_percent::writebacks 0.599345 # Average percentage of cache occupancy 108system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy 109system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy 110system.l2c.tags.occ_percent::cpu0.inst 0.066512 # Average percentage of cache occupancy 111system.l2c.tags.occ_percent::cpu0.data 0.037879 # Average percentage of cache occupancy 112system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000041 # Average percentage of cache occupancy 113system.l2c.tags.occ_percent::cpu1.inst 0.032447 # Average percentage of cache occupancy 114system.l2c.tags.occ_percent::cpu1.data 0.050521 # Average percentage of cache occupancy 115system.l2c.tags.occ_percent::total 0.786745 # Average percentage of cache occupancy 116system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id 117system.l2c.tags.occ_task_id_blocks::1024 65148 # Occupied blocks per task id 118system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id 119system.l2c.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id 120system.l2c.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id 121system.l2c.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id 122system.l2c.tags.age_task_id_blocks_1024::2 3771 # Occupied blocks per task id 123system.l2c.tags.age_task_id_blocks_1024::3 12549 # Occupied blocks per task id 124system.l2c.tags.age_task_id_blocks_1024::4 48575 # Occupied blocks per task id 125system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id 126system.l2c.tags.occ_task_id_percent::1024 0.994080 # Percentage of cache occupancy per task id 127system.l2c.tags.tag_accesses 16906854 # Number of tag accesses 128system.l2c.tags.data_accesses 16906854 # Number of data accesses 129system.l2c.ReadReq_hits::cpu0.dtb.walker 3874 # number of ReadReq hits 130system.l2c.ReadReq_hits::cpu0.itb.walker 1919 # number of ReadReq hits 131system.l2c.ReadReq_hits::cpu0.inst 421038 # number of ReadReq hits 132system.l2c.ReadReq_hits::cpu0.data 175188 # number of ReadReq hits 133system.l2c.ReadReq_hits::cpu1.dtb.walker 5331 # number of ReadReq hits 134system.l2c.ReadReq_hits::cpu1.itb.walker 1734 # number of ReadReq hits 135system.l2c.ReadReq_hits::cpu1.inst 430511 # number of ReadReq hits 136system.l2c.ReadReq_hits::cpu1.data 169511 # number of ReadReq hits 137system.l2c.ReadReq_hits::total 1209106 # number of ReadReq hits 138system.l2c.Writeback_hits::writebacks 567807 # number of Writeback hits 139system.l2c.Writeback_hits::total 567807 # number of Writeback hits 140system.l2c.UpgradeReq_hits::cpu0.data 611 # number of UpgradeReq hits 141system.l2c.UpgradeReq_hits::cpu1.data 663 # number of UpgradeReq hits 142system.l2c.UpgradeReq_hits::total 1274 # number of UpgradeReq hits 143system.l2c.SCUpgradeReq_hits::cpu0.data 137 # number of SCUpgradeReq hits 144system.l2c.SCUpgradeReq_hits::cpu1.data 31 # number of SCUpgradeReq hits 145system.l2c.SCUpgradeReq_hits::total 168 # number of SCUpgradeReq hits 146system.l2c.ReadExReq_hits::cpu0.data 58148 # number of ReadExReq hits 147system.l2c.ReadExReq_hits::cpu1.data 50212 # number of ReadExReq hits 148system.l2c.ReadExReq_hits::total 108360 # number of ReadExReq hits 149system.l2c.demand_hits::cpu0.dtb.walker 3874 # number of demand (read+write) hits 150system.l2c.demand_hits::cpu0.itb.walker 1919 # number of demand (read+write) hits 151system.l2c.demand_hits::cpu0.inst 421038 # number of demand (read+write) hits 152system.l2c.demand_hits::cpu0.data 233336 # number of demand (read+write) hits 153system.l2c.demand_hits::cpu1.dtb.walker 5331 # number of demand (read+write) hits 154system.l2c.demand_hits::cpu1.itb.walker 1734 # number of demand (read+write) hits 155system.l2c.demand_hits::cpu1.inst 430511 # number of demand (read+write) hits 156system.l2c.demand_hits::cpu1.data 219723 # number of demand (read+write) hits 157system.l2c.demand_hits::total 1317466 # number of demand (read+write) hits 158system.l2c.overall_hits::cpu0.dtb.walker 3874 # number of overall hits 159system.l2c.overall_hits::cpu0.itb.walker 1919 # number of overall hits 160system.l2c.overall_hits::cpu0.inst 421038 # number of overall hits 161system.l2c.overall_hits::cpu0.data 233336 # number of overall hits 162system.l2c.overall_hits::cpu1.dtb.walker 5331 # number of overall hits 163system.l2c.overall_hits::cpu1.itb.walker 1734 # number of overall hits 164system.l2c.overall_hits::cpu1.inst 430511 # number of overall hits 165system.l2c.overall_hits::cpu1.data 219723 # number of overall hits 166system.l2c.overall_hits::total 1317466 # number of overall hits 167system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses 168system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses 169system.l2c.ReadReq_misses::cpu0.inst 7432 # number of ReadReq misses 170system.l2c.ReadReq_misses::cpu0.data 6392 # number of ReadReq misses 171system.l2c.ReadReq_misses::cpu1.dtb.walker 3 # number of ReadReq misses 172system.l2c.ReadReq_misses::cpu1.inst 3347 # number of ReadReq misses 173system.l2c.ReadReq_misses::cpu1.data 5276 # number of ReadReq misses 174system.l2c.ReadReq_misses::total 22454 # number of ReadReq misses 175system.l2c.UpgradeReq_misses::cpu0.data 4932 # number of UpgradeReq misses 176system.l2c.UpgradeReq_misses::cpu1.data 4304 # number of UpgradeReq misses 177system.l2c.UpgradeReq_misses::total 9236 # number of UpgradeReq misses 178system.l2c.SCUpgradeReq_misses::cpu0.data 741 # number of SCUpgradeReq misses 179system.l2c.SCUpgradeReq_misses::cpu1.data 490 # number of SCUpgradeReq misses 180system.l2c.SCUpgradeReq_misses::total 1231 # number of SCUpgradeReq misses 181system.l2c.ReadExReq_misses::cpu0.data 92464 # number of ReadExReq misses 182system.l2c.ReadExReq_misses::cpu1.data 48372 # number of ReadExReq misses 183system.l2c.ReadExReq_misses::total 140836 # number of ReadExReq misses 184system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses 185system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses 186system.l2c.demand_misses::cpu0.inst 7432 # number of demand (read+write) misses 187system.l2c.demand_misses::cpu0.data 98856 # number of demand (read+write) misses 188system.l2c.demand_misses::cpu1.dtb.walker 3 # number of demand (read+write) misses 189system.l2c.demand_misses::cpu1.inst 3347 # number of demand (read+write) misses 190system.l2c.demand_misses::cpu1.data 53648 # number of demand (read+write) misses 191system.l2c.demand_misses::total 163290 # number of demand (read+write) misses 192system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses 193system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses 194system.l2c.overall_misses::cpu0.inst 7432 # number of overall misses 195system.l2c.overall_misses::cpu0.data 98856 # number of overall misses 196system.l2c.overall_misses::cpu1.dtb.walker 3 # number of overall misses 197system.l2c.overall_misses::cpu1.inst 3347 # number of overall misses 198system.l2c.overall_misses::cpu1.data 53648 # number of overall misses 199system.l2c.overall_misses::total 163290 # number of overall misses 200system.l2c.ReadReq_accesses::cpu0.dtb.walker 3875 # number of ReadReq accesses(hits+misses) 201system.l2c.ReadReq_accesses::cpu0.itb.walker 1922 # number of ReadReq accesses(hits+misses) 202system.l2c.ReadReq_accesses::cpu0.inst 428470 # number of ReadReq accesses(hits+misses) 203system.l2c.ReadReq_accesses::cpu0.data 181580 # number of ReadReq accesses(hits+misses) 204system.l2c.ReadReq_accesses::cpu1.dtb.walker 5334 # number of ReadReq accesses(hits+misses) 205system.l2c.ReadReq_accesses::cpu1.itb.walker 1734 # number of ReadReq accesses(hits+misses) 206system.l2c.ReadReq_accesses::cpu1.inst 433858 # number of ReadReq accesses(hits+misses) 207system.l2c.ReadReq_accesses::cpu1.data 174787 # number of ReadReq accesses(hits+misses) 208system.l2c.ReadReq_accesses::total 1231560 # number of ReadReq accesses(hits+misses) 209system.l2c.Writeback_accesses::writebacks 567807 # number of Writeback accesses(hits+misses) 210system.l2c.Writeback_accesses::total 567807 # number of Writeback accesses(hits+misses) 211system.l2c.UpgradeReq_accesses::cpu0.data 5543 # number of UpgradeReq accesses(hits+misses) 212system.l2c.UpgradeReq_accesses::cpu1.data 4967 # number of UpgradeReq accesses(hits+misses) 213system.l2c.UpgradeReq_accesses::total 10510 # number of UpgradeReq accesses(hits+misses) 214system.l2c.SCUpgradeReq_accesses::cpu0.data 878 # number of SCUpgradeReq accesses(hits+misses) 215system.l2c.SCUpgradeReq_accesses::cpu1.data 521 # number of SCUpgradeReq accesses(hits+misses) 216system.l2c.SCUpgradeReq_accesses::total 1399 # number of SCUpgradeReq accesses(hits+misses) 217system.l2c.ReadExReq_accesses::cpu0.data 150612 # number of ReadExReq accesses(hits+misses) 218system.l2c.ReadExReq_accesses::cpu1.data 98584 # number of ReadExReq accesses(hits+misses) 219system.l2c.ReadExReq_accesses::total 249196 # number of ReadExReq accesses(hits+misses) 220system.l2c.demand_accesses::cpu0.dtb.walker 3875 # number of demand (read+write) accesses 221system.l2c.demand_accesses::cpu0.itb.walker 1922 # number of demand (read+write) accesses 222system.l2c.demand_accesses::cpu0.inst 428470 # number of demand (read+write) accesses 223system.l2c.demand_accesses::cpu0.data 332192 # number of demand (read+write) accesses 224system.l2c.demand_accesses::cpu1.dtb.walker 5334 # number of demand (read+write) accesses 225system.l2c.demand_accesses::cpu1.itb.walker 1734 # number of demand (read+write) accesses 226system.l2c.demand_accesses::cpu1.inst 433858 # number of demand (read+write) accesses 227system.l2c.demand_accesses::cpu1.data 273371 # number of demand (read+write) accesses 228system.l2c.demand_accesses::total 1480756 # number of demand (read+write) accesses 229system.l2c.overall_accesses::cpu0.dtb.walker 3875 # number of overall (read+write) accesses 230system.l2c.overall_accesses::cpu0.itb.walker 1922 # number of overall (read+write) accesses 231system.l2c.overall_accesses::cpu0.inst 428470 # number of overall (read+write) accesses 232system.l2c.overall_accesses::cpu0.data 332192 # number of overall (read+write) accesses 233system.l2c.overall_accesses::cpu1.dtb.walker 5334 # number of overall (read+write) accesses 234system.l2c.overall_accesses::cpu1.itb.walker 1734 # number of overall (read+write) accesses 235system.l2c.overall_accesses::cpu1.inst 433858 # number of overall (read+write) accesses 236system.l2c.overall_accesses::cpu1.data 273371 # number of overall (read+write) accesses 237system.l2c.overall_accesses::total 1480756 # number of overall (read+write) accesses 238system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000258 # miss rate for ReadReq accesses 239system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001561 # miss rate for ReadReq accesses 240system.l2c.ReadReq_miss_rate::cpu0.inst 0.017345 # miss rate for ReadReq accesses 241system.l2c.ReadReq_miss_rate::cpu0.data 0.035202 # miss rate for ReadReq accesses 242system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000562 # miss rate for ReadReq accesses 243system.l2c.ReadReq_miss_rate::cpu1.inst 0.007715 # miss rate for ReadReq accesses 244system.l2c.ReadReq_miss_rate::cpu1.data 0.030185 # miss rate for ReadReq accesses 245system.l2c.ReadReq_miss_rate::total 0.018232 # miss rate for ReadReq accesses 246system.l2c.UpgradeReq_miss_rate::cpu0.data 0.889771 # miss rate for UpgradeReq accesses 247system.l2c.UpgradeReq_miss_rate::cpu1.data 0.866519 # miss rate for UpgradeReq accesses 248system.l2c.UpgradeReq_miss_rate::total 0.878782 # miss rate for UpgradeReq accesses 249system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.843964 # miss rate for SCUpgradeReq accesses 250system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.940499 # miss rate for SCUpgradeReq accesses 251system.l2c.SCUpgradeReq_miss_rate::total 0.879914 # miss rate for SCUpgradeReq accesses 252system.l2c.ReadExReq_miss_rate::cpu0.data 0.613922 # miss rate for ReadExReq accesses 253system.l2c.ReadExReq_miss_rate::cpu1.data 0.490668 # miss rate for ReadExReq accesses 254system.l2c.ReadExReq_miss_rate::total 0.565162 # miss rate for ReadExReq accesses 255system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000258 # miss rate for demand accesses 256system.l2c.demand_miss_rate::cpu0.itb.walker 0.001561 # miss rate for demand accesses 257system.l2c.demand_miss_rate::cpu0.inst 0.017345 # miss rate for demand accesses 258system.l2c.demand_miss_rate::cpu0.data 0.297587 # miss rate for demand accesses 259system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000562 # miss rate for demand accesses 260system.l2c.demand_miss_rate::cpu1.inst 0.007715 # miss rate for demand accesses 261system.l2c.demand_miss_rate::cpu1.data 0.196246 # miss rate for demand accesses 262system.l2c.demand_miss_rate::total 0.110275 # miss rate for demand accesses 263system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000258 # miss rate for overall accesses 264system.l2c.overall_miss_rate::cpu0.itb.walker 0.001561 # miss rate for overall accesses 265system.l2c.overall_miss_rate::cpu0.inst 0.017345 # miss rate for overall accesses 266system.l2c.overall_miss_rate::cpu0.data 0.297587 # miss rate for overall accesses 267system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000562 # miss rate for overall accesses 268system.l2c.overall_miss_rate::cpu1.inst 0.007715 # miss rate for overall accesses 269system.l2c.overall_miss_rate::cpu1.data 0.196246 # miss rate for overall accesses 270system.l2c.overall_miss_rate::total 0.110275 # miss rate for overall accesses 271system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 272system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 273system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 274system.l2c.blocked::no_targets 0 # number of cycles access was blocked 275system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 276system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 277system.l2c.fast_writes 0 # number of fast writes performed 278system.l2c.cache_copies 0 # number of cache copies performed 279system.l2c.writebacks::writebacks 65559 # number of writebacks 280system.l2c.writebacks::total 65559 # number of writebacks 281system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 282system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 283system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 284system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 285system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 286system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 287system.cf0.dma_write_txs 0 # Number of DMA write transactions. 288system.toL2Bus.throughput 154009014 # Throughput (bytes/s) 289system.toL2Bus.data_through_bus 140471123 # Total data (bytes) 290system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 291system.iobus.throughput 45730949 # Throughput (bytes/s) 292system.iobus.data_through_bus 41711051 # Total data (bytes) 293system.cpu0.dtb.inst_hits 0 # ITB inst hits 294system.cpu0.dtb.inst_misses 0 # ITB inst misses 295system.cpu0.dtb.read_hits 7975768 # DTB read hits 296system.cpu0.dtb.read_misses 3611 # DTB read misses 297system.cpu0.dtb.write_hits 5966574 # DTB write hits 298system.cpu0.dtb.write_misses 672 # DTB write misses 299system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 300system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 301system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 302system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 303system.cpu0.dtb.flush_entries 2004 # Number of entries that have been flushed from TLB 304system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 305system.cpu0.dtb.prefetch_faults 135 # Number of TLB faults due to prefetch 306system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 307system.cpu0.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions 308system.cpu0.dtb.read_accesses 7979379 # DTB read accesses 309system.cpu0.dtb.write_accesses 5967246 # DTB write accesses 310system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 311system.cpu0.dtb.hits 13942342 # DTB hits 312system.cpu0.dtb.misses 4283 # DTB misses 313system.cpu0.dtb.accesses 13946625 # DTB accesses 314system.cpu0.itb.inst_hits 30238804 # ITB inst hits 315system.cpu0.itb.inst_misses 2175 # ITB inst misses 316system.cpu0.itb.read_hits 0 # DTB read hits 317system.cpu0.itb.read_misses 0 # DTB read misses 318system.cpu0.itb.write_hits 0 # DTB write hits 319system.cpu0.itb.write_misses 0 # DTB write misses 320system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 321system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 322system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 323system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 324system.cpu0.itb.flush_entries 1499 # Number of entries that have been flushed from TLB 325system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 326system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 327system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 328system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 329system.cpu0.itb.read_accesses 0 # DTB read accesses 330system.cpu0.itb.write_accesses 0 # DTB write accesses 331system.cpu0.itb.inst_accesses 30240979 # ITB inst accesses 332system.cpu0.itb.hits 30238804 # DTB hits 333system.cpu0.itb.misses 2175 # DTB misses 334system.cpu0.itb.accesses 30240979 # DTB accesses 335system.cpu0.numCycles 1823671407 # number of cpu cycles simulated 336system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 337system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 338system.cpu0.committedInsts 29750005 # Number of instructions committed 339system.cpu0.committedOps 39129633 # Number of ops (including micro ops) committed 340system.cpu0.num_int_alu_accesses 34471201 # Number of integer alu accesses 341system.cpu0.num_fp_alu_accesses 5449 # Number of float alu accesses 342system.cpu0.num_func_calls 1241903 # number of times a function call or return occured 343system.cpu0.num_conditional_control_insts 4044057 # number of instructions that are conditional controls 344system.cpu0.num_int_insts 34471201 # number of integer instructions 345system.cpu0.num_fp_insts 5449 # number of float instructions 346system.cpu0.num_int_register_reads 175121947 # number of times the integer registers were read 347system.cpu0.num_int_register_writes 36551788 # number of times the integer registers were written 348system.cpu0.num_fp_register_reads 4535 # number of times the floating registers were read 349system.cpu0.num_fp_register_writes 916 # number of times the floating registers were written 350system.cpu0.num_mem_refs 14626951 # number of memory refs 351system.cpu0.num_load_insts 8357226 # Number of load instructions 352system.cpu0.num_store_insts 6269725 # Number of store instructions 353system.cpu0.num_idle_cycles 1784006336.868180 # Number of idle cycles 354system.cpu0.num_busy_cycles 39665070.131821 # Number of busy cycles 355system.cpu0.not_idle_fraction 0.021750 # Percentage of non-idle cycles 356system.cpu0.idle_fraction 0.978250 # Percentage of idle cycles 357system.cpu0.kern.inst.arm 0 # number of arm instructions executed 358system.cpu0.kern.inst.quiesce 49966 # number of quiesce instructions executed 359system.cpu0.icache.tags.replacements 428546 # number of replacements 360system.cpu0.icache.tags.tagsinuse 511.015216 # Cycle average of tags in use 361system.cpu0.icache.tags.total_refs 29811115 # Total number of references to valid blocks. 362system.cpu0.icache.tags.sampled_refs 429058 # Sample count of references to valid blocks. 363system.cpu0.icache.tags.avg_refs 69.480385 # Average number of references to valid blocks. 364system.cpu0.icache.tags.warmup_cycle 64537139000 # Cycle when the warmup percentage was hit. 365system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.015216 # Average occupied blocks per requestor 366system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998077 # Average percentage of cache occupancy 367system.cpu0.icache.tags.occ_percent::total 0.998077 # Average percentage of cache occupancy 368system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 369system.cpu0.icache.tags.age_task_id_blocks_1024::2 508 # Occupied blocks per task id 370system.cpu0.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id 371system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 372system.cpu0.icache.tags.tag_accesses 30669233 # Number of tag accesses 373system.cpu0.icache.tags.data_accesses 30669233 # Number of data accesses 374system.cpu0.icache.ReadReq_hits::cpu0.inst 29811115 # number of ReadReq hits 375system.cpu0.icache.ReadReq_hits::total 29811115 # number of ReadReq hits 376system.cpu0.icache.demand_hits::cpu0.inst 29811115 # number of demand (read+write) hits 377system.cpu0.icache.demand_hits::total 29811115 # number of demand (read+write) hits 378system.cpu0.icache.overall_hits::cpu0.inst 29811115 # number of overall hits 379system.cpu0.icache.overall_hits::total 29811115 # number of overall hits 380system.cpu0.icache.ReadReq_misses::cpu0.inst 429059 # number of ReadReq misses 381system.cpu0.icache.ReadReq_misses::total 429059 # number of ReadReq misses 382system.cpu0.icache.demand_misses::cpu0.inst 429059 # number of demand (read+write) misses 383system.cpu0.icache.demand_misses::total 429059 # number of demand (read+write) misses 384system.cpu0.icache.overall_misses::cpu0.inst 429059 # number of overall misses 385system.cpu0.icache.overall_misses::total 429059 # number of overall misses 386system.cpu0.icache.ReadReq_accesses::cpu0.inst 30240174 # number of ReadReq accesses(hits+misses) 387system.cpu0.icache.ReadReq_accesses::total 30240174 # number of ReadReq accesses(hits+misses) 388system.cpu0.icache.demand_accesses::cpu0.inst 30240174 # number of demand (read+write) accesses 389system.cpu0.icache.demand_accesses::total 30240174 # number of demand (read+write) accesses 390system.cpu0.icache.overall_accesses::cpu0.inst 30240174 # number of overall (read+write) accesses 391system.cpu0.icache.overall_accesses::total 30240174 # number of overall (read+write) accesses 392system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014188 # miss rate for ReadReq accesses 393system.cpu0.icache.ReadReq_miss_rate::total 0.014188 # miss rate for ReadReq accesses 394system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014188 # miss rate for demand accesses 395system.cpu0.icache.demand_miss_rate::total 0.014188 # miss rate for demand accesses 396system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014188 # miss rate for overall accesses 397system.cpu0.icache.overall_miss_rate::total 0.014188 # miss rate for overall accesses 398system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 399system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 400system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 401system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 402system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 403system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 404system.cpu0.icache.fast_writes 0 # number of fast writes performed 405system.cpu0.icache.cache_copies 0 # number of cache copies performed 406system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 407system.cpu0.dcache.tags.replacements 323609 # number of replacements 408system.cpu0.dcache.tags.tagsinuse 494.763091 # Cycle average of tags in use 409system.cpu0.dcache.tags.total_refs 12467604 # Total number of references to valid blocks. 410system.cpu0.dcache.tags.sampled_refs 323981 # Sample count of references to valid blocks. 411system.cpu0.dcache.tags.avg_refs 38.482516 # Average number of references to valid blocks. 412system.cpu0.dcache.tags.warmup_cycle 22115000 # Cycle when the warmup percentage was hit. 413system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.763091 # Average occupied blocks per requestor 414system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966334 # Average percentage of cache occupancy 415system.cpu0.dcache.tags.occ_percent::total 0.966334 # Average percentage of cache occupancy 416system.cpu0.dcache.tags.occ_task_id_blocks::1024 372 # Occupied blocks per task id 417system.cpu0.dcache.tags.age_task_id_blocks_1024::2 372 # Occupied blocks per task id 418system.cpu0.dcache.tags.occ_task_id_percent::1024 0.726562 # Percentage of cache occupancy per task id 419system.cpu0.dcache.tags.tag_accesses 51675155 # Number of tag accesses 420system.cpu0.dcache.tags.data_accesses 51675155 # Number of data accesses 421system.cpu0.dcache.ReadReq_hits::cpu0.data 6512305 # number of ReadReq hits 422system.cpu0.dcache.ReadReq_hits::total 6512305 # number of ReadReq hits 423system.cpu0.dcache.WriteReq_hits::cpu0.data 5630881 # number of WriteReq hits 424system.cpu0.dcache.WriteReq_hits::total 5630881 # number of WriteReq hits 425system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 151619 # number of LoadLockedReq hits 426system.cpu0.dcache.LoadLockedReq_hits::total 151619 # number of LoadLockedReq hits 427system.cpu0.dcache.StoreCondReq_hits::cpu0.data 153180 # number of StoreCondReq hits 428system.cpu0.dcache.StoreCondReq_hits::total 153180 # number of StoreCondReq hits 429system.cpu0.dcache.demand_hits::cpu0.data 12143186 # number of demand (read+write) hits 430system.cpu0.dcache.demand_hits::total 12143186 # number of demand (read+write) hits 431system.cpu0.dcache.overall_hits::cpu0.data 12143186 # number of overall hits 432system.cpu0.dcache.overall_hits::total 12143186 # number of overall hits 433system.cpu0.dcache.ReadReq_misses::cpu0.data 197167 # number of ReadReq misses 434system.cpu0.dcache.ReadReq_misses::total 197167 # number of ReadReq misses 435system.cpu0.dcache.WriteReq_misses::cpu0.data 167342 # number of WriteReq misses 436system.cpu0.dcache.WriteReq_misses::total 167342 # number of WriteReq misses 437system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9062 # number of LoadLockedReq misses 438system.cpu0.dcache.LoadLockedReq_misses::total 9062 # number of LoadLockedReq misses 439system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7466 # number of StoreCondReq misses 440system.cpu0.dcache.StoreCondReq_misses::total 7466 # number of StoreCondReq misses 441system.cpu0.dcache.demand_misses::cpu0.data 364509 # number of demand (read+write) misses 442system.cpu0.dcache.demand_misses::total 364509 # number of demand (read+write) misses 443system.cpu0.dcache.overall_misses::cpu0.data 364509 # number of overall misses 444system.cpu0.dcache.overall_misses::total 364509 # number of overall misses 445system.cpu0.dcache.ReadReq_accesses::cpu0.data 6709472 # number of ReadReq accesses(hits+misses) 446system.cpu0.dcache.ReadReq_accesses::total 6709472 # number of ReadReq accesses(hits+misses) 447system.cpu0.dcache.WriteReq_accesses::cpu0.data 5798223 # number of WriteReq accesses(hits+misses) 448system.cpu0.dcache.WriteReq_accesses::total 5798223 # number of WriteReq accesses(hits+misses) 449system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 160681 # number of LoadLockedReq accesses(hits+misses) 450system.cpu0.dcache.LoadLockedReq_accesses::total 160681 # number of LoadLockedReq accesses(hits+misses) 451system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 160646 # number of StoreCondReq accesses(hits+misses) 452system.cpu0.dcache.StoreCondReq_accesses::total 160646 # number of StoreCondReq accesses(hits+misses) 453system.cpu0.dcache.demand_accesses::cpu0.data 12507695 # number of demand (read+write) accesses 454system.cpu0.dcache.demand_accesses::total 12507695 # number of demand (read+write) accesses 455system.cpu0.dcache.overall_accesses::cpu0.data 12507695 # number of overall (read+write) accesses 456system.cpu0.dcache.overall_accesses::total 12507695 # number of overall (read+write) accesses 457system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029386 # miss rate for ReadReq accesses 458system.cpu0.dcache.ReadReq_miss_rate::total 0.029386 # miss rate for ReadReq accesses 459system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.028861 # miss rate for WriteReq accesses 460system.cpu0.dcache.WriteReq_miss_rate::total 0.028861 # miss rate for WriteReq accesses 461system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056397 # miss rate for LoadLockedReq accesses 462system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056397 # miss rate for LoadLockedReq accesses 463system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.046475 # miss rate for StoreCondReq accesses 464system.cpu0.dcache.StoreCondReq_miss_rate::total 0.046475 # miss rate for StoreCondReq accesses 465system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029143 # miss rate for demand accesses 466system.cpu0.dcache.demand_miss_rate::total 0.029143 # miss rate for demand accesses 467system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029143 # miss rate for overall accesses 468system.cpu0.dcache.overall_miss_rate::total 0.029143 # miss rate for overall accesses 469system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 470system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 471system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 472system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 473system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 474system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 475system.cpu0.dcache.fast_writes 0 # number of fast writes performed 476system.cpu0.dcache.cache_copies 0 # number of cache copies performed 477system.cpu0.dcache.writebacks::writebacks 300958 # number of writebacks 478system.cpu0.dcache.writebacks::total 300958 # number of writebacks 479system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 480system.cpu1.dtb.inst_hits 0 # ITB inst hits 481system.cpu1.dtb.inst_misses 0 # ITB inst misses 482system.cpu1.dtb.read_hits 7364781 # DTB read hits 483system.cpu1.dtb.read_misses 3705 # DTB read misses 484system.cpu1.dtb.write_hits 5489656 # DTB write hits 485system.cpu1.dtb.write_misses 1595 # DTB write misses 486system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 487system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 488system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 489system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 490system.cpu1.dtb.flush_entries 1788 # Number of entries that have been flushed from TLB 491system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 492system.cpu1.dtb.prefetch_faults 145 # Number of TLB faults due to prefetch 493system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 494system.cpu1.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions 495system.cpu1.dtb.read_accesses 7368486 # DTB read accesses 496system.cpu1.dtb.write_accesses 5491251 # DTB write accesses 497system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 498system.cpu1.dtb.hits 12854437 # DTB hits 499system.cpu1.dtb.misses 5300 # DTB misses 500system.cpu1.dtb.accesses 12859737 # DTB accesses 501system.cpu1.itb.inst_hits 32412306 # ITB inst hits 502system.cpu1.itb.inst_misses 2200 # ITB inst misses 503system.cpu1.itb.read_hits 0 # DTB read hits 504system.cpu1.itb.read_misses 0 # DTB read misses 505system.cpu1.itb.write_hits 0 # DTB write hits 506system.cpu1.itb.write_misses 0 # DTB write misses 507system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 508system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 509system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 510system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 511system.cpu1.itb.flush_entries 1327 # Number of entries that have been flushed from TLB 512system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 513system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 514system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 515system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 516system.cpu1.itb.read_accesses 0 # DTB read accesses 517system.cpu1.itb.write_accesses 0 # DTB write accesses 518system.cpu1.itb.inst_accesses 32414506 # ITB inst accesses 519system.cpu1.itb.hits 32412306 # DTB hits 520system.cpu1.itb.misses 2200 # DTB misses 521system.cpu1.itb.accesses 32414506 # DTB accesses 522system.cpu1.numCycles 1824193528 # number of cpu cycles simulated 523system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 524system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 525system.cpu1.committedInsts 31875965 # Number of instructions committed 526system.cpu1.committedOps 40213707 # Number of ops (including micro ops) committed 527system.cpu1.num_int_alu_accesses 35797832 # Number of integer alu accesses 528system.cpu1.num_fp_alu_accesses 4436 # Number of float alu accesses 529system.cpu1.num_func_calls 955227 # number of times a function call or return occured 530system.cpu1.num_conditional_control_insts 4048022 # number of instructions that are conditional controls 531system.cpu1.num_int_insts 35797832 # number of integer instructions 532system.cpu1.num_fp_insts 4436 # number of float instructions 533system.cpu1.num_int_register_reads 181634271 # number of times the integer registers were read 534system.cpu1.num_int_register_writes 39007898 # number of times the integer registers were written 535system.cpu1.num_fp_register_reads 3022 # number of times the floating registers were read 536system.cpu1.num_fp_register_writes 1416 # number of times the floating registers were written 537system.cpu1.num_mem_refs 13370713 # number of memory refs 538system.cpu1.num_load_insts 7642673 # Number of load instructions 539system.cpu1.num_store_insts 5728040 # Number of store instructions 540system.cpu1.num_idle_cycles 1783401357.733683 # Number of idle cycles 541system.cpu1.num_busy_cycles 40792170.266317 # Number of busy cycles 542system.cpu1.not_idle_fraction 0.022362 # Percentage of non-idle cycles 543system.cpu1.idle_fraction 0.977638 # Percentage of idle cycles 544system.cpu1.kern.inst.arm 0 # number of arm instructions executed 545system.cpu1.kern.inst.quiesce 40379 # number of quiesce instructions executed 546system.cpu1.icache.tags.replacements 433942 # number of replacements 547system.cpu1.icache.tags.tagsinuse 475.447912 # Cycle average of tags in use 548system.cpu1.icache.tags.total_refs 31979125 # Total number of references to valid blocks. 549system.cpu1.icache.tags.sampled_refs 434454 # Sample count of references to valid blocks. 550system.cpu1.icache.tags.avg_refs 73.607620 # Average number of references to valid blocks. 551system.cpu1.icache.tags.warmup_cycle 69967763000 # Cycle when the warmup percentage was hit. 552system.cpu1.icache.tags.occ_blocks::cpu1.inst 475.447912 # Average occupied blocks per requestor 553system.cpu1.icache.tags.occ_percent::cpu1.inst 0.928609 # Average percentage of cache occupancy 554system.cpu1.icache.tags.occ_percent::total 0.928609 # Average percentage of cache occupancy 555system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 556system.cpu1.icache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id 557system.cpu1.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id 558system.cpu1.icache.tags.age_task_id_blocks_1024::2 261 # Occupied blocks per task id 559system.cpu1.icache.tags.age_task_id_blocks_1024::3 20 # Occupied blocks per task id 560system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 561system.cpu1.icache.tags.tag_accesses 32848033 # Number of tag accesses 562system.cpu1.icache.tags.data_accesses 32848033 # Number of data accesses 563system.cpu1.icache.ReadReq_hits::cpu1.inst 31979125 # number of ReadReq hits 564system.cpu1.icache.ReadReq_hits::total 31979125 # number of ReadReq hits 565system.cpu1.icache.demand_hits::cpu1.inst 31979125 # number of demand (read+write) hits 566system.cpu1.icache.demand_hits::total 31979125 # number of demand (read+write) hits 567system.cpu1.icache.overall_hits::cpu1.inst 31979125 # number of overall hits 568system.cpu1.icache.overall_hits::total 31979125 # number of overall hits 569system.cpu1.icache.ReadReq_misses::cpu1.inst 434454 # number of ReadReq misses 570system.cpu1.icache.ReadReq_misses::total 434454 # number of ReadReq misses 571system.cpu1.icache.demand_misses::cpu1.inst 434454 # number of demand (read+write) misses 572system.cpu1.icache.demand_misses::total 434454 # number of demand (read+write) misses 573system.cpu1.icache.overall_misses::cpu1.inst 434454 # number of overall misses 574system.cpu1.icache.overall_misses::total 434454 # number of overall misses 575system.cpu1.icache.ReadReq_accesses::cpu1.inst 32413579 # number of ReadReq accesses(hits+misses) 576system.cpu1.icache.ReadReq_accesses::total 32413579 # number of ReadReq accesses(hits+misses) 577system.cpu1.icache.demand_accesses::cpu1.inst 32413579 # number of demand (read+write) accesses 578system.cpu1.icache.demand_accesses::total 32413579 # number of demand (read+write) accesses 579system.cpu1.icache.overall_accesses::cpu1.inst 32413579 # number of overall (read+write) accesses 580system.cpu1.icache.overall_accesses::total 32413579 # number of overall (read+write) accesses 581system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013403 # miss rate for ReadReq accesses 582system.cpu1.icache.ReadReq_miss_rate::total 0.013403 # miss rate for ReadReq accesses 583system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013403 # miss rate for demand accesses 584system.cpu1.icache.demand_miss_rate::total 0.013403 # miss rate for demand accesses 585system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013403 # miss rate for overall accesses 586system.cpu1.icache.overall_miss_rate::total 0.013403 # miss rate for overall accesses 587system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 588system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 589system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 590system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 591system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 592system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 593system.cpu1.icache.fast_writes 0 # number of fast writes performed 594system.cpu1.icache.cache_copies 0 # number of cache copies performed 595system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 596system.cpu1.dcache.tags.replacements 294289 # number of replacements 597system.cpu1.dcache.tags.tagsinuse 447.573682 # Cycle average of tags in use 598system.cpu1.dcache.tags.total_refs 11707745 # Total number of references to valid blocks. 599system.cpu1.dcache.tags.sampled_refs 294801 # Sample count of references to valid blocks. 600system.cpu1.dcache.tags.avg_refs 39.714061 # Average number of references to valid blocks. 601system.cpu1.dcache.tags.warmup_cycle 67293493000 # Cycle when the warmup percentage was hit. 602system.cpu1.dcache.tags.occ_blocks::cpu1.data 447.573682 # Average occupied blocks per requestor 603system.cpu1.dcache.tags.occ_percent::cpu1.data 0.874167 # Average percentage of cache occupancy 604system.cpu1.dcache.tags.occ_percent::total 0.874167 # Average percentage of cache occupancy 605system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 606system.cpu1.dcache.tags.age_task_id_blocks_1024::0 267 # Occupied blocks per task id 607system.cpu1.dcache.tags.age_task_id_blocks_1024::1 226 # Occupied blocks per task id 608system.cpu1.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id 609system.cpu1.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 610system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 611system.cpu1.dcache.tags.tag_accesses 48417680 # Number of tag accesses 612system.cpu1.dcache.tags.data_accesses 48417680 # Number of data accesses 613system.cpu1.dcache.ReadReq_hits::cpu1.data 7002209 # number of ReadReq hits 614system.cpu1.dcache.ReadReq_hits::total 7002209 # number of ReadReq hits 615system.cpu1.dcache.WriteReq_hits::cpu1.data 4520313 # number of WriteReq hits 616system.cpu1.dcache.WriteReq_hits::total 4520313 # number of WriteReq hits 617system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 77954 # number of LoadLockedReq hits 618system.cpu1.dcache.LoadLockedReq_hits::total 77954 # number of LoadLockedReq hits 619system.cpu1.dcache.StoreCondReq_hits::cpu1.data 79030 # number of StoreCondReq hits 620system.cpu1.dcache.StoreCondReq_hits::total 79030 # number of StoreCondReq hits 621system.cpu1.dcache.demand_hits::cpu1.data 11522522 # number of demand (read+write) hits 622system.cpu1.dcache.demand_hits::total 11522522 # number of demand (read+write) hits 623system.cpu1.dcache.overall_hits::cpu1.data 11522522 # number of overall hits 624system.cpu1.dcache.overall_hits::total 11522522 # number of overall hits 625system.cpu1.dcache.ReadReq_misses::cpu1.data 198275 # number of ReadReq misses 626system.cpu1.dcache.ReadReq_misses::total 198275 # number of ReadReq misses 627system.cpu1.dcache.WriteReq_misses::cpu1.data 125920 # number of WriteReq misses 628system.cpu1.dcache.WriteReq_misses::total 125920 # number of WriteReq misses 629system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11251 # number of LoadLockedReq misses 630system.cpu1.dcache.LoadLockedReq_misses::total 11251 # number of LoadLockedReq misses 631system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10133 # number of StoreCondReq misses 632system.cpu1.dcache.StoreCondReq_misses::total 10133 # number of StoreCondReq misses 633system.cpu1.dcache.demand_misses::cpu1.data 324195 # number of demand (read+write) misses 634system.cpu1.dcache.demand_misses::total 324195 # number of demand (read+write) misses 635system.cpu1.dcache.overall_misses::cpu1.data 324195 # number of overall misses 636system.cpu1.dcache.overall_misses::total 324195 # number of overall misses 637system.cpu1.dcache.ReadReq_accesses::cpu1.data 7200484 # number of ReadReq accesses(hits+misses) 638system.cpu1.dcache.ReadReq_accesses::total 7200484 # number of ReadReq accesses(hits+misses) 639system.cpu1.dcache.WriteReq_accesses::cpu1.data 4646233 # number of WriteReq accesses(hits+misses) 640system.cpu1.dcache.WriteReq_accesses::total 4646233 # number of WriteReq accesses(hits+misses) 641system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 89205 # number of LoadLockedReq accesses(hits+misses) 642system.cpu1.dcache.LoadLockedReq_accesses::total 89205 # number of LoadLockedReq accesses(hits+misses) 643system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 89163 # number of StoreCondReq accesses(hits+misses) 644system.cpu1.dcache.StoreCondReq_accesses::total 89163 # number of StoreCondReq accesses(hits+misses) 645system.cpu1.dcache.demand_accesses::cpu1.data 11846717 # number of demand (read+write) accesses 646system.cpu1.dcache.demand_accesses::total 11846717 # number of demand (read+write) accesses 647system.cpu1.dcache.overall_accesses::cpu1.data 11846717 # number of overall (read+write) accesses 648system.cpu1.dcache.overall_accesses::total 11846717 # number of overall (read+write) accesses 649system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.027536 # miss rate for ReadReq accesses 650system.cpu1.dcache.ReadReq_miss_rate::total 0.027536 # miss rate for ReadReq accesses 651system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027102 # miss rate for WriteReq accesses 652system.cpu1.dcache.WriteReq_miss_rate::total 0.027102 # miss rate for WriteReq accesses 653system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.126125 # miss rate for LoadLockedReq accesses 654system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.126125 # miss rate for LoadLockedReq accesses 655system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.113646 # miss rate for StoreCondReq accesses 656system.cpu1.dcache.StoreCondReq_miss_rate::total 0.113646 # miss rate for StoreCondReq accesses 657system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027366 # miss rate for demand accesses 658system.cpu1.dcache.demand_miss_rate::total 0.027366 # miss rate for demand accesses 659system.cpu1.dcache.overall_miss_rate::cpu1.data 0.027366 # miss rate for overall accesses 660system.cpu1.dcache.overall_miss_rate::total 0.027366 # miss rate for overall accesses 661system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 662system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 663system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 664system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 665system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 666system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 667system.cpu1.dcache.fast_writes 0 # number of fast writes performed 668system.cpu1.dcache.cache_copies 0 # number of cache copies performed 669system.cpu1.dcache.writebacks::writebacks 266849 # number of writebacks 670system.cpu1.dcache.writebacks::total 266849 # number of writebacks 671system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 672system.iocache.tags.replacements 0 # number of replacements 673system.iocache.tags.tagsinuse 0 # Cycle average of tags in use 674system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 675system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. 676system.iocache.tags.avg_refs nan # Average number of references to valid blocks. 677system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 678system.iocache.tags.tag_accesses 0 # Number of tag accesses 679system.iocache.tags.data_accesses 0 # Number of data accesses 680system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 681system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 682system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 683system.iocache.blocked::no_targets 0 # number of cycles access was blocked 684system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 685system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 686system.iocache.fast_writes 0 # number of fast writes performed 687system.iocache.cache_copies 0 # number of cache copies performed 688system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 689 690---------- End Simulation Statistics ---------- 691