stats.txt revision 9568:cd1351d4d850
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.913475 # Number of seconds simulated 4sim_ticks 1913474690000 # Number of ticks simulated 5final_tick 1913474690000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1324010 # Simulator instruction rate (inst/s) 8host_op_rate 1324010 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 45134311907 # Simulator tick rate (ticks/s) 10host_mem_usage 328328 # Number of bytes of host memory used 11host_seconds 42.40 # Real time elapsed on the host 12sim_insts 56131527 # Number of instructions simulated 13sim_ops 56131527 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 850560 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 24859456 # Number of bytes read from this memory 16system.physmem.bytes_read::tsunami.ide 2652096 # Number of bytes read from this memory 17system.physmem.bytes_read::total 28362112 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 850560 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 850560 # Number of instructions bytes read from this memory 20system.physmem.bytes_written::writebacks 7404992 # Number of bytes written to this memory 21system.physmem.bytes_written::total 7404992 # Number of bytes written to this memory 22system.physmem.num_reads::cpu.inst 13290 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 388429 # Number of read requests responded to by this memory 24system.physmem.num_reads::tsunami.ide 41439 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 443158 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 115703 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 115703 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 444511 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 12991787 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::tsunami.ide 1386010 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 14822308 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 444511 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 444511 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 3869919 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 3869919 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 3869919 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 444511 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 12991787 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::tsunami.ide 1386010 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::total 18692227 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.readReqs 443158 # Total number of read requests seen 42system.physmem.writeReqs 115703 # Total number of write requests seen 43system.physmem.cpureqs 560726 # Reqs generatd by CPU via cache - shady 44system.physmem.bytesRead 28362112 # Total number of bytes read from memory 45system.physmem.bytesWritten 7404992 # Total number of bytes written to memory 46system.physmem.bytesConsumedRd 28362112 # bytesRead derated as per pkt->getSize() 47system.physmem.bytesConsumedWr 7404992 # bytesWritten derated as per pkt->getSize() 48system.physmem.servicedByWrQ 61 # Number of read reqs serviced by write Q 49system.physmem.neitherReadNorWrite 130 # Reqs where no action is needed 50system.physmem.perBankRdReqs::0 27906 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::1 27707 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::2 27556 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::3 27383 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::4 27676 # Track reads on a per bank basis 55system.physmem.perBankRdReqs::5 27765 # Track reads on a per bank basis 56system.physmem.perBankRdReqs::6 27828 # Track reads on a per bank basis 57system.physmem.perBankRdReqs::7 27614 # Track reads on a per bank basis 58system.physmem.perBankRdReqs::8 28005 # Track reads on a per bank basis 59system.physmem.perBankRdReqs::9 27777 # Track reads on a per bank basis 60system.physmem.perBankRdReqs::10 27792 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::11 27558 # Track reads on a per bank basis 62system.physmem.perBankRdReqs::12 27591 # Track reads on a per bank basis 63system.physmem.perBankRdReqs::13 27731 # Track reads on a per bank basis 64system.physmem.perBankRdReqs::14 27648 # Track reads on a per bank basis 65system.physmem.perBankRdReqs::15 27560 # Track reads on a per bank basis 66system.physmem.perBankWrReqs::0 7488 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::1 7264 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::2 7148 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::3 7040 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::4 7173 # Track writes on a per bank basis 71system.physmem.perBankWrReqs::5 7213 # Track writes on a per bank basis 72system.physmem.perBankWrReqs::6 7315 # Track writes on a per bank basis 73system.physmem.perBankWrReqs::7 7181 # Track writes on a per bank basis 74system.physmem.perBankWrReqs::8 7581 # Track writes on a per bank basis 75system.physmem.perBankWrReqs::9 7357 # Track writes on a per bank basis 76system.physmem.perBankWrReqs::10 7354 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::11 7063 # Track writes on a per bank basis 78system.physmem.perBankWrReqs::12 7148 # Track writes on a per bank basis 79system.physmem.perBankWrReqs::13 7186 # Track writes on a per bank basis 80system.physmem.perBankWrReqs::14 7115 # Track writes on a per bank basis 81system.physmem.perBankWrReqs::15 7077 # Track writes on a per bank basis 82system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 83system.physmem.numWrRetry 1735 # Number of times wr buffer was full causing retry 84system.physmem.totGap 1913462790000 # Total gap between requests 85system.physmem.readPktSize::0 0 # Categorize read packet sizes 86system.physmem.readPktSize::1 0 # Categorize read packet sizes 87system.physmem.readPktSize::2 0 # Categorize read packet sizes 88system.physmem.readPktSize::3 0 # Categorize read packet sizes 89system.physmem.readPktSize::4 0 # Categorize read packet sizes 90system.physmem.readPktSize::5 0 # Categorize read packet sizes 91system.physmem.readPktSize::6 443158 # Categorize read packet sizes 92system.physmem.writePktSize::0 0 # Categorize write packet sizes 93system.physmem.writePktSize::1 0 # Categorize write packet sizes 94system.physmem.writePktSize::2 0 # Categorize write packet sizes 95system.physmem.writePktSize::3 0 # Categorize write packet sizes 96system.physmem.writePktSize::4 0 # Categorize write packet sizes 97system.physmem.writePktSize::5 0 # Categorize write packet sizes 98system.physmem.writePktSize::6 115703 # Categorize write packet sizes 99system.physmem.rdQLenPdf::0 402452 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::1 4725 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::2 3681 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::3 2218 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::4 3124 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::5 2960 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::6 2702 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::7 2703 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::8 2646 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::9 2585 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::10 1528 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::11 1461 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::12 1423 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::13 1368 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::14 1353 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::15 1388 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::16 1604 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::17 1473 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::18 916 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::19 777 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::20 10 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 131system.physmem.wrQLenPdf::0 3531 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::1 3690 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::2 4106 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::3 4152 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::4 4652 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::5 5003 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::6 5013 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::7 5015 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::8 5016 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::9 5031 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::10 5031 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::11 5031 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::12 5031 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::13 5030 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::14 5030 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::15 5030 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::16 5030 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::17 5030 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::18 5030 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::19 5030 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::20 5030 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::21 5030 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::22 5030 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::23 1500 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::24 1341 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::25 925 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::26 879 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::27 379 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::28 28 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::29 18 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::31 15 # What write queue length does an incoming req see 163system.physmem.totQLat 4718928250 # Total cycles spent in queuing delays 164system.physmem.totMemAccLat 13231418250 # Sum of mem lat for all requests 165system.physmem.totBusLat 2215485000 # Total cycles spent in databus access 166system.physmem.totBankLat 6297005000 # Total cycles spent in bank access 167system.physmem.avgQLat 10649.88 # Average queueing delay per request 168system.physmem.avgBankLat 14211.35 # Average bank access latency per request 169system.physmem.avgBusLat 5000.00 # Average bus latency per request 170system.physmem.avgMemAccLat 29861.22 # Average memory access latency 171system.physmem.avgRdBW 14.82 # Average achieved read bandwidth in MB/s 172system.physmem.avgWrBW 3.87 # Average achieved write bandwidth in MB/s 173system.physmem.avgConsumedRdBW 14.82 # Average consumed read bandwidth in MB/s 174system.physmem.avgConsumedWrBW 3.87 # Average consumed write bandwidth in MB/s 175system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 176system.physmem.busUtil 0.15 # Data bus utilization in percentage 177system.physmem.avgRdQLen 0.01 # Average read queue length over time 178system.physmem.avgWrQLen 9.64 # Average write queue length over time 179system.physmem.readRowHits 415747 # Number of row buffer hits during reads 180system.physmem.writeRowHits 89943 # Number of row buffer hits during writes 181system.physmem.readRowHitRate 93.83 # Row buffer hit rate for reads 182system.physmem.writeRowHitRate 77.74 # Row buffer hit rate for writes 183system.physmem.avgGap 3423861.73 # Average gap between requests 184system.iocache.replacements 41685 # number of replacements 185system.iocache.tagsinuse 1.364719 # Cycle average of tags in use 186system.iocache.total_refs 0 # Total number of references to valid blocks. 187system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. 188system.iocache.avg_refs 0 # Average number of references to valid blocks. 189system.iocache.warmup_cycle 1745699710000 # Cycle when the warmup percentage was hit. 190system.iocache.occ_blocks::tsunami.ide 1.364719 # Average occupied blocks per requestor 191system.iocache.occ_percent::tsunami.ide 0.085295 # Average percentage of cache occupancy 192system.iocache.occ_percent::total 0.085295 # Average percentage of cache occupancy 193system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 194system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 195system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 196system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 197system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 198system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 199system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 200system.iocache.overall_misses::total 41725 # number of overall misses 201system.iocache.ReadReq_miss_latency::tsunami.ide 20927998 # number of ReadReq miss cycles 202system.iocache.ReadReq_miss_latency::total 20927998 # number of ReadReq miss cycles 203system.iocache.WriteReq_miss_latency::tsunami.ide 10661973806 # number of WriteReq miss cycles 204system.iocache.WriteReq_miss_latency::total 10661973806 # number of WriteReq miss cycles 205system.iocache.demand_miss_latency::tsunami.ide 10682901804 # number of demand (read+write) miss cycles 206system.iocache.demand_miss_latency::total 10682901804 # number of demand (read+write) miss cycles 207system.iocache.overall_miss_latency::tsunami.ide 10682901804 # number of overall miss cycles 208system.iocache.overall_miss_latency::total 10682901804 # number of overall miss cycles 209system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 210system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 211system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 212system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 213system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 214system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 215system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 216system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 217system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 218system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 219system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 220system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 221system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 222system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 223system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 224system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 225system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120971.086705 # average ReadReq miss latency 226system.iocache.ReadReq_avg_miss_latency::total 120971.086705 # average ReadReq miss latency 227system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256593.516702 # average WriteReq miss latency 228system.iocache.WriteReq_avg_miss_latency::total 256593.516702 # average WriteReq miss latency 229system.iocache.demand_avg_miss_latency::tsunami.ide 256031.199617 # average overall miss latency 230system.iocache.demand_avg_miss_latency::total 256031.199617 # average overall miss latency 231system.iocache.overall_avg_miss_latency::tsunami.ide 256031.199617 # average overall miss latency 232system.iocache.overall_avg_miss_latency::total 256031.199617 # average overall miss latency 233system.iocache.blocked_cycles::no_mshrs 285723 # number of cycles access was blocked 234system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 235system.iocache.blocked::no_mshrs 27146 # number of cycles access was blocked 236system.iocache.blocked::no_targets 0 # number of cycles access was blocked 237system.iocache.avg_blocked_cycles::no_mshrs 10.525418 # average number of cycles each access was blocked 238system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 239system.iocache.fast_writes 0 # number of fast writes performed 240system.iocache.cache_copies 0 # number of cache copies performed 241system.iocache.writebacks::writebacks 41512 # number of writebacks 242system.iocache.writebacks::total 41512 # number of writebacks 243system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 244system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 245system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 246system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 247system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 248system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 249system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 250system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses 251system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931249 # number of ReadReq MSHR miss cycles 252system.iocache.ReadReq_mshr_miss_latency::total 11931249 # number of ReadReq MSHR miss cycles 253system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8499962078 # number of WriteReq MSHR miss cycles 254system.iocache.WriteReq_mshr_miss_latency::total 8499962078 # number of WriteReq MSHR miss cycles 255system.iocache.demand_mshr_miss_latency::tsunami.ide 8511893327 # number of demand (read+write) MSHR miss cycles 256system.iocache.demand_mshr_miss_latency::total 8511893327 # number of demand (read+write) MSHR miss cycles 257system.iocache.overall_mshr_miss_latency::tsunami.ide 8511893327 # number of overall MSHR miss cycles 258system.iocache.overall_mshr_miss_latency::total 8511893327 # number of overall MSHR miss cycles 259system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 260system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 261system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 262system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 263system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 264system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 265system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 266system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 267system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68966.757225 # average ReadReq mshr miss latency 268system.iocache.ReadReq_avg_mshr_miss_latency::total 68966.757225 # average ReadReq mshr miss latency 269system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204562.044619 # average WriteReq mshr miss latency 270system.iocache.WriteReq_avg_mshr_miss_latency::total 204562.044619 # average WriteReq mshr miss latency 271system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203999.840072 # average overall mshr miss latency 272system.iocache.demand_avg_mshr_miss_latency::total 203999.840072 # average overall mshr miss latency 273system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203999.840072 # average overall mshr miss latency 274system.iocache.overall_avg_mshr_miss_latency::total 203999.840072 # average overall mshr miss latency 275system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 276system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 277system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 278system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 279system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 280system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 281system.disk0.dma_write_txs 395 # Number of DMA write transactions. 282system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 283system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 284system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 285system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 286system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 287system.disk2.dma_write_txs 1 # Number of DMA write transactions. 288system.cpu.dtb.fetch_hits 0 # ITB hits 289system.cpu.dtb.fetch_misses 0 # ITB misses 290system.cpu.dtb.fetch_acv 0 # ITB acv 291system.cpu.dtb.fetch_accesses 0 # ITB accesses 292system.cpu.dtb.read_hits 9056964 # DTB read hits 293system.cpu.dtb.read_misses 10329 # DTB read misses 294system.cpu.dtb.read_acv 210 # DTB read access violations 295system.cpu.dtb.read_accesses 728856 # DTB read accesses 296system.cpu.dtb.write_hits 6352252 # DTB write hits 297system.cpu.dtb.write_misses 1142 # DTB write misses 298system.cpu.dtb.write_acv 157 # DTB write access violations 299system.cpu.dtb.write_accesses 291931 # DTB write accesses 300system.cpu.dtb.data_hits 15409216 # DTB hits 301system.cpu.dtb.data_misses 11471 # DTB misses 302system.cpu.dtb.data_acv 367 # DTB access violations 303system.cpu.dtb.data_accesses 1020787 # DTB accesses 304system.cpu.itb.fetch_hits 4974658 # ITB hits 305system.cpu.itb.fetch_misses 5006 # ITB misses 306system.cpu.itb.fetch_acv 184 # ITB acv 307system.cpu.itb.fetch_accesses 4979664 # ITB accesses 308system.cpu.itb.read_hits 0 # DTB read hits 309system.cpu.itb.read_misses 0 # DTB read misses 310system.cpu.itb.read_acv 0 # DTB read access violations 311system.cpu.itb.read_accesses 0 # DTB read accesses 312system.cpu.itb.write_hits 0 # DTB write hits 313system.cpu.itb.write_misses 0 # DTB write misses 314system.cpu.itb.write_acv 0 # DTB write access violations 315system.cpu.itb.write_accesses 0 # DTB write accesses 316system.cpu.itb.data_hits 0 # DTB hits 317system.cpu.itb.data_misses 0 # DTB misses 318system.cpu.itb.data_acv 0 # DTB access violations 319system.cpu.itb.data_accesses 0 # DTB accesses 320system.cpu.numCycles 3826949380 # number of cpu cycles simulated 321system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 322system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 323system.cpu.committedInsts 56131527 # Number of instructions committed 324system.cpu.committedOps 56131527 # Number of ops (including micro ops) committed 325system.cpu.num_int_alu_accesses 52005592 # Number of integer alu accesses 326system.cpu.num_fp_alu_accesses 324259 # Number of float alu accesses 327system.cpu.num_func_calls 1482234 # number of times a function call or return occured 328system.cpu.num_conditional_control_insts 6464100 # number of instructions that are conditional controls 329system.cpu.num_int_insts 52005592 # number of integer instructions 330system.cpu.num_fp_insts 324259 # number of float instructions 331system.cpu.num_int_register_reads 71250465 # number of times the integer registers were read 332system.cpu.num_int_register_writes 38480970 # number of times the integer registers were written 333system.cpu.num_fp_register_reads 163543 # number of times the floating registers were read 334system.cpu.num_fp_register_writes 166418 # number of times the floating registers were written 335system.cpu.num_mem_refs 15461819 # number of memory refs 336system.cpu.num_load_insts 9093811 # Number of load instructions 337system.cpu.num_store_insts 6368008 # Number of store instructions 338system.cpu.num_idle_cycles 3593003741.998122 # Number of idle cycles 339system.cpu.num_busy_cycles 233945638.001878 # Number of busy cycles 340system.cpu.not_idle_fraction 0.061131 # Percentage of non-idle cycles 341system.cpu.idle_fraction 0.938869 # Percentage of idle cycles 342system.cpu.kern.inst.arm 0 # number of arm instructions executed 343system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed 344system.cpu.kern.inst.hwrei 212010 # number of hwrei instructions executed 345system.cpu.kern.ipl_count::0 74899 40.89% 40.89% # number of times we switched to this ipl 346system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl 347system.cpu.kern.ipl_count::22 1933 1.06% 42.01% # number of times we switched to this ipl 348system.cpu.kern.ipl_count::31 106230 57.99% 100.00% # number of times we switched to this ipl 349system.cpu.kern.ipl_count::total 183193 # number of times we switched to this ipl 350system.cpu.kern.ipl_good::0 73532 49.31% 49.31% # number of times we switched to this ipl from a different ipl 351system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl 352system.cpu.kern.ipl_good::22 1933 1.30% 50.69% # number of times we switched to this ipl from a different ipl 353system.cpu.kern.ipl_good::31 73532 49.31% 100.00% # number of times we switched to this ipl from a different ipl 354system.cpu.kern.ipl_good::total 149128 # number of times we switched to this ipl from a different ipl 355system.cpu.kern.ipl_ticks::0 1858610780000 97.13% 97.13% # number of cycles we spent at this ipl 356system.cpu.kern.ipl_ticks::21 91300500 0.00% 97.14% # number of cycles we spent at this ipl 357system.cpu.kern.ipl_ticks::22 737276500 0.04% 97.18% # number of cycles we spent at this ipl 358system.cpu.kern.ipl_ticks::31 54034599000 2.82% 100.00% # number of cycles we spent at this ipl 359system.cpu.kern.ipl_ticks::total 1913473956000 # number of cycles we spent at this ipl 360system.cpu.kern.ipl_used::0 0.981749 # fraction of swpipl calls that actually changed the ipl 361system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 362system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 363system.cpu.kern.ipl_used::31 0.692196 # fraction of swpipl calls that actually changed the ipl 364system.cpu.kern.ipl_used::total 0.814049 # fraction of swpipl calls that actually changed the ipl 365system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 366system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 367system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 368system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 369system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 370system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 371system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 372system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed 373system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed 374system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed 375system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed 376system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed 377system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed 378system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed 379system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed 380system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed 381system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed 382system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed 383system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed 384system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed 385system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed 386system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed 387system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed 388system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed 389system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed 390system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed 391system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed 392system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 393system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 394system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 395system.cpu.kern.syscall::total 326 # number of syscalls executed 396system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 397system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 398system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 399system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 400system.cpu.kern.callpal::swpctx 4174 2.16% 2.17% # number of callpals executed 401system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed 402system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed 403system.cpu.kern.callpal::swpipl 175970 91.22% 93.41% # number of callpals executed 404system.cpu.kern.callpal::rdps 6834 3.54% 96.96% # number of callpals executed 405system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed 406system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed 407system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed 408system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed 409system.cpu.kern.callpal::rti 5158 2.67% 99.64% # number of callpals executed 410system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 411system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed 412system.cpu.kern.callpal::total 192916 # number of callpals executed 413system.cpu.kern.mode_switch::kernel 5900 # number of protection mode switches 414system.cpu.kern.mode_switch::user 1742 # number of protection mode switches 415system.cpu.kern.mode_switch::idle 2098 # number of protection mode switches 416system.cpu.kern.mode_good::kernel 1911 417system.cpu.kern.mode_good::user 1742 418system.cpu.kern.mode_good::idle 169 419system.cpu.kern.mode_switch_good::kernel 0.323898 # fraction of useful protection mode switches 420system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 421system.cpu.kern.mode_switch_good::idle 0.080553 # fraction of useful protection mode switches 422system.cpu.kern.mode_switch_good::total 0.392402 # fraction of useful protection mode switches 423system.cpu.kern.mode_ticks::kernel 45394142000 2.37% 2.37% # number of ticks spent at the given mode 424system.cpu.kern.mode_ticks::user 5131394000 0.27% 2.64% # number of ticks spent at the given mode 425system.cpu.kern.mode_ticks::idle 1862948418000 97.36% 100.00% # number of ticks spent at the given mode 426system.cpu.kern.swap_context 4175 # number of times the context was actually changed 427system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 428system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 429system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 430system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 431system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 432system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 433system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 434system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 435system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 436system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 437system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 438system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 439system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 440system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 441system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 442system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 443system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 444system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 445system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 446system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 447system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 448system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 449system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 450system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 451system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 452system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 453system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 454system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 455system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 456system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 457system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 458system.cpu.icache.replacements 927958 # number of replacements 459system.cpu.icache.tagsinuse 509.106403 # Cycle average of tags in use 460system.cpu.icache.total_refs 55214738 # Total number of references to valid blocks. 461system.cpu.icache.sampled_refs 928469 # Sample count of references to valid blocks. 462system.cpu.icache.avg_refs 59.468585 # Average number of references to valid blocks. 463system.cpu.icache.warmup_cycle 32313596000 # Cycle when the warmup percentage was hit. 464system.cpu.icache.occ_blocks::cpu.inst 509.106403 # Average occupied blocks per requestor 465system.cpu.icache.occ_percent::cpu.inst 0.994348 # Average percentage of cache occupancy 466system.cpu.icache.occ_percent::total 0.994348 # Average percentage of cache occupancy 467system.cpu.icache.ReadReq_hits::cpu.inst 55214738 # number of ReadReq hits 468system.cpu.icache.ReadReq_hits::total 55214738 # number of ReadReq hits 469system.cpu.icache.demand_hits::cpu.inst 55214738 # number of demand (read+write) hits 470system.cpu.icache.demand_hits::total 55214738 # number of demand (read+write) hits 471system.cpu.icache.overall_hits::cpu.inst 55214738 # number of overall hits 472system.cpu.icache.overall_hits::total 55214738 # number of overall hits 473system.cpu.icache.ReadReq_misses::cpu.inst 928628 # number of ReadReq misses 474system.cpu.icache.ReadReq_misses::total 928628 # number of ReadReq misses 475system.cpu.icache.demand_misses::cpu.inst 928628 # number of demand (read+write) misses 476system.cpu.icache.demand_misses::total 928628 # number of demand (read+write) misses 477system.cpu.icache.overall_misses::cpu.inst 928628 # number of overall misses 478system.cpu.icache.overall_misses::total 928628 # number of overall misses 479system.cpu.icache.ReadReq_miss_latency::cpu.inst 12770278000 # number of ReadReq miss cycles 480system.cpu.icache.ReadReq_miss_latency::total 12770278000 # number of ReadReq miss cycles 481system.cpu.icache.demand_miss_latency::cpu.inst 12770278000 # number of demand (read+write) miss cycles 482system.cpu.icache.demand_miss_latency::total 12770278000 # number of demand (read+write) miss cycles 483system.cpu.icache.overall_miss_latency::cpu.inst 12770278000 # number of overall miss cycles 484system.cpu.icache.overall_miss_latency::total 12770278000 # number of overall miss cycles 485system.cpu.icache.ReadReq_accesses::cpu.inst 56143366 # number of ReadReq accesses(hits+misses) 486system.cpu.icache.ReadReq_accesses::total 56143366 # number of ReadReq accesses(hits+misses) 487system.cpu.icache.demand_accesses::cpu.inst 56143366 # number of demand (read+write) accesses 488system.cpu.icache.demand_accesses::total 56143366 # number of demand (read+write) accesses 489system.cpu.icache.overall_accesses::cpu.inst 56143366 # number of overall (read+write) accesses 490system.cpu.icache.overall_accesses::total 56143366 # number of overall (read+write) accesses 491system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016540 # miss rate for ReadReq accesses 492system.cpu.icache.ReadReq_miss_rate::total 0.016540 # miss rate for ReadReq accesses 493system.cpu.icache.demand_miss_rate::cpu.inst 0.016540 # miss rate for demand accesses 494system.cpu.icache.demand_miss_rate::total 0.016540 # miss rate for demand accesses 495system.cpu.icache.overall_miss_rate::cpu.inst 0.016540 # miss rate for overall accesses 496system.cpu.icache.overall_miss_rate::total 0.016540 # miss rate for overall accesses 497system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13751.769277 # average ReadReq miss latency 498system.cpu.icache.ReadReq_avg_miss_latency::total 13751.769277 # average ReadReq miss latency 499system.cpu.icache.demand_avg_miss_latency::cpu.inst 13751.769277 # average overall miss latency 500system.cpu.icache.demand_avg_miss_latency::total 13751.769277 # average overall miss latency 501system.cpu.icache.overall_avg_miss_latency::cpu.inst 13751.769277 # average overall miss latency 502system.cpu.icache.overall_avg_miss_latency::total 13751.769277 # average overall miss latency 503system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 504system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 505system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 506system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 507system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 508system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 509system.cpu.icache.fast_writes 0 # number of fast writes performed 510system.cpu.icache.cache_copies 0 # number of cache copies performed 511system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928628 # number of ReadReq MSHR misses 512system.cpu.icache.ReadReq_mshr_misses::total 928628 # number of ReadReq MSHR misses 513system.cpu.icache.demand_mshr_misses::cpu.inst 928628 # number of demand (read+write) MSHR misses 514system.cpu.icache.demand_mshr_misses::total 928628 # number of demand (read+write) MSHR misses 515system.cpu.icache.overall_mshr_misses::cpu.inst 928628 # number of overall MSHR misses 516system.cpu.icache.overall_mshr_misses::total 928628 # number of overall MSHR misses 517system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10913022000 # number of ReadReq MSHR miss cycles 518system.cpu.icache.ReadReq_mshr_miss_latency::total 10913022000 # number of ReadReq MSHR miss cycles 519system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10913022000 # number of demand (read+write) MSHR miss cycles 520system.cpu.icache.demand_mshr_miss_latency::total 10913022000 # number of demand (read+write) MSHR miss cycles 521system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10913022000 # number of overall MSHR miss cycles 522system.cpu.icache.overall_mshr_miss_latency::total 10913022000 # number of overall MSHR miss cycles 523system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for ReadReq accesses 524system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016540 # mshr miss rate for ReadReq accesses 525system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for demand accesses 526system.cpu.icache.demand_mshr_miss_rate::total 0.016540 # mshr miss rate for demand accesses 527system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for overall accesses 528system.cpu.icache.overall_mshr_miss_rate::total 0.016540 # mshr miss rate for overall accesses 529system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11751.769277 # average ReadReq mshr miss latency 530system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11751.769277 # average ReadReq mshr miss latency 531system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11751.769277 # average overall mshr miss latency 532system.cpu.icache.demand_avg_mshr_miss_latency::total 11751.769277 # average overall mshr miss latency 533system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11751.769277 # average overall mshr miss latency 534system.cpu.icache.overall_avg_mshr_miss_latency::total 11751.769277 # average overall mshr miss latency 535system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 536system.cpu.l2cache.replacements 336244 # number of replacements 537system.cpu.l2cache.tagsinuse 65321.744295 # Cycle average of tags in use 538system.cpu.l2cache.total_refs 2445552 # Total number of references to valid blocks. 539system.cpu.l2cache.sampled_refs 401406 # Sample count of references to valid blocks. 540system.cpu.l2cache.avg_refs 6.092465 # Average number of references to valid blocks. 541system.cpu.l2cache.warmup_cycle 5250002751 # Cycle when the warmup percentage was hit. 542system.cpu.l2cache.occ_blocks::writebacks 55750.890928 # Average occupied blocks per requestor 543system.cpu.l2cache.occ_blocks::cpu.inst 4786.700552 # Average occupied blocks per requestor 544system.cpu.l2cache.occ_blocks::cpu.data 4784.152815 # Average occupied blocks per requestor 545system.cpu.l2cache.occ_percent::writebacks 0.850691 # Average percentage of cache occupancy 546system.cpu.l2cache.occ_percent::cpu.inst 0.073039 # Average percentage of cache occupancy 547system.cpu.l2cache.occ_percent::cpu.data 0.073000 # Average percentage of cache occupancy 548system.cpu.l2cache.occ_percent::total 0.996731 # Average percentage of cache occupancy 549system.cpu.l2cache.ReadReq_hits::cpu.inst 915318 # number of ReadReq hits 550system.cpu.l2cache.ReadReq_hits::cpu.data 813981 # number of ReadReq hits 551system.cpu.l2cache.ReadReq_hits::total 1729299 # number of ReadReq hits 552system.cpu.l2cache.Writeback_hits::writebacks 834498 # number of Writeback hits 553system.cpu.l2cache.Writeback_hits::total 834498 # number of Writeback hits 554system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits 555system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits 556system.cpu.l2cache.ReadExReq_hits::cpu.data 187514 # number of ReadExReq hits 557system.cpu.l2cache.ReadExReq_hits::total 187514 # number of ReadExReq hits 558system.cpu.l2cache.demand_hits::cpu.inst 915318 # number of demand (read+write) hits 559system.cpu.l2cache.demand_hits::cpu.data 1001495 # number of demand (read+write) hits 560system.cpu.l2cache.demand_hits::total 1916813 # number of demand (read+write) hits 561system.cpu.l2cache.overall_hits::cpu.inst 915318 # number of overall hits 562system.cpu.l2cache.overall_hits::cpu.data 1001495 # number of overall hits 563system.cpu.l2cache.overall_hits::total 1916813 # number of overall hits 564system.cpu.l2cache.ReadReq_misses::cpu.inst 13290 # number of ReadReq misses 565system.cpu.l2cache.ReadReq_misses::cpu.data 271963 # number of ReadReq misses 566system.cpu.l2cache.ReadReq_misses::total 285253 # number of ReadReq misses 567system.cpu.l2cache.UpgradeReq_misses::cpu.data 13 # number of UpgradeReq misses 568system.cpu.l2cache.UpgradeReq_misses::total 13 # number of UpgradeReq misses 569system.cpu.l2cache.ReadExReq_misses::cpu.data 116856 # number of ReadExReq misses 570system.cpu.l2cache.ReadExReq_misses::total 116856 # number of ReadExReq misses 571system.cpu.l2cache.demand_misses::cpu.inst 13290 # number of demand (read+write) misses 572system.cpu.l2cache.demand_misses::cpu.data 388819 # number of demand (read+write) misses 573system.cpu.l2cache.demand_misses::total 402109 # number of demand (read+write) misses 574system.cpu.l2cache.overall_misses::cpu.inst 13290 # number of overall misses 575system.cpu.l2cache.overall_misses::cpu.data 388819 # number of overall misses 576system.cpu.l2cache.overall_misses::total 402109 # number of overall misses 577system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 831194000 # number of ReadReq miss cycles 578system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11699138000 # number of ReadReq miss cycles 579system.cpu.l2cache.ReadReq_miss_latency::total 12530332000 # number of ReadReq miss cycles 580system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 189500 # number of UpgradeReq miss cycles 581system.cpu.l2cache.UpgradeReq_miss_latency::total 189500 # number of UpgradeReq miss cycles 582system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5596958000 # number of ReadExReq miss cycles 583system.cpu.l2cache.ReadExReq_miss_latency::total 5596958000 # number of ReadExReq miss cycles 584system.cpu.l2cache.demand_miss_latency::cpu.inst 831194000 # number of demand (read+write) miss cycles 585system.cpu.l2cache.demand_miss_latency::cpu.data 17296096000 # number of demand (read+write) miss cycles 586system.cpu.l2cache.demand_miss_latency::total 18127290000 # number of demand (read+write) miss cycles 587system.cpu.l2cache.overall_miss_latency::cpu.inst 831194000 # number of overall miss cycles 588system.cpu.l2cache.overall_miss_latency::cpu.data 17296096000 # number of overall miss cycles 589system.cpu.l2cache.overall_miss_latency::total 18127290000 # number of overall miss cycles 590system.cpu.l2cache.ReadReq_accesses::cpu.inst 928608 # number of ReadReq accesses(hits+misses) 591system.cpu.l2cache.ReadReq_accesses::cpu.data 1085944 # number of ReadReq accesses(hits+misses) 592system.cpu.l2cache.ReadReq_accesses::total 2014552 # number of ReadReq accesses(hits+misses) 593system.cpu.l2cache.Writeback_accesses::writebacks 834498 # number of Writeback accesses(hits+misses) 594system.cpu.l2cache.Writeback_accesses::total 834498 # number of Writeback accesses(hits+misses) 595system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses) 596system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses) 597system.cpu.l2cache.ReadExReq_accesses::cpu.data 304370 # number of ReadExReq accesses(hits+misses) 598system.cpu.l2cache.ReadExReq_accesses::total 304370 # number of ReadExReq accesses(hits+misses) 599system.cpu.l2cache.demand_accesses::cpu.inst 928608 # number of demand (read+write) accesses 600system.cpu.l2cache.demand_accesses::cpu.data 1390314 # number of demand (read+write) accesses 601system.cpu.l2cache.demand_accesses::total 2318922 # number of demand (read+write) accesses 602system.cpu.l2cache.overall_accesses::cpu.inst 928608 # number of overall (read+write) accesses 603system.cpu.l2cache.overall_accesses::cpu.data 1390314 # number of overall (read+write) accesses 604system.cpu.l2cache.overall_accesses::total 2318922 # number of overall (read+write) accesses 605system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014312 # miss rate for ReadReq accesses 606system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250439 # miss rate for ReadReq accesses 607system.cpu.l2cache.ReadReq_miss_rate::total 0.141596 # miss rate for ReadReq accesses 608system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.764706 # miss rate for UpgradeReq accesses 609system.cpu.l2cache.UpgradeReq_miss_rate::total 0.764706 # miss rate for UpgradeReq accesses 610system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383927 # miss rate for ReadExReq accesses 611system.cpu.l2cache.ReadExReq_miss_rate::total 0.383927 # miss rate for ReadExReq accesses 612system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014312 # miss rate for demand accesses 613system.cpu.l2cache.demand_miss_rate::cpu.data 0.279663 # miss rate for demand accesses 614system.cpu.l2cache.demand_miss_rate::total 0.173403 # miss rate for demand accesses 615system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014312 # miss rate for overall accesses 616system.cpu.l2cache.overall_miss_rate::cpu.data 0.279663 # miss rate for overall accesses 617system.cpu.l2cache.overall_miss_rate::total 0.173403 # miss rate for overall accesses 618system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 62542.814146 # average ReadReq miss latency 619system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 43017.388395 # average ReadReq miss latency 620system.cpu.l2cache.ReadReq_avg_miss_latency::total 43927.082274 # average ReadReq miss latency 621system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 14576.923077 # average UpgradeReq miss latency 622system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 14576.923077 # average UpgradeReq miss latency 623system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 47896.197029 # average ReadExReq miss latency 624system.cpu.l2cache.ReadExReq_avg_miss_latency::total 47896.197029 # average ReadExReq miss latency 625system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 62542.814146 # average overall miss latency 626system.cpu.l2cache.demand_avg_miss_latency::cpu.data 44483.669780 # average overall miss latency 627system.cpu.l2cache.demand_avg_miss_latency::total 45080.537864 # average overall miss latency 628system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 62542.814146 # average overall miss latency 629system.cpu.l2cache.overall_avg_miss_latency::cpu.data 44483.669780 # average overall miss latency 630system.cpu.l2cache.overall_avg_miss_latency::total 45080.537864 # average overall miss latency 631system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 632system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 633system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 634system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 635system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 636system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 637system.cpu.l2cache.fast_writes 0 # number of fast writes performed 638system.cpu.l2cache.cache_copies 0 # number of cache copies performed 639system.cpu.l2cache.writebacks::writebacks 74191 # number of writebacks 640system.cpu.l2cache.writebacks::total 74191 # number of writebacks 641system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13290 # number of ReadReq MSHR misses 642system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271963 # number of ReadReq MSHR misses 643system.cpu.l2cache.ReadReq_mshr_misses::total 285253 # number of ReadReq MSHR misses 644system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses 645system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses 646system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116856 # number of ReadExReq MSHR misses 647system.cpu.l2cache.ReadExReq_mshr_misses::total 116856 # number of ReadExReq MSHR misses 648system.cpu.l2cache.demand_mshr_misses::cpu.inst 13290 # number of demand (read+write) MSHR misses 649system.cpu.l2cache.demand_mshr_misses::cpu.data 388819 # number of demand (read+write) MSHR misses 650system.cpu.l2cache.demand_mshr_misses::total 402109 # number of demand (read+write) MSHR misses 651system.cpu.l2cache.overall_mshr_misses::cpu.inst 13290 # number of overall MSHR misses 652system.cpu.l2cache.overall_mshr_misses::cpu.data 388819 # number of overall MSHR misses 653system.cpu.l2cache.overall_mshr_misses::total 402109 # number of overall MSHR misses 654system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 666266030 # number of ReadReq MSHR miss cycles 655system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8360156960 # number of ReadReq MSHR miss cycles 656system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9026422990 # number of ReadReq MSHR miss cycles 657system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 230011 # number of UpgradeReq MSHR miss cycles 658system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 230011 # number of UpgradeReq MSHR miss cycles 659system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4160193080 # number of ReadExReq MSHR miss cycles 660system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4160193080 # number of ReadExReq MSHR miss cycles 661system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 666266030 # number of demand (read+write) MSHR miss cycles 662system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12520350040 # number of demand (read+write) MSHR miss cycles 663system.cpu.l2cache.demand_mshr_miss_latency::total 13186616070 # number of demand (read+write) MSHR miss cycles 664system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 666266030 # number of overall MSHR miss cycles 665system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12520350040 # number of overall MSHR miss cycles 666system.cpu.l2cache.overall_mshr_miss_latency::total 13186616070 # number of overall MSHR miss cycles 667system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334146000 # number of ReadReq MSHR uncacheable cycles 668system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334146000 # number of ReadReq MSHR uncacheable cycles 669system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1895853000 # number of WriteReq MSHR uncacheable cycles 670system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1895853000 # number of WriteReq MSHR uncacheable cycles 671system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3229999000 # number of overall MSHR uncacheable cycles 672system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3229999000 # number of overall MSHR uncacheable cycles 673system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014312 # mshr miss rate for ReadReq accesses 674system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250439 # mshr miss rate for ReadReq accesses 675system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141596 # mshr miss rate for ReadReq accesses 676system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses 677system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses 678system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383927 # mshr miss rate for ReadExReq accesses 679system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383927 # mshr miss rate for ReadExReq accesses 680system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014312 # mshr miss rate for demand accesses 681system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279663 # mshr miss rate for demand accesses 682system.cpu.l2cache.demand_mshr_miss_rate::total 0.173403 # mshr miss rate for demand accesses 683system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014312 # mshr miss rate for overall accesses 684system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279663 # mshr miss rate for overall accesses 685system.cpu.l2cache.overall_mshr_miss_rate::total 0.173403 # mshr miss rate for overall accesses 686system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 50132.884123 # average ReadReq mshr miss latency 687system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30740.052728 # average ReadReq mshr miss latency 688system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31643.569007 # average ReadReq mshr miss latency 689system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17693.153846 # average UpgradeReq mshr miss latency 690system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17693.153846 # average UpgradeReq mshr miss latency 691system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35601.022455 # average ReadExReq mshr miss latency 692system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35601.022455 # average ReadExReq mshr miss latency 693system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50132.884123 # average overall mshr miss latency 694system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 32200.972792 # average overall mshr miss latency 695system.cpu.l2cache.demand_avg_mshr_miss_latency::total 32793.635731 # average overall mshr miss latency 696system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50132.884123 # average overall mshr miss latency 697system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 32200.972792 # average overall mshr miss latency 698system.cpu.l2cache.overall_avg_mshr_miss_latency::total 32793.635731 # average overall mshr miss latency 699system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 700system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 701system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 702system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 703system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 704system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 705system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 706system.cpu.dcache.replacements 1389801 # number of replacements 707system.cpu.dcache.tagsinuse 511.980871 # Cycle average of tags in use 708system.cpu.dcache.total_refs 14037928 # Total number of references to valid blocks. 709system.cpu.dcache.sampled_refs 1390313 # Sample count of references to valid blocks. 710system.cpu.dcache.avg_refs 10.096955 # Average number of references to valid blocks. 711system.cpu.dcache.warmup_cycle 93552000 # Cycle when the warmup percentage was hit. 712system.cpu.dcache.occ_blocks::cpu.data 511.980871 # Average occupied blocks per requestor 713system.cpu.dcache.occ_percent::cpu.data 0.999963 # Average percentage of cache occupancy 714system.cpu.dcache.occ_percent::total 0.999963 # Average percentage of cache occupancy 715system.cpu.dcache.ReadReq_hits::cpu.data 7807394 # number of ReadReq hits 716system.cpu.dcache.ReadReq_hits::total 7807394 # number of ReadReq hits 717system.cpu.dcache.WriteReq_hits::cpu.data 5848285 # number of WriteReq hits 718system.cpu.dcache.WriteReq_hits::total 5848285 # number of WriteReq hits 719system.cpu.dcache.LoadLockedReq_hits::cpu.data 183004 # number of LoadLockedReq hits 720system.cpu.dcache.LoadLockedReq_hits::total 183004 # number of LoadLockedReq hits 721system.cpu.dcache.StoreCondReq_hits::cpu.data 199228 # number of StoreCondReq hits 722system.cpu.dcache.StoreCondReq_hits::total 199228 # number of StoreCondReq hits 723system.cpu.dcache.demand_hits::cpu.data 13655679 # number of demand (read+write) hits 724system.cpu.dcache.demand_hits::total 13655679 # number of demand (read+write) hits 725system.cpu.dcache.overall_hits::cpu.data 13655679 # number of overall hits 726system.cpu.dcache.overall_hits::total 13655679 # number of overall hits 727system.cpu.dcache.ReadReq_misses::cpu.data 1068700 # number of ReadReq misses 728system.cpu.dcache.ReadReq_misses::total 1068700 # number of ReadReq misses 729system.cpu.dcache.WriteReq_misses::cpu.data 304387 # number of WriteReq misses 730system.cpu.dcache.WriteReq_misses::total 304387 # number of WriteReq misses 731system.cpu.dcache.LoadLockedReq_misses::cpu.data 17244 # number of LoadLockedReq misses 732system.cpu.dcache.LoadLockedReq_misses::total 17244 # number of LoadLockedReq misses 733system.cpu.dcache.demand_misses::cpu.data 1373087 # number of demand (read+write) misses 734system.cpu.dcache.demand_misses::total 1373087 # number of demand (read+write) misses 735system.cpu.dcache.overall_misses::cpu.data 1373087 # number of overall misses 736system.cpu.dcache.overall_misses::total 1373087 # number of overall misses 737system.cpu.dcache.ReadReq_miss_latency::cpu.data 22867911000 # number of ReadReq miss cycles 738system.cpu.dcache.ReadReq_miss_latency::total 22867911000 # number of ReadReq miss cycles 739system.cpu.dcache.WriteReq_miss_latency::cpu.data 8385686000 # number of WriteReq miss cycles 740system.cpu.dcache.WriteReq_miss_latency::total 8385686000 # number of WriteReq miss cycles 741system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228869000 # number of LoadLockedReq miss cycles 742system.cpu.dcache.LoadLockedReq_miss_latency::total 228869000 # number of LoadLockedReq miss cycles 743system.cpu.dcache.demand_miss_latency::cpu.data 31253597000 # number of demand (read+write) miss cycles 744system.cpu.dcache.demand_miss_latency::total 31253597000 # number of demand (read+write) miss cycles 745system.cpu.dcache.overall_miss_latency::cpu.data 31253597000 # number of overall miss cycles 746system.cpu.dcache.overall_miss_latency::total 31253597000 # number of overall miss cycles 747system.cpu.dcache.ReadReq_accesses::cpu.data 8876094 # number of ReadReq accesses(hits+misses) 748system.cpu.dcache.ReadReq_accesses::total 8876094 # number of ReadReq accesses(hits+misses) 749system.cpu.dcache.WriteReq_accesses::cpu.data 6152672 # number of WriteReq accesses(hits+misses) 750system.cpu.dcache.WriteReq_accesses::total 6152672 # number of WriteReq accesses(hits+misses) 751system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200248 # number of LoadLockedReq accesses(hits+misses) 752system.cpu.dcache.LoadLockedReq_accesses::total 200248 # number of LoadLockedReq accesses(hits+misses) 753system.cpu.dcache.StoreCondReq_accesses::cpu.data 199228 # number of StoreCondReq accesses(hits+misses) 754system.cpu.dcache.StoreCondReq_accesses::total 199228 # number of StoreCondReq accesses(hits+misses) 755system.cpu.dcache.demand_accesses::cpu.data 15028766 # number of demand (read+write) accesses 756system.cpu.dcache.demand_accesses::total 15028766 # number of demand (read+write) accesses 757system.cpu.dcache.overall_accesses::cpu.data 15028766 # number of overall (read+write) accesses 758system.cpu.dcache.overall_accesses::total 15028766 # number of overall (read+write) accesses 759system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120402 # miss rate for ReadReq accesses 760system.cpu.dcache.ReadReq_miss_rate::total 0.120402 # miss rate for ReadReq accesses 761system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049472 # miss rate for WriteReq accesses 762system.cpu.dcache.WriteReq_miss_rate::total 0.049472 # miss rate for WriteReq accesses 763system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086113 # miss rate for LoadLockedReq accesses 764system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086113 # miss rate for LoadLockedReq accesses 765system.cpu.dcache.demand_miss_rate::cpu.data 0.091364 # miss rate for demand accesses 766system.cpu.dcache.demand_miss_rate::total 0.091364 # miss rate for demand accesses 767system.cpu.dcache.overall_miss_rate::cpu.data 0.091364 # miss rate for overall accesses 768system.cpu.dcache.overall_miss_rate::total 0.091364 # miss rate for overall accesses 769system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21397.876860 # average ReadReq miss latency 770system.cpu.dcache.ReadReq_avg_miss_latency::total 21397.876860 # average ReadReq miss latency 771system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27549.422282 # average WriteReq miss latency 772system.cpu.dcache.WriteReq_avg_miss_latency::total 27549.422282 # average WriteReq miss latency 773system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13272.384598 # average LoadLockedReq miss latency 774system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13272.384598 # average LoadLockedReq miss latency 775system.cpu.dcache.demand_avg_miss_latency::cpu.data 22761.556260 # average overall miss latency 776system.cpu.dcache.demand_avg_miss_latency::total 22761.556260 # average overall miss latency 777system.cpu.dcache.overall_avg_miss_latency::cpu.data 22761.556260 # average overall miss latency 778system.cpu.dcache.overall_avg_miss_latency::total 22761.556260 # average overall miss latency 779system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 780system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 781system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 782system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 783system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 784system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 785system.cpu.dcache.fast_writes 0 # number of fast writes performed 786system.cpu.dcache.cache_copies 0 # number of cache copies performed 787system.cpu.dcache.writebacks::writebacks 834498 # number of writebacks 788system.cpu.dcache.writebacks::total 834498 # number of writebacks 789system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1068700 # number of ReadReq MSHR misses 790system.cpu.dcache.ReadReq_mshr_misses::total 1068700 # number of ReadReq MSHR misses 791system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304387 # number of WriteReq MSHR misses 792system.cpu.dcache.WriteReq_mshr_misses::total 304387 # number of WriteReq MSHR misses 793system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17244 # number of LoadLockedReq MSHR misses 794system.cpu.dcache.LoadLockedReq_mshr_misses::total 17244 # number of LoadLockedReq MSHR misses 795system.cpu.dcache.demand_mshr_misses::cpu.data 1373087 # number of demand (read+write) MSHR misses 796system.cpu.dcache.demand_mshr_misses::total 1373087 # number of demand (read+write) MSHR misses 797system.cpu.dcache.overall_mshr_misses::cpu.data 1373087 # number of overall MSHR misses 798system.cpu.dcache.overall_mshr_misses::total 1373087 # number of overall MSHR misses 799system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 20730511000 # number of ReadReq MSHR miss cycles 800system.cpu.dcache.ReadReq_mshr_miss_latency::total 20730511000 # number of ReadReq MSHR miss cycles 801system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7776912000 # number of WriteReq MSHR miss cycles 802system.cpu.dcache.WriteReq_mshr_miss_latency::total 7776912000 # number of WriteReq MSHR miss cycles 803system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 194381000 # number of LoadLockedReq MSHR miss cycles 804system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 194381000 # number of LoadLockedReq MSHR miss cycles 805system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28507423000 # number of demand (read+write) MSHR miss cycles 806system.cpu.dcache.demand_mshr_miss_latency::total 28507423000 # number of demand (read+write) MSHR miss cycles 807system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28507423000 # number of overall MSHR miss cycles 808system.cpu.dcache.overall_mshr_miss_latency::total 28507423000 # number of overall MSHR miss cycles 809system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424236000 # number of ReadReq MSHR uncacheable cycles 810system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424236000 # number of ReadReq MSHR uncacheable cycles 811system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011665000 # number of WriteReq MSHR uncacheable cycles 812system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011665000 # number of WriteReq MSHR uncacheable cycles 813system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435901000 # number of overall MSHR uncacheable cycles 814system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435901000 # number of overall MSHR uncacheable cycles 815system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120402 # mshr miss rate for ReadReq accesses 816system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120402 # mshr miss rate for ReadReq accesses 817system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049472 # mshr miss rate for WriteReq accesses 818system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049472 # mshr miss rate for WriteReq accesses 819system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086113 # mshr miss rate for LoadLockedReq accesses 820system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086113 # mshr miss rate for LoadLockedReq accesses 821system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091364 # mshr miss rate for demand accesses 822system.cpu.dcache.demand_mshr_miss_rate::total 0.091364 # mshr miss rate for demand accesses 823system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091364 # mshr miss rate for overall accesses 824system.cpu.dcache.overall_mshr_miss_rate::total 0.091364 # mshr miss rate for overall accesses 825system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19397.876860 # average ReadReq mshr miss latency 826system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19397.876860 # average ReadReq mshr miss latency 827system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25549.422282 # average WriteReq mshr miss latency 828system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25549.422282 # average WriteReq mshr miss latency 829system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11272.384598 # average LoadLockedReq mshr miss latency 830system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11272.384598 # average LoadLockedReq mshr miss latency 831system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20761.556260 # average overall mshr miss latency 832system.cpu.dcache.demand_avg_mshr_miss_latency::total 20761.556260 # average overall mshr miss latency 833system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20761.556260 # average overall mshr miss latency 834system.cpu.dcache.overall_avg_mshr_miss_latency::total 20761.556260 # average overall mshr miss latency 835system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 836system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 837system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 838system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 839system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 840system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 841system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 842 843---------- End Simulation Statistics ---------- 844