stats.txt revision 9229:65f927bda74d
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.920895 # Number of seconds simulated 4sim_ticks 1920895294000 # Number of ticks simulated 5final_tick 1920895294000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1271848 # Simulator instruction rate (inst/s) 8host_op_rate 1271848 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 43474553061 # Simulator tick rate (ticks/s) 10host_mem_usage 295012 # Number of bytes of host memory used 11host_seconds 44.18 # Real time elapsed on the host 12sim_insts 56195754 # Number of instructions simulated 13sim_ops 56195754 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 850496 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 24859968 # Number of bytes read from this memory 16system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory 17system.physmem.bytes_read::total 28362816 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 850496 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 850496 # Number of instructions bytes read from this memory 20system.physmem.bytes_written::writebacks 7404288 # Number of bytes written to this memory 21system.physmem.bytes_written::total 7404288 # Number of bytes written to this memory 22system.physmem.num_reads::cpu.inst 13289 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 388437 # Number of read requests responded to by this memory 24system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 443169 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 115692 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 115692 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 442760 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 12941865 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::tsunami.ide 1380789 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 14765415 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 442760 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 442760 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 3854603 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 3854603 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 3854603 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 442760 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 12941865 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::tsunami.ide 1380789 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::total 18620018 # Total bandwidth to/from this memory (bytes/s) 41system.l2c.replacements 336257 # number of replacements 42system.l2c.tagsinuse 65308.063316 # Cycle average of tags in use 43system.l2c.total_refs 2448454 # Total number of references to valid blocks. 44system.l2c.sampled_refs 401419 # Sample count of references to valid blocks. 45system.l2c.avg_refs 6.099497 # Average number of references to valid blocks. 46system.l2c.warmup_cycle 6040304000 # Cycle when the warmup percentage was hit. 47system.l2c.occ_blocks::writebacks 55656.590733 # Average occupied blocks per requestor 48system.l2c.occ_blocks::cpu.inst 4765.137084 # Average occupied blocks per requestor 49system.l2c.occ_blocks::cpu.data 4886.335499 # Average occupied blocks per requestor 50system.l2c.occ_percent::writebacks 0.849252 # Average percentage of cache occupancy 51system.l2c.occ_percent::cpu.inst 0.072710 # Average percentage of cache occupancy 52system.l2c.occ_percent::cpu.data 0.074560 # Average percentage of cache occupancy 53system.l2c.occ_percent::total 0.996522 # Average percentage of cache occupancy 54system.l2c.ReadReq_hits::cpu.inst 916463 # number of ReadReq hits 55system.l2c.ReadReq_hits::cpu.data 814985 # number of ReadReq hits 56system.l2c.ReadReq_hits::total 1731448 # number of ReadReq hits 57system.l2c.Writeback_hits::writebacks 835257 # number of Writeback hits 58system.l2c.Writeback_hits::total 835257 # number of Writeback hits 59system.l2c.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits 60system.l2c.UpgradeReq_hits::total 4 # number of UpgradeReq hits 61system.l2c.ReadExReq_hits::cpu.data 187565 # number of ReadExReq hits 62system.l2c.ReadExReq_hits::total 187565 # number of ReadExReq hits 63system.l2c.demand_hits::cpu.inst 916463 # number of demand (read+write) hits 64system.l2c.demand_hits::cpu.data 1002550 # number of demand (read+write) hits 65system.l2c.demand_hits::total 1919013 # number of demand (read+write) hits 66system.l2c.overall_hits::cpu.inst 916463 # number of overall hits 67system.l2c.overall_hits::cpu.data 1002550 # number of overall hits 68system.l2c.overall_hits::total 1919013 # number of overall hits 69system.l2c.ReadReq_misses::cpu.inst 13289 # number of ReadReq misses 70system.l2c.ReadReq_misses::cpu.data 271966 # number of ReadReq misses 71system.l2c.ReadReq_misses::total 285255 # number of ReadReq misses 72system.l2c.UpgradeReq_misses::cpu.data 13 # number of UpgradeReq misses 73system.l2c.UpgradeReq_misses::total 13 # number of UpgradeReq misses 74system.l2c.ReadExReq_misses::cpu.data 116861 # number of ReadExReq misses 75system.l2c.ReadExReq_misses::total 116861 # number of ReadExReq misses 76system.l2c.demand_misses::cpu.inst 13289 # number of demand (read+write) misses 77system.l2c.demand_misses::cpu.data 388827 # number of demand (read+write) misses 78system.l2c.demand_misses::total 402116 # number of demand (read+write) misses 79system.l2c.overall_misses::cpu.inst 13289 # number of overall misses 80system.l2c.overall_misses::cpu.data 388827 # number of overall misses 81system.l2c.overall_misses::total 402116 # number of overall misses 82system.l2c.ReadReq_miss_latency::cpu.inst 691205000 # number of ReadReq miss cycles 83system.l2c.ReadReq_miss_latency::cpu.data 14147611000 # number of ReadReq miss cycles 84system.l2c.ReadReq_miss_latency::total 14838816000 # number of ReadReq miss cycles 85system.l2c.UpgradeReq_miss_latency::cpu.data 248000 # number of UpgradeReq miss cycles 86system.l2c.UpgradeReq_miss_latency::total 248000 # number of UpgradeReq miss cycles 87system.l2c.ReadExReq_miss_latency::cpu.data 6077413000 # number of ReadExReq miss cycles 88system.l2c.ReadExReq_miss_latency::total 6077413000 # number of ReadExReq miss cycles 89system.l2c.demand_miss_latency::cpu.inst 691205000 # number of demand (read+write) miss cycles 90system.l2c.demand_miss_latency::cpu.data 20225024000 # number of demand (read+write) miss cycles 91system.l2c.demand_miss_latency::total 20916229000 # number of demand (read+write) miss cycles 92system.l2c.overall_miss_latency::cpu.inst 691205000 # number of overall miss cycles 93system.l2c.overall_miss_latency::cpu.data 20225024000 # number of overall miss cycles 94system.l2c.overall_miss_latency::total 20916229000 # number of overall miss cycles 95system.l2c.ReadReq_accesses::cpu.inst 929752 # number of ReadReq accesses(hits+misses) 96system.l2c.ReadReq_accesses::cpu.data 1086951 # number of ReadReq accesses(hits+misses) 97system.l2c.ReadReq_accesses::total 2016703 # number of ReadReq accesses(hits+misses) 98system.l2c.Writeback_accesses::writebacks 835257 # number of Writeback accesses(hits+misses) 99system.l2c.Writeback_accesses::total 835257 # number of Writeback accesses(hits+misses) 100system.l2c.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses) 101system.l2c.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses) 102system.l2c.ReadExReq_accesses::cpu.data 304426 # number of ReadExReq accesses(hits+misses) 103system.l2c.ReadExReq_accesses::total 304426 # number of ReadExReq accesses(hits+misses) 104system.l2c.demand_accesses::cpu.inst 929752 # number of demand (read+write) accesses 105system.l2c.demand_accesses::cpu.data 1391377 # number of demand (read+write) accesses 106system.l2c.demand_accesses::total 2321129 # number of demand (read+write) accesses 107system.l2c.overall_accesses::cpu.inst 929752 # number of overall (read+write) accesses 108system.l2c.overall_accesses::cpu.data 1391377 # number of overall (read+write) accesses 109system.l2c.overall_accesses::total 2321129 # number of overall (read+write) accesses 110system.l2c.ReadReq_miss_rate::cpu.inst 0.014293 # miss rate for ReadReq accesses 111system.l2c.ReadReq_miss_rate::cpu.data 0.250210 # miss rate for ReadReq accesses 112system.l2c.ReadReq_miss_rate::total 0.141446 # miss rate for ReadReq accesses 113system.l2c.UpgradeReq_miss_rate::cpu.data 0.764706 # miss rate for UpgradeReq accesses 114system.l2c.UpgradeReq_miss_rate::total 0.764706 # miss rate for UpgradeReq accesses 115system.l2c.ReadExReq_miss_rate::cpu.data 0.383873 # miss rate for ReadExReq accesses 116system.l2c.ReadExReq_miss_rate::total 0.383873 # miss rate for ReadExReq accesses 117system.l2c.demand_miss_rate::cpu.inst 0.014293 # miss rate for demand accesses 118system.l2c.demand_miss_rate::cpu.data 0.279455 # miss rate for demand accesses 119system.l2c.demand_miss_rate::total 0.173242 # miss rate for demand accesses 120system.l2c.overall_miss_rate::cpu.inst 0.014293 # miss rate for overall accesses 121system.l2c.overall_miss_rate::cpu.data 0.279455 # miss rate for overall accesses 122system.l2c.overall_miss_rate::total 0.173242 # miss rate for overall accesses 123system.l2c.ReadReq_avg_miss_latency::cpu.inst 52013.319287 # average ReadReq miss latency 124system.l2c.ReadReq_avg_miss_latency::cpu.data 52019.778208 # average ReadReq miss latency 125system.l2c.ReadReq_avg_miss_latency::total 52019.477310 # average ReadReq miss latency 126system.l2c.UpgradeReq_avg_miss_latency::cpu.data 19076.923077 # average UpgradeReq miss latency 127system.l2c.UpgradeReq_avg_miss_latency::total 19076.923077 # average UpgradeReq miss latency 128system.l2c.ReadExReq_avg_miss_latency::cpu.data 52005.485149 # average ReadExReq miss latency 129system.l2c.ReadExReq_avg_miss_latency::total 52005.485149 # average ReadExReq miss latency 130system.l2c.demand_avg_miss_latency::cpu.inst 52013.319287 # average overall miss latency 131system.l2c.demand_avg_miss_latency::cpu.data 52015.482464 # average overall miss latency 132system.l2c.demand_avg_miss_latency::total 52015.410976 # average overall miss latency 133system.l2c.overall_avg_miss_latency::cpu.inst 52013.319287 # average overall miss latency 134system.l2c.overall_avg_miss_latency::cpu.data 52015.482464 # average overall miss latency 135system.l2c.overall_avg_miss_latency::total 52015.410976 # average overall miss latency 136system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 137system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 138system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 139system.l2c.blocked::no_targets 0 # number of cycles access was blocked 140system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 141system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 142system.l2c.fast_writes 0 # number of fast writes performed 143system.l2c.cache_copies 0 # number of cache copies performed 144system.l2c.writebacks::writebacks 74180 # number of writebacks 145system.l2c.writebacks::total 74180 # number of writebacks 146system.l2c.ReadReq_mshr_misses::cpu.inst 13289 # number of ReadReq MSHR misses 147system.l2c.ReadReq_mshr_misses::cpu.data 271966 # number of ReadReq MSHR misses 148system.l2c.ReadReq_mshr_misses::total 285255 # number of ReadReq MSHR misses 149system.l2c.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses 150system.l2c.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses 151system.l2c.ReadExReq_mshr_misses::cpu.data 116861 # number of ReadExReq MSHR misses 152system.l2c.ReadExReq_mshr_misses::total 116861 # number of ReadExReq MSHR misses 153system.l2c.demand_mshr_misses::cpu.inst 13289 # number of demand (read+write) MSHR misses 154system.l2c.demand_mshr_misses::cpu.data 388827 # number of demand (read+write) MSHR misses 155system.l2c.demand_mshr_misses::total 402116 # number of demand (read+write) MSHR misses 156system.l2c.overall_mshr_misses::cpu.inst 13289 # number of overall MSHR misses 157system.l2c.overall_mshr_misses::cpu.data 388827 # number of overall MSHR misses 158system.l2c.overall_mshr_misses::total 402116 # number of overall MSHR misses 159system.l2c.ReadReq_mshr_miss_latency::cpu.inst 531734000 # number of ReadReq MSHR miss cycles 160system.l2c.ReadReq_mshr_miss_latency::cpu.data 10884019000 # number of ReadReq MSHR miss cycles 161system.l2c.ReadReq_mshr_miss_latency::total 11415753000 # number of ReadReq MSHR miss cycles 162system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 560000 # number of UpgradeReq MSHR miss cycles 163system.l2c.UpgradeReq_mshr_miss_latency::total 560000 # number of UpgradeReq MSHR miss cycles 164system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4675081000 # number of ReadExReq MSHR miss cycles 165system.l2c.ReadExReq_mshr_miss_latency::total 4675081000 # number of ReadExReq MSHR miss cycles 166system.l2c.demand_mshr_miss_latency::cpu.inst 531734000 # number of demand (read+write) MSHR miss cycles 167system.l2c.demand_mshr_miss_latency::cpu.data 15559100000 # number of demand (read+write) MSHR miss cycles 168system.l2c.demand_mshr_miss_latency::total 16090834000 # number of demand (read+write) MSHR miss cycles 169system.l2c.overall_mshr_miss_latency::cpu.inst 531734000 # number of overall MSHR miss cycles 170system.l2c.overall_mshr_miss_latency::cpu.data 15559100000 # number of overall MSHR miss cycles 171system.l2c.overall_mshr_miss_latency::total 16090834000 # number of overall MSHR miss cycles 172system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 1331550000 # number of ReadReq MSHR uncacheable cycles 173system.l2c.ReadReq_mshr_uncacheable_latency::total 1331550000 # number of ReadReq MSHR uncacheable cycles 174system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1892958000 # number of WriteReq MSHR uncacheable cycles 175system.l2c.WriteReq_mshr_uncacheable_latency::total 1892958000 # number of WriteReq MSHR uncacheable cycles 176system.l2c.overall_mshr_uncacheable_latency::cpu.data 3224508000 # number of overall MSHR uncacheable cycles 177system.l2c.overall_mshr_uncacheable_latency::total 3224508000 # number of overall MSHR uncacheable cycles 178system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.014293 # mshr miss rate for ReadReq accesses 179system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.250210 # mshr miss rate for ReadReq accesses 180system.l2c.ReadReq_mshr_miss_rate::total 0.141446 # mshr miss rate for ReadReq accesses 181system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses 182system.l2c.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses 183system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.383873 # mshr miss rate for ReadExReq accesses 184system.l2c.ReadExReq_mshr_miss_rate::total 0.383873 # mshr miss rate for ReadExReq accesses 185system.l2c.demand_mshr_miss_rate::cpu.inst 0.014293 # mshr miss rate for demand accesses 186system.l2c.demand_mshr_miss_rate::cpu.data 0.279455 # mshr miss rate for demand accesses 187system.l2c.demand_mshr_miss_rate::total 0.173242 # mshr miss rate for demand accesses 188system.l2c.overall_mshr_miss_rate::cpu.inst 0.014293 # mshr miss rate for overall accesses 189system.l2c.overall_mshr_miss_rate::cpu.data 0.279455 # mshr miss rate for overall accesses 190system.l2c.overall_mshr_miss_rate::total 0.173242 # mshr miss rate for overall accesses 191system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40013.093536 # average ReadReq mshr miss latency 192system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40019.778208 # average ReadReq mshr miss latency 193system.l2c.ReadReq_avg_mshr_miss_latency::total 40019.466793 # average ReadReq mshr miss latency 194system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 43076.923077 # average UpgradeReq mshr miss latency 195system.l2c.UpgradeReq_avg_mshr_miss_latency::total 43076.923077 # average UpgradeReq mshr miss latency 196system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40005.485149 # average ReadExReq mshr miss latency 197system.l2c.ReadExReq_avg_mshr_miss_latency::total 40005.485149 # average ReadExReq mshr miss latency 198system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40013.093536 # average overall mshr miss latency 199system.l2c.demand_avg_mshr_miss_latency::cpu.data 40015.482464 # average overall mshr miss latency 200system.l2c.demand_avg_mshr_miss_latency::total 40015.403515 # average overall mshr miss latency 201system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40013.093536 # average overall mshr miss latency 202system.l2c.overall_avg_mshr_miss_latency::cpu.data 40015.482464 # average overall mshr miss latency 203system.l2c.overall_avg_mshr_miss_latency::total 40015.403515 # average overall mshr miss latency 204system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 205system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 206system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 207system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 208system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 209system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 210system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 211system.iocache.replacements 41685 # number of replacements 212system.iocache.tagsinuse 1.347775 # Cycle average of tags in use 213system.iocache.total_refs 0 # Total number of references to valid blocks. 214system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. 215system.iocache.avg_refs 0 # Average number of references to valid blocks. 216system.iocache.warmup_cycle 1754498131000 # Cycle when the warmup percentage was hit. 217system.iocache.occ_blocks::tsunami.ide 1.347775 # Average occupied blocks per requestor 218system.iocache.occ_percent::tsunami.ide 0.084236 # Average percentage of cache occupancy 219system.iocache.occ_percent::total 0.084236 # Average percentage of cache occupancy 220system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 221system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 222system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 223system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 224system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 225system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 226system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 227system.iocache.overall_misses::total 41725 # number of overall misses 228system.iocache.ReadReq_miss_latency::tsunami.ide 20672998 # number of ReadReq miss cycles 229system.iocache.ReadReq_miss_latency::total 20672998 # number of ReadReq miss cycles 230system.iocache.WriteReq_miss_latency::tsunami.ide 11448538806 # number of WriteReq miss cycles 231system.iocache.WriteReq_miss_latency::total 11448538806 # number of WriteReq miss cycles 232system.iocache.demand_miss_latency::tsunami.ide 11469211804 # number of demand (read+write) miss cycles 233system.iocache.demand_miss_latency::total 11469211804 # number of demand (read+write) miss cycles 234system.iocache.overall_miss_latency::tsunami.ide 11469211804 # number of overall miss cycles 235system.iocache.overall_miss_latency::total 11469211804 # number of overall miss cycles 236system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 237system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 238system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 239system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 240system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 241system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 242system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 243system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 244system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 245system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 246system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 247system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 248system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 249system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 250system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 251system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 252system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119497.098266 # average ReadReq miss latency 253system.iocache.ReadReq_avg_miss_latency::total 119497.098266 # average ReadReq miss latency 254system.iocache.WriteReq_avg_miss_latency::tsunami.ide 275523.171111 # average WriteReq miss latency 255system.iocache.WriteReq_avg_miss_latency::total 275523.171111 # average WriteReq miss latency 256system.iocache.demand_avg_miss_latency::tsunami.ide 274876.256537 # average overall miss latency 257system.iocache.demand_avg_miss_latency::total 274876.256537 # average overall miss latency 258system.iocache.overall_avg_miss_latency::tsunami.ide 274876.256537 # average overall miss latency 259system.iocache.overall_avg_miss_latency::total 274876.256537 # average overall miss latency 260system.iocache.blocked_cycles::no_mshrs 199147000 # number of cycles access was blocked 261system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 262system.iocache.blocked::no_mshrs 24626 # number of cycles access was blocked 263system.iocache.blocked::no_targets 0 # number of cycles access was blocked 264system.iocache.avg_blocked_cycles::no_mshrs 8086.859417 # average number of cycles each access was blocked 265system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 266system.iocache.fast_writes 0 # number of fast writes performed 267system.iocache.cache_copies 0 # number of cache copies performed 268system.iocache.writebacks::writebacks 41512 # number of writebacks 269system.iocache.writebacks::total 41512 # number of writebacks 270system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 271system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 272system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 273system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 274system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 275system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 276system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 277system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses 278system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676000 # number of ReadReq MSHR miss cycles 279system.iocache.ReadReq_mshr_miss_latency::total 11676000 # number of ReadReq MSHR miss cycles 280system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9287684000 # number of WriteReq MSHR miss cycles 281system.iocache.WriteReq_mshr_miss_latency::total 9287684000 # number of WriteReq MSHR miss cycles 282system.iocache.demand_mshr_miss_latency::tsunami.ide 9299360000 # number of demand (read+write) MSHR miss cycles 283system.iocache.demand_mshr_miss_latency::total 9299360000 # number of demand (read+write) MSHR miss cycles 284system.iocache.overall_mshr_miss_latency::tsunami.ide 9299360000 # number of overall MSHR miss cycles 285system.iocache.overall_mshr_miss_latency::total 9299360000 # number of overall MSHR miss cycles 286system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 287system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 288system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 289system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 290system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 291system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 292system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 293system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 294system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67491.329480 # average ReadReq mshr miss latency 295system.iocache.ReadReq_avg_mshr_miss_latency::total 67491.329480 # average ReadReq mshr miss latency 296system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 223519.541779 # average WriteReq mshr miss latency 297system.iocache.WriteReq_avg_mshr_miss_latency::total 223519.541779 # average WriteReq mshr miss latency 298system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 222872.618334 # average overall mshr miss latency 299system.iocache.demand_avg_mshr_miss_latency::total 222872.618334 # average overall mshr miss latency 300system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 222872.618334 # average overall mshr miss latency 301system.iocache.overall_avg_mshr_miss_latency::total 222872.618334 # average overall mshr miss latency 302system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 303system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 304system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 305system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 306system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 307system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 308system.disk0.dma_write_txs 395 # Number of DMA write transactions. 309system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 310system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 311system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 312system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 313system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 314system.disk2.dma_write_txs 1 # Number of DMA write transactions. 315system.cpu.dtb.fetch_hits 0 # ITB hits 316system.cpu.dtb.fetch_misses 0 # ITB misses 317system.cpu.dtb.fetch_acv 0 # ITB acv 318system.cpu.dtb.fetch_accesses 0 # ITB accesses 319system.cpu.dtb.read_hits 9066995 # DTB read hits 320system.cpu.dtb.read_misses 10329 # DTB read misses 321system.cpu.dtb.read_acv 210 # DTB read access violations 322system.cpu.dtb.read_accesses 728856 # DTB read accesses 323system.cpu.dtb.write_hits 6357563 # DTB write hits 324system.cpu.dtb.write_misses 1142 # DTB write misses 325system.cpu.dtb.write_acv 157 # DTB write access violations 326system.cpu.dtb.write_accesses 291931 # DTB write accesses 327system.cpu.dtb.data_hits 15424558 # DTB hits 328system.cpu.dtb.data_misses 11471 # DTB misses 329system.cpu.dtb.data_acv 367 # DTB access violations 330system.cpu.dtb.data_accesses 1020787 # DTB accesses 331system.cpu.itb.fetch_hits 4975749 # ITB hits 332system.cpu.itb.fetch_misses 5006 # ITB misses 333system.cpu.itb.fetch_acv 184 # ITB acv 334system.cpu.itb.fetch_accesses 4980755 # ITB accesses 335system.cpu.itb.read_hits 0 # DTB read hits 336system.cpu.itb.read_misses 0 # DTB read misses 337system.cpu.itb.read_acv 0 # DTB read access violations 338system.cpu.itb.read_accesses 0 # DTB read accesses 339system.cpu.itb.write_hits 0 # DTB write hits 340system.cpu.itb.write_misses 0 # DTB write misses 341system.cpu.itb.write_acv 0 # DTB write access violations 342system.cpu.itb.write_accesses 0 # DTB write accesses 343system.cpu.itb.data_hits 0 # DTB hits 344system.cpu.itb.data_misses 0 # DTB misses 345system.cpu.itb.data_acv 0 # DTB access violations 346system.cpu.itb.data_accesses 0 # DTB accesses 347system.cpu.numCycles 3841790588 # number of cpu cycles simulated 348system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 349system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 350system.cpu.committedInsts 56195754 # Number of instructions committed 351system.cpu.committedOps 56195754 # Number of ops (including micro ops) committed 352system.cpu.num_int_alu_accesses 52066962 # Number of integer alu accesses 353system.cpu.num_fp_alu_accesses 324393 # Number of float alu accesses 354system.cpu.num_func_calls 1483816 # number of times a function call or return occured 355system.cpu.num_conditional_control_insts 6469707 # number of instructions that are conditional controls 356system.cpu.num_int_insts 52066962 # number of integer instructions 357system.cpu.num_fp_insts 324393 # number of float instructions 358system.cpu.num_int_register_reads 71340235 # number of times the integer registers were read 359system.cpu.num_int_register_writes 38530699 # number of times the integer registers were written 360system.cpu.num_fp_register_reads 163609 # number of times the floating registers were read 361system.cpu.num_fp_register_writes 166486 # number of times the floating registers were written 362system.cpu.num_mem_refs 15477180 # number of memory refs 363system.cpu.num_load_insts 9103852 # Number of load instructions 364system.cpu.num_store_insts 6373328 # Number of store instructions 365system.cpu.num_idle_cycles 3586858626.998133 # Number of idle cycles 366system.cpu.num_busy_cycles 254931961.001867 # Number of busy cycles 367system.cpu.not_idle_fraction 0.066358 # Percentage of non-idle cycles 368system.cpu.idle_fraction 0.933642 # Percentage of idle cycles 369system.cpu.kern.inst.arm 0 # number of arm instructions executed 370system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed 371system.cpu.kern.inst.hwrei 212106 # number of hwrei instructions executed 372system.cpu.kern.ipl_count::0 74929 40.88% 40.88% # number of times we switched to this ipl 373system.cpu.kern.ipl_count::21 131 0.07% 40.95% # number of times we switched to this ipl 374system.cpu.kern.ipl_count::22 1936 1.06% 42.01% # number of times we switched to this ipl 375system.cpu.kern.ipl_count::31 106288 57.99% 100.00% # number of times we switched to this ipl 376system.cpu.kern.ipl_count::total 183284 # number of times we switched to this ipl 377system.cpu.kern.ipl_good::0 73562 49.31% 49.31% # number of times we switched to this ipl from a different ipl 378system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl 379system.cpu.kern.ipl_good::22 1936 1.30% 50.69% # number of times we switched to this ipl from a different ipl 380system.cpu.kern.ipl_good::31 73562 49.31% 100.00% # number of times we switched to this ipl from a different ipl 381system.cpu.kern.ipl_good::total 149191 # number of times we switched to this ipl from a different ipl 382system.cpu.kern.ipl_ticks::0 1860148981000 96.84% 96.84% # number of cycles we spent at this ipl 383system.cpu.kern.ipl_ticks::21 104328000 0.01% 96.84% # number of cycles we spent at this ipl 384system.cpu.kern.ipl_ticks::22 779009000 0.04% 96.88% # number of cycles we spent at this ipl 385system.cpu.kern.ipl_ticks::31 59862143000 3.12% 100.00% # number of cycles we spent at this ipl 386system.cpu.kern.ipl_ticks::total 1920894461000 # number of cycles we spent at this ipl 387system.cpu.kern.ipl_used::0 0.981756 # fraction of swpipl calls that actually changed the ipl 388system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 389system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 390system.cpu.kern.ipl_used::31 0.692101 # fraction of swpipl calls that actually changed the ipl 391system.cpu.kern.ipl_used::total 0.813988 # fraction of swpipl calls that actually changed the ipl 392system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 393system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 394system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 395system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 396system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 397system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 398system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 399system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed 400system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed 401system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed 402system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed 403system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed 404system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed 405system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed 406system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed 407system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed 408system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed 409system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed 410system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed 411system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed 412system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed 413system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed 414system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed 415system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed 416system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed 417system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed 418system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed 419system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 420system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 421system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 422system.cpu.kern.syscall::total 326 # number of syscalls executed 423system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 424system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 425system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 426system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 427system.cpu.kern.callpal::swpctx 4176 2.16% 2.17% # number of callpals executed 428system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed 429system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed 430system.cpu.kern.callpal::swpipl 176055 91.22% 93.41% # number of callpals executed 431system.cpu.kern.callpal::rdps 6837 3.54% 96.96% # number of callpals executed 432system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed 433system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed 434system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed 435system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed 436system.cpu.kern.callpal::rti 5161 2.67% 99.64% # number of callpals executed 437system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 438system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed 439system.cpu.kern.callpal::total 193009 # number of callpals executed 440system.cpu.kern.mode_switch::kernel 5906 # number of protection mode switches 441system.cpu.kern.mode_switch::user 1739 # number of protection mode switches 442system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches 443system.cpu.kern.mode_good::kernel 1909 444system.cpu.kern.mode_good::user 1739 445system.cpu.kern.mode_good::idle 170 446system.cpu.kern.mode_switch_good::kernel 0.323231 # fraction of useful protection mode switches 447system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 448system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches 449system.cpu.kern.mode_switch_good::total 0.391911 # fraction of useful protection mode switches 450system.cpu.kern.mode_ticks::kernel 46683787000 2.43% 2.43% # number of ticks spent at the given mode 451system.cpu.kern.mode_ticks::user 5260006000 0.27% 2.70% # number of ticks spent at the given mode 452system.cpu.kern.mode_ticks::idle 1868950661000 97.30% 100.00% # number of ticks spent at the given mode 453system.cpu.kern.swap_context 4177 # number of times the context was actually changed 454system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 455system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 456system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 457system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 458system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 459system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 460system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 461system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 462system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 463system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 464system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 465system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 466system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 467system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 468system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 469system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 470system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 471system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 472system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 473system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 474system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 475system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 476system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 477system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 478system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 479system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 480system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 481system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 482system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 483system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 484system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 485system.cpu.icache.replacements 929101 # number of replacements 486system.cpu.icache.tagsinuse 508.704776 # Cycle average of tags in use 487system.cpu.icache.total_refs 55277821 # Total number of references to valid blocks. 488system.cpu.icache.sampled_refs 929612 # Sample count of references to valid blocks. 489system.cpu.icache.avg_refs 59.463326 # Average number of references to valid blocks. 490system.cpu.icache.warmup_cycle 36213864000 # Cycle when the warmup percentage was hit. 491system.cpu.icache.occ_blocks::cpu.inst 508.704776 # Average occupied blocks per requestor 492system.cpu.icache.occ_percent::cpu.inst 0.993564 # Average percentage of cache occupancy 493system.cpu.icache.occ_percent::total 0.993564 # Average percentage of cache occupancy 494system.cpu.icache.ReadReq_hits::cpu.inst 55277821 # number of ReadReq hits 495system.cpu.icache.ReadReq_hits::total 55277821 # number of ReadReq hits 496system.cpu.icache.demand_hits::cpu.inst 55277821 # number of demand (read+write) hits 497system.cpu.icache.demand_hits::total 55277821 # number of demand (read+write) hits 498system.cpu.icache.overall_hits::cpu.inst 55277821 # number of overall hits 499system.cpu.icache.overall_hits::total 55277821 # number of overall hits 500system.cpu.icache.ReadReq_misses::cpu.inst 929772 # number of ReadReq misses 501system.cpu.icache.ReadReq_misses::total 929772 # number of ReadReq misses 502system.cpu.icache.demand_misses::cpu.inst 929772 # number of demand (read+write) misses 503system.cpu.icache.demand_misses::total 929772 # number of demand (read+write) misses 504system.cpu.icache.overall_misses::cpu.inst 929772 # number of overall misses 505system.cpu.icache.overall_misses::total 929772 # number of overall misses 506system.cpu.icache.ReadReq_miss_latency::cpu.inst 13856924500 # number of ReadReq miss cycles 507system.cpu.icache.ReadReq_miss_latency::total 13856924500 # number of ReadReq miss cycles 508system.cpu.icache.demand_miss_latency::cpu.inst 13856924500 # number of demand (read+write) miss cycles 509system.cpu.icache.demand_miss_latency::total 13856924500 # number of demand (read+write) miss cycles 510system.cpu.icache.overall_miss_latency::cpu.inst 13856924500 # number of overall miss cycles 511system.cpu.icache.overall_miss_latency::total 13856924500 # number of overall miss cycles 512system.cpu.icache.ReadReq_accesses::cpu.inst 56207593 # number of ReadReq accesses(hits+misses) 513system.cpu.icache.ReadReq_accesses::total 56207593 # number of ReadReq accesses(hits+misses) 514system.cpu.icache.demand_accesses::cpu.inst 56207593 # number of demand (read+write) accesses 515system.cpu.icache.demand_accesses::total 56207593 # number of demand (read+write) accesses 516system.cpu.icache.overall_accesses::cpu.inst 56207593 # number of overall (read+write) accesses 517system.cpu.icache.overall_accesses::total 56207593 # number of overall (read+write) accesses 518system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016542 # miss rate for ReadReq accesses 519system.cpu.icache.ReadReq_miss_rate::total 0.016542 # miss rate for ReadReq accesses 520system.cpu.icache.demand_miss_rate::cpu.inst 0.016542 # miss rate for demand accesses 521system.cpu.icache.demand_miss_rate::total 0.016542 # miss rate for demand accesses 522system.cpu.icache.overall_miss_rate::cpu.inst 0.016542 # miss rate for overall accesses 523system.cpu.icache.overall_miss_rate::total 0.016542 # miss rate for overall accesses 524system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14903.572596 # average ReadReq miss latency 525system.cpu.icache.ReadReq_avg_miss_latency::total 14903.572596 # average ReadReq miss latency 526system.cpu.icache.demand_avg_miss_latency::cpu.inst 14903.572596 # average overall miss latency 527system.cpu.icache.demand_avg_miss_latency::total 14903.572596 # average overall miss latency 528system.cpu.icache.overall_avg_miss_latency::cpu.inst 14903.572596 # average overall miss latency 529system.cpu.icache.overall_avg_miss_latency::total 14903.572596 # average overall miss latency 530system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 531system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 532system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 533system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 534system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 535system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 536system.cpu.icache.fast_writes 0 # number of fast writes performed 537system.cpu.icache.cache_copies 0 # number of cache copies performed 538system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929772 # number of ReadReq MSHR misses 539system.cpu.icache.ReadReq_mshr_misses::total 929772 # number of ReadReq MSHR misses 540system.cpu.icache.demand_mshr_misses::cpu.inst 929772 # number of demand (read+write) MSHR misses 541system.cpu.icache.demand_mshr_misses::total 929772 # number of demand (read+write) MSHR misses 542system.cpu.icache.overall_mshr_misses::cpu.inst 929772 # number of overall MSHR misses 543system.cpu.icache.overall_mshr_misses::total 929772 # number of overall MSHR misses 544system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11066921000 # number of ReadReq MSHR miss cycles 545system.cpu.icache.ReadReq_mshr_miss_latency::total 11066921000 # number of ReadReq MSHR miss cycles 546system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11066921000 # number of demand (read+write) MSHR miss cycles 547system.cpu.icache.demand_mshr_miss_latency::total 11066921000 # number of demand (read+write) MSHR miss cycles 548system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11066921000 # number of overall MSHR miss cycles 549system.cpu.icache.overall_mshr_miss_latency::total 11066921000 # number of overall MSHR miss cycles 550system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016542 # mshr miss rate for ReadReq accesses 551system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016542 # mshr miss rate for ReadReq accesses 552system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016542 # mshr miss rate for demand accesses 553system.cpu.icache.demand_mshr_miss_rate::total 0.016542 # mshr miss rate for demand accesses 554system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016542 # mshr miss rate for overall accesses 555system.cpu.icache.overall_mshr_miss_rate::total 0.016542 # mshr miss rate for overall accesses 556system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11902.833168 # average ReadReq mshr miss latency 557system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11902.833168 # average ReadReq mshr miss latency 558system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11902.833168 # average overall mshr miss latency 559system.cpu.icache.demand_avg_mshr_miss_latency::total 11902.833168 # average overall mshr miss latency 560system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11902.833168 # average overall mshr miss latency 561system.cpu.icache.overall_avg_mshr_miss_latency::total 11902.833168 # average overall mshr miss latency 562system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 563system.cpu.dcache.replacements 1390864 # number of replacements 564system.cpu.dcache.tagsinuse 511.979749 # Cycle average of tags in use 565system.cpu.dcache.total_refs 14052220 # Total number of references to valid blocks. 566system.cpu.dcache.sampled_refs 1391376 # Sample count of references to valid blocks. 567system.cpu.dcache.avg_refs 10.099513 # Average number of references to valid blocks. 568system.cpu.dcache.warmup_cycle 101905000 # Cycle when the warmup percentage was hit. 569system.cpu.dcache.occ_blocks::cpu.data 511.979749 # Average occupied blocks per requestor 570system.cpu.dcache.occ_percent::cpu.data 0.999960 # Average percentage of cache occupancy 571system.cpu.dcache.occ_percent::total 0.999960 # Average percentage of cache occupancy 572system.cpu.dcache.ReadReq_hits::cpu.data 7816402 # number of ReadReq hits 573system.cpu.dcache.ReadReq_hits::total 7816402 # number of ReadReq hits 574system.cpu.dcache.WriteReq_hits::cpu.data 5853491 # number of WriteReq hits 575system.cpu.dcache.WriteReq_hits::total 5853491 # number of WriteReq hits 576system.cpu.dcache.LoadLockedReq_hits::cpu.data 183030 # number of LoadLockedReq hits 577system.cpu.dcache.LoadLockedReq_hits::total 183030 # number of LoadLockedReq hits 578system.cpu.dcache.StoreCondReq_hits::cpu.data 199280 # number of StoreCondReq hits 579system.cpu.dcache.StoreCondReq_hits::total 199280 # number of StoreCondReq hits 580system.cpu.dcache.demand_hits::cpu.data 13669893 # number of demand (read+write) hits 581system.cpu.dcache.demand_hits::total 13669893 # number of demand (read+write) hits 582system.cpu.dcache.overall_hits::cpu.data 13669893 # number of overall hits 583system.cpu.dcache.overall_hits::total 13669893 # number of overall hits 584system.cpu.dcache.ReadReq_misses::cpu.data 1069678 # number of ReadReq misses 585system.cpu.dcache.ReadReq_misses::total 1069678 # number of ReadReq misses 586system.cpu.dcache.WriteReq_misses::cpu.data 304443 # number of WriteReq misses 587system.cpu.dcache.WriteReq_misses::total 304443 # number of WriteReq misses 588system.cpu.dcache.LoadLockedReq_misses::cpu.data 17273 # number of LoadLockedReq misses 589system.cpu.dcache.LoadLockedReq_misses::total 17273 # number of LoadLockedReq misses 590system.cpu.dcache.demand_misses::cpu.data 1374121 # number of demand (read+write) misses 591system.cpu.dcache.demand_misses::total 1374121 # number of demand (read+write) misses 592system.cpu.dcache.overall_misses::cpu.data 1374121 # number of overall misses 593system.cpu.dcache.overall_misses::total 1374121 # number of overall misses 594system.cpu.dcache.ReadReq_miss_latency::cpu.data 26660570000 # number of ReadReq miss cycles 595system.cpu.dcache.ReadReq_miss_latency::total 26660570000 # number of ReadReq miss cycles 596system.cpu.dcache.WriteReq_miss_latency::cpu.data 9239957000 # number of WriteReq miss cycles 597system.cpu.dcache.WriteReq_miss_latency::total 9239957000 # number of WriteReq miss cycles 598system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 247721000 # number of LoadLockedReq miss cycles 599system.cpu.dcache.LoadLockedReq_miss_latency::total 247721000 # number of LoadLockedReq miss cycles 600system.cpu.dcache.demand_miss_latency::cpu.data 35900527000 # number of demand (read+write) miss cycles 601system.cpu.dcache.demand_miss_latency::total 35900527000 # number of demand (read+write) miss cycles 602system.cpu.dcache.overall_miss_latency::cpu.data 35900527000 # number of overall miss cycles 603system.cpu.dcache.overall_miss_latency::total 35900527000 # number of overall miss cycles 604system.cpu.dcache.ReadReq_accesses::cpu.data 8886080 # number of ReadReq accesses(hits+misses) 605system.cpu.dcache.ReadReq_accesses::total 8886080 # number of ReadReq accesses(hits+misses) 606system.cpu.dcache.WriteReq_accesses::cpu.data 6157934 # number of WriteReq accesses(hits+misses) 607system.cpu.dcache.WriteReq_accesses::total 6157934 # number of WriteReq accesses(hits+misses) 608system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200303 # number of LoadLockedReq accesses(hits+misses) 609system.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses) 610system.cpu.dcache.StoreCondReq_accesses::cpu.data 199280 # number of StoreCondReq accesses(hits+misses) 611system.cpu.dcache.StoreCondReq_accesses::total 199280 # number of StoreCondReq accesses(hits+misses) 612system.cpu.dcache.demand_accesses::cpu.data 15044014 # number of demand (read+write) accesses 613system.cpu.dcache.demand_accesses::total 15044014 # number of demand (read+write) accesses 614system.cpu.dcache.overall_accesses::cpu.data 15044014 # number of overall (read+write) accesses 615system.cpu.dcache.overall_accesses::total 15044014 # number of overall (read+write) accesses 616system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120377 # miss rate for ReadReq accesses 617system.cpu.dcache.ReadReq_miss_rate::total 0.120377 # miss rate for ReadReq accesses 618system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049439 # miss rate for WriteReq accesses 619system.cpu.dcache.WriteReq_miss_rate::total 0.049439 # miss rate for WriteReq accesses 620system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086234 # miss rate for LoadLockedReq accesses 621system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086234 # miss rate for LoadLockedReq accesses 622system.cpu.dcache.demand_miss_rate::cpu.data 0.091340 # miss rate for demand accesses 623system.cpu.dcache.demand_miss_rate::total 0.091340 # miss rate for demand accesses 624system.cpu.dcache.overall_miss_rate::cpu.data 0.091340 # miss rate for overall accesses 625system.cpu.dcache.overall_miss_rate::total 0.091340 # miss rate for overall accesses 626system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24923.921030 # average ReadReq miss latency 627system.cpu.dcache.ReadReq_avg_miss_latency::total 24923.921030 # average ReadReq miss latency 628system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30350.367721 # average WriteReq miss latency 629system.cpu.dcache.WriteReq_avg_miss_latency::total 30350.367721 # average WriteReq miss latency 630system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14341.515660 # average LoadLockedReq miss latency 631system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14341.515660 # average LoadLockedReq miss latency 632system.cpu.dcache.demand_avg_miss_latency::cpu.data 26126.175934 # average overall miss latency 633system.cpu.dcache.demand_avg_miss_latency::total 26126.175934 # average overall miss latency 634system.cpu.dcache.overall_avg_miss_latency::cpu.data 26126.175934 # average overall miss latency 635system.cpu.dcache.overall_avg_miss_latency::total 26126.175934 # average overall miss latency 636system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 637system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 638system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 639system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 640system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 641system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 642system.cpu.dcache.fast_writes 0 # number of fast writes performed 643system.cpu.dcache.cache_copies 0 # number of cache copies performed 644system.cpu.dcache.writebacks::writebacks 835257 # number of writebacks 645system.cpu.dcache.writebacks::total 835257 # number of writebacks 646system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069678 # number of ReadReq MSHR misses 647system.cpu.dcache.ReadReq_mshr_misses::total 1069678 # number of ReadReq MSHR misses 648system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304443 # number of WriteReq MSHR misses 649system.cpu.dcache.WriteReq_mshr_misses::total 304443 # number of WriteReq MSHR misses 650system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17273 # number of LoadLockedReq MSHR misses 651system.cpu.dcache.LoadLockedReq_mshr_misses::total 17273 # number of LoadLockedReq MSHR misses 652system.cpu.dcache.demand_mshr_misses::cpu.data 1374121 # number of demand (read+write) MSHR misses 653system.cpu.dcache.demand_mshr_misses::total 1374121 # number of demand (read+write) MSHR misses 654system.cpu.dcache.overall_mshr_misses::cpu.data 1374121 # number of overall MSHR misses 655system.cpu.dcache.overall_mshr_misses::total 1374121 # number of overall MSHR misses 656system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23451491000 # number of ReadReq MSHR miss cycles 657system.cpu.dcache.ReadReq_mshr_miss_latency::total 23451491000 # number of ReadReq MSHR miss cycles 658system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8326628000 # number of WriteReq MSHR miss cycles 659system.cpu.dcache.WriteReq_mshr_miss_latency::total 8326628000 # number of WriteReq MSHR miss cycles 660system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 195902000 # number of LoadLockedReq MSHR miss cycles 661system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 195902000 # number of LoadLockedReq MSHR miss cycles 662system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31778119000 # number of demand (read+write) MSHR miss cycles 663system.cpu.dcache.demand_mshr_miss_latency::total 31778119000 # number of demand (read+write) MSHR miss cycles 664system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31778119000 # number of overall MSHR miss cycles 665system.cpu.dcache.overall_mshr_miss_latency::total 31778119000 # number of overall MSHR miss cycles 666system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1421708000 # number of ReadReq MSHR uncacheable cycles 667system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1421708000 # number of ReadReq MSHR uncacheable cycles 668system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2010806000 # number of WriteReq MSHR uncacheable cycles 669system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2010806000 # number of WriteReq MSHR uncacheable cycles 670system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3432514000 # number of overall MSHR uncacheable cycles 671system.cpu.dcache.overall_mshr_uncacheable_latency::total 3432514000 # number of overall MSHR uncacheable cycles 672system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120377 # mshr miss rate for ReadReq accesses 673system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120377 # mshr miss rate for ReadReq accesses 674system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049439 # mshr miss rate for WriteReq accesses 675system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049439 # mshr miss rate for WriteReq accesses 676system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086234 # mshr miss rate for LoadLockedReq accesses 677system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086234 # mshr miss rate for LoadLockedReq accesses 678system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091340 # mshr miss rate for demand accesses 679system.cpu.dcache.demand_mshr_miss_rate::total 0.091340 # mshr miss rate for demand accesses 680system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091340 # mshr miss rate for overall accesses 681system.cpu.dcache.overall_mshr_miss_rate::total 0.091340 # mshr miss rate for overall accesses 682system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21923.878962 # average ReadReq mshr miss latency 683system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21923.878962 # average ReadReq mshr miss latency 684system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27350.367721 # average WriteReq mshr miss latency 685system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27350.367721 # average WriteReq mshr miss latency 686system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11341.515660 # average LoadLockedReq mshr miss latency 687system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11341.515660 # average LoadLockedReq mshr miss latency 688system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23126.143185 # average overall mshr miss latency 689system.cpu.dcache.demand_avg_mshr_miss_latency::total 23126.143185 # average overall mshr miss latency 690system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23126.143185 # average overall mshr miss latency 691system.cpu.dcache.overall_avg_mshr_miss_latency::total 23126.143185 # average overall mshr miss latency 692system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 693system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 694system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 695system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 696system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 697system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 698system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 699 700---------- End Simulation Statistics ---------- 701