stats.txt revision 8802:ef66a9083bc4
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.915549 # Number of seconds simulated 4sim_ticks 1915548867000 # Number of ticks simulated 5final_tick 1915548867000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1659827 # Simulator instruction rate (inst/s) 8host_tick_rate 56637748152 # Simulator tick rate (ticks/s) 9host_mem_usage 290988 # Number of bytes of host memory used 10host_seconds 33.82 # Real time elapsed on the host 11sim_insts 56137087 # Number of instructions simulated 12system.physmem.bytes_read 29663360 # Number of bytes read from this memory 13system.physmem.bytes_inst_read 943040 # Number of instructions bytes read from this memory 14system.physmem.bytes_written 10122368 # Number of bytes written to this memory 15system.physmem.num_reads 463490 # Number of read requests responded to by this memory 16system.physmem.num_writes 158162 # Number of write requests responded to by this memory 17system.physmem.num_other 0 # Number of other requests responded to by this memory 18system.physmem.bw_read 15485567 # Total read bandwidth from this memory (bytes/s) 19system.physmem.bw_inst_read 492308 # Instruction read bandwidth from this memory (bytes/s) 20system.physmem.bw_write 5284317 # Write bandwidth from this memory (bytes/s) 21system.physmem.bw_total 20769884 # Total bandwidth to/from this memory (bytes/s) 22system.l2c.replacements 389289 # number of replacements 23system.l2c.tagsinuse 34352.038344 # Cycle average of tags in use 24system.l2c.total_refs 2311163 # Total number of references to valid blocks. 25system.l2c.sampled_refs 421794 # Sample count of references to valid blocks. 26system.l2c.avg_refs 5.479364 # Average number of references to valid blocks. 27system.l2c.warmup_cycle 6937912000 # Cycle when the warmup percentage was hit. 28system.l2c.occ_blocks::0 11241.373247 # Average occupied blocks per context 29system.l2c.occ_blocks::1 23110.665097 # Average occupied blocks per context 30system.l2c.occ_percent::0 0.171530 # Average percentage of cache occupancy 31system.l2c.occ_percent::1 0.352641 # Average percentage of cache occupancy 32system.l2c.ReadReq_hits::0 1710461 # number of ReadReq hits 33system.l2c.ReadReq_hits::total 1710461 # number of ReadReq hits 34system.l2c.Writeback_hits::0 826671 # number of Writeback hits 35system.l2c.Writeback_hits::total 826671 # number of Writeback hits 36system.l2c.UpgradeReq_hits::0 6 # number of UpgradeReq hits 37system.l2c.UpgradeReq_hits::total 6 # number of UpgradeReq hits 38system.l2c.ReadExReq_hits::0 185878 # number of ReadExReq hits 39system.l2c.ReadExReq_hits::total 185878 # number of ReadExReq hits 40system.l2c.demand_hits::0 1896339 # number of demand (read+write) hits 41system.l2c.demand_hits::1 0 # number of demand (read+write) hits 42system.l2c.demand_hits::total 1896339 # number of demand (read+write) hits 43system.l2c.overall_hits::0 1896339 # number of overall hits 44system.l2c.overall_hits::1 0 # number of overall hits 45system.l2c.overall_hits::total 1896339 # number of overall hits 46system.l2c.ReadReq_misses::0 304138 # number of ReadReq misses 47system.l2c.ReadReq_misses::total 304138 # number of ReadReq misses 48system.l2c.UpgradeReq_misses::0 7 # number of UpgradeReq misses 49system.l2c.UpgradeReq_misses::total 7 # number of UpgradeReq misses 50system.l2c.ReadExReq_misses::0 118294 # number of ReadExReq misses 51system.l2c.ReadExReq_misses::total 118294 # number of ReadExReq misses 52system.l2c.demand_misses::0 422432 # number of demand (read+write) misses 53system.l2c.demand_misses::1 0 # number of demand (read+write) misses 54system.l2c.demand_misses::total 422432 # number of demand (read+write) misses 55system.l2c.overall_misses::0 422432 # number of overall misses 56system.l2c.overall_misses::1 0 # number of overall misses 57system.l2c.overall_misses::total 422432 # number of overall misses 58system.l2c.ReadReq_miss_latency 15820206500 # number of ReadReq miss cycles 59system.l2c.UpgradeReq_miss_latency 248000 # number of UpgradeReq miss cycles 60system.l2c.ReadExReq_miss_latency 6151753000 # number of ReadExReq miss cycles 61system.l2c.demand_miss_latency 21971959500 # number of demand (read+write) miss cycles 62system.l2c.overall_miss_latency 21971959500 # number of overall miss cycles 63system.l2c.ReadReq_accesses::0 2014599 # number of ReadReq accesses(hits+misses) 64system.l2c.ReadReq_accesses::total 2014599 # number of ReadReq accesses(hits+misses) 65system.l2c.Writeback_accesses::0 826671 # number of Writeback accesses(hits+misses) 66system.l2c.Writeback_accesses::total 826671 # number of Writeback accesses(hits+misses) 67system.l2c.UpgradeReq_accesses::0 13 # number of UpgradeReq accesses(hits+misses) 68system.l2c.UpgradeReq_accesses::total 13 # number of UpgradeReq accesses(hits+misses) 69system.l2c.ReadExReq_accesses::0 304172 # number of ReadExReq accesses(hits+misses) 70system.l2c.ReadExReq_accesses::total 304172 # number of ReadExReq accesses(hits+misses) 71system.l2c.demand_accesses::0 2318771 # number of demand (read+write) accesses 72system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses 73system.l2c.demand_accesses::total 2318771 # number of demand (read+write) accesses 74system.l2c.overall_accesses::0 2318771 # number of overall (read+write) accesses 75system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses 76system.l2c.overall_accesses::total 2318771 # number of overall (read+write) accesses 77system.l2c.ReadReq_miss_rate::0 0.150967 # miss rate for ReadReq accesses 78system.l2c.UpgradeReq_miss_rate::0 0.538462 # miss rate for UpgradeReq accesses 79system.l2c.ReadExReq_miss_rate::0 0.388905 # miss rate for ReadExReq accesses 80system.l2c.demand_miss_rate::0 0.182179 # miss rate for demand accesses 81system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses 82system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses 83system.l2c.overall_miss_rate::0 0.182179 # miss rate for overall accesses 84system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses 85system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses 86system.l2c.ReadReq_avg_miss_latency::0 52016.540189 # average ReadReq miss latency 87system.l2c.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency 88system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency 89system.l2c.UpgradeReq_avg_miss_latency::0 35428.571429 # average UpgradeReq miss latency 90system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency 91system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency 92system.l2c.ReadExReq_avg_miss_latency::0 52003.930884 # average ReadExReq miss latency 93system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency 94system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency 95system.l2c.demand_avg_miss_latency::0 52013.009194 # average overall miss latency 96system.l2c.demand_avg_miss_latency::1 inf # average overall miss latency 97system.l2c.demand_avg_miss_latency::total inf # average overall miss latency 98system.l2c.overall_avg_miss_latency::0 52013.009194 # average overall miss latency 99system.l2c.overall_avg_miss_latency::1 inf # average overall miss latency 100system.l2c.overall_avg_miss_latency::total inf # average overall miss latency 101system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 102system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 103system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 104system.l2c.blocked::no_targets 0 # number of cycles access was blocked 105system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 106system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 107system.l2c.fast_writes 0 # number of fast writes performed 108system.l2c.cache_copies 0 # number of cache copies performed 109system.l2c.writebacks 116650 # number of writebacks 110system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 111system.l2c.overall_mshr_hits 0 # number of overall MSHR hits 112system.l2c.ReadReq_mshr_misses 304138 # number of ReadReq MSHR misses 113system.l2c.UpgradeReq_mshr_misses 7 # number of UpgradeReq MSHR misses 114system.l2c.ReadExReq_mshr_misses 118294 # number of ReadExReq MSHR misses 115system.l2c.demand_mshr_misses 422432 # number of demand (read+write) MSHR misses 116system.l2c.overall_mshr_misses 422432 # number of overall MSHR misses 117system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 118system.l2c.ReadReq_mshr_miss_latency 12170545000 # number of ReadReq MSHR miss cycles 119system.l2c.UpgradeReq_mshr_miss_latency 320000 # number of UpgradeReq MSHR miss cycles 120system.l2c.ReadExReq_mshr_miss_latency 4732225000 # number of ReadExReq MSHR miss cycles 121system.l2c.demand_mshr_miss_latency 16902770000 # number of demand (read+write) MSHR miss cycles 122system.l2c.overall_mshr_miss_latency 16902770000 # number of overall MSHR miss cycles 123system.l2c.ReadReq_mshr_uncacheable_latency 772673000 # number of ReadReq MSHR uncacheable cycles 124system.l2c.WriteReq_mshr_uncacheable_latency 1083819500 # number of WriteReq MSHR uncacheable cycles 125system.l2c.overall_mshr_uncacheable_latency 1856492500 # number of overall MSHR uncacheable cycles 126system.l2c.ReadReq_mshr_miss_rate::0 0.150967 # mshr miss rate for ReadReq accesses 127system.l2c.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses 128system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses 129system.l2c.UpgradeReq_mshr_miss_rate::0 0.538462 # mshr miss rate for UpgradeReq accesses 130system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses 131system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses 132system.l2c.ReadExReq_mshr_miss_rate::0 0.388905 # mshr miss rate for ReadExReq accesses 133system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses 134system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses 135system.l2c.demand_mshr_miss_rate::0 0.182179 # mshr miss rate for demand accesses 136system.l2c.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses 137system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses 138system.l2c.overall_mshr_miss_rate::0 0.182179 # mshr miss rate for overall accesses 139system.l2c.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses 140system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses 141system.l2c.ReadReq_avg_mshr_miss_latency 40016.522105 # average ReadReq mshr miss latency 142system.l2c.UpgradeReq_avg_mshr_miss_latency 45714.285714 # average UpgradeReq mshr miss latency 143system.l2c.ReadExReq_avg_mshr_miss_latency 40003.930884 # average ReadExReq mshr miss latency 144system.l2c.demand_avg_mshr_miss_latency 40012.996175 # average overall mshr miss latency 145system.l2c.overall_avg_mshr_miss_latency 40012.996175 # average overall mshr miss latency 146system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency 147system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency 148system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency 149system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated 150system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 151system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 152system.iocache.replacements 41685 # number of replacements 153system.iocache.tagsinuse 1.340325 # Cycle average of tags in use 154system.iocache.total_refs 0 # Total number of references to valid blocks. 155system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. 156system.iocache.avg_refs 0 # Average number of references to valid blocks. 157system.iocache.warmup_cycle 1750545944000 # Cycle when the warmup percentage was hit. 158system.iocache.occ_blocks::1 1.340325 # Average occupied blocks per context 159system.iocache.occ_percent::1 0.083770 # Average percentage of cache occupancy 160system.iocache.demand_hits::0 0 # number of demand (read+write) hits 161system.iocache.demand_hits::1 0 # number of demand (read+write) hits 162system.iocache.demand_hits::total 0 # number of demand (read+write) hits 163system.iocache.overall_hits::0 0 # number of overall hits 164system.iocache.overall_hits::1 0 # number of overall hits 165system.iocache.overall_hits::total 0 # number of overall hits 166system.iocache.ReadReq_misses::1 173 # number of ReadReq misses 167system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 168system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses 169system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 170system.iocache.demand_misses::0 0 # number of demand (read+write) misses 171system.iocache.demand_misses::1 41725 # number of demand (read+write) misses 172system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 173system.iocache.overall_misses::0 0 # number of overall misses 174system.iocache.overall_misses::1 41725 # number of overall misses 175system.iocache.overall_misses::total 41725 # number of overall misses 176system.iocache.ReadReq_miss_latency 19940998 # number of ReadReq miss cycles 177system.iocache.WriteReq_miss_latency 5722300806 # number of WriteReq miss cycles 178system.iocache.demand_miss_latency 5742241804 # number of demand (read+write) miss cycles 179system.iocache.overall_miss_latency 5742241804 # number of overall miss cycles 180system.iocache.ReadReq_accesses::1 173 # number of ReadReq accesses(hits+misses) 181system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 182system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) 183system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 184system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses 185system.iocache.demand_accesses::1 41725 # number of demand (read+write) accesses 186system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 187system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses 188system.iocache.overall_accesses::1 41725 # number of overall (read+write) accesses 189system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 190system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses 191system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses 192system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses 193system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses 194system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses 195system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses 196system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses 197system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses 198system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency 199system.iocache.ReadReq_avg_miss_latency::1 115265.884393 # average ReadReq miss latency 200system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency 201system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency 202system.iocache.WriteReq_avg_miss_latency::1 137714.208847 # average WriteReq miss latency 203system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency 204system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency 205system.iocache.demand_avg_miss_latency::1 137621.133709 # average overall miss latency 206system.iocache.demand_avg_miss_latency::total inf # average overall miss latency 207system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency 208system.iocache.overall_avg_miss_latency::1 137621.133709 # average overall miss latency 209system.iocache.overall_avg_miss_latency::total inf # average overall miss latency 210system.iocache.blocked_cycles::no_mshrs 64604060 # number of cycles access was blocked 211system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 212system.iocache.blocked::no_mshrs 10476 # number of cycles access was blocked 213system.iocache.blocked::no_targets 0 # number of cycles access was blocked 214system.iocache.avg_blocked_cycles::no_mshrs 6166.863307 # average number of cycles each access was blocked 215system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 216system.iocache.fast_writes 0 # number of fast writes performed 217system.iocache.cache_copies 0 # number of cache copies performed 218system.iocache.writebacks 41512 # number of writebacks 219system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 220system.iocache.overall_mshr_hits 0 # number of overall MSHR hits 221system.iocache.ReadReq_mshr_misses 173 # number of ReadReq MSHR misses 222system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses 223system.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses 224system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses 225system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 226system.iocache.ReadReq_mshr_miss_latency 10944998 # number of ReadReq MSHR miss cycles 227system.iocache.WriteReq_mshr_miss_latency 3561447990 # number of WriteReq MSHR miss cycles 228system.iocache.demand_mshr_miss_latency 3572392988 # number of demand (read+write) MSHR miss cycles 229system.iocache.overall_mshr_miss_latency 3572392988 # number of overall MSHR miss cycles 230system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 231system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses 232system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses 233system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses 234system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses 235system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses 236system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses 237system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses 238system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses 239system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses 240system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses 241system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses 242system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses 243system.iocache.ReadReq_avg_mshr_miss_latency 63265.884393 # average ReadReq mshr miss latency 244system.iocache.WriteReq_avg_mshr_miss_latency 85710.627407 # average WriteReq mshr miss latency 245system.iocache.demand_avg_mshr_miss_latency 85617.567118 # average overall mshr miss latency 246system.iocache.overall_avg_mshr_miss_latency 85617.567118 # average overall mshr miss latency 247system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 248system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated 249system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 250system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 251system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 252system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 253system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 254system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 255system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 256system.disk0.dma_write_txs 395 # Number of DMA write transactions. 257system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 258system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 259system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 260system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 261system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 262system.disk2.dma_write_txs 1 # Number of DMA write transactions. 263system.cpu.dtb.fetch_hits 0 # ITB hits 264system.cpu.dtb.fetch_misses 0 # ITB misses 265system.cpu.dtb.fetch_acv 0 # ITB acv 266system.cpu.dtb.fetch_accesses 0 # ITB accesses 267system.cpu.dtb.read_hits 9057511 # DTB read hits 268system.cpu.dtb.read_misses 10312 # DTB read misses 269system.cpu.dtb.read_acv 210 # DTB read access violations 270system.cpu.dtb.read_accesses 728817 # DTB read accesses 271system.cpu.dtb.write_hits 6352446 # DTB write hits 272system.cpu.dtb.write_misses 1140 # DTB write misses 273system.cpu.dtb.write_acv 157 # DTB write access violations 274system.cpu.dtb.write_accesses 291929 # DTB write accesses 275system.cpu.dtb.data_hits 15409957 # DTB hits 276system.cpu.dtb.data_misses 11452 # DTB misses 277system.cpu.dtb.data_acv 367 # DTB access violations 278system.cpu.dtb.data_accesses 1020746 # DTB accesses 279system.cpu.itb.fetch_hits 4973520 # ITB hits 280system.cpu.itb.fetch_misses 4997 # ITB misses 281system.cpu.itb.fetch_acv 184 # ITB acv 282system.cpu.itb.fetch_accesses 4978517 # ITB accesses 283system.cpu.itb.read_hits 0 # DTB read hits 284system.cpu.itb.read_misses 0 # DTB read misses 285system.cpu.itb.read_acv 0 # DTB read access violations 286system.cpu.itb.read_accesses 0 # DTB read accesses 287system.cpu.itb.write_hits 0 # DTB write hits 288system.cpu.itb.write_misses 0 # DTB write misses 289system.cpu.itb.write_acv 0 # DTB write access violations 290system.cpu.itb.write_accesses 0 # DTB write accesses 291system.cpu.itb.data_hits 0 # DTB hits 292system.cpu.itb.data_misses 0 # DTB misses 293system.cpu.itb.data_acv 0 # DTB access violations 294system.cpu.itb.data_accesses 0 # DTB accesses 295system.cpu.numCycles 3831097734 # number of cpu cycles simulated 296system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 297system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 298system.cpu.num_insts 56137087 # Number of instructions executed 299system.cpu.num_int_alu_accesses 52011214 # Number of integer alu accesses 300system.cpu.num_fp_alu_accesses 324192 # Number of float alu accesses 301system.cpu.num_func_calls 1482242 # number of times a function call or return occured 302system.cpu.num_conditional_control_insts 6464616 # number of instructions that are conditional controls 303system.cpu.num_int_insts 52011214 # number of integer instructions 304system.cpu.num_fp_insts 324192 # number of float instructions 305system.cpu.num_int_register_reads 71259077 # number of times the integer registers were read 306system.cpu.num_int_register_writes 38485860 # number of times the integer registers were written 307system.cpu.num_fp_register_reads 163510 # number of times the floating registers were read 308system.cpu.num_fp_register_writes 166384 # number of times the floating registers were written 309system.cpu.num_mem_refs 15462519 # number of memory refs 310system.cpu.num_load_insts 9094324 # Number of load instructions 311system.cpu.num_store_insts 6368195 # Number of store instructions 312system.cpu.num_idle_cycles 3587943187.998127 # Number of idle cycles 313system.cpu.num_busy_cycles 243154546.001873 # Number of busy cycles 314system.cpu.not_idle_fraction 0.063469 # Percentage of non-idle cycles 315system.cpu.idle_fraction 0.936531 # Percentage of idle cycles 316system.cpu.kern.inst.arm 0 # number of arm instructions executed 317system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed 318system.cpu.kern.inst.hwrei 211932 # number of hwrei instructions executed 319system.cpu.kern.ipl_count::0 74887 40.89% 40.89% # number of times we switched to this ipl 320system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl 321system.cpu.kern.ipl_count::22 1931 1.05% 42.02% # number of times we switched to this ipl 322system.cpu.kern.ipl_count::31 106197 57.98% 100.00% # number of times we switched to this ipl 323system.cpu.kern.ipl_count::total 183146 # number of times we switched to this ipl 324system.cpu.kern.ipl_good::0 73520 49.31% 49.31% # number of times we switched to this ipl from a different ipl 325system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl 326system.cpu.kern.ipl_good::22 1931 1.30% 50.69% # number of times we switched to this ipl from a different ipl 327system.cpu.kern.ipl_good::31 73520 49.31% 100.00% # number of times we switched to this ipl from a different ipl 328system.cpu.kern.ipl_good::total 149102 # number of times we switched to this ipl from a different ipl 329system.cpu.kern.ipl_ticks::0 1857816228500 96.99% 96.99% # number of cycles we spent at this ipl 330system.cpu.kern.ipl_ticks::21 79988500 0.00% 96.99% # number of cycles we spent at this ipl 331system.cpu.kern.ipl_ticks::22 554693000 0.03% 97.02% # number of cycles we spent at this ipl 332system.cpu.kern.ipl_ticks::31 57097199000 2.98% 100.00% # number of cycles we spent at this ipl 333system.cpu.kern.ipl_ticks::total 1915548109000 # number of cycles we spent at this ipl 334system.cpu.kern.ipl_used::0 0.981746 # fraction of swpipl calls that actually changed the ipl 335system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 336system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 337system.cpu.kern.ipl_used::31 0.692298 # fraction of swpipl calls that actually changed the ipl 338system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 339system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 340system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 341system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 342system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 343system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 344system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 345system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed 346system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed 347system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed 348system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed 349system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed 350system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed 351system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed 352system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed 353system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed 354system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed 355system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed 356system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed 357system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed 358system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed 359system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed 360system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed 361system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed 362system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed 363system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed 364system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed 365system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 366system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 367system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 368system.cpu.kern.syscall::total 326 # number of syscalls executed 369system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 370system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 371system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 372system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 373system.cpu.kern.callpal::swpctx 4173 2.16% 2.17% # number of callpals executed 374system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed 375system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed 376system.cpu.kern.callpal::swpipl 175927 91.22% 93.41% # number of callpals executed 377system.cpu.kern.callpal::rdps 6832 3.54% 96.96% # number of callpals executed 378system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed 379system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed 380system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed 381system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed 382system.cpu.kern.callpal::rti 5156 2.67% 99.64% # number of callpals executed 383system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 384system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed 385system.cpu.kern.callpal::total 192868 # number of callpals executed 386system.cpu.kern.mode_switch::kernel 5903 # number of protection mode switches 387system.cpu.kern.mode_switch::user 1738 # number of protection mode switches 388system.cpu.kern.mode_switch::idle 2092 # number of protection mode switches 389system.cpu.kern.mode_good::kernel 1906 390system.cpu.kern.mode_good::user 1738 391system.cpu.kern.mode_good::idle 168 392system.cpu.kern.mode_switch_good::kernel 0.322887 # fraction of useful protection mode switches 393system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 394system.cpu.kern.mode_switch_good::idle 0.080306 # fraction of useful protection mode switches 395system.cpu.kern.mode_switch_good::total 1.403193 # fraction of useful protection mode switches 396system.cpu.kern.mode_ticks::kernel 45253274000 2.36% 2.36% # number of ticks spent at the given mode 397system.cpu.kern.mode_ticks::user 5124228000 0.27% 2.63% # number of ticks spent at the given mode 398system.cpu.kern.mode_ticks::idle 1865170605000 97.37% 100.00% # number of ticks spent at the given mode 399system.cpu.kern.swap_context 4174 # number of times the context was actually changed 400system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 401system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 402system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 403system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 404system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 405system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post 406system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 407system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 408system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post 409system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 410system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 411system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post 412system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 413system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 414system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post 415system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 416system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 417system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post 418system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 419system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 420system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post 421system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 422system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 423system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post 424system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 425system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 426system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post 427system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 428system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post 429system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 430system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 431system.cpu.icache.replacements 927683 # number of replacements 432system.cpu.icache.tagsinuse 508.721464 # Cycle average of tags in use 433system.cpu.icache.total_refs 55220553 # Total number of references to valid blocks. 434system.cpu.icache.sampled_refs 928194 # Sample count of references to valid blocks. 435system.cpu.icache.avg_refs 59.492469 # Average number of references to valid blocks. 436system.cpu.icache.warmup_cycle 36307428000 # Cycle when the warmup percentage was hit. 437system.cpu.icache.occ_blocks::0 508.721464 # Average occupied blocks per context 438system.cpu.icache.occ_percent::0 0.993597 # Average percentage of cache occupancy 439system.cpu.icache.ReadReq_hits::0 55220553 # number of ReadReq hits 440system.cpu.icache.ReadReq_hits::total 55220553 # number of ReadReq hits 441system.cpu.icache.demand_hits::0 55220553 # number of demand (read+write) hits 442system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits 443system.cpu.icache.demand_hits::total 55220553 # number of demand (read+write) hits 444system.cpu.icache.overall_hits::0 55220553 # number of overall hits 445system.cpu.icache.overall_hits::1 0 # number of overall hits 446system.cpu.icache.overall_hits::total 55220553 # number of overall hits 447system.cpu.icache.ReadReq_misses::0 928354 # number of ReadReq misses 448system.cpu.icache.ReadReq_misses::total 928354 # number of ReadReq misses 449system.cpu.icache.demand_misses::0 928354 # number of demand (read+write) misses 450system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses 451system.cpu.icache.demand_misses::total 928354 # number of demand (read+write) misses 452system.cpu.icache.overall_misses::0 928354 # number of overall misses 453system.cpu.icache.overall_misses::1 0 # number of overall misses 454system.cpu.icache.overall_misses::total 928354 # number of overall misses 455system.cpu.icache.ReadReq_miss_latency 13616370500 # number of ReadReq miss cycles 456system.cpu.icache.demand_miss_latency 13616370500 # number of demand (read+write) miss cycles 457system.cpu.icache.overall_miss_latency 13616370500 # number of overall miss cycles 458system.cpu.icache.ReadReq_accesses::0 56148907 # number of ReadReq accesses(hits+misses) 459system.cpu.icache.ReadReq_accesses::total 56148907 # number of ReadReq accesses(hits+misses) 460system.cpu.icache.demand_accesses::0 56148907 # number of demand (read+write) accesses 461system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses 462system.cpu.icache.demand_accesses::total 56148907 # number of demand (read+write) accesses 463system.cpu.icache.overall_accesses::0 56148907 # number of overall (read+write) accesses 464system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses 465system.cpu.icache.overall_accesses::total 56148907 # number of overall (read+write) accesses 466system.cpu.icache.ReadReq_miss_rate::0 0.016534 # miss rate for ReadReq accesses 467system.cpu.icache.demand_miss_rate::0 0.016534 # miss rate for demand accesses 468system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses 469system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses 470system.cpu.icache.overall_miss_rate::0 0.016534 # miss rate for overall accesses 471system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses 472system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses 473system.cpu.icache.ReadReq_avg_miss_latency::0 14667.218001 # average ReadReq miss latency 474system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency 475system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency 476system.cpu.icache.demand_avg_miss_latency::0 14667.218001 # average overall miss latency 477system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency 478system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency 479system.cpu.icache.overall_avg_miss_latency::0 14667.218001 # average overall miss latency 480system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency 481system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency 482system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 483system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 484system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 485system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 486system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 487system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 488system.cpu.icache.fast_writes 0 # number of fast writes performed 489system.cpu.icache.cache_copies 0 # number of cache copies performed 490system.cpu.icache.writebacks 85 # number of writebacks 491system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 492system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits 493system.cpu.icache.ReadReq_mshr_misses 928354 # number of ReadReq MSHR misses 494system.cpu.icache.demand_mshr_misses 928354 # number of demand (read+write) MSHR misses 495system.cpu.icache.overall_mshr_misses 928354 # number of overall MSHR misses 496system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 497system.cpu.icache.ReadReq_mshr_miss_latency 10830625500 # number of ReadReq MSHR miss cycles 498system.cpu.icache.demand_mshr_miss_latency 10830625500 # number of demand (read+write) MSHR miss cycles 499system.cpu.icache.overall_mshr_miss_latency 10830625500 # number of overall MSHR miss cycles 500system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 501system.cpu.icache.ReadReq_mshr_miss_rate::0 0.016534 # mshr miss rate for ReadReq accesses 502system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses 503system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses 504system.cpu.icache.demand_mshr_miss_rate::0 0.016534 # mshr miss rate for demand accesses 505system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses 506system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses 507system.cpu.icache.overall_mshr_miss_rate::0 0.016534 # mshr miss rate for overall accesses 508system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses 509system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses 510system.cpu.icache.ReadReq_avg_mshr_miss_latency 11666.482290 # average ReadReq mshr miss latency 511system.cpu.icache.demand_avg_mshr_miss_latency 11666.482290 # average overall mshr miss latency 512system.cpu.icache.overall_avg_mshr_miss_latency 11666.482290 # average overall mshr miss latency 513system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 514system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated 515system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 516system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 517system.cpu.dcache.replacements 1390115 # number of replacements 518system.cpu.dcache.tagsinuse 511.984023 # Cycle average of tags in use 519system.cpu.dcache.total_refs 14038335 # Total number of references to valid blocks. 520system.cpu.dcache.sampled_refs 1390627 # Sample count of references to valid blocks. 521system.cpu.dcache.avg_refs 10.094968 # Average number of references to valid blocks. 522system.cpu.dcache.warmup_cycle 84029000 # Cycle when the warmup percentage was hit. 523system.cpu.dcache.occ_blocks::0 511.984023 # Average occupied blocks per context 524system.cpu.dcache.occ_percent::0 0.999969 # Average percentage of cache occupancy 525system.cpu.dcache.ReadReq_hits::0 7807536 # number of ReadReq hits 526system.cpu.dcache.ReadReq_hits::total 7807536 # number of ReadReq hits 527system.cpu.dcache.WriteReq_hits::0 5848554 # number of WriteReq hits 528system.cpu.dcache.WriteReq_hits::total 5848554 # number of WriteReq hits 529system.cpu.dcache.LoadLockedReq_hits::0 183025 # number of LoadLockedReq hits 530system.cpu.dcache.LoadLockedReq_hits::total 183025 # number of LoadLockedReq hits 531system.cpu.dcache.StoreCondReq_hits::0 199203 # number of StoreCondReq hits 532system.cpu.dcache.StoreCondReq_hits::total 199203 # number of StoreCondReq hits 533system.cpu.dcache.demand_hits::0 13656090 # number of demand (read+write) hits 534system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits 535system.cpu.dcache.demand_hits::total 13656090 # number of demand (read+write) hits 536system.cpu.dcache.overall_hits::0 13656090 # number of overall hits 537system.cpu.dcache.overall_hits::1 0 # number of overall hits 538system.cpu.dcache.overall_hits::total 13656090 # number of overall hits 539system.cpu.dcache.ReadReq_misses::0 1069110 # number of ReadReq misses 540system.cpu.dcache.ReadReq_misses::total 1069110 # number of ReadReq misses 541system.cpu.dcache.WriteReq_misses::0 304335 # number of WriteReq misses 542system.cpu.dcache.WriteReq_misses::total 304335 # number of WriteReq misses 543system.cpu.dcache.LoadLockedReq_misses::0 17201 # number of LoadLockedReq misses 544system.cpu.dcache.LoadLockedReq_misses::total 17201 # number of LoadLockedReq misses 545system.cpu.dcache.demand_misses::0 1373445 # number of demand (read+write) misses 546system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses 547system.cpu.dcache.demand_misses::total 1373445 # number of demand (read+write) misses 548system.cpu.dcache.overall_misses::0 1373445 # number of overall misses 549system.cpu.dcache.overall_misses::1 0 # number of overall misses 550system.cpu.dcache.overall_misses::total 1373445 # number of overall misses 551system.cpu.dcache.ReadReq_miss_latency 27121920500 # number of ReadReq miss cycles 552system.cpu.dcache.WriteReq_miss_latency 9228484000 # number of WriteReq miss cycles 553system.cpu.dcache.LoadLockedReq_miss_latency 245980000 # number of LoadLockedReq miss cycles 554system.cpu.dcache.demand_miss_latency 36350404500 # number of demand (read+write) miss cycles 555system.cpu.dcache.overall_miss_latency 36350404500 # number of overall miss cycles 556system.cpu.dcache.ReadReq_accesses::0 8876646 # number of ReadReq accesses(hits+misses) 557system.cpu.dcache.ReadReq_accesses::total 8876646 # number of ReadReq accesses(hits+misses) 558system.cpu.dcache.WriteReq_accesses::0 6152889 # number of WriteReq accesses(hits+misses) 559system.cpu.dcache.WriteReq_accesses::total 6152889 # number of WriteReq accesses(hits+misses) 560system.cpu.dcache.LoadLockedReq_accesses::0 200226 # number of LoadLockedReq accesses(hits+misses) 561system.cpu.dcache.LoadLockedReq_accesses::total 200226 # number of LoadLockedReq accesses(hits+misses) 562system.cpu.dcache.StoreCondReq_accesses::0 199203 # number of StoreCondReq accesses(hits+misses) 563system.cpu.dcache.StoreCondReq_accesses::total 199203 # number of StoreCondReq accesses(hits+misses) 564system.cpu.dcache.demand_accesses::0 15029535 # number of demand (read+write) accesses 565system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses 566system.cpu.dcache.demand_accesses::total 15029535 # number of demand (read+write) accesses 567system.cpu.dcache.overall_accesses::0 15029535 # number of overall (read+write) accesses 568system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses 569system.cpu.dcache.overall_accesses::total 15029535 # number of overall (read+write) accesses 570system.cpu.dcache.ReadReq_miss_rate::0 0.120441 # miss rate for ReadReq accesses 571system.cpu.dcache.WriteReq_miss_rate::0 0.049462 # miss rate for WriteReq accesses 572system.cpu.dcache.LoadLockedReq_miss_rate::0 0.085908 # miss rate for LoadLockedReq accesses 573system.cpu.dcache.demand_miss_rate::0 0.091383 # miss rate for demand accesses 574system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses 575system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses 576system.cpu.dcache.overall_miss_rate::0 0.091383 # miss rate for overall accesses 577system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses 578system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses 579system.cpu.dcache.ReadReq_avg_miss_latency::0 25368.690313 # average ReadReq miss latency 580system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency 581system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency 582system.cpu.dcache.WriteReq_avg_miss_latency::0 30323.439631 # average WriteReq miss latency 583system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency 584system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency 585system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14300.331376 # average LoadLockedReq miss latency 586system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency 587system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency 588system.cpu.dcache.demand_avg_miss_latency::0 26466.589124 # average overall miss latency 589system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency 590system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency 591system.cpu.dcache.overall_avg_miss_latency::0 26466.589124 # average overall miss latency 592system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency 593system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency 594system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 595system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 596system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 597system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 598system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 599system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 600system.cpu.dcache.fast_writes 0 # number of fast writes performed 601system.cpu.dcache.cache_copies 0 # number of cache copies performed 602system.cpu.dcache.writebacks 826586 # number of writebacks 603system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 604system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits 605system.cpu.dcache.ReadReq_mshr_misses 1069110 # number of ReadReq MSHR misses 606system.cpu.dcache.WriteReq_mshr_misses 304335 # number of WriteReq MSHR misses 607system.cpu.dcache.LoadLockedReq_mshr_misses 17201 # number of LoadLockedReq MSHR misses 608system.cpu.dcache.demand_mshr_misses 1373445 # number of demand (read+write) MSHR misses 609system.cpu.dcache.overall_mshr_misses 1373445 # number of overall MSHR misses 610system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 611system.cpu.dcache.ReadReq_mshr_miss_latency 23914545000 # number of ReadReq MSHR miss cycles 612system.cpu.dcache.WriteReq_mshr_miss_latency 8315479000 # number of WriteReq MSHR miss cycles 613system.cpu.dcache.LoadLockedReq_mshr_miss_latency 194377000 # number of LoadLockedReq MSHR miss cycles 614system.cpu.dcache.demand_mshr_miss_latency 32230024000 # number of demand (read+write) MSHR miss cycles 615system.cpu.dcache.overall_mshr_miss_latency 32230024000 # number of overall MSHR miss cycles 616system.cpu.dcache.ReadReq_mshr_uncacheable_latency 862763000 # number of ReadReq MSHR uncacheable cycles 617system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1199607500 # number of WriteReq MSHR uncacheable cycles 618system.cpu.dcache.overall_mshr_uncacheable_latency 2062370500 # number of overall MSHR uncacheable cycles 619system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.120441 # mshr miss rate for ReadReq accesses 620system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses 621system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses 622system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.049462 # mshr miss rate for WriteReq accesses 623system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses 624system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses 625system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.085908 # mshr miss rate for LoadLockedReq accesses 626system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses 627system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses 628system.cpu.dcache.demand_mshr_miss_rate::0 0.091383 # mshr miss rate for demand accesses 629system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses 630system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses 631system.cpu.dcache.overall_mshr_miss_rate::0 0.091383 # mshr miss rate for overall accesses 632system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses 633system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses 634system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22368.647754 # average ReadReq mshr miss latency 635system.cpu.dcache.WriteReq_avg_mshr_miss_latency 27323.439631 # average WriteReq mshr miss latency 636system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11300.331376 # average LoadLockedReq mshr miss latency 637system.cpu.dcache.demand_avg_mshr_miss_latency 23466.555996 # average overall mshr miss latency 638system.cpu.dcache.overall_avg_mshr_miss_latency 23466.555996 # average overall mshr miss latency 639system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency 640system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency 641system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency 642system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 643system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 644system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 645 646---------- End Simulation Statistics ---------- 647