stats.txt revision 11502:e273e86a873d
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.941276 # Number of seconds simulated 4sim_ticks 1941275996000 # Number of ticks simulated 5final_tick 1941275996000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 855166 # Simulator instruction rate (inst/s) 8host_op_rate 855166 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 29548473540 # Simulator tick rate (ticks/s) 10host_mem_usage 325188 # Number of bytes of host memory used 11host_seconds 65.70 # Real time elapsed on the host 12sim_insts 56182685 # Number of instructions simulated 13sim_ops 56182685 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 844800 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24856512 # Number of bytes read from this memory 18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 19system.physmem.bytes_read::total 25702272 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 844800 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 844800 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 7410752 # Number of bytes written to this memory 23system.physmem.bytes_written::total 7410752 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 13200 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 388383 # Number of read requests responded to by this memory 26system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory 27system.physmem.num_reads::total 401598 # Number of read requests responded to by this memory 28system.physmem.num_writes::writebacks 115793 # Number of write requests responded to by this memory 29system.physmem.num_writes::total 115793 # Number of write requests responded to by this memory 30system.physmem.bw_read::cpu.inst 435178 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::cpu.data 12804213 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::tsunami.ide 495 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::total 13239886 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_inst_read::cpu.inst 435178 # Instruction read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::total 435178 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_write::writebacks 3817464 # Write bandwidth from this memory (bytes/s) 37system.physmem.bw_write::total 3817464 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_total::writebacks 3817464 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::cpu.inst 435178 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.data 12804213 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::tsunami.ide 495 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::total 17057350 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.readReqs 401598 # Number of read requests accepted 44system.physmem.writeReqs 115793 # Number of write requests accepted 45system.physmem.readBursts 401598 # Number of DRAM read bursts, including those serviced by the write queue 46system.physmem.writeBursts 115793 # Number of DRAM write bursts, including those merged in the write queue 47system.physmem.bytesReadDRAM 25694784 # Total number of bytes read from DRAM 48system.physmem.bytesReadWrQ 7488 # Total number of bytes read from write queue 49system.physmem.bytesWritten 7408704 # Total number of bytes written to DRAM 50system.physmem.bytesReadSys 25702272 # Total read bytes from the system interface side 51system.physmem.bytesWrittenSys 7410752 # Total written bytes from the system interface side 52system.physmem.servicedByWrQ 117 # Number of DRAM read bursts serviced by the write queue 53system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 54system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 55system.physmem.perBankRdBursts::0 25225 # Per bank write bursts 56system.physmem.perBankRdBursts::1 25628 # Per bank write bursts 57system.physmem.perBankRdBursts::2 25541 # Per bank write bursts 58system.physmem.perBankRdBursts::3 25494 # Per bank write bursts 59system.physmem.perBankRdBursts::4 25069 # Per bank write bursts 60system.physmem.perBankRdBursts::5 24955 # Per bank write bursts 61system.physmem.perBankRdBursts::6 24242 # Per bank write bursts 62system.physmem.perBankRdBursts::7 24604 # Per bank write bursts 63system.physmem.perBankRdBursts::8 25085 # Per bank write bursts 64system.physmem.perBankRdBursts::9 24651 # Per bank write bursts 65system.physmem.perBankRdBursts::10 25269 # Per bank write bursts 66system.physmem.perBankRdBursts::11 24875 # Per bank write bursts 67system.physmem.perBankRdBursts::12 24508 # Per bank write bursts 68system.physmem.perBankRdBursts::13 25360 # Per bank write bursts 69system.physmem.perBankRdBursts::14 25616 # Per bank write bursts 70system.physmem.perBankRdBursts::15 25359 # Per bank write bursts 71system.physmem.perBankWrBursts::0 7625 # Per bank write bursts 72system.physmem.perBankWrBursts::1 7638 # Per bank write bursts 73system.physmem.perBankWrBursts::2 7842 # Per bank write bursts 74system.physmem.perBankWrBursts::3 7532 # Per bank write bursts 75system.physmem.perBankWrBursts::4 7224 # Per bank write bursts 76system.physmem.perBankWrBursts::5 6973 # Per bank write bursts 77system.physmem.perBankWrBursts::6 6356 # Per bank write bursts 78system.physmem.perBankWrBursts::7 6427 # Per bank write bursts 79system.physmem.perBankWrBursts::8 7248 # Per bank write bursts 80system.physmem.perBankWrBursts::9 6409 # Per bank write bursts 81system.physmem.perBankWrBursts::10 7117 # Per bank write bursts 82system.physmem.perBankWrBursts::11 6905 # Per bank write bursts 83system.physmem.perBankWrBursts::12 7093 # Per bank write bursts 84system.physmem.perBankWrBursts::13 7822 # Per bank write bursts 85system.physmem.perBankWrBursts::14 7863 # Per bank write bursts 86system.physmem.perBankWrBursts::15 7687 # Per bank write bursts 87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 88system.physmem.numWrRetry 8 # Number of times write queue was full causing retry 89system.physmem.totGap 1941264122500 # Total gap between requests 90system.physmem.readPktSize::0 0 # Read request sizes (log2) 91system.physmem.readPktSize::1 0 # Read request sizes (log2) 92system.physmem.readPktSize::2 0 # Read request sizes (log2) 93system.physmem.readPktSize::3 0 # Read request sizes (log2) 94system.physmem.readPktSize::4 0 # Read request sizes (log2) 95system.physmem.readPktSize::5 0 # Read request sizes (log2) 96system.physmem.readPktSize::6 401598 # Read request sizes (log2) 97system.physmem.writePktSize::0 0 # Write request sizes (log2) 98system.physmem.writePktSize::1 0 # Write request sizes (log2) 99system.physmem.writePktSize::2 0 # Write request sizes (log2) 100system.physmem.writePktSize::3 0 # Write request sizes (log2) 101system.physmem.writePktSize::4 0 # Write request sizes (log2) 102system.physmem.writePktSize::5 0 # Write request sizes (log2) 103system.physmem.writePktSize::6 115793 # Write request sizes (log2) 104system.physmem.rdQLenPdf::0 401467 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::1 1 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 136system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::15 1806 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::16 3249 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::17 7105 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::18 5703 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::19 6714 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::20 5907 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::21 5702 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::22 6222 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::23 6746 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::24 6250 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::25 8124 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::26 8385 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::27 7085 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::28 7386 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::29 6734 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::30 6941 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::31 5812 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::32 5400 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::33 238 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::34 188 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::35 170 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::36 137 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::37 103 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::38 203 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::39 108 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::40 138 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::41 138 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::42 146 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::43 179 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::44 218 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::45 158 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::46 212 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::47 264 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::48 181 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::49 256 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::50 159 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::51 153 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::52 176 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::53 103 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::54 122 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::55 116 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::56 115 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::57 90 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::58 118 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::59 95 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::60 101 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::61 57 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::62 31 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::63 34 # What write queue length does an incoming req see 200system.physmem.bytesPerActivate::samples 64912 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::mean 509.974858 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::gmean 310.431433 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::stdev 406.117715 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::0-127 15298 23.57% 23.57% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::128-255 11509 17.73% 41.30% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::256-383 4967 7.65% 48.95% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::384-511 3096 4.77% 53.72% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::512-639 2467 3.80% 57.52% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::640-767 4201 6.47% 63.99% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::768-895 1427 2.20% 66.19% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-1023 2061 3.18% 69.36% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1024-1151 19886 30.64% 100.00% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::total 64912 # Bytes accessed per row activation 214system.physmem.rdPerTurnAround::samples 5093 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::mean 78.826036 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::stdev 2956.913485 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::0-8191 5090 99.94% 99.94% # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes 221system.physmem.rdPerTurnAround::total 5093 # Reads before turning the bus around for writes 222system.physmem.wrPerTurnAround::samples 5093 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::mean 22.729433 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::gmean 19.333640 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::stdev 21.082746 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::16-23 4499 88.34% 88.34% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::24-31 29 0.57% 88.91% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::32-39 20 0.39% 89.30% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::40-47 41 0.81% 90.10% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::48-55 209 4.10% 94.21% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::56-63 11 0.22% 94.42% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::64-71 11 0.22% 94.64% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::72-79 30 0.59% 95.23% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::80-87 184 3.61% 98.84% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::88-95 6 0.12% 98.96% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::96-103 5 0.10% 99.06% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::104-111 4 0.08% 99.14% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::120-127 1 0.02% 99.16% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::128-135 8 0.16% 99.31% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::136-143 5 0.10% 99.41% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::144-151 1 0.02% 99.43% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::160-167 4 0.08% 99.51% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::168-175 5 0.10% 99.61% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::176-183 5 0.10% 99.71% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::184-191 1 0.02% 99.73% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::192-199 2 0.04% 99.76% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::208-215 7 0.14% 99.90% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::240-247 1 0.02% 99.92% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::256-263 4 0.08% 100.00% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::total 5093 # Writes before turning the bus around for reads 251system.physmem.totQLat 2720413750 # Total ticks spent queuing 252system.physmem.totMemAccLat 10248182500 # Total ticks spent from burst creation until serviced by the DRAM 253system.physmem.totBusLat 2007405000 # Total ticks spent in databus transfers 254system.physmem.avgQLat 6775.95 # Average queueing delay per DRAM burst 255system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 256system.physmem.avgMemAccLat 25525.95 # Average memory access latency per DRAM burst 257system.physmem.avgRdBW 13.24 # Average DRAM read bandwidth in MiByte/s 258system.physmem.avgWrBW 3.82 # Average achieved write bandwidth in MiByte/s 259system.physmem.avgRdBWSys 13.24 # Average system read bandwidth in MiByte/s 260system.physmem.avgWrBWSys 3.82 # Average system write bandwidth in MiByte/s 261system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 262system.physmem.busUtil 0.13 # Data bus utilization in percentage 263system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads 264system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 265system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 266system.physmem.avgWrQLen 22.10 # Average write queue length when enqueuing 267system.physmem.readRowHits 358846 # Number of row buffer hits during reads 268system.physmem.writeRowHits 93484 # Number of row buffer hits during writes 269system.physmem.readRowHitRate 89.38 # Row buffer hit rate for reads 270system.physmem.writeRowHitRate 80.73 # Row buffer hit rate for writes 271system.physmem.avgGap 3752025.30 # Average gap between requests 272system.physmem.pageHitRate 87.44 # Row buffer hit rate, read and write combined 273system.physmem_0.actEnergy 240264360 # Energy for activate commands per rank (pJ) 274system.physmem_0.preEnergy 131096625 # Energy for precharge commands per rank (pJ) 275system.physmem_0.readEnergy 1565912400 # Energy for read commands per rank (pJ) 276system.physmem_0.writeEnergy 373358160 # Energy for write commands per rank (pJ) 277system.physmem_0.refreshEnergy 126794687760 # Energy for refresh commands per rank (pJ) 278system.physmem_0.actBackEnergy 71567841690 # Energy for active background per rank (pJ) 279system.physmem_0.preBackEnergy 1101986721000 # Energy for precharge background per rank (pJ) 280system.physmem_0.totalEnergy 1302659881995 # Total energy per rank (pJ) 281system.physmem_0.averagePower 671.032847 # Core power per rank (mW) 282system.physmem_0.memoryStateTime::IDLE 1832974788000 # Time in different power states 283system.physmem_0.memoryStateTime::REF 64823460000 # Time in different power states 284system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 285system.physmem_0.memoryStateTime::ACT 43477648250 # Time in different power states 286system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 287system.physmem_1.actEnergy 250470360 # Energy for activate commands per rank (pJ) 288system.physmem_1.preEnergy 136665375 # Energy for precharge commands per rank (pJ) 289system.physmem_1.readEnergy 1565639400 # Energy for read commands per rank (pJ) 290system.physmem_1.writeEnergy 376773120 # Energy for write commands per rank (pJ) 291system.physmem_1.refreshEnergy 126794687760 # Energy for refresh commands per rank (pJ) 292system.physmem_1.actBackEnergy 72629101890 # Energy for active background per rank (pJ) 293system.physmem_1.preBackEnergy 1101055791000 # Energy for precharge background per rank (pJ) 294system.physmem_1.totalEnergy 1302809128905 # Total energy per rank (pJ) 295system.physmem_1.averagePower 671.109728 # Core power per rank (mW) 296system.physmem_1.memoryStateTime::IDLE 1831423384000 # Time in different power states 297system.physmem_1.memoryStateTime::REF 64823460000 # Time in different power states 298system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 299system.physmem_1.memoryStateTime::ACT 45029052250 # Time in different power states 300system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 301system.cpu_clk_domain.clock 500 # Clock period in ticks 302system.cpu.dtb.fetch_hits 0 # ITB hits 303system.cpu.dtb.fetch_misses 0 # ITB misses 304system.cpu.dtb.fetch_acv 0 # ITB acv 305system.cpu.dtb.fetch_accesses 0 # ITB accesses 306system.cpu.dtb.read_hits 9064642 # DTB read hits 307system.cpu.dtb.read_misses 10324 # DTB read misses 308system.cpu.dtb.read_acv 210 # DTB read access violations 309system.cpu.dtb.read_accesses 728853 # DTB read accesses 310system.cpu.dtb.write_hits 6356200 # DTB write hits 311system.cpu.dtb.write_misses 1142 # DTB write misses 312system.cpu.dtb.write_acv 157 # DTB write access violations 313system.cpu.dtb.write_accesses 291931 # DTB write accesses 314system.cpu.dtb.data_hits 15420842 # DTB hits 315system.cpu.dtb.data_misses 11466 # DTB misses 316system.cpu.dtb.data_acv 367 # DTB access violations 317system.cpu.dtb.data_accesses 1020784 # DTB accesses 318system.cpu.itb.fetch_hits 4975134 # ITB hits 319system.cpu.itb.fetch_misses 5010 # ITB misses 320system.cpu.itb.fetch_acv 184 # ITB acv 321system.cpu.itb.fetch_accesses 4980144 # ITB accesses 322system.cpu.itb.read_hits 0 # DTB read hits 323system.cpu.itb.read_misses 0 # DTB read misses 324system.cpu.itb.read_acv 0 # DTB read access violations 325system.cpu.itb.read_accesses 0 # DTB read accesses 326system.cpu.itb.write_hits 0 # DTB write hits 327system.cpu.itb.write_misses 0 # DTB write misses 328system.cpu.itb.write_acv 0 # DTB write access violations 329system.cpu.itb.write_accesses 0 # DTB write accesses 330system.cpu.itb.data_hits 0 # DTB hits 331system.cpu.itb.data_misses 0 # DTB misses 332system.cpu.itb.data_acv 0 # DTB access violations 333system.cpu.itb.data_accesses 0 # DTB accesses 334system.cpu.numCycles 3882551992 # number of cpu cycles simulated 335system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 336system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 337system.cpu.kern.inst.arm 0 # number of arm instructions executed 338system.cpu.kern.inst.quiesce 6375 # number of quiesce instructions executed 339system.cpu.kern.inst.hwrei 212050 # number of hwrei instructions executed 340system.cpu.kern.ipl_count::0 74912 40.88% 40.88% # number of times we switched to this ipl 341system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl 342system.cpu.kern.ipl_count::22 1935 1.06% 42.01% # number of times we switched to this ipl 343system.cpu.kern.ipl_count::31 106253 57.99% 100.00% # number of times we switched to this ipl 344system.cpu.kern.ipl_count::total 183231 # number of times we switched to this ipl 345system.cpu.kern.ipl_good::0 73545 49.31% 49.31% # number of times we switched to this ipl from a different ipl 346system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl 347system.cpu.kern.ipl_good::22 1935 1.30% 50.69% # number of times we switched to this ipl from a different ipl 348system.cpu.kern.ipl_good::31 73545 49.31% 100.00% # number of times we switched to this ipl from a different ipl 349system.cpu.kern.ipl_good::total 149156 # number of times we switched to this ipl from a different ipl 350system.cpu.kern.ipl_ticks::0 1860509936500 95.84% 95.84% # number of cycles we spent at this ipl 351system.cpu.kern.ipl_ticks::21 94066500 0.00% 95.84% # number of cycles we spent at this ipl 352system.cpu.kern.ipl_ticks::22 770529000 0.04% 95.88% # number of cycles we spent at this ipl 353system.cpu.kern.ipl_ticks::31 79900730000 4.12% 100.00% # number of cycles we spent at this ipl 354system.cpu.kern.ipl_ticks::total 1941275262000 # number of cycles we spent at this ipl 355system.cpu.kern.ipl_used::0 0.981752 # fraction of swpipl calls that actually changed the ipl 356system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 357system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 358system.cpu.kern.ipl_used::31 0.692169 # fraction of swpipl calls that actually changed the ipl 359system.cpu.kern.ipl_used::total 0.814033 # fraction of swpipl calls that actually changed the ipl 360system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 361system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 362system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 363system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 364system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 365system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 366system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 367system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed 368system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed 369system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed 370system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed 371system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed 372system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed 373system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed 374system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed 375system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed 376system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed 377system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed 378system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed 379system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed 380system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed 381system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed 382system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed 383system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed 384system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed 385system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed 386system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed 387system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 388system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 389system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 390system.cpu.kern.syscall::total 326 # number of syscalls executed 391system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 392system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 393system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 394system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 395system.cpu.kern.callpal::swpctx 4176 2.16% 2.17% # number of callpals executed 396system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed 397system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed 398system.cpu.kern.callpal::swpipl 176004 91.22% 93.41% # number of callpals executed 399system.cpu.kern.callpal::rdps 6835 3.54% 96.96% # number of callpals executed 400system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed 401system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed 402system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed 403system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed 404system.cpu.kern.callpal::rti 5160 2.67% 99.64% # number of callpals executed 405system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 406system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed 407system.cpu.kern.callpal::total 192955 # number of callpals executed 408system.cpu.kern.mode_switch::kernel 5908 # number of protection mode switches 409system.cpu.kern.mode_switch::user 1739 # number of protection mode switches 410system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches 411system.cpu.kern.mode_good::kernel 1909 412system.cpu.kern.mode_good::user 1739 413system.cpu.kern.mode_good::idle 170 414system.cpu.kern.mode_switch_good::kernel 0.323121 # fraction of useful protection mode switches 415system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 416system.cpu.kern.mode_switch_good::idle 0.081184 # fraction of useful protection mode switches 417system.cpu.kern.mode_switch_good::total 0.391952 # fraction of useful protection mode switches 418system.cpu.kern.mode_ticks::kernel 48613441500 2.50% 2.50% # number of ticks spent at the given mode 419system.cpu.kern.mode_ticks::user 5603081000 0.29% 2.79% # number of ticks spent at the given mode 420system.cpu.kern.mode_ticks::idle 1887058737500 97.21% 100.00% # number of ticks spent at the given mode 421system.cpu.kern.swap_context 4177 # number of times the context was actually changed 422system.cpu.committedInsts 56182685 # Number of instructions committed 423system.cpu.committedOps 56182685 # Number of ops (including micro ops) committed 424system.cpu.num_int_alu_accesses 52054580 # Number of integer alu accesses 425system.cpu.num_fp_alu_accesses 324393 # Number of float alu accesses 426system.cpu.num_func_calls 1483390 # number of times a function call or return occured 427system.cpu.num_conditional_control_insts 6468674 # number of instructions that are conditional controls 428system.cpu.num_int_insts 52054580 # number of integer instructions 429system.cpu.num_fp_insts 324393 # number of float instructions 430system.cpu.num_int_register_reads 71322431 # number of times the integer registers were read 431system.cpu.num_int_register_writes 38520860 # number of times the integer registers were written 432system.cpu.num_fp_register_reads 163609 # number of times the floating registers were read 433system.cpu.num_fp_register_writes 166486 # number of times the floating registers were written 434system.cpu.num_mem_refs 15473452 # number of memory refs 435system.cpu.num_load_insts 9101488 # Number of load instructions 436system.cpu.num_store_insts 6371964 # Number of store instructions 437system.cpu.num_idle_cycles 3583831790.000154 # Number of idle cycles 438system.cpu.num_busy_cycles 298720201.999846 # Number of busy cycles 439system.cpu.not_idle_fraction 0.076939 # Percentage of non-idle cycles 440system.cpu.idle_fraction 0.923061 # Percentage of idle cycles 441system.cpu.Branches 8422715 # Number of branches fetched 442system.cpu.op_class::No_OpClass 3200634 5.70% 5.70% # Class of executed instruction 443system.cpu.op_class::IntAlu 36230987 64.47% 70.17% # Class of executed instruction 444system.cpu.op_class::IntMult 61043 0.11% 70.28% # Class of executed instruction 445system.cpu.op_class::IntDiv 0 0.00% 70.28% # Class of executed instruction 446system.cpu.op_class::FloatAdd 38085 0.07% 70.35% # Class of executed instruction 447system.cpu.op_class::FloatCmp 0 0.00% 70.35% # Class of executed instruction 448system.cpu.op_class::FloatCvt 0 0.00% 70.35% # Class of executed instruction 449system.cpu.op_class::FloatMult 0 0.00% 70.35% # Class of executed instruction 450system.cpu.op_class::FloatDiv 3636 0.01% 70.35% # Class of executed instruction 451system.cpu.op_class::FloatSqrt 0 0.00% 70.35% # Class of executed instruction 452system.cpu.op_class::SimdAdd 0 0.00% 70.35% # Class of executed instruction 453system.cpu.op_class::SimdAddAcc 0 0.00% 70.35% # Class of executed instruction 454system.cpu.op_class::SimdAlu 0 0.00% 70.35% # Class of executed instruction 455system.cpu.op_class::SimdCmp 0 0.00% 70.35% # Class of executed instruction 456system.cpu.op_class::SimdCvt 0 0.00% 70.35% # Class of executed instruction 457system.cpu.op_class::SimdMisc 0 0.00% 70.35% # Class of executed instruction 458system.cpu.op_class::SimdMult 0 0.00% 70.35% # Class of executed instruction 459system.cpu.op_class::SimdMultAcc 0 0.00% 70.35% # Class of executed instruction 460system.cpu.op_class::SimdShift 0 0.00% 70.35% # Class of executed instruction 461system.cpu.op_class::SimdShiftAcc 0 0.00% 70.35% # Class of executed instruction 462system.cpu.op_class::SimdSqrt 0 0.00% 70.35% # Class of executed instruction 463system.cpu.op_class::SimdFloatAdd 0 0.00% 70.35% # Class of executed instruction 464system.cpu.op_class::SimdFloatAlu 0 0.00% 70.35% # Class of executed instruction 465system.cpu.op_class::SimdFloatCmp 0 0.00% 70.35% # Class of executed instruction 466system.cpu.op_class::SimdFloatCvt 0 0.00% 70.35% # Class of executed instruction 467system.cpu.op_class::SimdFloatDiv 0 0.00% 70.35% # Class of executed instruction 468system.cpu.op_class::SimdFloatMisc 0 0.00% 70.35% # Class of executed instruction 469system.cpu.op_class::SimdFloatMult 0 0.00% 70.35% # Class of executed instruction 470system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.35% # Class of executed instruction 471system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.35% # Class of executed instruction 472system.cpu.op_class::MemRead 9328618 16.60% 86.95% # Class of executed instruction 473system.cpu.op_class::MemWrite 6378045 11.35% 98.30% # Class of executed instruction 474system.cpu.op_class::IprAccess 953470 1.70% 100.00% # Class of executed instruction 475system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 476system.cpu.op_class::total 56194518 # Class of executed instruction 477system.cpu.dcache.tags.replacements 1390402 # number of replacements 478system.cpu.dcache.tags.tagsinuse 511.973391 # Cycle average of tags in use 479system.cpu.dcache.tags.total_refs 14048961 # Total number of references to valid blocks. 480system.cpu.dcache.tags.sampled_refs 1390914 # Sample count of references to valid blocks. 481system.cpu.dcache.tags.avg_refs 10.100525 # Average number of references to valid blocks. 482system.cpu.dcache.tags.warmup_cycle 145150500 # Cycle when the warmup percentage was hit. 483system.cpu.dcache.tags.occ_blocks::cpu.data 511.973391 # Average occupied blocks per requestor 484system.cpu.dcache.tags.occ_percent::cpu.data 0.999948 # Average percentage of cache occupancy 485system.cpu.dcache.tags.occ_percent::total 0.999948 # Average percentage of cache occupancy 486system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 487system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id 488system.cpu.dcache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id 489system.cpu.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id 490system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 491system.cpu.dcache.tags.tag_accesses 63150419 # Number of tag accesses 492system.cpu.dcache.tags.data_accesses 63150419 # Number of data accesses 493system.cpu.dcache.ReadReq_hits::cpu.data 7814383 # number of ReadReq hits 494system.cpu.dcache.ReadReq_hits::total 7814383 # number of ReadReq hits 495system.cpu.dcache.WriteReq_hits::cpu.data 5852265 # number of WriteReq hits 496system.cpu.dcache.WriteReq_hits::total 5852265 # number of WriteReq hits 497system.cpu.dcache.LoadLockedReq_hits::cpu.data 183036 # number of LoadLockedReq hits 498system.cpu.dcache.LoadLockedReq_hits::total 183036 # number of LoadLockedReq hits 499system.cpu.dcache.StoreCondReq_hits::cpu.data 199260 # number of StoreCondReq hits 500system.cpu.dcache.StoreCondReq_hits::total 199260 # number of StoreCondReq hits 501system.cpu.dcache.demand_hits::cpu.data 13666648 # number of demand (read+write) hits 502system.cpu.dcache.demand_hits::total 13666648 # number of demand (read+write) hits 503system.cpu.dcache.overall_hits::cpu.data 13666648 # number of overall hits 504system.cpu.dcache.overall_hits::total 13666648 # number of overall hits 505system.cpu.dcache.ReadReq_misses::cpu.data 1069359 # number of ReadReq misses 506system.cpu.dcache.ReadReq_misses::total 1069359 # number of ReadReq misses 507system.cpu.dcache.WriteReq_misses::cpu.data 304327 # number of WriteReq misses 508system.cpu.dcache.WriteReq_misses::total 304327 # number of WriteReq misses 509system.cpu.dcache.LoadLockedReq_misses::cpu.data 17246 # number of LoadLockedReq misses 510system.cpu.dcache.LoadLockedReq_misses::total 17246 # number of LoadLockedReq misses 511system.cpu.dcache.demand_misses::cpu.data 1373686 # number of demand (read+write) misses 512system.cpu.dcache.demand_misses::total 1373686 # number of demand (read+write) misses 513system.cpu.dcache.overall_misses::cpu.data 1373686 # number of overall misses 514system.cpu.dcache.overall_misses::total 1373686 # number of overall misses 515system.cpu.dcache.ReadReq_miss_latency::cpu.data 44772641000 # number of ReadReq miss cycles 516system.cpu.dcache.ReadReq_miss_latency::total 44772641000 # number of ReadReq miss cycles 517system.cpu.dcache.WriteReq_miss_latency::cpu.data 17635172000 # number of WriteReq miss cycles 518system.cpu.dcache.WriteReq_miss_latency::total 17635172000 # number of WriteReq miss cycles 519system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 232797500 # number of LoadLockedReq miss cycles 520system.cpu.dcache.LoadLockedReq_miss_latency::total 232797500 # number of LoadLockedReq miss cycles 521system.cpu.dcache.demand_miss_latency::cpu.data 62407813000 # number of demand (read+write) miss cycles 522system.cpu.dcache.demand_miss_latency::total 62407813000 # number of demand (read+write) miss cycles 523system.cpu.dcache.overall_miss_latency::cpu.data 62407813000 # number of overall miss cycles 524system.cpu.dcache.overall_miss_latency::total 62407813000 # number of overall miss cycles 525system.cpu.dcache.ReadReq_accesses::cpu.data 8883742 # number of ReadReq accesses(hits+misses) 526system.cpu.dcache.ReadReq_accesses::total 8883742 # number of ReadReq accesses(hits+misses) 527system.cpu.dcache.WriteReq_accesses::cpu.data 6156592 # number of WriteReq accesses(hits+misses) 528system.cpu.dcache.WriteReq_accesses::total 6156592 # number of WriteReq accesses(hits+misses) 529system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200282 # number of LoadLockedReq accesses(hits+misses) 530system.cpu.dcache.LoadLockedReq_accesses::total 200282 # number of LoadLockedReq accesses(hits+misses) 531system.cpu.dcache.StoreCondReq_accesses::cpu.data 199260 # number of StoreCondReq accesses(hits+misses) 532system.cpu.dcache.StoreCondReq_accesses::total 199260 # number of StoreCondReq accesses(hits+misses) 533system.cpu.dcache.demand_accesses::cpu.data 15040334 # number of demand (read+write) accesses 534system.cpu.dcache.demand_accesses::total 15040334 # number of demand (read+write) accesses 535system.cpu.dcache.overall_accesses::cpu.data 15040334 # number of overall (read+write) accesses 536system.cpu.dcache.overall_accesses::total 15040334 # number of overall (read+write) accesses 537system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120373 # miss rate for ReadReq accesses 538system.cpu.dcache.ReadReq_miss_rate::total 0.120373 # miss rate for ReadReq accesses 539system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049431 # miss rate for WriteReq accesses 540system.cpu.dcache.WriteReq_miss_rate::total 0.049431 # miss rate for WriteReq accesses 541system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086109 # miss rate for LoadLockedReq accesses 542system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086109 # miss rate for LoadLockedReq accesses 543system.cpu.dcache.demand_miss_rate::cpu.data 0.091333 # miss rate for demand accesses 544system.cpu.dcache.demand_miss_rate::total 0.091333 # miss rate for demand accesses 545system.cpu.dcache.overall_miss_rate::cpu.data 0.091333 # miss rate for overall accesses 546system.cpu.dcache.overall_miss_rate::total 0.091333 # miss rate for overall accesses 547system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41868.671793 # average ReadReq miss latency 548system.cpu.dcache.ReadReq_avg_miss_latency::total 41868.671793 # average ReadReq miss latency 549system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57948.101877 # average WriteReq miss latency 550system.cpu.dcache.WriteReq_avg_miss_latency::total 57948.101877 # average WriteReq miss latency 551system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13498.637365 # average LoadLockedReq miss latency 552system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13498.637365 # average LoadLockedReq miss latency 553system.cpu.dcache.demand_avg_miss_latency::cpu.data 45430.915799 # average overall miss latency 554system.cpu.dcache.demand_avg_miss_latency::total 45430.915799 # average overall miss latency 555system.cpu.dcache.overall_avg_miss_latency::cpu.data 45430.915799 # average overall miss latency 556system.cpu.dcache.overall_avg_miss_latency::total 45430.915799 # average overall miss latency 557system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 558system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 559system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 560system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 561system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 562system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 563system.cpu.dcache.writebacks::writebacks 834944 # number of writebacks 564system.cpu.dcache.writebacks::total 834944 # number of writebacks 565system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069359 # number of ReadReq MSHR misses 566system.cpu.dcache.ReadReq_mshr_misses::total 1069359 # number of ReadReq MSHR misses 567system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304327 # number of WriteReq MSHR misses 568system.cpu.dcache.WriteReq_mshr_misses::total 304327 # number of WriteReq MSHR misses 569system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17246 # number of LoadLockedReq MSHR misses 570system.cpu.dcache.LoadLockedReq_mshr_misses::total 17246 # number of LoadLockedReq MSHR misses 571system.cpu.dcache.demand_mshr_misses::cpu.data 1373686 # number of demand (read+write) MSHR misses 572system.cpu.dcache.demand_mshr_misses::total 1373686 # number of demand (read+write) MSHR misses 573system.cpu.dcache.overall_mshr_misses::cpu.data 1373686 # number of overall MSHR misses 574system.cpu.dcache.overall_mshr_misses::total 1373686 # number of overall MSHR misses 575system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 576system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable 577system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9653 # number of WriteReq MSHR uncacheable 578system.cpu.dcache.WriteReq_mshr_uncacheable::total 9653 # number of WriteReq MSHR uncacheable 579system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16583 # number of overall MSHR uncacheable misses 580system.cpu.dcache.overall_mshr_uncacheable_misses::total 16583 # number of overall MSHR uncacheable misses 581system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43703282000 # number of ReadReq MSHR miss cycles 582system.cpu.dcache.ReadReq_mshr_miss_latency::total 43703282000 # number of ReadReq MSHR miss cycles 583system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17330845000 # number of WriteReq MSHR miss cycles 584system.cpu.dcache.WriteReq_mshr_miss_latency::total 17330845000 # number of WriteReq MSHR miss cycles 585system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 215551500 # number of LoadLockedReq MSHR miss cycles 586system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 215551500 # number of LoadLockedReq MSHR miss cycles 587system.cpu.dcache.demand_mshr_miss_latency::cpu.data 61034127000 # number of demand (read+write) MSHR miss cycles 588system.cpu.dcache.demand_mshr_miss_latency::total 61034127000 # number of demand (read+write) MSHR miss cycles 589system.cpu.dcache.overall_mshr_miss_latency::cpu.data 61034127000 # number of overall MSHR miss cycles 590system.cpu.dcache.overall_mshr_miss_latency::total 61034127000 # number of overall MSHR miss cycles 591system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1526978500 # number of ReadReq MSHR uncacheable cycles 592system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1526978500 # number of ReadReq MSHR uncacheable cycles 593system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1526978500 # number of overall MSHR uncacheable cycles 594system.cpu.dcache.overall_mshr_uncacheable_latency::total 1526978500 # number of overall MSHR uncacheable cycles 595system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120373 # mshr miss rate for ReadReq accesses 596system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120373 # mshr miss rate for ReadReq accesses 597system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049431 # mshr miss rate for WriteReq accesses 598system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049431 # mshr miss rate for WriteReq accesses 599system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086109 # mshr miss rate for LoadLockedReq accesses 600system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086109 # mshr miss rate for LoadLockedReq accesses 601system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091333 # mshr miss rate for demand accesses 602system.cpu.dcache.demand_mshr_miss_rate::total 0.091333 # mshr miss rate for demand accesses 603system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091333 # mshr miss rate for overall accesses 604system.cpu.dcache.overall_mshr_miss_rate::total 0.091333 # mshr miss rate for overall accesses 605system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40868.671793 # average ReadReq mshr miss latency 606system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40868.671793 # average ReadReq mshr miss latency 607system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56948.101877 # average WriteReq mshr miss latency 608system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56948.101877 # average WriteReq mshr miss latency 609system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12498.637365 # average LoadLockedReq mshr miss latency 610system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12498.637365 # average LoadLockedReq mshr miss latency 611system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44430.915799 # average overall mshr miss latency 612system.cpu.dcache.demand_avg_mshr_miss_latency::total 44430.915799 # average overall mshr miss latency 613system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44430.915799 # average overall mshr miss latency 614system.cpu.dcache.overall_avg_mshr_miss_latency::total 44430.915799 # average overall mshr miss latency 615system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220343.217893 # average ReadReq mshr uncacheable latency 616system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220343.217893 # average ReadReq mshr uncacheable latency 617system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92080.956401 # average overall mshr uncacheable latency 618system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92080.956401 # average overall mshr uncacheable latency 619system.cpu.icache.tags.replacements 928931 # number of replacements 620system.cpu.icache.tags.tagsinuse 506.355616 # Cycle average of tags in use 621system.cpu.icache.tags.total_refs 55264917 # Total number of references to valid blocks. 622system.cpu.icache.tags.sampled_refs 929442 # Sample count of references to valid blocks. 623system.cpu.icache.tags.avg_refs 59.460318 # Average number of references to valid blocks. 624system.cpu.icache.tags.warmup_cycle 58592056500 # Cycle when the warmup percentage was hit. 625system.cpu.icache.tags.occ_blocks::cpu.inst 506.355616 # Average occupied blocks per requestor 626system.cpu.icache.tags.occ_percent::cpu.inst 0.988976 # Average percentage of cache occupancy 627system.cpu.icache.tags.occ_percent::total 0.988976 # Average percentage of cache occupancy 628system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 629system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id 630system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 631system.cpu.icache.tags.age_task_id_blocks_1024::2 438 # Occupied blocks per task id 632system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id 633system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id 634system.cpu.icache.tags.tag_accesses 57124121 # Number of tag accesses 635system.cpu.icache.tags.data_accesses 57124121 # Number of data accesses 636system.cpu.icache.ReadReq_hits::cpu.inst 55264917 # number of ReadReq hits 637system.cpu.icache.ReadReq_hits::total 55264917 # number of ReadReq hits 638system.cpu.icache.demand_hits::cpu.inst 55264917 # number of demand (read+write) hits 639system.cpu.icache.demand_hits::total 55264917 # number of demand (read+write) hits 640system.cpu.icache.overall_hits::cpu.inst 55264917 # number of overall hits 641system.cpu.icache.overall_hits::total 55264917 # number of overall hits 642system.cpu.icache.ReadReq_misses::cpu.inst 929602 # number of ReadReq misses 643system.cpu.icache.ReadReq_misses::total 929602 # number of ReadReq misses 644system.cpu.icache.demand_misses::cpu.inst 929602 # number of demand (read+write) misses 645system.cpu.icache.demand_misses::total 929602 # number of demand (read+write) misses 646system.cpu.icache.overall_misses::cpu.inst 929602 # number of overall misses 647system.cpu.icache.overall_misses::total 929602 # number of overall misses 648system.cpu.icache.ReadReq_miss_latency::cpu.inst 13686117000 # number of ReadReq miss cycles 649system.cpu.icache.ReadReq_miss_latency::total 13686117000 # number of ReadReq miss cycles 650system.cpu.icache.demand_miss_latency::cpu.inst 13686117000 # number of demand (read+write) miss cycles 651system.cpu.icache.demand_miss_latency::total 13686117000 # number of demand (read+write) miss cycles 652system.cpu.icache.overall_miss_latency::cpu.inst 13686117000 # number of overall miss cycles 653system.cpu.icache.overall_miss_latency::total 13686117000 # number of overall miss cycles 654system.cpu.icache.ReadReq_accesses::cpu.inst 56194519 # number of ReadReq accesses(hits+misses) 655system.cpu.icache.ReadReq_accesses::total 56194519 # number of ReadReq accesses(hits+misses) 656system.cpu.icache.demand_accesses::cpu.inst 56194519 # number of demand (read+write) accesses 657system.cpu.icache.demand_accesses::total 56194519 # number of demand (read+write) accesses 658system.cpu.icache.overall_accesses::cpu.inst 56194519 # number of overall (read+write) accesses 659system.cpu.icache.overall_accesses::total 56194519 # number of overall (read+write) accesses 660system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016543 # miss rate for ReadReq accesses 661system.cpu.icache.ReadReq_miss_rate::total 0.016543 # miss rate for ReadReq accesses 662system.cpu.icache.demand_miss_rate::cpu.inst 0.016543 # miss rate for demand accesses 663system.cpu.icache.demand_miss_rate::total 0.016543 # miss rate for demand accesses 664system.cpu.icache.overall_miss_rate::cpu.inst 0.016543 # miss rate for overall accesses 665system.cpu.icache.overall_miss_rate::total 0.016543 # miss rate for overall accesses 666system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14722.555459 # average ReadReq miss latency 667system.cpu.icache.ReadReq_avg_miss_latency::total 14722.555459 # average ReadReq miss latency 668system.cpu.icache.demand_avg_miss_latency::cpu.inst 14722.555459 # average overall miss latency 669system.cpu.icache.demand_avg_miss_latency::total 14722.555459 # average overall miss latency 670system.cpu.icache.overall_avg_miss_latency::cpu.inst 14722.555459 # average overall miss latency 671system.cpu.icache.overall_avg_miss_latency::total 14722.555459 # average overall miss latency 672system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 673system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 674system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 675system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 676system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 677system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 678system.cpu.icache.writebacks::writebacks 928931 # number of writebacks 679system.cpu.icache.writebacks::total 928931 # number of writebacks 680system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929602 # number of ReadReq MSHR misses 681system.cpu.icache.ReadReq_mshr_misses::total 929602 # number of ReadReq MSHR misses 682system.cpu.icache.demand_mshr_misses::cpu.inst 929602 # number of demand (read+write) MSHR misses 683system.cpu.icache.demand_mshr_misses::total 929602 # number of demand (read+write) MSHR misses 684system.cpu.icache.overall_mshr_misses::cpu.inst 929602 # number of overall MSHR misses 685system.cpu.icache.overall_mshr_misses::total 929602 # number of overall MSHR misses 686system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12756515000 # number of ReadReq MSHR miss cycles 687system.cpu.icache.ReadReq_mshr_miss_latency::total 12756515000 # number of ReadReq MSHR miss cycles 688system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12756515000 # number of demand (read+write) MSHR miss cycles 689system.cpu.icache.demand_mshr_miss_latency::total 12756515000 # number of demand (read+write) MSHR miss cycles 690system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12756515000 # number of overall MSHR miss cycles 691system.cpu.icache.overall_mshr_miss_latency::total 12756515000 # number of overall MSHR miss cycles 692system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016543 # mshr miss rate for ReadReq accesses 693system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016543 # mshr miss rate for ReadReq accesses 694system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016543 # mshr miss rate for demand accesses 695system.cpu.icache.demand_mshr_miss_rate::total 0.016543 # mshr miss rate for demand accesses 696system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016543 # mshr miss rate for overall accesses 697system.cpu.icache.overall_mshr_miss_rate::total 0.016543 # mshr miss rate for overall accesses 698system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13722.555459 # average ReadReq mshr miss latency 699system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13722.555459 # average ReadReq mshr miss latency 700system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13722.555459 # average overall mshr miss latency 701system.cpu.icache.demand_avg_mshr_miss_latency::total 13722.555459 # average overall mshr miss latency 702system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13722.555459 # average overall mshr miss latency 703system.cpu.icache.overall_avg_mshr_miss_latency::total 13722.555459 # average overall mshr miss latency 704system.cpu.l2cache.tags.replacements 336393 # number of replacements 705system.cpu.l2cache.tags.tagsinuse 65234.360001 # Cycle average of tags in use 706system.cpu.l2cache.tags.total_refs 3930403 # Total number of references to valid blocks. 707system.cpu.l2cache.tags.sampled_refs 401556 # Sample count of references to valid blocks. 708system.cpu.l2cache.tags.avg_refs 9.787932 # Average number of references to valid blocks. 709system.cpu.l2cache.tags.warmup_cycle 10619817000 # Cycle when the warmup percentage was hit. 710system.cpu.l2cache.tags.occ_blocks::writebacks 55072.820493 # Average occupied blocks per requestor 711system.cpu.l2cache.tags.occ_blocks::cpu.inst 4686.121272 # Average occupied blocks per requestor 712system.cpu.l2cache.tags.occ_blocks::cpu.data 5475.418237 # Average occupied blocks per requestor 713system.cpu.l2cache.tags.occ_percent::writebacks 0.840345 # Average percentage of cache occupancy 714system.cpu.l2cache.tags.occ_percent::cpu.inst 0.071505 # Average percentage of cache occupancy 715system.cpu.l2cache.tags.occ_percent::cpu.data 0.083548 # Average percentage of cache occupancy 716system.cpu.l2cache.tags.occ_percent::total 0.995397 # Average percentage of cache occupancy 717system.cpu.l2cache.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id 718system.cpu.l2cache.tags.age_task_id_blocks_1024::0 178 # Occupied blocks per task id 719system.cpu.l2cache.tags.age_task_id_blocks_1024::1 722 # Occupied blocks per task id 720system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5220 # Occupied blocks per task id 721system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3221 # Occupied blocks per task id 722system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55822 # Occupied blocks per task id 723system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id 724system.cpu.l2cache.tags.tag_accesses 37812972 # Number of tag accesses 725system.cpu.l2cache.tags.data_accesses 37812972 # Number of data accesses 726system.cpu.l2cache.WritebackDirty_hits::writebacks 834944 # number of WritebackDirty hits 727system.cpu.l2cache.WritebackDirty_hits::total 834944 # number of WritebackDirty hits 728system.cpu.l2cache.WritebackClean_hits::writebacks 928709 # number of WritebackClean hits 729system.cpu.l2cache.WritebackClean_hits::total 928709 # number of WritebackClean hits 730system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits 731system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits 732system.cpu.l2cache.ReadExReq_hits::cpu.data 187490 # number of ReadExReq hits 733system.cpu.l2cache.ReadExReq_hits::total 187490 # number of ReadExReq hits 734system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 916382 # number of ReadCleanReq hits 735system.cpu.l2cache.ReadCleanReq_hits::total 916382 # number of ReadCleanReq hits 736system.cpu.l2cache.ReadSharedReq_hits::cpu.data 814634 # number of ReadSharedReq hits 737system.cpu.l2cache.ReadSharedReq_hits::total 814634 # number of ReadSharedReq hits 738system.cpu.l2cache.demand_hits::cpu.inst 916382 # number of demand (read+write) hits 739system.cpu.l2cache.demand_hits::cpu.data 1002124 # number of demand (read+write) hits 740system.cpu.l2cache.demand_hits::total 1918506 # number of demand (read+write) hits 741system.cpu.l2cache.overall_hits::cpu.inst 916382 # number of overall hits 742system.cpu.l2cache.overall_hits::cpu.data 1002124 # number of overall hits 743system.cpu.l2cache.overall_hits::total 1918506 # number of overall hits 744system.cpu.l2cache.UpgradeReq_misses::cpu.data 13 # number of UpgradeReq misses 745system.cpu.l2cache.UpgradeReq_misses::total 13 # number of UpgradeReq misses 746system.cpu.l2cache.ReadExReq_misses::cpu.data 116820 # number of ReadExReq misses 747system.cpu.l2cache.ReadExReq_misses::total 116820 # number of ReadExReq misses 748system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 13200 # number of ReadCleanReq misses 749system.cpu.l2cache.ReadCleanReq_misses::total 13200 # number of ReadCleanReq misses 750system.cpu.l2cache.ReadSharedReq_misses::cpu.data 271971 # number of ReadSharedReq misses 751system.cpu.l2cache.ReadSharedReq_misses::total 271971 # number of ReadSharedReq misses 752system.cpu.l2cache.demand_misses::cpu.inst 13200 # number of demand (read+write) misses 753system.cpu.l2cache.demand_misses::cpu.data 388791 # number of demand (read+write) misses 754system.cpu.l2cache.demand_misses::total 401991 # number of demand (read+write) misses 755system.cpu.l2cache.overall_misses::cpu.inst 13200 # number of overall misses 756system.cpu.l2cache.overall_misses::cpu.data 388791 # number of overall misses 757system.cpu.l2cache.overall_misses::total 401991 # number of overall misses 758system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 315000 # number of UpgradeReq miss cycles 759system.cpu.l2cache.UpgradeReq_miss_latency::total 315000 # number of UpgradeReq miss cycles 760system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14901349500 # number of ReadExReq miss cycles 761system.cpu.l2cache.ReadExReq_miss_latency::total 14901349500 # number of ReadExReq miss cycles 762system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1726796000 # number of ReadCleanReq miss cycles 763system.cpu.l2cache.ReadCleanReq_miss_latency::total 1726796000 # number of ReadCleanReq miss cycles 764system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 33721236500 # number of ReadSharedReq miss cycles 765system.cpu.l2cache.ReadSharedReq_miss_latency::total 33721236500 # number of ReadSharedReq miss cycles 766system.cpu.l2cache.demand_miss_latency::cpu.inst 1726796000 # number of demand (read+write) miss cycles 767system.cpu.l2cache.demand_miss_latency::cpu.data 48622586000 # number of demand (read+write) miss cycles 768system.cpu.l2cache.demand_miss_latency::total 50349382000 # number of demand (read+write) miss cycles 769system.cpu.l2cache.overall_miss_latency::cpu.inst 1726796000 # number of overall miss cycles 770system.cpu.l2cache.overall_miss_latency::cpu.data 48622586000 # number of overall miss cycles 771system.cpu.l2cache.overall_miss_latency::total 50349382000 # number of overall miss cycles 772system.cpu.l2cache.WritebackDirty_accesses::writebacks 834944 # number of WritebackDirty accesses(hits+misses) 773system.cpu.l2cache.WritebackDirty_accesses::total 834944 # number of WritebackDirty accesses(hits+misses) 774system.cpu.l2cache.WritebackClean_accesses::writebacks 928709 # number of WritebackClean accesses(hits+misses) 775system.cpu.l2cache.WritebackClean_accesses::total 928709 # number of WritebackClean accesses(hits+misses) 776system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses) 777system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses) 778system.cpu.l2cache.ReadExReq_accesses::cpu.data 304310 # number of ReadExReq accesses(hits+misses) 779system.cpu.l2cache.ReadExReq_accesses::total 304310 # number of ReadExReq accesses(hits+misses) 780system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 929582 # number of ReadCleanReq accesses(hits+misses) 781system.cpu.l2cache.ReadCleanReq_accesses::total 929582 # number of ReadCleanReq accesses(hits+misses) 782system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1086605 # number of ReadSharedReq accesses(hits+misses) 783system.cpu.l2cache.ReadSharedReq_accesses::total 1086605 # number of ReadSharedReq accesses(hits+misses) 784system.cpu.l2cache.demand_accesses::cpu.inst 929582 # number of demand (read+write) accesses 785system.cpu.l2cache.demand_accesses::cpu.data 1390915 # number of demand (read+write) accesses 786system.cpu.l2cache.demand_accesses::total 2320497 # number of demand (read+write) accesses 787system.cpu.l2cache.overall_accesses::cpu.inst 929582 # number of overall (read+write) accesses 788system.cpu.l2cache.overall_accesses::cpu.data 1390915 # number of overall (read+write) accesses 789system.cpu.l2cache.overall_accesses::total 2320497 # number of overall (read+write) accesses 790system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.764706 # miss rate for UpgradeReq accesses 791system.cpu.l2cache.UpgradeReq_miss_rate::total 0.764706 # miss rate for UpgradeReq accesses 792system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383885 # miss rate for ReadExReq accesses 793system.cpu.l2cache.ReadExReq_miss_rate::total 0.383885 # miss rate for ReadExReq accesses 794system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014200 # miss rate for ReadCleanReq accesses 795system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014200 # miss rate for ReadCleanReq accesses 796system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.250294 # miss rate for ReadSharedReq accesses 797system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.250294 # miss rate for ReadSharedReq accesses 798system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014200 # miss rate for demand accesses 799system.cpu.l2cache.demand_miss_rate::cpu.data 0.279522 # miss rate for demand accesses 800system.cpu.l2cache.demand_miss_rate::total 0.173235 # miss rate for demand accesses 801system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014200 # miss rate for overall accesses 802system.cpu.l2cache.overall_miss_rate::cpu.data 0.279522 # miss rate for overall accesses 803system.cpu.l2cache.overall_miss_rate::total 0.173235 # miss rate for overall accesses 804system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 24230.769231 # average UpgradeReq miss latency 805system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 24230.769231 # average UpgradeReq miss latency 806system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127558.204931 # average ReadExReq miss latency 807system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127558.204931 # average ReadExReq miss latency 808system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130817.878788 # average ReadCleanReq miss latency 809system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130817.878788 # average ReadCleanReq miss latency 810system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123988.353538 # average ReadSharedReq miss latency 811system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123988.353538 # average ReadSharedReq miss latency 812system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130817.878788 # average overall miss latency 813system.cpu.l2cache.demand_avg_miss_latency::cpu.data 125060.986494 # average overall miss latency 814system.cpu.l2cache.demand_avg_miss_latency::total 125250.023010 # average overall miss latency 815system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130817.878788 # average overall miss latency 816system.cpu.l2cache.overall_avg_miss_latency::cpu.data 125060.986494 # average overall miss latency 817system.cpu.l2cache.overall_avg_miss_latency::total 125250.023010 # average overall miss latency 818system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 819system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 820system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 821system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 822system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 823system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 824system.cpu.l2cache.writebacks::writebacks 74281 # number of writebacks 825system.cpu.l2cache.writebacks::total 74281 # number of writebacks 826system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses 827system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses 828system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116820 # number of ReadExReq MSHR misses 829system.cpu.l2cache.ReadExReq_mshr_misses::total 116820 # number of ReadExReq MSHR misses 830system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 13200 # number of ReadCleanReq MSHR misses 831system.cpu.l2cache.ReadCleanReq_mshr_misses::total 13200 # number of ReadCleanReq MSHR misses 832system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 271971 # number of ReadSharedReq MSHR misses 833system.cpu.l2cache.ReadSharedReq_mshr_misses::total 271971 # number of ReadSharedReq MSHR misses 834system.cpu.l2cache.demand_mshr_misses::cpu.inst 13200 # number of demand (read+write) MSHR misses 835system.cpu.l2cache.demand_mshr_misses::cpu.data 388791 # number of demand (read+write) MSHR misses 836system.cpu.l2cache.demand_mshr_misses::total 401991 # number of demand (read+write) MSHR misses 837system.cpu.l2cache.overall_mshr_misses::cpu.inst 13200 # number of overall MSHR misses 838system.cpu.l2cache.overall_mshr_misses::cpu.data 388791 # number of overall MSHR misses 839system.cpu.l2cache.overall_mshr_misses::total 401991 # number of overall MSHR misses 840system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 841system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable 842system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9653 # number of WriteReq MSHR uncacheable 843system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9653 # number of WriteReq MSHR uncacheable 844system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16583 # number of overall MSHR uncacheable misses 845system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16583 # number of overall MSHR uncacheable misses 846system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 893500 # number of UpgradeReq MSHR miss cycles 847system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 893500 # number of UpgradeReq MSHR miss cycles 848system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13733149500 # number of ReadExReq MSHR miss cycles 849system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13733149500 # number of ReadExReq MSHR miss cycles 850system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1594796000 # number of ReadCleanReq MSHR miss cycles 851system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1594796000 # number of ReadCleanReq MSHR miss cycles 852system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31001526500 # number of ReadSharedReq MSHR miss cycles 853system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31001526500 # number of ReadSharedReq MSHR miss cycles 854system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1594796000 # number of demand (read+write) MSHR miss cycles 855system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 44734676000 # number of demand (read+write) MSHR miss cycles 856system.cpu.l2cache.demand_mshr_miss_latency::total 46329472000 # number of demand (read+write) MSHR miss cycles 857system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1594796000 # number of overall MSHR miss cycles 858system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 44734676000 # number of overall MSHR miss cycles 859system.cpu.l2cache.overall_mshr_miss_latency::total 46329472000 # number of overall MSHR miss cycles 860system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1440322500 # number of ReadReq MSHR uncacheable cycles 861system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1440322500 # number of ReadReq MSHR uncacheable cycles 862system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1440322500 # number of overall MSHR uncacheable cycles 863system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1440322500 # number of overall MSHR uncacheable cycles 864system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses 865system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses 866system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383885 # mshr miss rate for ReadExReq accesses 867system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383885 # mshr miss rate for ReadExReq accesses 868system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014200 # mshr miss rate for ReadCleanReq accesses 869system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014200 # mshr miss rate for ReadCleanReq accesses 870system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.250294 # mshr miss rate for ReadSharedReq accesses 871system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.250294 # mshr miss rate for ReadSharedReq accesses 872system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014200 # mshr miss rate for demand accesses 873system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279522 # mshr miss rate for demand accesses 874system.cpu.l2cache.demand_mshr_miss_rate::total 0.173235 # mshr miss rate for demand accesses 875system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014200 # mshr miss rate for overall accesses 876system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279522 # mshr miss rate for overall accesses 877system.cpu.l2cache.overall_mshr_miss_rate::total 0.173235 # mshr miss rate for overall accesses 878system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68730.769231 # average UpgradeReq mshr miss latency 879system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68730.769231 # average UpgradeReq mshr miss latency 880system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117558.204931 # average ReadExReq mshr miss latency 881system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117558.204931 # average ReadExReq mshr miss latency 882system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120817.878788 # average ReadCleanReq mshr miss latency 883system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120817.878788 # average ReadCleanReq mshr miss latency 884system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113988.353538 # average ReadSharedReq mshr miss latency 885system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113988.353538 # average ReadSharedReq mshr miss latency 886system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120817.878788 # average overall mshr miss latency 887system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 115060.986494 # average overall mshr miss latency 888system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115250.023010 # average overall mshr miss latency 889system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120817.878788 # average overall mshr miss latency 890system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 115060.986494 # average overall mshr miss latency 891system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115250.023010 # average overall mshr miss latency 892system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 207838.744589 # average ReadReq mshr uncacheable latency 893system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 207838.744589 # average ReadReq mshr uncacheable latency 894system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86855.363927 # average overall mshr uncacheable latency 895system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 86855.363927 # average overall mshr uncacheable latency 896system.cpu.toL2Bus.snoop_filter.tot_requests 4639867 # Total number of requests made to the snoop filter. 897system.cpu.toL2Bus.snoop_filter.hit_single_requests 2319499 # Number of requests hitting in the snoop filter with a single holder of the requested data. 898system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1502 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 899system.cpu.toL2Bus.snoop_filter.tot_snoops 1136 # Total number of snoops made to the snoop filter. 900system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1136 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 901system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 902system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution 903system.cpu.toL2Bus.trans_dist::ReadResp 2023294 # Transaction distribution 904system.cpu.toL2Bus.trans_dist::WriteReq 9653 # Transaction distribution 905system.cpu.toL2Bus.trans_dist::WriteResp 9653 # Transaction distribution 906system.cpu.toL2Bus.trans_dist::WritebackDirty 950745 # Transaction distribution 907system.cpu.toL2Bus.trans_dist::WritebackClean 928931 # Transaction distribution 908system.cpu.toL2Bus.trans_dist::CleanEvict 817743 # Transaction distribution 909system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution 910system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution 911system.cpu.toL2Bus.trans_dist::ReadExReq 304310 # Transaction distribution 912system.cpu.toL2Bus.trans_dist::ReadExResp 304310 # Transaction distribution 913system.cpu.toL2Bus.trans_dist::ReadCleanReq 929602 # Transaction distribution 914system.cpu.toL2Bus.trans_dist::ReadSharedReq 1086778 # Transaction distribution 915system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution 916system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2788115 # Packet count per connected master and slave (bytes) 917system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4205589 # Packet count per connected master and slave (bytes) 918system.cpu.toL2Bus.pkt_count::total 6993704 # Packet count per connected master and slave (bytes) 919system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 118944832 # Cumulative packet size per connected master and slave (bytes) 920system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142509612 # Cumulative packet size per connected master and slave (bytes) 921system.cpu.toL2Bus.pkt_size::total 261454444 # Cumulative packet size per connected master and slave (bytes) 922system.cpu.toL2Bus.snoops 419988 # Total snoops (count) 923system.cpu.toL2Bus.snoop_fanout::samples 2756928 # Request fanout histogram 924system.cpu.toL2Bus.snoop_fanout::mean 0.001015 # Request fanout histogram 925system.cpu.toL2Bus.snoop_fanout::stdev 0.031847 # Request fanout histogram 926system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 927system.cpu.toL2Bus.snoop_fanout::0 2754129 99.90% 99.90% # Request fanout histogram 928system.cpu.toL2Bus.snoop_fanout::1 2799 0.10% 100.00% # Request fanout histogram 929system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 930system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 931system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 932system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 933system.cpu.toL2Bus.snoop_fanout::total 2756928 # Request fanout histogram 934system.cpu.toL2Bus.reqLayer0.occupancy 4096926500 # Layer occupancy (ticks) 935system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 936system.cpu.toL2Bus.snoopLayer0.occupancy 293383 # Layer occupancy (ticks) 937system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 938system.cpu.toL2Bus.respLayer0.occupancy 1394403000 # Layer occupancy (ticks) 939system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 940system.cpu.toL2Bus.respLayer1.occupancy 2098137500 # Layer occupancy (ticks) 941system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 942system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 943system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 944system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 945system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 946system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 947system.disk0.dma_write_txs 395 # Number of DMA write transactions. 948system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 949system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 950system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 951system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 952system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 953system.disk2.dma_write_txs 1 # Number of DMA write transactions. 954system.iobus.trans_dist::ReadReq 7103 # Transaction distribution 955system.iobus.trans_dist::ReadResp 7103 # Transaction distribution 956system.iobus.trans_dist::WriteReq 51205 # Transaction distribution 957system.iobus.trans_dist::WriteResp 51205 # Transaction distribution 958system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5162 # Packet count per connected master and slave (bytes) 959system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) 960system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 961system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 962system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 963system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) 964system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) 965system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 966system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 967system.iobus.pkt_count_system.bridge.master::total 33166 # Packet count per connected master and slave (bytes) 968system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) 969system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) 970system.iobus.pkt_count::total 116616 # Packet count per connected master and slave (bytes) 971system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20648 # Cumulative packet size per connected master and slave (bytes) 972system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes) 973system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 974system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 975system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 976system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) 977system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) 978system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 979system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 980system.iobus.pkt_size_system.bridge.master::total 44588 # Cumulative packet size per connected master and slave (bytes) 981system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) 982system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) 983system.iobus.pkt_size::total 2706196 # Cumulative packet size per connected master and slave (bytes) 984system.iobus.reqLayer0.occupancy 5340500 # Layer occupancy (ticks) 985system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 986system.iobus.reqLayer1.occupancy 759000 # Layer occupancy (ticks) 987system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 988system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks) 989system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 990system.iobus.reqLayer6.occupancy 10000 # Layer occupancy (ticks) 991system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 992system.iobus.reqLayer22.occupancy 174000 # Layer occupancy (ticks) 993system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 994system.iobus.reqLayer23.occupancy 15817500 # Layer occupancy (ticks) 995system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 996system.iobus.reqLayer24.occupancy 1891500 # Layer occupancy (ticks) 997system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 998system.iobus.reqLayer25.occupancy 6038000 # Layer occupancy (ticks) 999system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1000system.iobus.reqLayer26.occupancy 82500 # Layer occupancy (ticks) 1001system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1002system.iobus.reqLayer27.occupancy 215662167 # Layer occupancy (ticks) 1003system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1004system.iobus.respLayer0.occupancy 23513000 # Layer occupancy (ticks) 1005system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1006system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) 1007system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 1008system.iocache.tags.replacements 41685 # number of replacements 1009system.iocache.tags.tagsinuse 1.339384 # Cycle average of tags in use 1010system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1011system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 1012system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1013system.iocache.tags.warmup_cycle 1774106669000 # Cycle when the warmup percentage was hit. 1014system.iocache.tags.occ_blocks::tsunami.ide 1.339384 # Average occupied blocks per requestor 1015system.iocache.tags.occ_percent::tsunami.ide 0.083712 # Average percentage of cache occupancy 1016system.iocache.tags.occ_percent::total 0.083712 # Average percentage of cache occupancy 1017system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1018system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1019system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1020system.iocache.tags.tag_accesses 375525 # Number of tag accesses 1021system.iocache.tags.data_accesses 375525 # Number of data accesses 1022system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 1023system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 1024system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 1025system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses 1026system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 1027system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 1028system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 1029system.iocache.overall_misses::total 41725 # number of overall misses 1030system.iocache.ReadReq_miss_latency::tsunami.ide 21742883 # number of ReadReq miss cycles 1031system.iocache.ReadReq_miss_latency::total 21742883 # number of ReadReq miss cycles 1032system.iocache.WriteLineReq_miss_latency::tsunami.ide 5244713284 # number of WriteLineReq miss cycles 1033system.iocache.WriteLineReq_miss_latency::total 5244713284 # number of WriteLineReq miss cycles 1034system.iocache.demand_miss_latency::tsunami.ide 5266456167 # number of demand (read+write) miss cycles 1035system.iocache.demand_miss_latency::total 5266456167 # number of demand (read+write) miss cycles 1036system.iocache.overall_miss_latency::tsunami.ide 5266456167 # number of overall miss cycles 1037system.iocache.overall_miss_latency::total 5266456167 # number of overall miss cycles 1038system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 1039system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 1040system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) 1041system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) 1042system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 1043system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 1044system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 1045system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 1046system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 1047system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1048system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses 1049system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1050system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 1051system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1052system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 1053system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1054system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125681.404624 # average ReadReq miss latency 1055system.iocache.ReadReq_avg_miss_latency::total 125681.404624 # average ReadReq miss latency 1056system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126220.477570 # average WriteLineReq miss latency 1057system.iocache.WriteLineReq_avg_miss_latency::total 126220.477570 # average WriteLineReq miss latency 1058system.iocache.demand_avg_miss_latency::tsunami.ide 126218.242469 # average overall miss latency 1059system.iocache.demand_avg_miss_latency::total 126218.242469 # average overall miss latency 1060system.iocache.overall_avg_miss_latency::tsunami.ide 126218.242469 # average overall miss latency 1061system.iocache.overall_avg_miss_latency::total 126218.242469 # average overall miss latency 1062system.iocache.blocked_cycles::no_mshrs 29 # number of cycles access was blocked 1063system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1064system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked 1065system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1066system.iocache.avg_blocked_cycles::no_mshrs 14.500000 # average number of cycles each access was blocked 1067system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1068system.iocache.writebacks::writebacks 41512 # number of writebacks 1069system.iocache.writebacks::total 41512 # number of writebacks 1070system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 1071system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 1072system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses 1073system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses 1074system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 1075system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 1076system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 1077system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses 1078system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13092883 # number of ReadReq MSHR miss cycles 1079system.iocache.ReadReq_mshr_miss_latency::total 13092883 # number of ReadReq MSHR miss cycles 1080system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3165314984 # number of WriteLineReq MSHR miss cycles 1081system.iocache.WriteLineReq_mshr_miss_latency::total 3165314984 # number of WriteLineReq MSHR miss cycles 1082system.iocache.demand_mshr_miss_latency::tsunami.ide 3178407867 # number of demand (read+write) MSHR miss cycles 1083system.iocache.demand_mshr_miss_latency::total 3178407867 # number of demand (read+write) MSHR miss cycles 1084system.iocache.overall_mshr_miss_latency::tsunami.ide 3178407867 # number of overall MSHR miss cycles 1085system.iocache.overall_mshr_miss_latency::total 3178407867 # number of overall MSHR miss cycles 1086system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 1087system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1088system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses 1089system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1090system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 1091system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1092system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 1093system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1094system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75681.404624 # average ReadReq mshr miss latency 1095system.iocache.ReadReq_avg_mshr_miss_latency::total 75681.404624 # average ReadReq mshr miss latency 1096system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76177.199268 # average WriteLineReq mshr miss latency 1097system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76177.199268 # average WriteLineReq mshr miss latency 1098system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76175.143607 # average overall mshr miss latency 1099system.iocache.demand_avg_mshr_miss_latency::total 76175.143607 # average overall mshr miss latency 1100system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76175.143607 # average overall mshr miss latency 1101system.iocache.overall_avg_mshr_miss_latency::total 76175.143607 # average overall mshr miss latency 1102system.membus.trans_dist::ReadReq 6930 # Transaction distribution 1103system.membus.trans_dist::ReadResp 292274 # Transaction distribution 1104system.membus.trans_dist::WriteReq 9653 # Transaction distribution 1105system.membus.trans_dist::WriteResp 9653 # Transaction distribution 1106system.membus.trans_dist::WritebackDirty 115793 # Transaction distribution 1107system.membus.trans_dist::CleanEvict 261560 # Transaction distribution 1108system.membus.trans_dist::UpgradeReq 150 # Transaction distribution 1109system.membus.trans_dist::UpgradeResp 2 # Transaction distribution 1110system.membus.trans_dist::ReadExReq 116683 # Transaction distribution 1111system.membus.trans_dist::ReadExResp 116683 # Transaction distribution 1112system.membus.trans_dist::ReadSharedReq 285344 # Transaction distribution 1113system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution 1114system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33166 # Packet count per connected master and slave (bytes) 1115system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1139255 # Packet count per connected master and slave (bytes) 1116system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1172421 # Packet count per connected master and slave (bytes) 1117system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes) 1118system.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes) 1119system.membus.pkt_count::total 1255846 # Packet count per connected master and slave (bytes) 1120system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44588 # Cumulative packet size per connected master and slave (bytes) 1121system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30455296 # Cumulative packet size per connected master and slave (bytes) 1122system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30499884 # Cumulative packet size per connected master and slave (bytes) 1123system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) 1124system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) 1125system.membus.pkt_size::total 33157612 # Cumulative packet size per connected master and slave (bytes) 1126system.membus.snoops 431 # Total snoops (count) 1127system.membus.snoop_fanout::samples 837673 # Request fanout histogram 1128system.membus.snoop_fanout::mean 1 # Request fanout histogram 1129system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1130system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1131system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1132system.membus.snoop_fanout::1 837673 100.00% 100.00% # Request fanout histogram 1133system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1134system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1135system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1136system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1137system.membus.snoop_fanout::total 837673 # Request fanout histogram 1138system.membus.reqLayer0.occupancy 30122500 # Layer occupancy (ticks) 1139system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1140system.membus.reqLayer1.occupancy 1287200967 # Layer occupancy (ticks) 1141system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 1142system.membus.respLayer1.occupancy 2143013000 # Layer occupancy (ticks) 1143system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 1144system.membus.respLayer2.occupancy 887117 # Layer occupancy (ticks) 1145system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1146system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1147system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1148system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1149system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1150system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1151system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1152system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 1153system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1154system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 1155system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1156system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1157system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 1158system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1159system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1160system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 1161system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1162system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1163system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 1164system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1165system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1166system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 1167system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1168system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1169system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1170system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1171system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1172system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1173system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1174system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1175system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 1176system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 1177 1178---------- End Simulation Statistics ---------- 1179