stats.txt revision 11245:1c5102c0a7a9
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.941276 # Number of seconds simulated 4sim_ticks 1941275996000 # Number of ticks simulated 5final_tick 1941275996000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 921196 # Simulator instruction rate (inst/s) 8host_op_rate 921196 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 31829968739 # Simulator tick rate (ticks/s) 10host_mem_usage 330408 # Number of bytes of host memory used 11host_seconds 60.99 # Real time elapsed on the host 12sim_insts 56182743 # Number of instructions simulated 13sim_ops 56182743 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 844800 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24856512 # Number of bytes read from this memory 18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 19system.physmem.bytes_read::total 25702272 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 844800 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 844800 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 7410752 # Number of bytes written to this memory 23system.physmem.bytes_written::total 7410752 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 13200 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 388383 # Number of read requests responded to by this memory 26system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory 27system.physmem.num_reads::total 401598 # Number of read requests responded to by this memory 28system.physmem.num_writes::writebacks 115793 # Number of write requests responded to by this memory 29system.physmem.num_writes::total 115793 # Number of write requests responded to by this memory 30system.physmem.bw_read::cpu.inst 435178 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::cpu.data 12804213 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::tsunami.ide 495 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::total 13239886 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_inst_read::cpu.inst 435178 # Instruction read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::total 435178 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_write::writebacks 3817464 # Write bandwidth from this memory (bytes/s) 37system.physmem.bw_write::total 3817464 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_total::writebacks 3817464 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::cpu.inst 435178 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.data 12804213 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::tsunami.ide 495 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::total 17057350 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.readReqs 401598 # Number of read requests accepted 44system.physmem.writeReqs 115793 # Number of write requests accepted 45system.physmem.readBursts 401598 # Number of DRAM read bursts, including those serviced by the write queue 46system.physmem.writeBursts 115793 # Number of DRAM write bursts, including those merged in the write queue 47system.physmem.bytesReadDRAM 25694784 # Total number of bytes read from DRAM 48system.physmem.bytesReadWrQ 7488 # Total number of bytes read from write queue 49system.physmem.bytesWritten 7408704 # Total number of bytes written to DRAM 50system.physmem.bytesReadSys 25702272 # Total read bytes from the system interface side 51system.physmem.bytesWrittenSys 7410752 # Total written bytes from the system interface side 52system.physmem.servicedByWrQ 117 # Number of DRAM read bursts serviced by the write queue 53system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 54system.physmem.neitherReadNorWriteReqs 303100 # Number of requests that are neither read nor write 55system.physmem.perBankRdBursts::0 25225 # Per bank write bursts 56system.physmem.perBankRdBursts::1 25628 # Per bank write bursts 57system.physmem.perBankRdBursts::2 25541 # Per bank write bursts 58system.physmem.perBankRdBursts::3 25494 # Per bank write bursts 59system.physmem.perBankRdBursts::4 25069 # Per bank write bursts 60system.physmem.perBankRdBursts::5 24955 # Per bank write bursts 61system.physmem.perBankRdBursts::6 24242 # Per bank write bursts 62system.physmem.perBankRdBursts::7 24604 # Per bank write bursts 63system.physmem.perBankRdBursts::8 25085 # Per bank write bursts 64system.physmem.perBankRdBursts::9 24651 # Per bank write bursts 65system.physmem.perBankRdBursts::10 25269 # Per bank write bursts 66system.physmem.perBankRdBursts::11 24875 # Per bank write bursts 67system.physmem.perBankRdBursts::12 24508 # Per bank write bursts 68system.physmem.perBankRdBursts::13 25360 # Per bank write bursts 69system.physmem.perBankRdBursts::14 25616 # Per bank write bursts 70system.physmem.perBankRdBursts::15 25359 # Per bank write bursts 71system.physmem.perBankWrBursts::0 7625 # Per bank write bursts 72system.physmem.perBankWrBursts::1 7638 # Per bank write bursts 73system.physmem.perBankWrBursts::2 7842 # Per bank write bursts 74system.physmem.perBankWrBursts::3 7532 # Per bank write bursts 75system.physmem.perBankWrBursts::4 7224 # Per bank write bursts 76system.physmem.perBankWrBursts::5 6973 # Per bank write bursts 77system.physmem.perBankWrBursts::6 6356 # Per bank write bursts 78system.physmem.perBankWrBursts::7 6427 # Per bank write bursts 79system.physmem.perBankWrBursts::8 7248 # Per bank write bursts 80system.physmem.perBankWrBursts::9 6409 # Per bank write bursts 81system.physmem.perBankWrBursts::10 7117 # Per bank write bursts 82system.physmem.perBankWrBursts::11 6905 # Per bank write bursts 83system.physmem.perBankWrBursts::12 7093 # Per bank write bursts 84system.physmem.perBankWrBursts::13 7822 # Per bank write bursts 85system.physmem.perBankWrBursts::14 7863 # Per bank write bursts 86system.physmem.perBankWrBursts::15 7687 # Per bank write bursts 87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 88system.physmem.numWrRetry 16 # Number of times write queue was full causing retry 89system.physmem.totGap 1941264122500 # Total gap between requests 90system.physmem.readPktSize::0 0 # Read request sizes (log2) 91system.physmem.readPktSize::1 0 # Read request sizes (log2) 92system.physmem.readPktSize::2 0 # Read request sizes (log2) 93system.physmem.readPktSize::3 0 # Read request sizes (log2) 94system.physmem.readPktSize::4 0 # Read request sizes (log2) 95system.physmem.readPktSize::5 0 # Read request sizes (log2) 96system.physmem.readPktSize::6 401598 # Read request sizes (log2) 97system.physmem.writePktSize::0 0 # Write request sizes (log2) 98system.physmem.writePktSize::1 0 # Write request sizes (log2) 99system.physmem.writePktSize::2 0 # Write request sizes (log2) 100system.physmem.writePktSize::3 0 # Write request sizes (log2) 101system.physmem.writePktSize::4 0 # Write request sizes (log2) 102system.physmem.writePktSize::5 0 # Write request sizes (log2) 103system.physmem.writePktSize::6 115793 # Write request sizes (log2) 104system.physmem.rdQLenPdf::0 401467 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::1 1 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 136system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::15 1810 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::16 2178 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::17 5487 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::18 5490 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::19 6052 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::20 6389 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::21 5822 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::22 6245 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::23 7624 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::24 8044 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::25 9020 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::26 8199 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::27 8442 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::28 7229 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::29 6622 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::30 6009 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::31 5554 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::32 5298 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::33 207 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::34 172 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::35 177 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::36 248 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::37 163 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::38 145 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::39 137 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::40 120 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::41 222 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::42 197 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::43 167 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::44 118 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::45 124 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::46 185 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::47 144 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::48 211 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::49 134 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::50 146 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::51 138 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::52 101 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::53 157 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::54 176 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::55 99 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::56 127 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::57 65 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::58 92 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::59 100 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::60 62 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::61 55 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::62 24 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::63 51 # What write queue length does an incoming req see 200system.physmem.bytesPerActivate::samples 64945 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::mean 509.715729 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::gmean 310.174215 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::stdev 406.042967 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::0-127 15358 23.65% 23.65% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::128-255 11454 17.64% 41.28% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::256-383 4958 7.63% 48.92% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::384-511 3153 4.85% 53.77% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::512-639 2453 3.78% 57.55% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::640-767 4205 6.47% 64.02% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::768-895 1430 2.20% 66.23% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-1023 2063 3.18% 69.40% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1024-1151 19871 30.60% 100.00% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::total 64945 # Bytes accessed per row activation 214system.physmem.rdPerTurnAround::samples 5113 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::mean 78.517700 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::stdev 2951.127633 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::0-8191 5110 99.94% 99.94% # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes 221system.physmem.rdPerTurnAround::total 5113 # Reads before turning the bus around for writes 222system.physmem.wrPerTurnAround::samples 5113 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::mean 22.640524 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::gmean 19.158069 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::stdev 21.669047 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::16-19 4483 87.68% 87.68% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::20-23 26 0.51% 88.19% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::24-27 11 0.22% 88.40% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::28-31 181 3.54% 91.94% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::32-35 5 0.10% 92.04% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::36-39 20 0.39% 92.43% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::40-43 39 0.76% 93.19% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::44-47 6 0.12% 93.31% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::48-51 12 0.23% 93.55% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::52-55 31 0.61% 94.15% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::56-59 3 0.06% 94.21% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::60-63 3 0.06% 94.27% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::64-67 9 0.18% 94.45% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::68-71 1 0.02% 94.47% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::72-75 22 0.43% 94.90% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::76-79 27 0.53% 95.42% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::80-83 2 0.04% 95.46% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::84-87 26 0.51% 95.97% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::92-95 3 0.06% 96.03% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::100-103 161 3.15% 99.18% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::104-107 1 0.02% 99.20% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::124-127 1 0.02% 99.22% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::128-131 5 0.10% 99.32% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::136-139 1 0.02% 99.34% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::140-143 2 0.04% 99.37% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::156-159 3 0.06% 99.43% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::160-163 1 0.02% 99.45% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::164-167 4 0.08% 99.53% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::168-171 4 0.08% 99.61% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::180-183 11 0.22% 99.82% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::188-191 5 0.10% 99.92% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::192-195 1 0.02% 99.94% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::200-203 1 0.02% 99.96% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::212-215 1 0.02% 99.98% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::228-231 1 0.02% 100.00% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::total 5113 # Writes before turning the bus around for reads 262system.physmem.totQLat 2718840250 # Total ticks spent queuing 263system.physmem.totMemAccLat 10246609000 # Total ticks spent from burst creation until serviced by the DRAM 264system.physmem.totBusLat 2007405000 # Total ticks spent in databus transfers 265system.physmem.avgQLat 6772.03 # Average queueing delay per DRAM burst 266system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 267system.physmem.avgMemAccLat 25522.03 # Average memory access latency per DRAM burst 268system.physmem.avgRdBW 13.24 # Average DRAM read bandwidth in MiByte/s 269system.physmem.avgWrBW 3.82 # Average achieved write bandwidth in MiByte/s 270system.physmem.avgRdBWSys 13.24 # Average system read bandwidth in MiByte/s 271system.physmem.avgWrBWSys 3.82 # Average system write bandwidth in MiByte/s 272system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 273system.physmem.busUtil 0.13 # Data bus utilization in percentage 274system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads 275system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 276system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 277system.physmem.avgWrQLen 22.09 # Average write queue length when enqueuing 278system.physmem.readRowHits 358828 # Number of row buffer hits during reads 279system.physmem.writeRowHits 93469 # Number of row buffer hits during writes 280system.physmem.readRowHitRate 89.38 # Row buffer hit rate for reads 281system.physmem.writeRowHitRate 80.72 # Row buffer hit rate for writes 282system.physmem.avgGap 3752025.30 # Average gap between requests 283system.physmem.pageHitRate 87.44 # Row buffer hit rate, read and write combined 284system.physmem_0.actEnergy 240377760 # Energy for activate commands per rank (pJ) 285system.physmem_0.preEnergy 131158500 # Energy for precharge commands per rank (pJ) 286system.physmem_0.readEnergy 1565912400 # Energy for read commands per rank (pJ) 287system.physmem_0.writeEnergy 373358160 # Energy for write commands per rank (pJ) 288system.physmem_0.refreshEnergy 126794687760 # Energy for refresh commands per rank (pJ) 289system.physmem_0.actBackEnergy 71534855790 # Energy for active background per rank (pJ) 290system.physmem_0.preBackEnergy 1102015656000 # Energy for precharge background per rank (pJ) 291system.physmem_0.totalEnergy 1302656006370 # Total energy per rank (pJ) 292system.physmem_0.averagePower 671.030850 # Core power per rank (mW) 293system.physmem_0.memoryStateTime::IDLE 1833021874000 # Time in different power states 294system.physmem_0.memoryStateTime::REF 64823460000 # Time in different power states 295system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 296system.physmem_0.memoryStateTime::ACT 43430562250 # Time in different power states 297system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 298system.physmem_1.actEnergy 250606440 # Energy for activate commands per rank (pJ) 299system.physmem_1.preEnergy 136739625 # Energy for precharge commands per rank (pJ) 300system.physmem_1.readEnergy 1565639400 # Energy for read commands per rank (pJ) 301system.physmem_1.writeEnergy 376773120 # Energy for write commands per rank (pJ) 302system.physmem_1.refreshEnergy 126794687760 # Energy for refresh commands per rank (pJ) 303system.physmem_1.actBackEnergy 72705843270 # Energy for active background per rank (pJ) 304system.physmem_1.preBackEnergy 1100988474000 # Energy for precharge background per rank (pJ) 305system.physmem_1.totalEnergy 1302818763615 # Total energy per rank (pJ) 306system.physmem_1.averagePower 671.114691 # Core power per rank (mW) 307system.physmem_1.memoryStateTime::IDLE 1831312114000 # Time in different power states 308system.physmem_1.memoryStateTime::REF 64823460000 # Time in different power states 309system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 310system.physmem_1.memoryStateTime::ACT 45140322250 # Time in different power states 311system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 312system.cpu_clk_domain.clock 500 # Clock period in ticks 313system.cpu.dtb.fetch_hits 0 # ITB hits 314system.cpu.dtb.fetch_misses 0 # ITB misses 315system.cpu.dtb.fetch_acv 0 # ITB acv 316system.cpu.dtb.fetch_accesses 0 # ITB accesses 317system.cpu.dtb.read_hits 9064657 # DTB read hits 318system.cpu.dtb.read_misses 10324 # DTB read misses 319system.cpu.dtb.read_acv 210 # DTB read access violations 320system.cpu.dtb.read_accesses 728853 # DTB read accesses 321system.cpu.dtb.write_hits 6356207 # DTB write hits 322system.cpu.dtb.write_misses 1142 # DTB write misses 323system.cpu.dtb.write_acv 157 # DTB write access violations 324system.cpu.dtb.write_accesses 291931 # DTB write accesses 325system.cpu.dtb.data_hits 15420864 # DTB hits 326system.cpu.dtb.data_misses 11466 # DTB misses 327system.cpu.dtb.data_acv 367 # DTB access violations 328system.cpu.dtb.data_accesses 1020784 # DTB accesses 329system.cpu.itb.fetch_hits 4975134 # ITB hits 330system.cpu.itb.fetch_misses 5010 # ITB misses 331system.cpu.itb.fetch_acv 184 # ITB acv 332system.cpu.itb.fetch_accesses 4980144 # ITB accesses 333system.cpu.itb.read_hits 0 # DTB read hits 334system.cpu.itb.read_misses 0 # DTB read misses 335system.cpu.itb.read_acv 0 # DTB read access violations 336system.cpu.itb.read_accesses 0 # DTB read accesses 337system.cpu.itb.write_hits 0 # DTB write hits 338system.cpu.itb.write_misses 0 # DTB write misses 339system.cpu.itb.write_acv 0 # DTB write access violations 340system.cpu.itb.write_accesses 0 # DTB write accesses 341system.cpu.itb.data_hits 0 # DTB hits 342system.cpu.itb.data_misses 0 # DTB misses 343system.cpu.itb.data_acv 0 # DTB access violations 344system.cpu.itb.data_accesses 0 # DTB accesses 345system.cpu.numCycles 3882551992 # number of cpu cycles simulated 346system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 347system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 348system.cpu.kern.inst.arm 0 # number of arm instructions executed 349system.cpu.kern.inst.quiesce 6375 # number of quiesce instructions executed 350system.cpu.kern.inst.hwrei 212050 # number of hwrei instructions executed 351system.cpu.kern.ipl_count::0 74912 40.88% 40.88% # number of times we switched to this ipl 352system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl 353system.cpu.kern.ipl_count::22 1935 1.06% 42.01% # number of times we switched to this ipl 354system.cpu.kern.ipl_count::31 106253 57.99% 100.00% # number of times we switched to this ipl 355system.cpu.kern.ipl_count::total 183231 # number of times we switched to this ipl 356system.cpu.kern.ipl_good::0 73545 49.31% 49.31% # number of times we switched to this ipl from a different ipl 357system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl 358system.cpu.kern.ipl_good::22 1935 1.30% 50.69% # number of times we switched to this ipl from a different ipl 359system.cpu.kern.ipl_good::31 73545 49.31% 100.00% # number of times we switched to this ipl from a different ipl 360system.cpu.kern.ipl_good::total 149156 # number of times we switched to this ipl from a different ipl 361system.cpu.kern.ipl_ticks::0 1860509805500 95.84% 95.84% # number of cycles we spent at this ipl 362system.cpu.kern.ipl_ticks::21 94040000 0.00% 95.84% # number of cycles we spent at this ipl 363system.cpu.kern.ipl_ticks::22 770515500 0.04% 95.88% # number of cycles we spent at this ipl 364system.cpu.kern.ipl_ticks::31 79900901000 4.12% 100.00% # number of cycles we spent at this ipl 365system.cpu.kern.ipl_ticks::total 1941275262000 # number of cycles we spent at this ipl 366system.cpu.kern.ipl_used::0 0.981752 # fraction of swpipl calls that actually changed the ipl 367system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 368system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 369system.cpu.kern.ipl_used::31 0.692169 # fraction of swpipl calls that actually changed the ipl 370system.cpu.kern.ipl_used::total 0.814033 # fraction of swpipl calls that actually changed the ipl 371system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 372system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 373system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 374system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 375system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 376system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 377system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 378system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed 379system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed 380system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed 381system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed 382system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed 383system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed 384system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed 385system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed 386system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed 387system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed 388system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed 389system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed 390system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed 391system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed 392system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed 393system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed 394system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed 395system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed 396system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed 397system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed 398system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 399system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 400system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 401system.cpu.kern.syscall::total 326 # number of syscalls executed 402system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 403system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 404system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 405system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 406system.cpu.kern.callpal::swpctx 4176 2.16% 2.17% # number of callpals executed 407system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed 408system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed 409system.cpu.kern.callpal::swpipl 176004 91.22% 93.41% # number of callpals executed 410system.cpu.kern.callpal::rdps 6835 3.54% 96.96% # number of callpals executed 411system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed 412system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed 413system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed 414system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed 415system.cpu.kern.callpal::rti 5160 2.67% 99.64% # number of callpals executed 416system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 417system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed 418system.cpu.kern.callpal::total 192955 # number of callpals executed 419system.cpu.kern.mode_switch::kernel 5908 # number of protection mode switches 420system.cpu.kern.mode_switch::user 1739 # number of protection mode switches 421system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches 422system.cpu.kern.mode_good::kernel 1909 423system.cpu.kern.mode_good::user 1739 424system.cpu.kern.mode_good::idle 170 425system.cpu.kern.mode_switch_good::kernel 0.323121 # fraction of useful protection mode switches 426system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 427system.cpu.kern.mode_switch_good::idle 0.081184 # fraction of useful protection mode switches 428system.cpu.kern.mode_switch_good::total 0.391952 # fraction of useful protection mode switches 429system.cpu.kern.mode_ticks::kernel 48611852500 2.50% 2.50% # number of ticks spent at the given mode 430system.cpu.kern.mode_ticks::user 5602941000 0.29% 2.79% # number of ticks spent at the given mode 431system.cpu.kern.mode_ticks::idle 1887060466500 97.21% 100.00% # number of ticks spent at the given mode 432system.cpu.kern.swap_context 4177 # number of times the context was actually changed 433system.cpu.committedInsts 56182743 # Number of instructions committed 434system.cpu.committedOps 56182743 # Number of ops (including micro ops) committed 435system.cpu.num_int_alu_accesses 52054633 # Number of integer alu accesses 436system.cpu.num_fp_alu_accesses 324393 # Number of float alu accesses 437system.cpu.num_func_calls 1483394 # number of times a function call or return occured 438system.cpu.num_conditional_control_insts 6468678 # number of instructions that are conditional controls 439system.cpu.num_int_insts 52054633 # number of integer instructions 440system.cpu.num_fp_insts 324393 # number of float instructions 441system.cpu.num_int_register_reads 71322499 # number of times the integer registers were read 442system.cpu.num_int_register_writes 38520900 # number of times the integer registers were written 443system.cpu.num_fp_register_reads 163609 # number of times the floating registers were read 444system.cpu.num_fp_register_writes 166486 # number of times the floating registers were written 445system.cpu.num_mem_refs 15473474 # number of memory refs 446system.cpu.num_load_insts 9101503 # Number of load instructions 447system.cpu.num_store_insts 6371971 # Number of store instructions 448system.cpu.num_idle_cycles 3583834697.998154 # Number of idle cycles 449system.cpu.num_busy_cycles 298717294.001846 # Number of busy cycles 450system.cpu.not_idle_fraction 0.076938 # Percentage of non-idle cycles 451system.cpu.idle_fraction 0.923062 # Percentage of idle cycles 452system.cpu.Branches 8422724 # Number of branches fetched 453system.cpu.op_class::No_OpClass 3200638 5.70% 5.70% # Class of executed instruction 454system.cpu.op_class::IntAlu 36231019 64.47% 70.17% # Class of executed instruction 455system.cpu.op_class::IntMult 61043 0.11% 70.28% # Class of executed instruction 456system.cpu.op_class::IntDiv 0 0.00% 70.28% # Class of executed instruction 457system.cpu.op_class::FloatAdd 38085 0.07% 70.35% # Class of executed instruction 458system.cpu.op_class::FloatCmp 0 0.00% 70.35% # Class of executed instruction 459system.cpu.op_class::FloatCvt 0 0.00% 70.35% # Class of executed instruction 460system.cpu.op_class::FloatMult 0 0.00% 70.35% # Class of executed instruction 461system.cpu.op_class::FloatDiv 3636 0.01% 70.35% # Class of executed instruction 462system.cpu.op_class::FloatSqrt 0 0.00% 70.35% # Class of executed instruction 463system.cpu.op_class::SimdAdd 0 0.00% 70.35% # Class of executed instruction 464system.cpu.op_class::SimdAddAcc 0 0.00% 70.35% # Class of executed instruction 465system.cpu.op_class::SimdAlu 0 0.00% 70.35% # Class of executed instruction 466system.cpu.op_class::SimdCmp 0 0.00% 70.35% # Class of executed instruction 467system.cpu.op_class::SimdCvt 0 0.00% 70.35% # Class of executed instruction 468system.cpu.op_class::SimdMisc 0 0.00% 70.35% # Class of executed instruction 469system.cpu.op_class::SimdMult 0 0.00% 70.35% # Class of executed instruction 470system.cpu.op_class::SimdMultAcc 0 0.00% 70.35% # Class of executed instruction 471system.cpu.op_class::SimdShift 0 0.00% 70.35% # Class of executed instruction 472system.cpu.op_class::SimdShiftAcc 0 0.00% 70.35% # Class of executed instruction 473system.cpu.op_class::SimdSqrt 0 0.00% 70.35% # Class of executed instruction 474system.cpu.op_class::SimdFloatAdd 0 0.00% 70.35% # Class of executed instruction 475system.cpu.op_class::SimdFloatAlu 0 0.00% 70.35% # Class of executed instruction 476system.cpu.op_class::SimdFloatCmp 0 0.00% 70.35% # Class of executed instruction 477system.cpu.op_class::SimdFloatCvt 0 0.00% 70.35% # Class of executed instruction 478system.cpu.op_class::SimdFloatDiv 0 0.00% 70.35% # Class of executed instruction 479system.cpu.op_class::SimdFloatMisc 0 0.00% 70.35% # Class of executed instruction 480system.cpu.op_class::SimdFloatMult 0 0.00% 70.35% # Class of executed instruction 481system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.35% # Class of executed instruction 482system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.35% # Class of executed instruction 483system.cpu.op_class::MemRead 9328633 16.60% 86.95% # Class of executed instruction 484system.cpu.op_class::MemWrite 6378052 11.35% 98.30% # Class of executed instruction 485system.cpu.op_class::IprAccess 953470 1.70% 100.00% # Class of executed instruction 486system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 487system.cpu.op_class::total 56194576 # Class of executed instruction 488system.cpu.dcache.tags.replacements 1390387 # number of replacements 489system.cpu.dcache.tags.tagsinuse 511.973391 # Cycle average of tags in use 490system.cpu.dcache.tags.total_refs 14048998 # Total number of references to valid blocks. 491system.cpu.dcache.tags.sampled_refs 1390899 # Sample count of references to valid blocks. 492system.cpu.dcache.tags.avg_refs 10.100660 # Average number of references to valid blocks. 493system.cpu.dcache.tags.warmup_cycle 145150500 # Cycle when the warmup percentage was hit. 494system.cpu.dcache.tags.occ_blocks::cpu.data 511.973391 # Average occupied blocks per requestor 495system.cpu.dcache.tags.occ_percent::cpu.data 0.999948 # Average percentage of cache occupancy 496system.cpu.dcache.tags.occ_percent::total 0.999948 # Average percentage of cache occupancy 497system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 498system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id 499system.cpu.dcache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id 500system.cpu.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id 501system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 502system.cpu.dcache.tags.tag_accesses 63150492 # Number of tag accesses 503system.cpu.dcache.tags.data_accesses 63150492 # Number of data accesses 504system.cpu.dcache.ReadReq_hits::cpu.data 7814415 # number of ReadReq hits 505system.cpu.dcache.ReadReq_hits::total 7814415 # number of ReadReq hits 506system.cpu.dcache.WriteReq_hits::cpu.data 5852271 # number of WriteReq hits 507system.cpu.dcache.WriteReq_hits::total 5852271 # number of WriteReq hits 508system.cpu.dcache.LoadLockedReq_hits::cpu.data 183035 # number of LoadLockedReq hits 509system.cpu.dcache.LoadLockedReq_hits::total 183035 # number of LoadLockedReq hits 510system.cpu.dcache.StoreCondReq_hits::cpu.data 199260 # number of StoreCondReq hits 511system.cpu.dcache.StoreCondReq_hits::total 199260 # number of StoreCondReq hits 512system.cpu.dcache.demand_hits::cpu.data 13666686 # number of demand (read+write) hits 513system.cpu.dcache.demand_hits::total 13666686 # number of demand (read+write) hits 514system.cpu.dcache.overall_hits::cpu.data 13666686 # number of overall hits 515system.cpu.dcache.overall_hits::total 13666686 # number of overall hits 516system.cpu.dcache.ReadReq_misses::cpu.data 1069342 # number of ReadReq misses 517system.cpu.dcache.ReadReq_misses::total 1069342 # number of ReadReq misses 518system.cpu.dcache.WriteReq_misses::cpu.data 304328 # number of WriteReq misses 519system.cpu.dcache.WriteReq_misses::total 304328 # number of WriteReq misses 520system.cpu.dcache.LoadLockedReq_misses::cpu.data 17247 # number of LoadLockedReq misses 521system.cpu.dcache.LoadLockedReq_misses::total 17247 # number of LoadLockedReq misses 522system.cpu.dcache.demand_misses::cpu.data 1373670 # number of demand (read+write) misses 523system.cpu.dcache.demand_misses::total 1373670 # number of demand (read+write) misses 524system.cpu.dcache.overall_misses::cpu.data 1373670 # number of overall misses 525system.cpu.dcache.overall_misses::total 1373670 # number of overall misses 526system.cpu.dcache.ReadReq_miss_latency::cpu.data 44771016500 # number of ReadReq miss cycles 527system.cpu.dcache.ReadReq_miss_latency::total 44771016500 # number of ReadReq miss cycles 528system.cpu.dcache.WriteReq_miss_latency::cpu.data 17634519000 # number of WriteReq miss cycles 529system.cpu.dcache.WriteReq_miss_latency::total 17634519000 # number of WriteReq miss cycles 530system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 232810500 # number of LoadLockedReq miss cycles 531system.cpu.dcache.LoadLockedReq_miss_latency::total 232810500 # number of LoadLockedReq miss cycles 532system.cpu.dcache.demand_miss_latency::cpu.data 62405535500 # number of demand (read+write) miss cycles 533system.cpu.dcache.demand_miss_latency::total 62405535500 # number of demand (read+write) miss cycles 534system.cpu.dcache.overall_miss_latency::cpu.data 62405535500 # number of overall miss cycles 535system.cpu.dcache.overall_miss_latency::total 62405535500 # number of overall miss cycles 536system.cpu.dcache.ReadReq_accesses::cpu.data 8883757 # number of ReadReq accesses(hits+misses) 537system.cpu.dcache.ReadReq_accesses::total 8883757 # number of ReadReq accesses(hits+misses) 538system.cpu.dcache.WriteReq_accesses::cpu.data 6156599 # number of WriteReq accesses(hits+misses) 539system.cpu.dcache.WriteReq_accesses::total 6156599 # number of WriteReq accesses(hits+misses) 540system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200282 # number of LoadLockedReq accesses(hits+misses) 541system.cpu.dcache.LoadLockedReq_accesses::total 200282 # number of LoadLockedReq accesses(hits+misses) 542system.cpu.dcache.StoreCondReq_accesses::cpu.data 199260 # number of StoreCondReq accesses(hits+misses) 543system.cpu.dcache.StoreCondReq_accesses::total 199260 # number of StoreCondReq accesses(hits+misses) 544system.cpu.dcache.demand_accesses::cpu.data 15040356 # number of demand (read+write) accesses 545system.cpu.dcache.demand_accesses::total 15040356 # number of demand (read+write) accesses 546system.cpu.dcache.overall_accesses::cpu.data 15040356 # number of overall (read+write) accesses 547system.cpu.dcache.overall_accesses::total 15040356 # number of overall (read+write) accesses 548system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120370 # miss rate for ReadReq accesses 549system.cpu.dcache.ReadReq_miss_rate::total 0.120370 # miss rate for ReadReq accesses 550system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049431 # miss rate for WriteReq accesses 551system.cpu.dcache.WriteReq_miss_rate::total 0.049431 # miss rate for WriteReq accesses 552system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086114 # miss rate for LoadLockedReq accesses 553system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086114 # miss rate for LoadLockedReq accesses 554system.cpu.dcache.demand_miss_rate::cpu.data 0.091332 # miss rate for demand accesses 555system.cpu.dcache.demand_miss_rate::total 0.091332 # miss rate for demand accesses 556system.cpu.dcache.overall_miss_rate::cpu.data 0.091332 # miss rate for overall accesses 557system.cpu.dcache.overall_miss_rate::total 0.091332 # miss rate for overall accesses 558system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41867.818247 # average ReadReq miss latency 559system.cpu.dcache.ReadReq_avg_miss_latency::total 41867.818247 # average ReadReq miss latency 560system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57945.765753 # average WriteReq miss latency 561system.cpu.dcache.WriteReq_avg_miss_latency::total 57945.765753 # average WriteReq miss latency 562system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13498.608454 # average LoadLockedReq miss latency 563system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13498.608454 # average LoadLockedReq miss latency 564system.cpu.dcache.demand_avg_miss_latency::cpu.data 45429.786994 # average overall miss latency 565system.cpu.dcache.demand_avg_miss_latency::total 45429.786994 # average overall miss latency 566system.cpu.dcache.overall_avg_miss_latency::cpu.data 45429.786994 # average overall miss latency 567system.cpu.dcache.overall_avg_miss_latency::total 45429.786994 # average overall miss latency 568system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 569system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 570system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 571system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 572system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 573system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 574system.cpu.dcache.fast_writes 0 # number of fast writes performed 575system.cpu.dcache.cache_copies 0 # number of cache copies performed 576system.cpu.dcache.writebacks::writebacks 834936 # number of writebacks 577system.cpu.dcache.writebacks::total 834936 # number of writebacks 578system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069342 # number of ReadReq MSHR misses 579system.cpu.dcache.ReadReq_mshr_misses::total 1069342 # number of ReadReq MSHR misses 580system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304328 # number of WriteReq MSHR misses 581system.cpu.dcache.WriteReq_mshr_misses::total 304328 # number of WriteReq MSHR misses 582system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17247 # number of LoadLockedReq MSHR misses 583system.cpu.dcache.LoadLockedReq_mshr_misses::total 17247 # number of LoadLockedReq MSHR misses 584system.cpu.dcache.demand_mshr_misses::cpu.data 1373670 # number of demand (read+write) MSHR misses 585system.cpu.dcache.demand_mshr_misses::total 1373670 # number of demand (read+write) MSHR misses 586system.cpu.dcache.overall_mshr_misses::cpu.data 1373670 # number of overall MSHR misses 587system.cpu.dcache.overall_mshr_misses::total 1373670 # number of overall MSHR misses 588system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 589system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable 590system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9653 # number of WriteReq MSHR uncacheable 591system.cpu.dcache.WriteReq_mshr_uncacheable::total 9653 # number of WriteReq MSHR uncacheable 592system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16583 # number of overall MSHR uncacheable misses 593system.cpu.dcache.overall_mshr_uncacheable_misses::total 16583 # number of overall MSHR uncacheable misses 594system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43701674500 # number of ReadReq MSHR miss cycles 595system.cpu.dcache.ReadReq_mshr_miss_latency::total 43701674500 # number of ReadReq MSHR miss cycles 596system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17330191000 # number of WriteReq MSHR miss cycles 597system.cpu.dcache.WriteReq_mshr_miss_latency::total 17330191000 # number of WriteReq MSHR miss cycles 598system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 215563500 # number of LoadLockedReq MSHR miss cycles 599system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 215563500 # number of LoadLockedReq MSHR miss cycles 600system.cpu.dcache.demand_mshr_miss_latency::cpu.data 61031865500 # number of demand (read+write) MSHR miss cycles 601system.cpu.dcache.demand_mshr_miss_latency::total 61031865500 # number of demand (read+write) MSHR miss cycles 602system.cpu.dcache.overall_mshr_miss_latency::cpu.data 61031865500 # number of overall MSHR miss cycles 603system.cpu.dcache.overall_mshr_miss_latency::total 61031865500 # number of overall MSHR miss cycles 604system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1526978500 # number of ReadReq MSHR uncacheable cycles 605system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1526978500 # number of ReadReq MSHR uncacheable cycles 606system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2172467000 # number of WriteReq MSHR uncacheable cycles 607system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2172467000 # number of WriteReq MSHR uncacheable cycles 608system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3699445500 # number of overall MSHR uncacheable cycles 609system.cpu.dcache.overall_mshr_uncacheable_latency::total 3699445500 # number of overall MSHR uncacheable cycles 610system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120370 # mshr miss rate for ReadReq accesses 611system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120370 # mshr miss rate for ReadReq accesses 612system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049431 # mshr miss rate for WriteReq accesses 613system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049431 # mshr miss rate for WriteReq accesses 614system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086114 # mshr miss rate for LoadLockedReq accesses 615system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086114 # mshr miss rate for LoadLockedReq accesses 616system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091332 # mshr miss rate for demand accesses 617system.cpu.dcache.demand_mshr_miss_rate::total 0.091332 # mshr miss rate for demand accesses 618system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091332 # mshr miss rate for overall accesses 619system.cpu.dcache.overall_mshr_miss_rate::total 0.091332 # mshr miss rate for overall accesses 620system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40867.818247 # average ReadReq mshr miss latency 621system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40867.818247 # average ReadReq mshr miss latency 622system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56945.765753 # average WriteReq mshr miss latency 623system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56945.765753 # average WriteReq mshr miss latency 624system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12498.608454 # average LoadLockedReq mshr miss latency 625system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12498.608454 # average LoadLockedReq mshr miss latency 626system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44429.786994 # average overall mshr miss latency 627system.cpu.dcache.demand_avg_mshr_miss_latency::total 44429.786994 # average overall mshr miss latency 628system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44429.786994 # average overall mshr miss latency 629system.cpu.dcache.overall_avg_mshr_miss_latency::total 44429.786994 # average overall mshr miss latency 630system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220343.217893 # average ReadReq mshr uncacheable latency 631system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220343.217893 # average ReadReq mshr uncacheable latency 632system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 225056.148348 # average WriteReq mshr uncacheable latency 633system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 225056.148348 # average WriteReq mshr uncacheable latency 634system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 223086.624857 # average overall mshr uncacheable latency 635system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 223086.624857 # average overall mshr uncacheable latency 636system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 637system.cpu.icache.tags.replacements 928920 # number of replacements 638system.cpu.icache.tags.tagsinuse 506.355618 # Cycle average of tags in use 639system.cpu.icache.tags.total_refs 55264986 # Total number of references to valid blocks. 640system.cpu.icache.tags.sampled_refs 929431 # Sample count of references to valid blocks. 641system.cpu.icache.tags.avg_refs 59.461096 # Average number of references to valid blocks. 642system.cpu.icache.tags.warmup_cycle 58592056500 # Cycle when the warmup percentage was hit. 643system.cpu.icache.tags.occ_blocks::cpu.inst 506.355618 # Average occupied blocks per requestor 644system.cpu.icache.tags.occ_percent::cpu.inst 0.988976 # Average percentage of cache occupancy 645system.cpu.icache.tags.occ_percent::total 0.988976 # Average percentage of cache occupancy 646system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 647system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id 648system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 649system.cpu.icache.tags.age_task_id_blocks_1024::2 438 # Occupied blocks per task id 650system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id 651system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id 652system.cpu.icache.tags.tag_accesses 57124168 # Number of tag accesses 653system.cpu.icache.tags.data_accesses 57124168 # Number of data accesses 654system.cpu.icache.ReadReq_hits::cpu.inst 55264986 # number of ReadReq hits 655system.cpu.icache.ReadReq_hits::total 55264986 # number of ReadReq hits 656system.cpu.icache.demand_hits::cpu.inst 55264986 # number of demand (read+write) hits 657system.cpu.icache.demand_hits::total 55264986 # number of demand (read+write) hits 658system.cpu.icache.overall_hits::cpu.inst 55264986 # number of overall hits 659system.cpu.icache.overall_hits::total 55264986 # number of overall hits 660system.cpu.icache.ReadReq_misses::cpu.inst 929591 # number of ReadReq misses 661system.cpu.icache.ReadReq_misses::total 929591 # number of ReadReq misses 662system.cpu.icache.demand_misses::cpu.inst 929591 # number of demand (read+write) misses 663system.cpu.icache.demand_misses::total 929591 # number of demand (read+write) misses 664system.cpu.icache.overall_misses::cpu.inst 929591 # number of overall misses 665system.cpu.icache.overall_misses::total 929591 # number of overall misses 666system.cpu.icache.ReadReq_miss_latency::cpu.inst 13686841500 # number of ReadReq miss cycles 667system.cpu.icache.ReadReq_miss_latency::total 13686841500 # number of ReadReq miss cycles 668system.cpu.icache.demand_miss_latency::cpu.inst 13686841500 # number of demand (read+write) miss cycles 669system.cpu.icache.demand_miss_latency::total 13686841500 # number of demand (read+write) miss cycles 670system.cpu.icache.overall_miss_latency::cpu.inst 13686841500 # number of overall miss cycles 671system.cpu.icache.overall_miss_latency::total 13686841500 # number of overall miss cycles 672system.cpu.icache.ReadReq_accesses::cpu.inst 56194577 # number of ReadReq accesses(hits+misses) 673system.cpu.icache.ReadReq_accesses::total 56194577 # number of ReadReq accesses(hits+misses) 674system.cpu.icache.demand_accesses::cpu.inst 56194577 # number of demand (read+write) accesses 675system.cpu.icache.demand_accesses::total 56194577 # number of demand (read+write) accesses 676system.cpu.icache.overall_accesses::cpu.inst 56194577 # number of overall (read+write) accesses 677system.cpu.icache.overall_accesses::total 56194577 # number of overall (read+write) accesses 678system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016542 # miss rate for ReadReq accesses 679system.cpu.icache.ReadReq_miss_rate::total 0.016542 # miss rate for ReadReq accesses 680system.cpu.icache.demand_miss_rate::cpu.inst 0.016542 # miss rate for demand accesses 681system.cpu.icache.demand_miss_rate::total 0.016542 # miss rate for demand accesses 682system.cpu.icache.overall_miss_rate::cpu.inst 0.016542 # miss rate for overall accesses 683system.cpu.icache.overall_miss_rate::total 0.016542 # miss rate for overall accesses 684system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14723.509049 # average ReadReq miss latency 685system.cpu.icache.ReadReq_avg_miss_latency::total 14723.509049 # average ReadReq miss latency 686system.cpu.icache.demand_avg_miss_latency::cpu.inst 14723.509049 # average overall miss latency 687system.cpu.icache.demand_avg_miss_latency::total 14723.509049 # average overall miss latency 688system.cpu.icache.overall_avg_miss_latency::cpu.inst 14723.509049 # average overall miss latency 689system.cpu.icache.overall_avg_miss_latency::total 14723.509049 # average overall miss latency 690system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 691system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 692system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 693system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 694system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 695system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 696system.cpu.icache.fast_writes 0 # number of fast writes performed 697system.cpu.icache.cache_copies 0 # number of cache copies performed 698system.cpu.icache.writebacks::writebacks 928920 # number of writebacks 699system.cpu.icache.writebacks::total 928920 # number of writebacks 700system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929591 # number of ReadReq MSHR misses 701system.cpu.icache.ReadReq_mshr_misses::total 929591 # number of ReadReq MSHR misses 702system.cpu.icache.demand_mshr_misses::cpu.inst 929591 # number of demand (read+write) MSHR misses 703system.cpu.icache.demand_mshr_misses::total 929591 # number of demand (read+write) MSHR misses 704system.cpu.icache.overall_mshr_misses::cpu.inst 929591 # number of overall MSHR misses 705system.cpu.icache.overall_mshr_misses::total 929591 # number of overall MSHR misses 706system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12757250500 # number of ReadReq MSHR miss cycles 707system.cpu.icache.ReadReq_mshr_miss_latency::total 12757250500 # number of ReadReq MSHR miss cycles 708system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12757250500 # number of demand (read+write) MSHR miss cycles 709system.cpu.icache.demand_mshr_miss_latency::total 12757250500 # number of demand (read+write) MSHR miss cycles 710system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12757250500 # number of overall MSHR miss cycles 711system.cpu.icache.overall_mshr_miss_latency::total 12757250500 # number of overall MSHR miss cycles 712system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016542 # mshr miss rate for ReadReq accesses 713system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016542 # mshr miss rate for ReadReq accesses 714system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016542 # mshr miss rate for demand accesses 715system.cpu.icache.demand_mshr_miss_rate::total 0.016542 # mshr miss rate for demand accesses 716system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016542 # mshr miss rate for overall accesses 717system.cpu.icache.overall_mshr_miss_rate::total 0.016542 # mshr miss rate for overall accesses 718system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13723.509049 # average ReadReq mshr miss latency 719system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13723.509049 # average ReadReq mshr miss latency 720system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13723.509049 # average overall mshr miss latency 721system.cpu.icache.demand_avg_mshr_miss_latency::total 13723.509049 # average overall mshr miss latency 722system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13723.509049 # average overall mshr miss latency 723system.cpu.icache.overall_avg_mshr_miss_latency::total 13723.509049 # average overall mshr miss latency 724system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 725system.cpu.l2cache.tags.replacements 336393 # number of replacements 726system.cpu.l2cache.tags.tagsinuse 65234.360010 # Cycle average of tags in use 727system.cpu.l2cache.tags.total_refs 3930350 # Total number of references to valid blocks. 728system.cpu.l2cache.tags.sampled_refs 401556 # Sample count of references to valid blocks. 729system.cpu.l2cache.tags.avg_refs 9.787800 # Average number of references to valid blocks. 730system.cpu.l2cache.tags.warmup_cycle 10619817000 # Cycle when the warmup percentage was hit. 731system.cpu.l2cache.tags.occ_blocks::writebacks 55072.826279 # Average occupied blocks per requestor 732system.cpu.l2cache.tags.occ_blocks::cpu.inst 4686.115262 # Average occupied blocks per requestor 733system.cpu.l2cache.tags.occ_blocks::cpu.data 5475.418469 # Average occupied blocks per requestor 734system.cpu.l2cache.tags.occ_percent::writebacks 0.840345 # Average percentage of cache occupancy 735system.cpu.l2cache.tags.occ_percent::cpu.inst 0.071504 # Average percentage of cache occupancy 736system.cpu.l2cache.tags.occ_percent::cpu.data 0.083548 # Average percentage of cache occupancy 737system.cpu.l2cache.tags.occ_percent::total 0.995397 # Average percentage of cache occupancy 738system.cpu.l2cache.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id 739system.cpu.l2cache.tags.age_task_id_blocks_1024::0 178 # Occupied blocks per task id 740system.cpu.l2cache.tags.age_task_id_blocks_1024::1 722 # Occupied blocks per task id 741system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5220 # Occupied blocks per task id 742system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3221 # Occupied blocks per task id 743system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55822 # Occupied blocks per task id 744system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id 745system.cpu.l2cache.tags.tag_accesses 37812565 # Number of tag accesses 746system.cpu.l2cache.tags.data_accesses 37812565 # Number of data accesses 747system.cpu.l2cache.WritebackDirty_hits::writebacks 834936 # number of WritebackDirty hits 748system.cpu.l2cache.WritebackDirty_hits::total 834936 # number of WritebackDirty hits 749system.cpu.l2cache.WritebackClean_hits::writebacks 928699 # number of WritebackClean hits 750system.cpu.l2cache.WritebackClean_hits::total 928699 # number of WritebackClean hits 751system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits 752system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits 753system.cpu.l2cache.ReadExReq_hits::cpu.data 187491 # number of ReadExReq hits 754system.cpu.l2cache.ReadExReq_hits::total 187491 # number of ReadExReq hits 755system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 916371 # number of ReadCleanReq hits 756system.cpu.l2cache.ReadCleanReq_hits::total 916371 # number of ReadCleanReq hits 757system.cpu.l2cache.ReadSharedReq_hits::cpu.data 814618 # number of ReadSharedReq hits 758system.cpu.l2cache.ReadSharedReq_hits::total 814618 # number of ReadSharedReq hits 759system.cpu.l2cache.demand_hits::cpu.inst 916371 # number of demand (read+write) hits 760system.cpu.l2cache.demand_hits::cpu.data 1002109 # number of demand (read+write) hits 761system.cpu.l2cache.demand_hits::total 1918480 # number of demand (read+write) hits 762system.cpu.l2cache.overall_hits::cpu.inst 916371 # number of overall hits 763system.cpu.l2cache.overall_hits::cpu.data 1002109 # number of overall hits 764system.cpu.l2cache.overall_hits::total 1918480 # number of overall hits 765system.cpu.l2cache.UpgradeReq_misses::cpu.data 13 # number of UpgradeReq misses 766system.cpu.l2cache.UpgradeReq_misses::total 13 # number of UpgradeReq misses 767system.cpu.l2cache.ReadExReq_misses::cpu.data 116820 # number of ReadExReq misses 768system.cpu.l2cache.ReadExReq_misses::total 116820 # number of ReadExReq misses 769system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 13200 # number of ReadCleanReq misses 770system.cpu.l2cache.ReadCleanReq_misses::total 13200 # number of ReadCleanReq misses 771system.cpu.l2cache.ReadSharedReq_misses::cpu.data 271971 # number of ReadSharedReq misses 772system.cpu.l2cache.ReadSharedReq_misses::total 271971 # number of ReadSharedReq misses 773system.cpu.l2cache.demand_misses::cpu.inst 13200 # number of demand (read+write) misses 774system.cpu.l2cache.demand_misses::cpu.data 388791 # number of demand (read+write) misses 775system.cpu.l2cache.demand_misses::total 401991 # number of demand (read+write) misses 776system.cpu.l2cache.overall_misses::cpu.inst 13200 # number of overall misses 777system.cpu.l2cache.overall_misses::cpu.data 388791 # number of overall misses 778system.cpu.l2cache.overall_misses::total 401991 # number of overall misses 779system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 320500 # number of UpgradeReq miss cycles 780system.cpu.l2cache.UpgradeReq_miss_latency::total 320500 # number of UpgradeReq miss cycles 781system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14900653000 # number of ReadExReq miss cycles 782system.cpu.l2cache.ReadExReq_miss_latency::total 14900653000 # number of ReadExReq miss cycles 783system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1727668500 # number of ReadCleanReq miss cycles 784system.cpu.l2cache.ReadCleanReq_miss_latency::total 1727668500 # number of ReadCleanReq miss cycles 785system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 33719834000 # number of ReadSharedReq miss cycles 786system.cpu.l2cache.ReadSharedReq_miss_latency::total 33719834000 # number of ReadSharedReq miss cycles 787system.cpu.l2cache.demand_miss_latency::cpu.inst 1727668500 # number of demand (read+write) miss cycles 788system.cpu.l2cache.demand_miss_latency::cpu.data 48620487000 # number of demand (read+write) miss cycles 789system.cpu.l2cache.demand_miss_latency::total 50348155500 # number of demand (read+write) miss cycles 790system.cpu.l2cache.overall_miss_latency::cpu.inst 1727668500 # number of overall miss cycles 791system.cpu.l2cache.overall_miss_latency::cpu.data 48620487000 # number of overall miss cycles 792system.cpu.l2cache.overall_miss_latency::total 50348155500 # number of overall miss cycles 793system.cpu.l2cache.WritebackDirty_accesses::writebacks 834936 # number of WritebackDirty accesses(hits+misses) 794system.cpu.l2cache.WritebackDirty_accesses::total 834936 # number of WritebackDirty accesses(hits+misses) 795system.cpu.l2cache.WritebackClean_accesses::writebacks 928699 # number of WritebackClean accesses(hits+misses) 796system.cpu.l2cache.WritebackClean_accesses::total 928699 # number of WritebackClean accesses(hits+misses) 797system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses) 798system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses) 799system.cpu.l2cache.ReadExReq_accesses::cpu.data 304311 # number of ReadExReq accesses(hits+misses) 800system.cpu.l2cache.ReadExReq_accesses::total 304311 # number of ReadExReq accesses(hits+misses) 801system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 929571 # number of ReadCleanReq accesses(hits+misses) 802system.cpu.l2cache.ReadCleanReq_accesses::total 929571 # number of ReadCleanReq accesses(hits+misses) 803system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1086589 # number of ReadSharedReq accesses(hits+misses) 804system.cpu.l2cache.ReadSharedReq_accesses::total 1086589 # number of ReadSharedReq accesses(hits+misses) 805system.cpu.l2cache.demand_accesses::cpu.inst 929571 # number of demand (read+write) accesses 806system.cpu.l2cache.demand_accesses::cpu.data 1390900 # number of demand (read+write) accesses 807system.cpu.l2cache.demand_accesses::total 2320471 # number of demand (read+write) accesses 808system.cpu.l2cache.overall_accesses::cpu.inst 929571 # number of overall (read+write) accesses 809system.cpu.l2cache.overall_accesses::cpu.data 1390900 # number of overall (read+write) accesses 810system.cpu.l2cache.overall_accesses::total 2320471 # number of overall (read+write) accesses 811system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.764706 # miss rate for UpgradeReq accesses 812system.cpu.l2cache.UpgradeReq_miss_rate::total 0.764706 # miss rate for UpgradeReq accesses 813system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383884 # miss rate for ReadExReq accesses 814system.cpu.l2cache.ReadExReq_miss_rate::total 0.383884 # miss rate for ReadExReq accesses 815system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014200 # miss rate for ReadCleanReq accesses 816system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014200 # miss rate for ReadCleanReq accesses 817system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.250298 # miss rate for ReadSharedReq accesses 818system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.250298 # miss rate for ReadSharedReq accesses 819system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014200 # miss rate for demand accesses 820system.cpu.l2cache.demand_miss_rate::cpu.data 0.279525 # miss rate for demand accesses 821system.cpu.l2cache.demand_miss_rate::total 0.173237 # miss rate for demand accesses 822system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014200 # miss rate for overall accesses 823system.cpu.l2cache.overall_miss_rate::cpu.data 0.279525 # miss rate for overall accesses 824system.cpu.l2cache.overall_miss_rate::total 0.173237 # miss rate for overall accesses 825system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 24653.846154 # average UpgradeReq miss latency 826system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 24653.846154 # average UpgradeReq miss latency 827system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127552.242767 # average ReadExReq miss latency 828system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127552.242767 # average ReadExReq miss latency 829system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130883.977273 # average ReadCleanReq miss latency 830system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130883.977273 # average ReadCleanReq miss latency 831system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123983.196738 # average ReadSharedReq miss latency 832system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123983.196738 # average ReadSharedReq miss latency 833system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130883.977273 # average overall miss latency 834system.cpu.l2cache.demand_avg_miss_latency::cpu.data 125055.587707 # average overall miss latency 835system.cpu.l2cache.demand_avg_miss_latency::total 125246.971947 # average overall miss latency 836system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130883.977273 # average overall miss latency 837system.cpu.l2cache.overall_avg_miss_latency::cpu.data 125055.587707 # average overall miss latency 838system.cpu.l2cache.overall_avg_miss_latency::total 125246.971947 # average overall miss latency 839system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 840system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 841system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 842system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 843system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 844system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 845system.cpu.l2cache.fast_writes 0 # number of fast writes performed 846system.cpu.l2cache.cache_copies 0 # number of cache copies performed 847system.cpu.l2cache.writebacks::writebacks 74281 # number of writebacks 848system.cpu.l2cache.writebacks::total 74281 # number of writebacks 849system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses 850system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses 851system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116820 # number of ReadExReq MSHR misses 852system.cpu.l2cache.ReadExReq_mshr_misses::total 116820 # number of ReadExReq MSHR misses 853system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 13200 # number of ReadCleanReq MSHR misses 854system.cpu.l2cache.ReadCleanReq_mshr_misses::total 13200 # number of ReadCleanReq MSHR misses 855system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 271971 # number of ReadSharedReq MSHR misses 856system.cpu.l2cache.ReadSharedReq_mshr_misses::total 271971 # number of ReadSharedReq MSHR misses 857system.cpu.l2cache.demand_mshr_misses::cpu.inst 13200 # number of demand (read+write) MSHR misses 858system.cpu.l2cache.demand_mshr_misses::cpu.data 388791 # number of demand (read+write) MSHR misses 859system.cpu.l2cache.demand_mshr_misses::total 401991 # number of demand (read+write) MSHR misses 860system.cpu.l2cache.overall_mshr_misses::cpu.inst 13200 # number of overall MSHR misses 861system.cpu.l2cache.overall_mshr_misses::cpu.data 388791 # number of overall MSHR misses 862system.cpu.l2cache.overall_mshr_misses::total 401991 # number of overall MSHR misses 863system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 864system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable 865system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9653 # number of WriteReq MSHR uncacheable 866system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9653 # number of WriteReq MSHR uncacheable 867system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16583 # number of overall MSHR uncacheable misses 868system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16583 # number of overall MSHR uncacheable misses 869system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 924500 # number of UpgradeReq MSHR miss cycles 870system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 924500 # number of UpgradeReq MSHR miss cycles 871system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13732453000 # number of ReadExReq MSHR miss cycles 872system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13732453000 # number of ReadExReq MSHR miss cycles 873system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1595668500 # number of ReadCleanReq MSHR miss cycles 874system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1595668500 # number of ReadCleanReq MSHR miss cycles 875system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31000124000 # number of ReadSharedReq MSHR miss cycles 876system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31000124000 # number of ReadSharedReq MSHR miss cycles 877system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1595668500 # number of demand (read+write) MSHR miss cycles 878system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 44732577000 # number of demand (read+write) MSHR miss cycles 879system.cpu.l2cache.demand_mshr_miss_latency::total 46328245500 # number of demand (read+write) MSHR miss cycles 880system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1595668500 # number of overall MSHR miss cycles 881system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 44732577000 # number of overall MSHR miss cycles 882system.cpu.l2cache.overall_mshr_miss_latency::total 46328245500 # number of overall MSHR miss cycles 883system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1440322500 # number of ReadReq MSHR uncacheable cycles 884system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1440322500 # number of ReadReq MSHR uncacheable cycles 885system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2061377000 # number of WriteReq MSHR uncacheable cycles 886system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2061377000 # number of WriteReq MSHR uncacheable cycles 887system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3501699500 # number of overall MSHR uncacheable cycles 888system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3501699500 # number of overall MSHR uncacheable cycles 889system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses 890system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses 891system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383884 # mshr miss rate for ReadExReq accesses 892system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383884 # mshr miss rate for ReadExReq accesses 893system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014200 # mshr miss rate for ReadCleanReq accesses 894system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014200 # mshr miss rate for ReadCleanReq accesses 895system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.250298 # mshr miss rate for ReadSharedReq accesses 896system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.250298 # mshr miss rate for ReadSharedReq accesses 897system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014200 # mshr miss rate for demand accesses 898system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279525 # mshr miss rate for demand accesses 899system.cpu.l2cache.demand_mshr_miss_rate::total 0.173237 # mshr miss rate for demand accesses 900system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014200 # mshr miss rate for overall accesses 901system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279525 # mshr miss rate for overall accesses 902system.cpu.l2cache.overall_mshr_miss_rate::total 0.173237 # mshr miss rate for overall accesses 903system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71115.384615 # average UpgradeReq mshr miss latency 904system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71115.384615 # average UpgradeReq mshr miss latency 905system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117552.242767 # average ReadExReq mshr miss latency 906system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117552.242767 # average ReadExReq mshr miss latency 907system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120883.977273 # average ReadCleanReq mshr miss latency 908system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120883.977273 # average ReadCleanReq mshr miss latency 909system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113983.196738 # average ReadSharedReq mshr miss latency 910system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113983.196738 # average ReadSharedReq mshr miss latency 911system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120883.977273 # average overall mshr miss latency 912system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 115055.587707 # average overall mshr miss latency 913system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115246.971947 # average overall mshr miss latency 914system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120883.977273 # average overall mshr miss latency 915system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 115055.587707 # average overall mshr miss latency 916system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115246.971947 # average overall mshr miss latency 917system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 207838.744589 # average ReadReq mshr uncacheable latency 918system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 207838.744589 # average ReadReq mshr uncacheable latency 919system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 213547.808971 # average WriteReq mshr uncacheable latency 920system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 213547.808971 # average WriteReq mshr uncacheable latency 921system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 211162.003256 # average overall mshr uncacheable latency 922system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 211162.003256 # average overall mshr uncacheable latency 923system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 924system.cpu.toL2Bus.snoop_filter.tot_requests 4639815 # Total number of requests made to the snoop filter. 925system.cpu.toL2Bus.snoop_filter.hit_single_requests 2319473 # Number of requests hitting in the snoop filter with a single holder of the requested data. 926system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1501 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 927system.cpu.toL2Bus.snoop_filter.tot_snoops 1136 # Total number of snoops made to the snoop filter. 928system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1136 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 929system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 930system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution 931system.cpu.toL2Bus.trans_dist::ReadResp 2023267 # Transaction distribution 932system.cpu.toL2Bus.trans_dist::WriteReq 9653 # Transaction distribution 933system.cpu.toL2Bus.trans_dist::WriteResp 9653 # Transaction distribution 934system.cpu.toL2Bus.trans_dist::WritebackDirty 950745 # Transaction distribution 935system.cpu.toL2Bus.trans_dist::WritebackClean 928699 # Transaction distribution 936system.cpu.toL2Bus.trans_dist::CleanEvict 816471 # Transaction distribution 937system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution 938system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution 939system.cpu.toL2Bus.trans_dist::ReadExReq 304311 # Transaction distribution 940system.cpu.toL2Bus.trans_dist::ReadExResp 304311 # Transaction distribution 941system.cpu.toL2Bus.trans_dist::ReadCleanReq 929591 # Transaction distribution 942system.cpu.toL2Bus.trans_dist::ReadSharedReq 1086762 # Transaction distribution 943system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution 944system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2787861 # Packet count per connected master and slave (bytes) 945system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4204279 # Packet count per connected master and slave (bytes) 946system.cpu.toL2Bus.pkt_count::total 6992140 # Packet count per connected master and slave (bytes) 947system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 118929280 # Cumulative packet size per connected master and slave (bytes) 948system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142508140 # Cumulative packet size per connected master and slave (bytes) 949system.cpu.toL2Bus.pkt_size::total 261437420 # Cumulative packet size per connected master and slave (bytes) 950system.cpu.toL2Bus.snoops 419996 # Total snoops (count) 951system.cpu.toL2Bus.snoop_fanout::samples 2756910 # Request fanout histogram 952system.cpu.toL2Bus.snoop_fanout::mean 0.001015 # Request fanout histogram 953system.cpu.toL2Bus.snoop_fanout::stdev 0.031841 # Request fanout histogram 954system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 955system.cpu.toL2Bus.snoop_fanout::0 2754112 99.90% 99.90% # Request fanout histogram 956system.cpu.toL2Bus.snoop_fanout::1 2798 0.10% 100.00% # Request fanout histogram 957system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 958system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 959system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 960system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 961system.cpu.toL2Bus.snoop_fanout::total 2756910 # Request fanout histogram 962system.cpu.toL2Bus.reqLayer0.occupancy 4096881500 # Layer occupancy (ticks) 963system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 964system.cpu.toL2Bus.snoopLayer0.occupancy 293383 # Layer occupancy (ticks) 965system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 966system.cpu.toL2Bus.respLayer0.occupancy 1394386500 # Layer occupancy (ticks) 967system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 968system.cpu.toL2Bus.respLayer1.occupancy 2098115000 # Layer occupancy (ticks) 969system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 970system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 971system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 972system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 973system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 974system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 975system.disk0.dma_write_txs 395 # Number of DMA write transactions. 976system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 977system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 978system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 979system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 980system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 981system.disk2.dma_write_txs 1 # Number of DMA write transactions. 982system.iobus.trans_dist::ReadReq 7103 # Transaction distribution 983system.iobus.trans_dist::ReadResp 7103 # Transaction distribution 984system.iobus.trans_dist::WriteReq 51205 # Transaction distribution 985system.iobus.trans_dist::WriteResp 51205 # Transaction distribution 986system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5162 # Packet count per connected master and slave (bytes) 987system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) 988system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 989system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 990system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 991system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) 992system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) 993system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 994system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 995system.iobus.pkt_count_system.bridge.master::total 33166 # Packet count per connected master and slave (bytes) 996system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) 997system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) 998system.iobus.pkt_count::total 116616 # Packet count per connected master and slave (bytes) 999system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20648 # Cumulative packet size per connected master and slave (bytes) 1000system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes) 1001system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 1002system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 1003system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 1004system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) 1005system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) 1006system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 1007system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 1008system.iobus.pkt_size_system.bridge.master::total 44588 # Cumulative packet size per connected master and slave (bytes) 1009system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) 1010system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) 1011system.iobus.pkt_size::total 2706196 # Cumulative packet size per connected master and slave (bytes) 1012system.iobus.reqLayer0.occupancy 5340500 # Layer occupancy (ticks) 1013system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1014system.iobus.reqLayer1.occupancy 759000 # Layer occupancy (ticks) 1015system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1016system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks) 1017system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1018system.iobus.reqLayer6.occupancy 10000 # Layer occupancy (ticks) 1019system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1020system.iobus.reqLayer22.occupancy 174000 # Layer occupancy (ticks) 1021system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 1022system.iobus.reqLayer23.occupancy 15817000 # Layer occupancy (ticks) 1023system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1024system.iobus.reqLayer24.occupancy 1891500 # Layer occupancy (ticks) 1025system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1026system.iobus.reqLayer25.occupancy 6032000 # Layer occupancy (ticks) 1027system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1028system.iobus.reqLayer26.occupancy 82500 # Layer occupancy (ticks) 1029system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1030system.iobus.reqLayer27.occupancy 215014002 # Layer occupancy (ticks) 1031system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1032system.iobus.respLayer0.occupancy 23513000 # Layer occupancy (ticks) 1033system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1034system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) 1035system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 1036system.iocache.tags.replacements 41685 # number of replacements 1037system.iocache.tags.tagsinuse 1.339384 # Cycle average of tags in use 1038system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1039system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 1040system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1041system.iocache.tags.warmup_cycle 1774106672000 # Cycle when the warmup percentage was hit. 1042system.iocache.tags.occ_blocks::tsunami.ide 1.339384 # Average occupied blocks per requestor 1043system.iocache.tags.occ_percent::tsunami.ide 0.083712 # Average percentage of cache occupancy 1044system.iocache.tags.occ_percent::total 0.083712 # Average percentage of cache occupancy 1045system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1046system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1047system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1048system.iocache.tags.tag_accesses 375525 # Number of tag accesses 1049system.iocache.tags.data_accesses 375525 # Number of data accesses 1050system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 1051system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 1052system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 1053system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses 1054system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses 1055system.iocache.demand_misses::total 173 # number of demand (read+write) misses 1056system.iocache.overall_misses::tsunami.ide 173 # number of overall misses 1057system.iocache.overall_misses::total 173 # number of overall misses 1058system.iocache.ReadReq_miss_latency::tsunami.ide 21742883 # number of ReadReq miss cycles 1059system.iocache.ReadReq_miss_latency::total 21742883 # number of ReadReq miss cycles 1060system.iocache.WriteLineReq_miss_latency::tsunami.ide 5428926119 # number of WriteLineReq miss cycles 1061system.iocache.WriteLineReq_miss_latency::total 5428926119 # number of WriteLineReq miss cycles 1062system.iocache.demand_miss_latency::tsunami.ide 21742883 # number of demand (read+write) miss cycles 1063system.iocache.demand_miss_latency::total 21742883 # number of demand (read+write) miss cycles 1064system.iocache.overall_miss_latency::tsunami.ide 21742883 # number of overall miss cycles 1065system.iocache.overall_miss_latency::total 21742883 # number of overall miss cycles 1066system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 1067system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 1068system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) 1069system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) 1070system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses 1071system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses 1072system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses 1073system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses 1074system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 1075system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1076system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses 1077system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1078system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 1079system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1080system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 1081system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1082system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125681.404624 # average ReadReq miss latency 1083system.iocache.ReadReq_avg_miss_latency::total 125681.404624 # average ReadReq miss latency 1084system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130653.786075 # average WriteLineReq miss latency 1085system.iocache.WriteLineReq_avg_miss_latency::total 130653.786075 # average WriteLineReq miss latency 1086system.iocache.demand_avg_miss_latency::tsunami.ide 125681.404624 # average overall miss latency 1087system.iocache.demand_avg_miss_latency::total 125681.404624 # average overall miss latency 1088system.iocache.overall_avg_miss_latency::tsunami.ide 125681.404624 # average overall miss latency 1089system.iocache.overall_avg_miss_latency::total 125681.404624 # average overall miss latency 1090system.iocache.blocked_cycles::no_mshrs 32 # number of cycles access was blocked 1091system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1092system.iocache.blocked::no_mshrs 4 # number of cycles access was blocked 1093system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1094system.iocache.avg_blocked_cycles::no_mshrs 8 # average number of cycles each access was blocked 1095system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1096system.iocache.fast_writes 0 # number of fast writes performed 1097system.iocache.cache_copies 0 # number of cache copies performed 1098system.iocache.writebacks::writebacks 41512 # number of writebacks 1099system.iocache.writebacks::total 41512 # number of writebacks 1100system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 1101system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 1102system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses 1103system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses 1104system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses 1105system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses 1106system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses 1107system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses 1108system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13092883 # number of ReadReq MSHR miss cycles 1109system.iocache.ReadReq_mshr_miss_latency::total 13092883 # number of ReadReq MSHR miss cycles 1110system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3351326119 # number of WriteLineReq MSHR miss cycles 1111system.iocache.WriteLineReq_mshr_miss_latency::total 3351326119 # number of WriteLineReq MSHR miss cycles 1112system.iocache.demand_mshr_miss_latency::tsunami.ide 13092883 # number of demand (read+write) MSHR miss cycles 1113system.iocache.demand_mshr_miss_latency::total 13092883 # number of demand (read+write) MSHR miss cycles 1114system.iocache.overall_mshr_miss_latency::tsunami.ide 13092883 # number of overall MSHR miss cycles 1115system.iocache.overall_mshr_miss_latency::total 13092883 # number of overall MSHR miss cycles 1116system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 1117system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1118system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses 1119system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1120system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 1121system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1122system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 1123system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1124system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75681.404624 # average ReadReq mshr miss latency 1125system.iocache.ReadReq_avg_mshr_miss_latency::total 75681.404624 # average ReadReq mshr miss latency 1126system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80653.786075 # average WriteLineReq mshr miss latency 1127system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80653.786075 # average WriteLineReq mshr miss latency 1128system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75681.404624 # average overall mshr miss latency 1129system.iocache.demand_avg_mshr_miss_latency::total 75681.404624 # average overall mshr miss latency 1130system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75681.404624 # average overall mshr miss latency 1131system.iocache.overall_avg_mshr_miss_latency::total 75681.404624 # average overall mshr miss latency 1132system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1133system.membus.trans_dist::ReadReq 6930 # Transaction distribution 1134system.membus.trans_dist::ReadResp 292274 # Transaction distribution 1135system.membus.trans_dist::WriteReq 9653 # Transaction distribution 1136system.membus.trans_dist::WriteResp 9653 # Transaction distribution 1137system.membus.trans_dist::WritebackDirty 115793 # Transaction distribution 1138system.membus.trans_dist::CleanEvict 261400 # Transaction distribution 1139system.membus.trans_dist::UpgradeReq 150 # Transaction distribution 1140system.membus.trans_dist::UpgradeResp 150 # Transaction distribution 1141system.membus.trans_dist::ReadExReq 116683 # Transaction distribution 1142system.membus.trans_dist::ReadExResp 116683 # Transaction distribution 1143system.membus.trans_dist::ReadSharedReq 285344 # Transaction distribution 1144system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution 1145system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution 1146system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33166 # Packet count per connected master and slave (bytes) 1147system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1139403 # Packet count per connected master and slave (bytes) 1148system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1172569 # Packet count per connected master and slave (bytes) 1149system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124817 # Packet count per connected master and slave (bytes) 1150system.membus.pkt_count_system.iocache.mem_side::total 124817 # Packet count per connected master and slave (bytes) 1151system.membus.pkt_count::total 1297386 # Packet count per connected master and slave (bytes) 1152system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44588 # Cumulative packet size per connected master and slave (bytes) 1153system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30455296 # Cumulative packet size per connected master and slave (bytes) 1154system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30499884 # Cumulative packet size per connected master and slave (bytes) 1155system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) 1156system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) 1157system.membus.pkt_size::total 33157612 # Cumulative packet size per connected master and slave (bytes) 1158system.membus.snoops 431 # Total snoops (count) 1159system.membus.snoop_fanout::samples 837681 # Request fanout histogram 1160system.membus.snoop_fanout::mean 1 # Request fanout histogram 1161system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1162system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1163system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1164system.membus.snoop_fanout::1 837681 100.00% 100.00% # Request fanout histogram 1165system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1166system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1167system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1168system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1169system.membus.snoop_fanout::total 837681 # Request fanout histogram 1170system.membus.reqLayer0.occupancy 30116000 # Layer occupancy (ticks) 1171system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1172system.membus.reqLayer1.occupancy 1287207146 # Layer occupancy (ticks) 1173system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 1174system.membus.respLayer1.occupancy 2143289352 # Layer occupancy (ticks) 1175system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 1176system.membus.respLayer2.occupancy 69814679 # Layer occupancy (ticks) 1177system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1178system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1179system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1180system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1181system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1182system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1183system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1184system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 1185system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1186system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 1187system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1188system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1189system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 1190system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1191system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1192system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 1193system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1194system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1195system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 1196system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1197system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1198system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 1199system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1200system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1201system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1202system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1203system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1204system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1205system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1206system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1207system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 1208system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 1209 1210---------- End Simulation Statistics ---------- 1211