stats.txt revision 11687:b3d5f0e9e258
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.966742 # Number of seconds simulated 4sim_ticks 1966741627000 # Number of ticks simulated 5final_tick 1966741627000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1743154 # Simulator instruction rate (inst/s) 8host_op_rate 1743154 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 56239519255 # Simulator tick rate (ticks/s) 10host_mem_usage 337608 # Number of bytes of host memory used 11host_seconds 34.97 # Real time elapsed on the host 12sim_insts 60959478 # Number of instructions simulated 13sim_ops 60959478 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu0.inst 796480 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.data 24829632 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.inst 62464 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.data 430848 # Number of bytes read from this memory 21system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 22system.physmem.bytes_read::total 26120384 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu0.inst 796480 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::cpu1.inst 62464 # Number of instructions bytes read from this memory 25system.physmem.bytes_inst_read::total 858944 # Number of instructions bytes read from this memory 26system.physmem.bytes_written::writebacks 7775296 # Number of bytes written to this memory 27system.physmem.bytes_written::total 7775296 # Number of bytes written to this memory 28system.physmem.num_reads::cpu0.inst 12445 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu0.data 387963 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu1.inst 976 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu1.data 6732 # Number of read requests responded to by this memory 32system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory 33system.physmem.num_reads::total 408131 # Number of read requests responded to by this memory 34system.physmem.num_writes::writebacks 121489 # Number of write requests responded to by this memory 35system.physmem.num_writes::total 121489 # Number of write requests responded to by this memory 36system.physmem.bw_read::cpu0.inst 404974 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu0.data 12624755 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu1.inst 31760 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu1.data 219067 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::tsunami.ide 488 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::total 13281045 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu0.inst 404974 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::cpu1.inst 31760 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_inst_read::total 436735 # Instruction read bandwidth from this memory (bytes/s) 45system.physmem.bw_write::writebacks 3953390 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 3953390 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 3953390 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu0.inst 404974 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu0.data 12624755 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu1.inst 31760 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu1.data 219067 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::tsunami.ide 488 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::total 17234435 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.readReqs 408131 # Number of read requests accepted 55system.physmem.writeReqs 121489 # Number of write requests accepted 56system.physmem.readBursts 408131 # Number of DRAM read bursts, including those serviced by the write queue 57system.physmem.writeBursts 121489 # Number of DRAM write bursts, including those merged in the write queue 58system.physmem.bytesReadDRAM 26113216 # Total number of bytes read from DRAM 59system.physmem.bytesReadWrQ 7168 # Total number of bytes read from write queue 60system.physmem.bytesWritten 7773568 # Total number of bytes written to DRAM 61system.physmem.bytesReadSys 26120384 # Total read bytes from the system interface side 62system.physmem.bytesWrittenSys 7775296 # Total written bytes from the system interface side 63system.physmem.servicedByWrQ 112 # Number of DRAM read bursts serviced by the write queue 64system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 65system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 66system.physmem.perBankRdBursts::0 25299 # Per bank write bursts 67system.physmem.perBankRdBursts::1 25599 # Per bank write bursts 68system.physmem.perBankRdBursts::2 25910 # Per bank write bursts 69system.physmem.perBankRdBursts::3 25657 # Per bank write bursts 70system.physmem.perBankRdBursts::4 25586 # Per bank write bursts 71system.physmem.perBankRdBursts::5 25177 # Per bank write bursts 72system.physmem.perBankRdBursts::6 26012 # Per bank write bursts 73system.physmem.perBankRdBursts::7 25110 # Per bank write bursts 74system.physmem.perBankRdBursts::8 25002 # Per bank write bursts 75system.physmem.perBankRdBursts::9 25326 # Per bank write bursts 76system.physmem.perBankRdBursts::10 25348 # Per bank write bursts 77system.physmem.perBankRdBursts::11 25350 # Per bank write bursts 78system.physmem.perBankRdBursts::12 25736 # Per bank write bursts 79system.physmem.perBankRdBursts::13 25396 # Per bank write bursts 80system.physmem.perBankRdBursts::14 25673 # Per bank write bursts 81system.physmem.perBankRdBursts::15 25838 # Per bank write bursts 82system.physmem.perBankWrBursts::0 7888 # Per bank write bursts 83system.physmem.perBankWrBursts::1 7973 # Per bank write bursts 84system.physmem.perBankWrBursts::2 7891 # Per bank write bursts 85system.physmem.perBankWrBursts::3 7697 # Per bank write bursts 86system.physmem.perBankWrBursts::4 7528 # Per bank write bursts 87system.physmem.perBankWrBursts::5 7375 # Per bank write bursts 88system.physmem.perBankWrBursts::6 8079 # Per bank write bursts 89system.physmem.perBankWrBursts::7 7030 # Per bank write bursts 90system.physmem.perBankWrBursts::8 7056 # Per bank write bursts 91system.physmem.perBankWrBursts::9 7058 # Per bank write bursts 92system.physmem.perBankWrBursts::10 7243 # Per bank write bursts 93system.physmem.perBankWrBursts::11 7671 # Per bank write bursts 94system.physmem.perBankWrBursts::12 7657 # Per bank write bursts 95system.physmem.perBankWrBursts::13 7555 # Per bank write bursts 96system.physmem.perBankWrBursts::14 7813 # Per bank write bursts 97system.physmem.perBankWrBursts::15 7948 # Per bank write bursts 98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 99system.physmem.numWrRetry 71 # Number of times write queue was full causing retry 100system.physmem.totGap 1966734334500 # Total gap between requests 101system.physmem.readPktSize::0 0 # Read request sizes (log2) 102system.physmem.readPktSize::1 0 # Read request sizes (log2) 103system.physmem.readPktSize::2 0 # Read request sizes (log2) 104system.physmem.readPktSize::3 0 # Read request sizes (log2) 105system.physmem.readPktSize::4 0 # Read request sizes (log2) 106system.physmem.readPktSize::5 0 # Read request sizes (log2) 107system.physmem.readPktSize::6 408131 # Read request sizes (log2) 108system.physmem.writePktSize::0 0 # Write request sizes (log2) 109system.physmem.writePktSize::1 0 # Write request sizes (log2) 110system.physmem.writePktSize::2 0 # Write request sizes (log2) 111system.physmem.writePktSize::3 0 # Write request sizes (log2) 112system.physmem.writePktSize::4 0 # Write request sizes (log2) 113system.physmem.writePktSize::5 0 # Write request sizes (log2) 114system.physmem.writePktSize::6 121489 # Write request sizes (log2) 115system.physmem.rdQLenPdf::0 407926 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::1 80 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 147system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::15 1643 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::16 2752 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::17 5759 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::18 5841 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::19 6396 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::20 6541 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::21 7366 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::22 8415 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::23 6986 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::24 7365 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::25 8033 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::26 7676 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::27 6912 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::28 7040 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::29 6284 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::30 6217 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::31 5993 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::32 5793 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::33 415 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::34 410 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::35 293 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::36 317 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::37 250 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::38 276 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::39 265 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::40 272 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::41 261 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::42 288 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::43 315 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::44 340 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::45 315 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::46 287 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::47 286 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::48 292 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::49 287 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::50 265 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::51 188 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::52 200 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::53 214 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::54 205 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::55 238 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::56 331 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::57 265 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::58 195 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::59 356 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::60 350 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::61 199 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::62 124 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::63 163 # What write queue length does an incoming req see 211system.physmem.bytesPerActivate::samples 65984 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::mean 513.560621 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::gmean 309.956643 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::stdev 413.656575 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::0-127 15493 23.48% 23.48% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::128-255 12381 18.76% 42.24% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::256-383 4640 7.03% 49.28% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::384-511 3311 5.02% 54.29% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::512-639 3269 4.95% 59.25% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::640-767 1542 2.34% 61.58% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::768-895 1639 2.48% 64.07% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::896-1023 1098 1.66% 65.73% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1024-1151 22611 34.27% 100.00% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::total 65984 # Bytes accessed per row activation 225system.physmem.rdPerTurnAround::samples 5405 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::mean 75.487327 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::stdev 2871.274927 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::0-8191 5402 99.94% 99.94% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes 232system.physmem.rdPerTurnAround::total 5405 # Reads before turning the bus around for writes 233system.physmem.wrPerTurnAround::samples 5405 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::mean 22.472155 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::gmean 18.786030 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::stdev 24.242091 # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::16-23 4888 90.43% 90.43% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::24-31 28 0.52% 90.95% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::32-39 175 3.24% 94.19% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::40-47 6 0.11% 94.30% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::48-55 5 0.09% 94.39% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::56-63 18 0.33% 94.73% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::64-71 9 0.17% 94.89% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::72-79 2 0.04% 94.93% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::80-87 25 0.46% 95.39% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::88-95 5 0.09% 95.49% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::96-103 152 2.81% 98.30% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::104-111 23 0.43% 98.72% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::112-119 6 0.11% 98.83% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::120-127 3 0.06% 98.89% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::128-135 4 0.07% 98.96% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::136-143 5 0.09% 99.06% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::144-151 2 0.04% 99.09% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::152-159 1 0.02% 99.11% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::160-167 1 0.02% 99.13% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::168-175 6 0.11% 99.24% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::176-183 7 0.13% 99.37% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::184-191 9 0.17% 99.54% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::192-199 7 0.13% 99.67% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::200-207 4 0.07% 99.74% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::208-215 1 0.02% 99.76% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::216-223 6 0.11% 99.87% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::224-231 3 0.06% 99.93% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::256-263 2 0.04% 99.96% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::264-271 1 0.02% 99.98% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::336-343 1 0.02% 100.00% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::total 5405 # Writes before turning the bus around for reads 268system.physmem.totQLat 6252046750 # Total ticks spent queuing 269system.physmem.totMemAccLat 13902403000 # Total ticks spent from burst creation until serviced by the DRAM 270system.physmem.totBusLat 2040095000 # Total ticks spent in databus transfers 271system.physmem.avgQLat 15322.93 # Average queueing delay per DRAM burst 272system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 273system.physmem.avgMemAccLat 34072.93 # Average memory access latency per DRAM burst 274system.physmem.avgRdBW 13.28 # Average DRAM read bandwidth in MiByte/s 275system.physmem.avgWrBW 3.95 # Average achieved write bandwidth in MiByte/s 276system.physmem.avgRdBWSys 13.28 # Average system read bandwidth in MiByte/s 277system.physmem.avgWrBWSys 3.95 # Average system write bandwidth in MiByte/s 278system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 279system.physmem.busUtil 0.13 # Data bus utilization in percentage 280system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads 281system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 282system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 283system.physmem.avgWrQLen 22.83 # Average write queue length when enqueuing 284system.physmem.readRowHits 365911 # Number of row buffer hits during reads 285system.physmem.writeRowHits 97586 # Number of row buffer hits during writes 286system.physmem.readRowHitRate 89.68 # Row buffer hit rate for reads 287system.physmem.writeRowHitRate 80.32 # Row buffer hit rate for writes 288system.physmem.avgGap 3713482.00 # Average gap between requests 289system.physmem.pageHitRate 87.53 # Row buffer hit rate, read and write combined 290system.physmem_0.actEnergy 236241180 # Energy for activate commands per rank (pJ) 291system.physmem_0.preEnergy 125565165 # Energy for precharge commands per rank (pJ) 292system.physmem_0.readEnergy 1459059000 # Energy for read commands per rank (pJ) 293system.physmem_0.writeEnergy 320826420 # Energy for write commands per rank (pJ) 294system.physmem_0.refreshEnergy 5643624480.000001 # Energy for refresh commands per rank (pJ) 295system.physmem_0.actBackEnergy 5139412980 # Energy for active background per rank (pJ) 296system.physmem_0.preBackEnergy 370844640 # Energy for precharge background per rank (pJ) 297system.physmem_0.actPowerDownEnergy 13440056220 # Energy for active power-down per rank (pJ) 298system.physmem_0.prePowerDownEnergy 6440902560 # Energy for precharge power-down per rank (pJ) 299system.physmem_0.selfRefreshEnergy 458973488295 # Energy for self refresh per rank (pJ) 300system.physmem_0.totalEnergy 492152011950 # Total energy per rank (pJ) 301system.physmem_0.averagePower 250.237247 # Core power per rank (mW) 302system.physmem_0.totalIdleTime 1954499558250 # Total Idle time Per DRAM Rank 303system.physmem_0.memoryStateTime::IDLE 615960500 # Time in different power states 304system.physmem_0.memoryStateTime::REF 2400520000 # Time in different power states 305system.physmem_0.memoryStateTime::SREF 1908253811750 # Time in different power states 306system.physmem_0.memoryStateTime::PRE_PDN 16773151500 # Time in different power states 307system.physmem_0.memoryStateTime::ACT 9224451750 # Time in different power states 308system.physmem_0.memoryStateTime::ACT_PDN 29473731500 # Time in different power states 309system.physmem_1.actEnergy 234884580 # Energy for activate commands per rank (pJ) 310system.physmem_1.preEnergy 124844115 # Energy for precharge commands per rank (pJ) 311system.physmem_1.readEnergy 1454196660 # Energy for read commands per rank (pJ) 312system.physmem_1.writeEnergy 313205220 # Energy for write commands per rank (pJ) 313system.physmem_1.refreshEnergy 5773313520.000001 # Energy for refresh commands per rank (pJ) 314system.physmem_1.actBackEnergy 5158429890 # Energy for active background per rank (pJ) 315system.physmem_1.preBackEnergy 364374240 # Energy for precharge background per rank (pJ) 316system.physmem_1.actPowerDownEnergy 13818451860 # Energy for active power-down per rank (pJ) 317system.physmem_1.prePowerDownEnergy 6703686720 # Energy for precharge power-down per rank (pJ) 318system.physmem_1.selfRefreshEnergy 458612092095 # Energy for self refresh per rank (pJ) 319system.physmem_1.totalEnergy 492560034510 # Total energy per rank (pJ) 320system.physmem_1.averagePower 250.444709 # Core power per rank (mW) 321system.physmem_1.totalIdleTime 1954406570250 # Total Idle time Per DRAM Rank 322system.physmem_1.memoryStateTime::IDLE 598675750 # Time in different power states 323system.physmem_1.memoryStateTime::REF 2455572000 # Time in different power states 324system.physmem_1.memoryStateTime::SREF 1906713566750 # Time in different power states 325system.physmem_1.memoryStateTime::PRE_PDN 17457468500 # Time in different power states 326system.physmem_1.memoryStateTime::ACT 9212976500 # Time in different power states 327system.physmem_1.memoryStateTime::ACT_PDN 30303367500 # Time in different power states 328system.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states 329system.bridge.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states 330system.cpu_clk_domain.clock 500 # Clock period in ticks 331system.cpu0.dtb.fetch_hits 0 # ITB hits 332system.cpu0.dtb.fetch_misses 0 # ITB misses 333system.cpu0.dtb.fetch_acv 0 # ITB acv 334system.cpu0.dtb.fetch_accesses 0 # ITB accesses 335system.cpu0.dtb.read_hits 7479115 # DTB read hits 336system.cpu0.dtb.read_misses 7764 # DTB read misses 337system.cpu0.dtb.read_acv 210 # DTB read access violations 338system.cpu0.dtb.read_accesses 524068 # DTB read accesses 339system.cpu0.dtb.write_hits 5079820 # DTB write hits 340system.cpu0.dtb.write_misses 909 # DTB write misses 341system.cpu0.dtb.write_acv 133 # DTB write access violations 342system.cpu0.dtb.write_accesses 202594 # DTB write accesses 343system.cpu0.dtb.data_hits 12558935 # DTB hits 344system.cpu0.dtb.data_misses 8673 # DTB misses 345system.cpu0.dtb.data_acv 343 # DTB access violations 346system.cpu0.dtb.data_accesses 726662 # DTB accesses 347system.cpu0.itb.fetch_hits 3638634 # ITB hits 348system.cpu0.itb.fetch_misses 3984 # ITB misses 349system.cpu0.itb.fetch_acv 184 # ITB acv 350system.cpu0.itb.fetch_accesses 3642618 # ITB accesses 351system.cpu0.itb.read_hits 0 # DTB read hits 352system.cpu0.itb.read_misses 0 # DTB read misses 353system.cpu0.itb.read_acv 0 # DTB read access violations 354system.cpu0.itb.read_accesses 0 # DTB read accesses 355system.cpu0.itb.write_hits 0 # DTB write hits 356system.cpu0.itb.write_misses 0 # DTB write misses 357system.cpu0.itb.write_acv 0 # DTB write access violations 358system.cpu0.itb.write_accesses 0 # DTB write accesses 359system.cpu0.itb.data_hits 0 # DTB hits 360system.cpu0.itb.data_misses 0 # DTB misses 361system.cpu0.itb.data_acv 0 # DTB access violations 362system.cpu0.itb.data_accesses 0 # DTB accesses 363system.cpu0.numPwrStateTransitions 13588 # Number of power state transitions 364system.cpu0.pwrStateClkGateDist::samples 6794 # Distribution of time spent in the clock gated state 365system.cpu0.pwrStateClkGateDist::mean 272289101.854578 # Distribution of time spent in the clock gated state 366system.cpu0.pwrStateClkGateDist::stdev 432882462.064242 # Distribution of time spent in the clock gated state 367system.cpu0.pwrStateClkGateDist::1000-5e+10 6794 100.00% 100.00% # Distribution of time spent in the clock gated state 368system.cpu0.pwrStateClkGateDist::min_value 249000 # Distribution of time spent in the clock gated state 369system.cpu0.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state 370system.cpu0.pwrStateClkGateDist::total 6794 # Distribution of time spent in the clock gated state 371system.cpu0.pwrStateResidencyTicks::ON 116809469000 # Cumulative time (in ticks) in various power states 372system.cpu0.pwrStateResidencyTicks::CLK_GATED 1849932158000 # Cumulative time (in ticks) in various power states 373system.cpu0.numCycles 3933483254 # number of cpu cycles simulated 374system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 375system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 376system.cpu0.kern.inst.arm 0 # number of arm instructions executed 377system.cpu0.kern.inst.quiesce 6794 # number of quiesce instructions executed 378system.cpu0.kern.inst.hwrei 163850 # number of hwrei instructions executed 379system.cpu0.kern.ipl_count::0 56218 40.17% 40.17% # number of times we switched to this ipl 380system.cpu0.kern.ipl_count::21 131 0.09% 40.26% # number of times we switched to this ipl 381system.cpu0.kern.ipl_count::22 1975 1.41% 41.67% # number of times we switched to this ipl 382system.cpu0.kern.ipl_count::30 433 0.31% 41.98% # number of times we switched to this ipl 383system.cpu0.kern.ipl_count::31 81195 58.02% 100.00% # number of times we switched to this ipl 384system.cpu0.kern.ipl_count::total 139952 # number of times we switched to this ipl 385system.cpu0.kern.ipl_good::0 55706 49.07% 49.07% # number of times we switched to this ipl from a different ipl 386system.cpu0.kern.ipl_good::21 131 0.12% 49.19% # number of times we switched to this ipl from a different ipl 387system.cpu0.kern.ipl_good::22 1975 1.74% 50.93% # number of times we switched to this ipl from a different ipl 388system.cpu0.kern.ipl_good::30 433 0.38% 51.31% # number of times we switched to this ipl from a different ipl 389system.cpu0.kern.ipl_good::31 55273 48.69% 100.00% # number of times we switched to this ipl from a different ipl 390system.cpu0.kern.ipl_good::total 113518 # number of times we switched to this ipl from a different ipl 391system.cpu0.kern.ipl_ticks::0 1903167810000 96.77% 96.77% # number of cycles we spent at this ipl 392system.cpu0.kern.ipl_ticks::21 93266000 0.00% 96.77% # number of cycles we spent at this ipl 393system.cpu0.kern.ipl_ticks::22 790441500 0.04% 96.81% # number of cycles we spent at this ipl 394system.cpu0.kern.ipl_ticks::30 321171500 0.02% 96.83% # number of cycles we spent at this ipl 395system.cpu0.kern.ipl_ticks::31 62368212000 3.17% 100.00% # number of cycles we spent at this ipl 396system.cpu0.kern.ipl_ticks::total 1966740901000 # number of cycles we spent at this ipl 397system.cpu0.kern.ipl_used::0 0.990893 # fraction of swpipl calls that actually changed the ipl 398system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 399system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 400system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 401system.cpu0.kern.ipl_used::31 0.680744 # fraction of swpipl calls that actually changed the ipl 402system.cpu0.kern.ipl_used::total 0.811121 # fraction of swpipl calls that actually changed the ipl 403system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed 404system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed 405system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed 406system.cpu0.kern.syscall::6 33 14.10% 27.78% # number of syscalls executed 407system.cpu0.kern.syscall::12 1 0.43% 28.21% # number of syscalls executed 408system.cpu0.kern.syscall::17 10 4.27% 32.48% # number of syscalls executed 409system.cpu0.kern.syscall::19 10 4.27% 36.75% # number of syscalls executed 410system.cpu0.kern.syscall::20 6 2.56% 39.32% # number of syscalls executed 411system.cpu0.kern.syscall::23 1 0.43% 39.74% # number of syscalls executed 412system.cpu0.kern.syscall::24 3 1.28% 41.03% # number of syscalls executed 413system.cpu0.kern.syscall::33 8 3.42% 44.44% # number of syscalls executed 414system.cpu0.kern.syscall::41 2 0.85% 45.30% # number of syscalls executed 415system.cpu0.kern.syscall::45 39 16.67% 61.97% # number of syscalls executed 416system.cpu0.kern.syscall::47 3 1.28% 63.25% # number of syscalls executed 417system.cpu0.kern.syscall::48 10 4.27% 67.52% # number of syscalls executed 418system.cpu0.kern.syscall::54 10 4.27% 71.79% # number of syscalls executed 419system.cpu0.kern.syscall::58 1 0.43% 72.22% # number of syscalls executed 420system.cpu0.kern.syscall::59 6 2.56% 74.79% # number of syscalls executed 421system.cpu0.kern.syscall::71 27 11.54% 86.32% # number of syscalls executed 422system.cpu0.kern.syscall::73 3 1.28% 87.61% # number of syscalls executed 423system.cpu0.kern.syscall::74 7 2.99% 90.60% # number of syscalls executed 424system.cpu0.kern.syscall::87 1 0.43% 91.03% # number of syscalls executed 425system.cpu0.kern.syscall::90 3 1.28% 92.31% # number of syscalls executed 426system.cpu0.kern.syscall::92 9 3.85% 96.15% # number of syscalls executed 427system.cpu0.kern.syscall::97 2 0.85% 97.01% # number of syscalls executed 428system.cpu0.kern.syscall::98 2 0.85% 97.86% # number of syscalls executed 429system.cpu0.kern.syscall::132 1 0.43% 98.29% # number of syscalls executed 430system.cpu0.kern.syscall::144 2 0.85% 99.15% # number of syscalls executed 431system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed 432system.cpu0.kern.syscall::total 234 # number of syscalls executed 433system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 434system.cpu0.kern.callpal::wripir 525 0.35% 0.36% # number of callpals executed 435system.cpu0.kern.callpal::wrmces 1 0.00% 0.36% # number of callpals executed 436system.cpu0.kern.callpal::wrfen 1 0.00% 0.36% # number of callpals executed 437system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.36% # number of callpals executed 438system.cpu0.kern.callpal::swpctx 3064 2.07% 2.43% # number of callpals executed 439system.cpu0.kern.callpal::tbi 51 0.03% 2.46% # number of callpals executed 440system.cpu0.kern.callpal::wrent 7 0.00% 2.46% # number of callpals executed 441system.cpu0.kern.callpal::swpipl 133000 89.79% 92.25% # number of callpals executed 442system.cpu0.kern.callpal::rdps 6513 4.40% 96.65% # number of callpals executed 443system.cpu0.kern.callpal::wrkgp 1 0.00% 96.65% # number of callpals executed 444system.cpu0.kern.callpal::wrusp 4 0.00% 96.65% # number of callpals executed 445system.cpu0.kern.callpal::rdusp 9 0.01% 96.66% # number of callpals executed 446system.cpu0.kern.callpal::whami 2 0.00% 96.66% # number of callpals executed 447system.cpu0.kern.callpal::rti 4412 2.98% 99.64% # number of callpals executed 448system.cpu0.kern.callpal::callsys 394 0.27% 99.91% # number of callpals executed 449system.cpu0.kern.callpal::imb 139 0.09% 100.00% # number of callpals executed 450system.cpu0.kern.callpal::total 148125 # number of callpals executed 451system.cpu0.kern.mode_switch::kernel 6988 # number of protection mode switches 452system.cpu0.kern.mode_switch::user 1369 # number of protection mode switches 453system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches 454system.cpu0.kern.mode_good::kernel 1368 455system.cpu0.kern.mode_good::user 1369 456system.cpu0.kern.mode_good::idle 0 457system.cpu0.kern.mode_switch_good::kernel 0.195764 # fraction of useful protection mode switches 458system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 459system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches 460system.cpu0.kern.mode_switch_good::total 0.327510 # fraction of useful protection mode switches 461system.cpu0.kern.mode_ticks::kernel 1962821824500 99.80% 99.80% # number of ticks spent at the given mode 462system.cpu0.kern.mode_ticks::user 3919074500 0.20% 100.00% # number of ticks spent at the given mode 463system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode 464system.cpu0.kern.swap_context 3065 # number of times the context was actually changed 465system.cpu0.committedInsts 47690735 # Number of instructions committed 466system.cpu0.committedOps 47690735 # Number of ops (including micro ops) committed 467system.cpu0.num_int_alu_accesses 44243506 # Number of integer alu accesses 468system.cpu0.num_fp_alu_accesses 210072 # Number of float alu accesses 469system.cpu0.num_func_calls 1190980 # number of times a function call or return occured 470system.cpu0.num_conditional_control_insts 5607273 # number of instructions that are conditional controls 471system.cpu0.num_int_insts 44243506 # number of integer instructions 472system.cpu0.num_fp_insts 210072 # number of float instructions 473system.cpu0.num_int_register_reads 60857324 # number of times the integer registers were read 474system.cpu0.num_int_register_writes 32955789 # number of times the integer registers were written 475system.cpu0.num_fp_register_reads 102653 # number of times the floating registers were read 476system.cpu0.num_fp_register_writes 104432 # number of times the floating registers were written 477system.cpu0.num_mem_refs 12599733 # number of memory refs 478system.cpu0.num_load_insts 7506744 # Number of load instructions 479system.cpu0.num_store_insts 5092989 # Number of store instructions 480system.cpu0.num_idle_cycles 3699864315.998118 # Number of idle cycles 481system.cpu0.num_busy_cycles 233618938.001881 # Number of busy cycles 482system.cpu0.not_idle_fraction 0.059392 # Percentage of non-idle cycles 483system.cpu0.idle_fraction 0.940608 # Percentage of idle cycles 484system.cpu0.Branches 7182999 # Number of branches fetched 485system.cpu0.op_class::No_OpClass 2715471 5.69% 5.69% # Class of executed instruction 486system.cpu0.op_class::IntAlu 31387897 65.80% 71.50% # Class of executed instruction 487system.cpu0.op_class::IntMult 52053 0.11% 71.61% # Class of executed instruction 488system.cpu0.op_class::IntDiv 0 0.00% 71.61% # Class of executed instruction 489system.cpu0.op_class::FloatAdd 26676 0.06% 71.66% # Class of executed instruction 490system.cpu0.op_class::FloatCmp 0 0.00% 71.66% # Class of executed instruction 491system.cpu0.op_class::FloatCvt 0 0.00% 71.66% # Class of executed instruction 492system.cpu0.op_class::FloatMult 0 0.00% 71.66% # Class of executed instruction 493system.cpu0.op_class::FloatMultAcc 0 0.00% 71.66% # Class of executed instruction 494system.cpu0.op_class::FloatDiv 1883 0.00% 71.66% # Class of executed instruction 495system.cpu0.op_class::FloatMisc 0 0.00% 71.66% # Class of executed instruction 496system.cpu0.op_class::FloatSqrt 0 0.00% 71.66% # Class of executed instruction 497system.cpu0.op_class::SimdAdd 0 0.00% 71.66% # Class of executed instruction 498system.cpu0.op_class::SimdAddAcc 0 0.00% 71.66% # Class of executed instruction 499system.cpu0.op_class::SimdAlu 0 0.00% 71.66% # Class of executed instruction 500system.cpu0.op_class::SimdCmp 0 0.00% 71.66% # Class of executed instruction 501system.cpu0.op_class::SimdCvt 0 0.00% 71.66% # Class of executed instruction 502system.cpu0.op_class::SimdMisc 0 0.00% 71.66% # Class of executed instruction 503system.cpu0.op_class::SimdMult 0 0.00% 71.66% # Class of executed instruction 504system.cpu0.op_class::SimdMultAcc 0 0.00% 71.66% # Class of executed instruction 505system.cpu0.op_class::SimdShift 0 0.00% 71.66% # Class of executed instruction 506system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.66% # Class of executed instruction 507system.cpu0.op_class::SimdSqrt 0 0.00% 71.66% # Class of executed instruction 508system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.66% # Class of executed instruction 509system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.66% # Class of executed instruction 510system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.66% # Class of executed instruction 511system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.66% # Class of executed instruction 512system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.66% # Class of executed instruction 513system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.66% # Class of executed instruction 514system.cpu0.op_class::SimdFloatMult 0 0.00% 71.66% # Class of executed instruction 515system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.66% # Class of executed instruction 516system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.66% # Class of executed instruction 517system.cpu0.op_class::MemRead 7588274 15.91% 87.57% # Class of executed instruction 518system.cpu0.op_class::MemWrite 5010180 10.50% 98.08% # Class of executed instruction 519system.cpu0.op_class::FloatMemRead 92589 0.19% 98.27% # Class of executed instruction 520system.cpu0.op_class::FloatMemWrite 88924 0.19% 98.46% # Class of executed instruction 521system.cpu0.op_class::IprAccess 735804 1.54% 100.00% # Class of executed instruction 522system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 523system.cpu0.op_class::total 47699751 # Class of executed instruction 524system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states 525system.cpu0.dcache.tags.replacements 1183172 # number of replacements 526system.cpu0.dcache.tags.tagsinuse 505.236482 # Cycle average of tags in use 527system.cpu0.dcache.tags.total_refs 11369674 # Total number of references to valid blocks. 528system.cpu0.dcache.tags.sampled_refs 1183684 # Sample count of references to valid blocks. 529system.cpu0.dcache.tags.avg_refs 9.605329 # Average number of references to valid blocks. 530system.cpu0.dcache.tags.warmup_cycle 121324500 # Cycle when the warmup percentage was hit. 531system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.236482 # Average occupied blocks per requestor 532system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986790 # Average percentage of cache occupancy 533system.cpu0.dcache.tags.occ_percent::total 0.986790 # Average percentage of cache occupancy 534system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 535system.cpu0.dcache.tags.age_task_id_blocks_1024::0 115 # Occupied blocks per task id 536system.cpu0.dcache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id 537system.cpu0.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id 538system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 539system.cpu0.dcache.tags.tag_accesses 51472726 # Number of tag accesses 540system.cpu0.dcache.tags.data_accesses 51472726 # Number of data accesses 541system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states 542system.cpu0.dcache.ReadReq_hits::cpu0.data 6400739 # number of ReadReq hits 543system.cpu0.dcache.ReadReq_hits::total 6400739 # number of ReadReq hits 544system.cpu0.dcache.WriteReq_hits::cpu0.data 4669408 # number of WriteReq hits 545system.cpu0.dcache.WriteReq_hits::total 4669408 # number of WriteReq hits 546system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 138994 # number of LoadLockedReq hits 547system.cpu0.dcache.LoadLockedReq_hits::total 138994 # number of LoadLockedReq hits 548system.cpu0.dcache.StoreCondReq_hits::cpu0.data 146309 # number of StoreCondReq hits 549system.cpu0.dcache.StoreCondReq_hits::total 146309 # number of StoreCondReq hits 550system.cpu0.dcache.demand_hits::cpu0.data 11070147 # number of demand (read+write) hits 551system.cpu0.dcache.demand_hits::total 11070147 # number of demand (read+write) hits 552system.cpu0.dcache.overall_hits::cpu0.data 11070147 # number of overall hits 553system.cpu0.dcache.overall_hits::total 11070147 # number of overall hits 554system.cpu0.dcache.ReadReq_misses::cpu0.data 938380 # number of ReadReq misses 555system.cpu0.dcache.ReadReq_misses::total 938380 # number of ReadReq misses 556system.cpu0.dcache.WriteReq_misses::cpu0.data 255338 # number of WriteReq misses 557system.cpu0.dcache.WriteReq_misses::total 255338 # number of WriteReq misses 558system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13584 # number of LoadLockedReq misses 559system.cpu0.dcache.LoadLockedReq_misses::total 13584 # number of LoadLockedReq misses 560system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5728 # number of StoreCondReq misses 561system.cpu0.dcache.StoreCondReq_misses::total 5728 # number of StoreCondReq misses 562system.cpu0.dcache.demand_misses::cpu0.data 1193718 # number of demand (read+write) misses 563system.cpu0.dcache.demand_misses::total 1193718 # number of demand (read+write) misses 564system.cpu0.dcache.overall_misses::cpu0.data 1193718 # number of overall misses 565system.cpu0.dcache.overall_misses::total 1193718 # number of overall misses 566system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 31213946000 # number of ReadReq miss cycles 567system.cpu0.dcache.ReadReq_miss_latency::total 31213946000 # number of ReadReq miss cycles 568system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 12660198000 # number of WriteReq miss cycles 569system.cpu0.dcache.WriteReq_miss_latency::total 12660198000 # number of WriteReq miss cycles 570system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 149666500 # number of LoadLockedReq miss cycles 571system.cpu0.dcache.LoadLockedReq_miss_latency::total 149666500 # number of LoadLockedReq miss cycles 572system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 31954500 # number of StoreCondReq miss cycles 573system.cpu0.dcache.StoreCondReq_miss_latency::total 31954500 # number of StoreCondReq miss cycles 574system.cpu0.dcache.demand_miss_latency::cpu0.data 43874144000 # number of demand (read+write) miss cycles 575system.cpu0.dcache.demand_miss_latency::total 43874144000 # number of demand (read+write) miss cycles 576system.cpu0.dcache.overall_miss_latency::cpu0.data 43874144000 # number of overall miss cycles 577system.cpu0.dcache.overall_miss_latency::total 43874144000 # number of overall miss cycles 578system.cpu0.dcache.ReadReq_accesses::cpu0.data 7339119 # number of ReadReq accesses(hits+misses) 579system.cpu0.dcache.ReadReq_accesses::total 7339119 # number of ReadReq accesses(hits+misses) 580system.cpu0.dcache.WriteReq_accesses::cpu0.data 4924746 # number of WriteReq accesses(hits+misses) 581system.cpu0.dcache.WriteReq_accesses::total 4924746 # number of WriteReq accesses(hits+misses) 582system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 152578 # number of LoadLockedReq accesses(hits+misses) 583system.cpu0.dcache.LoadLockedReq_accesses::total 152578 # number of LoadLockedReq accesses(hits+misses) 584system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 152037 # number of StoreCondReq accesses(hits+misses) 585system.cpu0.dcache.StoreCondReq_accesses::total 152037 # number of StoreCondReq accesses(hits+misses) 586system.cpu0.dcache.demand_accesses::cpu0.data 12263865 # number of demand (read+write) accesses 587system.cpu0.dcache.demand_accesses::total 12263865 # number of demand (read+write) accesses 588system.cpu0.dcache.overall_accesses::cpu0.data 12263865 # number of overall (read+write) accesses 589system.cpu0.dcache.overall_accesses::total 12263865 # number of overall (read+write) accesses 590system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127860 # miss rate for ReadReq accesses 591system.cpu0.dcache.ReadReq_miss_rate::total 0.127860 # miss rate for ReadReq accesses 592system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051848 # miss rate for WriteReq accesses 593system.cpu0.dcache.WriteReq_miss_rate::total 0.051848 # miss rate for WriteReq accesses 594system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.089030 # miss rate for LoadLockedReq accesses 595system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.089030 # miss rate for LoadLockedReq accesses 596system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.037675 # miss rate for StoreCondReq accesses 597system.cpu0.dcache.StoreCondReq_miss_rate::total 0.037675 # miss rate for StoreCondReq accesses 598system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097336 # miss rate for demand accesses 599system.cpu0.dcache.demand_miss_rate::total 0.097336 # miss rate for demand accesses 600system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097336 # miss rate for overall accesses 601system.cpu0.dcache.overall_miss_rate::total 0.097336 # miss rate for overall accesses 602system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 33263.652252 # average ReadReq miss latency 603system.cpu0.dcache.ReadReq_avg_miss_latency::total 33263.652252 # average ReadReq miss latency 604system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 49582.114687 # average WriteReq miss latency 605system.cpu0.dcache.WriteReq_avg_miss_latency::total 49582.114687 # average WriteReq miss latency 606system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11017.851885 # average LoadLockedReq miss latency 607system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11017.851885 # average LoadLockedReq miss latency 608system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5578.648743 # average StoreCondReq miss latency 609system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5578.648743 # average StoreCondReq miss latency 610system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36754.194877 # average overall miss latency 611system.cpu0.dcache.demand_avg_miss_latency::total 36754.194877 # average overall miss latency 612system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36754.194877 # average overall miss latency 613system.cpu0.dcache.overall_avg_miss_latency::total 36754.194877 # average overall miss latency 614system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 615system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 616system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 617system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 618system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 619system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 620system.cpu0.dcache.writebacks::writebacks 681271 # number of writebacks 621system.cpu0.dcache.writebacks::total 681271 # number of writebacks 622system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 938380 # number of ReadReq MSHR misses 623system.cpu0.dcache.ReadReq_mshr_misses::total 938380 # number of ReadReq MSHR misses 624system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 255338 # number of WriteReq MSHR misses 625system.cpu0.dcache.WriteReq_mshr_misses::total 255338 # number of WriteReq MSHR misses 626system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13584 # number of LoadLockedReq MSHR misses 627system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13584 # number of LoadLockedReq MSHR misses 628system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5728 # number of StoreCondReq MSHR misses 629system.cpu0.dcache.StoreCondReq_mshr_misses::total 5728 # number of StoreCondReq MSHR misses 630system.cpu0.dcache.demand_mshr_misses::cpu0.data 1193718 # number of demand (read+write) MSHR misses 631system.cpu0.dcache.demand_mshr_misses::total 1193718 # number of demand (read+write) MSHR misses 632system.cpu0.dcache.overall_mshr_misses::cpu0.data 1193718 # number of overall MSHR misses 633system.cpu0.dcache.overall_mshr_misses::total 1193718 # number of overall MSHR misses 634system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7073 # number of ReadReq MSHR uncacheable 635system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7073 # number of ReadReq MSHR uncacheable 636system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10752 # number of WriteReq MSHR uncacheable 637system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10752 # number of WriteReq MSHR uncacheable 638system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17825 # number of overall MSHR uncacheable misses 639system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17825 # number of overall MSHR uncacheable misses 640system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 30275566000 # number of ReadReq MSHR miss cycles 641system.cpu0.dcache.ReadReq_mshr_miss_latency::total 30275566000 # number of ReadReq MSHR miss cycles 642system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 12404860000 # number of WriteReq MSHR miss cycles 643system.cpu0.dcache.WriteReq_mshr_miss_latency::total 12404860000 # number of WriteReq MSHR miss cycles 644system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 136082500 # number of LoadLockedReq MSHR miss cycles 645system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 136082500 # number of LoadLockedReq MSHR miss cycles 646system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 26226500 # number of StoreCondReq MSHR miss cycles 647system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 26226500 # number of StoreCondReq MSHR miss cycles 648system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 42680426000 # number of demand (read+write) MSHR miss cycles 649system.cpu0.dcache.demand_mshr_miss_latency::total 42680426000 # number of demand (read+write) MSHR miss cycles 650system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 42680426000 # number of overall MSHR miss cycles 651system.cpu0.dcache.overall_mshr_miss_latency::total 42680426000 # number of overall MSHR miss cycles 652system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1572135500 # number of ReadReq MSHR uncacheable cycles 653system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1572135500 # number of ReadReq MSHR uncacheable cycles 654system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1572135500 # number of overall MSHR uncacheable cycles 655system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1572135500 # number of overall MSHR uncacheable cycles 656system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127860 # mshr miss rate for ReadReq accesses 657system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127860 # mshr miss rate for ReadReq accesses 658system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051848 # mshr miss rate for WriteReq accesses 659system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051848 # mshr miss rate for WriteReq accesses 660system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.089030 # mshr miss rate for LoadLockedReq accesses 661system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.089030 # mshr miss rate for LoadLockedReq accesses 662system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.037675 # mshr miss rate for StoreCondReq accesses 663system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.037675 # mshr miss rate for StoreCondReq accesses 664system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097336 # mshr miss rate for demand accesses 665system.cpu0.dcache.demand_mshr_miss_rate::total 0.097336 # mshr miss rate for demand accesses 666system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097336 # mshr miss rate for overall accesses 667system.cpu0.dcache.overall_mshr_miss_rate::total 0.097336 # mshr miss rate for overall accesses 668system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 32263.652252 # average ReadReq mshr miss latency 669system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 32263.652252 # average ReadReq mshr miss latency 670system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 48582.114687 # average WriteReq mshr miss latency 671system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 48582.114687 # average WriteReq mshr miss latency 672system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10017.851885 # average LoadLockedReq mshr miss latency 673system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10017.851885 # average LoadLockedReq mshr miss latency 674system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4578.648743 # average StoreCondReq mshr miss latency 675system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4578.648743 # average StoreCondReq mshr miss latency 676system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35754.194877 # average overall mshr miss latency 677system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35754.194877 # average overall mshr miss latency 678system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35754.194877 # average overall mshr miss latency 679system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35754.194877 # average overall mshr miss latency 680system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222272.797964 # average ReadReq mshr uncacheable latency 681system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222272.797964 # average ReadReq mshr uncacheable latency 682system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 88198.345021 # average overall mshr uncacheable latency 683system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 88198.345021 # average overall mshr uncacheable latency 684system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states 685system.cpu0.icache.tags.replacements 692001 # number of replacements 686system.cpu0.icache.tags.tagsinuse 507.922544 # Cycle average of tags in use 687system.cpu0.icache.tags.total_refs 47007113 # Total number of references to valid blocks. 688system.cpu0.icache.tags.sampled_refs 692513 # Sample count of references to valid blocks. 689system.cpu0.icache.tags.avg_refs 67.879033 # Average number of references to valid blocks. 690system.cpu0.icache.tags.warmup_cycle 44813245500 # Cycle when the warmup percentage was hit. 691system.cpu0.icache.tags.occ_blocks::cpu0.inst 507.922544 # Average occupied blocks per requestor 692system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992036 # Average percentage of cache occupancy 693system.cpu0.icache.tags.occ_percent::total 0.992036 # Average percentage of cache occupancy 694system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 695system.cpu0.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id 696system.cpu0.icache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id 697system.cpu0.icache.tags.age_task_id_blocks_1024::2 435 # Occupied blocks per task id 698system.cpu0.icache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id 699system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 700system.cpu0.icache.tags.tag_accesses 48392391 # Number of tag accesses 701system.cpu0.icache.tags.data_accesses 48392391 # Number of data accesses 702system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states 703system.cpu0.icache.ReadReq_hits::cpu0.inst 47007113 # number of ReadReq hits 704system.cpu0.icache.ReadReq_hits::total 47007113 # number of ReadReq hits 705system.cpu0.icache.demand_hits::cpu0.inst 47007113 # number of demand (read+write) hits 706system.cpu0.icache.demand_hits::total 47007113 # number of demand (read+write) hits 707system.cpu0.icache.overall_hits::cpu0.inst 47007113 # number of overall hits 708system.cpu0.icache.overall_hits::total 47007113 # number of overall hits 709system.cpu0.icache.ReadReq_misses::cpu0.inst 692639 # number of ReadReq misses 710system.cpu0.icache.ReadReq_misses::total 692639 # number of ReadReq misses 711system.cpu0.icache.demand_misses::cpu0.inst 692639 # number of demand (read+write) misses 712system.cpu0.icache.demand_misses::total 692639 # number of demand (read+write) misses 713system.cpu0.icache.overall_misses::cpu0.inst 692639 # number of overall misses 714system.cpu0.icache.overall_misses::total 692639 # number of overall misses 715system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10340404000 # number of ReadReq miss cycles 716system.cpu0.icache.ReadReq_miss_latency::total 10340404000 # number of ReadReq miss cycles 717system.cpu0.icache.demand_miss_latency::cpu0.inst 10340404000 # number of demand (read+write) miss cycles 718system.cpu0.icache.demand_miss_latency::total 10340404000 # number of demand (read+write) miss cycles 719system.cpu0.icache.overall_miss_latency::cpu0.inst 10340404000 # number of overall miss cycles 720system.cpu0.icache.overall_miss_latency::total 10340404000 # number of overall miss cycles 721system.cpu0.icache.ReadReq_accesses::cpu0.inst 47699752 # number of ReadReq accesses(hits+misses) 722system.cpu0.icache.ReadReq_accesses::total 47699752 # number of ReadReq accesses(hits+misses) 723system.cpu0.icache.demand_accesses::cpu0.inst 47699752 # number of demand (read+write) accesses 724system.cpu0.icache.demand_accesses::total 47699752 # number of demand (read+write) accesses 725system.cpu0.icache.overall_accesses::cpu0.inst 47699752 # number of overall (read+write) accesses 726system.cpu0.icache.overall_accesses::total 47699752 # number of overall (read+write) accesses 727system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014521 # miss rate for ReadReq accesses 728system.cpu0.icache.ReadReq_miss_rate::total 0.014521 # miss rate for ReadReq accesses 729system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014521 # miss rate for demand accesses 730system.cpu0.icache.demand_miss_rate::total 0.014521 # miss rate for demand accesses 731system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014521 # miss rate for overall accesses 732system.cpu0.icache.overall_miss_rate::total 0.014521 # miss rate for overall accesses 733system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14928.994758 # average ReadReq miss latency 734system.cpu0.icache.ReadReq_avg_miss_latency::total 14928.994758 # average ReadReq miss latency 735system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14928.994758 # average overall miss latency 736system.cpu0.icache.demand_avg_miss_latency::total 14928.994758 # average overall miss latency 737system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14928.994758 # average overall miss latency 738system.cpu0.icache.overall_avg_miss_latency::total 14928.994758 # average overall miss latency 739system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 740system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 741system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 742system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 743system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 744system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 745system.cpu0.icache.writebacks::writebacks 692001 # number of writebacks 746system.cpu0.icache.writebacks::total 692001 # number of writebacks 747system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 692639 # number of ReadReq MSHR misses 748system.cpu0.icache.ReadReq_mshr_misses::total 692639 # number of ReadReq MSHR misses 749system.cpu0.icache.demand_mshr_misses::cpu0.inst 692639 # number of demand (read+write) MSHR misses 750system.cpu0.icache.demand_mshr_misses::total 692639 # number of demand (read+write) MSHR misses 751system.cpu0.icache.overall_mshr_misses::cpu0.inst 692639 # number of overall MSHR misses 752system.cpu0.icache.overall_mshr_misses::total 692639 # number of overall MSHR misses 753system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9647765000 # number of ReadReq MSHR miss cycles 754system.cpu0.icache.ReadReq_mshr_miss_latency::total 9647765000 # number of ReadReq MSHR miss cycles 755system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9647765000 # number of demand (read+write) MSHR miss cycles 756system.cpu0.icache.demand_mshr_miss_latency::total 9647765000 # number of demand (read+write) MSHR miss cycles 757system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9647765000 # number of overall MSHR miss cycles 758system.cpu0.icache.overall_mshr_miss_latency::total 9647765000 # number of overall MSHR miss cycles 759system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014521 # mshr miss rate for ReadReq accesses 760system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014521 # mshr miss rate for ReadReq accesses 761system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014521 # mshr miss rate for demand accesses 762system.cpu0.icache.demand_mshr_miss_rate::total 0.014521 # mshr miss rate for demand accesses 763system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014521 # mshr miss rate for overall accesses 764system.cpu0.icache.overall_mshr_miss_rate::total 0.014521 # mshr miss rate for overall accesses 765system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13928.994758 # average ReadReq mshr miss latency 766system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13928.994758 # average ReadReq mshr miss latency 767system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13928.994758 # average overall mshr miss latency 768system.cpu0.icache.demand_avg_mshr_miss_latency::total 13928.994758 # average overall mshr miss latency 769system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13928.994758 # average overall mshr miss latency 770system.cpu0.icache.overall_avg_mshr_miss_latency::total 13928.994758 # average overall mshr miss latency 771system.cpu1.dtb.fetch_hits 0 # ITB hits 772system.cpu1.dtb.fetch_misses 0 # ITB misses 773system.cpu1.dtb.fetch_acv 0 # ITB acv 774system.cpu1.dtb.fetch_accesses 0 # ITB accesses 775system.cpu1.dtb.read_hits 2442522 # DTB read hits 776system.cpu1.dtb.read_misses 2621 # DTB read misses 777system.cpu1.dtb.read_acv 0 # DTB read access violations 778system.cpu1.dtb.read_accesses 205338 # DTB read accesses 779system.cpu1.dtb.write_hits 1749235 # DTB write hits 780system.cpu1.dtb.write_misses 236 # DTB write misses 781system.cpu1.dtb.write_acv 24 # DTB write access violations 782system.cpu1.dtb.write_accesses 89740 # DTB write accesses 783system.cpu1.dtb.data_hits 4191757 # DTB hits 784system.cpu1.dtb.data_misses 2857 # DTB misses 785system.cpu1.dtb.data_acv 24 # DTB access violations 786system.cpu1.dtb.data_accesses 295078 # DTB accesses 787system.cpu1.itb.fetch_hits 1826928 # ITB hits 788system.cpu1.itb.fetch_misses 1064 # ITB misses 789system.cpu1.itb.fetch_acv 0 # ITB acv 790system.cpu1.itb.fetch_accesses 1827992 # ITB accesses 791system.cpu1.itb.read_hits 0 # DTB read hits 792system.cpu1.itb.read_misses 0 # DTB read misses 793system.cpu1.itb.read_acv 0 # DTB read access violations 794system.cpu1.itb.read_accesses 0 # DTB read accesses 795system.cpu1.itb.write_hits 0 # DTB write hits 796system.cpu1.itb.write_misses 0 # DTB write misses 797system.cpu1.itb.write_acv 0 # DTB write access violations 798system.cpu1.itb.write_accesses 0 # DTB write accesses 799system.cpu1.itb.data_hits 0 # DTB hits 800system.cpu1.itb.data_misses 0 # DTB misses 801system.cpu1.itb.data_acv 0 # DTB access violations 802system.cpu1.itb.data_accesses 0 # DTB accesses 803system.cpu1.numPwrStateTransitions 5609 # Number of power state transitions 804system.cpu1.pwrStateClkGateDist::samples 2805 # Distribution of time spent in the clock gated state 805system.cpu1.pwrStateClkGateDist::mean 692202308.556150 # Distribution of time spent in the clock gated state 806system.cpu1.pwrStateClkGateDist::stdev 417084374.205506 # Distribution of time spent in the clock gated state 807system.cpu1.pwrStateClkGateDist::1000-5e+10 2805 100.00% 100.00% # Distribution of time spent in the clock gated state 808system.cpu1.pwrStateClkGateDist::min_value 82000 # Distribution of time spent in the clock gated state 809system.cpu1.pwrStateClkGateDist::max_value 974673500 # Distribution of time spent in the clock gated state 810system.cpu1.pwrStateClkGateDist::total 2805 # Distribution of time spent in the clock gated state 811system.cpu1.pwrStateResidencyTicks::ON 25114151500 # Cumulative time (in ticks) in various power states 812system.cpu1.pwrStateResidencyTicks::CLK_GATED 1941627475500 # Cumulative time (in ticks) in various power states 813system.cpu1.numCycles 3931646339 # number of cpu cycles simulated 814system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 815system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 816system.cpu1.kern.inst.arm 0 # number of arm instructions executed 817system.cpu1.kern.inst.quiesce 2805 # number of quiesce instructions executed 818system.cpu1.kern.inst.hwrei 79700 # number of hwrei instructions executed 819system.cpu1.kern.ipl_count::0 27196 38.42% 38.42% # number of times we switched to this ipl 820system.cpu1.kern.ipl_count::22 1969 2.78% 41.20% # number of times we switched to this ipl 821system.cpu1.kern.ipl_count::30 525 0.74% 41.94% # number of times we switched to this ipl 822system.cpu1.kern.ipl_count::31 41097 58.06% 100.00% # number of times we switched to this ipl 823system.cpu1.kern.ipl_count::total 70787 # number of times we switched to this ipl 824system.cpu1.kern.ipl_good::0 26331 48.20% 48.20% # number of times we switched to this ipl from a different ipl 825system.cpu1.kern.ipl_good::22 1969 3.60% 51.80% # number of times we switched to this ipl from a different ipl 826system.cpu1.kern.ipl_good::30 525 0.96% 52.76% # number of times we switched to this ipl from a different ipl 827system.cpu1.kern.ipl_good::31 25806 47.24% 100.00% # number of times we switched to this ipl from a different ipl 828system.cpu1.kern.ipl_good::total 54631 # number of times we switched to this ipl from a different ipl 829system.cpu1.kern.ipl_ticks::0 1909855366000 97.15% 97.15% # number of cycles we spent at this ipl 830system.cpu1.kern.ipl_ticks::22 731068500 0.04% 97.19% # number of cycles we spent at this ipl 831system.cpu1.kern.ipl_ticks::30 371926000 0.02% 97.21% # number of cycles we spent at this ipl 832system.cpu1.kern.ipl_ticks::31 54864779000 2.79% 100.00% # number of cycles we spent at this ipl 833system.cpu1.kern.ipl_ticks::total 1965823139500 # number of cycles we spent at this ipl 834system.cpu1.kern.ipl_used::0 0.968194 # fraction of swpipl calls that actually changed the ipl 835system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 836system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 837system.cpu1.kern.ipl_used::31 0.627929 # fraction of swpipl calls that actually changed the ipl 838system.cpu1.kern.ipl_used::total 0.771766 # fraction of swpipl calls that actually changed the ipl 839system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed 840system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed 841system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed 842system.cpu1.kern.syscall::17 5 5.43% 27.17% # number of syscalls executed 843system.cpu1.kern.syscall::23 3 3.26% 30.43% # number of syscalls executed 844system.cpu1.kern.syscall::24 3 3.26% 33.70% # number of syscalls executed 845system.cpu1.kern.syscall::33 3 3.26% 36.96% # number of syscalls executed 846system.cpu1.kern.syscall::45 15 16.30% 53.26% # number of syscalls executed 847system.cpu1.kern.syscall::47 3 3.26% 56.52% # number of syscalls executed 848system.cpu1.kern.syscall::59 1 1.09% 57.61% # number of syscalls executed 849system.cpu1.kern.syscall::71 27 29.35% 86.96% # number of syscalls executed 850system.cpu1.kern.syscall::74 9 9.78% 96.74% # number of syscalls executed 851system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed 852system.cpu1.kern.syscall::total 92 # number of syscalls executed 853system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 854system.cpu1.kern.callpal::wripir 433 0.59% 0.59% # number of callpals executed 855system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed 856system.cpu1.kern.callpal::wrfen 1 0.00% 0.60% # number of callpals executed 857system.cpu1.kern.callpal::swpctx 2016 2.75% 3.35% # number of callpals executed 858system.cpu1.kern.callpal::tbi 3 0.00% 3.35% # number of callpals executed 859system.cpu1.kern.callpal::wrent 7 0.01% 3.36% # number of callpals executed 860system.cpu1.kern.callpal::swpipl 64567 88.14% 91.50% # number of callpals executed 861system.cpu1.kern.callpal::rdps 2334 3.19% 94.68% # number of callpals executed 862system.cpu1.kern.callpal::wrkgp 1 0.00% 94.68% # number of callpals executed 863system.cpu1.kern.callpal::wrusp 3 0.00% 94.69% # number of callpals executed 864system.cpu1.kern.callpal::whami 3 0.00% 94.69% # number of callpals executed 865system.cpu1.kern.callpal::rti 3725 5.08% 99.78% # number of callpals executed 866system.cpu1.kern.callpal::callsys 121 0.17% 99.94% # number of callpals executed 867system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed 868system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed 869system.cpu1.kern.callpal::total 73259 # number of callpals executed 870system.cpu1.kern.mode_switch::kernel 1964 # number of protection mode switches 871system.cpu1.kern.mode_switch::user 367 # number of protection mode switches 872system.cpu1.kern.mode_switch::idle 2923 # number of protection mode switches 873system.cpu1.kern.mode_good::kernel 816 874system.cpu1.kern.mode_good::user 367 875system.cpu1.kern.mode_good::idle 449 876system.cpu1.kern.mode_switch_good::kernel 0.415479 # fraction of useful protection mode switches 877system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 878system.cpu1.kern.mode_switch_good::idle 0.153609 # fraction of useful protection mode switches 879system.cpu1.kern.mode_switch_good::total 0.310620 # fraction of useful protection mode switches 880system.cpu1.kern.mode_ticks::kernel 18376717500 0.94% 0.94% # number of ticks spent at the given mode 881system.cpu1.kern.mode_ticks::user 1492465500 0.08% 1.01% # number of ticks spent at the given mode 882system.cpu1.kern.mode_ticks::idle 1945081083000 98.99% 100.00% # number of ticks spent at the given mode 883system.cpu1.kern.swap_context 2017 # number of times the context was actually changed 884system.cpu1.committedInsts 13268743 # Number of instructions committed 885system.cpu1.committedOps 13268743 # Number of ops (including micro ops) committed 886system.cpu1.num_int_alu_accesses 12224543 # Number of integer alu accesses 887system.cpu1.num_fp_alu_accesses 175144 # Number of float alu accesses 888system.cpu1.num_func_calls 423393 # number of times a function call or return occured 889system.cpu1.num_conditional_control_insts 1315452 # number of instructions that are conditional controls 890system.cpu1.num_int_insts 12224543 # number of integer instructions 891system.cpu1.num_fp_insts 175144 # number of float instructions 892system.cpu1.num_int_register_reads 16795911 # number of times the integer registers were read 893system.cpu1.num_int_register_writes 8988763 # number of times the integer registers were written 894system.cpu1.num_fp_register_reads 90944 # number of times the floating registers were read 895system.cpu1.num_fp_register_writes 92918 # number of times the floating registers were written 896system.cpu1.num_mem_refs 4214824 # number of memory refs 897system.cpu1.num_load_insts 2456352 # Number of load instructions 898system.cpu1.num_store_insts 1758472 # Number of store instructions 899system.cpu1.num_idle_cycles 3881441492.340690 # Number of idle cycles 900system.cpu1.num_busy_cycles 50204846.659310 # Number of busy cycles 901system.cpu1.not_idle_fraction 0.012769 # Percentage of non-idle cycles 902system.cpu1.idle_fraction 0.987231 # Percentage of idle cycles 903system.cpu1.Branches 1899015 # Number of branches fetched 904system.cpu1.op_class::No_OpClass 719201 5.42% 5.42% # Class of executed instruction 905system.cpu1.op_class::IntAlu 7861154 59.23% 64.65% # Class of executed instruction 906system.cpu1.op_class::IntMult 22602 0.17% 64.82% # Class of executed instruction 907system.cpu1.op_class::IntDiv 0 0.00% 64.82% # Class of executed instruction 908system.cpu1.op_class::FloatAdd 13252 0.10% 64.92% # Class of executed instruction 909system.cpu1.op_class::FloatCmp 0 0.00% 64.92% # Class of executed instruction 910system.cpu1.op_class::FloatCvt 0 0.00% 64.92% # Class of executed instruction 911system.cpu1.op_class::FloatMult 0 0.00% 64.92% # Class of executed instruction 912system.cpu1.op_class::FloatMultAcc 0 0.00% 64.92% # Class of executed instruction 913system.cpu1.op_class::FloatDiv 1759 0.01% 64.94% # Class of executed instruction 914system.cpu1.op_class::FloatMisc 0 0.00% 64.94% # Class of executed instruction 915system.cpu1.op_class::FloatSqrt 0 0.00% 64.94% # Class of executed instruction 916system.cpu1.op_class::SimdAdd 0 0.00% 64.94% # Class of executed instruction 917system.cpu1.op_class::SimdAddAcc 0 0.00% 64.94% # Class of executed instruction 918system.cpu1.op_class::SimdAlu 0 0.00% 64.94% # Class of executed instruction 919system.cpu1.op_class::SimdCmp 0 0.00% 64.94% # Class of executed instruction 920system.cpu1.op_class::SimdCvt 0 0.00% 64.94% # Class of executed instruction 921system.cpu1.op_class::SimdMisc 0 0.00% 64.94% # Class of executed instruction 922system.cpu1.op_class::SimdMult 0 0.00% 64.94% # Class of executed instruction 923system.cpu1.op_class::SimdMultAcc 0 0.00% 64.94% # Class of executed instruction 924system.cpu1.op_class::SimdShift 0 0.00% 64.94% # Class of executed instruction 925system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.94% # Class of executed instruction 926system.cpu1.op_class::SimdSqrt 0 0.00% 64.94% # Class of executed instruction 927system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.94% # Class of executed instruction 928system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.94% # Class of executed instruction 929system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.94% # Class of executed instruction 930system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.94% # Class of executed instruction 931system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.94% # Class of executed instruction 932system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.94% # Class of executed instruction 933system.cpu1.op_class::SimdFloatMult 0 0.00% 64.94% # Class of executed instruction 934system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.94% # Class of executed instruction 935system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.94% # Class of executed instruction 936system.cpu1.op_class::MemRead 2447876 18.44% 83.38% # Class of executed instruction 937system.cpu1.op_class::MemWrite 1681278 12.67% 96.05% # Class of executed instruction 938system.cpu1.op_class::FloatMemRead 81935 0.62% 96.67% # Class of executed instruction 939system.cpu1.op_class::FloatMemWrite 78198 0.59% 97.25% # Class of executed instruction 940system.cpu1.op_class::IprAccess 364369 2.75% 100.00% # Class of executed instruction 941system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 942system.cpu1.op_class::total 13271624 # Class of executed instruction 943system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states 944system.cpu1.dcache.tags.replacements 162095 # number of replacements 945system.cpu1.dcache.tags.tagsinuse 484.320037 # Cycle average of tags in use 946system.cpu1.dcache.tags.total_refs 4015175 # Total number of references to valid blocks. 947system.cpu1.dcache.tags.sampled_refs 162424 # Sample count of references to valid blocks. 948system.cpu1.dcache.tags.avg_refs 24.720331 # Average number of references to valid blocks. 949system.cpu1.dcache.tags.warmup_cycle 72635663500 # Cycle when the warmup percentage was hit. 950system.cpu1.dcache.tags.occ_blocks::cpu1.data 484.320037 # Average occupied blocks per requestor 951system.cpu1.dcache.tags.occ_percent::cpu1.data 0.945938 # Average percentage of cache occupancy 952system.cpu1.dcache.tags.occ_percent::total 0.945938 # Average percentage of cache occupancy 953system.cpu1.dcache.tags.occ_task_id_blocks::1024 329 # Occupied blocks per task id 954system.cpu1.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id 955system.cpu1.dcache.tags.age_task_id_blocks_1024::3 297 # Occupied blocks per task id 956system.cpu1.dcache.tags.occ_task_id_percent::1024 0.642578 # Percentage of cache occupancy per task id 957system.cpu1.dcache.tags.tag_accesses 16996897 # Number of tag accesses 958system.cpu1.dcache.tags.data_accesses 16996897 # Number of data accesses 959system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states 960system.cpu1.dcache.ReadReq_hits::cpu1.data 2273870 # number of ReadReq hits 961system.cpu1.dcache.ReadReq_hits::total 2273870 # number of ReadReq hits 962system.cpu1.dcache.WriteReq_hits::cpu1.data 1634166 # number of WriteReq hits 963system.cpu1.dcache.WriteReq_hits::total 1634166 # number of WriteReq hits 964system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 51918 # number of LoadLockedReq hits 965system.cpu1.dcache.LoadLockedReq_hits::total 51918 # number of LoadLockedReq hits 966system.cpu1.dcache.StoreCondReq_hits::cpu1.data 52084 # number of StoreCondReq hits 967system.cpu1.dcache.StoreCondReq_hits::total 52084 # number of StoreCondReq hits 968system.cpu1.dcache.demand_hits::cpu1.data 3908036 # number of demand (read+write) hits 969system.cpu1.dcache.demand_hits::total 3908036 # number of demand (read+write) hits 970system.cpu1.dcache.overall_hits::cpu1.data 3908036 # number of overall hits 971system.cpu1.dcache.overall_hits::total 3908036 # number of overall hits 972system.cpu1.dcache.ReadReq_misses::cpu1.data 118670 # number of ReadReq misses 973system.cpu1.dcache.ReadReq_misses::total 118670 # number of ReadReq misses 974system.cpu1.dcache.WriteReq_misses::cpu1.data 58749 # number of WriteReq misses 975system.cpu1.dcache.WriteReq_misses::total 58749 # number of WriteReq misses 976system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9148 # number of LoadLockedReq misses 977system.cpu1.dcache.LoadLockedReq_misses::total 9148 # number of LoadLockedReq misses 978system.cpu1.dcache.StoreCondReq_misses::cpu1.data 6116 # number of StoreCondReq misses 979system.cpu1.dcache.StoreCondReq_misses::total 6116 # number of StoreCondReq misses 980system.cpu1.dcache.demand_misses::cpu1.data 177419 # number of demand (read+write) misses 981system.cpu1.dcache.demand_misses::total 177419 # number of demand (read+write) misses 982system.cpu1.dcache.overall_misses::cpu1.data 177419 # number of overall misses 983system.cpu1.dcache.overall_misses::total 177419 # number of overall misses 984system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1466187000 # number of ReadReq miss cycles 985system.cpu1.dcache.ReadReq_miss_latency::total 1466187000 # number of ReadReq miss cycles 986system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1296760000 # number of WriteReq miss cycles 987system.cpu1.dcache.WriteReq_miss_latency::total 1296760000 # number of WriteReq miss cycles 988system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 84020000 # number of LoadLockedReq miss cycles 989system.cpu1.dcache.LoadLockedReq_miss_latency::total 84020000 # number of LoadLockedReq miss cycles 990system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 34172000 # number of StoreCondReq miss cycles 991system.cpu1.dcache.StoreCondReq_miss_latency::total 34172000 # number of StoreCondReq miss cycles 992system.cpu1.dcache.demand_miss_latency::cpu1.data 2762947000 # number of demand (read+write) miss cycles 993system.cpu1.dcache.demand_miss_latency::total 2762947000 # number of demand (read+write) miss cycles 994system.cpu1.dcache.overall_miss_latency::cpu1.data 2762947000 # number of overall miss cycles 995system.cpu1.dcache.overall_miss_latency::total 2762947000 # number of overall miss cycles 996system.cpu1.dcache.ReadReq_accesses::cpu1.data 2392540 # number of ReadReq accesses(hits+misses) 997system.cpu1.dcache.ReadReq_accesses::total 2392540 # number of ReadReq accesses(hits+misses) 998system.cpu1.dcache.WriteReq_accesses::cpu1.data 1692915 # number of WriteReq accesses(hits+misses) 999system.cpu1.dcache.WriteReq_accesses::total 1692915 # number of WriteReq accesses(hits+misses) 1000system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 61066 # number of LoadLockedReq accesses(hits+misses) 1001system.cpu1.dcache.LoadLockedReq_accesses::total 61066 # number of LoadLockedReq accesses(hits+misses) 1002system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 58200 # number of StoreCondReq accesses(hits+misses) 1003system.cpu1.dcache.StoreCondReq_accesses::total 58200 # number of StoreCondReq accesses(hits+misses) 1004system.cpu1.dcache.demand_accesses::cpu1.data 4085455 # number of demand (read+write) accesses 1005system.cpu1.dcache.demand_accesses::total 4085455 # number of demand (read+write) accesses 1006system.cpu1.dcache.overall_accesses::cpu1.data 4085455 # number of overall (read+write) accesses 1007system.cpu1.dcache.overall_accesses::total 4085455 # number of overall (read+write) accesses 1008system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049600 # miss rate for ReadReq accesses 1009system.cpu1.dcache.ReadReq_miss_rate::total 0.049600 # miss rate for ReadReq accesses 1010system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034703 # miss rate for WriteReq accesses 1011system.cpu1.dcache.WriteReq_miss_rate::total 0.034703 # miss rate for WriteReq accesses 1012system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.149805 # miss rate for LoadLockedReq accesses 1013system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.149805 # miss rate for LoadLockedReq accesses 1014system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.105086 # miss rate for StoreCondReq accesses 1015system.cpu1.dcache.StoreCondReq_miss_rate::total 0.105086 # miss rate for StoreCondReq accesses 1016system.cpu1.dcache.demand_miss_rate::cpu1.data 0.043427 # miss rate for demand accesses 1017system.cpu1.dcache.demand_miss_rate::total 0.043427 # miss rate for demand accesses 1018system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043427 # miss rate for overall accesses 1019system.cpu1.dcache.overall_miss_rate::total 0.043427 # miss rate for overall accesses 1020system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12355.161372 # average ReadReq miss latency 1021system.cpu1.dcache.ReadReq_avg_miss_latency::total 12355.161372 # average ReadReq miss latency 1022system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22072.886347 # average WriteReq miss latency 1023system.cpu1.dcache.WriteReq_avg_miss_latency::total 22072.886347 # average WriteReq miss latency 1024system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9184.521207 # average LoadLockedReq miss latency 1025system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9184.521207 # average LoadLockedReq miss latency 1026system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5587.311969 # average StoreCondReq miss latency 1027system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5587.311969 # average StoreCondReq miss latency 1028system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15573.005146 # average overall miss latency 1029system.cpu1.dcache.demand_avg_miss_latency::total 15573.005146 # average overall miss latency 1030system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15573.005146 # average overall miss latency 1031system.cpu1.dcache.overall_avg_miss_latency::total 15573.005146 # average overall miss latency 1032system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1033system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1034system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1035system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1036system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1037system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1038system.cpu1.dcache.writebacks::writebacks 111600 # number of writebacks 1039system.cpu1.dcache.writebacks::total 111600 # number of writebacks 1040system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 118670 # number of ReadReq MSHR misses 1041system.cpu1.dcache.ReadReq_mshr_misses::total 118670 # number of ReadReq MSHR misses 1042system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 58749 # number of WriteReq MSHR misses 1043system.cpu1.dcache.WriteReq_mshr_misses::total 58749 # number of WriteReq MSHR misses 1044system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9148 # number of LoadLockedReq MSHR misses 1045system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9148 # number of LoadLockedReq MSHR misses 1046system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6116 # number of StoreCondReq MSHR misses 1047system.cpu1.dcache.StoreCondReq_mshr_misses::total 6116 # number of StoreCondReq MSHR misses 1048system.cpu1.dcache.demand_mshr_misses::cpu1.data 177419 # number of demand (read+write) MSHR misses 1049system.cpu1.dcache.demand_mshr_misses::total 177419 # number of demand (read+write) MSHR misses 1050system.cpu1.dcache.overall_mshr_misses::cpu1.data 177419 # number of overall MSHR misses 1051system.cpu1.dcache.overall_mshr_misses::total 177419 # number of overall MSHR misses 1052system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 125 # number of ReadReq MSHR uncacheable 1053system.cpu1.dcache.ReadReq_mshr_uncacheable::total 125 # number of ReadReq MSHR uncacheable 1054system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3371 # number of WriteReq MSHR uncacheable 1055system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3371 # number of WriteReq MSHR uncacheable 1056system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3496 # number of overall MSHR uncacheable misses 1057system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3496 # number of overall MSHR uncacheable misses 1058system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1347517000 # number of ReadReq MSHR miss cycles 1059system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1347517000 # number of ReadReq MSHR miss cycles 1060system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1238011000 # number of WriteReq MSHR miss cycles 1061system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1238011000 # number of WriteReq MSHR miss cycles 1062system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 74872000 # number of LoadLockedReq MSHR miss cycles 1063system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 74872000 # number of LoadLockedReq MSHR miss cycles 1064system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 28056000 # number of StoreCondReq MSHR miss cycles 1065system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 28056000 # number of StoreCondReq MSHR miss cycles 1066system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2585528000 # number of demand (read+write) MSHR miss cycles 1067system.cpu1.dcache.demand_mshr_miss_latency::total 2585528000 # number of demand (read+write) MSHR miss cycles 1068system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2585528000 # number of overall MSHR miss cycles 1069system.cpu1.dcache.overall_mshr_miss_latency::total 2585528000 # number of overall MSHR miss cycles 1070system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 26291000 # number of ReadReq MSHR uncacheable cycles 1071system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 26291000 # number of ReadReq MSHR uncacheable cycles 1072system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 26291000 # number of overall MSHR uncacheable cycles 1073system.cpu1.dcache.overall_mshr_uncacheable_latency::total 26291000 # number of overall MSHR uncacheable cycles 1074system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049600 # mshr miss rate for ReadReq accesses 1075system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049600 # mshr miss rate for ReadReq accesses 1076system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034703 # mshr miss rate for WriteReq accesses 1077system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034703 # mshr miss rate for WriteReq accesses 1078system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.149805 # mshr miss rate for LoadLockedReq accesses 1079system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.149805 # mshr miss rate for LoadLockedReq accesses 1080system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.105086 # mshr miss rate for StoreCondReq accesses 1081system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.105086 # mshr miss rate for StoreCondReq accesses 1082system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043427 # mshr miss rate for demand accesses 1083system.cpu1.dcache.demand_mshr_miss_rate::total 0.043427 # mshr miss rate for demand accesses 1084system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043427 # mshr miss rate for overall accesses 1085system.cpu1.dcache.overall_mshr_miss_rate::total 0.043427 # mshr miss rate for overall accesses 1086system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11355.161372 # average ReadReq mshr miss latency 1087system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11355.161372 # average ReadReq mshr miss latency 1088system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 21072.886347 # average WriteReq mshr miss latency 1089system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 21072.886347 # average WriteReq mshr miss latency 1090system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8184.521207 # average LoadLockedReq mshr miss latency 1091system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8184.521207 # average LoadLockedReq mshr miss latency 1092system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4587.311969 # average StoreCondReq mshr miss latency 1093system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4587.311969 # average StoreCondReq mshr miss latency 1094system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14573.005146 # average overall mshr miss latency 1095system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14573.005146 # average overall mshr miss latency 1096system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14573.005146 # average overall mshr miss latency 1097system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14573.005146 # average overall mshr miss latency 1098system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 210328 # average ReadReq mshr uncacheable latency 1099system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 210328 # average ReadReq mshr uncacheable latency 1100system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 7520.308924 # average overall mshr uncacheable latency 1101system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 7520.308924 # average overall mshr uncacheable latency 1102system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states 1103system.cpu1.icache.tags.replacements 326538 # number of replacements 1104system.cpu1.icache.tags.tagsinuse 445.783445 # Cycle average of tags in use 1105system.cpu1.icache.tags.total_refs 12944535 # Total number of references to valid blocks. 1106system.cpu1.icache.tags.sampled_refs 327049 # Sample count of references to valid blocks. 1107system.cpu1.icache.tags.avg_refs 39.579803 # Average number of references to valid blocks. 1108system.cpu1.icache.tags.warmup_cycle 1960887554500 # Cycle when the warmup percentage was hit. 1109system.cpu1.icache.tags.occ_blocks::cpu1.inst 445.783445 # Average occupied blocks per requestor 1110system.cpu1.icache.tags.occ_percent::cpu1.inst 0.870671 # Average percentage of cache occupancy 1111system.cpu1.icache.tags.occ_percent::total 0.870671 # Average percentage of cache occupancy 1112system.cpu1.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 1113system.cpu1.icache.tags.age_task_id_blocks_1024::2 75 # Occupied blocks per task id 1114system.cpu1.icache.tags.age_task_id_blocks_1024::3 434 # Occupied blocks per task id 1115system.cpu1.icache.tags.age_task_id_blocks_1024::4 2 # Occupied blocks per task id 1116system.cpu1.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id 1117system.cpu1.icache.tags.tag_accesses 13598713 # Number of tag accesses 1118system.cpu1.icache.tags.data_accesses 13598713 # Number of data accesses 1119system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states 1120system.cpu1.icache.ReadReq_hits::cpu1.inst 12944535 # number of ReadReq hits 1121system.cpu1.icache.ReadReq_hits::total 12944535 # number of ReadReq hits 1122system.cpu1.icache.demand_hits::cpu1.inst 12944535 # number of demand (read+write) hits 1123system.cpu1.icache.demand_hits::total 12944535 # number of demand (read+write) hits 1124system.cpu1.icache.overall_hits::cpu1.inst 12944535 # number of overall hits 1125system.cpu1.icache.overall_hits::total 12944535 # number of overall hits 1126system.cpu1.icache.ReadReq_misses::cpu1.inst 327089 # number of ReadReq misses 1127system.cpu1.icache.ReadReq_misses::total 327089 # number of ReadReq misses 1128system.cpu1.icache.demand_misses::cpu1.inst 327089 # number of demand (read+write) misses 1129system.cpu1.icache.demand_misses::total 327089 # number of demand (read+write) misses 1130system.cpu1.icache.overall_misses::cpu1.inst 327089 # number of overall misses 1131system.cpu1.icache.overall_misses::total 327089 # number of overall misses 1132system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4450039000 # number of ReadReq miss cycles 1133system.cpu1.icache.ReadReq_miss_latency::total 4450039000 # number of ReadReq miss cycles 1134system.cpu1.icache.demand_miss_latency::cpu1.inst 4450039000 # number of demand (read+write) miss cycles 1135system.cpu1.icache.demand_miss_latency::total 4450039000 # number of demand (read+write) miss cycles 1136system.cpu1.icache.overall_miss_latency::cpu1.inst 4450039000 # number of overall miss cycles 1137system.cpu1.icache.overall_miss_latency::total 4450039000 # number of overall miss cycles 1138system.cpu1.icache.ReadReq_accesses::cpu1.inst 13271624 # number of ReadReq accesses(hits+misses) 1139system.cpu1.icache.ReadReq_accesses::total 13271624 # number of ReadReq accesses(hits+misses) 1140system.cpu1.icache.demand_accesses::cpu1.inst 13271624 # number of demand (read+write) accesses 1141system.cpu1.icache.demand_accesses::total 13271624 # number of demand (read+write) accesses 1142system.cpu1.icache.overall_accesses::cpu1.inst 13271624 # number of overall (read+write) accesses 1143system.cpu1.icache.overall_accesses::total 13271624 # number of overall (read+write) accesses 1144system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024646 # miss rate for ReadReq accesses 1145system.cpu1.icache.ReadReq_miss_rate::total 0.024646 # miss rate for ReadReq accesses 1146system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024646 # miss rate for demand accesses 1147system.cpu1.icache.demand_miss_rate::total 0.024646 # miss rate for demand accesses 1148system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024646 # miss rate for overall accesses 1149system.cpu1.icache.overall_miss_rate::total 0.024646 # miss rate for overall accesses 1150system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13604.979073 # average ReadReq miss latency 1151system.cpu1.icache.ReadReq_avg_miss_latency::total 13604.979073 # average ReadReq miss latency 1152system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13604.979073 # average overall miss latency 1153system.cpu1.icache.demand_avg_miss_latency::total 13604.979073 # average overall miss latency 1154system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13604.979073 # average overall miss latency 1155system.cpu1.icache.overall_avg_miss_latency::total 13604.979073 # average overall miss latency 1156system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1157system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1158system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1159system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1160system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1161system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1162system.cpu1.icache.writebacks::writebacks 326538 # number of writebacks 1163system.cpu1.icache.writebacks::total 326538 # number of writebacks 1164system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 327089 # number of ReadReq MSHR misses 1165system.cpu1.icache.ReadReq_mshr_misses::total 327089 # number of ReadReq MSHR misses 1166system.cpu1.icache.demand_mshr_misses::cpu1.inst 327089 # number of demand (read+write) MSHR misses 1167system.cpu1.icache.demand_mshr_misses::total 327089 # number of demand (read+write) MSHR misses 1168system.cpu1.icache.overall_mshr_misses::cpu1.inst 327089 # number of overall MSHR misses 1169system.cpu1.icache.overall_mshr_misses::total 327089 # number of overall MSHR misses 1170system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4122950000 # number of ReadReq MSHR miss cycles 1171system.cpu1.icache.ReadReq_mshr_miss_latency::total 4122950000 # number of ReadReq MSHR miss cycles 1172system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4122950000 # number of demand (read+write) MSHR miss cycles 1173system.cpu1.icache.demand_mshr_miss_latency::total 4122950000 # number of demand (read+write) MSHR miss cycles 1174system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4122950000 # number of overall MSHR miss cycles 1175system.cpu1.icache.overall_mshr_miss_latency::total 4122950000 # number of overall MSHR miss cycles 1176system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024646 # mshr miss rate for ReadReq accesses 1177system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024646 # mshr miss rate for ReadReq accesses 1178system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024646 # mshr miss rate for demand accesses 1179system.cpu1.icache.demand_mshr_miss_rate::total 0.024646 # mshr miss rate for demand accesses 1180system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024646 # mshr miss rate for overall accesses 1181system.cpu1.icache.overall_mshr_miss_rate::total 0.024646 # mshr miss rate for overall accesses 1182system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12604.979073 # average ReadReq mshr miss latency 1183system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12604.979073 # average ReadReq mshr miss latency 1184system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12604.979073 # average overall mshr miss latency 1185system.cpu1.icache.demand_avg_mshr_miss_latency::total 12604.979073 # average overall mshr miss latency 1186system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12604.979073 # average overall mshr miss latency 1187system.cpu1.icache.overall_avg_mshr_miss_latency::total 12604.979073 # average overall mshr miss latency 1188system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1189system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 1190system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 1191system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 1192system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 1193system.disk0.dma_write_txs 395 # Number of DMA write transactions. 1194system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1195system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1196system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1197system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 1198system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 1199system.disk2.dma_write_txs 1 # Number of DMA write transactions. 1200system.iobus.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states 1201system.iobus.trans_dist::ReadReq 7376 # Transaction distribution 1202system.iobus.trans_dist::ReadResp 7376 # Transaction distribution 1203system.iobus.trans_dist::WriteReq 55675 # Transaction distribution 1204system.iobus.trans_dist::WriteResp 55675 # Transaction distribution 1205system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14036 # Packet count per connected master and slave (bytes) 1206system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1010 # Packet count per connected master and slave (bytes) 1207system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 1208system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 1209system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 1210system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) 1211system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2474 # Packet count per connected master and slave (bytes) 1212system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 1213system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 1214system.iobus.pkt_count_system.bridge.master::total 42642 # Packet count per connected master and slave (bytes) 1215system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83460 # Packet count per connected master and slave (bytes) 1216system.iobus.pkt_count_system.tsunami.ide.dma::total 83460 # Packet count per connected master and slave (bytes) 1217system.iobus.pkt_count::total 126102 # Packet count per connected master and slave (bytes) 1218system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 56144 # Cumulative packet size per connected master and slave (bytes) 1219system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2733 # Cumulative packet size per connected master and slave (bytes) 1220system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 1221system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 1222system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 1223system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) 1224system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9876 # Cumulative packet size per connected master and slave (bytes) 1225system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 1226system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 1227system.iobus.pkt_size_system.bridge.master::total 82394 # Cumulative packet size per connected master and slave (bytes) 1228system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661648 # Cumulative packet size per connected master and slave (bytes) 1229system.iobus.pkt_size_system.tsunami.ide.dma::total 2661648 # Cumulative packet size per connected master and slave (bytes) 1230system.iobus.pkt_size::total 2744042 # Cumulative packet size per connected master and slave (bytes) 1231system.iobus.reqLayer0.occupancy 15108500 # Layer occupancy (ticks) 1232system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1233system.iobus.reqLayer1.occupancy 758000 # Layer occupancy (ticks) 1234system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1235system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks) 1236system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1237system.iobus.reqLayer6.occupancy 10000 # Layer occupancy (ticks) 1238system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1239system.iobus.reqLayer22.occupancy 174000 # Layer occupancy (ticks) 1240system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 1241system.iobus.reqLayer23.occupancy 15840500 # Layer occupancy (ticks) 1242system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1243system.iobus.reqLayer24.occupancy 2459000 # Layer occupancy (ticks) 1244system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1245system.iobus.reqLayer25.occupancy 6051000 # Layer occupancy (ticks) 1246system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1247system.iobus.reqLayer26.occupancy 82500 # Layer occupancy (ticks) 1248system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1249system.iobus.reqLayer27.occupancy 216235265 # Layer occupancy (ticks) 1250system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1251system.iobus.respLayer0.occupancy 28519000 # Layer occupancy (ticks) 1252system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1253system.iobus.respLayer1.occupancy 41956000 # Layer occupancy (ticks) 1254system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 1255system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states 1256system.iocache.tags.replacements 41698 # number of replacements 1257system.iocache.tags.tagsinuse 0.568421 # Cycle average of tags in use 1258system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1259system.iocache.tags.sampled_refs 41714 # Sample count of references to valid blocks. 1260system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1261system.iocache.tags.warmup_cycle 1760410342000 # Cycle when the warmup percentage was hit. 1262system.iocache.tags.occ_blocks::tsunami.ide 0.568421 # Average occupied blocks per requestor 1263system.iocache.tags.occ_percent::tsunami.ide 0.035526 # Average percentage of cache occupancy 1264system.iocache.tags.occ_percent::total 0.035526 # Average percentage of cache occupancy 1265system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1266system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1267system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1268system.iocache.tags.tag_accesses 375570 # Number of tag accesses 1269system.iocache.tags.data_accesses 375570 # Number of data accesses 1270system.iocache.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states 1271system.iocache.ReadReq_misses::tsunami.ide 178 # number of ReadReq misses 1272system.iocache.ReadReq_misses::total 178 # number of ReadReq misses 1273system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 1274system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses 1275system.iocache.demand_misses::tsunami.ide 41730 # number of demand (read+write) misses 1276system.iocache.demand_misses::total 41730 # number of demand (read+write) misses 1277system.iocache.overall_misses::tsunami.ide 41730 # number of overall misses 1278system.iocache.overall_misses::total 41730 # number of overall misses 1279system.iocache.ReadReq_miss_latency::tsunami.ide 22412883 # number of ReadReq miss cycles 1280system.iocache.ReadReq_miss_latency::total 22412883 # number of ReadReq miss cycles 1281system.iocache.WriteLineReq_miss_latency::tsunami.ide 4956087382 # number of WriteLineReq miss cycles 1282system.iocache.WriteLineReq_miss_latency::total 4956087382 # number of WriteLineReq miss cycles 1283system.iocache.demand_miss_latency::tsunami.ide 4978500265 # number of demand (read+write) miss cycles 1284system.iocache.demand_miss_latency::total 4978500265 # number of demand (read+write) miss cycles 1285system.iocache.overall_miss_latency::tsunami.ide 4978500265 # number of overall miss cycles 1286system.iocache.overall_miss_latency::total 4978500265 # number of overall miss cycles 1287system.iocache.ReadReq_accesses::tsunami.ide 178 # number of ReadReq accesses(hits+misses) 1288system.iocache.ReadReq_accesses::total 178 # number of ReadReq accesses(hits+misses) 1289system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) 1290system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) 1291system.iocache.demand_accesses::tsunami.ide 41730 # number of demand (read+write) accesses 1292system.iocache.demand_accesses::total 41730 # number of demand (read+write) accesses 1293system.iocache.overall_accesses::tsunami.ide 41730 # number of overall (read+write) accesses 1294system.iocache.overall_accesses::total 41730 # number of overall (read+write) accesses 1295system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 1296system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1297system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses 1298system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1299system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 1300system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1301system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 1302system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1303system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125915.073034 # average ReadReq miss latency 1304system.iocache.ReadReq_avg_miss_latency::total 125915.073034 # average ReadReq miss latency 1305system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 119274.340152 # average WriteLineReq miss latency 1306system.iocache.WriteLineReq_avg_miss_latency::total 119274.340152 # average WriteLineReq miss latency 1307system.iocache.demand_avg_miss_latency::tsunami.ide 119302.666307 # average overall miss latency 1308system.iocache.demand_avg_miss_latency::total 119302.666307 # average overall miss latency 1309system.iocache.overall_avg_miss_latency::tsunami.ide 119302.666307 # average overall miss latency 1310system.iocache.overall_avg_miss_latency::total 119302.666307 # average overall miss latency 1311system.iocache.blocked_cycles::no_mshrs 1665 # number of cycles access was blocked 1312system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1313system.iocache.blocked::no_mshrs 10 # number of cycles access was blocked 1314system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1315system.iocache.avg_blocked_cycles::no_mshrs 166.500000 # average number of cycles each access was blocked 1316system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1317system.iocache.writebacks::writebacks 41520 # number of writebacks 1318system.iocache.writebacks::total 41520 # number of writebacks 1319system.iocache.ReadReq_mshr_misses::tsunami.ide 178 # number of ReadReq MSHR misses 1320system.iocache.ReadReq_mshr_misses::total 178 # number of ReadReq MSHR misses 1321system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses 1322system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses 1323system.iocache.demand_mshr_misses::tsunami.ide 41730 # number of demand (read+write) MSHR misses 1324system.iocache.demand_mshr_misses::total 41730 # number of demand (read+write) MSHR misses 1325system.iocache.overall_mshr_misses::tsunami.ide 41730 # number of overall MSHR misses 1326system.iocache.overall_mshr_misses::total 41730 # number of overall MSHR misses 1327system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13512883 # number of ReadReq MSHR miss cycles 1328system.iocache.ReadReq_mshr_miss_latency::total 13512883 # number of ReadReq MSHR miss cycles 1329system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2876027417 # number of WriteLineReq MSHR miss cycles 1330system.iocache.WriteLineReq_mshr_miss_latency::total 2876027417 # number of WriteLineReq MSHR miss cycles 1331system.iocache.demand_mshr_miss_latency::tsunami.ide 2889540300 # number of demand (read+write) MSHR miss cycles 1332system.iocache.demand_mshr_miss_latency::total 2889540300 # number of demand (read+write) MSHR miss cycles 1333system.iocache.overall_mshr_miss_latency::tsunami.ide 2889540300 # number of overall MSHR miss cycles 1334system.iocache.overall_mshr_miss_latency::total 2889540300 # number of overall MSHR miss cycles 1335system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 1336system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1337system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses 1338system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1339system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 1340system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1341system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 1342system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1343system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75915.073034 # average ReadReq mshr miss latency 1344system.iocache.ReadReq_avg_mshr_miss_latency::total 75915.073034 # average ReadReq mshr miss latency 1345system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 69215.138068 # average WriteLineReq mshr miss latency 1346system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69215.138068 # average WriteLineReq mshr miss latency 1347system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 69243.716751 # average overall mshr miss latency 1348system.iocache.demand_avg_mshr_miss_latency::total 69243.716751 # average overall mshr miss latency 1349system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 69243.716751 # average overall mshr miss latency 1350system.iocache.overall_avg_mshr_miss_latency::total 69243.716751 # average overall mshr miss latency 1351system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states 1352system.l2c.tags.replacements 342937 # number of replacements 1353system.l2c.tags.tagsinuse 65389.954388 # Cycle average of tags in use 1354system.l2c.tags.total_refs 3989146 # Total number of references to valid blocks. 1355system.l2c.tags.sampled_refs 408458 # Sample count of references to valid blocks. 1356system.l2c.tags.avg_refs 9.766355 # Average number of references to valid blocks. 1357system.l2c.tags.warmup_cycle 7750506000 # Cycle when the warmup percentage was hit. 1358system.l2c.tags.occ_blocks::writebacks 285.827023 # Average occupied blocks per requestor 1359system.l2c.tags.occ_blocks::cpu0.inst 4791.190703 # Average occupied blocks per requestor 1360system.l2c.tags.occ_blocks::cpu0.data 59306.187710 # Average occupied blocks per requestor 1361system.l2c.tags.occ_blocks::cpu1.inst 166.825599 # Average occupied blocks per requestor 1362system.l2c.tags.occ_blocks::cpu1.data 839.923352 # Average occupied blocks per requestor 1363system.l2c.tags.occ_percent::writebacks 0.004361 # Average percentage of cache occupancy 1364system.l2c.tags.occ_percent::cpu0.inst 0.073108 # Average percentage of cache occupancy 1365system.l2c.tags.occ_percent::cpu0.data 0.904941 # Average percentage of cache occupancy 1366system.l2c.tags.occ_percent::cpu1.inst 0.002546 # Average percentage of cache occupancy 1367system.l2c.tags.occ_percent::cpu1.data 0.012816 # Average percentage of cache occupancy 1368system.l2c.tags.occ_percent::total 0.997772 # Average percentage of cache occupancy 1369system.l2c.tags.occ_task_id_blocks::1024 65521 # Occupied blocks per task id 1370system.l2c.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id 1371system.l2c.tags.age_task_id_blocks_1024::1 697 # Occupied blocks per task id 1372system.l2c.tags.age_task_id_blocks_1024::2 1597 # Occupied blocks per task id 1373system.l2c.tags.age_task_id_blocks_1024::3 6182 # Occupied blocks per task id 1374system.l2c.tags.age_task_id_blocks_1024::4 57022 # Occupied blocks per task id 1375system.l2c.tags.occ_task_id_percent::1024 0.999771 # Percentage of cache occupancy per task id 1376system.l2c.tags.tag_accesses 35591920 # Number of tag accesses 1377system.l2c.tags.data_accesses 35591920 # Number of data accesses 1378system.l2c.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states 1379system.l2c.WritebackDirty_hits::writebacks 792871 # number of WritebackDirty hits 1380system.l2c.WritebackDirty_hits::total 792871 # number of WritebackDirty hits 1381system.l2c.WritebackClean_hits::writebacks 746791 # number of WritebackClean hits 1382system.l2c.WritebackClean_hits::total 746791 # number of WritebackClean hits 1383system.l2c.UpgradeReq_hits::cpu0.data 3150 # number of UpgradeReq hits 1384system.l2c.UpgradeReq_hits::cpu1.data 2355 # number of UpgradeReq hits 1385system.l2c.UpgradeReq_hits::total 5505 # number of UpgradeReq hits 1386system.l2c.SCUpgradeReq_hits::cpu0.data 947 # number of SCUpgradeReq hits 1387system.l2c.SCUpgradeReq_hits::cpu1.data 959 # number of SCUpgradeReq hits 1388system.l2c.SCUpgradeReq_hits::total 1906 # number of SCUpgradeReq hits 1389system.l2c.ReadExReq_hits::cpu0.data 128503 # number of ReadExReq hits 1390system.l2c.ReadExReq_hits::cpu1.data 43274 # number of ReadExReq hits 1391system.l2c.ReadExReq_hits::total 171777 # number of ReadExReq hits 1392system.l2c.ReadCleanReq_hits::cpu0.inst 680173 # number of ReadCleanReq hits 1393system.l2c.ReadCleanReq_hits::cpu1.inst 326101 # number of ReadCleanReq hits 1394system.l2c.ReadCleanReq_hits::total 1006274 # number of ReadCleanReq hits 1395system.l2c.ReadSharedReq_hits::cpu0.data 663284 # number of ReadSharedReq hits 1396system.l2c.ReadSharedReq_hits::cpu1.data 108416 # number of ReadSharedReq hits 1397system.l2c.ReadSharedReq_hits::total 771700 # number of ReadSharedReq hits 1398system.l2c.demand_hits::cpu0.inst 680173 # number of demand (read+write) hits 1399system.l2c.demand_hits::cpu0.data 791787 # number of demand (read+write) hits 1400system.l2c.demand_hits::cpu1.inst 326101 # number of demand (read+write) hits 1401system.l2c.demand_hits::cpu1.data 151690 # number of demand (read+write) hits 1402system.l2c.demand_hits::total 1949751 # number of demand (read+write) hits 1403system.l2c.overall_hits::cpu0.inst 680173 # number of overall hits 1404system.l2c.overall_hits::cpu0.data 791787 # number of overall hits 1405system.l2c.overall_hits::cpu1.inst 326101 # number of overall hits 1406system.l2c.overall_hits::cpu1.data 151690 # number of overall hits 1407system.l2c.overall_hits::total 1949751 # number of overall hits 1408system.l2c.UpgradeReq_misses::cpu0.data 5 # number of UpgradeReq misses 1409system.l2c.UpgradeReq_misses::cpu1.data 1 # number of UpgradeReq misses 1410system.l2c.UpgradeReq_misses::total 6 # number of UpgradeReq misses 1411system.l2c.ReadExReq_misses::cpu0.data 116830 # number of ReadExReq misses 1412system.l2c.ReadExReq_misses::cpu1.data 6419 # number of ReadExReq misses 1413system.l2c.ReadExReq_misses::total 123249 # number of ReadExReq misses 1414system.l2c.ReadCleanReq_misses::cpu0.inst 12445 # number of ReadCleanReq misses 1415system.l2c.ReadCleanReq_misses::cpu1.inst 987 # number of ReadCleanReq misses 1416system.l2c.ReadCleanReq_misses::total 13432 # number of ReadCleanReq misses 1417system.l2c.ReadSharedReq_misses::cpu0.data 271517 # number of ReadSharedReq misses 1418system.l2c.ReadSharedReq_misses::cpu1.data 340 # number of ReadSharedReq misses 1419system.l2c.ReadSharedReq_misses::total 271857 # number of ReadSharedReq misses 1420system.l2c.demand_misses::cpu0.inst 12445 # number of demand (read+write) misses 1421system.l2c.demand_misses::cpu0.data 388347 # number of demand (read+write) misses 1422system.l2c.demand_misses::cpu1.inst 987 # number of demand (read+write) misses 1423system.l2c.demand_misses::cpu1.data 6759 # number of demand (read+write) misses 1424system.l2c.demand_misses::total 408538 # number of demand (read+write) misses 1425system.l2c.overall_misses::cpu0.inst 12445 # number of overall misses 1426system.l2c.overall_misses::cpu0.data 388347 # number of overall misses 1427system.l2c.overall_misses::cpu1.inst 987 # number of overall misses 1428system.l2c.overall_misses::cpu1.data 6759 # number of overall misses 1429system.l2c.overall_misses::total 408538 # number of overall misses 1430system.l2c.UpgradeReq_miss_latency::cpu0.data 300000 # number of UpgradeReq miss cycles 1431system.l2c.UpgradeReq_miss_latency::cpu1.data 28500 # number of UpgradeReq miss cycles 1432system.l2c.UpgradeReq_miss_latency::total 328500 # number of UpgradeReq miss cycles 1433system.l2c.ReadExReq_miss_latency::cpu0.data 10622495500 # number of ReadExReq miss cycles 1434system.l2c.ReadExReq_miss_latency::cpu1.data 657559500 # number of ReadExReq miss cycles 1435system.l2c.ReadExReq_miss_latency::total 11280055000 # number of ReadExReq miss cycles 1436system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1281839000 # number of ReadCleanReq miss cycles 1437system.l2c.ReadCleanReq_miss_latency::cpu1.inst 101239000 # number of ReadCleanReq miss cycles 1438system.l2c.ReadCleanReq_miss_latency::total 1383078000 # number of ReadCleanReq miss cycles 1439system.l2c.ReadSharedReq_miss_latency::cpu0.data 21946509000 # number of ReadSharedReq miss cycles 1440system.l2c.ReadSharedReq_miss_latency::cpu1.data 42090000 # number of ReadSharedReq miss cycles 1441system.l2c.ReadSharedReq_miss_latency::total 21988599000 # number of ReadSharedReq miss cycles 1442system.l2c.demand_miss_latency::cpu0.inst 1281839000 # number of demand (read+write) miss cycles 1443system.l2c.demand_miss_latency::cpu0.data 32569004500 # number of demand (read+write) miss cycles 1444system.l2c.demand_miss_latency::cpu1.inst 101239000 # number of demand (read+write) miss cycles 1445system.l2c.demand_miss_latency::cpu1.data 699649500 # number of demand (read+write) miss cycles 1446system.l2c.demand_miss_latency::total 34651732000 # number of demand (read+write) miss cycles 1447system.l2c.overall_miss_latency::cpu0.inst 1281839000 # number of overall miss cycles 1448system.l2c.overall_miss_latency::cpu0.data 32569004500 # number of overall miss cycles 1449system.l2c.overall_miss_latency::cpu1.inst 101239000 # number of overall miss cycles 1450system.l2c.overall_miss_latency::cpu1.data 699649500 # number of overall miss cycles 1451system.l2c.overall_miss_latency::total 34651732000 # number of overall miss cycles 1452system.l2c.WritebackDirty_accesses::writebacks 792871 # number of WritebackDirty accesses(hits+misses) 1453system.l2c.WritebackDirty_accesses::total 792871 # number of WritebackDirty accesses(hits+misses) 1454system.l2c.WritebackClean_accesses::writebacks 746791 # number of WritebackClean accesses(hits+misses) 1455system.l2c.WritebackClean_accesses::total 746791 # number of WritebackClean accesses(hits+misses) 1456system.l2c.UpgradeReq_accesses::cpu0.data 3155 # number of UpgradeReq accesses(hits+misses) 1457system.l2c.UpgradeReq_accesses::cpu1.data 2356 # number of UpgradeReq accesses(hits+misses) 1458system.l2c.UpgradeReq_accesses::total 5511 # number of UpgradeReq accesses(hits+misses) 1459system.l2c.SCUpgradeReq_accesses::cpu0.data 947 # number of SCUpgradeReq accesses(hits+misses) 1460system.l2c.SCUpgradeReq_accesses::cpu1.data 959 # number of SCUpgradeReq accesses(hits+misses) 1461system.l2c.SCUpgradeReq_accesses::total 1906 # number of SCUpgradeReq accesses(hits+misses) 1462system.l2c.ReadExReq_accesses::cpu0.data 245333 # number of ReadExReq accesses(hits+misses) 1463system.l2c.ReadExReq_accesses::cpu1.data 49693 # number of ReadExReq accesses(hits+misses) 1464system.l2c.ReadExReq_accesses::total 295026 # number of ReadExReq accesses(hits+misses) 1465system.l2c.ReadCleanReq_accesses::cpu0.inst 692618 # number of ReadCleanReq accesses(hits+misses) 1466system.l2c.ReadCleanReq_accesses::cpu1.inst 327088 # number of ReadCleanReq accesses(hits+misses) 1467system.l2c.ReadCleanReq_accesses::total 1019706 # number of ReadCleanReq accesses(hits+misses) 1468system.l2c.ReadSharedReq_accesses::cpu0.data 934801 # number of ReadSharedReq accesses(hits+misses) 1469system.l2c.ReadSharedReq_accesses::cpu1.data 108756 # number of ReadSharedReq accesses(hits+misses) 1470system.l2c.ReadSharedReq_accesses::total 1043557 # number of ReadSharedReq accesses(hits+misses) 1471system.l2c.demand_accesses::cpu0.inst 692618 # number of demand (read+write) accesses 1472system.l2c.demand_accesses::cpu0.data 1180134 # number of demand (read+write) accesses 1473system.l2c.demand_accesses::cpu1.inst 327088 # number of demand (read+write) accesses 1474system.l2c.demand_accesses::cpu1.data 158449 # number of demand (read+write) accesses 1475system.l2c.demand_accesses::total 2358289 # number of demand (read+write) accesses 1476system.l2c.overall_accesses::cpu0.inst 692618 # number of overall (read+write) accesses 1477system.l2c.overall_accesses::cpu0.data 1180134 # number of overall (read+write) accesses 1478system.l2c.overall_accesses::cpu1.inst 327088 # number of overall (read+write) accesses 1479system.l2c.overall_accesses::cpu1.data 158449 # number of overall (read+write) accesses 1480system.l2c.overall_accesses::total 2358289 # number of overall (read+write) accesses 1481system.l2c.UpgradeReq_miss_rate::cpu0.data 0.001585 # miss rate for UpgradeReq accesses 1482system.l2c.UpgradeReq_miss_rate::cpu1.data 0.000424 # miss rate for UpgradeReq accesses 1483system.l2c.UpgradeReq_miss_rate::total 0.001089 # miss rate for UpgradeReq accesses 1484system.l2c.ReadExReq_miss_rate::cpu0.data 0.476210 # miss rate for ReadExReq accesses 1485system.l2c.ReadExReq_miss_rate::cpu1.data 0.129173 # miss rate for ReadExReq accesses 1486system.l2c.ReadExReq_miss_rate::total 0.417756 # miss rate for ReadExReq accesses 1487system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.017968 # miss rate for ReadCleanReq accesses 1488system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.003018 # miss rate for ReadCleanReq accesses 1489system.l2c.ReadCleanReq_miss_rate::total 0.013172 # miss rate for ReadCleanReq accesses 1490system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.290454 # miss rate for ReadSharedReq accesses 1491system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.003126 # miss rate for ReadSharedReq accesses 1492system.l2c.ReadSharedReq_miss_rate::total 0.260510 # miss rate for ReadSharedReq accesses 1493system.l2c.demand_miss_rate::cpu0.inst 0.017968 # miss rate for demand accesses 1494system.l2c.demand_miss_rate::cpu0.data 0.329070 # miss rate for demand accesses 1495system.l2c.demand_miss_rate::cpu1.inst 0.003018 # miss rate for demand accesses 1496system.l2c.demand_miss_rate::cpu1.data 0.042657 # miss rate for demand accesses 1497system.l2c.demand_miss_rate::total 0.173235 # miss rate for demand accesses 1498system.l2c.overall_miss_rate::cpu0.inst 0.017968 # miss rate for overall accesses 1499system.l2c.overall_miss_rate::cpu0.data 0.329070 # miss rate for overall accesses 1500system.l2c.overall_miss_rate::cpu1.inst 0.003018 # miss rate for overall accesses 1501system.l2c.overall_miss_rate::cpu1.data 0.042657 # miss rate for overall accesses 1502system.l2c.overall_miss_rate::total 0.173235 # miss rate for overall accesses 1503system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 60000 # average UpgradeReq miss latency 1504system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 28500 # average UpgradeReq miss latency 1505system.l2c.UpgradeReq_avg_miss_latency::total 54750 # average UpgradeReq miss latency 1506system.l2c.ReadExReq_avg_miss_latency::cpu0.data 90922.669691 # average ReadExReq miss latency 1507system.l2c.ReadExReq_avg_miss_latency::cpu1.data 102439.554448 # average ReadExReq miss latency 1508system.l2c.ReadExReq_avg_miss_latency::total 91522.486998 # average ReadExReq miss latency 1509system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 103000.321414 # average ReadCleanReq miss latency 1510system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 102572.441743 # average ReadCleanReq miss latency 1511system.l2c.ReadCleanReq_avg_miss_latency::total 102968.880286 # average ReadCleanReq miss latency 1512system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 80829.226163 # average ReadSharedReq miss latency 1513system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 123794.117647 # average ReadSharedReq miss latency 1514system.l2c.ReadSharedReq_avg_miss_latency::total 80882.960527 # average ReadSharedReq miss latency 1515system.l2c.demand_avg_miss_latency::cpu0.inst 103000.321414 # average overall miss latency 1516system.l2c.demand_avg_miss_latency::cpu0.data 83865.729618 # average overall miss latency 1517system.l2c.demand_avg_miss_latency::cpu1.inst 102572.441743 # average overall miss latency 1518system.l2c.demand_avg_miss_latency::cpu1.data 103513.759432 # average overall miss latency 1519system.l2c.demand_avg_miss_latency::total 84818.871194 # average overall miss latency 1520system.l2c.overall_avg_miss_latency::cpu0.inst 103000.321414 # average overall miss latency 1521system.l2c.overall_avg_miss_latency::cpu0.data 83865.729618 # average overall miss latency 1522system.l2c.overall_avg_miss_latency::cpu1.inst 102572.441743 # average overall miss latency 1523system.l2c.overall_avg_miss_latency::cpu1.data 103513.759432 # average overall miss latency 1524system.l2c.overall_avg_miss_latency::total 84818.871194 # average overall miss latency 1525system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1526system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 1527system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 1528system.l2c.blocked::no_targets 0 # number of cycles access was blocked 1529system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1530system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1531system.l2c.writebacks::writebacks 79969 # number of writebacks 1532system.l2c.writebacks::total 79969 # number of writebacks 1533system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 11 # number of ReadCleanReq MSHR hits 1534system.l2c.ReadCleanReq_mshr_hits::total 11 # number of ReadCleanReq MSHR hits 1535system.l2c.demand_mshr_hits::cpu1.inst 11 # number of demand (read+write) MSHR hits 1536system.l2c.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits 1537system.l2c.overall_mshr_hits::cpu1.inst 11 # number of overall MSHR hits 1538system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits 1539system.l2c.CleanEvict_mshr_misses::writebacks 10 # number of CleanEvict MSHR misses 1540system.l2c.CleanEvict_mshr_misses::total 10 # number of CleanEvict MSHR misses 1541system.l2c.UpgradeReq_mshr_misses::cpu0.data 5 # number of UpgradeReq MSHR misses 1542system.l2c.UpgradeReq_mshr_misses::cpu1.data 1 # number of UpgradeReq MSHR misses 1543system.l2c.UpgradeReq_mshr_misses::total 6 # number of UpgradeReq MSHR misses 1544system.l2c.ReadExReq_mshr_misses::cpu0.data 116830 # number of ReadExReq MSHR misses 1545system.l2c.ReadExReq_mshr_misses::cpu1.data 6419 # number of ReadExReq MSHR misses 1546system.l2c.ReadExReq_mshr_misses::total 123249 # number of ReadExReq MSHR misses 1547system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 12445 # number of ReadCleanReq MSHR misses 1548system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 976 # number of ReadCleanReq MSHR misses 1549system.l2c.ReadCleanReq_mshr_misses::total 13421 # number of ReadCleanReq MSHR misses 1550system.l2c.ReadSharedReq_mshr_misses::cpu0.data 271517 # number of ReadSharedReq MSHR misses 1551system.l2c.ReadSharedReq_mshr_misses::cpu1.data 340 # number of ReadSharedReq MSHR misses 1552system.l2c.ReadSharedReq_mshr_misses::total 271857 # number of ReadSharedReq MSHR misses 1553system.l2c.demand_mshr_misses::cpu0.inst 12445 # number of demand (read+write) MSHR misses 1554system.l2c.demand_mshr_misses::cpu0.data 388347 # number of demand (read+write) MSHR misses 1555system.l2c.demand_mshr_misses::cpu1.inst 976 # number of demand (read+write) MSHR misses 1556system.l2c.demand_mshr_misses::cpu1.data 6759 # number of demand (read+write) MSHR misses 1557system.l2c.demand_mshr_misses::total 408527 # number of demand (read+write) MSHR misses 1558system.l2c.overall_mshr_misses::cpu0.inst 12445 # number of overall MSHR misses 1559system.l2c.overall_mshr_misses::cpu0.data 388347 # number of overall MSHR misses 1560system.l2c.overall_mshr_misses::cpu1.inst 976 # number of overall MSHR misses 1561system.l2c.overall_mshr_misses::cpu1.data 6759 # number of overall MSHR misses 1562system.l2c.overall_mshr_misses::total 408527 # number of overall MSHR misses 1563system.l2c.ReadReq_mshr_uncacheable::cpu0.data 7073 # number of ReadReq MSHR uncacheable 1564system.l2c.ReadReq_mshr_uncacheable::cpu1.data 125 # number of ReadReq MSHR uncacheable 1565system.l2c.ReadReq_mshr_uncacheable::total 7198 # number of ReadReq MSHR uncacheable 1566system.l2c.WriteReq_mshr_uncacheable::cpu0.data 10752 # number of WriteReq MSHR uncacheable 1567system.l2c.WriteReq_mshr_uncacheable::cpu1.data 3371 # number of WriteReq MSHR uncacheable 1568system.l2c.WriteReq_mshr_uncacheable::total 14123 # number of WriteReq MSHR uncacheable 1569system.l2c.overall_mshr_uncacheable_misses::cpu0.data 17825 # number of overall MSHR uncacheable misses 1570system.l2c.overall_mshr_uncacheable_misses::cpu1.data 3496 # number of overall MSHR uncacheable misses 1571system.l2c.overall_mshr_uncacheable_misses::total 21321 # number of overall MSHR uncacheable misses 1572system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 250000 # number of UpgradeReq MSHR miss cycles 1573system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 18500 # number of UpgradeReq MSHR miss cycles 1574system.l2c.UpgradeReq_mshr_miss_latency::total 268500 # number of UpgradeReq MSHR miss cycles 1575system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 9454195500 # number of ReadExReq MSHR miss cycles 1576system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 593369500 # number of ReadExReq MSHR miss cycles 1577system.l2c.ReadExReq_mshr_miss_latency::total 10047565000 # number of ReadExReq MSHR miss cycles 1578system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 1157389000 # number of ReadCleanReq MSHR miss cycles 1579system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 90609000 # number of ReadCleanReq MSHR miss cycles 1580system.l2c.ReadCleanReq_mshr_miss_latency::total 1247998000 # number of ReadCleanReq MSHR miss cycles 1581system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 19231339000 # number of ReadSharedReq MSHR miss cycles 1582system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 38690000 # number of ReadSharedReq MSHR miss cycles 1583system.l2c.ReadSharedReq_mshr_miss_latency::total 19270029000 # number of ReadSharedReq MSHR miss cycles 1584system.l2c.demand_mshr_miss_latency::cpu0.inst 1157389000 # number of demand (read+write) MSHR miss cycles 1585system.l2c.demand_mshr_miss_latency::cpu0.data 28685534500 # number of demand (read+write) MSHR miss cycles 1586system.l2c.demand_mshr_miss_latency::cpu1.inst 90609000 # number of demand (read+write) MSHR miss cycles 1587system.l2c.demand_mshr_miss_latency::cpu1.data 632059500 # number of demand (read+write) MSHR miss cycles 1588system.l2c.demand_mshr_miss_latency::total 30565592000 # number of demand (read+write) MSHR miss cycles 1589system.l2c.overall_mshr_miss_latency::cpu0.inst 1157389000 # number of overall MSHR miss cycles 1590system.l2c.overall_mshr_miss_latency::cpu0.data 28685534500 # number of overall MSHR miss cycles 1591system.l2c.overall_mshr_miss_latency::cpu1.inst 90609000 # number of overall MSHR miss cycles 1592system.l2c.overall_mshr_miss_latency::cpu1.data 632059500 # number of overall MSHR miss cycles 1593system.l2c.overall_mshr_miss_latency::total 30565592000 # number of overall MSHR miss cycles 1594system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1483681000 # number of ReadReq MSHR uncacheable cycles 1595system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 24728000 # number of ReadReq MSHR uncacheable cycles 1596system.l2c.ReadReq_mshr_uncacheable_latency::total 1508409000 # number of ReadReq MSHR uncacheable cycles 1597system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1483681000 # number of overall MSHR uncacheable cycles 1598system.l2c.overall_mshr_uncacheable_latency::cpu1.data 24728000 # number of overall MSHR uncacheable cycles 1599system.l2c.overall_mshr_uncacheable_latency::total 1508409000 # number of overall MSHR uncacheable cycles 1600system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 1601system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 1602system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.001585 # mshr miss rate for UpgradeReq accesses 1603system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.000424 # mshr miss rate for UpgradeReq accesses 1604system.l2c.UpgradeReq_mshr_miss_rate::total 0.001089 # mshr miss rate for UpgradeReq accesses 1605system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.476210 # mshr miss rate for ReadExReq accesses 1606system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.129173 # mshr miss rate for ReadExReq accesses 1607system.l2c.ReadExReq_mshr_miss_rate::total 0.417756 # mshr miss rate for ReadExReq accesses 1608system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.017968 # mshr miss rate for ReadCleanReq accesses 1609system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.002984 # mshr miss rate for ReadCleanReq accesses 1610system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013162 # mshr miss rate for ReadCleanReq accesses 1611system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.290454 # mshr miss rate for ReadSharedReq accesses 1612system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.003126 # mshr miss rate for ReadSharedReq accesses 1613system.l2c.ReadSharedReq_mshr_miss_rate::total 0.260510 # mshr miss rate for ReadSharedReq accesses 1614system.l2c.demand_mshr_miss_rate::cpu0.inst 0.017968 # mshr miss rate for demand accesses 1615system.l2c.demand_mshr_miss_rate::cpu0.data 0.329070 # mshr miss rate for demand accesses 1616system.l2c.demand_mshr_miss_rate::cpu1.inst 0.002984 # mshr miss rate for demand accesses 1617system.l2c.demand_mshr_miss_rate::cpu1.data 0.042657 # mshr miss rate for demand accesses 1618system.l2c.demand_mshr_miss_rate::total 0.173230 # mshr miss rate for demand accesses 1619system.l2c.overall_mshr_miss_rate::cpu0.inst 0.017968 # mshr miss rate for overall accesses 1620system.l2c.overall_mshr_miss_rate::cpu0.data 0.329070 # mshr miss rate for overall accesses 1621system.l2c.overall_mshr_miss_rate::cpu1.inst 0.002984 # mshr miss rate for overall accesses 1622system.l2c.overall_mshr_miss_rate::cpu1.data 0.042657 # mshr miss rate for overall accesses 1623system.l2c.overall_mshr_miss_rate::total 0.173230 # mshr miss rate for overall accesses 1624system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 50000 # average UpgradeReq mshr miss latency 1625system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18500 # average UpgradeReq mshr miss latency 1626system.l2c.UpgradeReq_avg_mshr_miss_latency::total 44750 # average UpgradeReq mshr miss latency 1627system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 80922.669691 # average ReadExReq mshr miss latency 1628system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 92439.554448 # average ReadExReq mshr miss latency 1629system.l2c.ReadExReq_avg_mshr_miss_latency::total 81522.486998 # average ReadExReq mshr miss latency 1630system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 93000.321414 # average ReadCleanReq mshr miss latency 1631system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 92837.090164 # average ReadCleanReq mshr miss latency 1632system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 92988.450935 # average ReadCleanReq mshr miss latency 1633system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 70829.226163 # average ReadSharedReq mshr miss latency 1634system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 113794.117647 # average ReadSharedReq mshr miss latency 1635system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 70882.960527 # average ReadSharedReq mshr miss latency 1636system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 93000.321414 # average overall mshr miss latency 1637system.l2c.demand_avg_mshr_miss_latency::cpu0.data 73865.729618 # average overall mshr miss latency 1638system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 92837.090164 # average overall mshr miss latency 1639system.l2c.demand_avg_mshr_miss_latency::cpu1.data 93513.759432 # average overall mshr miss latency 1640system.l2c.demand_avg_mshr_miss_latency::total 74819.025425 # average overall mshr miss latency 1641system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 93000.321414 # average overall mshr miss latency 1642system.l2c.overall_avg_mshr_miss_latency::cpu0.data 73865.729618 # average overall mshr miss latency 1643system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 92837.090164 # average overall mshr miss latency 1644system.l2c.overall_avg_mshr_miss_latency::cpu1.data 93513.759432 # average overall mshr miss latency 1645system.l2c.overall_avg_mshr_miss_latency::total 74819.025425 # average overall mshr miss latency 1646system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209766.859890 # average ReadReq mshr uncacheable latency 1647system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 197824 # average ReadReq mshr uncacheable latency 1648system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209559.460961 # average ReadReq mshr uncacheable latency 1649system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 83235.960729 # average overall mshr uncacheable latency 1650system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 7073.226545 # average overall mshr uncacheable latency 1651system.l2c.overall_avg_mshr_uncacheable_latency::total 70747.572816 # average overall mshr uncacheable latency 1652system.membus.snoop_filter.tot_requests 856503 # Total number of requests made to the snoop filter. 1653system.membus.snoop_filter.hit_single_requests 407142 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1654system.membus.snoop_filter.hit_multi_requests 413 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1655system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1656system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1657system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1658system.membus.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states 1659system.membus.trans_dist::ReadReq 7198 # Transaction distribution 1660system.membus.trans_dist::ReadResp 292654 # Transaction distribution 1661system.membus.trans_dist::WriteReq 14123 # Transaction distribution 1662system.membus.trans_dist::WriteResp 14123 # Transaction distribution 1663system.membus.trans_dist::WritebackDirty 121489 # Transaction distribution 1664system.membus.trans_dist::CleanEvict 262335 # Transaction distribution 1665system.membus.trans_dist::UpgradeReq 11693 # Transaction distribution 1666system.membus.trans_dist::SCUpgradeReq 9938 # Transaction distribution 1667system.membus.trans_dist::UpgradeResp 3 # Transaction distribution 1668system.membus.trans_dist::ReadExReq 123969 # Transaction distribution 1669system.membus.trans_dist::ReadExResp 123101 # Transaction distribution 1670system.membus.trans_dist::ReadSharedReq 285456 # Transaction distribution 1671system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution 1672system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42642 # Packet count per connected master and slave (bytes) 1673system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1181120 # Packet count per connected master and slave (bytes) 1674system.membus.pkt_count_system.l2c.mem_side::total 1223762 # Packet count per connected master and slave (bytes) 1675system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83443 # Packet count per connected master and slave (bytes) 1676system.membus.pkt_count_system.iocache.mem_side::total 83443 # Packet count per connected master and slave (bytes) 1677system.membus.pkt_count::total 1307205 # Packet count per connected master and slave (bytes) 1678system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 82394 # Cumulative packet size per connected master and slave (bytes) 1679system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31237440 # Cumulative packet size per connected master and slave (bytes) 1680system.membus.pkt_size_system.l2c.mem_side::total 31319834 # Cumulative packet size per connected master and slave (bytes) 1681system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) 1682system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) 1683system.membus.pkt_size::total 33978074 # Cumulative packet size per connected master and slave (bytes) 1684system.membus.snoops 22774 # Total snoops (count) 1685system.membus.snoopTraffic 27264 # Total snoop traffic (bytes) 1686system.membus.snoop_fanout::samples 493929 # Request fanout histogram 1687system.membus.snoop_fanout::mean 0.001371 # Request fanout histogram 1688system.membus.snoop_fanout::stdev 0.036997 # Request fanout histogram 1689system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1690system.membus.snoop_fanout::0 493252 99.86% 99.86% # Request fanout histogram 1691system.membus.snoop_fanout::1 677 0.14% 100.00% # Request fanout histogram 1692system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1693system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1694system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1695system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1696system.membus.snoop_fanout::total 493929 # Request fanout histogram 1697system.membus.reqLayer0.occupancy 40493000 # Layer occupancy (ticks) 1698system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1699system.membus.reqLayer1.occupancy 1323047597 # Layer occupancy (ticks) 1700system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 1701system.membus.respLayer1.occupancy 2182313750 # Layer occupancy (ticks) 1702system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 1703system.membus.respLayer2.occupancy 915117 # Layer occupancy (ticks) 1704system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1705system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states 1706system.toL2Bus.snoop_filter.tot_requests 4789247 # Total number of requests made to the snoop filter. 1707system.toL2Bus.snoop_filter.hit_single_requests 2394847 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1708system.toL2Bus.snoop_filter.hit_multi_requests 361788 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1709system.toL2Bus.snoop_filter.tot_snoops 989 # Total number of snoops made to the snoop filter. 1710system.toL2Bus.snoop_filter.hit_single_snoops 928 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1711system.toL2Bus.snoop_filter.hit_multi_snoops 61 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1712system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states 1713system.toL2Bus.trans_dist::ReadReq 7198 # Transaction distribution 1714system.toL2Bus.trans_dist::ReadResp 2106871 # Transaction distribution 1715system.toL2Bus.trans_dist::WriteReq 14123 # Transaction distribution 1716system.toL2Bus.trans_dist::WriteResp 14123 # Transaction distribution 1717system.toL2Bus.trans_dist::WritebackDirty 872840 # Transaction distribution 1718system.toL2Bus.trans_dist::WritebackClean 1018539 # Transaction distribution 1719system.toL2Bus.trans_dist::CleanEvict 815364 # Transaction distribution 1720system.toL2Bus.trans_dist::UpgradeReq 17050 # Transaction distribution 1721system.toL2Bus.trans_dist::SCUpgradeReq 11844 # Transaction distribution 1722system.toL2Bus.trans_dist::UpgradeResp 28894 # Transaction distribution 1723system.toL2Bus.trans_dist::ReadExReq 297037 # Transaction distribution 1724system.toL2Bus.trans_dist::ReadExResp 297037 # Transaction distribution 1725system.toL2Bus.trans_dist::ReadCleanReq 1019728 # Transaction distribution 1726system.toL2Bus.trans_dist::ReadSharedReq 1079947 # Transaction distribution 1727system.toL2Bus.trans_dist::InvalidateReq 246 # Transaction distribution 1728system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2077258 # Packet count per connected master and slave (bytes) 1729system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3616236 # Packet count per connected master and slave (bytes) 1730system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 980715 # Packet count per connected master and slave (bytes) 1731system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 523549 # Packet count per connected master and slave (bytes) 1732system.toL2Bus.pkt_count::total 7197758 # Packet count per connected master and slave (bytes) 1733system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 88615616 # Cumulative packet size per connected master and slave (bytes) 1734system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119196292 # Cumulative packet size per connected master and slave (bytes) 1735system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 41832064 # Cumulative packet size per connected master and slave (bytes) 1736system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17309590 # Cumulative packet size per connected master and slave (bytes) 1737system.toL2Bus.pkt_size::total 266953562 # Cumulative packet size per connected master and slave (bytes) 1738system.toL2Bus.snoops 403246 # Total snoops (count) 1739system.toL2Bus.snoopTraffic 7576960 # Total snoop traffic (bytes) 1740system.toL2Bus.snoop_fanout::samples 2790110 # Request fanout histogram 1741system.toL2Bus.snoop_fanout::mean 0.141029 # Request fanout histogram 1742system.toL2Bus.snoop_fanout::stdev 0.348296 # Request fanout histogram 1743system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1744system.toL2Bus.snoop_fanout::0 2396861 85.91% 85.91% # Request fanout histogram 1745system.toL2Bus.snoop_fanout::1 393013 14.09% 99.99% # Request fanout histogram 1746system.toL2Bus.snoop_fanout::2 235 0.01% 100.00% # Request fanout histogram 1747system.toL2Bus.snoop_fanout::3 1 0.00% 100.00% # Request fanout histogram 1748system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram 1749system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1750system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1751system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram 1752system.toL2Bus.snoop_fanout::total 2790110 # Request fanout histogram 1753system.toL2Bus.reqLayer0.occupancy 4223757496 # Layer occupancy (ticks) 1754system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 1755system.toL2Bus.snoopLayer0.occupancy 302383 # Layer occupancy (ticks) 1756system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1757system.toL2Bus.respLayer0.occupancy 1039141633 # Layer occupancy (ticks) 1758system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1759system.toL2Bus.respLayer1.occupancy 1817975093 # Layer occupancy (ticks) 1760system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1761system.toL2Bus.respLayer2.occupancy 491872018 # Layer occupancy (ticks) 1762system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1763system.toL2Bus.respLayer3.occupancy 276251327 # Layer occupancy (ticks) 1764system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1765system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states 1766system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states 1767system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states 1768system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states 1769system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1770system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1771system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1772system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1773system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1774system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1775system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 1776system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1777system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 1778system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1779system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1780system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 1781system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1782system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1783system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 1784system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1785system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1786system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 1787system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1788system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1789system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 1790system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1791system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1792system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1793system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1794system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1795system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1796system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1797system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1798system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 1799system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 1800system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states 1801system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states 1802system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states 1803system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states 1804system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states 1805system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states 1806system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states 1807system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states 1808system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states 1809system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states 1810system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states 1811system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states 1812system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states 1813system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states 1814system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states 1815system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states 1816system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states 1817system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states 1818system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states 1819system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states 1820system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states 1821system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states 1822system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states 1823 1824---------- End Simulation Statistics ---------- 1825