stats.txt revision 11336:b318499f676c
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.982593 # Number of seconds simulated 4sim_ticks 1982593132000 # Number of ticks simulated 5final_tick 1982593132000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1109655 # Simulator instruction rate (inst/s) 8host_op_rate 1109654 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 36063876778 # Simulator tick rate (ticks/s) 10host_mem_usage 333984 # Number of bytes of host memory used 11host_seconds 54.97 # Real time elapsed on the host 12sim_insts 61002651 # Number of instructions simulated 13sim_ops 61002651 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.inst 800256 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.data 24686464 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.inst 59392 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.data 523264 # Number of bytes read from this memory 20system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 21system.physmem.bytes_read::total 26070336 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu0.inst 800256 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::cpu1.inst 59392 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::total 859648 # Number of instructions bytes read from this memory 25system.physmem.bytes_written::writebacks 7739904 # Number of bytes written to this memory 26system.physmem.bytes_written::total 7739904 # Number of bytes written to this memory 27system.physmem.num_reads::cpu0.inst 12504 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu0.data 385726 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu1.inst 928 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu1.data 8176 # Number of read requests responded to by this memory 31system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory 32system.physmem.num_reads::total 407349 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 120936 # Number of write requests responded to by this memory 34system.physmem.num_writes::total 120936 # Number of write requests responded to by this memory 35system.physmem.bw_read::cpu0.inst 403641 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu0.data 12451604 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu1.inst 29957 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu1.data 263929 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::tsunami.ide 484 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::total 13149615 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::cpu0.inst 403641 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu1.inst 29957 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 433598 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 3903930 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::total 3903930 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_total::writebacks 3903930 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu0.inst 403641 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu0.data 12451604 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu1.inst 29957 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu1.data 263929 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::tsunami.ide 484 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::total 17053544 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.readReqs 407349 # Number of read requests accepted 54system.physmem.writeReqs 120936 # Number of write requests accepted 55system.physmem.readBursts 407349 # Number of DRAM read bursts, including those serviced by the write queue 56system.physmem.writeBursts 120936 # Number of DRAM write bursts, including those merged in the write queue 57system.physmem.bytesReadDRAM 26062656 # Total number of bytes read from DRAM 58system.physmem.bytesReadWrQ 7680 # Total number of bytes read from write queue 59system.physmem.bytesWritten 7738112 # Total number of bytes written to DRAM 60system.physmem.bytesReadSys 26070336 # Total read bytes from the system interface side 61system.physmem.bytesWrittenSys 7739904 # Total written bytes from the system interface side 62system.physmem.servicedByWrQ 120 # Number of DRAM read bursts serviced by the write queue 63system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 64system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 65system.physmem.perBankRdBursts::0 25226 # Per bank write bursts 66system.physmem.perBankRdBursts::1 25379 # Per bank write bursts 67system.physmem.perBankRdBursts::2 25428 # Per bank write bursts 68system.physmem.perBankRdBursts::3 24855 # Per bank write bursts 69system.physmem.perBankRdBursts::4 25157 # Per bank write bursts 70system.physmem.perBankRdBursts::5 25423 # Per bank write bursts 71system.physmem.perBankRdBursts::6 25496 # Per bank write bursts 72system.physmem.perBankRdBursts::7 25345 # Per bank write bursts 73system.physmem.perBankRdBursts::8 25239 # Per bank write bursts 74system.physmem.perBankRdBursts::9 25589 # Per bank write bursts 75system.physmem.perBankRdBursts::10 25733 # Per bank write bursts 76system.physmem.perBankRdBursts::11 25919 # Per bank write bursts 77system.physmem.perBankRdBursts::12 25947 # Per bank write bursts 78system.physmem.perBankRdBursts::13 25572 # Per bank write bursts 79system.physmem.perBankRdBursts::14 25277 # Per bank write bursts 80system.physmem.perBankRdBursts::15 25644 # Per bank write bursts 81system.physmem.perBankWrBursts::0 7850 # Per bank write bursts 82system.physmem.perBankWrBursts::1 7778 # Per bank write bursts 83system.physmem.perBankWrBursts::2 7471 # Per bank write bursts 84system.physmem.perBankWrBursts::3 6886 # Per bank write bursts 85system.physmem.perBankWrBursts::4 7104 # Per bank write bursts 86system.physmem.perBankWrBursts::5 7345 # Per bank write bursts 87system.physmem.perBankWrBursts::6 7430 # Per bank write bursts 88system.physmem.perBankWrBursts::7 7151 # Per bank write bursts 89system.physmem.perBankWrBursts::8 7161 # Per bank write bursts 90system.physmem.perBankWrBursts::9 7315 # Per bank write bursts 91system.physmem.perBankWrBursts::10 7729 # Per bank write bursts 92system.physmem.perBankWrBursts::11 8152 # Per bank write bursts 93system.physmem.perBankWrBursts::12 8256 # Per bank write bursts 94system.physmem.perBankWrBursts::13 7924 # Per bank write bursts 95system.physmem.perBankWrBursts::14 7541 # Per bank write bursts 96system.physmem.perBankWrBursts::15 7815 # Per bank write bursts 97system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 98system.physmem.numWrRetry 11 # Number of times write queue was full causing retry 99system.physmem.totGap 1982585764500 # Total gap between requests 100system.physmem.readPktSize::0 0 # Read request sizes (log2) 101system.physmem.readPktSize::1 0 # Read request sizes (log2) 102system.physmem.readPktSize::2 0 # Read request sizes (log2) 103system.physmem.readPktSize::3 0 # Read request sizes (log2) 104system.physmem.readPktSize::4 0 # Read request sizes (log2) 105system.physmem.readPktSize::5 0 # Read request sizes (log2) 106system.physmem.readPktSize::6 407349 # Read request sizes (log2) 107system.physmem.writePktSize::0 0 # Write request sizes (log2) 108system.physmem.writePktSize::1 0 # Write request sizes (log2) 109system.physmem.writePktSize::2 0 # Write request sizes (log2) 110system.physmem.writePktSize::3 0 # Write request sizes (log2) 111system.physmem.writePktSize::4 0 # Write request sizes (log2) 112system.physmem.writePktSize::5 0 # Write request sizes (log2) 113system.physmem.writePktSize::6 120936 # Write request sizes (log2) 114system.physmem.rdQLenPdf::0 407149 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::1 67 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 146system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::15 1879 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::16 3334 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::17 7458 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::18 6021 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::19 7046 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::20 6129 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::21 5977 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::22 6491 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::23 7102 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::24 6544 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::25 8528 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::26 8912 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::27 7538 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::28 8021 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::29 7097 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::30 7359 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::31 6085 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::32 5703 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::33 205 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::34 125 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::35 115 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::36 87 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::37 97 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::38 151 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::39 103 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::40 93 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::41 105 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::42 117 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::43 145 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::44 161 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::45 145 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::46 174 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::47 210 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::48 139 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::49 225 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::50 127 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::51 152 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::52 133 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::53 125 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::54 126 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::55 80 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::56 92 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::57 105 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::58 71 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::59 69 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::60 93 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::61 66 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::62 31 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::63 30 # What write queue length does an incoming req see 210system.physmem.bytesPerActivate::samples 67582 # Bytes accessed per row activation 211system.physmem.bytesPerActivate::mean 500.144536 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::gmean 302.732498 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::stdev 404.890859 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::0-127 16271 24.08% 24.08% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::128-255 12393 18.34% 42.41% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::256-383 5170 7.65% 50.06% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::384-511 3294 4.87% 54.94% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::512-639 2518 3.73% 58.66% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::640-767 4277 6.33% 64.99% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::768-895 1487 2.20% 67.19% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::896-1023 2102 3.11% 70.30% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::1024-1151 20070 29.70% 100.00% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::total 67582 # Bytes accessed per row activation 224system.physmem.rdPerTurnAround::samples 5413 # Reads before turning the bus around for writes 225system.physmem.rdPerTurnAround::mean 75.229078 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::stdev 2867.379606 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::0-8191 5410 99.94% 99.94% # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::total 5413 # Reads before turning the bus around for writes 232system.physmem.wrPerTurnAround::samples 5413 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::mean 22.336597 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::gmean 19.167195 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::stdev 20.176387 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::16-23 4808 88.82% 88.82% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::24-31 29 0.54% 89.36% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::32-39 21 0.39% 89.75% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::40-47 46 0.85% 90.60% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::48-55 212 3.92% 94.51% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::56-63 15 0.28% 94.79% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::64-71 14 0.26% 95.05% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::72-79 26 0.48% 95.53% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::80-87 189 3.49% 99.02% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::88-95 5 0.09% 99.11% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::96-103 5 0.09% 99.21% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::104-111 4 0.07% 99.28% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::128-135 5 0.09% 99.37% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::136-143 2 0.04% 99.41% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::144-151 4 0.07% 99.48% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::152-159 1 0.02% 99.50% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::160-167 1 0.02% 99.52% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::168-175 8 0.15% 99.67% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::176-183 1 0.02% 99.69% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::184-191 2 0.04% 99.72% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::192-199 3 0.06% 99.78% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::208-215 8 0.15% 99.93% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::224-231 2 0.04% 99.96% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::256-263 2 0.04% 100.00% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::total 5413 # Writes before turning the bus around for reads 261system.physmem.totQLat 2790032750 # Total ticks spent queuing 262system.physmem.totMemAccLat 10425576500 # Total ticks spent from burst creation until serviced by the DRAM 263system.physmem.totBusLat 2036145000 # Total ticks spent in databus transfers 264system.physmem.avgQLat 6851.26 # Average queueing delay per DRAM burst 265system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 266system.physmem.avgMemAccLat 25601.26 # Average memory access latency per DRAM burst 267system.physmem.avgRdBW 13.15 # Average DRAM read bandwidth in MiByte/s 268system.physmem.avgWrBW 3.90 # Average achieved write bandwidth in MiByte/s 269system.physmem.avgRdBWSys 13.15 # Average system read bandwidth in MiByte/s 270system.physmem.avgWrBWSys 3.90 # Average system write bandwidth in MiByte/s 271system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 272system.physmem.busUtil 0.13 # Data bus utilization in percentage 273system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads 274system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 275system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 276system.physmem.avgWrQLen 24.37 # Average write queue length when enqueuing 277system.physmem.readRowHits 363813 # Number of row buffer hits during reads 278system.physmem.writeRowHits 96742 # Number of row buffer hits during writes 279system.physmem.readRowHitRate 89.34 # Row buffer hit rate for reads 280system.physmem.writeRowHitRate 79.99 # Row buffer hit rate for writes 281system.physmem.avgGap 3752871.58 # Average gap between requests 282system.physmem.pageHitRate 87.20 # Row buffer hit rate, read and write combined 283system.physmem_0.actEnergy 244006560 # Energy for activate commands per rank (pJ) 284system.physmem_0.preEnergy 133138500 # Energy for precharge commands per rank (pJ) 285system.physmem_0.readEnergy 1578010200 # Energy for read commands per rank (pJ) 286system.physmem_0.writeEnergy 382417200 # Energy for write commands per rank (pJ) 287system.physmem_0.refreshEnergy 129493107120 # Energy for refresh commands per rank (pJ) 288system.physmem_0.actBackEnergy 72939489120 # Energy for active background per rank (pJ) 289system.physmem_0.preBackEnergy 1125571835250 # Energy for precharge background per rank (pJ) 290system.physmem_0.totalEnergy 1330342003950 # Total energy per rank (pJ) 291system.physmem_0.averagePower 671.012251 # Core power per rank (mW) 292system.physmem_0.memoryStateTime::IDLE 1872206783000 # Time in different power states 293system.physmem_0.memoryStateTime::REF 66203020000 # Time in different power states 294system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 295system.physmem_0.memoryStateTime::ACT 44179949500 # Time in different power states 296system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 297system.physmem_1.actEnergy 266913360 # Energy for activate commands per rank (pJ) 298system.physmem_1.preEnergy 145637250 # Energy for precharge commands per rank (pJ) 299system.physmem_1.readEnergy 1598376000 # Energy for read commands per rank (pJ) 300system.physmem_1.writeEnergy 401066640 # Energy for write commands per rank (pJ) 301system.physmem_1.refreshEnergy 129493107120 # Energy for refresh commands per rank (pJ) 302system.physmem_1.actBackEnergy 73838725110 # Energy for active background per rank (pJ) 303system.physmem_1.preBackEnergy 1124783023500 # Energy for precharge background per rank (pJ) 304system.physmem_1.totalEnergy 1330526848980 # Total energy per rank (pJ) 305system.physmem_1.averagePower 671.105490 # Core power per rank (mW) 306system.physmem_1.memoryStateTime::IDLE 1870895185000 # Time in different power states 307system.physmem_1.memoryStateTime::REF 66203020000 # Time in different power states 308system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 309system.physmem_1.memoryStateTime::ACT 45491533750 # Time in different power states 310system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 311system.cpu_clk_domain.clock 500 # Clock period in ticks 312system.cpu0.dtb.fetch_hits 0 # ITB hits 313system.cpu0.dtb.fetch_misses 0 # ITB misses 314system.cpu0.dtb.fetch_acv 0 # ITB acv 315system.cpu0.dtb.fetch_accesses 0 # ITB accesses 316system.cpu0.dtb.read_hits 7416541 # DTB read hits 317system.cpu0.dtb.read_misses 7442 # DTB read misses 318system.cpu0.dtb.read_acv 210 # DTB read access violations 319system.cpu0.dtb.read_accesses 490672 # DTB read accesses 320system.cpu0.dtb.write_hits 5004457 # DTB write hits 321system.cpu0.dtb.write_misses 812 # DTB write misses 322system.cpu0.dtb.write_acv 134 # DTB write access violations 323system.cpu0.dtb.write_accesses 187451 # DTB write accesses 324system.cpu0.dtb.data_hits 12420998 # DTB hits 325system.cpu0.dtb.data_misses 8254 # DTB misses 326system.cpu0.dtb.data_acv 344 # DTB access violations 327system.cpu0.dtb.data_accesses 678123 # DTB accesses 328system.cpu0.itb.fetch_hits 3482402 # ITB hits 329system.cpu0.itb.fetch_misses 3871 # ITB misses 330system.cpu0.itb.fetch_acv 184 # ITB acv 331system.cpu0.itb.fetch_accesses 3486273 # ITB accesses 332system.cpu0.itb.read_hits 0 # DTB read hits 333system.cpu0.itb.read_misses 0 # DTB read misses 334system.cpu0.itb.read_acv 0 # DTB read access violations 335system.cpu0.itb.read_accesses 0 # DTB read accesses 336system.cpu0.itb.write_hits 0 # DTB write hits 337system.cpu0.itb.write_misses 0 # DTB write misses 338system.cpu0.itb.write_acv 0 # DTB write access violations 339system.cpu0.itb.write_accesses 0 # DTB write accesses 340system.cpu0.itb.data_hits 0 # DTB hits 341system.cpu0.itb.data_misses 0 # DTB misses 342system.cpu0.itb.data_acv 0 # DTB access violations 343system.cpu0.itb.data_accesses 0 # DTB accesses 344system.cpu0.numCycles 3964851877 # number of cpu cycles simulated 345system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 346system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 347system.cpu0.kern.inst.arm 0 # number of arm instructions executed 348system.cpu0.kern.inst.quiesce 6803 # number of quiesce instructions executed 349system.cpu0.kern.inst.hwrei 162801 # number of hwrei instructions executed 350system.cpu0.kern.ipl_count::0 55926 40.12% 40.12% # number of times we switched to this ipl 351system.cpu0.kern.ipl_count::21 133 0.10% 40.21% # number of times we switched to this ipl 352system.cpu0.kern.ipl_count::22 1977 1.42% 41.63% # number of times we switched to this ipl 353system.cpu0.kern.ipl_count::30 435 0.31% 41.94% # number of times we switched to this ipl 354system.cpu0.kern.ipl_count::31 80941 58.06% 100.00% # number of times we switched to this ipl 355system.cpu0.kern.ipl_count::total 139412 # number of times we switched to this ipl 356system.cpu0.kern.ipl_good::0 55417 49.07% 49.07% # number of times we switched to this ipl from a different ipl 357system.cpu0.kern.ipl_good::21 133 0.12% 49.18% # number of times we switched to this ipl from a different ipl 358system.cpu0.kern.ipl_good::22 1977 1.75% 50.93% # number of times we switched to this ipl from a different ipl 359system.cpu0.kern.ipl_good::30 435 0.39% 51.32% # number of times we switched to this ipl from a different ipl 360system.cpu0.kern.ipl_good::31 54983 48.68% 100.00% # number of times we switched to this ipl from a different ipl 361system.cpu0.kern.ipl_good::total 112945 # number of times we switched to this ipl from a different ipl 362system.cpu0.kern.ipl_ticks::0 1904793300500 96.08% 96.08% # number of cycles we spent at this ipl 363system.cpu0.kern.ipl_ticks::21 93813000 0.00% 96.09% # number of cycles we spent at this ipl 364system.cpu0.kern.ipl_ticks::22 790638500 0.04% 96.13% # number of cycles we spent at this ipl 365system.cpu0.kern.ipl_ticks::30 326474000 0.02% 96.15% # number of cycles we spent at this ipl 366system.cpu0.kern.ipl_ticks::31 76421682500 3.85% 100.00% # number of cycles we spent at this ipl 367system.cpu0.kern.ipl_ticks::total 1982425908500 # number of cycles we spent at this ipl 368system.cpu0.kern.ipl_used::0 0.990899 # fraction of swpipl calls that actually changed the ipl 369system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 370system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 371system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 372system.cpu0.kern.ipl_used::31 0.679297 # fraction of swpipl calls that actually changed the ipl 373system.cpu0.kern.ipl_used::total 0.810153 # fraction of swpipl calls that actually changed the ipl 374system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed 375system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed 376system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed 377system.cpu0.kern.syscall::6 32 14.41% 28.38% # number of syscalls executed 378system.cpu0.kern.syscall::12 1 0.45% 28.83% # number of syscalls executed 379system.cpu0.kern.syscall::17 9 4.05% 32.88% # number of syscalls executed 380system.cpu0.kern.syscall::19 10 4.50% 37.39% # number of syscalls executed 381system.cpu0.kern.syscall::20 6 2.70% 40.09% # number of syscalls executed 382system.cpu0.kern.syscall::23 1 0.45% 40.54% # number of syscalls executed 383system.cpu0.kern.syscall::24 3 1.35% 41.89% # number of syscalls executed 384system.cpu0.kern.syscall::33 7 3.15% 45.05% # number of syscalls executed 385system.cpu0.kern.syscall::41 2 0.90% 45.95% # number of syscalls executed 386system.cpu0.kern.syscall::45 36 16.22% 62.16% # number of syscalls executed 387system.cpu0.kern.syscall::47 3 1.35% 63.51% # number of syscalls executed 388system.cpu0.kern.syscall::48 10 4.50% 68.02% # number of syscalls executed 389system.cpu0.kern.syscall::54 10 4.50% 72.52% # number of syscalls executed 390system.cpu0.kern.syscall::58 1 0.45% 72.97% # number of syscalls executed 391system.cpu0.kern.syscall::59 6 2.70% 75.68% # number of syscalls executed 392system.cpu0.kern.syscall::71 23 10.36% 86.04% # number of syscalls executed 393system.cpu0.kern.syscall::73 3 1.35% 87.39% # number of syscalls executed 394system.cpu0.kern.syscall::74 6 2.70% 90.09% # number of syscalls executed 395system.cpu0.kern.syscall::87 1 0.45% 90.54% # number of syscalls executed 396system.cpu0.kern.syscall::90 3 1.35% 91.89% # number of syscalls executed 397system.cpu0.kern.syscall::92 9 4.05% 95.95% # number of syscalls executed 398system.cpu0.kern.syscall::97 2 0.90% 96.85% # number of syscalls executed 399system.cpu0.kern.syscall::98 2 0.90% 97.75% # number of syscalls executed 400system.cpu0.kern.syscall::132 1 0.45% 98.20% # number of syscalls executed 401system.cpu0.kern.syscall::144 2 0.90% 99.10% # number of syscalls executed 402system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed 403system.cpu0.kern.syscall::total 222 # number of syscalls executed 404system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 405system.cpu0.kern.callpal::wripir 524 0.36% 0.36% # number of callpals executed 406system.cpu0.kern.callpal::wrmces 1 0.00% 0.36% # number of callpals executed 407system.cpu0.kern.callpal::wrfen 1 0.00% 0.36% # number of callpals executed 408system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.36% # number of callpals executed 409system.cpu0.kern.callpal::swpctx 3024 2.05% 2.41% # number of callpals executed 410system.cpu0.kern.callpal::tbi 51 0.03% 2.44% # number of callpals executed 411system.cpu0.kern.callpal::wrent 7 0.00% 2.45% # number of callpals executed 412system.cpu0.kern.callpal::swpipl 132542 89.80% 92.24% # number of callpals executed 413system.cpu0.kern.callpal::rdps 6593 4.47% 96.71% # number of callpals executed 414system.cpu0.kern.callpal::wrkgp 1 0.00% 96.71% # number of callpals executed 415system.cpu0.kern.callpal::wrusp 3 0.00% 96.71% # number of callpals executed 416system.cpu0.kern.callpal::rdusp 9 0.01% 96.72% # number of callpals executed 417system.cpu0.kern.callpal::whami 2 0.00% 96.72% # number of callpals executed 418system.cpu0.kern.callpal::rti 4325 2.93% 99.65% # number of callpals executed 419system.cpu0.kern.callpal::callsys 381 0.26% 99.91% # number of callpals executed 420system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed 421system.cpu0.kern.callpal::total 147602 # number of callpals executed 422system.cpu0.kern.mode_switch::kernel 6863 # number of protection mode switches 423system.cpu0.kern.mode_switch::user 1282 # number of protection mode switches 424system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches 425system.cpu0.kern.mode_good::kernel 1282 426system.cpu0.kern.mode_good::user 1282 427system.cpu0.kern.mode_good::idle 0 428system.cpu0.kern.mode_switch_good::kernel 0.186799 # fraction of useful protection mode switches 429system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 430system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches 431system.cpu0.kern.mode_switch_good::total 0.314794 # fraction of useful protection mode switches 432system.cpu0.kern.mode_ticks::kernel 1977682087000 99.80% 99.80% # number of ticks spent at the given mode 433system.cpu0.kern.mode_ticks::user 3901070000 0.20% 100.00% # number of ticks spent at the given mode 434system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode 435system.cpu0.kern.swap_context 3025 # number of times the context was actually changed 436system.cpu0.committedInsts 47316172 # Number of instructions committed 437system.cpu0.committedOps 47316172 # Number of ops (including micro ops) committed 438system.cpu0.num_int_alu_accesses 43886449 # Number of integer alu accesses 439system.cpu0.num_fp_alu_accesses 206939 # Number of float alu accesses 440system.cpu0.num_func_calls 1185652 # number of times a function call or return occured 441system.cpu0.num_conditional_control_insts 5565345 # number of instructions that are conditional controls 442system.cpu0.num_int_insts 43886449 # number of integer instructions 443system.cpu0.num_fp_insts 206939 # number of float instructions 444system.cpu0.num_int_register_reads 60334275 # number of times the integer registers were read 445system.cpu0.num_int_register_writes 32718467 # number of times the integer registers were written 446system.cpu0.num_fp_register_reads 100516 # number of times the floating registers were read 447system.cpu0.num_fp_register_writes 102286 # number of times the floating registers were written 448system.cpu0.num_mem_refs 12460893 # number of memory refs 449system.cpu0.num_load_insts 7443480 # Number of load instructions 450system.cpu0.num_store_insts 5017413 # Number of store instructions 451system.cpu0.num_idle_cycles 3699956428.707181 # Number of idle cycles 452system.cpu0.num_busy_cycles 264895448.292820 # Number of busy cycles 453system.cpu0.not_idle_fraction 0.066811 # Percentage of non-idle cycles 454system.cpu0.idle_fraction 0.933189 # Percentage of idle cycles 455system.cpu0.Branches 7133641 # Number of branches fetched 456system.cpu0.op_class::No_OpClass 2703037 5.71% 5.71% # Class of executed instruction 457system.cpu0.op_class::IntAlu 31175022 65.87% 71.59% # Class of executed instruction 458system.cpu0.op_class::IntMult 51696 0.11% 71.70% # Class of executed instruction 459system.cpu0.op_class::IntDiv 0 0.00% 71.70% # Class of executed instruction 460system.cpu0.op_class::FloatAdd 25566 0.05% 71.75% # Class of executed instruction 461system.cpu0.op_class::FloatCmp 0 0.00% 71.75% # Class of executed instruction 462system.cpu0.op_class::FloatCvt 0 0.00% 71.75% # Class of executed instruction 463system.cpu0.op_class::FloatMult 0 0.00% 71.75% # Class of executed instruction 464system.cpu0.op_class::FloatDiv 1656 0.00% 71.75% # Class of executed instruction 465system.cpu0.op_class::FloatSqrt 0 0.00% 71.75% # Class of executed instruction 466system.cpu0.op_class::SimdAdd 0 0.00% 71.75% # Class of executed instruction 467system.cpu0.op_class::SimdAddAcc 0 0.00% 71.75% # Class of executed instruction 468system.cpu0.op_class::SimdAlu 0 0.00% 71.75% # Class of executed instruction 469system.cpu0.op_class::SimdCmp 0 0.00% 71.75% # Class of executed instruction 470system.cpu0.op_class::SimdCvt 0 0.00% 71.75% # Class of executed instruction 471system.cpu0.op_class::SimdMisc 0 0.00% 71.75% # Class of executed instruction 472system.cpu0.op_class::SimdMult 0 0.00% 71.75% # Class of executed instruction 473system.cpu0.op_class::SimdMultAcc 0 0.00% 71.75% # Class of executed instruction 474system.cpu0.op_class::SimdShift 0 0.00% 71.75% # Class of executed instruction 475system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.75% # Class of executed instruction 476system.cpu0.op_class::SimdSqrt 0 0.00% 71.75% # Class of executed instruction 477system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.75% # Class of executed instruction 478system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.75% # Class of executed instruction 479system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.75% # Class of executed instruction 480system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.75% # Class of executed instruction 481system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.75% # Class of executed instruction 482system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.75% # Class of executed instruction 483system.cpu0.op_class::SimdFloatMult 0 0.00% 71.75% # Class of executed instruction 484system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.75% # Class of executed instruction 485system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.75% # Class of executed instruction 486system.cpu0.op_class::MemRead 7616572 16.09% 87.85% # Class of executed instruction 487system.cpu0.op_class::MemWrite 5023515 10.61% 98.46% # Class of executed instruction 488system.cpu0.op_class::IprAccess 727706 1.54% 100.00% # Class of executed instruction 489system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 490system.cpu0.op_class::total 47324770 # Class of executed instruction 491system.cpu0.dcache.tags.replacements 1172753 # number of replacements 492system.cpu0.dcache.tags.tagsinuse 505.332741 # Cycle average of tags in use 493system.cpu0.dcache.tags.total_refs 11237004 # Total number of references to valid blocks. 494system.cpu0.dcache.tags.sampled_refs 1173173 # Sample count of references to valid blocks. 495system.cpu0.dcache.tags.avg_refs 9.578301 # Average number of references to valid blocks. 496system.cpu0.dcache.tags.warmup_cycle 144706500 # Cycle when the warmup percentage was hit. 497system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.332741 # Average occupied blocks per requestor 498system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986978 # Average percentage of cache occupancy 499system.cpu0.dcache.tags.occ_percent::total 0.986978 # Average percentage of cache occupancy 500system.cpu0.dcache.tags.occ_task_id_blocks::1024 420 # Occupied blocks per task id 501system.cpu0.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id 502system.cpu0.dcache.tags.age_task_id_blocks_1024::3 372 # Occupied blocks per task id 503system.cpu0.dcache.tags.occ_task_id_percent::1024 0.820312 # Percentage of cache occupancy per task id 504system.cpu0.dcache.tags.tag_accesses 50908772 # Number of tag accesses 505system.cpu0.dcache.tags.data_accesses 50908772 # Number of data accesses 506system.cpu0.dcache.ReadReq_hits::cpu0.data 6342827 # number of ReadReq hits 507system.cpu0.dcache.ReadReq_hits::total 6342827 # number of ReadReq hits 508system.cpu0.dcache.WriteReq_hits::cpu0.data 4601104 # number of WriteReq hits 509system.cpu0.dcache.WriteReq_hits::total 4601104 # number of WriteReq hits 510system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 138127 # number of LoadLockedReq hits 511system.cpu0.dcache.LoadLockedReq_hits::total 138127 # number of LoadLockedReq hits 512system.cpu0.dcache.StoreCondReq_hits::cpu0.data 145435 # number of StoreCondReq hits 513system.cpu0.dcache.StoreCondReq_hits::total 145435 # number of StoreCondReq hits 514system.cpu0.dcache.demand_hits::cpu0.data 10943931 # number of demand (read+write) hits 515system.cpu0.dcache.demand_hits::total 10943931 # number of demand (read+write) hits 516system.cpu0.dcache.overall_hits::cpu0.data 10943931 # number of overall hits 517system.cpu0.dcache.overall_hits::total 10943931 # number of overall hits 518system.cpu0.dcache.ReadReq_misses::cpu0.data 934208 # number of ReadReq misses 519system.cpu0.dcache.ReadReq_misses::total 934208 # number of ReadReq misses 520system.cpu0.dcache.WriteReq_misses::cpu0.data 249079 # number of WriteReq misses 521system.cpu0.dcache.WriteReq_misses::total 249079 # number of WriteReq misses 522system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13580 # number of LoadLockedReq misses 523system.cpu0.dcache.LoadLockedReq_misses::total 13580 # number of LoadLockedReq misses 524system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5739 # number of StoreCondReq misses 525system.cpu0.dcache.StoreCondReq_misses::total 5739 # number of StoreCondReq misses 526system.cpu0.dcache.demand_misses::cpu0.data 1183287 # number of demand (read+write) misses 527system.cpu0.dcache.demand_misses::total 1183287 # number of demand (read+write) misses 528system.cpu0.dcache.overall_misses::cpu0.data 1183287 # number of overall misses 529system.cpu0.dcache.overall_misses::total 1183287 # number of overall misses 530system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 42886334500 # number of ReadReq miss cycles 531system.cpu0.dcache.ReadReq_miss_latency::total 42886334500 # number of ReadReq miss cycles 532system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 16793569500 # number of WriteReq miss cycles 533system.cpu0.dcache.WriteReq_miss_latency::total 16793569500 # number of WriteReq miss cycles 534system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 151760500 # number of LoadLockedReq miss cycles 535system.cpu0.dcache.LoadLockedReq_miss_latency::total 151760500 # number of LoadLockedReq miss cycles 536system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 94775500 # number of StoreCondReq miss cycles 537system.cpu0.dcache.StoreCondReq_miss_latency::total 94775500 # number of StoreCondReq miss cycles 538system.cpu0.dcache.demand_miss_latency::cpu0.data 59679904000 # number of demand (read+write) miss cycles 539system.cpu0.dcache.demand_miss_latency::total 59679904000 # number of demand (read+write) miss cycles 540system.cpu0.dcache.overall_miss_latency::cpu0.data 59679904000 # number of overall miss cycles 541system.cpu0.dcache.overall_miss_latency::total 59679904000 # number of overall miss cycles 542system.cpu0.dcache.ReadReq_accesses::cpu0.data 7277035 # number of ReadReq accesses(hits+misses) 543system.cpu0.dcache.ReadReq_accesses::total 7277035 # number of ReadReq accesses(hits+misses) 544system.cpu0.dcache.WriteReq_accesses::cpu0.data 4850183 # number of WriteReq accesses(hits+misses) 545system.cpu0.dcache.WriteReq_accesses::total 4850183 # number of WriteReq accesses(hits+misses) 546system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 151707 # number of LoadLockedReq accesses(hits+misses) 547system.cpu0.dcache.LoadLockedReq_accesses::total 151707 # number of LoadLockedReq accesses(hits+misses) 548system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 151174 # number of StoreCondReq accesses(hits+misses) 549system.cpu0.dcache.StoreCondReq_accesses::total 151174 # number of StoreCondReq accesses(hits+misses) 550system.cpu0.dcache.demand_accesses::cpu0.data 12127218 # number of demand (read+write) accesses 551system.cpu0.dcache.demand_accesses::total 12127218 # number of demand (read+write) accesses 552system.cpu0.dcache.overall_accesses::cpu0.data 12127218 # number of overall (read+write) accesses 553system.cpu0.dcache.overall_accesses::total 12127218 # number of overall (read+write) accesses 554system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.128378 # miss rate for ReadReq accesses 555system.cpu0.dcache.ReadReq_miss_rate::total 0.128378 # miss rate for ReadReq accesses 556system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051355 # miss rate for WriteReq accesses 557system.cpu0.dcache.WriteReq_miss_rate::total 0.051355 # miss rate for WriteReq accesses 558system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.089515 # miss rate for LoadLockedReq accesses 559system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.089515 # miss rate for LoadLockedReq accesses 560system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.037963 # miss rate for StoreCondReq accesses 561system.cpu0.dcache.StoreCondReq_miss_rate::total 0.037963 # miss rate for StoreCondReq accesses 562system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097573 # miss rate for demand accesses 563system.cpu0.dcache.demand_miss_rate::total 0.097573 # miss rate for demand accesses 564system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097573 # miss rate for overall accesses 565system.cpu0.dcache.overall_miss_rate::total 0.097573 # miss rate for overall accesses 566system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 45906.623043 # average ReadReq miss latency 567system.cpu0.dcache.ReadReq_avg_miss_latency::total 45906.623043 # average ReadReq miss latency 568system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 67422.663091 # average WriteReq miss latency 569system.cpu0.dcache.WriteReq_avg_miss_latency::total 67422.663091 # average WriteReq miss latency 570system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11175.294551 # average LoadLockedReq miss latency 571system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11175.294551 # average LoadLockedReq miss latency 572system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 16514.288204 # average StoreCondReq miss latency 573system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 16514.288204 # average StoreCondReq miss latency 574system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50435.696496 # average overall miss latency 575system.cpu0.dcache.demand_avg_miss_latency::total 50435.696496 # average overall miss latency 576system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50435.696496 # average overall miss latency 577system.cpu0.dcache.overall_avg_miss_latency::total 50435.696496 # average overall miss latency 578system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 579system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 580system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 581system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 582system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 583system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 584system.cpu0.dcache.fast_writes 0 # number of fast writes performed 585system.cpu0.dcache.cache_copies 0 # number of cache copies performed 586system.cpu0.dcache.writebacks::writebacks 672821 # number of writebacks 587system.cpu0.dcache.writebacks::total 672821 # number of writebacks 588system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 934208 # number of ReadReq MSHR misses 589system.cpu0.dcache.ReadReq_mshr_misses::total 934208 # number of ReadReq MSHR misses 590system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 249079 # number of WriteReq MSHR misses 591system.cpu0.dcache.WriteReq_mshr_misses::total 249079 # number of WriteReq MSHR misses 592system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13580 # number of LoadLockedReq MSHR misses 593system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13580 # number of LoadLockedReq MSHR misses 594system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5739 # number of StoreCondReq MSHR misses 595system.cpu0.dcache.StoreCondReq_mshr_misses::total 5739 # number of StoreCondReq MSHR misses 596system.cpu0.dcache.demand_mshr_misses::cpu0.data 1183287 # number of demand (read+write) MSHR misses 597system.cpu0.dcache.demand_mshr_misses::total 1183287 # number of demand (read+write) MSHR misses 598system.cpu0.dcache.overall_mshr_misses::cpu0.data 1183287 # number of overall MSHR misses 599system.cpu0.dcache.overall_mshr_misses::total 1183287 # number of overall MSHR misses 600system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7086 # number of ReadReq MSHR uncacheable 601system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7086 # number of ReadReq MSHR uncacheable 602system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10784 # number of WriteReq MSHR uncacheable 603system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10784 # number of WriteReq MSHR uncacheable 604system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17870 # number of overall MSHR uncacheable misses 605system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17870 # number of overall MSHR uncacheable misses 606system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 41952126500 # number of ReadReq MSHR miss cycles 607system.cpu0.dcache.ReadReq_mshr_miss_latency::total 41952126500 # number of ReadReq MSHR miss cycles 608system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 16544490500 # number of WriteReq MSHR miss cycles 609system.cpu0.dcache.WriteReq_mshr_miss_latency::total 16544490500 # number of WriteReq MSHR miss cycles 610system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 138180500 # number of LoadLockedReq MSHR miss cycles 611system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 138180500 # number of LoadLockedReq MSHR miss cycles 612system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 89036500 # number of StoreCondReq MSHR miss cycles 613system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 89036500 # number of StoreCondReq MSHR miss cycles 614system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 58496617000 # number of demand (read+write) MSHR miss cycles 615system.cpu0.dcache.demand_mshr_miss_latency::total 58496617000 # number of demand (read+write) MSHR miss cycles 616system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 58496617000 # number of overall MSHR miss cycles 617system.cpu0.dcache.overall_mshr_miss_latency::total 58496617000 # number of overall MSHR miss cycles 618system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1567540500 # number of ReadReq MSHR uncacheable cycles 619system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1567540500 # number of ReadReq MSHR uncacheable cycles 620system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2452068500 # number of WriteReq MSHR uncacheable cycles 621system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2452068500 # number of WriteReq MSHR uncacheable cycles 622system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4019609000 # number of overall MSHR uncacheable cycles 623system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4019609000 # number of overall MSHR uncacheable cycles 624system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.128378 # mshr miss rate for ReadReq accesses 625system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.128378 # mshr miss rate for ReadReq accesses 626system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051355 # mshr miss rate for WriteReq accesses 627system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051355 # mshr miss rate for WriteReq accesses 628system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.089515 # mshr miss rate for LoadLockedReq accesses 629system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.089515 # mshr miss rate for LoadLockedReq accesses 630system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.037963 # mshr miss rate for StoreCondReq accesses 631system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.037963 # mshr miss rate for StoreCondReq accesses 632system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097573 # mshr miss rate for demand accesses 633system.cpu0.dcache.demand_mshr_miss_rate::total 0.097573 # mshr miss rate for demand accesses 634system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097573 # mshr miss rate for overall accesses 635system.cpu0.dcache.overall_mshr_miss_rate::total 0.097573 # mshr miss rate for overall accesses 636system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 44906.623043 # average ReadReq mshr miss latency 637system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 44906.623043 # average ReadReq mshr miss latency 638system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 66422.663091 # average WriteReq mshr miss latency 639system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 66422.663091 # average WriteReq mshr miss latency 640system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10175.294551 # average LoadLockedReq mshr miss latency 641system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10175.294551 # average LoadLockedReq mshr miss latency 642system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 15514.288204 # average StoreCondReq mshr miss latency 643system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 15514.288204 # average StoreCondReq mshr miss latency 644system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 49435.696496 # average overall mshr miss latency 645system.cpu0.dcache.demand_avg_mshr_miss_latency::total 49435.696496 # average overall mshr miss latency 646system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 49435.696496 # average overall mshr miss latency 647system.cpu0.dcache.overall_avg_mshr_miss_latency::total 49435.696496 # average overall mshr miss latency 648system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 221216.553768 # average ReadReq mshr uncacheable latency 649system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221216.553768 # average ReadReq mshr uncacheable latency 650system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 227380.239243 # average WriteReq mshr uncacheable latency 651system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 227380.239243 # average WriteReq mshr uncacheable latency 652system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 224936.149972 # average overall mshr uncacheable latency 653system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 224936.149972 # average overall mshr uncacheable latency 654system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 655system.cpu0.icache.tags.replacements 686592 # number of replacements 656system.cpu0.icache.tags.tagsinuse 506.490691 # Cycle average of tags in use 657system.cpu0.icache.tags.total_refs 46637544 # Total number of references to valid blocks. 658system.cpu0.icache.tags.sampled_refs 687104 # Sample count of references to valid blocks. 659system.cpu0.icache.tags.avg_refs 67.875524 # Average number of references to valid blocks. 660system.cpu0.icache.tags.warmup_cycle 58998281500 # Cycle when the warmup percentage was hit. 661system.cpu0.icache.tags.occ_blocks::cpu0.inst 506.490691 # Average occupied blocks per requestor 662system.cpu0.icache.tags.occ_percent::cpu0.inst 0.989240 # Average percentage of cache occupancy 663system.cpu0.icache.tags.occ_percent::total 0.989240 # Average percentage of cache occupancy 664system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 665system.cpu0.icache.tags.age_task_id_blocks_1024::2 95 # Occupied blocks per task id 666system.cpu0.icache.tags.age_task_id_blocks_1024::3 417 # Occupied blocks per task id 667system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 668system.cpu0.icache.tags.tag_accesses 48011996 # Number of tag accesses 669system.cpu0.icache.tags.data_accesses 48011996 # Number of data accesses 670system.cpu0.icache.ReadReq_hits::cpu0.inst 46637544 # number of ReadReq hits 671system.cpu0.icache.ReadReq_hits::total 46637544 # number of ReadReq hits 672system.cpu0.icache.demand_hits::cpu0.inst 46637544 # number of demand (read+write) hits 673system.cpu0.icache.demand_hits::total 46637544 # number of demand (read+write) hits 674system.cpu0.icache.overall_hits::cpu0.inst 46637544 # number of overall hits 675system.cpu0.icache.overall_hits::total 46637544 # number of overall hits 676system.cpu0.icache.ReadReq_misses::cpu0.inst 687226 # number of ReadReq misses 677system.cpu0.icache.ReadReq_misses::total 687226 # number of ReadReq misses 678system.cpu0.icache.demand_misses::cpu0.inst 687226 # number of demand (read+write) misses 679system.cpu0.icache.demand_misses::total 687226 # number of demand (read+write) misses 680system.cpu0.icache.overall_misses::cpu0.inst 687226 # number of overall misses 681system.cpu0.icache.overall_misses::total 687226 # number of overall misses 682system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10626395500 # number of ReadReq miss cycles 683system.cpu0.icache.ReadReq_miss_latency::total 10626395500 # number of ReadReq miss cycles 684system.cpu0.icache.demand_miss_latency::cpu0.inst 10626395500 # number of demand (read+write) miss cycles 685system.cpu0.icache.demand_miss_latency::total 10626395500 # number of demand (read+write) miss cycles 686system.cpu0.icache.overall_miss_latency::cpu0.inst 10626395500 # number of overall miss cycles 687system.cpu0.icache.overall_miss_latency::total 10626395500 # number of overall miss cycles 688system.cpu0.icache.ReadReq_accesses::cpu0.inst 47324770 # number of ReadReq accesses(hits+misses) 689system.cpu0.icache.ReadReq_accesses::total 47324770 # number of ReadReq accesses(hits+misses) 690system.cpu0.icache.demand_accesses::cpu0.inst 47324770 # number of demand (read+write) accesses 691system.cpu0.icache.demand_accesses::total 47324770 # number of demand (read+write) accesses 692system.cpu0.icache.overall_accesses::cpu0.inst 47324770 # number of overall (read+write) accesses 693system.cpu0.icache.overall_accesses::total 47324770 # number of overall (read+write) accesses 694system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014521 # miss rate for ReadReq accesses 695system.cpu0.icache.ReadReq_miss_rate::total 0.014521 # miss rate for ReadReq accesses 696system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014521 # miss rate for demand accesses 697system.cpu0.icache.demand_miss_rate::total 0.014521 # miss rate for demand accesses 698system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014521 # miss rate for overall accesses 699system.cpu0.icache.overall_miss_rate::total 0.014521 # miss rate for overall accesses 700system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15462.737877 # average ReadReq miss latency 701system.cpu0.icache.ReadReq_avg_miss_latency::total 15462.737877 # average ReadReq miss latency 702system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15462.737877 # average overall miss latency 703system.cpu0.icache.demand_avg_miss_latency::total 15462.737877 # average overall miss latency 704system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15462.737877 # average overall miss latency 705system.cpu0.icache.overall_avg_miss_latency::total 15462.737877 # average overall miss latency 706system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 707system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 708system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 709system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 710system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 711system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 712system.cpu0.icache.fast_writes 0 # number of fast writes performed 713system.cpu0.icache.cache_copies 0 # number of cache copies performed 714system.cpu0.icache.writebacks::writebacks 686592 # number of writebacks 715system.cpu0.icache.writebacks::total 686592 # number of writebacks 716system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 687226 # number of ReadReq MSHR misses 717system.cpu0.icache.ReadReq_mshr_misses::total 687226 # number of ReadReq MSHR misses 718system.cpu0.icache.demand_mshr_misses::cpu0.inst 687226 # number of demand (read+write) MSHR misses 719system.cpu0.icache.demand_mshr_misses::total 687226 # number of demand (read+write) MSHR misses 720system.cpu0.icache.overall_mshr_misses::cpu0.inst 687226 # number of overall MSHR misses 721system.cpu0.icache.overall_mshr_misses::total 687226 # number of overall MSHR misses 722system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9939169500 # number of ReadReq MSHR miss cycles 723system.cpu0.icache.ReadReq_mshr_miss_latency::total 9939169500 # number of ReadReq MSHR miss cycles 724system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9939169500 # number of demand (read+write) MSHR miss cycles 725system.cpu0.icache.demand_mshr_miss_latency::total 9939169500 # number of demand (read+write) MSHR miss cycles 726system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9939169500 # number of overall MSHR miss cycles 727system.cpu0.icache.overall_mshr_miss_latency::total 9939169500 # number of overall MSHR miss cycles 728system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014521 # mshr miss rate for ReadReq accesses 729system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014521 # mshr miss rate for ReadReq accesses 730system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014521 # mshr miss rate for demand accesses 731system.cpu0.icache.demand_mshr_miss_rate::total 0.014521 # mshr miss rate for demand accesses 732system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014521 # mshr miss rate for overall accesses 733system.cpu0.icache.overall_mshr_miss_rate::total 0.014521 # mshr miss rate for overall accesses 734system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14462.737877 # average ReadReq mshr miss latency 735system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14462.737877 # average ReadReq mshr miss latency 736system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14462.737877 # average overall mshr miss latency 737system.cpu0.icache.demand_avg_mshr_miss_latency::total 14462.737877 # average overall mshr miss latency 738system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14462.737877 # average overall mshr miss latency 739system.cpu0.icache.overall_avg_mshr_miss_latency::total 14462.737877 # average overall mshr miss latency 740system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 741system.cpu1.dtb.fetch_hits 0 # ITB hits 742system.cpu1.dtb.fetch_misses 0 # ITB misses 743system.cpu1.dtb.fetch_acv 0 # ITB acv 744system.cpu1.dtb.fetch_accesses 0 # ITB accesses 745system.cpu1.dtb.read_hits 2511145 # DTB read hits 746system.cpu1.dtb.read_misses 2993 # DTB read misses 747system.cpu1.dtb.read_acv 0 # DTB read access violations 748system.cpu1.dtb.read_accesses 239364 # DTB read accesses 749system.cpu1.dtb.write_hits 1829996 # DTB write hits 750system.cpu1.dtb.write_misses 342 # DTB write misses 751system.cpu1.dtb.write_acv 29 # DTB write access violations 752system.cpu1.dtb.write_accesses 105248 # DTB write accesses 753system.cpu1.dtb.data_hits 4341141 # DTB hits 754system.cpu1.dtb.data_misses 3335 # DTB misses 755system.cpu1.dtb.data_acv 29 # DTB access violations 756system.cpu1.dtb.data_accesses 344612 # DTB accesses 757system.cpu1.itb.fetch_hits 1990273 # ITB hits 758system.cpu1.itb.fetch_misses 1216 # ITB misses 759system.cpu1.itb.fetch_acv 0 # ITB acv 760system.cpu1.itb.fetch_accesses 1991489 # ITB accesses 761system.cpu1.itb.read_hits 0 # DTB read hits 762system.cpu1.itb.read_misses 0 # DTB read misses 763system.cpu1.itb.read_acv 0 # DTB read access violations 764system.cpu1.itb.read_accesses 0 # DTB read accesses 765system.cpu1.itb.write_hits 0 # DTB write hits 766system.cpu1.itb.write_misses 0 # DTB write misses 767system.cpu1.itb.write_acv 0 # DTB write access violations 768system.cpu1.itb.write_accesses 0 # DTB write accesses 769system.cpu1.itb.data_hits 0 # DTB hits 770system.cpu1.itb.data_misses 0 # DTB misses 771system.cpu1.itb.data_acv 0 # DTB access violations 772system.cpu1.itb.data_accesses 0 # DTB accesses 773system.cpu1.numCycles 3965186264 # number of cpu cycles simulated 774system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 775system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 776system.cpu1.kern.inst.arm 0 # number of arm instructions executed 777system.cpu1.kern.inst.quiesce 2869 # number of quiesce instructions executed 778system.cpu1.kern.inst.hwrei 81047 # number of hwrei instructions executed 779system.cpu1.kern.ipl_count::0 27546 38.52% 38.52% # number of times we switched to this ipl 780system.cpu1.kern.ipl_count::22 1971 2.76% 41.28% # number of times we switched to this ipl 781system.cpu1.kern.ipl_count::30 524 0.73% 42.01% # number of times we switched to this ipl 782system.cpu1.kern.ipl_count::31 41461 57.99% 100.00% # number of times we switched to this ipl 783system.cpu1.kern.ipl_count::total 71502 # number of times we switched to this ipl 784system.cpu1.kern.ipl_good::0 26678 48.22% 48.22% # number of times we switched to this ipl from a different ipl 785system.cpu1.kern.ipl_good::22 1971 3.56% 51.78% # number of times we switched to this ipl from a different ipl 786system.cpu1.kern.ipl_good::30 524 0.95% 52.73% # number of times we switched to this ipl from a different ipl 787system.cpu1.kern.ipl_good::31 26154 47.27% 100.00% # number of times we switched to this ipl from a different ipl 788system.cpu1.kern.ipl_good::total 55327 # number of times we switched to this ipl from a different ipl 789system.cpu1.kern.ipl_ticks::0 1912240588500 96.45% 96.45% # number of cycles we spent at this ipl 790system.cpu1.kern.ipl_ticks::22 731240000 0.04% 96.49% # number of cycles we spent at this ipl 791system.cpu1.kern.ipl_ticks::30 374509500 0.02% 96.51% # number of cycles we spent at this ipl 792system.cpu1.kern.ipl_ticks::31 69246057000 3.49% 100.00% # number of cycles we spent at this ipl 793system.cpu1.kern.ipl_ticks::total 1982592395000 # number of cycles we spent at this ipl 794system.cpu1.kern.ipl_used::0 0.968489 # fraction of swpipl calls that actually changed the ipl 795system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 796system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 797system.cpu1.kern.ipl_used::31 0.630810 # fraction of swpipl calls that actually changed the ipl 798system.cpu1.kern.ipl_used::total 0.773783 # fraction of swpipl calls that actually changed the ipl 799system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed 800system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed 801system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed 802system.cpu1.kern.syscall::17 6 5.77% 26.92% # number of syscalls executed 803system.cpu1.kern.syscall::23 3 2.88% 29.81% # number of syscalls executed 804system.cpu1.kern.syscall::24 3 2.88% 32.69% # number of syscalls executed 805system.cpu1.kern.syscall::33 4 3.85% 36.54% # number of syscalls executed 806system.cpu1.kern.syscall::45 18 17.31% 53.85% # number of syscalls executed 807system.cpu1.kern.syscall::47 3 2.88% 56.73% # number of syscalls executed 808system.cpu1.kern.syscall::59 1 0.96% 57.69% # number of syscalls executed 809system.cpu1.kern.syscall::71 31 29.81% 87.50% # number of syscalls executed 810system.cpu1.kern.syscall::74 10 9.62% 97.12% # number of syscalls executed 811system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed 812system.cpu1.kern.syscall::total 104 # number of syscalls executed 813system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 814system.cpu1.kern.callpal::wripir 435 0.59% 0.59% # number of callpals executed 815system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed 816system.cpu1.kern.callpal::wrfen 1 0.00% 0.59% # number of callpals executed 817system.cpu1.kern.callpal::swpctx 2066 2.79% 3.39% # number of callpals executed 818system.cpu1.kern.callpal::tbi 3 0.00% 3.39% # number of callpals executed 819system.cpu1.kern.callpal::wrent 7 0.01% 3.40% # number of callpals executed 820system.cpu1.kern.callpal::swpipl 65180 88.12% 91.52% # number of callpals executed 821system.cpu1.kern.callpal::rdps 2261 3.06% 94.57% # number of callpals executed 822system.cpu1.kern.callpal::wrkgp 1 0.00% 94.57% # number of callpals executed 823system.cpu1.kern.callpal::wrusp 4 0.01% 94.58% # number of callpals executed 824system.cpu1.kern.callpal::whami 3 0.00% 94.58% # number of callpals executed 825system.cpu1.kern.callpal::rti 3826 5.17% 99.76% # number of callpals executed 826system.cpu1.kern.callpal::callsys 136 0.18% 99.94% # number of callpals executed 827system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed 828system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed 829system.cpu1.kern.callpal::total 73970 # number of callpals executed 830system.cpu1.kern.mode_switch::kernel 2115 # number of protection mode switches 831system.cpu1.kern.mode_switch::user 464 # number of protection mode switches 832system.cpu1.kern.mode_switch::idle 2921 # number of protection mode switches 833system.cpu1.kern.mode_good::kernel 912 834system.cpu1.kern.mode_good::user 464 835system.cpu1.kern.mode_good::idle 448 836system.cpu1.kern.mode_switch_good::kernel 0.431206 # fraction of useful protection mode switches 837system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 838system.cpu1.kern.mode_switch_good::idle 0.153372 # fraction of useful protection mode switches 839system.cpu1.kern.mode_switch_good::total 0.331636 # fraction of useful protection mode switches 840system.cpu1.kern.mode_ticks::kernel 19470103000 0.98% 0.98% # number of ticks spent at the given mode 841system.cpu1.kern.mode_ticks::user 1729907500 0.09% 1.07% # number of ticks spent at the given mode 842system.cpu1.kern.mode_ticks::idle 1961392382500 98.93% 100.00% # number of ticks spent at the given mode 843system.cpu1.kern.swap_context 2067 # number of times the context was actually changed 844system.cpu1.committedInsts 13686479 # Number of instructions committed 845system.cpu1.committedOps 13686479 # Number of ops (including micro ops) committed 846system.cpu1.num_int_alu_accesses 12624111 # Number of integer alu accesses 847system.cpu1.num_fp_alu_accesses 178612 # Number of float alu accesses 848system.cpu1.num_func_calls 430158 # number of times a function call or return occured 849system.cpu1.num_conditional_control_insts 1359705 # number of instructions that are conditional controls 850system.cpu1.num_int_insts 12624111 # number of integer instructions 851system.cpu1.num_fp_insts 178612 # number of float instructions 852system.cpu1.num_int_register_reads 17383206 # number of times the integer registers were read 853system.cpu1.num_int_register_writes 9260208 # number of times the integer registers were written 854system.cpu1.num_fp_register_reads 93246 # number of times the floating registers were read 855system.cpu1.num_fp_register_writes 95234 # number of times the floating registers were written 856system.cpu1.num_mem_refs 4365297 # number of memory refs 857system.cpu1.num_load_insts 2525800 # Number of load instructions 858system.cpu1.num_store_insts 1839497 # Number of store instructions 859system.cpu1.num_idle_cycles 3912233484.998027 # Number of idle cycles 860system.cpu1.num_busy_cycles 52952779.001973 # Number of busy cycles 861system.cpu1.not_idle_fraction 0.013354 # Percentage of non-idle cycles 862system.cpu1.idle_fraction 0.986646 # Percentage of idle cycles 863system.cpu1.Branches 1950120 # Number of branches fetched 864system.cpu1.op_class::No_OpClass 733810 5.36% 5.36% # Class of executed instruction 865system.cpu1.op_class::IntAlu 8101284 59.18% 64.54% # Class of executed instruction 866system.cpu1.op_class::IntMult 23184 0.17% 64.71% # Class of executed instruction 867system.cpu1.op_class::IntDiv 0 0.00% 64.71% # Class of executed instruction 868system.cpu1.op_class::FloatAdd 14372 0.10% 64.81% # Class of executed instruction 869system.cpu1.op_class::FloatCmp 0 0.00% 64.81% # Class of executed instruction 870system.cpu1.op_class::FloatCvt 0 0.00% 64.81% # Class of executed instruction 871system.cpu1.op_class::FloatMult 0 0.00% 64.81% # Class of executed instruction 872system.cpu1.op_class::FloatDiv 1986 0.01% 64.83% # Class of executed instruction 873system.cpu1.op_class::FloatSqrt 0 0.00% 64.83% # Class of executed instruction 874system.cpu1.op_class::SimdAdd 0 0.00% 64.83% # Class of executed instruction 875system.cpu1.op_class::SimdAddAcc 0 0.00% 64.83% # Class of executed instruction 876system.cpu1.op_class::SimdAlu 0 0.00% 64.83% # Class of executed instruction 877system.cpu1.op_class::SimdCmp 0 0.00% 64.83% # Class of executed instruction 878system.cpu1.op_class::SimdCvt 0 0.00% 64.83% # Class of executed instruction 879system.cpu1.op_class::SimdMisc 0 0.00% 64.83% # Class of executed instruction 880system.cpu1.op_class::SimdMult 0 0.00% 64.83% # Class of executed instruction 881system.cpu1.op_class::SimdMultAcc 0 0.00% 64.83% # Class of executed instruction 882system.cpu1.op_class::SimdShift 0 0.00% 64.83% # Class of executed instruction 883system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.83% # Class of executed instruction 884system.cpu1.op_class::SimdSqrt 0 0.00% 64.83% # Class of executed instruction 885system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.83% # Class of executed instruction 886system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.83% # Class of executed instruction 887system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.83% # Class of executed instruction 888system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.83% # Class of executed instruction 889system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.83% # Class of executed instruction 890system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.83% # Class of executed instruction 891system.cpu1.op_class::SimdFloatMult 0 0.00% 64.83% # Class of executed instruction 892system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.83% # Class of executed instruction 893system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.83% # Class of executed instruction 894system.cpu1.op_class::MemRead 2600475 19.00% 83.82% # Class of executed instruction 895system.cpu1.op_class::MemWrite 1840521 13.44% 97.27% # Class of executed instruction 896system.cpu1.op_class::IprAccess 374211 2.73% 100.00% # Class of executed instruction 897system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 898system.cpu1.op_class::total 13689843 # Class of executed instruction 899system.cpu1.dcache.tags.replacements 173686 # number of replacements 900system.cpu1.dcache.tags.tagsinuse 481.983606 # Cycle average of tags in use 901system.cpu1.dcache.tags.total_refs 4164884 # Total number of references to valid blocks. 902system.cpu1.dcache.tags.sampled_refs 174198 # Sample count of references to valid blocks. 903system.cpu1.dcache.tags.avg_refs 23.908908 # Average number of references to valid blocks. 904system.cpu1.dcache.tags.warmup_cycle 90321767000 # Cycle when the warmup percentage was hit. 905system.cpu1.dcache.tags.occ_blocks::cpu1.data 481.983606 # Average occupied blocks per requestor 906system.cpu1.dcache.tags.occ_percent::cpu1.data 0.941374 # Average percentage of cache occupancy 907system.cpu1.dcache.tags.occ_percent::total 0.941374 # Average percentage of cache occupancy 908system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 909system.cpu1.dcache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id 910system.cpu1.dcache.tags.age_task_id_blocks_1024::1 333 # Occupied blocks per task id 911system.cpu1.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id 912system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 913system.cpu1.dcache.tags.tag_accesses 17608316 # Number of tag accesses 914system.cpu1.dcache.tags.data_accesses 17608316 # Number of data accesses 915system.cpu1.dcache.ReadReq_hits::cpu1.data 2339523 # number of ReadReq hits 916system.cpu1.dcache.ReadReq_hits::total 2339523 # number of ReadReq hits 917system.cpu1.dcache.WriteReq_hits::cpu1.data 1707175 # number of WriteReq hits 918system.cpu1.dcache.WriteReq_hits::total 1707175 # number of WriteReq hits 919system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 50425 # number of LoadLockedReq hits 920system.cpu1.dcache.LoadLockedReq_hits::total 50425 # number of LoadLockedReq hits 921system.cpu1.dcache.StoreCondReq_hits::cpu1.data 53078 # number of StoreCondReq hits 922system.cpu1.dcache.StoreCondReq_hits::total 53078 # number of StoreCondReq hits 923system.cpu1.dcache.demand_hits::cpu1.data 4046698 # number of demand (read+write) hits 924system.cpu1.dcache.demand_hits::total 4046698 # number of demand (read+write) hits 925system.cpu1.dcache.overall_hits::cpu1.data 4046698 # number of overall hits 926system.cpu1.dcache.overall_hits::total 4046698 # number of overall hits 927system.cpu1.dcache.ReadReq_misses::cpu1.data 123485 # number of ReadReq misses 928system.cpu1.dcache.ReadReq_misses::total 123485 # number of ReadReq misses 929system.cpu1.dcache.WriteReq_misses::cpu1.data 65589 # number of WriteReq misses 930system.cpu1.dcache.WriteReq_misses::total 65589 # number of WriteReq misses 931system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9256 # number of LoadLockedReq misses 932system.cpu1.dcache.LoadLockedReq_misses::total 9256 # number of LoadLockedReq misses 933system.cpu1.dcache.StoreCondReq_misses::cpu1.data 6109 # number of StoreCondReq misses 934system.cpu1.dcache.StoreCondReq_misses::total 6109 # number of StoreCondReq misses 935system.cpu1.dcache.demand_misses::cpu1.data 189074 # number of demand (read+write) misses 936system.cpu1.dcache.demand_misses::total 189074 # number of demand (read+write) misses 937system.cpu1.dcache.overall_misses::cpu1.data 189074 # number of overall misses 938system.cpu1.dcache.overall_misses::total 189074 # number of overall misses 939system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1555964500 # number of ReadReq miss cycles 940system.cpu1.dcache.ReadReq_miss_latency::total 1555964500 # number of ReadReq miss cycles 941system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1870805000 # number of WriteReq miss cycles 942system.cpu1.dcache.WriteReq_miss_latency::total 1870805000 # number of WriteReq miss cycles 943system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 85075000 # number of LoadLockedReq miss cycles 944system.cpu1.dcache.LoadLockedReq_miss_latency::total 85075000 # number of LoadLockedReq miss cycles 945system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 96955500 # number of StoreCondReq miss cycles 946system.cpu1.dcache.StoreCondReq_miss_latency::total 96955500 # number of StoreCondReq miss cycles 947system.cpu1.dcache.demand_miss_latency::cpu1.data 3426769500 # number of demand (read+write) miss cycles 948system.cpu1.dcache.demand_miss_latency::total 3426769500 # number of demand (read+write) miss cycles 949system.cpu1.dcache.overall_miss_latency::cpu1.data 3426769500 # number of overall miss cycles 950system.cpu1.dcache.overall_miss_latency::total 3426769500 # number of overall miss cycles 951system.cpu1.dcache.ReadReq_accesses::cpu1.data 2463008 # number of ReadReq accesses(hits+misses) 952system.cpu1.dcache.ReadReq_accesses::total 2463008 # number of ReadReq accesses(hits+misses) 953system.cpu1.dcache.WriteReq_accesses::cpu1.data 1772764 # number of WriteReq accesses(hits+misses) 954system.cpu1.dcache.WriteReq_accesses::total 1772764 # number of WriteReq accesses(hits+misses) 955system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 59681 # number of LoadLockedReq accesses(hits+misses) 956system.cpu1.dcache.LoadLockedReq_accesses::total 59681 # number of LoadLockedReq accesses(hits+misses) 957system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 59187 # number of StoreCondReq accesses(hits+misses) 958system.cpu1.dcache.StoreCondReq_accesses::total 59187 # number of StoreCondReq accesses(hits+misses) 959system.cpu1.dcache.demand_accesses::cpu1.data 4235772 # number of demand (read+write) accesses 960system.cpu1.dcache.demand_accesses::total 4235772 # number of demand (read+write) accesses 961system.cpu1.dcache.overall_accesses::cpu1.data 4235772 # number of overall (read+write) accesses 962system.cpu1.dcache.overall_accesses::total 4235772 # number of overall (read+write) accesses 963system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.050136 # miss rate for ReadReq accesses 964system.cpu1.dcache.ReadReq_miss_rate::total 0.050136 # miss rate for ReadReq accesses 965system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036998 # miss rate for WriteReq accesses 966system.cpu1.dcache.WriteReq_miss_rate::total 0.036998 # miss rate for WriteReq accesses 967system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.155091 # miss rate for LoadLockedReq accesses 968system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.155091 # miss rate for LoadLockedReq accesses 969system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103215 # miss rate for StoreCondReq accesses 970system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103215 # miss rate for StoreCondReq accesses 971system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044637 # miss rate for demand accesses 972system.cpu1.dcache.demand_miss_rate::total 0.044637 # miss rate for demand accesses 973system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044637 # miss rate for overall accesses 974system.cpu1.dcache.overall_miss_rate::total 0.044637 # miss rate for overall accesses 975system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12600.433251 # average ReadReq miss latency 976system.cpu1.dcache.ReadReq_avg_miss_latency::total 12600.433251 # average ReadReq miss latency 977system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 28523.151748 # average WriteReq miss latency 978system.cpu1.dcache.WriteReq_avg_miss_latency::total 28523.151748 # average WriteReq miss latency 979system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9191.335350 # average LoadLockedReq miss latency 980system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9191.335350 # average LoadLockedReq miss latency 981system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 15870.928139 # average StoreCondReq miss latency 982system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 15870.928139 # average StoreCondReq miss latency 983system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18123.959402 # average overall miss latency 984system.cpu1.dcache.demand_avg_miss_latency::total 18123.959402 # average overall miss latency 985system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18123.959402 # average overall miss latency 986system.cpu1.dcache.overall_avg_miss_latency::total 18123.959402 # average overall miss latency 987system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 988system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 989system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 990system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 991system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 992system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 993system.cpu1.dcache.fast_writes 0 # number of fast writes performed 994system.cpu1.dcache.cache_copies 0 # number of cache copies performed 995system.cpu1.dcache.writebacks::writebacks 119736 # number of writebacks 996system.cpu1.dcache.writebacks::total 119736 # number of writebacks 997system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 123485 # number of ReadReq MSHR misses 998system.cpu1.dcache.ReadReq_mshr_misses::total 123485 # number of ReadReq MSHR misses 999system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 65589 # number of WriteReq MSHR misses 1000system.cpu1.dcache.WriteReq_mshr_misses::total 65589 # number of WriteReq MSHR misses 1001system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9256 # number of LoadLockedReq MSHR misses 1002system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9256 # number of LoadLockedReq MSHR misses 1003system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6109 # number of StoreCondReq MSHR misses 1004system.cpu1.dcache.StoreCondReq_mshr_misses::total 6109 # number of StoreCondReq MSHR misses 1005system.cpu1.dcache.demand_mshr_misses::cpu1.data 189074 # number of demand (read+write) MSHR misses 1006system.cpu1.dcache.demand_mshr_misses::total 189074 # number of demand (read+write) MSHR misses 1007system.cpu1.dcache.overall_mshr_misses::cpu1.data 189074 # number of overall MSHR misses 1008system.cpu1.dcache.overall_mshr_misses::total 189074 # number of overall MSHR misses 1009system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 118 # number of ReadReq MSHR uncacheable 1010system.cpu1.dcache.ReadReq_mshr_uncacheable::total 118 # number of ReadReq MSHR uncacheable 1011system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3348 # number of WriteReq MSHR uncacheable 1012system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3348 # number of WriteReq MSHR uncacheable 1013system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3466 # number of overall MSHR uncacheable misses 1014system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3466 # number of overall MSHR uncacheable misses 1015system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1432479500 # number of ReadReq MSHR miss cycles 1016system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1432479500 # number of ReadReq MSHR miss cycles 1017system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1805216000 # number of WriteReq MSHR miss cycles 1018system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1805216000 # number of WriteReq MSHR miss cycles 1019system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 75819000 # number of LoadLockedReq MSHR miss cycles 1020system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 75819000 # number of LoadLockedReq MSHR miss cycles 1021system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 90846500 # number of StoreCondReq MSHR miss cycles 1022system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 90846500 # number of StoreCondReq MSHR miss cycles 1023system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3237695500 # number of demand (read+write) MSHR miss cycles 1024system.cpu1.dcache.demand_mshr_miss_latency::total 3237695500 # number of demand (read+write) MSHR miss cycles 1025system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3237695500 # number of overall MSHR miss cycles 1026system.cpu1.dcache.overall_mshr_miss_latency::total 3237695500 # number of overall MSHR miss cycles 1027system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 25051000 # number of ReadReq MSHR uncacheable cycles 1028system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 25051000 # number of ReadReq MSHR uncacheable cycles 1029system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 789482000 # number of WriteReq MSHR uncacheable cycles 1030system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 789482000 # number of WriteReq MSHR uncacheable cycles 1031system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 814533000 # number of overall MSHR uncacheable cycles 1032system.cpu1.dcache.overall_mshr_uncacheable_latency::total 814533000 # number of overall MSHR uncacheable cycles 1033system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.050136 # mshr miss rate for ReadReq accesses 1034system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.050136 # mshr miss rate for ReadReq accesses 1035system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036998 # mshr miss rate for WriteReq accesses 1036system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036998 # mshr miss rate for WriteReq accesses 1037system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.155091 # mshr miss rate for LoadLockedReq accesses 1038system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.155091 # mshr miss rate for LoadLockedReq accesses 1039system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103215 # mshr miss rate for StoreCondReq accesses 1040system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103215 # mshr miss rate for StoreCondReq accesses 1041system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044637 # mshr miss rate for demand accesses 1042system.cpu1.dcache.demand_mshr_miss_rate::total 0.044637 # mshr miss rate for demand accesses 1043system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044637 # mshr miss rate for overall accesses 1044system.cpu1.dcache.overall_mshr_miss_rate::total 0.044637 # mshr miss rate for overall accesses 1045system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11600.433251 # average ReadReq mshr miss latency 1046system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11600.433251 # average ReadReq mshr miss latency 1047system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27523.151748 # average WriteReq mshr miss latency 1048system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27523.151748 # average WriteReq mshr miss latency 1049system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8191.335350 # average LoadLockedReq mshr miss latency 1050system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8191.335350 # average LoadLockedReq mshr miss latency 1051system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14870.928139 # average StoreCondReq mshr miss latency 1052system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 14870.928139 # average StoreCondReq mshr miss latency 1053system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17123.959402 # average overall mshr miss latency 1054system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17123.959402 # average overall mshr miss latency 1055system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17123.959402 # average overall mshr miss latency 1056system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17123.959402 # average overall mshr miss latency 1057system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 212296.610169 # average ReadReq mshr uncacheable latency 1058system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 212296.610169 # average ReadReq mshr uncacheable latency 1059system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 235807.048984 # average WriteReq mshr uncacheable latency 1060system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 235807.048984 # average WriteReq mshr uncacheable latency 1061system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 235006.635892 # average overall mshr uncacheable latency 1062system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 235006.635892 # average overall mshr uncacheable latency 1063system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1064system.cpu1.icache.tags.replacements 331505 # number of replacements 1065system.cpu1.icache.tags.tagsinuse 442.932847 # Cycle average of tags in use 1066system.cpu1.icache.tags.total_refs 13357787 # Total number of references to valid blocks. 1067system.cpu1.icache.tags.sampled_refs 332017 # Sample count of references to valid blocks. 1068system.cpu1.icache.tags.avg_refs 40.232238 # Average number of references to valid blocks. 1069system.cpu1.icache.tags.warmup_cycle 1975288394500 # Cycle when the warmup percentage was hit. 1070system.cpu1.icache.tags.occ_blocks::cpu1.inst 442.932847 # Average occupied blocks per requestor 1071system.cpu1.icache.tags.occ_percent::cpu1.inst 0.865103 # Average percentage of cache occupancy 1072system.cpu1.icache.tags.occ_percent::total 0.865103 # Average percentage of cache occupancy 1073system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1074system.cpu1.icache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id 1075system.cpu1.icache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id 1076system.cpu1.icache.tags.age_task_id_blocks_1024::2 405 # Occupied blocks per task id 1077system.cpu1.icache.tags.age_task_id_blocks_1024::3 32 # Occupied blocks per task id 1078system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1079system.cpu1.icache.tags.tag_accesses 14021901 # Number of tag accesses 1080system.cpu1.icache.tags.data_accesses 14021901 # Number of data accesses 1081system.cpu1.icache.ReadReq_hits::cpu1.inst 13357787 # number of ReadReq hits 1082system.cpu1.icache.ReadReq_hits::total 13357787 # number of ReadReq hits 1083system.cpu1.icache.demand_hits::cpu1.inst 13357787 # number of demand (read+write) hits 1084system.cpu1.icache.demand_hits::total 13357787 # number of demand (read+write) hits 1085system.cpu1.icache.overall_hits::cpu1.inst 13357787 # number of overall hits 1086system.cpu1.icache.overall_hits::total 13357787 # number of overall hits 1087system.cpu1.icache.ReadReq_misses::cpu1.inst 332057 # number of ReadReq misses 1088system.cpu1.icache.ReadReq_misses::total 332057 # number of ReadReq misses 1089system.cpu1.icache.demand_misses::cpu1.inst 332057 # number of demand (read+write) misses 1090system.cpu1.icache.demand_misses::total 332057 # number of demand (read+write) misses 1091system.cpu1.icache.overall_misses::cpu1.inst 332057 # number of overall misses 1092system.cpu1.icache.overall_misses::total 332057 # number of overall misses 1093system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4541544500 # number of ReadReq miss cycles 1094system.cpu1.icache.ReadReq_miss_latency::total 4541544500 # number of ReadReq miss cycles 1095system.cpu1.icache.demand_miss_latency::cpu1.inst 4541544500 # number of demand (read+write) miss cycles 1096system.cpu1.icache.demand_miss_latency::total 4541544500 # number of demand (read+write) miss cycles 1097system.cpu1.icache.overall_miss_latency::cpu1.inst 4541544500 # number of overall miss cycles 1098system.cpu1.icache.overall_miss_latency::total 4541544500 # number of overall miss cycles 1099system.cpu1.icache.ReadReq_accesses::cpu1.inst 13689844 # number of ReadReq accesses(hits+misses) 1100system.cpu1.icache.ReadReq_accesses::total 13689844 # number of ReadReq accesses(hits+misses) 1101system.cpu1.icache.demand_accesses::cpu1.inst 13689844 # number of demand (read+write) accesses 1102system.cpu1.icache.demand_accesses::total 13689844 # number of demand (read+write) accesses 1103system.cpu1.icache.overall_accesses::cpu1.inst 13689844 # number of overall (read+write) accesses 1104system.cpu1.icache.overall_accesses::total 13689844 # number of overall (read+write) accesses 1105system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024256 # miss rate for ReadReq accesses 1106system.cpu1.icache.ReadReq_miss_rate::total 0.024256 # miss rate for ReadReq accesses 1107system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024256 # miss rate for demand accesses 1108system.cpu1.icache.demand_miss_rate::total 0.024256 # miss rate for demand accesses 1109system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024256 # miss rate for overall accesses 1110system.cpu1.icache.overall_miss_rate::total 0.024256 # miss rate for overall accesses 1111system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13677.002744 # average ReadReq miss latency 1112system.cpu1.icache.ReadReq_avg_miss_latency::total 13677.002744 # average ReadReq miss latency 1113system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13677.002744 # average overall miss latency 1114system.cpu1.icache.demand_avg_miss_latency::total 13677.002744 # average overall miss latency 1115system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13677.002744 # average overall miss latency 1116system.cpu1.icache.overall_avg_miss_latency::total 13677.002744 # average overall miss latency 1117system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1118system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1119system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1120system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1121system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1122system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1123system.cpu1.icache.fast_writes 0 # number of fast writes performed 1124system.cpu1.icache.cache_copies 0 # number of cache copies performed 1125system.cpu1.icache.writebacks::writebacks 331505 # number of writebacks 1126system.cpu1.icache.writebacks::total 331505 # number of writebacks 1127system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 332057 # number of ReadReq MSHR misses 1128system.cpu1.icache.ReadReq_mshr_misses::total 332057 # number of ReadReq MSHR misses 1129system.cpu1.icache.demand_mshr_misses::cpu1.inst 332057 # number of demand (read+write) MSHR misses 1130system.cpu1.icache.demand_mshr_misses::total 332057 # number of demand (read+write) MSHR misses 1131system.cpu1.icache.overall_mshr_misses::cpu1.inst 332057 # number of overall MSHR misses 1132system.cpu1.icache.overall_mshr_misses::total 332057 # number of overall MSHR misses 1133system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4209487500 # number of ReadReq MSHR miss cycles 1134system.cpu1.icache.ReadReq_mshr_miss_latency::total 4209487500 # number of ReadReq MSHR miss cycles 1135system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4209487500 # number of demand (read+write) MSHR miss cycles 1136system.cpu1.icache.demand_mshr_miss_latency::total 4209487500 # number of demand (read+write) MSHR miss cycles 1137system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4209487500 # number of overall MSHR miss cycles 1138system.cpu1.icache.overall_mshr_miss_latency::total 4209487500 # number of overall MSHR miss cycles 1139system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024256 # mshr miss rate for ReadReq accesses 1140system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024256 # mshr miss rate for ReadReq accesses 1141system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024256 # mshr miss rate for demand accesses 1142system.cpu1.icache.demand_mshr_miss_rate::total 0.024256 # mshr miss rate for demand accesses 1143system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024256 # mshr miss rate for overall accesses 1144system.cpu1.icache.overall_mshr_miss_rate::total 0.024256 # mshr miss rate for overall accesses 1145system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12677.002744 # average ReadReq mshr miss latency 1146system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12677.002744 # average ReadReq mshr miss latency 1147system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12677.002744 # average overall mshr miss latency 1148system.cpu1.icache.demand_avg_mshr_miss_latency::total 12677.002744 # average overall mshr miss latency 1149system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12677.002744 # average overall mshr miss latency 1150system.cpu1.icache.overall_avg_mshr_miss_latency::total 12677.002744 # average overall mshr miss latency 1151system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1152system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1153system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 1154system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 1155system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 1156system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 1157system.disk0.dma_write_txs 395 # Number of DMA write transactions. 1158system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1159system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1160system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1161system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 1162system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 1163system.disk2.dma_write_txs 1 # Number of DMA write transactions. 1164system.iobus.trans_dist::ReadReq 7379 # Transaction distribution 1165system.iobus.trans_dist::ReadResp 7379 # Transaction distribution 1166system.iobus.trans_dist::WriteReq 55684 # Transaction distribution 1167system.iobus.trans_dist::WriteResp 55684 # Transaction distribution 1168system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14066 # Packet count per connected master and slave (bytes) 1169system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) 1170system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 1171system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 1172system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 1173system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) 1174system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2476 # Packet count per connected master and slave (bytes) 1175system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6674 # Packet count per connected master and slave (bytes) 1176system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 1177system.iobus.pkt_count_system.bridge.master::total 42672 # Packet count per connected master and slave (bytes) 1178system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) 1179system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes) 1180system.iobus.pkt_count::total 126126 # Packet count per connected master and slave (bytes) 1181system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 56264 # Cumulative packet size per connected master and slave (bytes) 1182system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes) 1183system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 1184system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 1185system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 1186system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) 1187system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9884 # Cumulative packet size per connected master and slave (bytes) 1188system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4194 # Cumulative packet size per connected master and slave (bytes) 1189system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 1190system.iobus.pkt_size_system.bridge.master::total 82507 # Cumulative packet size per connected master and slave (bytes) 1191system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) 1192system.iobus.pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes) 1193system.iobus.pkt_size::total 2744131 # Cumulative packet size per connected master and slave (bytes) 1194system.iobus.reqLayer0.occupancy 15127500 # Layer occupancy (ticks) 1195system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1196system.iobus.reqLayer1.occupancy 758000 # Layer occupancy (ticks) 1197system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1198system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks) 1199system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1200system.iobus.reqLayer6.occupancy 10000 # Layer occupancy (ticks) 1201system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1202system.iobus.reqLayer22.occupancy 175000 # Layer occupancy (ticks) 1203system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 1204system.iobus.reqLayer23.occupancy 15843000 # Layer occupancy (ticks) 1205system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1206system.iobus.reqLayer24.occupancy 2460000 # Layer occupancy (ticks) 1207system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1208system.iobus.reqLayer25.occupancy 6055000 # Layer occupancy (ticks) 1209system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1210system.iobus.reqLayer26.occupancy 83000 # Layer occupancy (ticks) 1211system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1212system.iobus.reqLayer27.occupancy 215669663 # Layer occupancy (ticks) 1213system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1214system.iobus.respLayer0.occupancy 28540000 # Layer occupancy (ticks) 1215system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1216system.iobus.respLayer1.occupancy 41950000 # Layer occupancy (ticks) 1217system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 1218system.iocache.tags.replacements 41695 # number of replacements 1219system.iocache.tags.tagsinuse 0.566874 # Cycle average of tags in use 1220system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1221system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks. 1222system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1223system.iocache.tags.warmup_cycle 1775103309000 # Cycle when the warmup percentage was hit. 1224system.iocache.tags.occ_blocks::tsunami.ide 0.566874 # Average occupied blocks per requestor 1225system.iocache.tags.occ_percent::tsunami.ide 0.035430 # Average percentage of cache occupancy 1226system.iocache.tags.occ_percent::total 0.035430 # Average percentage of cache occupancy 1227system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1228system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1229system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1230system.iocache.tags.tag_accesses 375543 # Number of tag accesses 1231system.iocache.tags.data_accesses 375543 # Number of data accesses 1232system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses 1233system.iocache.ReadReq_misses::total 175 # number of ReadReq misses 1234system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 1235system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses 1236system.iocache.demand_misses::tsunami.ide 175 # number of demand (read+write) misses 1237system.iocache.demand_misses::total 175 # number of demand (read+write) misses 1238system.iocache.overall_misses::tsunami.ide 175 # number of overall misses 1239system.iocache.overall_misses::total 175 # number of overall misses 1240system.iocache.ReadReq_miss_latency::tsunami.ide 21956883 # number of ReadReq miss cycles 1241system.iocache.ReadReq_miss_latency::total 21956883 # number of ReadReq miss cycles 1242system.iocache.WriteLineReq_miss_latency::tsunami.ide 5245212780 # number of WriteLineReq miss cycles 1243system.iocache.WriteLineReq_miss_latency::total 5245212780 # number of WriteLineReq miss cycles 1244system.iocache.demand_miss_latency::tsunami.ide 21956883 # number of demand (read+write) miss cycles 1245system.iocache.demand_miss_latency::total 21956883 # number of demand (read+write) miss cycles 1246system.iocache.overall_miss_latency::tsunami.ide 21956883 # number of overall miss cycles 1247system.iocache.overall_miss_latency::total 21956883 # number of overall miss cycles 1248system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) 1249system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) 1250system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) 1251system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) 1252system.iocache.demand_accesses::tsunami.ide 175 # number of demand (read+write) accesses 1253system.iocache.demand_accesses::total 175 # number of demand (read+write) accesses 1254system.iocache.overall_accesses::tsunami.ide 175 # number of overall (read+write) accesses 1255system.iocache.overall_accesses::total 175 # number of overall (read+write) accesses 1256system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 1257system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1258system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses 1259system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1260system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 1261system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1262system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 1263system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1264system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125467.902857 # average ReadReq miss latency 1265system.iocache.ReadReq_avg_miss_latency::total 125467.902857 # average ReadReq miss latency 1266system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126232.498556 # average WriteLineReq miss latency 1267system.iocache.WriteLineReq_avg_miss_latency::total 126232.498556 # average WriteLineReq miss latency 1268system.iocache.demand_avg_miss_latency::tsunami.ide 125467.902857 # average overall miss latency 1269system.iocache.demand_avg_miss_latency::total 125467.902857 # average overall miss latency 1270system.iocache.overall_avg_miss_latency::tsunami.ide 125467.902857 # average overall miss latency 1271system.iocache.overall_avg_miss_latency::total 125467.902857 # average overall miss latency 1272system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1273system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1274system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1275system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1276system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1277system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1278system.iocache.fast_writes 0 # number of fast writes performed 1279system.iocache.cache_copies 0 # number of cache copies performed 1280system.iocache.writebacks::writebacks 41520 # number of writebacks 1281system.iocache.writebacks::total 41520 # number of writebacks 1282system.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses 1283system.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses 1284system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses 1285system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses 1286system.iocache.demand_mshr_misses::tsunami.ide 175 # number of demand (read+write) MSHR misses 1287system.iocache.demand_mshr_misses::total 175 # number of demand (read+write) MSHR misses 1288system.iocache.overall_mshr_misses::tsunami.ide 175 # number of overall MSHR misses 1289system.iocache.overall_mshr_misses::total 175 # number of overall MSHR misses 1290system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13206883 # number of ReadReq MSHR miss cycles 1291system.iocache.ReadReq_mshr_miss_latency::total 13206883 # number of ReadReq MSHR miss cycles 1292system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3165805993 # number of WriteLineReq MSHR miss cycles 1293system.iocache.WriteLineReq_mshr_miss_latency::total 3165805993 # number of WriteLineReq MSHR miss cycles 1294system.iocache.demand_mshr_miss_latency::tsunami.ide 13206883 # number of demand (read+write) MSHR miss cycles 1295system.iocache.demand_mshr_miss_latency::total 13206883 # number of demand (read+write) MSHR miss cycles 1296system.iocache.overall_mshr_miss_latency::tsunami.ide 13206883 # number of overall MSHR miss cycles 1297system.iocache.overall_mshr_miss_latency::total 13206883 # number of overall MSHR miss cycles 1298system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 1299system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1300system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses 1301system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1302system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 1303system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1304system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 1305system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1306system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75467.902857 # average ReadReq mshr miss latency 1307system.iocache.ReadReq_avg_mshr_miss_latency::total 75467.902857 # average ReadReq mshr miss latency 1308system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76189.016004 # average WriteLineReq mshr miss latency 1309system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76189.016004 # average WriteLineReq mshr miss latency 1310system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75467.902857 # average overall mshr miss latency 1311system.iocache.demand_avg_mshr_miss_latency::total 75467.902857 # average overall mshr miss latency 1312system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75467.902857 # average overall mshr miss latency 1313system.iocache.overall_avg_mshr_miss_latency::total 75467.902857 # average overall mshr miss latency 1314system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1315system.l2c.tags.replacements 342144 # number of replacements 1316system.l2c.tags.tagsinuse 65164.214079 # Cycle average of tags in use 1317system.l2c.tags.total_refs 3686310 # Total number of references to valid blocks. 1318system.l2c.tags.sampled_refs 407150 # Sample count of references to valid blocks. 1319system.l2c.tags.avg_refs 9.053936 # Average number of references to valid blocks. 1320system.l2c.tags.warmup_cycle 12928623000 # Cycle when the warmup percentage was hit. 1321system.l2c.tags.occ_blocks::writebacks 54851.914684 # Average occupied blocks per requestor 1322system.l2c.tags.occ_blocks::cpu0.inst 4798.806705 # Average occupied blocks per requestor 1323system.l2c.tags.occ_blocks::cpu0.data 5354.570072 # Average occupied blocks per requestor 1324system.l2c.tags.occ_blocks::cpu1.inst 119.591740 # Average occupied blocks per requestor 1325system.l2c.tags.occ_blocks::cpu1.data 39.330879 # Average occupied blocks per requestor 1326system.l2c.tags.occ_percent::writebacks 0.836974 # Average percentage of cache occupancy 1327system.l2c.tags.occ_percent::cpu0.inst 0.073224 # Average percentage of cache occupancy 1328system.l2c.tags.occ_percent::cpu0.data 0.081704 # Average percentage of cache occupancy 1329system.l2c.tags.occ_percent::cpu1.inst 0.001825 # Average percentage of cache occupancy 1330system.l2c.tags.occ_percent::cpu1.data 0.000600 # Average percentage of cache occupancy 1331system.l2c.tags.occ_percent::total 0.994327 # Average percentage of cache occupancy 1332system.l2c.tags.occ_task_id_blocks::1024 65006 # Occupied blocks per task id 1333system.l2c.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id 1334system.l2c.tags.age_task_id_blocks_1024::1 517 # Occupied blocks per task id 1335system.l2c.tags.age_task_id_blocks_1024::2 5381 # Occupied blocks per task id 1336system.l2c.tags.age_task_id_blocks_1024::3 6294 # Occupied blocks per task id 1337system.l2c.tags.age_task_id_blocks_1024::4 52712 # Occupied blocks per task id 1338system.l2c.tags.occ_task_id_percent::1024 0.991913 # Percentage of cache occupancy per task id 1339system.l2c.tags.tag_accesses 35907872 # Number of tag accesses 1340system.l2c.tags.data_accesses 35907872 # Number of data accesses 1341system.l2c.WritebackDirty_hits::writebacks 792557 # number of WritebackDirty hits 1342system.l2c.WritebackDirty_hits::total 792557 # number of WritebackDirty hits 1343system.l2c.WritebackClean_hits::writebacks 746952 # number of WritebackClean hits 1344system.l2c.WritebackClean_hits::total 746952 # number of WritebackClean hits 1345system.l2c.UpgradeReq_hits::cpu0.data 186 # number of UpgradeReq hits 1346system.l2c.UpgradeReq_hits::cpu1.data 548 # number of UpgradeReq hits 1347system.l2c.UpgradeReq_hits::total 734 # number of UpgradeReq hits 1348system.l2c.SCUpgradeReq_hits::cpu0.data 40 # number of SCUpgradeReq hits 1349system.l2c.SCUpgradeReq_hits::cpu1.data 23 # number of SCUpgradeReq hits 1350system.l2c.SCUpgradeReq_hits::total 63 # number of SCUpgradeReq hits 1351system.l2c.ReadExReq_hits::cpu0.data 124117 # number of ReadExReq hits 1352system.l2c.ReadExReq_hits::cpu1.data 48557 # number of ReadExReq hits 1353system.l2c.ReadExReq_hits::total 172674 # number of ReadExReq hits 1354system.l2c.ReadCleanReq_hits::cpu0.inst 674696 # number of ReadCleanReq hits 1355system.l2c.ReadCleanReq_hits::cpu1.inst 331117 # number of ReadCleanReq hits 1356system.l2c.ReadCleanReq_hits::total 1005813 # number of ReadCleanReq hits 1357system.l2c.ReadSharedReq_hits::cpu0.data 659477 # number of ReadSharedReq hits 1358system.l2c.ReadSharedReq_hits::cpu1.data 113729 # number of ReadSharedReq hits 1359system.l2c.ReadSharedReq_hits::total 773206 # number of ReadSharedReq hits 1360system.l2c.demand_hits::cpu0.inst 674696 # number of demand (read+write) hits 1361system.l2c.demand_hits::cpu0.data 783594 # number of demand (read+write) hits 1362system.l2c.demand_hits::cpu1.inst 331117 # number of demand (read+write) hits 1363system.l2c.demand_hits::cpu1.data 162286 # number of demand (read+write) hits 1364system.l2c.demand_hits::total 1951693 # number of demand (read+write) hits 1365system.l2c.overall_hits::cpu0.inst 674696 # number of overall hits 1366system.l2c.overall_hits::cpu0.data 783594 # number of overall hits 1367system.l2c.overall_hits::cpu1.inst 331117 # number of overall hits 1368system.l2c.overall_hits::cpu1.data 162286 # number of overall hits 1369system.l2c.overall_hits::total 1951693 # number of overall hits 1370system.l2c.UpgradeReq_misses::cpu0.data 2972 # number of UpgradeReq misses 1371system.l2c.UpgradeReq_misses::cpu1.data 1811 # number of UpgradeReq misses 1372system.l2c.UpgradeReq_misses::total 4783 # number of UpgradeReq misses 1373system.l2c.SCUpgradeReq_misses::cpu0.data 926 # number of SCUpgradeReq misses 1374system.l2c.SCUpgradeReq_misses::cpu1.data 930 # number of SCUpgradeReq misses 1375system.l2c.SCUpgradeReq_misses::total 1856 # number of SCUpgradeReq misses 1376system.l2c.ReadExReq_misses::cpu0.data 114977 # number of ReadExReq misses 1377system.l2c.ReadExReq_misses::cpu1.data 7877 # number of ReadExReq misses 1378system.l2c.ReadExReq_misses::total 122854 # number of ReadExReq misses 1379system.l2c.ReadCleanReq_misses::cpu0.inst 12504 # number of ReadCleanReq misses 1380system.l2c.ReadCleanReq_misses::cpu1.inst 939 # number of ReadCleanReq misses 1381system.l2c.ReadCleanReq_misses::total 13443 # number of ReadCleanReq misses 1382system.l2c.ReadSharedReq_misses::cpu0.data 271537 # number of ReadSharedReq misses 1383system.l2c.ReadSharedReq_misses::cpu1.data 337 # number of ReadSharedReq misses 1384system.l2c.ReadSharedReq_misses::total 271874 # number of ReadSharedReq misses 1385system.l2c.demand_misses::cpu0.inst 12504 # number of demand (read+write) misses 1386system.l2c.demand_misses::cpu0.data 386514 # number of demand (read+write) misses 1387system.l2c.demand_misses::cpu1.inst 939 # number of demand (read+write) misses 1388system.l2c.demand_misses::cpu1.data 8214 # number of demand (read+write) misses 1389system.l2c.demand_misses::total 408171 # number of demand (read+write) misses 1390system.l2c.overall_misses::cpu0.inst 12504 # number of overall misses 1391system.l2c.overall_misses::cpu0.data 386514 # number of overall misses 1392system.l2c.overall_misses::cpu1.inst 939 # number of overall misses 1393system.l2c.overall_misses::cpu1.data 8214 # number of overall misses 1394system.l2c.overall_misses::total 408171 # number of overall misses 1395system.l2c.UpgradeReq_miss_latency::cpu0.data 3619500 # number of UpgradeReq miss cycles 1396system.l2c.UpgradeReq_miss_latency::cpu1.data 35439500 # number of UpgradeReq miss cycles 1397system.l2c.UpgradeReq_miss_latency::total 39059000 # number of UpgradeReq miss cycles 1398system.l2c.SCUpgradeReq_miss_latency::cpu0.data 3369500 # number of SCUpgradeReq miss cycles 1399system.l2c.SCUpgradeReq_miss_latency::cpu1.data 943000 # number of SCUpgradeReq miss cycles 1400system.l2c.SCUpgradeReq_miss_latency::total 4312500 # number of SCUpgradeReq miss cycles 1401system.l2c.ReadExReq_miss_latency::cpu0.data 14618391000 # number of ReadExReq miss cycles 1402system.l2c.ReadExReq_miss_latency::cpu1.data 1036807500 # number of ReadExReq miss cycles 1403system.l2c.ReadExReq_miss_latency::total 15655198500 # number of ReadExReq miss cycles 1404system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1642625500 # number of ReadCleanReq miss cycles 1405system.l2c.ReadCleanReq_miss_latency::cpu1.inst 124569500 # number of ReadCleanReq miss cycles 1406system.l2c.ReadCleanReq_miss_latency::total 1767195000 # number of ReadCleanReq miss cycles 1407system.l2c.ReadSharedReq_miss_latency::cpu0.data 33669095000 # number of ReadSharedReq miss cycles 1408system.l2c.ReadSharedReq_miss_latency::cpu1.data 43269000 # number of ReadSharedReq miss cycles 1409system.l2c.ReadSharedReq_miss_latency::total 33712364000 # number of ReadSharedReq miss cycles 1410system.l2c.demand_miss_latency::cpu0.inst 1642625500 # number of demand (read+write) miss cycles 1411system.l2c.demand_miss_latency::cpu0.data 48287486000 # number of demand (read+write) miss cycles 1412system.l2c.demand_miss_latency::cpu1.inst 124569500 # number of demand (read+write) miss cycles 1413system.l2c.demand_miss_latency::cpu1.data 1080076500 # number of demand (read+write) miss cycles 1414system.l2c.demand_miss_latency::total 51134757500 # number of demand (read+write) miss cycles 1415system.l2c.overall_miss_latency::cpu0.inst 1642625500 # number of overall miss cycles 1416system.l2c.overall_miss_latency::cpu0.data 48287486000 # number of overall miss cycles 1417system.l2c.overall_miss_latency::cpu1.inst 124569500 # number of overall miss cycles 1418system.l2c.overall_miss_latency::cpu1.data 1080076500 # number of overall miss cycles 1419system.l2c.overall_miss_latency::total 51134757500 # number of overall miss cycles 1420system.l2c.WritebackDirty_accesses::writebacks 792557 # number of WritebackDirty accesses(hits+misses) 1421system.l2c.WritebackDirty_accesses::total 792557 # number of WritebackDirty accesses(hits+misses) 1422system.l2c.WritebackClean_accesses::writebacks 746952 # number of WritebackClean accesses(hits+misses) 1423system.l2c.WritebackClean_accesses::total 746952 # number of WritebackClean accesses(hits+misses) 1424system.l2c.UpgradeReq_accesses::cpu0.data 3158 # number of UpgradeReq accesses(hits+misses) 1425system.l2c.UpgradeReq_accesses::cpu1.data 2359 # number of UpgradeReq accesses(hits+misses) 1426system.l2c.UpgradeReq_accesses::total 5517 # number of UpgradeReq accesses(hits+misses) 1427system.l2c.SCUpgradeReq_accesses::cpu0.data 966 # number of SCUpgradeReq accesses(hits+misses) 1428system.l2c.SCUpgradeReq_accesses::cpu1.data 953 # number of SCUpgradeReq accesses(hits+misses) 1429system.l2c.SCUpgradeReq_accesses::total 1919 # number of SCUpgradeReq accesses(hits+misses) 1430system.l2c.ReadExReq_accesses::cpu0.data 239094 # number of ReadExReq accesses(hits+misses) 1431system.l2c.ReadExReq_accesses::cpu1.data 56434 # number of ReadExReq accesses(hits+misses) 1432system.l2c.ReadExReq_accesses::total 295528 # number of ReadExReq accesses(hits+misses) 1433system.l2c.ReadCleanReq_accesses::cpu0.inst 687200 # number of ReadCleanReq accesses(hits+misses) 1434system.l2c.ReadCleanReq_accesses::cpu1.inst 332056 # number of ReadCleanReq accesses(hits+misses) 1435system.l2c.ReadCleanReq_accesses::total 1019256 # number of ReadCleanReq accesses(hits+misses) 1436system.l2c.ReadSharedReq_accesses::cpu0.data 931014 # number of ReadSharedReq accesses(hits+misses) 1437system.l2c.ReadSharedReq_accesses::cpu1.data 114066 # number of ReadSharedReq accesses(hits+misses) 1438system.l2c.ReadSharedReq_accesses::total 1045080 # number of ReadSharedReq accesses(hits+misses) 1439system.l2c.demand_accesses::cpu0.inst 687200 # number of demand (read+write) accesses 1440system.l2c.demand_accesses::cpu0.data 1170108 # number of demand (read+write) accesses 1441system.l2c.demand_accesses::cpu1.inst 332056 # number of demand (read+write) accesses 1442system.l2c.demand_accesses::cpu1.data 170500 # number of demand (read+write) accesses 1443system.l2c.demand_accesses::total 2359864 # number of demand (read+write) accesses 1444system.l2c.overall_accesses::cpu0.inst 687200 # number of overall (read+write) accesses 1445system.l2c.overall_accesses::cpu0.data 1170108 # number of overall (read+write) accesses 1446system.l2c.overall_accesses::cpu1.inst 332056 # number of overall (read+write) accesses 1447system.l2c.overall_accesses::cpu1.data 170500 # number of overall (read+write) accesses 1448system.l2c.overall_accesses::total 2359864 # number of overall (read+write) accesses 1449system.l2c.UpgradeReq_miss_rate::cpu0.data 0.941102 # miss rate for UpgradeReq accesses 1450system.l2c.UpgradeReq_miss_rate::cpu1.data 0.767698 # miss rate for UpgradeReq accesses 1451system.l2c.UpgradeReq_miss_rate::total 0.866957 # miss rate for UpgradeReq accesses 1452system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.958592 # miss rate for SCUpgradeReq accesses 1453system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.975866 # miss rate for SCUpgradeReq accesses 1454system.l2c.SCUpgradeReq_miss_rate::total 0.967170 # miss rate for SCUpgradeReq accesses 1455system.l2c.ReadExReq_miss_rate::cpu0.data 0.480886 # miss rate for ReadExReq accesses 1456system.l2c.ReadExReq_miss_rate::cpu1.data 0.139579 # miss rate for ReadExReq accesses 1457system.l2c.ReadExReq_miss_rate::total 0.415710 # miss rate for ReadExReq accesses 1458system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.018196 # miss rate for ReadCleanReq accesses 1459system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.002828 # miss rate for ReadCleanReq accesses 1460system.l2c.ReadCleanReq_miss_rate::total 0.013189 # miss rate for ReadCleanReq accesses 1461system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.291657 # miss rate for ReadSharedReq accesses 1462system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.002954 # miss rate for ReadSharedReq accesses 1463system.l2c.ReadSharedReq_miss_rate::total 0.260147 # miss rate for ReadSharedReq accesses 1464system.l2c.demand_miss_rate::cpu0.inst 0.018196 # miss rate for demand accesses 1465system.l2c.demand_miss_rate::cpu0.data 0.330323 # miss rate for demand accesses 1466system.l2c.demand_miss_rate::cpu1.inst 0.002828 # miss rate for demand accesses 1467system.l2c.demand_miss_rate::cpu1.data 0.048176 # miss rate for demand accesses 1468system.l2c.demand_miss_rate::total 0.172964 # miss rate for demand accesses 1469system.l2c.overall_miss_rate::cpu0.inst 0.018196 # miss rate for overall accesses 1470system.l2c.overall_miss_rate::cpu0.data 0.330323 # miss rate for overall accesses 1471system.l2c.overall_miss_rate::cpu1.inst 0.002828 # miss rate for overall accesses 1472system.l2c.overall_miss_rate::cpu1.data 0.048176 # miss rate for overall accesses 1473system.l2c.overall_miss_rate::total 0.172964 # miss rate for overall accesses 1474system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1217.866756 # average UpgradeReq miss latency 1475system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 19569.022639 # average UpgradeReq miss latency 1476system.l2c.UpgradeReq_avg_miss_latency::total 8166.213673 # average UpgradeReq miss latency 1477system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3638.768898 # average SCUpgradeReq miss latency 1478system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1013.978495 # average SCUpgradeReq miss latency 1479system.l2c.SCUpgradeReq_avg_miss_latency::total 2323.545259 # average SCUpgradeReq miss latency 1480system.l2c.ReadExReq_avg_miss_latency::cpu0.data 127141.871853 # average ReadExReq miss latency 1481system.l2c.ReadExReq_avg_miss_latency::cpu1.data 131624.666751 # average ReadExReq miss latency 1482system.l2c.ReadExReq_avg_miss_latency::total 127429.294121 # average ReadExReq miss latency 1483system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 131368.002239 # average ReadCleanReq miss latency 1484system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 132661.874334 # average ReadCleanReq miss latency 1485system.l2c.ReadCleanReq_avg_miss_latency::total 131458.379826 # average ReadCleanReq miss latency 1486system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 123994.501670 # average ReadSharedReq miss latency 1487system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 128394.658754 # average ReadSharedReq miss latency 1488system.l2c.ReadSharedReq_avg_miss_latency::total 123999.955862 # average ReadSharedReq miss latency 1489system.l2c.demand_avg_miss_latency::cpu0.inst 131368.002239 # average overall miss latency 1490system.l2c.demand_avg_miss_latency::cpu0.data 124930.755419 # average overall miss latency 1491system.l2c.demand_avg_miss_latency::cpu1.inst 132661.874334 # average overall miss latency 1492system.l2c.demand_avg_miss_latency::cpu1.data 131492.147553 # average overall miss latency 1493system.l2c.demand_avg_miss_latency::total 125277.781861 # average overall miss latency 1494system.l2c.overall_avg_miss_latency::cpu0.inst 131368.002239 # average overall miss latency 1495system.l2c.overall_avg_miss_latency::cpu0.data 124930.755419 # average overall miss latency 1496system.l2c.overall_avg_miss_latency::cpu1.inst 132661.874334 # average overall miss latency 1497system.l2c.overall_avg_miss_latency::cpu1.data 131492.147553 # average overall miss latency 1498system.l2c.overall_avg_miss_latency::total 125277.781861 # average overall miss latency 1499system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1500system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 1501system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 1502system.l2c.blocked::no_targets 0 # number of cycles access was blocked 1503system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1504system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1505system.l2c.fast_writes 0 # number of fast writes performed 1506system.l2c.cache_copies 0 # number of cache copies performed 1507system.l2c.writebacks::writebacks 79416 # number of writebacks 1508system.l2c.writebacks::total 79416 # number of writebacks 1509system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 11 # number of ReadCleanReq MSHR hits 1510system.l2c.ReadCleanReq_mshr_hits::total 11 # number of ReadCleanReq MSHR hits 1511system.l2c.demand_mshr_hits::cpu1.inst 11 # number of demand (read+write) MSHR hits 1512system.l2c.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits 1513system.l2c.overall_mshr_hits::cpu1.inst 11 # number of overall MSHR hits 1514system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits 1515system.l2c.CleanEvict_mshr_misses::writebacks 10 # number of CleanEvict MSHR misses 1516system.l2c.CleanEvict_mshr_misses::total 10 # number of CleanEvict MSHR misses 1517system.l2c.UpgradeReq_mshr_misses::cpu0.data 2972 # number of UpgradeReq MSHR misses 1518system.l2c.UpgradeReq_mshr_misses::cpu1.data 1811 # number of UpgradeReq MSHR misses 1519system.l2c.UpgradeReq_mshr_misses::total 4783 # number of UpgradeReq MSHR misses 1520system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 926 # number of SCUpgradeReq MSHR misses 1521system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 930 # number of SCUpgradeReq MSHR misses 1522system.l2c.SCUpgradeReq_mshr_misses::total 1856 # number of SCUpgradeReq MSHR misses 1523system.l2c.ReadExReq_mshr_misses::cpu0.data 114977 # number of ReadExReq MSHR misses 1524system.l2c.ReadExReq_mshr_misses::cpu1.data 7877 # number of ReadExReq MSHR misses 1525system.l2c.ReadExReq_mshr_misses::total 122854 # number of ReadExReq MSHR misses 1526system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 12504 # number of ReadCleanReq MSHR misses 1527system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 928 # number of ReadCleanReq MSHR misses 1528system.l2c.ReadCleanReq_mshr_misses::total 13432 # number of ReadCleanReq MSHR misses 1529system.l2c.ReadSharedReq_mshr_misses::cpu0.data 271537 # number of ReadSharedReq MSHR misses 1530system.l2c.ReadSharedReq_mshr_misses::cpu1.data 337 # number of ReadSharedReq MSHR misses 1531system.l2c.ReadSharedReq_mshr_misses::total 271874 # number of ReadSharedReq MSHR misses 1532system.l2c.demand_mshr_misses::cpu0.inst 12504 # number of demand (read+write) MSHR misses 1533system.l2c.demand_mshr_misses::cpu0.data 386514 # number of demand (read+write) MSHR misses 1534system.l2c.demand_mshr_misses::cpu1.inst 928 # number of demand (read+write) MSHR misses 1535system.l2c.demand_mshr_misses::cpu1.data 8214 # number of demand (read+write) MSHR misses 1536system.l2c.demand_mshr_misses::total 408160 # number of demand (read+write) MSHR misses 1537system.l2c.overall_mshr_misses::cpu0.inst 12504 # number of overall MSHR misses 1538system.l2c.overall_mshr_misses::cpu0.data 386514 # number of overall MSHR misses 1539system.l2c.overall_mshr_misses::cpu1.inst 928 # number of overall MSHR misses 1540system.l2c.overall_mshr_misses::cpu1.data 8214 # number of overall MSHR misses 1541system.l2c.overall_mshr_misses::total 408160 # number of overall MSHR misses 1542system.l2c.ReadReq_mshr_uncacheable::cpu0.data 7086 # number of ReadReq MSHR uncacheable 1543system.l2c.ReadReq_mshr_uncacheable::cpu1.data 118 # number of ReadReq MSHR uncacheable 1544system.l2c.ReadReq_mshr_uncacheable::total 7204 # number of ReadReq MSHR uncacheable 1545system.l2c.WriteReq_mshr_uncacheable::cpu0.data 10784 # number of WriteReq MSHR uncacheable 1546system.l2c.WriteReq_mshr_uncacheable::cpu1.data 3348 # number of WriteReq MSHR uncacheable 1547system.l2c.WriteReq_mshr_uncacheable::total 14132 # number of WriteReq MSHR uncacheable 1548system.l2c.overall_mshr_uncacheable_misses::cpu0.data 17870 # number of overall MSHR uncacheable misses 1549system.l2c.overall_mshr_uncacheable_misses::cpu1.data 3466 # number of overall MSHR uncacheable misses 1550system.l2c.overall_mshr_uncacheable_misses::total 21336 # number of overall MSHR uncacheable misses 1551system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 204336000 # number of UpgradeReq MSHR miss cycles 1552system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 124703500 # number of UpgradeReq MSHR miss cycles 1553system.l2c.UpgradeReq_mshr_miss_latency::total 329039500 # number of UpgradeReq MSHR miss cycles 1554system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 63412000 # number of SCUpgradeReq MSHR miss cycles 1555system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 64097500 # number of SCUpgradeReq MSHR miss cycles 1556system.l2c.SCUpgradeReq_mshr_miss_latency::total 127509500 # number of SCUpgradeReq MSHR miss cycles 1557system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 13468621000 # number of ReadExReq MSHR miss cycles 1558system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 958037500 # number of ReadExReq MSHR miss cycles 1559system.l2c.ReadExReq_mshr_miss_latency::total 14426658500 # number of ReadExReq MSHR miss cycles 1560system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 1517585500 # number of ReadCleanReq MSHR miss cycles 1561system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 113934001 # number of ReadCleanReq MSHR miss cycles 1562system.l2c.ReadCleanReq_mshr_miss_latency::total 1631519501 # number of ReadCleanReq MSHR miss cycles 1563system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 30953725000 # number of ReadSharedReq MSHR miss cycles 1564system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 39899000 # number of ReadSharedReq MSHR miss cycles 1565system.l2c.ReadSharedReq_mshr_miss_latency::total 30993624000 # number of ReadSharedReq MSHR miss cycles 1566system.l2c.demand_mshr_miss_latency::cpu0.inst 1517585500 # number of demand (read+write) MSHR miss cycles 1567system.l2c.demand_mshr_miss_latency::cpu0.data 44422346000 # number of demand (read+write) MSHR miss cycles 1568system.l2c.demand_mshr_miss_latency::cpu1.inst 113934001 # number of demand (read+write) MSHR miss cycles 1569system.l2c.demand_mshr_miss_latency::cpu1.data 997936500 # number of demand (read+write) MSHR miss cycles 1570system.l2c.demand_mshr_miss_latency::total 47051802001 # number of demand (read+write) MSHR miss cycles 1571system.l2c.overall_mshr_miss_latency::cpu0.inst 1517585500 # number of overall MSHR miss cycles 1572system.l2c.overall_mshr_miss_latency::cpu0.data 44422346000 # number of overall MSHR miss cycles 1573system.l2c.overall_mshr_miss_latency::cpu1.inst 113934001 # number of overall MSHR miss cycles 1574system.l2c.overall_mshr_miss_latency::cpu1.data 997936500 # number of overall MSHR miss cycles 1575system.l2c.overall_mshr_miss_latency::total 47051802001 # number of overall MSHR miss cycles 1576system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1478927500 # number of ReadReq MSHR uncacheable cycles 1577system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 23575500 # number of ReadReq MSHR uncacheable cycles 1578system.l2c.ReadReq_mshr_uncacheable_latency::total 1502503000 # number of ReadReq MSHR uncacheable cycles 1579system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2327963000 # number of WriteReq MSHR uncacheable cycles 1580system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 750967000 # number of WriteReq MSHR uncacheable cycles 1581system.l2c.WriteReq_mshr_uncacheable_latency::total 3078930000 # number of WriteReq MSHR uncacheable cycles 1582system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3806890500 # number of overall MSHR uncacheable cycles 1583system.l2c.overall_mshr_uncacheable_latency::cpu1.data 774542500 # number of overall MSHR uncacheable cycles 1584system.l2c.overall_mshr_uncacheable_latency::total 4581433000 # number of overall MSHR uncacheable cycles 1585system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 1586system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 1587system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.941102 # mshr miss rate for UpgradeReq accesses 1588system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.767698 # mshr miss rate for UpgradeReq accesses 1589system.l2c.UpgradeReq_mshr_miss_rate::total 0.866957 # mshr miss rate for UpgradeReq accesses 1590system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.958592 # mshr miss rate for SCUpgradeReq accesses 1591system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.975866 # mshr miss rate for SCUpgradeReq accesses 1592system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.967170 # mshr miss rate for SCUpgradeReq accesses 1593system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.480886 # mshr miss rate for ReadExReq accesses 1594system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.139579 # mshr miss rate for ReadExReq accesses 1595system.l2c.ReadExReq_mshr_miss_rate::total 0.415710 # mshr miss rate for ReadExReq accesses 1596system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.018196 # mshr miss rate for ReadCleanReq accesses 1597system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.002795 # mshr miss rate for ReadCleanReq accesses 1598system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013178 # mshr miss rate for ReadCleanReq accesses 1599system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.291657 # mshr miss rate for ReadSharedReq accesses 1600system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.002954 # mshr miss rate for ReadSharedReq accesses 1601system.l2c.ReadSharedReq_mshr_miss_rate::total 0.260147 # mshr miss rate for ReadSharedReq accesses 1602system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018196 # mshr miss rate for demand accesses 1603system.l2c.demand_mshr_miss_rate::cpu0.data 0.330323 # mshr miss rate for demand accesses 1604system.l2c.demand_mshr_miss_rate::cpu1.inst 0.002795 # mshr miss rate for demand accesses 1605system.l2c.demand_mshr_miss_rate::cpu1.data 0.048176 # mshr miss rate for demand accesses 1606system.l2c.demand_mshr_miss_rate::total 0.172959 # mshr miss rate for demand accesses 1607system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018196 # mshr miss rate for overall accesses 1608system.l2c.overall_mshr_miss_rate::cpu0.data 0.330323 # mshr miss rate for overall accesses 1609system.l2c.overall_mshr_miss_rate::cpu1.inst 0.002795 # mshr miss rate for overall accesses 1610system.l2c.overall_mshr_miss_rate::cpu1.data 0.048176 # mshr miss rate for overall accesses 1611system.l2c.overall_mshr_miss_rate::total 0.172959 # mshr miss rate for overall accesses 1612system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 68753.701211 # average UpgradeReq mshr miss latency 1613system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 68858.917725 # average UpgradeReq mshr miss latency 1614system.l2c.UpgradeReq_avg_mshr_miss_latency::total 68793.539619 # average UpgradeReq mshr miss latency 1615system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 68479.481641 # average SCUpgradeReq mshr miss latency 1616system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 68922.043011 # average SCUpgradeReq mshr miss latency 1617system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 68701.239224 # average SCUpgradeReq mshr miss latency 1618system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 117141.871853 # average ReadExReq mshr miss latency 1619system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121624.666751 # average ReadExReq mshr miss latency 1620system.l2c.ReadExReq_avg_mshr_miss_latency::total 117429.294121 # average ReadExReq mshr miss latency 1621system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 121368.002239 # average ReadCleanReq mshr miss latency 1622system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122773.707974 # average ReadCleanReq mshr miss latency 1623system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 121465.120682 # average ReadCleanReq mshr miss latency 1624system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 113994.501670 # average ReadSharedReq mshr miss latency 1625system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 118394.658754 # average ReadSharedReq mshr miss latency 1626system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 113999.955862 # average ReadSharedReq mshr miss latency 1627system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121368.002239 # average overall mshr miss latency 1628system.l2c.demand_avg_mshr_miss_latency::cpu0.data 114930.755419 # average overall mshr miss latency 1629system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122773.707974 # average overall mshr miss latency 1630system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121492.147553 # average overall mshr miss latency 1631system.l2c.demand_avg_mshr_miss_latency::total 115277.837125 # average overall mshr miss latency 1632system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121368.002239 # average overall mshr miss latency 1633system.l2c.overall_avg_mshr_miss_latency::cpu0.data 114930.755419 # average overall mshr miss latency 1634system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122773.707974 # average overall mshr miss latency 1635system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121492.147553 # average overall mshr miss latency 1636system.l2c.overall_avg_mshr_miss_latency::total 115277.837125 # average overall mshr miss latency 1637system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208711.191081 # average ReadReq mshr uncacheable latency 1638system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 199792.372881 # average ReadReq mshr uncacheable latency 1639system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 208565.102721 # average ReadReq mshr uncacheable latency 1640system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 215871.939911 # average WriteReq mshr uncacheable latency 1641system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 224303.166069 # average WriteReq mshr uncacheable latency 1642system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 217869.374469 # average WriteReq mshr uncacheable latency 1643system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 213032.484611 # average overall mshr uncacheable latency 1644system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 223468.695903 # average overall mshr uncacheable latency 1645system.l2c.overall_avg_mshr_uncacheable_latency::total 214727.830896 # average overall mshr uncacheable latency 1646system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 1647system.membus.trans_dist::ReadReq 7204 # Transaction distribution 1648system.membus.trans_dist::ReadResp 292685 # Transaction distribution 1649system.membus.trans_dist::WriteReq 14132 # Transaction distribution 1650system.membus.trans_dist::WriteResp 14132 # Transaction distribution 1651system.membus.trans_dist::WritebackDirty 120936 # Transaction distribution 1652system.membus.trans_dist::CleanEvict 262098 # Transaction distribution 1653system.membus.trans_dist::UpgradeReq 16894 # Transaction distribution 1654system.membus.trans_dist::SCUpgradeReq 11785 # Transaction distribution 1655system.membus.trans_dist::UpgradeResp 3 # Transaction distribution 1656system.membus.trans_dist::ReadExReq 123162 # Transaction distribution 1657system.membus.trans_dist::ReadExResp 122291 # Transaction distribution 1658system.membus.trans_dist::ReadSharedReq 285481 # Transaction distribution 1659system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution 1660system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42672 # Packet count per connected master and slave (bytes) 1661system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1185820 # Packet count per connected master and slave (bytes) 1662system.membus.pkt_count_system.l2c.mem_side::total 1228492 # Packet count per connected master and slave (bytes) 1663system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83437 # Packet count per connected master and slave (bytes) 1664system.membus.pkt_count_system.iocache.mem_side::total 83437 # Packet count per connected master and slave (bytes) 1665system.membus.pkt_count::total 1311929 # Packet count per connected master and slave (bytes) 1666system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 82507 # Cumulative packet size per connected master and slave (bytes) 1667system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31152000 # Cumulative packet size per connected master and slave (bytes) 1668system.membus.pkt_size_system.l2c.mem_side::total 31234507 # Cumulative packet size per connected master and slave (bytes) 1669system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) 1670system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) 1671system.membus.pkt_size::total 33892747 # Cumulative packet size per connected master and slave (bytes) 1672system.membus.snoops 22774 # Total snoops (count) 1673system.membus.snoop_fanout::samples 883255 # Request fanout histogram 1674system.membus.snoop_fanout::mean 1 # Request fanout histogram 1675system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1676system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1677system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1678system.membus.snoop_fanout::1 883255 100.00% 100.00% # Request fanout histogram 1679system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1680system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1681system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1682system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1683system.membus.snoop_fanout::total 883255 # Request fanout histogram 1684system.membus.reqLayer0.occupancy 40521000 # Layer occupancy (ticks) 1685system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1686system.membus.reqLayer1.occupancy 1327609723 # Layer occupancy (ticks) 1687system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 1688system.membus.respLayer1.occupancy 2178253250 # Layer occupancy (ticks) 1689system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 1690system.membus.respLayer2.occupancy 898617 # Layer occupancy (ticks) 1691system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1692system.toL2Bus.snoop_filter.tot_requests 4790864 # Total number of requests made to the snoop filter. 1693system.toL2Bus.snoop_filter.hit_single_requests 2395593 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1694system.toL2Bus.snoop_filter.hit_multi_requests 361656 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1695system.toL2Bus.snoop_filter.tot_snoops 1242 # Total number of snoops made to the snoop filter. 1696system.toL2Bus.snoop_filter.hit_single_snoops 1182 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1697system.toL2Bus.snoop_filter.hit_multi_snoops 60 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1698system.toL2Bus.trans_dist::ReadReq 7204 # Transaction distribution 1699system.toL2Bus.trans_dist::ReadResp 2107176 # Transaction distribution 1700system.toL2Bus.trans_dist::WriteReq 14132 # Transaction distribution 1701system.toL2Bus.trans_dist::WriteResp 14132 # Transaction distribution 1702system.toL2Bus.trans_dist::WritebackDirty 913504 # Transaction distribution 1703system.toL2Bus.trans_dist::WritebackClean 1018097 # Transaction distribution 1704system.toL2Bus.trans_dist::CleanEvict 816785 # Transaction distribution 1705system.toL2Bus.trans_dist::UpgradeReq 17065 # Transaction distribution 1706system.toL2Bus.trans_dist::SCUpgradeReq 11848 # Transaction distribution 1707system.toL2Bus.trans_dist::UpgradeResp 28913 # Transaction distribution 1708system.toL2Bus.trans_dist::ReadExReq 297603 # Transaction distribution 1709system.toL2Bus.trans_dist::ReadExResp 297603 # Transaction distribution 1710system.toL2Bus.trans_dist::ReadCleanReq 1019283 # Transaction distribution 1711system.toL2Bus.trans_dist::ReadSharedReq 1080704 # Transaction distribution 1712system.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution 1713system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2061018 # Packet count per connected master and slave (bytes) 1714system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3585479 # Packet count per connected master and slave (bytes) 1715system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 995618 # Packet count per connected master and slave (bytes) 1716system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 558881 # Packet count per connected master and slave (bytes) 1717system.toL2Bus.pkt_count::total 7200996 # Packet count per connected master and slave (bytes) 1718system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 87922688 # Cumulative packet size per connected master and slave (bytes) 1719system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 118013949 # Cumulative packet size per connected master and slave (bytes) 1720system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 42467904 # Cumulative packet size per connected master and slave (bytes) 1721system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 18601358 # Cumulative packet size per connected master and slave (bytes) 1722system.toL2Bus.pkt_size::total 267005899 # Cumulative packet size per connected master and slave (bytes) 1723system.toL2Bus.snoops 484765 # Total snoops (count) 1724system.toL2Bus.snoop_fanout::samples 2873241 # Request fanout histogram 1725system.toL2Bus.snoop_fanout::mean 0.136986 # Request fanout histogram 1726system.toL2Bus.snoop_fanout::stdev 0.344076 # Request fanout histogram 1727system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1728system.toL2Bus.snoop_fanout::0 2479885 86.31% 86.31% # Request fanout histogram 1729system.toL2Bus.snoop_fanout::1 393120 13.68% 99.99% # Request fanout histogram 1730system.toL2Bus.snoop_fanout::2 234 0.01% 100.00% # Request fanout histogram 1731system.toL2Bus.snoop_fanout::3 2 0.00% 100.00% # Request fanout histogram 1732system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram 1733system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1734system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1735system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram 1736system.toL2Bus.snoop_fanout::total 2873241 # Request fanout histogram 1737system.toL2Bus.reqLayer0.occupancy 4223821996 # Layer occupancy (ticks) 1738system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 1739system.toL2Bus.snoopLayer0.occupancy 297883 # Layer occupancy (ticks) 1740system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1741system.toL2Bus.respLayer0.occupancy 1031213250 # Layer occupancy (ticks) 1742system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1743system.toL2Bus.respLayer1.occupancy 1802267282 # Layer occupancy (ticks) 1744system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1745system.toL2Bus.respLayer2.occupancy 499176813 # Layer occupancy (ticks) 1746system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1747system.toL2Bus.respLayer3.occupancy 293823888 # Layer occupancy (ticks) 1748system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1749system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1750system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1751system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1752system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1753system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1754system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1755system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 1756system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1757system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 1758system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1759system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1760system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 1761system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1762system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1763system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 1764system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1765system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1766system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 1767system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1768system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1769system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 1770system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1771system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1772system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1773system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1774system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1775system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1776system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1777system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1778system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 1779system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 1780 1781---------- End Simulation Statistics ---------- 1782