stats.txt revision 8802:ef66a9083bc4
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.829332 # Number of seconds simulated 4sim_ticks 1829332258000 # Number of ticks simulated 5final_tick 1829332258000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 3300922 # Simulator instruction rate (inst/s) 8host_tick_rate 100577077281 # Simulator tick rate (ticks/s) 9host_mem_usage 294216 # Number of bytes of host memory used 10host_seconds 18.19 # Real time elapsed on the host 11sim_insts 60038305 # Number of instructions simulated 12system.physmem.bytes_read 71650816 # Number of bytes read from this memory 13system.physmem.bytes_inst_read 955904 # Number of instructions bytes read from this memory 14system.physmem.bytes_written 10156864 # Number of bytes written to this memory 15system.physmem.num_reads 1119544 # Number of read requests responded to by this memory 16system.physmem.num_writes 158701 # Number of write requests responded to by this memory 17system.physmem.num_other 0 # Number of other requests responded to by this memory 18system.physmem.bw_read 39167743 # Total read bandwidth from this memory (bytes/s) 19system.physmem.bw_inst_read 522543 # Instruction read bandwidth from this memory (bytes/s) 20system.physmem.bw_write 5552225 # Write bandwidth from this memory (bytes/s) 21system.physmem.bw_total 44719968 # Total bandwidth to/from this memory (bytes/s) 22system.l2c.replacements 1045877 # number of replacements 23system.l2c.tagsinuse 33807.015903 # Cycle average of tags in use 24system.l2c.total_refs 2291835 # Total number of references to valid blocks. 25system.l2c.sampled_refs 1077848 # Sample count of references to valid blocks. 26system.l2c.avg_refs 2.126306 # Average number of references to valid blocks. 27system.l2c.warmup_cycle 765422500 # Cycle when the warmup percentage was hit. 28system.l2c.occ_blocks::0 10193.605493 # Average occupied blocks per context 29system.l2c.occ_blocks::1 23613.410409 # Average occupied blocks per context 30system.l2c.occ_percent::0 0.155542 # Average percentage of cache occupancy 31system.l2c.occ_percent::1 0.360312 # Average percentage of cache occupancy 32system.l2c.ReadReq_hits::0 1699395 # number of ReadReq hits 33system.l2c.ReadReq_hits::total 1699395 # number of ReadReq hits 34system.l2c.Writeback_hits::0 825291 # number of Writeback hits 35system.l2c.Writeback_hits::total 825291 # number of Writeback hits 36system.l2c.UpgradeReq_hits::0 1 # number of UpgradeReq hits 37system.l2c.UpgradeReq_hits::total 1 # number of UpgradeReq hits 38system.l2c.ReadExReq_hits::0 185383 # number of ReadExReq hits 39system.l2c.ReadExReq_hits::total 185383 # number of ReadExReq hits 40system.l2c.demand_hits::0 1884778 # number of demand (read+write) hits 41system.l2c.demand_hits::1 0 # number of demand (read+write) hits 42system.l2c.demand_hits::total 1884778 # number of demand (read+write) hits 43system.l2c.overall_hits::0 1884778 # number of overall hits 44system.l2c.overall_hits::1 0 # number of overall hits 45system.l2c.overall_hits::total 1884778 # number of overall hits 46system.l2c.ReadReq_misses::0 959629 # number of ReadReq misses 47system.l2c.ReadReq_misses::total 959629 # number of ReadReq misses 48system.l2c.UpgradeReq_misses::0 12 # number of UpgradeReq misses 49system.l2c.UpgradeReq_misses::total 12 # number of UpgradeReq misses 50system.l2c.ReadExReq_misses::0 118859 # number of ReadExReq misses 51system.l2c.ReadExReq_misses::total 118859 # number of ReadExReq misses 52system.l2c.demand_misses::0 1078488 # number of demand (read+write) misses 53system.l2c.demand_misses::1 0 # number of demand (read+write) misses 54system.l2c.demand_misses::total 1078488 # number of demand (read+write) misses 55system.l2c.overall_misses::0 1078488 # number of overall misses 56system.l2c.overall_misses::1 0 # number of overall misses 57system.l2c.overall_misses::total 1078488 # number of overall misses 58system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles 59system.l2c.overall_miss_latency 0 # number of overall miss cycles 60system.l2c.ReadReq_accesses::0 2659024 # number of ReadReq accesses(hits+misses) 61system.l2c.ReadReq_accesses::total 2659024 # number of ReadReq accesses(hits+misses) 62system.l2c.Writeback_accesses::0 825291 # number of Writeback accesses(hits+misses) 63system.l2c.Writeback_accesses::total 825291 # number of Writeback accesses(hits+misses) 64system.l2c.UpgradeReq_accesses::0 13 # number of UpgradeReq accesses(hits+misses) 65system.l2c.UpgradeReq_accesses::total 13 # number of UpgradeReq accesses(hits+misses) 66system.l2c.ReadExReq_accesses::0 304242 # number of ReadExReq accesses(hits+misses) 67system.l2c.ReadExReq_accesses::total 304242 # number of ReadExReq accesses(hits+misses) 68system.l2c.demand_accesses::0 2963266 # number of demand (read+write) accesses 69system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses 70system.l2c.demand_accesses::total 2963266 # number of demand (read+write) accesses 71system.l2c.overall_accesses::0 2963266 # number of overall (read+write) accesses 72system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses 73system.l2c.overall_accesses::total 2963266 # number of overall (read+write) accesses 74system.l2c.ReadReq_miss_rate::0 0.360895 # miss rate for ReadReq accesses 75system.l2c.UpgradeReq_miss_rate::0 0.923077 # miss rate for UpgradeReq accesses 76system.l2c.ReadExReq_miss_rate::0 0.390673 # miss rate for ReadExReq accesses 77system.l2c.demand_miss_rate::0 0.363952 # miss rate for demand accesses 78system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses 79system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses 80system.l2c.overall_miss_rate::0 0.363952 # miss rate for overall accesses 81system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses 82system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses 83system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency 84system.l2c.demand_avg_miss_latency::1 no_value # average overall miss latency 85system.l2c.demand_avg_miss_latency::total no_value # average overall miss latency 86system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency 87system.l2c.overall_avg_miss_latency::1 no_value # average overall miss latency 88system.l2c.overall_avg_miss_latency::total no_value # average overall miss latency 89system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 90system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 91system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 92system.l2c.blocked::no_targets 0 # number of cycles access was blocked 93system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 94system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 95system.l2c.fast_writes 0 # number of fast writes performed 96system.l2c.cache_copies 0 # number of cache copies performed 97system.l2c.writebacks 117189 # number of writebacks 98system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 99system.l2c.overall_mshr_hits 0 # number of overall MSHR hits 100system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 101system.l2c.overall_mshr_misses 0 # number of overall MSHR misses 102system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 103system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 104system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 105system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 106system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses 107system.l2c.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses 108system.l2c.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses 109system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses 110system.l2c.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses 111system.l2c.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses 112system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 113system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 114system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 115system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated 116system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 117system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 118system.iocache.replacements 41686 # number of replacements 119system.iocache.tagsinuse 1.225570 # Cycle average of tags in use 120system.iocache.total_refs 0 # Total number of references to valid blocks. 121system.iocache.sampled_refs 41702 # Sample count of references to valid blocks. 122system.iocache.avg_refs 0 # Average number of references to valid blocks. 123system.iocache.warmup_cycle 1685780659017 # Cycle when the warmup percentage was hit. 124system.iocache.occ_blocks::1 1.225570 # Average occupied blocks per context 125system.iocache.occ_percent::1 0.076598 # Average percentage of cache occupancy 126system.iocache.demand_hits::0 0 # number of demand (read+write) hits 127system.iocache.demand_hits::1 0 # number of demand (read+write) hits 128system.iocache.demand_hits::total 0 # number of demand (read+write) hits 129system.iocache.overall_hits::0 0 # number of overall hits 130system.iocache.overall_hits::1 0 # number of overall hits 131system.iocache.overall_hits::total 0 # number of overall hits 132system.iocache.ReadReq_misses::1 174 # number of ReadReq misses 133system.iocache.ReadReq_misses::total 174 # number of ReadReq misses 134system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses 135system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 136system.iocache.demand_misses::0 0 # number of demand (read+write) misses 137system.iocache.demand_misses::1 41726 # number of demand (read+write) misses 138system.iocache.demand_misses::total 41726 # number of demand (read+write) misses 139system.iocache.overall_misses::0 0 # number of overall misses 140system.iocache.overall_misses::1 41726 # number of overall misses 141system.iocache.overall_misses::total 41726 # number of overall misses 142system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles 143system.iocache.overall_miss_latency 0 # number of overall miss cycles 144system.iocache.ReadReq_accesses::1 174 # number of ReadReq accesses(hits+misses) 145system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) 146system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) 147system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 148system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses 149system.iocache.demand_accesses::1 41726 # number of demand (read+write) accesses 150system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses 151system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses 152system.iocache.overall_accesses::1 41726 # number of overall (read+write) accesses 153system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses 154system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses 155system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses 156system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses 157system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses 158system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses 159system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses 160system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses 161system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses 162system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency 163system.iocache.demand_avg_miss_latency::1 0 # average overall miss latency 164system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency 165system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency 166system.iocache.overall_avg_miss_latency::1 0 # average overall miss latency 167system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency 168system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 169system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 170system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 171system.iocache.blocked::no_targets 0 # number of cycles access was blocked 172system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 173system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 174system.iocache.fast_writes 0 # number of fast writes performed 175system.iocache.cache_copies 0 # number of cache copies performed 176system.iocache.writebacks 41512 # number of writebacks 177system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 178system.iocache.overall_mshr_hits 0 # number of overall MSHR hits 179system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 180system.iocache.overall_mshr_misses 0 # number of overall MSHR misses 181system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 182system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 183system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 184system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 185system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses 186system.iocache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses 187system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses 188system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses 189system.iocache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses 190system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses 191system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 192system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 193system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 194system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated 195system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 196system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 197system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 198system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 199system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 200system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 201system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 202system.disk0.dma_write_txs 395 # Number of DMA write transactions. 203system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 204system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 205system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 206system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 207system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 208system.disk2.dma_write_txs 1 # Number of DMA write transactions. 209system.cpu.dtb.fetch_hits 0 # ITB hits 210system.cpu.dtb.fetch_misses 0 # ITB misses 211system.cpu.dtb.fetch_acv 0 # ITB acv 212system.cpu.dtb.fetch_accesses 0 # ITB accesses 213system.cpu.dtb.read_hits 9710427 # DTB read hits 214system.cpu.dtb.read_misses 10329 # DTB read misses 215system.cpu.dtb.read_acv 210 # DTB read access violations 216system.cpu.dtb.read_accesses 728856 # DTB read accesses 217system.cpu.dtb.write_hits 6352498 # DTB write hits 218system.cpu.dtb.write_misses 1142 # DTB write misses 219system.cpu.dtb.write_acv 157 # DTB write access violations 220system.cpu.dtb.write_accesses 291931 # DTB write accesses 221system.cpu.dtb.data_hits 16062925 # DTB hits 222system.cpu.dtb.data_misses 11471 # DTB misses 223system.cpu.dtb.data_acv 367 # DTB access violations 224system.cpu.dtb.data_accesses 1020787 # DTB accesses 225system.cpu.itb.fetch_hits 4974648 # ITB hits 226system.cpu.itb.fetch_misses 5006 # ITB misses 227system.cpu.itb.fetch_acv 184 # ITB acv 228system.cpu.itb.fetch_accesses 4979654 # ITB accesses 229system.cpu.itb.read_hits 0 # DTB read hits 230system.cpu.itb.read_misses 0 # DTB read misses 231system.cpu.itb.read_acv 0 # DTB read access violations 232system.cpu.itb.read_accesses 0 # DTB read accesses 233system.cpu.itb.write_hits 0 # DTB write hits 234system.cpu.itb.write_misses 0 # DTB write misses 235system.cpu.itb.write_acv 0 # DTB write access violations 236system.cpu.itb.write_accesses 0 # DTB write accesses 237system.cpu.itb.data_hits 0 # DTB hits 238system.cpu.itb.data_misses 0 # DTB misses 239system.cpu.itb.data_acv 0 # DTB access violations 240system.cpu.itb.data_accesses 0 # DTB accesses 241system.cpu.numCycles 3658664408 # number of cpu cycles simulated 242system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 243system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 244system.cpu.num_insts 60038305 # Number of instructions executed 245system.cpu.num_int_alu_accesses 55913521 # Number of integer alu accesses 246system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses 247system.cpu.num_func_calls 1484182 # number of times a function call or return occured 248system.cpu.num_conditional_control_insts 7110746 # number of instructions that are conditional controls 249system.cpu.num_int_insts 55913521 # number of integer instructions 250system.cpu.num_fp_insts 324460 # number of float instructions 251system.cpu.num_int_register_reads 76953934 # number of times the integer registers were read 252system.cpu.num_int_register_writes 41740225 # number of times the integer registers were written 253system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read 254system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written 255system.cpu.num_mem_refs 16115709 # number of memory refs 256system.cpu.num_load_insts 9747513 # Number of load instructions 257system.cpu.num_store_insts 6368196 # Number of store instructions 258system.cpu.num_idle_cycles 3598608979.180807 # Number of idle cycles 259system.cpu.num_busy_cycles 60055428.819193 # Number of busy cycles 260system.cpu.not_idle_fraction 0.016415 # Percentage of non-idle cycles 261system.cpu.idle_fraction 0.983585 # Percentage of idle cycles 262system.cpu.kern.inst.arm 0 # number of arm instructions executed 263system.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed 264system.cpu.kern.inst.hwrei 211319 # number of hwrei instructions executed 265system.cpu.kern.ipl_count::0 74830 40.99% 40.99% # number of times we switched to this ipl 266system.cpu.kern.ipl_count::21 243 0.13% 41.12% # number of times we switched to this ipl 267system.cpu.kern.ipl_count::22 1866 1.02% 42.14% # number of times we switched to this ipl 268system.cpu.kern.ipl_count::31 105623 57.86% 100.00% # number of times we switched to this ipl 269system.cpu.kern.ipl_count::total 182562 # number of times we switched to this ipl 270system.cpu.kern.ipl_good::0 73463 49.29% 49.29% # number of times we switched to this ipl from a different ipl 271system.cpu.kern.ipl_good::21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl 272system.cpu.kern.ipl_good::22 1866 1.25% 50.71% # number of times we switched to this ipl from a different ipl 273system.cpu.kern.ipl_good::31 73463 49.29% 100.00% # number of times we switched to this ipl from a different ipl 274system.cpu.kern.ipl_good::total 149035 # number of times we switched to this ipl from a different ipl 275system.cpu.kern.ipl_ticks::0 1811927407500 99.05% 99.05% # number of cycles we spent at this ipl 276system.cpu.kern.ipl_ticks::21 20110000 0.00% 99.05% # number of cycles we spent at this ipl 277system.cpu.kern.ipl_ticks::22 80238000 0.00% 99.05% # number of cycles we spent at this ipl 278system.cpu.kern.ipl_ticks::31 17304295000 0.95% 100.00% # number of cycles we spent at this ipl 279system.cpu.kern.ipl_ticks::total 1829332050500 # number of cycles we spent at this ipl 280system.cpu.kern.ipl_used::0 0.981732 # fraction of swpipl calls that actually changed the ipl 281system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 282system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 283system.cpu.kern.ipl_used::31 0.695521 # fraction of swpipl calls that actually changed the ipl 284system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 285system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 286system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 287system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 288system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 289system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 290system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 291system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed 292system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed 293system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed 294system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed 295system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed 296system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed 297system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed 298system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed 299system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed 300system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed 301system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed 302system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed 303system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed 304system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed 305system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed 306system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed 307system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed 308system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed 309system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed 310system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed 311system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 312system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 313system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 314system.cpu.kern.syscall::total 326 # number of syscalls executed 315system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 316system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 317system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 318system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 319system.cpu.kern.callpal::swpctx 4177 2.17% 2.18% # number of callpals executed 320system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed 321system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed 322system.cpu.kern.callpal::swpipl 175249 91.19% 93.40% # number of callpals executed 323system.cpu.kern.callpal::rdps 6771 3.52% 96.92% # number of callpals executed 324system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed 325system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed 326system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed 327system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed 328system.cpu.kern.callpal::rti 5203 2.71% 99.64% # number of callpals executed 329system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 330system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed 331system.cpu.kern.callpal::total 192180 # number of callpals executed 332system.cpu.kern.mode_switch::kernel 5949 # number of protection mode switches 333system.cpu.kern.mode_switch::user 1738 # number of protection mode switches 334system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches 335system.cpu.kern.mode_good::kernel 1909 336system.cpu.kern.mode_good::user 1738 337system.cpu.kern.mode_good::idle 171 338system.cpu.kern.mode_switch_good::kernel 0.320894 # fraction of useful protection mode switches 339system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 340system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches 341system.cpu.kern.mode_switch_good::total 1.402439 # fraction of useful protection mode switches 342system.cpu.kern.mode_ticks::kernel 26834202500 1.47% 1.47% # number of ticks spent at the given mode 343system.cpu.kern.mode_ticks::user 1465074000 0.08% 1.55% # number of ticks spent at the given mode 344system.cpu.kern.mode_ticks::idle 1801032773000 98.45% 100.00% # number of ticks spent at the given mode 345system.cpu.kern.swap_context 4178 # number of times the context was actually changed 346system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 347system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 348system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 349system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 350system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 351system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post 352system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 353system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 354system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post 355system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 356system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 357system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post 358system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 359system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 360system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post 361system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 362system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 363system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post 364system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 365system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 366system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post 367system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 368system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 369system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post 370system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 371system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 372system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post 373system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 374system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post 375system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 376system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 377system.cpu.icache.replacements 919594 # number of replacements 378system.cpu.icache.tagsinuse 511.215243 # Cycle average of tags in use 379system.cpu.icache.total_refs 59129922 # Total number of references to valid blocks. 380system.cpu.icache.sampled_refs 920106 # Sample count of references to valid blocks. 381system.cpu.icache.avg_refs 64.264250 # Average number of references to valid blocks. 382system.cpu.icache.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit. 383system.cpu.icache.occ_blocks::0 511.215243 # Average occupied blocks per context 384system.cpu.icache.occ_percent::0 0.998467 # Average percentage of cache occupancy 385system.cpu.icache.ReadReq_hits::0 59129922 # number of ReadReq hits 386system.cpu.icache.ReadReq_hits::total 59129922 # number of ReadReq hits 387system.cpu.icache.demand_hits::0 59129922 # number of demand (read+write) hits 388system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits 389system.cpu.icache.demand_hits::total 59129922 # number of demand (read+write) hits 390system.cpu.icache.overall_hits::0 59129922 # number of overall hits 391system.cpu.icache.overall_hits::1 0 # number of overall hits 392system.cpu.icache.overall_hits::total 59129922 # number of overall hits 393system.cpu.icache.ReadReq_misses::0 920221 # number of ReadReq misses 394system.cpu.icache.ReadReq_misses::total 920221 # number of ReadReq misses 395system.cpu.icache.demand_misses::0 920221 # number of demand (read+write) misses 396system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses 397system.cpu.icache.demand_misses::total 920221 # number of demand (read+write) misses 398system.cpu.icache.overall_misses::0 920221 # number of overall misses 399system.cpu.icache.overall_misses::1 0 # number of overall misses 400system.cpu.icache.overall_misses::total 920221 # number of overall misses 401system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles 402system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles 403system.cpu.icache.ReadReq_accesses::0 60050143 # number of ReadReq accesses(hits+misses) 404system.cpu.icache.ReadReq_accesses::total 60050143 # number of ReadReq accesses(hits+misses) 405system.cpu.icache.demand_accesses::0 60050143 # number of demand (read+write) accesses 406system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses 407system.cpu.icache.demand_accesses::total 60050143 # number of demand (read+write) accesses 408system.cpu.icache.overall_accesses::0 60050143 # number of overall (read+write) accesses 409system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses 410system.cpu.icache.overall_accesses::total 60050143 # number of overall (read+write) accesses 411system.cpu.icache.ReadReq_miss_rate::0 0.015324 # miss rate for ReadReq accesses 412system.cpu.icache.demand_miss_rate::0 0.015324 # miss rate for demand accesses 413system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses 414system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses 415system.cpu.icache.overall_miss_rate::0 0.015324 # miss rate for overall accesses 416system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses 417system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses 418system.cpu.icache.demand_avg_miss_latency::0 0 # average overall miss latency 419system.cpu.icache.demand_avg_miss_latency::1 no_value # average overall miss latency 420system.cpu.icache.demand_avg_miss_latency::total no_value # average overall miss latency 421system.cpu.icache.overall_avg_miss_latency::0 0 # average overall miss latency 422system.cpu.icache.overall_avg_miss_latency::1 no_value # average overall miss latency 423system.cpu.icache.overall_avg_miss_latency::total no_value # average overall miss latency 424system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 425system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 426system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 427system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 428system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 429system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 430system.cpu.icache.fast_writes 0 # number of fast writes performed 431system.cpu.icache.cache_copies 0 # number of cache copies performed 432system.cpu.icache.writebacks 108 # number of writebacks 433system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 434system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits 435system.cpu.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 436system.cpu.icache.overall_mshr_misses 0 # number of overall MSHR misses 437system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 438system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 439system.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 440system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 441system.cpu.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses 442system.cpu.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses 443system.cpu.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses 444system.cpu.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses 445system.cpu.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses 446system.cpu.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses 447system.cpu.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 448system.cpu.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 449system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 450system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated 451system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 452system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 453system.cpu.dcache.replacements 2042700 # number of replacements 454system.cpu.dcache.tagsinuse 511.997802 # Cycle average of tags in use 455system.cpu.dcache.total_refs 14038433 # Total number of references to valid blocks. 456system.cpu.dcache.sampled_refs 2043212 # Sample count of references to valid blocks. 457system.cpu.dcache.avg_refs 6.870767 # Average number of references to valid blocks. 458system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. 459system.cpu.dcache.occ_blocks::0 511.997802 # Average occupied blocks per context 460system.cpu.dcache.occ_percent::0 0.999996 # Average percentage of cache occupancy 461system.cpu.dcache.ReadReq_hits::0 7807782 # number of ReadReq hits 462system.cpu.dcache.ReadReq_hits::total 7807782 # number of ReadReq hits 463system.cpu.dcache.WriteReq_hits::0 5848212 # number of WriteReq hits 464system.cpu.dcache.WriteReq_hits::total 5848212 # number of WriteReq hits 465system.cpu.dcache.LoadLockedReq_hits::0 183141 # number of LoadLockedReq hits 466system.cpu.dcache.LoadLockedReq_hits::total 183141 # number of LoadLockedReq hits 467system.cpu.dcache.StoreCondReq_hits::0 199282 # number of StoreCondReq hits 468system.cpu.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits 469system.cpu.dcache.demand_hits::0 13655994 # number of demand (read+write) hits 470system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits 471system.cpu.dcache.demand_hits::total 13655994 # number of demand (read+write) hits 472system.cpu.dcache.overall_hits::0 13655994 # number of overall hits 473system.cpu.dcache.overall_hits::1 0 # number of overall hits 474system.cpu.dcache.overall_hits::total 13655994 # number of overall hits 475system.cpu.dcache.ReadReq_misses::0 1721705 # number of ReadReq misses 476system.cpu.dcache.ReadReq_misses::total 1721705 # number of ReadReq misses 477system.cpu.dcache.WriteReq_misses::0 304362 # number of WriteReq misses 478system.cpu.dcache.WriteReq_misses::total 304362 # number of WriteReq misses 479system.cpu.dcache.LoadLockedReq_misses::0 17162 # number of LoadLockedReq misses 480system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses 481system.cpu.dcache.demand_misses::0 2026067 # number of demand (read+write) misses 482system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses 483system.cpu.dcache.demand_misses::total 2026067 # number of demand (read+write) misses 484system.cpu.dcache.overall_misses::0 2026067 # number of overall misses 485system.cpu.dcache.overall_misses::1 0 # number of overall misses 486system.cpu.dcache.overall_misses::total 2026067 # number of overall misses 487system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles 488system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles 489system.cpu.dcache.ReadReq_accesses::0 9529487 # number of ReadReq accesses(hits+misses) 490system.cpu.dcache.ReadReq_accesses::total 9529487 # number of ReadReq accesses(hits+misses) 491system.cpu.dcache.WriteReq_accesses::0 6152574 # number of WriteReq accesses(hits+misses) 492system.cpu.dcache.WriteReq_accesses::total 6152574 # number of WriteReq accesses(hits+misses) 493system.cpu.dcache.LoadLockedReq_accesses::0 200303 # number of LoadLockedReq accesses(hits+misses) 494system.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses) 495system.cpu.dcache.StoreCondReq_accesses::0 199282 # number of StoreCondReq accesses(hits+misses) 496system.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses) 497system.cpu.dcache.demand_accesses::0 15682061 # number of demand (read+write) accesses 498system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses 499system.cpu.dcache.demand_accesses::total 15682061 # number of demand (read+write) accesses 500system.cpu.dcache.overall_accesses::0 15682061 # number of overall (read+write) accesses 501system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses 502system.cpu.dcache.overall_accesses::total 15682061 # number of overall (read+write) accesses 503system.cpu.dcache.ReadReq_miss_rate::0 0.180671 # miss rate for ReadReq accesses 504system.cpu.dcache.WriteReq_miss_rate::0 0.049469 # miss rate for WriteReq accesses 505system.cpu.dcache.LoadLockedReq_miss_rate::0 0.085680 # miss rate for LoadLockedReq accesses 506system.cpu.dcache.demand_miss_rate::0 0.129196 # miss rate for demand accesses 507system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses 508system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses 509system.cpu.dcache.overall_miss_rate::0 0.129196 # miss rate for overall accesses 510system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses 511system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses 512system.cpu.dcache.demand_avg_miss_latency::0 0 # average overall miss latency 513system.cpu.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency 514system.cpu.dcache.demand_avg_miss_latency::total no_value # average overall miss latency 515system.cpu.dcache.overall_avg_miss_latency::0 0 # average overall miss latency 516system.cpu.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency 517system.cpu.dcache.overall_avg_miss_latency::total no_value # average overall miss latency 518system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 519system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 520system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 521system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 522system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 523system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 524system.cpu.dcache.fast_writes 0 # number of fast writes performed 525system.cpu.dcache.cache_copies 0 # number of cache copies performed 526system.cpu.dcache.writebacks 825183 # number of writebacks 527system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 528system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits 529system.cpu.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 530system.cpu.dcache.overall_mshr_misses 0 # number of overall MSHR misses 531system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 532system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 533system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 534system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 535system.cpu.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses 536system.cpu.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses 537system.cpu.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses 538system.cpu.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses 539system.cpu.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses 540system.cpu.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses 541system.cpu.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 542system.cpu.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 543system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 544system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 545system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 546system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 547 548---------- End Simulation Statistics ---------- 549