stats.txt revision 9312
12968SN/A
22968SN/A---------- Begin Simulation Statistics ----------
39289Sandreas.hansson@arm.comsim_seconds                                  1.829331                       # Number of seconds simulated
49289Sandreas.hansson@arm.comsim_ticks                                1829330593000                       # Number of ticks simulated
59289Sandreas.hansson@arm.comfinal_tick                               1829330593000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
68721SN/Asim_freq                                 1000000000000                       # Frequency of simulated ticks
79312Sandreas.hansson@arm.comhost_inst_rate                                1577718                       # Simulator instruction rate (inst/s)
89312Sandreas.hansson@arm.comhost_op_rate                                  1577717                       # Simulator op (including micro ops) rate (op/s)
99312Sandreas.hansson@arm.comhost_tick_rate                            48072530632                       # Simulator tick rate (ticks/s)
109312Sandreas.hansson@arm.comhost_mem_usage                                 294780                       # Number of bytes of host memory used
119312Sandreas.hansson@arm.comhost_seconds                                    38.05                       # Real time elapsed on the host
129289Sandreas.hansson@arm.comsim_insts                                    60037737                       # Number of instructions simulated
139289Sandreas.hansson@arm.comsim_ops                                      60037737                       # Number of ops (including micro ops) simulated
149289Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst            857856                       # Number of bytes read from this memory
159289Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data          66839296                       # Number of bytes read from this memory
169079SAli.Saidi@ARM.comsystem.physmem.bytes_read::tsunami.ide        2652288                       # Number of bytes read from this memory
179289Sandreas.hansson@arm.comsystem.physmem.bytes_read::total             70349440                       # Number of bytes read from this memory
189289Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst       857856                       # Number of instructions bytes read from this memory
199289Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total          857856                       # Number of instructions bytes read from this memory
209289Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks      7411136                       # Number of bytes written to this memory
219289Sandreas.hansson@arm.comsystem.physmem.bytes_written::total           7411136                       # Number of bytes written to this memory
229289Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst              13404                       # Number of read requests responded to by this memory
239289Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data            1044364                       # Number of read requests responded to by this memory
249079SAli.Saidi@ARM.comsystem.physmem.num_reads::tsunami.ide           41442                       # Number of read requests responded to by this memory
259289Sandreas.hansson@arm.comsystem.physmem.num_reads::total               1099210                       # Number of read requests responded to by this memory
269289Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks          115799                       # Number of write requests responded to by this memory
279289Sandreas.hansson@arm.comsystem.physmem.num_writes::total               115799                       # Number of write requests responded to by this memory
289289Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst               468945                       # Total read bandwidth from this memory (bytes/s)
299289Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data             36537571                       # Total read bandwidth from this memory (bytes/s)
309289Sandreas.hansson@arm.comsystem.physmem.bw_read::tsunami.ide           1449868                       # Total read bandwidth from this memory (bytes/s)
319289Sandreas.hansson@arm.comsystem.physmem.bw_read::total                38456384                       # Total read bandwidth from this memory (bytes/s)
329289Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst          468945                       # Instruction read bandwidth from this memory (bytes/s)
339289Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total             468945                       # Instruction read bandwidth from this memory (bytes/s)
349289Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks           4051283                       # Write bandwidth from this memory (bytes/s)
359289Sandreas.hansson@arm.comsystem.physmem.bw_write::total                4051283                       # Write bandwidth from this memory (bytes/s)
369289Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks           4051283                       # Total bandwidth to/from this memory (bytes/s)
379289Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst              468945                       # Total bandwidth to/from this memory (bytes/s)
389289Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data            36537571                       # Total bandwidth to/from this memory (bytes/s)
399289Sandreas.hansson@arm.comsystem.physmem.bw_total::tsunami.ide          1449868                       # Total bandwidth to/from this memory (bytes/s)
409289Sandreas.hansson@arm.comsystem.physmem.bw_total::total               42507667                       # Total bandwidth to/from this memory (bytes/s)
419312Sandreas.hansson@arm.comsystem.physmem.readReqs                             0                       # Total number of read requests seen
429312Sandreas.hansson@arm.comsystem.physmem.writeReqs                            0                       # Total number of write requests seen
439312Sandreas.hansson@arm.comsystem.physmem.cpureqs                              0                       # Reqs generatd by CPU via cache - shady
449312Sandreas.hansson@arm.comsystem.physmem.bytesRead                            0                       # Total number of bytes read from memory
459312Sandreas.hansson@arm.comsystem.physmem.bytesWritten                         0                       # Total number of bytes written to memory
469312Sandreas.hansson@arm.comsystem.physmem.bytesConsumedRd                      0                       # bytesRead derated as per pkt->getSize()
479312Sandreas.hansson@arm.comsystem.physmem.bytesConsumedWr                      0                       # bytesWritten derated as per pkt->getSize()
489312Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ                        0                       # Number of read reqs serviced by write Q
499312Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWrite                  0                       # Reqs where no action is needed
509312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::0                     0                       # Track reads on a per bank basis
519312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::1                     0                       # Track reads on a per bank basis
529312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::2                     0                       # Track reads on a per bank basis
539312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::3                     0                       # Track reads on a per bank basis
549312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::4                     0                       # Track reads on a per bank basis
559312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::5                     0                       # Track reads on a per bank basis
569312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::6                     0                       # Track reads on a per bank basis
579312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::7                     0                       # Track reads on a per bank basis
589312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::8                     0                       # Track reads on a per bank basis
599312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::9                     0                       # Track reads on a per bank basis
609312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::10                    0                       # Track reads on a per bank basis
619312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::11                    0                       # Track reads on a per bank basis
629312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::12                    0                       # Track reads on a per bank basis
639312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::13                    0                       # Track reads on a per bank basis
649312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::14                    0                       # Track reads on a per bank basis
659312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::15                    0                       # Track reads on a per bank basis
669312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::0                     0                       # Track writes on a per bank basis
679312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::1                     0                       # Track writes on a per bank basis
689312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::2                     0                       # Track writes on a per bank basis
699312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::3                     0                       # Track writes on a per bank basis
709312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::4                     0                       # Track writes on a per bank basis
719312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::5                     0                       # Track writes on a per bank basis
729312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::6                     0                       # Track writes on a per bank basis
739312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::7                     0                       # Track writes on a per bank basis
749312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::8                     0                       # Track writes on a per bank basis
759312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::9                     0                       # Track writes on a per bank basis
769312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::10                    0                       # Track writes on a per bank basis
779312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::11                    0                       # Track writes on a per bank basis
789312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::12                    0                       # Track writes on a per bank basis
799312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::13                    0                       # Track writes on a per bank basis
809312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::14                    0                       # Track writes on a per bank basis
819312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::15                    0                       # Track writes on a per bank basis
829312Sandreas.hansson@arm.comsystem.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
839312Sandreas.hansson@arm.comsystem.physmem.numWrRetry                           0                       # Number of times wr buffer was full causing retry
849312Sandreas.hansson@arm.comsystem.physmem.totGap                               0                       # Total gap between requests
859312Sandreas.hansson@arm.comsystem.physmem.readPktSize::0                       0                       # Categorize read packet sizes
869312Sandreas.hansson@arm.comsystem.physmem.readPktSize::1                       0                       # Categorize read packet sizes
879312Sandreas.hansson@arm.comsystem.physmem.readPktSize::2                       0                       # Categorize read packet sizes
889312Sandreas.hansson@arm.comsystem.physmem.readPktSize::3                       0                       # Categorize read packet sizes
899312Sandreas.hansson@arm.comsystem.physmem.readPktSize::4                       0                       # Categorize read packet sizes
909312Sandreas.hansson@arm.comsystem.physmem.readPktSize::5                       0                       # Categorize read packet sizes
919312Sandreas.hansson@arm.comsystem.physmem.readPktSize::6                       0                       # Categorize read packet sizes
929312Sandreas.hansson@arm.comsystem.physmem.readPktSize::7                       0                       # Categorize read packet sizes
939312Sandreas.hansson@arm.comsystem.physmem.readPktSize::8                       0                       # Categorize read packet sizes
949312Sandreas.hansson@arm.comsystem.physmem.writePktSize::0                      0                       # categorize write packet sizes
959312Sandreas.hansson@arm.comsystem.physmem.writePktSize::1                      0                       # categorize write packet sizes
969312Sandreas.hansson@arm.comsystem.physmem.writePktSize::2                      0                       # categorize write packet sizes
979312Sandreas.hansson@arm.comsystem.physmem.writePktSize::3                      0                       # categorize write packet sizes
989312Sandreas.hansson@arm.comsystem.physmem.writePktSize::4                      0                       # categorize write packet sizes
999312Sandreas.hansson@arm.comsystem.physmem.writePktSize::5                      0                       # categorize write packet sizes
1009312Sandreas.hansson@arm.comsystem.physmem.writePktSize::6                      0                       # categorize write packet sizes
1019312Sandreas.hansson@arm.comsystem.physmem.writePktSize::7                      0                       # categorize write packet sizes
1029312Sandreas.hansson@arm.comsystem.physmem.writePktSize::8                      0                       # categorize write packet sizes
1039312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::0                    0                       # categorize neither packet sizes
1049312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::1                    0                       # categorize neither packet sizes
1059312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::2                    0                       # categorize neither packet sizes
1069312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::3                    0                       # categorize neither packet sizes
1079312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::4                    0                       # categorize neither packet sizes
1089312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::5                    0                       # categorize neither packet sizes
1099312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::6                    0                       # categorize neither packet sizes
1109312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::7                    0                       # categorize neither packet sizes
1119312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::8                    0                       # categorize neither packet sizes
1129312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0                         0                       # What read queue length does an incoming req see
1139312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1                         0                       # What read queue length does an incoming req see
1149312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2                         0                       # What read queue length does an incoming req see
1159312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
1169312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
1179312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
1189312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
1199312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
1209312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
1219312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
1229312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
1239312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
1249312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
1259312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
1269312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
1279312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
1289312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
1299312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
1309312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
1319312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
1329312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
1339312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
1349312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
1359312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
1369312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
1379312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
1389312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
1399312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
1409312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
1419312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
1429312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
1439312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
1449312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::32                        0                       # What read queue length does an incoming req see
1459312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
1469312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
1479312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
1489312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
1499312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
1509312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
1519312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
1529312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
1539312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
1549312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
1559312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
1569312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
1579312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
1589312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
1599312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
1609312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
1619312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
1629312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
1639312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
1649312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
1659312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
1669312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
1679312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
1689312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
1699312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
1709312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
1719312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
1729312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
1739312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
1749312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
1759312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
1769312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
1779312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
1789312Sandreas.hansson@arm.comsystem.physmem.totQLat                              0                       # Total cycles spent in queuing delays
1799312Sandreas.hansson@arm.comsystem.physmem.totMemAccLat                         0                       # Sum of mem lat for all requests
1809312Sandreas.hansson@arm.comsystem.physmem.totBusLat                            0                       # Total cycles spent in databus access
1819312Sandreas.hansson@arm.comsystem.physmem.totBankLat                           0                       # Total cycles spent in bank access
1829312Sandreas.hansson@arm.comsystem.physmem.avgQLat                            nan                       # Average queueing delay per request
1839312Sandreas.hansson@arm.comsystem.physmem.avgBankLat                         nan                       # Average bank access latency per request
1849312Sandreas.hansson@arm.comsystem.physmem.avgBusLat                          nan                       # Average bus latency per request
1859312Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat                       nan                       # Average memory access latency
1869312Sandreas.hansson@arm.comsystem.physmem.avgRdBW                           0.00                       # Average achieved read bandwidth in MB/s
1879312Sandreas.hansson@arm.comsystem.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MB/s
1889312Sandreas.hansson@arm.comsystem.physmem.avgConsumedRdBW                   0.00                       # Average consumed read bandwidth in MB/s
1899312Sandreas.hansson@arm.comsystem.physmem.avgConsumedWrBW                   0.00                       # Average consumed write bandwidth in MB/s
1909312Sandreas.hansson@arm.comsystem.physmem.peakBW                        16000.00                       # Theoretical peak bandwidth in MB/s
1919312Sandreas.hansson@arm.comsystem.physmem.busUtil                           0.00                       # Data bus utilization in percentage
1929312Sandreas.hansson@arm.comsystem.physmem.avgRdQLen                         0.00                       # Average read queue length over time
1939312Sandreas.hansson@arm.comsystem.physmem.avgWrQLen                         0.00                       # Average write queue length over time
1949312Sandreas.hansson@arm.comsystem.physmem.readRowHits                          0                       # Number of row buffer hits during reads
1959312Sandreas.hansson@arm.comsystem.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
1969312Sandreas.hansson@arm.comsystem.physmem.readRowHitRate                     nan                       # Row buffer hit rate for reads
1979312Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
1989312Sandreas.hansson@arm.comsystem.physmem.avgGap                             nan                       # Average gap between requests
1998721SN/Asystem.iocache.replacements                     41686                       # number of replacements
2009289Sandreas.hansson@arm.comsystem.iocache.tagsinuse                     1.225558                       # Cycle average of tags in use
2018721SN/Asystem.iocache.total_refs                           0                       # Total number of references to valid blocks.
2028721SN/Asystem.iocache.sampled_refs                     41702                       # Sample count of references to valid blocks.
2038721SN/Asystem.iocache.avg_refs                             0                       # Average number of references to valid blocks.
2049289Sandreas.hansson@arm.comsystem.iocache.warmup_cycle              1685780599067                       # Cycle when the warmup percentage was hit.
2059289Sandreas.hansson@arm.comsystem.iocache.occ_blocks::tsunami.ide       1.225558                       # Average occupied blocks per requestor
2069289Sandreas.hansson@arm.comsystem.iocache.occ_percent::tsunami.ide      0.076597                       # Average percentage of cache occupancy
2079289Sandreas.hansson@arm.comsystem.iocache.occ_percent::total            0.076597                       # Average percentage of cache occupancy
2088835SAli.Saidi@ARM.comsystem.iocache.ReadReq_misses::tsunami.ide          174                       # number of ReadReq misses
2098721SN/Asystem.iocache.ReadReq_misses::total              174                       # number of ReadReq misses
2108835SAli.Saidi@ARM.comsystem.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
2118721SN/Asystem.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
2128835SAli.Saidi@ARM.comsystem.iocache.demand_misses::tsunami.ide        41726                       # number of demand (read+write) misses
2138721SN/Asystem.iocache.demand_misses::total             41726                       # number of demand (read+write) misses
2148835SAli.Saidi@ARM.comsystem.iocache.overall_misses::tsunami.ide        41726                       # number of overall misses
2158721SN/Asystem.iocache.overall_misses::total            41726                       # number of overall misses
2168835SAli.Saidi@ARM.comsystem.iocache.ReadReq_accesses::tsunami.ide          174                       # number of ReadReq accesses(hits+misses)
2178721SN/Asystem.iocache.ReadReq_accesses::total            174                       # number of ReadReq accesses(hits+misses)
2188835SAli.Saidi@ARM.comsystem.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
2198721SN/Asystem.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
2208835SAli.Saidi@ARM.comsystem.iocache.demand_accesses::tsunami.ide        41726                       # number of demand (read+write) accesses
2218721SN/Asystem.iocache.demand_accesses::total           41726                       # number of demand (read+write) accesses
2228835SAli.Saidi@ARM.comsystem.iocache.overall_accesses::tsunami.ide        41726                       # number of overall (read+write) accesses
2238721SN/Asystem.iocache.overall_accesses::total          41726                       # number of overall (read+write) accesses
2248835SAli.Saidi@ARM.comsystem.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
2259055Ssaidi@eecs.umich.edusystem.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
2268835SAli.Saidi@ARM.comsystem.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
2279055Ssaidi@eecs.umich.edusystem.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
2288835SAli.Saidi@ARM.comsystem.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
2299055Ssaidi@eecs.umich.edusystem.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
2308835SAli.Saidi@ARM.comsystem.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
2319055Ssaidi@eecs.umich.edusystem.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
2328721SN/Asystem.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
2338721SN/Asystem.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
2348721SN/Asystem.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
2358721SN/Asystem.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
2368983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
2378983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
2388721SN/Asystem.iocache.fast_writes                          0                       # number of fast writes performed
2398721SN/Asystem.iocache.cache_copies                         0                       # number of cache copies performed
2408835SAli.Saidi@ARM.comsystem.iocache.writebacks::writebacks           41512                       # number of writebacks
2418835SAli.Saidi@ARM.comsystem.iocache.writebacks::total                41512                       # number of writebacks
2428721SN/Asystem.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
2438721SN/Asystem.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
2448721SN/Asystem.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
2458721SN/Asystem.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
2468721SN/Asystem.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
2478721SN/Asystem.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
2488721SN/Asystem.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
2498721SN/Asystem.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
2508721SN/Asystem.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
2518721SN/Asystem.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
2528721SN/Asystem.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
2538721SN/Asystem.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
2548721SN/Asystem.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
2558721SN/Asystem.cpu.dtb.fetch_hits                           0                       # ITB hits
2568721SN/Asystem.cpu.dtb.fetch_misses                         0                       # ITB misses
2578721SN/Asystem.cpu.dtb.fetch_acv                            0                       # ITB acv
2588721SN/Asystem.cpu.dtb.fetch_accesses                       0                       # ITB accesses
2599289Sandreas.hansson@arm.comsystem.cpu.dtb.read_hits                      9710417                       # DTB read hits
2608721SN/Asystem.cpu.dtb.read_misses                      10329                       # DTB read misses
2618721SN/Asystem.cpu.dtb.read_acv                           210                       # DTB read access violations
2628721SN/Asystem.cpu.dtb.read_accesses                   728856                       # DTB read accesses
2639289Sandreas.hansson@arm.comsystem.cpu.dtb.write_hits                     6352487                       # DTB write hits
2648721SN/Asystem.cpu.dtb.write_misses                      1142                       # DTB write misses
2658721SN/Asystem.cpu.dtb.write_acv                          157                       # DTB write access violations
2668721SN/Asystem.cpu.dtb.write_accesses                  291931                       # DTB write accesses
2679289Sandreas.hansson@arm.comsystem.cpu.dtb.data_hits                     16062904                       # DTB hits
2686024SN/Asystem.cpu.dtb.data_misses                      11471                       # DTB misses
2698721SN/Asystem.cpu.dtb.data_acv                           367                       # DTB access violations
2708721SN/Asystem.cpu.dtb.data_accesses                  1020787                       # DTB accesses
2719289Sandreas.hansson@arm.comsystem.cpu.itb.fetch_hits                     4974615                       # ITB hits
2728721SN/Asystem.cpu.itb.fetch_misses                      5006                       # ITB misses
2738721SN/Asystem.cpu.itb.fetch_acv                          184                       # ITB acv
2749289Sandreas.hansson@arm.comsystem.cpu.itb.fetch_accesses                 4979621                       # ITB accesses
2758721SN/Asystem.cpu.itb.read_hits                            0                       # DTB read hits
2768721SN/Asystem.cpu.itb.read_misses                          0                       # DTB read misses
2778721SN/Asystem.cpu.itb.read_acv                             0                       # DTB read access violations
2788721SN/Asystem.cpu.itb.read_accesses                        0                       # DTB read accesses
2798721SN/Asystem.cpu.itb.write_hits                           0                       # DTB write hits
2808721SN/Asystem.cpu.itb.write_misses                         0                       # DTB write misses
2818721SN/Asystem.cpu.itb.write_acv                            0                       # DTB write access violations
2828721SN/Asystem.cpu.itb.write_accesses                       0                       # DTB write accesses
2836024SN/Asystem.cpu.itb.data_hits                            0                       # DTB hits
2846024SN/Asystem.cpu.itb.data_misses                          0                       # DTB misses
2858721SN/Asystem.cpu.itb.data_acv                             0                       # DTB access violations
2868721SN/Asystem.cpu.itb.data_accesses                        0                       # DTB accesses
2879289Sandreas.hansson@arm.comsystem.cpu.numCycles                       3658661078                       # number of cpu cycles simulated
2888721SN/Asystem.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
2898721SN/Asystem.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
2909289Sandreas.hansson@arm.comsystem.cpu.committedInsts                    60037737                       # Number of instructions committed
2919289Sandreas.hansson@arm.comsystem.cpu.committedOps                      60037737                       # Number of ops (including micro ops) committed
2929289Sandreas.hansson@arm.comsystem.cpu.num_int_alu_accesses              55912968                       # Number of integer alu accesses
2938721SN/Asystem.cpu.num_fp_alu_accesses                 324460                       # Number of float alu accesses
2949289Sandreas.hansson@arm.comsystem.cpu.num_func_calls                     1484174                       # number of times a function call or return occured
2959289Sandreas.hansson@arm.comsystem.cpu.num_conditional_control_insts      7110641                       # number of instructions that are conditional controls
2969289Sandreas.hansson@arm.comsystem.cpu.num_int_insts                     55912968                       # number of integer instructions
2978721SN/Asystem.cpu.num_fp_insts                        324460                       # number of float instructions
2989289Sandreas.hansson@arm.comsystem.cpu.num_int_register_reads            76953007                       # number of times the integer registers were read
2999289Sandreas.hansson@arm.comsystem.cpu.num_int_register_writes           41739788                       # number of times the integer registers were written
3008721SN/Asystem.cpu.num_fp_register_reads               163642                       # number of times the floating registers were read
3018721SN/Asystem.cpu.num_fp_register_writes              166520                       # number of times the floating registers were written
3029289Sandreas.hansson@arm.comsystem.cpu.num_mem_refs                      16115688                       # number of memory refs
3039289Sandreas.hansson@arm.comsystem.cpu.num_load_insts                     9747503                       # Number of load instructions
3049289Sandreas.hansson@arm.comsystem.cpu.num_store_insts                    6368185                       # Number of store instructions
3059312Sandreas.hansson@arm.comsystem.cpu.num_idle_cycles               3598606250.520791                       # Number of idle cycles
3069312Sandreas.hansson@arm.comsystem.cpu.num_busy_cycles               60054827.479209                       # Number of busy cycles
3079289Sandreas.hansson@arm.comsystem.cpu.not_idle_fraction                 0.016414                       # Percentage of non-idle cycles
3089289Sandreas.hansson@arm.comsystem.cpu.idle_fraction                     0.983586                       # Percentage of idle cycles
3092968SN/Asystem.cpu.kern.inst.arm                            0                       # number of arm instructions executed
3108721SN/Asystem.cpu.kern.inst.quiesce                     6357                       # number of quiesce instructions executed
3119289Sandreas.hansson@arm.comsystem.cpu.kern.inst.hwrei                     211316                       # number of hwrei instructions executed
3126291SN/Asystem.cpu.kern.ipl_count::0                    74830     40.99%     40.99% # number of times we switched to this ipl
3136291SN/Asystem.cpu.kern.ipl_count::21                     243      0.13%     41.12% # number of times we switched to this ipl
3146291SN/Asystem.cpu.kern.ipl_count::22                    1866      1.02%     42.14% # number of times we switched to this ipl
3159289Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::31                  105620     57.86%    100.00% # number of times we switched to this ipl
3169289Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::total               182559                       # number of times we switched to this ipl
3176291SN/Asystem.cpu.kern.ipl_good::0                     73463     49.29%     49.29% # number of times we switched to this ipl from a different ipl
3186291SN/Asystem.cpu.kern.ipl_good::21                      243      0.16%     49.46% # number of times we switched to this ipl from a different ipl
3196291SN/Asystem.cpu.kern.ipl_good::22                     1866      1.25%     50.71% # number of times we switched to this ipl from a different ipl
3206291SN/Asystem.cpu.kern.ipl_good::31                    73463     49.29%    100.00% # number of times we switched to this ipl from a different ipl
3216127SN/Asystem.cpu.kern.ipl_good::total                149035                       # number of times we switched to this ipl from a different ipl
3229289Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::0             1811925911500     99.05%     99.05% # number of cycles we spent at this ipl
3236291SN/Asystem.cpu.kern.ipl_ticks::21                20110000      0.00%     99.05% # number of cycles we spent at this ipl
3246291SN/Asystem.cpu.kern.ipl_ticks::22                80238000      0.00%     99.05% # number of cycles we spent at this ipl
3259289Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::31             17304126000      0.95%    100.00% # number of cycles we spent at this ipl
3269289Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::total         1829330385500                       # number of cycles we spent at this ipl
3276127SN/Asystem.cpu.kern.ipl_used::0                  0.981732                       # fraction of swpipl calls that actually changed the ipl
3286127SN/Asystem.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
3296127SN/Asystem.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
3309289Sandreas.hansson@arm.comsystem.cpu.kern.ipl_used::31                 0.695541                       # fraction of swpipl calls that actually changed the ipl
3319289Sandreas.hansson@arm.comsystem.cpu.kern.ipl_used::total              0.816366                       # fraction of swpipl calls that actually changed the ipl
3326291SN/Asystem.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
3336291SN/Asystem.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
3346291SN/Asystem.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
3356291SN/Asystem.cpu.kern.syscall::6                         42     12.88%     25.77% # number of syscalls executed
3366291SN/Asystem.cpu.kern.syscall::12                         1      0.31%     26.07% # number of syscalls executed
3376291SN/Asystem.cpu.kern.syscall::15                         1      0.31%     26.38% # number of syscalls executed
3386291SN/Asystem.cpu.kern.syscall::17                        15      4.60%     30.98% # number of syscalls executed
3396291SN/Asystem.cpu.kern.syscall::19                        10      3.07%     34.05% # number of syscalls executed
3406291SN/Asystem.cpu.kern.syscall::20                         6      1.84%     35.89% # number of syscalls executed
3416291SN/Asystem.cpu.kern.syscall::23                         4      1.23%     37.12% # number of syscalls executed
3426291SN/Asystem.cpu.kern.syscall::24                         6      1.84%     38.96% # number of syscalls executed
3436291SN/Asystem.cpu.kern.syscall::33                        11      3.37%     42.33% # number of syscalls executed
3446291SN/Asystem.cpu.kern.syscall::41                         2      0.61%     42.94% # number of syscalls executed
3456291SN/Asystem.cpu.kern.syscall::45                        54     16.56%     59.51% # number of syscalls executed
3466291SN/Asystem.cpu.kern.syscall::47                         6      1.84%     61.35% # number of syscalls executed
3476291SN/Asystem.cpu.kern.syscall::48                        10      3.07%     64.42% # number of syscalls executed
3486291SN/Asystem.cpu.kern.syscall::54                        10      3.07%     67.48% # number of syscalls executed
3496291SN/Asystem.cpu.kern.syscall::58                         1      0.31%     67.79% # number of syscalls executed
3506291SN/Asystem.cpu.kern.syscall::59                         7      2.15%     69.94% # number of syscalls executed
3516291SN/Asystem.cpu.kern.syscall::71                        54     16.56%     86.50% # number of syscalls executed
3526291SN/Asystem.cpu.kern.syscall::73                         3      0.92%     87.42% # number of syscalls executed
3536291SN/Asystem.cpu.kern.syscall::74                        16      4.91%     92.33% # number of syscalls executed
3546291SN/Asystem.cpu.kern.syscall::87                         1      0.31%     92.64% # number of syscalls executed
3556291SN/Asystem.cpu.kern.syscall::90                         3      0.92%     93.56% # number of syscalls executed
3566291SN/Asystem.cpu.kern.syscall::92                         9      2.76%     96.32% # number of syscalls executed
3576291SN/Asystem.cpu.kern.syscall::97                         2      0.61%     96.93% # number of syscalls executed
3586291SN/Asystem.cpu.kern.syscall::98                         2      0.61%     97.55% # number of syscalls executed
3596291SN/Asystem.cpu.kern.syscall::132                        4      1.23%     98.77% # number of syscalls executed
3606291SN/Asystem.cpu.kern.syscall::144                        2      0.61%     99.39% # number of syscalls executed
3616291SN/Asystem.cpu.kern.syscall::147                        2      0.61%    100.00% # number of syscalls executed
3626127SN/Asystem.cpu.kern.syscall::total                    326                       # number of syscalls executed
3638721SN/Asystem.cpu.kern.callpal::cserve                     1      0.00%      0.00% # number of callpals executed
3648721SN/Asystem.cpu.kern.callpal::wrmces                     1      0.00%      0.00% # number of callpals executed
3658721SN/Asystem.cpu.kern.callpal::wrfen                      1      0.00%      0.00% # number of callpals executed
3668721SN/Asystem.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # number of callpals executed
3678721SN/Asystem.cpu.kern.callpal::swpctx                  4177      2.17%      2.18% # number of callpals executed
3688721SN/Asystem.cpu.kern.callpal::tbi                       54      0.03%      2.20% # number of callpals executed
3698721SN/Asystem.cpu.kern.callpal::wrent                      7      0.00%      2.21% # number of callpals executed
3709289Sandreas.hansson@arm.comsystem.cpu.kern.callpal::swpipl                175246     91.19%     93.40% # number of callpals executed
3718721SN/Asystem.cpu.kern.callpal::rdps                    6771      3.52%     96.92% # number of callpals executed
3728721SN/Asystem.cpu.kern.callpal::wrkgp                      1      0.00%     96.92% # number of callpals executed
3738721SN/Asystem.cpu.kern.callpal::wrusp                      7      0.00%     96.92% # number of callpals executed
3748721SN/Asystem.cpu.kern.callpal::rdusp                      9      0.00%     96.93% # number of callpals executed
3758721SN/Asystem.cpu.kern.callpal::whami                      2      0.00%     96.93% # number of callpals executed
3768721SN/Asystem.cpu.kern.callpal::rti                     5203      2.71%     99.64% # number of callpals executed
3778721SN/Asystem.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
3788721SN/Asystem.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
3799289Sandreas.hansson@arm.comsystem.cpu.kern.callpal::total                 192177                       # number of callpals executed
3809289Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch::kernel              5948                       # number of protection mode switches
3819289Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch::user                1735                       # number of protection mode switches
3829289Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch::idle                2098                       # number of protection mode switches
3839289Sandreas.hansson@arm.comsystem.cpu.kern.mode_good::kernel                1906                      
3849289Sandreas.hansson@arm.comsystem.cpu.kern.mode_good::user                  1735                      
3858721SN/Asystem.cpu.kern.mode_good::idle                   171                      
3869289Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch_good::kernel     0.320444                       # fraction of useful protection mode switches
3878721SN/Asystem.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
3889289Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch_good::idle       0.081506                       # fraction of useful protection mode switches
3899289Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch_good::total      0.389735                       # fraction of useful protection mode switches
3909289Sandreas.hansson@arm.comsystem.cpu.kern.mode_ticks::kernel        26832734500      1.47%      1.47% # number of ticks spent at the given mode
3919289Sandreas.hansson@arm.comsystem.cpu.kern.mode_ticks::user           1465059000      0.08%      1.55% # number of ticks spent at the given mode
3929289Sandreas.hansson@arm.comsystem.cpu.kern.mode_ticks::idle         1801032591000     98.45%    100.00% # number of ticks spent at the given mode
3938721SN/Asystem.cpu.kern.swap_context                     4178                       # number of times the context was actually changed
3942968SN/Asystem.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
3952968SN/Asystem.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
3962968SN/Asystem.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
3972968SN/Asystem.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
3988721SN/Asystem.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
3998983Snate@binkert.orgsystem.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
4008721SN/Asystem.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
4018721SN/Asystem.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
4028983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
4038721SN/Asystem.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
4048721SN/Asystem.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
4058983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
4068721SN/Asystem.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
4078721SN/Asystem.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
4088983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
4098721SN/Asystem.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
4108721SN/Asystem.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
4118983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
4128721SN/Asystem.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
4138721SN/Asystem.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
4148983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
4158721SN/Asystem.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
4168721SN/Asystem.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
4178983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
4188721SN/Asystem.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
4198721SN/Asystem.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
4208983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
4218721SN/Asystem.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
4228983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
4238721SN/Asystem.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
4242968SN/Asystem.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
4259289Sandreas.hansson@arm.comsystem.cpu.icache.replacements                 919577                       # number of replacements
4269289Sandreas.hansson@arm.comsystem.cpu.icache.tagsinuse                511.215229                       # Cycle average of tags in use
4279289Sandreas.hansson@arm.comsystem.cpu.icache.total_refs                 59129371                       # Total number of references to valid blocks.
4289289Sandreas.hansson@arm.comsystem.cpu.icache.sampled_refs                 920089                       # Sample count of references to valid blocks.
4299289Sandreas.hansson@arm.comsystem.cpu.icache.avg_refs                  64.264839                       # Average number of references to valid blocks.
4308721SN/Asystem.cpu.icache.warmup_cycle             9686972500                       # Cycle when the warmup percentage was hit.
4319289Sandreas.hansson@arm.comsystem.cpu.icache.occ_blocks::cpu.inst     511.215229                       # Average occupied blocks per requestor
4328835SAli.Saidi@ARM.comsystem.cpu.icache.occ_percent::cpu.inst      0.998467                       # Average percentage of cache occupancy
4338835SAli.Saidi@ARM.comsystem.cpu.icache.occ_percent::total         0.998467                       # Average percentage of cache occupancy
4349289Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst     59129371                       # number of ReadReq hits
4359289Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total        59129371                       # number of ReadReq hits
4369289Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst      59129371                       # number of demand (read+write) hits
4379289Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total         59129371                       # number of demand (read+write) hits
4389289Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst     59129371                       # number of overall hits
4399289Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total        59129371                       # number of overall hits
4409289Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst       920204                       # number of ReadReq misses
4419289Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total        920204                       # number of ReadReq misses
4429289Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst       920204                       # number of demand (read+write) misses
4439289Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total         920204                       # number of demand (read+write) misses
4449289Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst       920204                       # number of overall misses
4459289Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total        920204                       # number of overall misses
4469289Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst     60049575                       # number of ReadReq accesses(hits+misses)
4479289Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total     60049575                       # number of ReadReq accesses(hits+misses)
4489289Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst     60049575                       # number of demand (read+write) accesses
4499289Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total     60049575                       # number of demand (read+write) accesses
4509289Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst     60049575                       # number of overall (read+write) accesses
4519289Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total     60049575                       # number of overall (read+write) accesses
4528835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst     0.015324                       # miss rate for ReadReq accesses
4539055Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_miss_rate::total     0.015324                       # miss rate for ReadReq accesses
4548835SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_rate::cpu.inst     0.015324                       # miss rate for demand accesses
4559055Ssaidi@eecs.umich.edusystem.cpu.icache.demand_miss_rate::total     0.015324                       # miss rate for demand accesses
4568835SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_rate::cpu.inst     0.015324                       # miss rate for overall accesses
4579055Ssaidi@eecs.umich.edusystem.cpu.icache.overall_miss_rate::total     0.015324                       # miss rate for overall accesses
4588721SN/Asystem.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
4598721SN/Asystem.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
4608721SN/Asystem.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
4618721SN/Asystem.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
4628983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
4638983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
4648721SN/Asystem.cpu.icache.fast_writes                       0                       # number of fast writes performed
4658721SN/Asystem.cpu.icache.cache_copies                      0                       # number of cache copies performed
4668721SN/Asystem.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
4679312Sandreas.hansson@arm.comsystem.cpu.dcache.replacements                2042707                       # number of replacements
4688721SN/Asystem.cpu.dcache.tagsinuse                511.997802                       # Cycle average of tags in use
4699312Sandreas.hansson@arm.comsystem.cpu.dcache.total_refs                 14038405                       # Total number of references to valid blocks.
4709312Sandreas.hansson@arm.comsystem.cpu.dcache.sampled_refs                2043219                       # Sample count of references to valid blocks.
4719312Sandreas.hansson@arm.comsystem.cpu.dcache.avg_refs                   6.870729                       # Average number of references to valid blocks.
4728721SN/Asystem.cpu.dcache.warmup_cycle               10840000                       # Cycle when the warmup percentage was hit.
4738835SAli.Saidi@ARM.comsystem.cpu.dcache.occ_blocks::cpu.data     511.997802                       # Average occupied blocks per requestor
4748835SAli.Saidi@ARM.comsystem.cpu.dcache.occ_percent::cpu.data      0.999996                       # Average percentage of cache occupancy
4758835SAli.Saidi@ARM.comsystem.cpu.dcache.occ_percent::total         0.999996                       # Average percentage of cache occupancy
4769312Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data      7807769                       # number of ReadReq hits
4779312Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total         7807769                       # number of ReadReq hits
4789289Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data      5848199                       # number of WriteReq hits
4799289Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total        5848199                       # number of WriteReq hits
4809289Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data       183140                       # number of LoadLockedReq hits
4819289Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total       183140                       # number of LoadLockedReq hits
4829289Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data       199281                       # number of StoreCondReq hits
4839289Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::total       199281                       # number of StoreCondReq hits
4849312Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data      13655968                       # number of demand (read+write) hits
4859312Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total         13655968                       # number of demand (read+write) hits
4869312Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data     13655968                       # number of overall hits
4879312Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total        13655968                       # number of overall hits
4889312Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data      1721709                       # number of ReadReq misses
4899312Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total       1721709                       # number of ReadReq misses
4909289Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data       304365                       # number of WriteReq misses
4919289Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total       304365                       # number of WriteReq misses
4928835SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data        17162                       # number of LoadLockedReq misses
4938721SN/Asystem.cpu.dcache.LoadLockedReq_misses::total        17162                       # number of LoadLockedReq misses
4949312Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data      2026074                       # number of demand (read+write) misses
4959312Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total        2026074                       # number of demand (read+write) misses
4969312Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data      2026074                       # number of overall misses
4979312Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total       2026074                       # number of overall misses
4989289Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data      9529478                       # number of ReadReq accesses(hits+misses)
4999289Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total      9529478                       # number of ReadReq accesses(hits+misses)
5009289Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data      6152564                       # number of WriteReq accesses(hits+misses)
5019289Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::total      6152564                       # number of WriteReq accesses(hits+misses)
5029289Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data       200302                       # number of LoadLockedReq accesses(hits+misses)
5039289Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total       200302                       # number of LoadLockedReq accesses(hits+misses)
5049289Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data       199281                       # number of StoreCondReq accesses(hits+misses)
5059289Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total       199281                       # number of StoreCondReq accesses(hits+misses)
5069289Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data     15682042                       # number of demand (read+write) accesses
5079289Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total     15682042                       # number of demand (read+write) accesses
5089289Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data     15682042                       # number of overall (read+write) accesses
5099289Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total     15682042                       # number of overall (read+write) accesses
5109079SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data     0.180672                       # miss rate for ReadReq accesses
5119079SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_rate::total     0.180672                       # miss rate for ReadReq accesses
5129289Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data     0.049470                       # miss rate for WriteReq accesses
5139289Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total     0.049470                       # miss rate for WriteReq accesses
5149289Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.085681                       # miss rate for LoadLockedReq accesses
5159289Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total     0.085681                       # miss rate for LoadLockedReq accesses
5169079SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_rate::cpu.data     0.129197                       # miss rate for demand accesses
5179079SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_rate::total     0.129197                       # miss rate for demand accesses
5189079SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_rate::cpu.data     0.129197                       # miss rate for overall accesses
5199079SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_rate::total     0.129197                       # miss rate for overall accesses
5208721SN/Asystem.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
5218721SN/Asystem.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
5228721SN/Asystem.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
5238721SN/Asystem.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
5248983Snate@binkert.orgsystem.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
5258983Snate@binkert.orgsystem.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
5268721SN/Asystem.cpu.dcache.fast_writes                       0                       # number of fast writes performed
5278721SN/Asystem.cpu.dcache.cache_copies                      0                       # number of cache copies performed
5289079SAli.Saidi@ARM.comsystem.cpu.dcache.writebacks::writebacks       833491                       # number of writebacks
5299079SAli.Saidi@ARM.comsystem.cpu.dcache.writebacks::total            833491                       # number of writebacks
5308721SN/Asystem.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
5319289Sandreas.hansson@arm.comsystem.cpu.l2cache.replacements                992297                       # number of replacements
5329289Sandreas.hansson@arm.comsystem.cpu.l2cache.tagsinuse             65424.375500                       # Cycle average of tags in use
5339312Sandreas.hansson@arm.comsystem.cpu.l2cache.total_refs                 2433228                       # Total number of references to valid blocks.
5349289Sandreas.hansson@arm.comsystem.cpu.l2cache.sampled_refs               1057460                       # Sample count of references to valid blocks.
5359312Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_refs                  2.301012                       # Average number of references to valid blocks.
5369289Sandreas.hansson@arm.comsystem.cpu.l2cache.warmup_cycle             614754000                       # Cycle when the warmup percentage was hit.
5379312Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_blocks::writebacks 56309.097197                       # Average occupied blocks per requestor
5389312Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_blocks::cpu.inst   4867.351143                       # Average occupied blocks per requestor
5399312Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_blocks::cpu.data   4247.927159                       # Average occupied blocks per requestor
5409289Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::writebacks     0.859209                       # Average percentage of cache occupancy
5419289Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::cpu.inst     0.074270                       # Average percentage of cache occupancy
5429289Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::cpu.data     0.064818                       # Average percentage of cache occupancy
5439289Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::total        0.998297                       # Average percentage of cache occupancy
5449289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst       906782                       # number of ReadReq hits
5459312Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.data       811231                       # number of ReadReq hits
5469312Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::total        1718013                       # number of ReadReq hits
5479289Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::writebacks       833491                       # number of Writeback hits
5489289Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::total       833491                       # number of Writeback hits
5499289Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::cpu.data            4                       # number of UpgradeReq hits
5509289Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::total            4                       # number of UpgradeReq hits
5519289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data       187234                       # number of ReadExReq hits
5529289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::total       187234                       # number of ReadExReq hits
5539289Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst       906782                       # number of demand (read+write) hits
5549312Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.data       998465                       # number of demand (read+write) hits
5559312Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total         1905247                       # number of demand (read+write) hits
5569289Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst       906782                       # number of overall hits
5579312Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.data       998465                       # number of overall hits
5589312Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total        1905247                       # number of overall hits
5599289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst        13404                       # number of ReadReq misses
5609289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.data       927640                       # number of ReadReq misses
5619289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::total       941044                       # number of ReadReq misses
5629289Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::cpu.data           12                       # number of UpgradeReq misses
5639289Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::total           12                       # number of UpgradeReq misses
5649289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data       117115                       # number of ReadExReq misses
5659289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::total       117115                       # number of ReadExReq misses
5669289Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst        13404                       # number of demand (read+write) misses
5679289Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data      1044755                       # number of demand (read+write) misses
5689289Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total       1058159                       # number of demand (read+write) misses
5699289Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst        13404                       # number of overall misses
5709289Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data      1044755                       # number of overall misses
5719289Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total      1058159                       # number of overall misses
5729289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst       920186                       # number of ReadReq accesses(hits+misses)
5739312Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data      1738871                       # number of ReadReq accesses(hits+misses)
5749312Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::total      2659057                       # number of ReadReq accesses(hits+misses)
5759289Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::writebacks       833491                       # number of Writeback accesses(hits+misses)
5769289Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::total       833491                       # number of Writeback accesses(hits+misses)
5779289Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::cpu.data           16                       # number of UpgradeReq accesses(hits+misses)
5789289Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::total           16                       # number of UpgradeReq accesses(hits+misses)
5799289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data       304349                       # number of ReadExReq accesses(hits+misses)
5809289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total       304349                       # number of ReadExReq accesses(hits+misses)
5819289Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst       920186                       # number of demand (read+write) accesses
5829312Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data      2043220                       # number of demand (read+write) accesses
5839312Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total      2963406                       # number of demand (read+write) accesses
5849289Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst       920186                       # number of overall (read+write) accesses
5859312Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data      2043220                       # number of overall (read+write) accesses
5869312Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total      2963406                       # number of overall (read+write) accesses
5879289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.014567                       # miss rate for ReadReq accesses
5889312Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.533473                       # miss rate for ReadReq accesses
5899289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::total     0.353901                       # miss rate for ReadReq accesses
5909289Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.750000                       # miss rate for UpgradeReq accesses
5919289Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::total     0.750000                       # miss rate for UpgradeReq accesses
5929289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.384805                       # miss rate for ReadExReq accesses
5939289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total     0.384805                       # miss rate for ReadExReq accesses
5949289Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst     0.014567                       # miss rate for demand accesses
5959312Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data     0.511328                       # miss rate for demand accesses
5969289Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total     0.357075                       # miss rate for demand accesses
5979289Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst     0.014567                       # miss rate for overall accesses
5989312Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data     0.511328                       # miss rate for overall accesses
5999289Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total     0.357075                       # miss rate for overall accesses
6009289Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
6019289Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
6029289Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
6039289Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
6049289Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
6059289Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
6069289Sandreas.hansson@arm.comsystem.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
6079289Sandreas.hansson@arm.comsystem.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
6089289Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::writebacks        74287                       # number of writebacks
6099289Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::total            74287                       # number of writebacks
6109289Sandreas.hansson@arm.comsystem.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
6112968SN/A
6122968SN/A---------- End Simulation Statistics   ----------
613