stats.txt revision 5703
1 2---------- Begin Simulation Statistics ---------- 3host_inst_rate 3096300 # Simulator instruction rate (inst/s) 4host_mem_usage 288712 # Number of bytes of host memory used 5host_seconds 19.38 # Real time elapsed on the host 6host_tick_rate 94358252114 # Simulator tick rate (ticks/s) 7sim_freq 1000000000000 # Frequency of simulated ticks 8sim_insts 59995351 # Number of instructions simulated 9sim_seconds 1.828356 # Number of seconds simulated 10sim_ticks 1828355695500 # Number of ticks simulated 11system.cpu.dcache.LoadLockedReq_accesses 200279 # number of LoadLockedReq accesses(hits+misses) 12system.cpu.dcache.LoadLockedReq_hits 183118 # number of LoadLockedReq hits 13system.cpu.dcache.LoadLockedReq_miss_rate 0.085685 # miss rate for LoadLockedReq accesses 14system.cpu.dcache.LoadLockedReq_misses 17161 # number of LoadLockedReq misses 15system.cpu.dcache.ReadReq_accesses 9523053 # number of ReadReq accesses(hits+misses) 16system.cpu.dcache.ReadReq_hits 7801372 # number of ReadReq hits 17system.cpu.dcache.ReadReq_miss_rate 0.180791 # miss rate for ReadReq accesses 18system.cpu.dcache.ReadReq_misses 1721681 # number of ReadReq misses 19system.cpu.dcache.StoreCondReq_accesses 199258 # number of StoreCondReq accesses(hits+misses) 20system.cpu.dcache.StoreCondReq_hits 169391 # number of StoreCondReq hits 21system.cpu.dcache.StoreCondReq_miss_rate 0.149891 # miss rate for StoreCondReq accesses 22system.cpu.dcache.StoreCondReq_misses 29867 # number of StoreCondReq misses 23system.cpu.dcache.WriteReq_accesses 6150189 # number of WriteReq accesses(hits+misses) 24system.cpu.dcache.WriteReq_hits 5750766 # number of WriteReq hits 25system.cpu.dcache.WriteReq_miss_rate 0.064945 # miss rate for WriteReq accesses 26system.cpu.dcache.WriteReq_misses 399423 # number of WriteReq misses 27system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked 28system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked 29system.cpu.dcache.avg_refs 6.866519 # Average number of references to valid blocks. 30system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked 31system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked 32system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked 33system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked 34system.cpu.dcache.cache_copies 0 # number of cache copies performed 35system.cpu.dcache.demand_accesses 15673242 # number of demand (read+write) accesses 36system.cpu.dcache.demand_avg_miss_latency 0 # average overall miss latency 37system.cpu.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency 38system.cpu.dcache.demand_hits 13552138 # number of demand (read+write) hits 39system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles 40system.cpu.dcache.demand_miss_rate 0.135333 # miss rate for demand accesses 41system.cpu.dcache.demand_misses 2121104 # number of demand (read+write) misses 42system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 43system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 44system.cpu.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses 45system.cpu.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 46system.cpu.dcache.fast_writes 0 # number of fast writes performed 47system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 48system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 49system.cpu.dcache.overall_accesses 15673242 # number of overall (read+write) accesses 50system.cpu.dcache.overall_avg_miss_latency 0 # average overall miss latency 51system.cpu.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency 52system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency 53system.cpu.dcache.overall_hits 13552138 # number of overall hits 54system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles 55system.cpu.dcache.overall_miss_rate 0.135333 # miss rate for overall accesses 56system.cpu.dcache.overall_misses 2121104 # number of overall misses 57system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits 58system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 59system.cpu.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses 60system.cpu.dcache.overall_mshr_misses 0 # number of overall MSHR misses 61system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 62system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 63system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 64system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 65system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 66system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 67system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified 68system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 69system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 70system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 71system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 72system.cpu.dcache.replacements 2042676 # number of replacements 73system.cpu.dcache.sampled_refs 2043188 # Sample count of references to valid blocks. 74system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 75system.cpu.dcache.tagsinuse 511.997800 # Cycle average of tags in use 76system.cpu.dcache.total_refs 14029590 # Total number of references to valid blocks. 77system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. 78system.cpu.dcache.writebacks 428892 # number of writebacks 79system.cpu.dtb.accesses 1020787 # DTB accesses 80system.cpu.dtb.acv 367 # DTB access violations 81system.cpu.dtb.hits 16053817 # DTB hits 82system.cpu.dtb.misses 11471 # DTB misses 83system.cpu.dtb.read_accesses 728856 # DTB read accesses 84system.cpu.dtb.read_acv 210 # DTB read access violations 85system.cpu.dtb.read_hits 9703849 # DTB read hits 86system.cpu.dtb.read_misses 10329 # DTB read misses 87system.cpu.dtb.write_accesses 291931 # DTB write accesses 88system.cpu.dtb.write_acv 157 # DTB write access violations 89system.cpu.dtb.write_hits 6349968 # DTB write hits 90system.cpu.dtb.write_misses 1142 # DTB write misses 91system.cpu.icache.ReadReq_accesses 60007189 # number of ReadReq accesses(hits+misses) 92system.cpu.icache.ReadReq_hits 59087131 # number of ReadReq hits 93system.cpu.icache.ReadReq_miss_rate 0.015332 # miss rate for ReadReq accesses 94system.cpu.icache.ReadReq_misses 920058 # number of ReadReq misses 95system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked 96system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked 97system.cpu.icache.avg_refs 64.229122 # Average number of references to valid blocks. 98system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked 99system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked 100system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked 101system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked 102system.cpu.icache.cache_copies 0 # number of cache copies performed 103system.cpu.icache.demand_accesses 60007189 # number of demand (read+write) accesses 104system.cpu.icache.demand_avg_miss_latency 0 # average overall miss latency 105system.cpu.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency 106system.cpu.icache.demand_hits 59087131 # number of demand (read+write) hits 107system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles 108system.cpu.icache.demand_miss_rate 0.015332 # miss rate for demand accesses 109system.cpu.icache.demand_misses 920058 # number of demand (read+write) misses 110system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 111system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 112system.cpu.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses 113system.cpu.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 114system.cpu.icache.fast_writes 0 # number of fast writes performed 115system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated 116system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 117system.cpu.icache.overall_accesses 60007189 # number of overall (read+write) accesses 118system.cpu.icache.overall_avg_miss_latency 0 # average overall miss latency 119system.cpu.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency 120system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency 121system.cpu.icache.overall_hits 59087131 # number of overall hits 122system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles 123system.cpu.icache.overall_miss_rate 0.015332 # miss rate for overall accesses 124system.cpu.icache.overall_misses 920058 # number of overall misses 125system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits 126system.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 127system.cpu.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses 128system.cpu.icache.overall_mshr_misses 0 # number of overall MSHR misses 129system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 130system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 131system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 132system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 133system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 134system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 135system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified 136system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 137system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 138system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 139system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 140system.cpu.icache.replacements 919431 # number of replacements 141system.cpu.icache.sampled_refs 919943 # Sample count of references to valid blocks. 142system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 143system.cpu.icache.tagsinuse 511.214823 # Cycle average of tags in use 144system.cpu.icache.total_refs 59087131 # Total number of references to valid blocks. 145system.cpu.icache.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit. 146system.cpu.icache.writebacks 0 # number of writebacks 147system.cpu.idle_fraction 0.983588 # Percentage of idle cycles 148system.cpu.itb.accesses 4979228 # ITB accesses 149system.cpu.itb.acv 184 # ITB acv 150system.cpu.itb.hits 4974222 # ITB hits 151system.cpu.itb.misses 5006 # ITB misses 152system.cpu.kern.callpal 192140 # number of callpals executed 153system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed 154system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed 155system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed 156system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # number of callpals executed 157system.cpu.kern.callpal_swpctx 4177 2.17% 2.18% # number of callpals executed 158system.cpu.kern.callpal_tbi 54 0.03% 2.20% # number of callpals executed 159system.cpu.kern.callpal_wrent 7 0.00% 2.21% # number of callpals executed 160system.cpu.kern.callpal_swpipl 175211 91.19% 93.40% # number of callpals executed 161system.cpu.kern.callpal_rdps 6770 3.52% 96.92% # number of callpals executed 162system.cpu.kern.callpal_wrkgp 1 0.00% 96.92% # number of callpals executed 163system.cpu.kern.callpal_wrusp 7 0.00% 96.92% # number of callpals executed 164system.cpu.kern.callpal_rdusp 9 0.00% 96.93% # number of callpals executed 165system.cpu.kern.callpal_whami 2 0.00% 96.93% # number of callpals executed 166system.cpu.kern.callpal_rti 5202 2.71% 99.64% # number of callpals executed 167system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed 168system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed 169system.cpu.kern.inst.arm 0 # number of arm instructions executed 170system.cpu.kern.inst.hwrei 211278 # number of hwrei instructions executed 171system.cpu.kern.inst.quiesce 6240 # number of quiesce instructions executed 172system.cpu.kern.ipl_count 182522 # number of times we switched to this ipl 173system.cpu.kern.ipl_count_0 74815 40.99% 40.99% # number of times we switched to this ipl 174system.cpu.kern.ipl_count_21 243 0.13% 41.12% # number of times we switched to this ipl 175system.cpu.kern.ipl_count_22 1865 1.02% 42.14% # number of times we switched to this ipl 176system.cpu.kern.ipl_count_31 105599 57.86% 100.00% # number of times we switched to this ipl 177system.cpu.kern.ipl_good 149004 # number of times we switched to this ipl from a different ipl 178system.cpu.kern.ipl_good_0 73448 49.29% 49.29% # number of times we switched to this ipl from a different ipl 179system.cpu.kern.ipl_good_21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl 180system.cpu.kern.ipl_good_22 1865 1.25% 50.71% # number of times we switched to this ipl from a different ipl 181system.cpu.kern.ipl_good_31 73448 49.29% 100.00% # number of times we switched to this ipl from a different ipl 182system.cpu.kern.ipl_ticks 1828355488000 # number of cycles we spent at this ipl 183system.cpu.kern.ipl_ticks_0 1811087822500 99.06% 99.06% # number of cycles we spent at this ipl 184system.cpu.kern.ipl_ticks_21 20110000 0.00% 99.06% # number of cycles we spent at this ipl 185system.cpu.kern.ipl_ticks_22 80195000 0.00% 99.06% # number of cycles we spent at this ipl 186system.cpu.kern.ipl_ticks_31 17167360500 0.94% 100.00% # number of cycles we spent at this ipl 187system.cpu.kern.ipl_used_0 0.981728 # fraction of swpipl calls that actually changed the ipl 188system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl 189system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl 190system.cpu.kern.ipl_used_31 0.695537 # fraction of swpipl calls that actually changed the ipl 191system.cpu.kern.mode_good_kernel 1909 192system.cpu.kern.mode_good_user 1738 193system.cpu.kern.mode_good_idle 171 194system.cpu.kern.mode_switch_kernel 5948 # number of protection mode switches 195system.cpu.kern.mode_switch_user 1738 # number of protection mode switches 196system.cpu.kern.mode_switch_idle 2097 # number of protection mode switches 197system.cpu.kern.mode_switch_good 1.402493 # fraction of useful protection mode switches 198system.cpu.kern.mode_switch_good_kernel 0.320948 # fraction of useful protection mode switches 199system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches 200system.cpu.kern.mode_switch_good_idle 0.081545 # fraction of useful protection mode switches 201system.cpu.kern.mode_ticks_kernel 26834029500 1.47% 1.47% # number of ticks spent at the given mode 202system.cpu.kern.mode_ticks_user 1465074000 0.08% 1.55% # number of ticks spent at the given mode 203system.cpu.kern.mode_ticks_idle 1800056383500 98.45% 100.00% # number of ticks spent at the given mode 204system.cpu.kern.swap_context 4178 # number of times the context was actually changed 205system.cpu.kern.syscall 326 # number of syscalls executed 206system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed 207system.cpu.kern.syscall_3 30 9.20% 11.66% # number of syscalls executed 208system.cpu.kern.syscall_4 4 1.23% 12.88% # number of syscalls executed 209system.cpu.kern.syscall_6 42 12.88% 25.77% # number of syscalls executed 210system.cpu.kern.syscall_12 1 0.31% 26.07% # number of syscalls executed 211system.cpu.kern.syscall_15 1 0.31% 26.38% # number of syscalls executed 212system.cpu.kern.syscall_17 15 4.60% 30.98% # number of syscalls executed 213system.cpu.kern.syscall_19 10 3.07% 34.05% # number of syscalls executed 214system.cpu.kern.syscall_20 6 1.84% 35.89% # number of syscalls executed 215system.cpu.kern.syscall_23 4 1.23% 37.12% # number of syscalls executed 216system.cpu.kern.syscall_24 6 1.84% 38.96% # number of syscalls executed 217system.cpu.kern.syscall_33 11 3.37% 42.33% # number of syscalls executed 218system.cpu.kern.syscall_41 2 0.61% 42.94% # number of syscalls executed 219system.cpu.kern.syscall_45 54 16.56% 59.51% # number of syscalls executed 220system.cpu.kern.syscall_47 6 1.84% 61.35% # number of syscalls executed 221system.cpu.kern.syscall_48 10 3.07% 64.42% # number of syscalls executed 222system.cpu.kern.syscall_54 10 3.07% 67.48% # number of syscalls executed 223system.cpu.kern.syscall_58 1 0.31% 67.79% # number of syscalls executed 224system.cpu.kern.syscall_59 7 2.15% 69.94% # number of syscalls executed 225system.cpu.kern.syscall_71 54 16.56% 86.50% # number of syscalls executed 226system.cpu.kern.syscall_73 3 0.92% 87.42% # number of syscalls executed 227system.cpu.kern.syscall_74 16 4.91% 92.33% # number of syscalls executed 228system.cpu.kern.syscall_87 1 0.31% 92.64% # number of syscalls executed 229system.cpu.kern.syscall_90 3 0.92% 93.56% # number of syscalls executed 230system.cpu.kern.syscall_92 9 2.76% 96.32% # number of syscalls executed 231system.cpu.kern.syscall_97 2 0.61% 96.93% # number of syscalls executed 232system.cpu.kern.syscall_98 2 0.61% 97.55% # number of syscalls executed 233system.cpu.kern.syscall_132 4 1.23% 98.77% # number of syscalls executed 234system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed 235system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed 236system.cpu.not_idle_fraction 0.016412 # Percentage of non-idle cycles 237system.cpu.numCycles 3656711283 # number of cpu cycles simulated 238system.cpu.num_insts 59995351 # Number of instructions executed 239system.cpu.num_refs 16302128 # Number of memory references 240system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 241system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 242system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 243system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 244system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 245system.disk0.dma_write_txs 395 # Number of DMA write transactions. 246system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 247system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 248system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 249system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 250system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 251system.disk2.dma_write_txs 1 # Number of DMA write transactions. 252system.iocache.ReadReq_accesses 174 # number of ReadReq accesses(hits+misses) 253system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses 254system.iocache.ReadReq_misses 174 # number of ReadReq misses 255system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses) 256system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses 257system.iocache.WriteReq_misses 41552 # number of WriteReq misses 258system.iocache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked 259system.iocache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked 260system.iocache.avg_refs 0 # Average number of references to valid blocks. 261system.iocache.blocked_no_mshrs 0 # number of cycles access was blocked 262system.iocache.blocked_no_targets 0 # number of cycles access was blocked 263system.iocache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked 264system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked 265system.iocache.cache_copies 0 # number of cache copies performed 266system.iocache.demand_accesses 41726 # number of demand (read+write) accesses 267system.iocache.demand_avg_miss_latency 0 # average overall miss latency 268system.iocache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency 269system.iocache.demand_hits 0 # number of demand (read+write) hits 270system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles 271system.iocache.demand_miss_rate 1 # miss rate for demand accesses 272system.iocache.demand_misses 41726 # number of demand (read+write) misses 273system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 274system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 275system.iocache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses 276system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 277system.iocache.fast_writes 0 # number of fast writes performed 278system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated 279system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 280system.iocache.overall_accesses 41726 # number of overall (read+write) accesses 281system.iocache.overall_avg_miss_latency 0 # average overall miss latency 282system.iocache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency 283system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency 284system.iocache.overall_hits 0 # number of overall hits 285system.iocache.overall_miss_latency 0 # number of overall miss cycles 286system.iocache.overall_miss_rate 1 # miss rate for overall accesses 287system.iocache.overall_misses 41726 # number of overall misses 288system.iocache.overall_mshr_hits 0 # number of overall MSHR hits 289system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 290system.iocache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses 291system.iocache.overall_mshr_misses 0 # number of overall MSHR misses 292system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 293system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 294system.iocache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 295system.iocache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 296system.iocache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 297system.iocache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 298system.iocache.prefetcher.num_hwpf_identified 0 # number of hwpf identified 299system.iocache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 300system.iocache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 301system.iocache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 302system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 303system.iocache.replacements 41686 # number of replacements 304system.iocache.sampled_refs 41702 # Sample count of references to valid blocks. 305system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 306system.iocache.tagsinuse 1.226225 # Cycle average of tags in use 307system.iocache.total_refs 0 # Total number of references to valid blocks. 308system.iocache.warmup_cycle 1684804097017 # Cycle when the warmup percentage was hit. 309system.iocache.writebacks 41512 # number of writebacks 310system.l2c.ReadExReq_accesses 304347 # number of ReadExReq accesses(hits+misses) 311system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses 312system.l2c.ReadExReq_misses 304347 # number of ReadExReq misses 313system.l2c.ReadReq_accesses 2658883 # number of ReadReq accesses(hits+misses) 314system.l2c.ReadReq_hits 1696464 # number of ReadReq hits 315system.l2c.ReadReq_miss_rate 0.361964 # miss rate for ReadReq accesses 316system.l2c.ReadReq_misses 962419 # number of ReadReq misses 317system.l2c.UpgradeReq_accesses 124943 # number of UpgradeReq accesses(hits+misses) 318system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses 319system.l2c.UpgradeReq_misses 124943 # number of UpgradeReq misses 320system.l2c.Writeback_accesses 428892 # number of Writeback accesses(hits+misses) 321system.l2c.Writeback_hits 428892 # number of Writeback hits 322system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked 323system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked 324system.l2c.avg_refs 1.726803 # Average number of references to valid blocks. 325system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked 326system.l2c.blocked_no_targets 0 # number of cycles access was blocked 327system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked 328system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked 329system.l2c.cache_copies 0 # number of cache copies performed 330system.l2c.demand_accesses 2963230 # number of demand (read+write) accesses 331system.l2c.demand_avg_miss_latency 0 # average overall miss latency 332system.l2c.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency 333system.l2c.demand_hits 1696464 # number of demand (read+write) hits 334system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles 335system.l2c.demand_miss_rate 0.427495 # miss rate for demand accesses 336system.l2c.demand_misses 1266766 # number of demand (read+write) misses 337system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 338system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 339system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses 340system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 341system.l2c.fast_writes 0 # number of fast writes performed 342system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated 343system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 344system.l2c.overall_accesses 2963230 # number of overall (read+write) accesses 345system.l2c.overall_avg_miss_latency 0 # average overall miss latency 346system.l2c.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency 347system.l2c.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency 348system.l2c.overall_hits 1696464 # number of overall hits 349system.l2c.overall_miss_latency 0 # number of overall miss cycles 350system.l2c.overall_miss_rate 0.427495 # miss rate for overall accesses 351system.l2c.overall_misses 1266766 # number of overall misses 352system.l2c.overall_mshr_hits 0 # number of overall MSHR hits 353system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 354system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses 355system.l2c.overall_mshr_misses 0 # number of overall MSHR misses 356system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 357system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 358system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 359system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 360system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 361system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 362system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified 363system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued 364system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 365system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 366system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 367system.l2c.replacements 1050731 # number of replacements 368system.l2c.sampled_refs 1081071 # Sample count of references to valid blocks. 369system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 370system.l2c.tagsinuse 30223.992851 # Cycle average of tags in use 371system.l2c.total_refs 1866797 # Total number of references to valid blocks. 372system.l2c.warmup_cycle 765422500 # Cycle when the warmup percentage was hit. 373system.l2c.writebacks 119150 # number of writebacks 374system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post 375system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post 376system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post 377system.tsunami.ethernet.coalescedRxOrn <err: div-0> # average number of RxOrn's coalesced into each post 378system.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post 379system.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post 380system.tsunami.ethernet.coalescedTxDesc <err: div-0> # average number of TxDesc's coalesced into each post 381system.tsunami.ethernet.coalescedTxIdle <err: div-0> # average number of TxIdle's coalesced into each post 382system.tsunami.ethernet.coalescedTxOk <err: div-0> # average number of TxOk's coalesced into each post 383system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 384system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 385system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 386system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 387system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 388system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 389system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 390system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 391system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 392system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 393system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 394system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 395system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 396system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 397system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 398system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 399system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 400system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 401system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 402system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 403system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 404system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 405 406---------- End Simulation Statistics ---------- 407