stats.txt revision 8802:ef66a9083bc4
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.870336 # Number of seconds simulated 4sim_ticks 1870335522500 # Number of ticks simulated 5final_tick 1870335522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 3272042 # Simulator instruction rate (inst/s) 8host_tick_rate 96902915749 # Simulator tick rate (ticks/s) 9host_mem_usage 296264 # Number of bytes of host memory used 10host_seconds 19.30 # Real time elapsed on the host 11sim_insts 63154034 # Number of instructions simulated 12system.physmem.bytes_read 72297472 # Number of bytes read from this memory 13system.physmem.bytes_inst_read 995008 # Number of instructions bytes read from this memory 14system.physmem.bytes_written 10452352 # Number of bytes written to this memory 15system.physmem.num_reads 1129648 # Number of read requests responded to by this memory 16system.physmem.num_writes 163318 # Number of write requests responded to by this memory 17system.physmem.num_other 0 # Number of other requests responded to by this memory 18system.physmem.bw_read 38654814 # Total read bandwidth from this memory (bytes/s) 19system.physmem.bw_inst_read 531994 # Instruction read bandwidth from this memory (bytes/s) 20system.physmem.bw_write 5588490 # Write bandwidth from this memory (bytes/s) 21system.physmem.bw_total 44243304 # Total bandwidth to/from this memory (bytes/s) 22system.l2c.replacements 1051788 # number of replacements 23system.l2c.tagsinuse 34117.721410 # Cycle average of tags in use 24system.l2c.total_refs 2341203 # Total number of references to valid blocks. 25system.l2c.sampled_refs 1087985 # Sample count of references to valid blocks. 26system.l2c.avg_refs 2.151871 # Average number of references to valid blocks. 27system.l2c.warmup_cycle 990121000 # Cycle when the warmup percentage was hit. 28system.l2c.occ_blocks::0 10019.673951 # Average occupied blocks per context 29system.l2c.occ_blocks::1 266.115685 # Average occupied blocks per context 30system.l2c.occ_blocks::2 23831.931773 # Average occupied blocks per context 31system.l2c.occ_percent::0 0.152888 # Average percentage of cache occupancy 32system.l2c.occ_percent::1 0.004061 # Average percentage of cache occupancy 33system.l2c.occ_percent::2 0.363646 # Average percentage of cache occupancy 34system.l2c.ReadReq_hits::0 1620505 # number of ReadReq hits 35system.l2c.ReadReq_hits::1 137130 # number of ReadReq hits 36system.l2c.ReadReq_hits::total 1757635 # number of ReadReq hits 37system.l2c.Writeback_hits::0 811846 # number of Writeback hits 38system.l2c.Writeback_hits::total 811846 # number of Writeback hits 39system.l2c.UpgradeReq_hits::0 134 # number of UpgradeReq hits 40system.l2c.UpgradeReq_hits::1 39 # number of UpgradeReq hits 41system.l2c.UpgradeReq_hits::total 173 # number of UpgradeReq hits 42system.l2c.SCUpgradeReq_hits::0 15 # number of SCUpgradeReq hits 43system.l2c.SCUpgradeReq_hits::1 9 # number of SCUpgradeReq hits 44system.l2c.SCUpgradeReq_hits::total 24 # number of SCUpgradeReq hits 45system.l2c.ReadExReq_hits::0 164417 # number of ReadExReq hits 46system.l2c.ReadExReq_hits::1 14126 # number of ReadExReq hits 47system.l2c.ReadExReq_hits::total 178543 # number of ReadExReq hits 48system.l2c.demand_hits::0 1784922 # number of demand (read+write) hits 49system.l2c.demand_hits::1 151256 # number of demand (read+write) hits 50system.l2c.demand_hits::2 0 # number of demand (read+write) hits 51system.l2c.demand_hits::total 1936178 # number of demand (read+write) hits 52system.l2c.overall_hits::0 1784922 # number of overall hits 53system.l2c.overall_hits::1 151256 # number of overall hits 54system.l2c.overall_hits::2 0 # number of overall hits 55system.l2c.overall_hits::total 1936178 # number of overall hits 56system.l2c.ReadReq_misses::0 956917 # number of ReadReq misses 57system.l2c.ReadReq_misses::1 4511 # number of ReadReq misses 58system.l2c.ReadReq_misses::total 961428 # number of ReadReq misses 59system.l2c.UpgradeReq_misses::0 2441 # number of UpgradeReq misses 60system.l2c.UpgradeReq_misses::1 567 # number of UpgradeReq misses 61system.l2c.UpgradeReq_misses::total 3008 # number of UpgradeReq misses 62system.l2c.SCUpgradeReq_misses::0 65 # number of SCUpgradeReq misses 63system.l2c.SCUpgradeReq_misses::1 101 # number of SCUpgradeReq misses 64system.l2c.SCUpgradeReq_misses::total 166 # number of SCUpgradeReq misses 65system.l2c.ReadExReq_misses::0 117481 # number of ReadExReq misses 66system.l2c.ReadExReq_misses::1 9826 # number of ReadExReq misses 67system.l2c.ReadExReq_misses::total 127307 # number of ReadExReq misses 68system.l2c.demand_misses::0 1074398 # number of demand (read+write) misses 69system.l2c.demand_misses::1 14337 # number of demand (read+write) misses 70system.l2c.demand_misses::2 0 # number of demand (read+write) misses 71system.l2c.demand_misses::total 1088735 # number of demand (read+write) misses 72system.l2c.overall_misses::0 1074398 # number of overall misses 73system.l2c.overall_misses::1 14337 # number of overall misses 74system.l2c.overall_misses::2 0 # number of overall misses 75system.l2c.overall_misses::total 1088735 # number of overall misses 76system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles 77system.l2c.overall_miss_latency 0 # number of overall miss cycles 78system.l2c.ReadReq_accesses::0 2577422 # number of ReadReq accesses(hits+misses) 79system.l2c.ReadReq_accesses::1 141641 # number of ReadReq accesses(hits+misses) 80system.l2c.ReadReq_accesses::total 2719063 # number of ReadReq accesses(hits+misses) 81system.l2c.Writeback_accesses::0 811846 # number of Writeback accesses(hits+misses) 82system.l2c.Writeback_accesses::total 811846 # number of Writeback accesses(hits+misses) 83system.l2c.UpgradeReq_accesses::0 2575 # number of UpgradeReq accesses(hits+misses) 84system.l2c.UpgradeReq_accesses::1 606 # number of UpgradeReq accesses(hits+misses) 85system.l2c.UpgradeReq_accesses::total 3181 # number of UpgradeReq accesses(hits+misses) 86system.l2c.SCUpgradeReq_accesses::0 80 # number of SCUpgradeReq accesses(hits+misses) 87system.l2c.SCUpgradeReq_accesses::1 110 # number of SCUpgradeReq accesses(hits+misses) 88system.l2c.SCUpgradeReq_accesses::total 190 # number of SCUpgradeReq accesses(hits+misses) 89system.l2c.ReadExReq_accesses::0 281898 # number of ReadExReq accesses(hits+misses) 90system.l2c.ReadExReq_accesses::1 23952 # number of ReadExReq accesses(hits+misses) 91system.l2c.ReadExReq_accesses::total 305850 # number of ReadExReq accesses(hits+misses) 92system.l2c.demand_accesses::0 2859320 # number of demand (read+write) accesses 93system.l2c.demand_accesses::1 165593 # number of demand (read+write) accesses 94system.l2c.demand_accesses::2 0 # number of demand (read+write) accesses 95system.l2c.demand_accesses::total 3024913 # number of demand (read+write) accesses 96system.l2c.overall_accesses::0 2859320 # number of overall (read+write) accesses 97system.l2c.overall_accesses::1 165593 # number of overall (read+write) accesses 98system.l2c.overall_accesses::2 0 # number of overall (read+write) accesses 99system.l2c.overall_accesses::total 3024913 # number of overall (read+write) accesses 100system.l2c.ReadReq_miss_rate::0 0.371269 # miss rate for ReadReq accesses 101system.l2c.ReadReq_miss_rate::1 0.031848 # miss rate for ReadReq accesses 102system.l2c.UpgradeReq_miss_rate::0 0.947961 # miss rate for UpgradeReq accesses 103system.l2c.UpgradeReq_miss_rate::1 0.935644 # miss rate for UpgradeReq accesses 104system.l2c.SCUpgradeReq_miss_rate::0 0.812500 # miss rate for SCUpgradeReq accesses 105system.l2c.SCUpgradeReq_miss_rate::1 0.918182 # miss rate for SCUpgradeReq accesses 106system.l2c.ReadExReq_miss_rate::0 0.416750 # miss rate for ReadExReq accesses 107system.l2c.ReadExReq_miss_rate::1 0.410237 # miss rate for ReadExReq accesses 108system.l2c.demand_miss_rate::0 0.375753 # miss rate for demand accesses 109system.l2c.demand_miss_rate::1 0.086580 # miss rate for demand accesses 110system.l2c.demand_miss_rate::2 no_value # miss rate for demand accesses 111system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses 112system.l2c.overall_miss_rate::0 0.375753 # miss rate for overall accesses 113system.l2c.overall_miss_rate::1 0.086580 # miss rate for overall accesses 114system.l2c.overall_miss_rate::2 no_value # miss rate for overall accesses 115system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses 116system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency 117system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency 118system.l2c.demand_avg_miss_latency::2 no_value # average overall miss latency 119system.l2c.demand_avg_miss_latency::total no_value # average overall miss latency 120system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency 121system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency 122system.l2c.overall_avg_miss_latency::2 no_value # average overall miss latency 123system.l2c.overall_avg_miss_latency::total no_value # average overall miss latency 124system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 125system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 126system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 127system.l2c.blocked::no_targets 0 # number of cycles access was blocked 128system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 129system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 130system.l2c.fast_writes 0 # number of fast writes performed 131system.l2c.cache_copies 0 # number of cache copies performed 132system.l2c.writebacks 121798 # number of writebacks 133system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 134system.l2c.overall_mshr_hits 0 # number of overall MSHR hits 135system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 136system.l2c.overall_mshr_misses 0 # number of overall MSHR misses 137system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 138system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 139system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 140system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 141system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses 142system.l2c.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses 143system.l2c.demand_mshr_miss_rate::2 no_value # mshr miss rate for demand accesses 144system.l2c.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses 145system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses 146system.l2c.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses 147system.l2c.overall_mshr_miss_rate::2 no_value # mshr miss rate for overall accesses 148system.l2c.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses 149system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 150system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 151system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 152system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated 153system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 154system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 155system.iocache.replacements 41695 # number of replacements 156system.iocache.tagsinuse 0.435437 # Cycle average of tags in use 157system.iocache.total_refs 0 # Total number of references to valid blocks. 158system.iocache.sampled_refs 41711 # Sample count of references to valid blocks. 159system.iocache.avg_refs 0 # Average number of references to valid blocks. 160system.iocache.warmup_cycle 1685787165017 # Cycle when the warmup percentage was hit. 161system.iocache.occ_blocks::1 0.435437 # Average occupied blocks per context 162system.iocache.occ_percent::1 0.027215 # Average percentage of cache occupancy 163system.iocache.demand_hits::0 0 # number of demand (read+write) hits 164system.iocache.demand_hits::1 0 # number of demand (read+write) hits 165system.iocache.demand_hits::total 0 # number of demand (read+write) hits 166system.iocache.overall_hits::0 0 # number of overall hits 167system.iocache.overall_hits::1 0 # number of overall hits 168system.iocache.overall_hits::total 0 # number of overall hits 169system.iocache.ReadReq_misses::1 175 # number of ReadReq misses 170system.iocache.ReadReq_misses::total 175 # number of ReadReq misses 171system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses 172system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 173system.iocache.demand_misses::0 0 # number of demand (read+write) misses 174system.iocache.demand_misses::1 41727 # number of demand (read+write) misses 175system.iocache.demand_misses::total 41727 # number of demand (read+write) misses 176system.iocache.overall_misses::0 0 # number of overall misses 177system.iocache.overall_misses::1 41727 # number of overall misses 178system.iocache.overall_misses::total 41727 # number of overall misses 179system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles 180system.iocache.overall_miss_latency 0 # number of overall miss cycles 181system.iocache.ReadReq_accesses::1 175 # number of ReadReq accesses(hits+misses) 182system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) 183system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) 184system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 185system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses 186system.iocache.demand_accesses::1 41727 # number of demand (read+write) accesses 187system.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses 188system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses 189system.iocache.overall_accesses::1 41727 # number of overall (read+write) accesses 190system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses 191system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses 192system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses 193system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses 194system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses 195system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses 196system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses 197system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses 198system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses 199system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency 200system.iocache.demand_avg_miss_latency::1 0 # average overall miss latency 201system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency 202system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency 203system.iocache.overall_avg_miss_latency::1 0 # average overall miss latency 204system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency 205system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 206system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 207system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 208system.iocache.blocked::no_targets 0 # number of cycles access was blocked 209system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 210system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 211system.iocache.fast_writes 0 # number of fast writes performed 212system.iocache.cache_copies 0 # number of cache copies performed 213system.iocache.writebacks 41520 # number of writebacks 214system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 215system.iocache.overall_mshr_hits 0 # number of overall MSHR hits 216system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 217system.iocache.overall_mshr_misses 0 # number of overall MSHR misses 218system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 219system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 220system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 221system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 222system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses 223system.iocache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses 224system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses 225system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses 226system.iocache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses 227system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses 228system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 229system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 230system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 231system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated 232system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 233system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 234system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 235system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 236system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 237system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 238system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 239system.disk0.dma_write_txs 395 # Number of DMA write transactions. 240system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 241system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 242system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 243system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 244system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 245system.disk2.dma_write_txs 1 # Number of DMA write transactions. 246system.cpu0.dtb.fetch_hits 0 # ITB hits 247system.cpu0.dtb.fetch_misses 0 # ITB misses 248system.cpu0.dtb.fetch_acv 0 # ITB acv 249system.cpu0.dtb.fetch_accesses 0 # ITB accesses 250system.cpu0.dtb.read_hits 9154530 # DTB read hits 251system.cpu0.dtb.read_misses 7079 # DTB read misses 252system.cpu0.dtb.read_acv 152 # DTB read access violations 253system.cpu0.dtb.read_accesses 508987 # DTB read accesses 254system.cpu0.dtb.write_hits 5936899 # DTB write hits 255system.cpu0.dtb.write_misses 726 # DTB write misses 256system.cpu0.dtb.write_acv 99 # DTB write access violations 257system.cpu0.dtb.write_accesses 189050 # DTB write accesses 258system.cpu0.dtb.data_hits 15091429 # DTB hits 259system.cpu0.dtb.data_misses 7805 # DTB misses 260system.cpu0.dtb.data_acv 251 # DTB access violations 261system.cpu0.dtb.data_accesses 698037 # DTB accesses 262system.cpu0.itb.fetch_hits 3855556 # ITB hits 263system.cpu0.itb.fetch_misses 3485 # ITB misses 264system.cpu0.itb.fetch_acv 127 # ITB acv 265system.cpu0.itb.fetch_accesses 3859041 # ITB accesses 266system.cpu0.itb.read_hits 0 # DTB read hits 267system.cpu0.itb.read_misses 0 # DTB read misses 268system.cpu0.itb.read_acv 0 # DTB read access violations 269system.cpu0.itb.read_accesses 0 # DTB read accesses 270system.cpu0.itb.write_hits 0 # DTB write hits 271system.cpu0.itb.write_misses 0 # DTB write misses 272system.cpu0.itb.write_acv 0 # DTB write access violations 273system.cpu0.itb.write_accesses 0 # DTB write accesses 274system.cpu0.itb.data_hits 0 # DTB hits 275system.cpu0.itb.data_misses 0 # DTB misses 276system.cpu0.itb.data_acv 0 # DTB access violations 277system.cpu0.itb.data_accesses 0 # DTB accesses 278system.cpu0.numCycles 3740670933 # number of cpu cycles simulated 279system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 280system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 281system.cpu0.num_insts 57222076 # Number of instructions executed 282system.cpu0.num_int_alu_accesses 53249924 # Number of integer alu accesses 283system.cpu0.num_fp_alu_accesses 299810 # Number of float alu accesses 284system.cpu0.num_func_calls 1399585 # number of times a function call or return occured 285system.cpu0.num_conditional_control_insts 6808233 # number of instructions that are conditional controls 286system.cpu0.num_int_insts 53249924 # number of integer instructions 287system.cpu0.num_fp_insts 299810 # number of float instructions 288system.cpu0.num_int_register_reads 73318596 # number of times the integer registers were read 289system.cpu0.num_int_register_writes 39827534 # number of times the integer registers were written 290system.cpu0.num_fp_register_reads 147724 # number of times the floating registers were read 291system.cpu0.num_fp_register_writes 150835 # number of times the floating registers were written 292system.cpu0.num_mem_refs 15135515 # number of memory refs 293system.cpu0.num_load_insts 9184477 # Number of load instructions 294system.cpu0.num_store_insts 5951038 # Number of store instructions 295system.cpu0.num_idle_cycles 3683437089.313678 # Number of idle cycles 296system.cpu0.num_busy_cycles 57233843.686322 # Number of busy cycles 297system.cpu0.not_idle_fraction 0.015300 # Percentage of non-idle cycles 298system.cpu0.idle_fraction 0.984700 # Percentage of idle cycles 299system.cpu0.kern.inst.arm 0 # number of arm instructions executed 300system.cpu0.kern.inst.quiesce 6283 # number of quiesce instructions executed 301system.cpu0.kern.inst.hwrei 197120 # number of hwrei instructions executed 302system.cpu0.kern.ipl_count::0 71004 40.60% 40.60% # number of times we switched to this ipl 303system.cpu0.kern.ipl_count::21 243 0.14% 40.74% # number of times we switched to this ipl 304system.cpu0.kern.ipl_count::22 1908 1.09% 41.83% # number of times we switched to this ipl 305system.cpu0.kern.ipl_count::30 8 0.00% 41.84% # number of times we switched to this ipl 306system.cpu0.kern.ipl_count::31 101705 58.16% 100.00% # number of times we switched to this ipl 307system.cpu0.kern.ipl_count::total 174868 # number of times we switched to this ipl 308system.cpu0.kern.ipl_good::0 69637 49.24% 49.24% # number of times we switched to this ipl from a different ipl 309system.cpu0.kern.ipl_good::21 243 0.17% 49.41% # number of times we switched to this ipl from a different ipl 310system.cpu0.kern.ipl_good::22 1908 1.35% 50.76% # number of times we switched to this ipl from a different ipl 311system.cpu0.kern.ipl_good::30 8 0.01% 50.77% # number of times we switched to this ipl from a different ipl 312system.cpu0.kern.ipl_good::31 69629 49.23% 100.00% # number of times we switched to this ipl from a different ipl 313system.cpu0.kern.ipl_good::total 141425 # number of times we switched to this ipl from a different ipl 314system.cpu0.kern.ipl_ticks::0 1852989766500 99.07% 99.07% # number of cycles we spent at this ipl 315system.cpu0.kern.ipl_ticks::21 20110000 0.00% 99.07% # number of cycles we spent at this ipl 316system.cpu0.kern.ipl_ticks::22 82044000 0.00% 99.08% # number of cycles we spent at this ipl 317system.cpu0.kern.ipl_ticks::30 949500 0.00% 99.08% # number of cycles we spent at this ipl 318system.cpu0.kern.ipl_ticks::31 17242445000 0.92% 100.00% # number of cycles we spent at this ipl 319system.cpu0.kern.ipl_ticks::total 1870335315000 # number of cycles we spent at this ipl 320system.cpu0.kern.ipl_used::0 0.980748 # fraction of swpipl calls that actually changed the ipl 321system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 322system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 323system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 324system.cpu0.kern.ipl_used::31 0.684617 # fraction of swpipl calls that actually changed the ipl 325system.cpu0.kern.syscall::2 6 2.65% 2.65% # number of syscalls executed 326system.cpu0.kern.syscall::3 19 8.41% 11.06% # number of syscalls executed 327system.cpu0.kern.syscall::4 2 0.88% 11.95% # number of syscalls executed 328system.cpu0.kern.syscall::6 32 14.16% 26.11% # number of syscalls executed 329system.cpu0.kern.syscall::12 1 0.44% 26.55% # number of syscalls executed 330system.cpu0.kern.syscall::15 1 0.44% 26.99% # number of syscalls executed 331system.cpu0.kern.syscall::17 9 3.98% 30.97% # number of syscalls executed 332system.cpu0.kern.syscall::19 8 3.54% 34.51% # number of syscalls executed 333system.cpu0.kern.syscall::20 6 2.65% 37.17% # number of syscalls executed 334system.cpu0.kern.syscall::23 2 0.88% 38.05% # number of syscalls executed 335system.cpu0.kern.syscall::24 4 1.77% 39.82% # number of syscalls executed 336system.cpu0.kern.syscall::33 7 3.10% 42.92% # number of syscalls executed 337system.cpu0.kern.syscall::41 2 0.88% 43.81% # number of syscalls executed 338system.cpu0.kern.syscall::45 37 16.37% 60.18% # number of syscalls executed 339system.cpu0.kern.syscall::47 4 1.77% 61.95% # number of syscalls executed 340system.cpu0.kern.syscall::48 8 3.54% 65.49% # number of syscalls executed 341system.cpu0.kern.syscall::54 10 4.42% 69.91% # number of syscalls executed 342system.cpu0.kern.syscall::58 1 0.44% 70.35% # number of syscalls executed 343system.cpu0.kern.syscall::59 4 1.77% 72.12% # number of syscalls executed 344system.cpu0.kern.syscall::71 30 13.27% 85.40% # number of syscalls executed 345system.cpu0.kern.syscall::73 3 1.33% 86.73% # number of syscalls executed 346system.cpu0.kern.syscall::74 8 3.54% 90.27% # number of syscalls executed 347system.cpu0.kern.syscall::87 1 0.44% 90.71% # number of syscalls executed 348system.cpu0.kern.syscall::90 2 0.88% 91.59% # number of syscalls executed 349system.cpu0.kern.syscall::92 9 3.98% 95.58% # number of syscalls executed 350system.cpu0.kern.syscall::97 2 0.88% 96.46% # number of syscalls executed 351system.cpu0.kern.syscall::98 2 0.88% 97.35% # number of syscalls executed 352system.cpu0.kern.syscall::132 2 0.88% 98.23% # number of syscalls executed 353system.cpu0.kern.syscall::144 2 0.88% 99.12% # number of syscalls executed 354system.cpu0.kern.syscall::147 2 0.88% 100.00% # number of syscalls executed 355system.cpu0.kern.syscall::total 226 # number of syscalls executed 356system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 357system.cpu0.kern.callpal::wripir 110 0.06% 0.06% # number of callpals executed 358system.cpu0.kern.callpal::wrmces 1 0.00% 0.06% # number of callpals executed 359system.cpu0.kern.callpal::wrfen 1 0.00% 0.06% # number of callpals executed 360system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.06% # number of callpals executed 361system.cpu0.kern.callpal::swpctx 3762 2.05% 2.11% # number of callpals executed 362system.cpu0.kern.callpal::tbi 38 0.02% 2.14% # number of callpals executed 363system.cpu0.kern.callpal::wrent 7 0.00% 2.14% # number of callpals executed 364system.cpu0.kern.callpal::swpipl 168035 91.68% 93.82% # number of callpals executed 365system.cpu0.kern.callpal::rdps 6150 3.36% 97.17% # number of callpals executed 366system.cpu0.kern.callpal::wrkgp 1 0.00% 97.17% # number of callpals executed 367system.cpu0.kern.callpal::wrusp 3 0.00% 97.17% # number of callpals executed 368system.cpu0.kern.callpal::rdusp 7 0.00% 97.18% # number of callpals executed 369system.cpu0.kern.callpal::whami 2 0.00% 97.18% # number of callpals executed 370system.cpu0.kern.callpal::rti 4673 2.55% 99.73% # number of callpals executed 371system.cpu0.kern.callpal::callsys 357 0.19% 99.92% # number of callpals executed 372system.cpu0.kern.callpal::imb 142 0.08% 100.00% # number of callpals executed 373system.cpu0.kern.callpal::total 183291 # number of callpals executed 374system.cpu0.kern.mode_switch::kernel 7091 # number of protection mode switches 375system.cpu0.kern.mode_switch::user 1158 # number of protection mode switches 376system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches 377system.cpu0.kern.mode_good::kernel 1157 378system.cpu0.kern.mode_good::user 1158 379system.cpu0.kern.mode_good::idle 0 380system.cpu0.kern.mode_switch_good::kernel 0.163165 # fraction of useful protection mode switches 381system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 382system.cpu0.kern.mode_switch_good::idle no_value # fraction of useful protection mode switches 383system.cpu0.kern.mode_switch_good::total no_value # fraction of useful protection mode switches 384system.cpu0.kern.mode_ticks::kernel 1869378305000 99.95% 99.95% # number of ticks spent at the given mode 385system.cpu0.kern.mode_ticks::user 957009000 0.05% 100.00% # number of ticks spent at the given mode 386system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode 387system.cpu0.kern.swap_context 3763 # number of times the context was actually changed 388system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 389system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 390system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 391system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 392system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 393system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post 394system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 395system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 396system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post 397system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 398system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 399system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post 400system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 401system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 402system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post 403system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 404system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 405system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post 406system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 407system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 408system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post 409system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 410system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 411system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post 412system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 413system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 414system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post 415system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 416system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post 417system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 418system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 419system.cpu0.icache.replacements 884404 # number of replacements 420system.cpu0.icache.tagsinuse 511.244754 # Cycle average of tags in use 421system.cpu0.icache.total_refs 56345132 # Total number of references to valid blocks. 422system.cpu0.icache.sampled_refs 884916 # Sample count of references to valid blocks. 423system.cpu0.icache.avg_refs 63.672859 # Average number of references to valid blocks. 424system.cpu0.icache.warmup_cycle 9786576500 # Cycle when the warmup percentage was hit. 425system.cpu0.icache.occ_blocks::0 511.244754 # Average occupied blocks per context 426system.cpu0.icache.occ_percent::0 0.998525 # Average percentage of cache occupancy 427system.cpu0.icache.ReadReq_hits::0 56345132 # number of ReadReq hits 428system.cpu0.icache.ReadReq_hits::total 56345132 # number of ReadReq hits 429system.cpu0.icache.demand_hits::0 56345132 # number of demand (read+write) hits 430system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits 431system.cpu0.icache.demand_hits::total 56345132 # number of demand (read+write) hits 432system.cpu0.icache.overall_hits::0 56345132 # number of overall hits 433system.cpu0.icache.overall_hits::1 0 # number of overall hits 434system.cpu0.icache.overall_hits::total 56345132 # number of overall hits 435system.cpu0.icache.ReadReq_misses::0 885000 # number of ReadReq misses 436system.cpu0.icache.ReadReq_misses::total 885000 # number of ReadReq misses 437system.cpu0.icache.demand_misses::0 885000 # number of demand (read+write) misses 438system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses 439system.cpu0.icache.demand_misses::total 885000 # number of demand (read+write) misses 440system.cpu0.icache.overall_misses::0 885000 # number of overall misses 441system.cpu0.icache.overall_misses::1 0 # number of overall misses 442system.cpu0.icache.overall_misses::total 885000 # number of overall misses 443system.cpu0.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles 444system.cpu0.icache.overall_miss_latency 0 # number of overall miss cycles 445system.cpu0.icache.ReadReq_accesses::0 57230132 # number of ReadReq accesses(hits+misses) 446system.cpu0.icache.ReadReq_accesses::total 57230132 # number of ReadReq accesses(hits+misses) 447system.cpu0.icache.demand_accesses::0 57230132 # number of demand (read+write) accesses 448system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses 449system.cpu0.icache.demand_accesses::total 57230132 # number of demand (read+write) accesses 450system.cpu0.icache.overall_accesses::0 57230132 # number of overall (read+write) accesses 451system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses 452system.cpu0.icache.overall_accesses::total 57230132 # number of overall (read+write) accesses 453system.cpu0.icache.ReadReq_miss_rate::0 0.015464 # miss rate for ReadReq accesses 454system.cpu0.icache.demand_miss_rate::0 0.015464 # miss rate for demand accesses 455system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses 456system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses 457system.cpu0.icache.overall_miss_rate::0 0.015464 # miss rate for overall accesses 458system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses 459system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses 460system.cpu0.icache.demand_avg_miss_latency::0 0 # average overall miss latency 461system.cpu0.icache.demand_avg_miss_latency::1 no_value # average overall miss latency 462system.cpu0.icache.demand_avg_miss_latency::total no_value # average overall miss latency 463system.cpu0.icache.overall_avg_miss_latency::0 0 # average overall miss latency 464system.cpu0.icache.overall_avg_miss_latency::1 no_value # average overall miss latency 465system.cpu0.icache.overall_avg_miss_latency::total no_value # average overall miss latency 466system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 467system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 468system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 469system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 470system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 471system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 472system.cpu0.icache.fast_writes 0 # number of fast writes performed 473system.cpu0.icache.cache_copies 0 # number of cache copies performed 474system.cpu0.icache.writebacks 95 # number of writebacks 475system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 476system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits 477system.cpu0.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 478system.cpu0.icache.overall_mshr_misses 0 # number of overall MSHR misses 479system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 480system.cpu0.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 481system.cpu0.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 482system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 483system.cpu0.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses 484system.cpu0.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses 485system.cpu0.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses 486system.cpu0.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses 487system.cpu0.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses 488system.cpu0.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses 489system.cpu0.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 490system.cpu0.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 491system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 492system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated 493system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 494system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 495system.cpu0.dcache.replacements 1978962 # number of replacements 496system.cpu0.dcache.tagsinuse 504.827058 # Cycle average of tags in use 497system.cpu0.dcache.total_refs 13123502 # Total number of references to valid blocks. 498system.cpu0.dcache.sampled_refs 1979474 # Sample count of references to valid blocks. 499system.cpu0.dcache.avg_refs 6.629793 # Average number of references to valid blocks. 500system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. 501system.cpu0.dcache.occ_blocks::0 504.827058 # Average occupied blocks per context 502system.cpu0.dcache.occ_percent::0 0.985990 # Average percentage of cache occupancy 503system.cpu0.dcache.ReadReq_hits::0 7298106 # number of ReadReq hits 504system.cpu0.dcache.ReadReq_hits::total 7298106 # number of ReadReq hits 505system.cpu0.dcache.WriteReq_hits::0 5462265 # number of WriteReq hits 506system.cpu0.dcache.WriteReq_hits::total 5462265 # number of WriteReq hits 507system.cpu0.dcache.LoadLockedReq_hits::0 172138 # number of LoadLockedReq hits 508system.cpu0.dcache.LoadLockedReq_hits::total 172138 # number of LoadLockedReq hits 509system.cpu0.dcache.StoreCondReq_hits::0 186635 # number of StoreCondReq hits 510system.cpu0.dcache.StoreCondReq_hits::total 186635 # number of StoreCondReq hits 511system.cpu0.dcache.demand_hits::0 12760371 # number of demand (read+write) hits 512system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits 513system.cpu0.dcache.demand_hits::total 12760371 # number of demand (read+write) hits 514system.cpu0.dcache.overall_hits::0 12760371 # number of overall hits 515system.cpu0.dcache.overall_hits::1 0 # number of overall hits 516system.cpu0.dcache.overall_hits::total 12760371 # number of overall hits 517system.cpu0.dcache.ReadReq_misses::0 1683563 # number of ReadReq misses 518system.cpu0.dcache.ReadReq_misses::total 1683563 # number of ReadReq misses 519system.cpu0.dcache.WriteReq_misses::0 285996 # number of WriteReq misses 520system.cpu0.dcache.WriteReq_misses::total 285996 # number of WriteReq misses 521system.cpu0.dcache.LoadLockedReq_misses::0 16159 # number of LoadLockedReq misses 522system.cpu0.dcache.LoadLockedReq_misses::total 16159 # number of LoadLockedReq misses 523system.cpu0.dcache.StoreCondReq_misses::0 703 # number of StoreCondReq misses 524system.cpu0.dcache.StoreCondReq_misses::total 703 # number of StoreCondReq misses 525system.cpu0.dcache.demand_misses::0 1969559 # number of demand (read+write) misses 526system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses 527system.cpu0.dcache.demand_misses::total 1969559 # number of demand (read+write) misses 528system.cpu0.dcache.overall_misses::0 1969559 # number of overall misses 529system.cpu0.dcache.overall_misses::1 0 # number of overall misses 530system.cpu0.dcache.overall_misses::total 1969559 # number of overall misses 531system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles 532system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles 533system.cpu0.dcache.ReadReq_accesses::0 8981669 # number of ReadReq accesses(hits+misses) 534system.cpu0.dcache.ReadReq_accesses::total 8981669 # number of ReadReq accesses(hits+misses) 535system.cpu0.dcache.WriteReq_accesses::0 5748261 # number of WriteReq accesses(hits+misses) 536system.cpu0.dcache.WriteReq_accesses::total 5748261 # number of WriteReq accesses(hits+misses) 537system.cpu0.dcache.LoadLockedReq_accesses::0 188297 # number of LoadLockedReq accesses(hits+misses) 538system.cpu0.dcache.LoadLockedReq_accesses::total 188297 # number of LoadLockedReq accesses(hits+misses) 539system.cpu0.dcache.StoreCondReq_accesses::0 187338 # number of StoreCondReq accesses(hits+misses) 540system.cpu0.dcache.StoreCondReq_accesses::total 187338 # number of StoreCondReq accesses(hits+misses) 541system.cpu0.dcache.demand_accesses::0 14729930 # number of demand (read+write) accesses 542system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses 543system.cpu0.dcache.demand_accesses::total 14729930 # number of demand (read+write) accesses 544system.cpu0.dcache.overall_accesses::0 14729930 # number of overall (read+write) accesses 545system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses 546system.cpu0.dcache.overall_accesses::total 14729930 # number of overall (read+write) accesses 547system.cpu0.dcache.ReadReq_miss_rate::0 0.187444 # miss rate for ReadReq accesses 548system.cpu0.dcache.WriteReq_miss_rate::0 0.049753 # miss rate for WriteReq accesses 549system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.085817 # miss rate for LoadLockedReq accesses 550system.cpu0.dcache.StoreCondReq_miss_rate::0 0.003753 # miss rate for StoreCondReq accesses 551system.cpu0.dcache.demand_miss_rate::0 0.133711 # miss rate for demand accesses 552system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses 553system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses 554system.cpu0.dcache.overall_miss_rate::0 0.133711 # miss rate for overall accesses 555system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses 556system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses 557system.cpu0.dcache.demand_avg_miss_latency::0 0 # average overall miss latency 558system.cpu0.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency 559system.cpu0.dcache.demand_avg_miss_latency::total no_value # average overall miss latency 560system.cpu0.dcache.overall_avg_miss_latency::0 0 # average overall miss latency 561system.cpu0.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency 562system.cpu0.dcache.overall_avg_miss_latency::total no_value # average overall miss latency 563system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 564system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 565system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 566system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 567system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 568system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 569system.cpu0.dcache.fast_writes 0 # number of fast writes performed 570system.cpu0.dcache.cache_copies 0 # number of cache copies performed 571system.cpu0.dcache.writebacks 771740 # number of writebacks 572system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 573system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits 574system.cpu0.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 575system.cpu0.dcache.overall_mshr_misses 0 # number of overall MSHR misses 576system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 577system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 578system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 579system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 580system.cpu0.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses 581system.cpu0.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses 582system.cpu0.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses 583system.cpu0.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses 584system.cpu0.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses 585system.cpu0.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses 586system.cpu0.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 587system.cpu0.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 588system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 589system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 590system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 591system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 592system.cpu1.dtb.fetch_hits 0 # ITB hits 593system.cpu1.dtb.fetch_misses 0 # ITB misses 594system.cpu1.dtb.fetch_acv 0 # ITB acv 595system.cpu1.dtb.fetch_accesses 0 # ITB accesses 596system.cpu1.dtb.read_hits 1163439 # DTB read hits 597system.cpu1.dtb.read_misses 3277 # DTB read misses 598system.cpu1.dtb.read_acv 58 # DTB read access violations 599system.cpu1.dtb.read_accesses 220342 # DTB read accesses 600system.cpu1.dtb.write_hits 751446 # DTB write hits 601system.cpu1.dtb.write_misses 415 # DTB write misses 602system.cpu1.dtb.write_acv 58 # DTB write access violations 603system.cpu1.dtb.write_accesses 103280 # DTB write accesses 604system.cpu1.dtb.data_hits 1914885 # DTB hits 605system.cpu1.dtb.data_misses 3692 # DTB misses 606system.cpu1.dtb.data_acv 116 # DTB access violations 607system.cpu1.dtb.data_accesses 323622 # DTB accesses 608system.cpu1.itb.fetch_hits 1468399 # ITB hits 609system.cpu1.itb.fetch_misses 1539 # ITB misses 610system.cpu1.itb.fetch_acv 57 # ITB acv 611system.cpu1.itb.fetch_accesses 1469938 # ITB accesses 612system.cpu1.itb.read_hits 0 # DTB read hits 613system.cpu1.itb.read_misses 0 # DTB read misses 614system.cpu1.itb.read_acv 0 # DTB read access violations 615system.cpu1.itb.read_accesses 0 # DTB read accesses 616system.cpu1.itb.write_hits 0 # DTB write hits 617system.cpu1.itb.write_misses 0 # DTB write misses 618system.cpu1.itb.write_acv 0 # DTB write access violations 619system.cpu1.itb.write_accesses 0 # DTB write accesses 620system.cpu1.itb.data_hits 0 # DTB hits 621system.cpu1.itb.data_misses 0 # DTB misses 622system.cpu1.itb.data_acv 0 # DTB access violations 623system.cpu1.itb.data_accesses 0 # DTB accesses 624system.cpu1.numCycles 3740248881 # number of cpu cycles simulated 625system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 626system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 627system.cpu1.num_insts 5931958 # Number of instructions executed 628system.cpu1.num_int_alu_accesses 5550578 # Number of integer alu accesses 629system.cpu1.num_fp_alu_accesses 28590 # Number of float alu accesses 630system.cpu1.num_func_calls 182742 # number of times a function call or return occured 631system.cpu1.num_conditional_control_insts 577190 # number of instructions that are conditional controls 632system.cpu1.num_int_insts 5550578 # number of integer instructions 633system.cpu1.num_fp_insts 28590 # number of float instructions 634system.cpu1.num_int_register_reads 7657288 # number of times the integer registers were read 635system.cpu1.num_int_register_writes 4163275 # number of times the integer registers were written 636system.cpu1.num_fp_register_reads 17889 # number of times the floating registers were read 637system.cpu1.num_fp_register_writes 17683 # number of times the floating registers were written 638system.cpu1.num_mem_refs 1926244 # number of memory refs 639system.cpu1.num_load_insts 1170888 # Number of load instructions 640system.cpu1.num_store_insts 755356 # Number of store instructions 641system.cpu1.num_idle_cycles 3734312190.077655 # Number of idle cycles 642system.cpu1.num_busy_cycles 5936690.922345 # Number of busy cycles 643system.cpu1.not_idle_fraction 0.001587 # Percentage of non-idle cycles 644system.cpu1.idle_fraction 0.998413 # Percentage of idle cycles 645system.cpu1.kern.inst.arm 0 # number of arm instructions executed 646system.cpu1.kern.inst.quiesce 2204 # number of quiesce instructions executed 647system.cpu1.kern.inst.hwrei 39554 # number of hwrei instructions executed 648system.cpu1.kern.ipl_count::0 10328 33.46% 33.46% # number of times we switched to this ipl 649system.cpu1.kern.ipl_count::22 1907 6.18% 39.64% # number of times we switched to this ipl 650system.cpu1.kern.ipl_count::30 110 0.36% 40.00% # number of times we switched to this ipl 651system.cpu1.kern.ipl_count::31 18518 60.00% 100.00% # number of times we switched to this ipl 652system.cpu1.kern.ipl_count::total 30863 # number of times we switched to this ipl 653system.cpu1.kern.ipl_good::0 10318 45.77% 45.77% # number of times we switched to this ipl from a different ipl 654system.cpu1.kern.ipl_good::22 1907 8.46% 54.23% # number of times we switched to this ipl from a different ipl 655system.cpu1.kern.ipl_good::30 110 0.49% 54.72% # number of times we switched to this ipl from a different ipl 656system.cpu1.kern.ipl_good::31 10208 45.28% 100.00% # number of times we switched to this ipl from a different ipl 657system.cpu1.kern.ipl_good::total 22543 # number of times we switched to this ipl from a different ipl 658system.cpu1.kern.ipl_ticks::0 1859123008500 99.41% 99.41% # number of cycles we spent at this ipl 659system.cpu1.kern.ipl_ticks::22 82001000 0.00% 99.42% # number of cycles we spent at this ipl 660system.cpu1.kern.ipl_ticks::30 14064500 0.00% 99.42% # number of cycles we spent at this ipl 661system.cpu1.kern.ipl_ticks::31 10905353000 0.58% 100.00% # number of cycles we spent at this ipl 662system.cpu1.kern.ipl_ticks::total 1870124427000 # number of cycles we spent at this ipl 663system.cpu1.kern.ipl_used::0 0.999032 # fraction of swpipl calls that actually changed the ipl 664system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 665system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 666system.cpu1.kern.ipl_used::31 0.551247 # fraction of swpipl calls that actually changed the ipl 667system.cpu1.kern.syscall::2 2 2.00% 2.00% # number of syscalls executed 668system.cpu1.kern.syscall::3 11 11.00% 13.00% # number of syscalls executed 669system.cpu1.kern.syscall::4 2 2.00% 15.00% # number of syscalls executed 670system.cpu1.kern.syscall::6 10 10.00% 25.00% # number of syscalls executed 671system.cpu1.kern.syscall::17 6 6.00% 31.00% # number of syscalls executed 672system.cpu1.kern.syscall::19 2 2.00% 33.00% # number of syscalls executed 673system.cpu1.kern.syscall::23 2 2.00% 35.00% # number of syscalls executed 674system.cpu1.kern.syscall::24 2 2.00% 37.00% # number of syscalls executed 675system.cpu1.kern.syscall::33 4 4.00% 41.00% # number of syscalls executed 676system.cpu1.kern.syscall::45 17 17.00% 58.00% # number of syscalls executed 677system.cpu1.kern.syscall::47 2 2.00% 60.00% # number of syscalls executed 678system.cpu1.kern.syscall::48 2 2.00% 62.00% # number of syscalls executed 679system.cpu1.kern.syscall::59 3 3.00% 65.00% # number of syscalls executed 680system.cpu1.kern.syscall::71 24 24.00% 89.00% # number of syscalls executed 681system.cpu1.kern.syscall::74 8 8.00% 97.00% # number of syscalls executed 682system.cpu1.kern.syscall::90 1 1.00% 98.00% # number of syscalls executed 683system.cpu1.kern.syscall::132 2 2.00% 100.00% # number of syscalls executed 684system.cpu1.kern.syscall::total 100 # number of syscalls executed 685system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 686system.cpu1.kern.callpal::wripir 8 0.02% 0.03% # number of callpals executed 687system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed 688system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed 689system.cpu1.kern.callpal::swpctx 470 1.46% 1.50% # number of callpals executed 690system.cpu1.kern.callpal::tbi 15 0.05% 1.54% # number of callpals executed 691system.cpu1.kern.callpal::wrent 7 0.02% 1.57% # number of callpals executed 692system.cpu1.kern.callpal::swpipl 26238 81.66% 83.22% # number of callpals executed 693system.cpu1.kern.callpal::rdps 2576 8.02% 91.24% # number of callpals executed 694system.cpu1.kern.callpal::wrkgp 1 0.00% 91.25% # number of callpals executed 695system.cpu1.kern.callpal::wrusp 4 0.01% 91.26% # number of callpals executed 696system.cpu1.kern.callpal::rdusp 2 0.01% 91.26% # number of callpals executed 697system.cpu1.kern.callpal::whami 3 0.01% 91.27% # number of callpals executed 698system.cpu1.kern.callpal::rti 2607 8.11% 99.39% # number of callpals executed 699system.cpu1.kern.callpal::callsys 158 0.49% 99.88% # number of callpals executed 700system.cpu1.kern.callpal::imb 38 0.12% 100.00% # number of callpals executed 701system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed 702system.cpu1.kern.callpal::total 32131 # number of callpals executed 703system.cpu1.kern.mode_switch::kernel 1033 # number of protection mode switches 704system.cpu1.kern.mode_switch::user 580 # number of protection mode switches 705system.cpu1.kern.mode_switch::idle 2046 # number of protection mode switches 706system.cpu1.kern.mode_good::kernel 612 707system.cpu1.kern.mode_good::user 580 708system.cpu1.kern.mode_good::idle 32 709system.cpu1.kern.mode_switch_good::kernel 0.592449 # fraction of useful protection mode switches 710system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 711system.cpu1.kern.mode_switch_good::idle 0.015640 # fraction of useful protection mode switches 712system.cpu1.kern.mode_switch_good::total 1.608089 # fraction of useful protection mode switches 713system.cpu1.kern.mode_ticks::kernel 1373917500 0.07% 0.07% # number of ticks spent at the given mode 714system.cpu1.kern.mode_ticks::user 508289000 0.03% 0.10% # number of ticks spent at the given mode 715system.cpu1.kern.mode_ticks::idle 1868002549000 99.90% 100.00% # number of ticks spent at the given mode 716system.cpu1.kern.swap_context 471 # number of times the context was actually changed 717system.cpu1.icache.replacements 103091 # number of replacements 718system.cpu1.icache.tagsinuse 427.126317 # Cycle average of tags in use 719system.cpu1.icache.total_refs 5832136 # Total number of references to valid blocks. 720system.cpu1.icache.sampled_refs 103603 # Sample count of references to valid blocks. 721system.cpu1.icache.avg_refs 56.293119 # Average number of references to valid blocks. 722system.cpu1.icache.warmup_cycle 1868933059000 # Cycle when the warmup percentage was hit. 723system.cpu1.icache.occ_blocks::0 427.126317 # Average occupied blocks per context 724system.cpu1.icache.occ_percent::0 0.834231 # Average percentage of cache occupancy 725system.cpu1.icache.ReadReq_hits::0 5832136 # number of ReadReq hits 726system.cpu1.icache.ReadReq_hits::total 5832136 # number of ReadReq hits 727system.cpu1.icache.demand_hits::0 5832136 # number of demand (read+write) hits 728system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits 729system.cpu1.icache.demand_hits::total 5832136 # number of demand (read+write) hits 730system.cpu1.icache.overall_hits::0 5832136 # number of overall hits 731system.cpu1.icache.overall_hits::1 0 # number of overall hits 732system.cpu1.icache.overall_hits::total 5832136 # number of overall hits 733system.cpu1.icache.ReadReq_misses::0 103630 # number of ReadReq misses 734system.cpu1.icache.ReadReq_misses::total 103630 # number of ReadReq misses 735system.cpu1.icache.demand_misses::0 103630 # number of demand (read+write) misses 736system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses 737system.cpu1.icache.demand_misses::total 103630 # number of demand (read+write) misses 738system.cpu1.icache.overall_misses::0 103630 # number of overall misses 739system.cpu1.icache.overall_misses::1 0 # number of overall misses 740system.cpu1.icache.overall_misses::total 103630 # number of overall misses 741system.cpu1.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles 742system.cpu1.icache.overall_miss_latency 0 # number of overall miss cycles 743system.cpu1.icache.ReadReq_accesses::0 5935766 # number of ReadReq accesses(hits+misses) 744system.cpu1.icache.ReadReq_accesses::total 5935766 # number of ReadReq accesses(hits+misses) 745system.cpu1.icache.demand_accesses::0 5935766 # number of demand (read+write) accesses 746system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses 747system.cpu1.icache.demand_accesses::total 5935766 # number of demand (read+write) accesses 748system.cpu1.icache.overall_accesses::0 5935766 # number of overall (read+write) accesses 749system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses 750system.cpu1.icache.overall_accesses::total 5935766 # number of overall (read+write) accesses 751system.cpu1.icache.ReadReq_miss_rate::0 0.017459 # miss rate for ReadReq accesses 752system.cpu1.icache.demand_miss_rate::0 0.017459 # miss rate for demand accesses 753system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses 754system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses 755system.cpu1.icache.overall_miss_rate::0 0.017459 # miss rate for overall accesses 756system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses 757system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses 758system.cpu1.icache.demand_avg_miss_latency::0 0 # average overall miss latency 759system.cpu1.icache.demand_avg_miss_latency::1 no_value # average overall miss latency 760system.cpu1.icache.demand_avg_miss_latency::total no_value # average overall miss latency 761system.cpu1.icache.overall_avg_miss_latency::0 0 # average overall miss latency 762system.cpu1.icache.overall_avg_miss_latency::1 no_value # average overall miss latency 763system.cpu1.icache.overall_avg_miss_latency::total no_value # average overall miss latency 764system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 765system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 766system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 767system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 768system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 769system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 770system.cpu1.icache.fast_writes 0 # number of fast writes performed 771system.cpu1.icache.cache_copies 0 # number of cache copies performed 772system.cpu1.icache.writebacks 15 # number of writebacks 773system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 774system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits 775system.cpu1.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 776system.cpu1.icache.overall_mshr_misses 0 # number of overall MSHR misses 777system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 778system.cpu1.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 779system.cpu1.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 780system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 781system.cpu1.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses 782system.cpu1.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses 783system.cpu1.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses 784system.cpu1.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses 785system.cpu1.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses 786system.cpu1.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses 787system.cpu1.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 788system.cpu1.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 789system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 790system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated 791system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 792system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 793system.cpu1.dcache.replacements 62338 # number of replacements 794system.cpu1.dcache.tagsinuse 391.951263 # Cycle average of tags in use 795system.cpu1.dcache.total_refs 1834544 # Total number of references to valid blocks. 796system.cpu1.dcache.sampled_refs 62657 # Sample count of references to valid blocks. 797system.cpu1.dcache.avg_refs 29.279155 # Average number of references to valid blocks. 798system.cpu1.dcache.warmup_cycle 1851267520500 # Cycle when the warmup percentage was hit. 799system.cpu1.dcache.occ_blocks::0 391.951263 # Average occupied blocks per context 800system.cpu1.dcache.occ_percent::0 0.765530 # Average percentage of cache occupancy 801system.cpu1.dcache.ReadReq_hits::0 1109315 # number of ReadReq hits 802system.cpu1.dcache.ReadReq_hits::total 1109315 # number of ReadReq hits 803system.cpu1.dcache.WriteReq_hits::0 707444 # number of WriteReq hits 804system.cpu1.dcache.WriteReq_hits::total 707444 # number of WriteReq hits 805system.cpu1.dcache.LoadLockedReq_hits::0 15129 # number of LoadLockedReq hits 806system.cpu1.dcache.LoadLockedReq_hits::total 15129 # number of LoadLockedReq hits 807system.cpu1.dcache.StoreCondReq_hits::0 15613 # number of StoreCondReq hits 808system.cpu1.dcache.StoreCondReq_hits::total 15613 # number of StoreCondReq hits 809system.cpu1.dcache.demand_hits::0 1816759 # number of demand (read+write) hits 810system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits 811system.cpu1.dcache.demand_hits::total 1816759 # number of demand (read+write) hits 812system.cpu1.dcache.overall_hits::0 1816759 # number of overall hits 813system.cpu1.dcache.overall_hits::1 0 # number of overall hits 814system.cpu1.dcache.overall_hits::total 1816759 # number of overall hits 815system.cpu1.dcache.ReadReq_misses::0 41650 # number of ReadReq misses 816system.cpu1.dcache.ReadReq_misses::total 41650 # number of ReadReq misses 817system.cpu1.dcache.WriteReq_misses::0 25861 # number of WriteReq misses 818system.cpu1.dcache.WriteReq_misses::total 25861 # number of WriteReq misses 819system.cpu1.dcache.LoadLockedReq_misses::0 1289 # number of LoadLockedReq misses 820system.cpu1.dcache.LoadLockedReq_misses::total 1289 # number of LoadLockedReq misses 821system.cpu1.dcache.StoreCondReq_misses::0 732 # number of StoreCondReq misses 822system.cpu1.dcache.StoreCondReq_misses::total 732 # number of StoreCondReq misses 823system.cpu1.dcache.demand_misses::0 67511 # number of demand (read+write) misses 824system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses 825system.cpu1.dcache.demand_misses::total 67511 # number of demand (read+write) misses 826system.cpu1.dcache.overall_misses::0 67511 # number of overall misses 827system.cpu1.dcache.overall_misses::1 0 # number of overall misses 828system.cpu1.dcache.overall_misses::total 67511 # number of overall misses 829system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles 830system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles 831system.cpu1.dcache.ReadReq_accesses::0 1150965 # number of ReadReq accesses(hits+misses) 832system.cpu1.dcache.ReadReq_accesses::total 1150965 # number of ReadReq accesses(hits+misses) 833system.cpu1.dcache.WriteReq_accesses::0 733305 # number of WriteReq accesses(hits+misses) 834system.cpu1.dcache.WriteReq_accesses::total 733305 # number of WriteReq accesses(hits+misses) 835system.cpu1.dcache.LoadLockedReq_accesses::0 16418 # number of LoadLockedReq accesses(hits+misses) 836system.cpu1.dcache.LoadLockedReq_accesses::total 16418 # number of LoadLockedReq accesses(hits+misses) 837system.cpu1.dcache.StoreCondReq_accesses::0 16345 # number of StoreCondReq accesses(hits+misses) 838system.cpu1.dcache.StoreCondReq_accesses::total 16345 # number of StoreCondReq accesses(hits+misses) 839system.cpu1.dcache.demand_accesses::0 1884270 # number of demand (read+write) accesses 840system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses 841system.cpu1.dcache.demand_accesses::total 1884270 # number of demand (read+write) accesses 842system.cpu1.dcache.overall_accesses::0 1884270 # number of overall (read+write) accesses 843system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses 844system.cpu1.dcache.overall_accesses::total 1884270 # number of overall (read+write) accesses 845system.cpu1.dcache.ReadReq_miss_rate::0 0.036187 # miss rate for ReadReq accesses 846system.cpu1.dcache.WriteReq_miss_rate::0 0.035266 # miss rate for WriteReq accesses 847system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.078511 # miss rate for LoadLockedReq accesses 848system.cpu1.dcache.StoreCondReq_miss_rate::0 0.044784 # miss rate for StoreCondReq accesses 849system.cpu1.dcache.demand_miss_rate::0 0.035829 # miss rate for demand accesses 850system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses 851system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses 852system.cpu1.dcache.overall_miss_rate::0 0.035829 # miss rate for overall accesses 853system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses 854system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses 855system.cpu1.dcache.demand_avg_miss_latency::0 0 # average overall miss latency 856system.cpu1.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency 857system.cpu1.dcache.demand_avg_miss_latency::total no_value # average overall miss latency 858system.cpu1.dcache.overall_avg_miss_latency::0 0 # average overall miss latency 859system.cpu1.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency 860system.cpu1.dcache.overall_avg_miss_latency::total no_value # average overall miss latency 861system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 862system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 863system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 864system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 865system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 866system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 867system.cpu1.dcache.fast_writes 0 # number of fast writes performed 868system.cpu1.dcache.cache_copies 0 # number of cache copies performed 869system.cpu1.dcache.writebacks 39996 # number of writebacks 870system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 871system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits 872system.cpu1.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 873system.cpu1.dcache.overall_mshr_misses 0 # number of overall MSHR misses 874system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 875system.cpu1.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 876system.cpu1.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 877system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 878system.cpu1.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses 879system.cpu1.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses 880system.cpu1.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses 881system.cpu1.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses 882system.cpu1.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses 883system.cpu1.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses 884system.cpu1.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 885system.cpu1.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 886system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 887system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 888system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 889system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 890 891---------- End Simulation Statistics ---------- 892