stats.txt revision 11754
12968SN/A 22968SN/A---------- Begin Simulation Statistics ---------- 310409Sandreas.hansson@arm.comsim_seconds 1.869358 # Number of seconds simulated 411754Sandreas.hansson@arm.comsim_ticks 1869358054000 # Number of ticks simulated 511754Sandreas.hansson@arm.comfinal_tick 1869358054000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68721SN/Asim_freq 1000000000000 # Frequency of simulated ticks 711754Sandreas.hansson@arm.comhost_inst_rate 2951277 # Simulator instruction rate (inst/s) 811754Sandreas.hansson@arm.comhost_op_rate 2951276 # Simulator op (including micro ops) rate (op/s) 911754Sandreas.hansson@arm.comhost_tick_rate 84876880961 # Simulator tick rate (ticks/s) 1011754Sandreas.hansson@arm.comhost_mem_usage 336132 # Number of bytes of host memory used 1111754Sandreas.hansson@arm.comhost_seconds 22.02 # Real time elapsed on the host 1211336Sandreas.hansson@arm.comsim_insts 64999904 # Number of instructions simulated 1311336Sandreas.hansson@arm.comsim_ops 64999904 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611754Sandreas.hansson@arm.comsystem.physmem.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states 1711201Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.inst 758272 # Number of bytes read from this memory 1811606Sandreas.sandberg@arm.comsystem.physmem.bytes_read::cpu0.data 66535744 # Number of bytes read from this memory 1911336Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.inst 106112 # Number of bytes read from this memory 2011606Sandreas.sandberg@arm.comsystem.physmem.bytes_read::cpu1.data 766400 # Number of bytes read from this memory 2110352Sandreas.hansson@arm.comsystem.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 2211606Sandreas.sandberg@arm.comsystem.physmem.bytes_read::total 68167488 # Number of bytes read from this memory 2311201Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 758272 # Number of instructions bytes read from this memory 2411336Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 106112 # Number of instructions bytes read from this memory 2511336Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 864384 # Number of instructions bytes read from this memory 2611606Sandreas.sandberg@arm.comsystem.physmem.bytes_written::writebacks 7837888 # Number of bytes written to this memory 2711606Sandreas.sandberg@arm.comsystem.physmem.bytes_written::total 7837888 # Number of bytes written to this memory 2811201Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.inst 11848 # Number of read requests responded to by this memory 2911606Sandreas.sandberg@arm.comsystem.physmem.num_reads::cpu0.data 1039621 # Number of read requests responded to by this memory 3011336Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.inst 1658 # Number of read requests responded to by this memory 3111606Sandreas.sandberg@arm.comsystem.physmem.num_reads::cpu1.data 11975 # Number of read requests responded to by this memory 3210352Sandreas.hansson@arm.comsystem.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory 3311606Sandreas.sandberg@arm.comsystem.physmem.num_reads::total 1065117 # Number of read requests responded to by this memory 3411606Sandreas.sandberg@arm.comsystem.physmem.num_writes::writebacks 122467 # Number of write requests responded to by this memory 3511606Sandreas.sandberg@arm.comsystem.physmem.num_writes::total 122467 # Number of write requests responded to by this memory 3611201Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.inst 405632 # Total read bandwidth from this memory (bytes/s) 3711754Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.data 35592830 # Total read bandwidth from this memory (bytes/s) 3811336Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.inst 56764 # Total read bandwidth from this memory (bytes/s) 3911606Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu1.data 409980 # Total read bandwidth from this memory (bytes/s) 4010409Sandreas.hansson@arm.comsystem.physmem.bw_read::tsunami.ide 514 # Total read bandwidth from this memory (bytes/s) 4111754Sandreas.hansson@arm.comsystem.physmem.bw_read::total 36465720 # Total read bandwidth from this memory (bytes/s) 4211201Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu0.inst 405632 # Instruction read bandwidth from this memory (bytes/s) 4311336Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu1.inst 56764 # Instruction read bandwidth from this memory (bytes/s) 4411336Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 462396 # Instruction read bandwidth from this memory (bytes/s) 4511606Sandreas.sandberg@arm.comsystem.physmem.bw_write::writebacks 4192823 # Write bandwidth from this memory (bytes/s) 4611606Sandreas.sandberg@arm.comsystem.physmem.bw_write::total 4192823 # Write bandwidth from this memory (bytes/s) 4711606Sandreas.sandberg@arm.comsystem.physmem.bw_total::writebacks 4192823 # Total bandwidth to/from this memory (bytes/s) 4811201Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.inst 405632 # Total bandwidth to/from this memory (bytes/s) 4911754Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.data 35592830 # Total bandwidth to/from this memory (bytes/s) 5011336Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.inst 56764 # Total bandwidth to/from this memory (bytes/s) 5111606Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu1.data 409980 # Total bandwidth to/from this memory (bytes/s) 5210585Sandreas.hansson@arm.comsystem.physmem.bw_total::tsunami.ide 514 # Total bandwidth to/from this memory (bytes/s) 5311754Sandreas.hansson@arm.comsystem.physmem.bw_total::total 40658544 # Total bandwidth to/from this memory (bytes/s) 5411754Sandreas.hansson@arm.comsystem.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states 5511754Sandreas.hansson@arm.comsystem.bridge.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states 5610036SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 578721SN/Asystem.cpu0.dtb.fetch_hits 0 # ITB hits 588721SN/Asystem.cpu0.dtb.fetch_misses 0 # ITB misses 598721SN/Asystem.cpu0.dtb.fetch_acv 0 # ITB acv 608721SN/Asystem.cpu0.dtb.fetch_accesses 0 # ITB accesses 6111336Sandreas.hansson@arm.comsystem.cpu0.dtb.read_hits 7758808 # DTB read hits 6210409Sandreas.hansson@arm.comsystem.cpu0.dtb.read_misses 7155 # DTB read misses 638721SN/Asystem.cpu0.dtb.read_acv 152 # DTB read access violations 6410409Sandreas.hansson@arm.comsystem.cpu0.dtb.read_accesses 531148 # DTB read accesses 6511336Sandreas.hansson@arm.comsystem.cpu0.dtb.write_hits 4740251 # DTB write hits 6610409Sandreas.hansson@arm.comsystem.cpu0.dtb.write_misses 732 # DTB write misses 6710409Sandreas.hansson@arm.comsystem.cpu0.dtb.write_acv 102 # DTB write access violations 6810409Sandreas.hansson@arm.comsystem.cpu0.dtb.write_accesses 201714 # DTB write accesses 6911336Sandreas.hansson@arm.comsystem.cpu0.dtb.data_hits 12499059 # DTB hits 7010409Sandreas.hansson@arm.comsystem.cpu0.dtb.data_misses 7887 # DTB misses 7110409Sandreas.hansson@arm.comsystem.cpu0.dtb.data_acv 254 # DTB access violations 7210409Sandreas.hansson@arm.comsystem.cpu0.dtb.data_accesses 732862 # DTB accesses 7311336Sandreas.hansson@arm.comsystem.cpu0.itb.fetch_hits 3525726 # ITB hits 7410409Sandreas.hansson@arm.comsystem.cpu0.itb.fetch_misses 3572 # ITB misses 758721SN/Asystem.cpu0.itb.fetch_acv 127 # ITB acv 7611336Sandreas.hansson@arm.comsystem.cpu0.itb.fetch_accesses 3529298 # ITB accesses 778721SN/Asystem.cpu0.itb.read_hits 0 # DTB read hits 788721SN/Asystem.cpu0.itb.read_misses 0 # DTB read misses 798721SN/Asystem.cpu0.itb.read_acv 0 # DTB read access violations 808721SN/Asystem.cpu0.itb.read_accesses 0 # DTB read accesses 818721SN/Asystem.cpu0.itb.write_hits 0 # DTB write hits 828721SN/Asystem.cpu0.itb.write_misses 0 # DTB write misses 838721SN/Asystem.cpu0.itb.write_acv 0 # DTB write access violations 848721SN/Asystem.cpu0.itb.write_accesses 0 # DTB write accesses 856024SN/Asystem.cpu0.itb.data_hits 0 # DTB hits 866024SN/Asystem.cpu0.itb.data_misses 0 # DTB misses 878721SN/Asystem.cpu0.itb.data_acv 0 # DTB access violations 888721SN/Asystem.cpu0.itb.data_accesses 0 # DTB accesses 8911530Sandreas.sandberg@arm.comsystem.cpu0.numPwrStateTransitions 13588 # Number of power state transitions 9011530Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::samples 6794 # Distribution of time spent in the clock gated state 9111754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::mean 271506712.952752 # Distribution of time spent in the clock gated state 9211754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::stdev 434955679.637595 # Distribution of time spent in the clock gated state 9311530Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::1000-5e+10 6794 100.00% 100.00% # Distribution of time spent in the clock gated state 9411530Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::min_value 21000 # Distribution of time spent in the clock gated state 9511530Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state 9611530Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::total 6794 # Distribution of time spent in the clock gated state 9711530Sandreas.sandberg@arm.comsystem.cpu0.pwrStateResidencyTicks::ON 24741446199 # Cumulative time (in ticks) in various power states 9811754Sandreas.hansson@arm.comsystem.cpu0.pwrStateResidencyTicks::CLK_GATED 1844616607801 # Cumulative time (in ticks) in various power states 9911754Sandreas.hansson@arm.comsystem.cpu0.numCycles 3738722903 # number of cpu cycles simulated 1008721SN/Asystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 1018721SN/Asystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 1022968SN/Asystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 10310409Sandreas.hansson@arm.comsystem.cpu0.kern.inst.quiesce 6794 # number of quiesce instructions executed 10411336Sandreas.hansson@arm.comsystem.cpu0.kern.inst.hwrei 150435 # number of hwrei instructions executed 10510409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::0 51398 40.00% 40.00% # number of times we switched to this ipl 10611336Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::21 243 0.19% 40.19% # number of times we switched to this ipl 10710409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::22 1907 1.48% 41.67% # number of times we switched to this ipl 10810409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::30 514 0.40% 42.07% # number of times we switched to this ipl 10911336Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::31 74446 57.93% 100.00% # number of times we switched to this ipl 11011336Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::total 128508 # number of times we switched to this ipl 11110409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::0 51050 48.97% 48.97% # number of times we switched to this ipl from a different ipl 11210409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::21 243 0.23% 49.20% # number of times we switched to this ipl from a different ipl 11310409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::22 1907 1.83% 51.03% # number of times we switched to this ipl from a different ipl 11410409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::30 514 0.49% 51.52% # number of times we switched to this ipl from a different ipl 11510409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::31 50536 48.48% 100.00% # number of times we switched to this ipl from a different ipl 11610409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::total 104250 # number of times we switched to this ipl from a different ipl 11711754Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::0 1853222787000 99.14% 99.14% # number of cycles we spent at this ipl 11810409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::21 20110000 0.00% 99.14% # number of cycles we spent at this ipl 11910409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::22 82001000 0.00% 99.14% # number of cycles we spent at this ipl 12010409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::30 57621500 0.00% 99.15% # number of cycles we spent at this ipl 12111336Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::31 15975327000 0.85% 100.00% # number of cycles we spent at this ipl 12211754Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::total 1869357846500 # number of cycles we spent at this ipl 12310409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_used::0 0.993229 # fraction of swpipl calls that actually changed the ipl 1246127SN/Asystem.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 1256127SN/Asystem.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 1266127SN/Asystem.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 12711336Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_used::31 0.678828 # fraction of swpipl calls that actually changed the ipl 12811336Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_used::total 0.811234 # fraction of swpipl calls that actually changed the ipl 1298721SN/Asystem.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 13010409Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wripir 616 0.45% 0.45% # number of callpals executed 13110409Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wrmces 1 0.00% 0.45% # number of callpals executed 13210409Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wrfen 1 0.00% 0.46% # number of callpals executed 13310409Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wrvptptr 1 0.00% 0.46% # number of callpals executed 13410409Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::swpctx 2743 2.02% 2.47% # number of callpals executed 13510409Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::tbi 39 0.03% 2.50% # number of callpals executed 13610409Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wrent 7 0.01% 2.51% # number of callpals executed 13711336Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::swpipl 121668 89.51% 92.02% # number of callpals executed 13810409Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::rdps 6149 4.52% 96.54% # number of callpals executed 13910409Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wrkgp 1 0.00% 96.54% # number of callpals executed 14010409Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wrusp 3 0.00% 96.54% # number of callpals executed 14110409Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::rdusp 7 0.01% 96.55% # number of callpals executed 14210409Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::whami 2 0.00% 96.55% # number of callpals executed 14310409Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::rti 4175 3.07% 99.62% # number of callpals executed 14410409Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::callsys 369 0.27% 99.89% # number of callpals executed 14510409Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::imb 146 0.11% 100.00% # number of callpals executed 14611336Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::total 135929 # number of callpals executed 14710409Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch::kernel 6593 # number of protection mode switches 14811336Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch::user 1173 # number of protection mode switches 1498721SN/Asystem.cpu0.kern.mode_switch::idle 0 # number of protection mode switches 15011336Sandreas.hansson@arm.comsystem.cpu0.kern.mode_good::kernel 1172 15111336Sandreas.hansson@arm.comsystem.cpu0.kern.mode_good::user 1173 1528721SN/Asystem.cpu0.kern.mode_good::idle 0 15311336Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch_good::kernel 0.177764 # fraction of useful protection mode switches 1548721SN/Asystem.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 1558983Snate@binkert.orgsystem.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches 15611336Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch_good::total 0.301957 # fraction of useful protection mode switches 15711754Sandreas.hansson@arm.comsystem.cpu0.kern.mode_ticks::kernel 1868349218500 99.95% 99.95% # number of ticks spent at the given mode 15811336Sandreas.hansson@arm.comsystem.cpu0.kern.mode_ticks::user 1008627000 0.05% 100.00% # number of ticks spent at the given mode 1598721SN/Asystem.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode 16010409Sandreas.hansson@arm.comsystem.cpu0.kern.swap_context 2744 # number of times the context was actually changed 16111336Sandreas.hansson@arm.comsystem.cpu0.committedInsts 49477745 # Number of instructions committed 16211336Sandreas.hansson@arm.comsystem.cpu0.committedOps 49477745 # Number of ops (including micro ops) committed 16311336Sandreas.hansson@arm.comsystem.cpu0.num_int_alu_accesses 46201705 # Number of integer alu accesses 16411201Sandreas.hansson@arm.comsystem.cpu0.num_fp_alu_accesses 197598 # Number of float alu accesses 16511336Sandreas.hansson@arm.comsystem.cpu0.num_func_calls 1124633 # number of times a function call or return occured 16611336Sandreas.hansson@arm.comsystem.cpu0.num_conditional_control_insts 6043603 # number of instructions that are conditional controls 16711336Sandreas.hansson@arm.comsystem.cpu0.num_int_insts 46201705 # number of integer instructions 16811201Sandreas.hansson@arm.comsystem.cpu0.num_fp_insts 197598 # number of float instructions 16911336Sandreas.hansson@arm.comsystem.cpu0.num_int_register_reads 64003225 # number of times the integer registers were read 17011336Sandreas.hansson@arm.comsystem.cpu0.num_int_register_writes 34834421 # number of times the integer registers were written 17111201Sandreas.hansson@arm.comsystem.cpu0.num_fp_register_reads 97440 # number of times the floating registers were read 17211201Sandreas.hansson@arm.comsystem.cpu0.num_fp_register_writes 98967 # number of times the floating registers were written 17311336Sandreas.hansson@arm.comsystem.cpu0.num_mem_refs 12536107 # number of memory refs 17411336Sandreas.hansson@arm.comsystem.cpu0.num_load_insts 7783754 # Number of load instructions 17511336Sandreas.hansson@arm.comsystem.cpu0.num_store_insts 4752353 # Number of store instructions 17611754Sandreas.hansson@arm.comsystem.cpu0.num_idle_cycles 3689239920.666412 # Number of idle cycles 17711754Sandreas.hansson@arm.comsystem.cpu0.num_busy_cycles 49482982.333588 # Number of busy cycles 17811201Sandreas.hansson@arm.comsystem.cpu0.not_idle_fraction 0.013235 # Percentage of non-idle cycles 17911201Sandreas.hansson@arm.comsystem.cpu0.idle_fraction 0.986765 # Percentage of idle cycles 18011336Sandreas.hansson@arm.comsystem.cpu0.Branches 7530826 # Number of branches fetched 18111336Sandreas.hansson@arm.comsystem.cpu0.op_class::No_OpClass 2589816 5.23% 5.23% # Class of executed instruction 18211336Sandreas.hansson@arm.comsystem.cpu0.op_class::IntAlu 33436017 67.57% 72.80% # Class of executed instruction 18311336Sandreas.hansson@arm.comsystem.cpu0.op_class::IntMult 50540 0.10% 72.90% # Class of executed instruction 18411201Sandreas.hansson@arm.comsystem.cpu0.op_class::IntDiv 0 0.00% 72.90% # Class of executed instruction 18511201Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatAdd 27840 0.06% 72.96% # Class of executed instruction 18611201Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCmp 0 0.00% 72.96% # Class of executed instruction 18711201Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCvt 0 0.00% 72.96% # Class of executed instruction 18811201Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMult 0 0.00% 72.96% # Class of executed instruction 18911687Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMultAcc 0 0.00% 72.96% # Class of executed instruction 19011201Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatDiv 2233 0.00% 72.96% # Class of executed instruction 19111687Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMisc 0 0.00% 72.96% # Class of executed instruction 19211201Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatSqrt 0 0.00% 72.96% # Class of executed instruction 19311201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAdd 0 0.00% 72.96% # Class of executed instruction 19411201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAddAcc 0 0.00% 72.96% # Class of executed instruction 19511201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAlu 0 0.00% 72.96% # Class of executed instruction 19611201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCmp 0 0.00% 72.96% # Class of executed instruction 19711201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCvt 0 0.00% 72.96% # Class of executed instruction 19811201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMisc 0 0.00% 72.96% # Class of executed instruction 19911201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMult 0 0.00% 72.96% # Class of executed instruction 20011201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMultAcc 0 0.00% 72.96% # Class of executed instruction 20111201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdShift 0 0.00% 72.96% # Class of executed instruction 20211201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdShiftAcc 0 0.00% 72.96% # Class of executed instruction 20311201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdSqrt 0 0.00% 72.96% # Class of executed instruction 20411201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAdd 0 0.00% 72.96% # Class of executed instruction 20511201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAlu 0 0.00% 72.96% # Class of executed instruction 20611201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCmp 0 0.00% 72.96% # Class of executed instruction 20711201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCvt 0 0.00% 72.96% # Class of executed instruction 20811201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatDiv 0 0.00% 72.96% # Class of executed instruction 20911201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMisc 0 0.00% 72.96% # Class of executed instruction 21011201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMult 0 0.00% 72.96% # Class of executed instruction 21111201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMultAcc 0 0.00% 72.96% # Class of executed instruction 21211201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatSqrt 0 0.00% 72.96% # Class of executed instruction 21311687Sandreas.hansson@arm.comsystem.cpu0.op_class::MemRead 7859946 15.88% 88.85% # Class of executed instruction 21411687Sandreas.hansson@arm.comsystem.cpu0.op_class::MemWrite 4676411 9.45% 98.30% # Class of executed instruction 21511687Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMemRead 85644 0.17% 98.47% # Class of executed instruction 21611687Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMemWrite 81881 0.17% 98.63% # Class of executed instruction 21711336Sandreas.hansson@arm.comsystem.cpu0.op_class::IprAccess 675558 1.37% 100.00% # Class of executed instruction 21811201Sandreas.hansson@arm.comsystem.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 21911336Sandreas.hansson@arm.comsystem.cpu0.op_class::total 49485886 # Class of executed instruction 22011754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states 22111502SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.replacements 1781367 # number of replacements 22211754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tagsinuse 506.187332 # Cycle average of tags in use 22311502SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.total_refs 10705767 # Total number of references to valid blocks. 22411502SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.sampled_refs 1781879 # Sample count of references to valid blocks. 22511502SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.avg_refs 6.008134 # Average number of references to valid blocks. 22610585Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. 22711754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.data 506.187332 # Average occupied blocks per requestor 22810585Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.988647 # Average percentage of cache occupancy 22910585Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::total 0.988647 # Average percentage of cache occupancy 23010585Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 23110585Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::0 446 # Occupied blocks per task id 23210585Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id 23310585Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id 23410585Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 23511502SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.tag_accesses 51822038 # Number of tag accesses 23611502SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.data_accesses 51822038 # Number of data accesses 23711754Sandreas.hansson@arm.comsystem.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states 23811502SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 6068885 # number of ReadReq hits 23911502SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_hits::total 6068885 # number of ReadReq hits 24011606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 4360096 # number of WriteReq hits 24111606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_hits::total 4360096 # number of WriteReq hits 24211336Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 127592 # number of LoadLockedReq hits 24311336Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::total 127592 # number of LoadLockedReq hits 24411606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 132871 # number of StoreCondReq hits 24511606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_hits::total 132871 # number of StoreCondReq hits 24611606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 10428981 # number of demand (read+write) hits 24711606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_hits::total 10428981 # number of demand (read+write) hits 24811606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 10428981 # number of overall hits 24911606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_hits::total 10428981 # number of overall hits 25011502SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 1560065 # number of ReadReq misses 25111502SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_misses::total 1560065 # number of ReadReq misses 25211606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 236527 # number of WriteReq misses 25311606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_misses::total 236527 # number of WriteReq misses 25411336Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 12626 # number of LoadLockedReq misses 25511336Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::total 12626 # number of LoadLockedReq misses 25611606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 6899 # number of StoreCondReq misses 25711606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_misses::total 6899 # number of StoreCondReq misses 25811606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 1796592 # number of demand (read+write) misses 25911606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_misses::total 1796592 # number of demand (read+write) misses 26011606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 1796592 # number of overall misses 26111606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_misses::total 1796592 # number of overall misses 26211336Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 7628950 # number of ReadReq accesses(hits+misses) 26311336Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 7628950 # number of ReadReq accesses(hits+misses) 26411336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 4596623 # number of WriteReq accesses(hits+misses) 26511336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 4596623 # number of WriteReq accesses(hits+misses) 26610585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 140218 # number of LoadLockedReq accesses(hits+misses) 26710585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 140218 # number of LoadLockedReq accesses(hits+misses) 26810585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 139770 # number of StoreCondReq accesses(hits+misses) 26910585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::total 139770 # number of StoreCondReq accesses(hits+misses) 27011336Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 12225573 # number of demand (read+write) accesses 27111336Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::total 12225573 # number of demand (read+write) accesses 27211336Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 12225573 # number of overall (read+write) accesses 27311336Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::total 12225573 # number of overall (read+write) accesses 27411336Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.204493 # miss rate for ReadReq accesses 27511336Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.204493 # miss rate for ReadReq accesses 27611606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051457 # miss rate for WriteReq accesses 27711606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.051457 # miss rate for WriteReq accesses 27811336Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.090046 # miss rate for LoadLockedReq accesses 27911336Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.090046 # miss rate for LoadLockedReq accesses 28011606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.049360 # miss rate for StoreCondReq accesses 28111606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.049360 # miss rate for StoreCondReq accesses 28211606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.146954 # miss rate for demand accesses 28311606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.146954 # miss rate for demand accesses 28411606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.146954 # miss rate for overall accesses 28511606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.146954 # miss rate for overall accesses 28610585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 28710585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 28810585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 28910585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 29010585Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 29110585Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 29211606Sandreas.sandberg@arm.comsystem.cpu0.dcache.writebacks::writebacks 633925 # number of writebacks 29311606Sandreas.sandberg@arm.comsystem.cpu0.dcache.writebacks::total 633925 # number of writebacks 29411754Sandreas.hansson@arm.comsystem.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states 29511336Sandreas.hansson@arm.comsystem.cpu0.icache.tags.replacements 618292 # number of replacements 29611336Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tagsinuse 511.240644 # Cycle average of tags in use 29711336Sandreas.hansson@arm.comsystem.cpu0.icache.tags.total_refs 48866947 # Total number of references to valid blocks. 29811336Sandreas.hansson@arm.comsystem.cpu0.icache.tags.sampled_refs 618804 # Sample count of references to valid blocks. 29911336Sandreas.hansson@arm.comsystem.cpu0.icache.tags.avg_refs 78.969992 # Average number of references to valid blocks. 30010409Sandreas.hansson@arm.comsystem.cpu0.icache.tags.warmup_cycle 9786048500 # Cycle when the warmup percentage was hit. 30111336Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 511.240644 # Average occupied blocks per requestor 30210409Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.998517 # Average percentage of cache occupancy 30310409Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::total 0.998517 # Average percentage of cache occupancy 30410036SAli.Saidi@ARM.comsystem.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 30510409Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id 30610409Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::1 116 # Occupied blocks per task id 30710409Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 333 # Occupied blocks per task id 30810036SAli.Saidi@ARM.comsystem.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 30911336Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tag_accesses 50104825 # Number of tag accesses 31011336Sandreas.hansson@arm.comsystem.cpu0.icache.tags.data_accesses 50104825 # Number of data accesses 31111754Sandreas.hansson@arm.comsystem.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states 31211336Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 48866947 # number of ReadReq hits 31311336Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::total 48866947 # number of ReadReq hits 31411336Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 48866947 # number of demand (read+write) hits 31511336Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::total 48866947 # number of demand (read+write) hits 31611336Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 48866947 # number of overall hits 31711336Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::total 48866947 # number of overall hits 31811336Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 618939 # number of ReadReq misses 31911336Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::total 618939 # number of ReadReq misses 32011336Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 618939 # number of demand (read+write) misses 32111336Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::total 618939 # number of demand (read+write) misses 32211336Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 618939 # number of overall misses 32311336Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::total 618939 # number of overall misses 32411336Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 49485886 # number of ReadReq accesses(hits+misses) 32511336Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::total 49485886 # number of ReadReq accesses(hits+misses) 32611336Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 49485886 # number of demand (read+write) accesses 32711336Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::total 49485886 # number of demand (read+write) accesses 32811336Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 49485886 # number of overall (read+write) accesses 32911336Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::total 49485886 # number of overall (read+write) accesses 33010409Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.012507 # miss rate for ReadReq accesses 33110409Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.012507 # miss rate for ReadReq accesses 33210409Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.012507 # miss rate for demand accesses 33310409Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.012507 # miss rate for demand accesses 33410409Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.012507 # miss rate for overall accesses 33510409Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.012507 # miss rate for overall accesses 3368721SN/Asystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 3378721SN/Asystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 3388721SN/Asystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 3398721SN/Asystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 3408983Snate@binkert.orgsystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 3418983Snate@binkert.orgsystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 34211336Sandreas.hansson@arm.comsystem.cpu0.icache.writebacks::writebacks 618292 # number of writebacks 34311336Sandreas.hansson@arm.comsystem.cpu0.icache.writebacks::total 618292 # number of writebacks 3448721SN/Asystem.cpu1.dtb.fetch_hits 0 # ITB hits 3458721SN/Asystem.cpu1.dtb.fetch_misses 0 # ITB misses 3468721SN/Asystem.cpu1.dtb.fetch_acv 0 # ITB acv 3478721SN/Asystem.cpu1.dtb.fetch_accesses 0 # ITB accesses 34811336Sandreas.hansson@arm.comsystem.cpu1.dtb.read_hits 2831559 # DTB read hits 34910409Sandreas.hansson@arm.comsystem.cpu1.dtb.read_misses 3191 # DTB read misses 3508721SN/Asystem.cpu1.dtb.read_acv 58 # DTB read access violations 35110409Sandreas.hansson@arm.comsystem.cpu1.dtb.read_accesses 198160 # DTB read accesses 35210409Sandreas.hansson@arm.comsystem.cpu1.dtb.write_hits 2101673 # DTB write hits 35310409Sandreas.hansson@arm.comsystem.cpu1.dtb.write_misses 412 # DTB write misses 35410409Sandreas.hansson@arm.comsystem.cpu1.dtb.write_acv 55 # DTB write access violations 35510409Sandreas.hansson@arm.comsystem.cpu1.dtb.write_accesses 90619 # DTB write accesses 35611336Sandreas.hansson@arm.comsystem.cpu1.dtb.data_hits 4933232 # DTB hits 35710409Sandreas.hansson@arm.comsystem.cpu1.dtb.data_misses 3603 # DTB misses 35810409Sandreas.hansson@arm.comsystem.cpu1.dtb.data_acv 113 # DTB access violations 35910409Sandreas.hansson@arm.comsystem.cpu1.dtb.data_accesses 288779 # DTB accesses 36010409Sandreas.hansson@arm.comsystem.cpu1.itb.fetch_hits 1950883 # ITB hits 36110409Sandreas.hansson@arm.comsystem.cpu1.itb.fetch_misses 1451 # ITB misses 3628721SN/Asystem.cpu1.itb.fetch_acv 57 # ITB acv 36310409Sandreas.hansson@arm.comsystem.cpu1.itb.fetch_accesses 1952334 # ITB accesses 3648721SN/Asystem.cpu1.itb.read_hits 0 # DTB read hits 3658721SN/Asystem.cpu1.itb.read_misses 0 # DTB read misses 3668721SN/Asystem.cpu1.itb.read_acv 0 # DTB read access violations 3678721SN/Asystem.cpu1.itb.read_accesses 0 # DTB read accesses 3688721SN/Asystem.cpu1.itb.write_hits 0 # DTB write hits 3698721SN/Asystem.cpu1.itb.write_misses 0 # DTB write misses 3708721SN/Asystem.cpu1.itb.write_acv 0 # DTB write access violations 3718721SN/Asystem.cpu1.itb.write_accesses 0 # DTB write accesses 3726024SN/Asystem.cpu1.itb.data_hits 0 # DTB hits 3736024SN/Asystem.cpu1.itb.data_misses 0 # DTB misses 3748721SN/Asystem.cpu1.itb.data_acv 0 # DTB access violations 3758721SN/Asystem.cpu1.itb.data_accesses 0 # DTB accesses 37611530Sandreas.sandberg@arm.comsystem.cpu1.numPwrStateTransitions 5407 # Number of power state transitions 37711530Sandreas.sandberg@arm.comsystem.cpu1.pwrStateClkGateDist::samples 2704 # Distribution of time spent in the clock gated state 37811754Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::mean 688459953.587278 # Distribution of time spent in the clock gated state 37911754Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::stdev 437290552.872181 # Distribution of time spent in the clock gated state 38011530Sandreas.sandberg@arm.comsystem.cpu1.pwrStateClkGateDist::1000-5e+10 2704 100.00% 100.00% # Distribution of time spent in the clock gated state 38111530Sandreas.sandberg@arm.comsystem.cpu1.pwrStateClkGateDist::min_value 400000 # Distribution of time spent in the clock gated state 38211530Sandreas.sandberg@arm.comsystem.cpu1.pwrStateClkGateDist::max_value 976035500 # Distribution of time spent in the clock gated state 38311530Sandreas.sandberg@arm.comsystem.cpu1.pwrStateClkGateDist::total 2704 # Distribution of time spent in the clock gated state 38411530Sandreas.sandberg@arm.comsystem.cpu1.pwrStateResidencyTicks::ON 7762339500 # Cumulative time (in ticks) in various power states 38511754Sandreas.hansson@arm.comsystem.cpu1.pwrStateResidencyTicks::CLK_GATED 1861595714500 # Cumulative time (in ticks) in various power states 38611754Sandreas.hansson@arm.comsystem.cpu1.numCycles 3738296719 # number of cpu cycles simulated 3878721SN/Asystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 3888721SN/Asystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 3892968SN/Asystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 39010409Sandreas.hansson@arm.comsystem.cpu1.kern.inst.quiesce 2704 # number of quiesce instructions executed 39110409Sandreas.hansson@arm.comsystem.cpu1.kern.inst.hwrei 92290 # number of hwrei instructions executed 39210409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::0 31964 39.34% 39.34% # number of times we switched to this ipl 39310409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::22 1906 2.35% 41.68% # number of times we switched to this ipl 39410409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::30 616 0.76% 42.44% # number of times we switched to this ipl 39510409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::31 46769 57.56% 100.00% # number of times we switched to this ipl 39610409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::total 81255 # number of times we switched to this ipl 39710409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::0 30935 48.51% 48.51% # number of times we switched to this ipl from a different ipl 39810409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::22 1906 2.99% 51.49% # number of times we switched to this ipl from a different ipl 39910409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::30 616 0.97% 52.46% # number of times we switched to this ipl from a different ipl 40010409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::31 30319 47.54% 100.00% # number of times we switched to this ipl from a different ipl 40110409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::total 63776 # number of times we switched to this ipl from a different ipl 40211754Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::0 1856123556500 99.30% 99.30% # number of cycles we spent at this ipl 40310409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::22 81958000 0.00% 99.31% # number of cycles we spent at this ipl 40410409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::30 70736500 0.00% 99.31% # number of cycles we spent at this ipl 40511336Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::31 12870743500 0.69% 100.00% # number of cycles we spent at this ipl 40611754Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::total 1869146994500 # number of cycles we spent at this ipl 40710409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_used::0 0.967808 # fraction of swpipl calls that actually changed the ipl 4086127SN/Asystem.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 4096127SN/Asystem.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 41010409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_used::31 0.648271 # fraction of swpipl calls that actually changed the ipl 41110409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_used::total 0.784887 # fraction of swpipl calls that actually changed the ipl 4128721SN/Asystem.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 41310409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wripir 514 0.61% 0.61% # number of callpals executed 41410409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wrmces 1 0.00% 0.61% # number of callpals executed 41510409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wrfen 1 0.00% 0.61% # number of callpals executed 41610409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::swpctx 2506 2.96% 3.58% # number of callpals executed 41710409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::tbi 14 0.02% 3.59% # number of callpals executed 41810409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wrent 7 0.01% 3.60% # number of callpals executed 41910409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::swpipl 74617 88.26% 91.86% # number of callpals executed 42010409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::rdps 2575 3.05% 94.91% # number of callpals executed 42110409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wrkgp 1 0.00% 94.91% # number of callpals executed 42210409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wrusp 4 0.00% 94.91% # number of callpals executed 42310409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::rdusp 2 0.00% 94.91% # number of callpals executed 42410409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::whami 3 0.00% 94.92% # number of callpals executed 42510409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::rti 4115 4.87% 99.79% # number of callpals executed 42610409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::callsys 146 0.17% 99.96% # number of callpals executed 42710409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::imb 34 0.04% 100.00% # number of callpals executed 4288721SN/Asystem.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed 42910409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::total 84542 # number of callpals executed 43010409Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch::kernel 2548 # number of protection mode switches 43110409Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch::user 564 # number of protection mode switches 43210409Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch::idle 3056 # number of protection mode switches 43310409Sandreas.hansson@arm.comsystem.cpu1.kern.mode_good::kernel 1106 43410409Sandreas.hansson@arm.comsystem.cpu1.kern.mode_good::user 564 43510409Sandreas.hansson@arm.comsystem.cpu1.kern.mode_good::idle 542 43610409Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch_good::kernel 0.434066 # fraction of useful protection mode switches 4378721SN/Asystem.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 43810409Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch_good::idle 0.177356 # fraction of useful protection mode switches 43910409Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch_good::total 0.358625 # fraction of useful protection mode switches 44011336Sandreas.hansson@arm.comsystem.cpu1.kern.mode_ticks::kernel 5986368000 0.32% 0.32% # number of ticks spent at the given mode 44110409Sandreas.hansson@arm.comsystem.cpu1.kern.mode_ticks::user 456602000 0.02% 0.34% # number of ticks spent at the given mode 44211754Sandreas.hansson@arm.comsystem.cpu1.kern.mode_ticks::idle 1862102446500 99.66% 100.00% # number of ticks spent at the given mode 44310409Sandreas.hansson@arm.comsystem.cpu1.kern.swap_context 2507 # number of times the context was actually changed 44411336Sandreas.hansson@arm.comsystem.cpu1.committedInsts 15522159 # Number of instructions committed 44511336Sandreas.hansson@arm.comsystem.cpu1.committedOps 15522159 # Number of ops (including micro ops) committed 44611336Sandreas.hansson@arm.comsystem.cpu1.num_int_alu_accesses 14295544 # Number of integer alu accesses 44711201Sandreas.hansson@arm.comsystem.cpu1.num_fp_alu_accesses 198941 # Number of float alu accesses 44811201Sandreas.hansson@arm.comsystem.cpu1.num_func_calls 493140 # number of times a function call or return occured 44911336Sandreas.hansson@arm.comsystem.cpu1.num_conditional_control_insts 1540068 # number of instructions that are conditional controls 45011336Sandreas.hansson@arm.comsystem.cpu1.num_int_insts 14295544 # number of integer instructions 45111201Sandreas.hansson@arm.comsystem.cpu1.num_fp_insts 198941 # number of float instructions 45211336Sandreas.hansson@arm.comsystem.cpu1.num_int_register_reads 19514289 # number of times the integer registers were read 45311336Sandreas.hansson@arm.comsystem.cpu1.num_int_register_writes 10457600 # number of times the integer registers were written 45411201Sandreas.hansson@arm.comsystem.cpu1.num_fp_register_reads 101734 # number of times the floating registers were read 45511201Sandreas.hansson@arm.comsystem.cpu1.num_fp_register_writes 104129 # number of times the floating registers were written 45611336Sandreas.hansson@arm.comsystem.cpu1.num_mem_refs 4961786 # number of memory refs 45711336Sandreas.hansson@arm.comsystem.cpu1.num_load_insts 2849090 # Number of load instructions 45811201Sandreas.hansson@arm.comsystem.cpu1.num_store_insts 2112696 # Number of store instructions 45911754Sandreas.hansson@arm.comsystem.cpu1.num_idle_cycles 3722773781.474732 # Number of idle cycles 46011754Sandreas.hansson@arm.comsystem.cpu1.num_busy_cycles 15522937.525268 # Number of busy cycles 46111201Sandreas.hansson@arm.comsystem.cpu1.not_idle_fraction 0.004152 # Percentage of non-idle cycles 46211201Sandreas.hansson@arm.comsystem.cpu1.idle_fraction 0.995848 # Percentage of idle cycles 46311336Sandreas.hansson@arm.comsystem.cpu1.Branches 2214163 # Number of branches fetched 46411201Sandreas.hansson@arm.comsystem.cpu1.op_class::No_OpClass 856043 5.51% 5.51% # Class of executed instruction 46511336Sandreas.hansson@arm.comsystem.cpu1.op_class::IntAlu 9156766 58.98% 64.49% # Class of executed instruction 46611201Sandreas.hansson@arm.comsystem.cpu1.op_class::IntMult 25065 0.16% 64.65% # Class of executed instruction 46711201Sandreas.hansson@arm.comsystem.cpu1.op_class::IntDiv 0 0.00% 64.65% # Class of executed instruction 46811201Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatAdd 12426 0.08% 64.73% # Class of executed instruction 46911201Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatCmp 0 0.00% 64.73% # Class of executed instruction 47011201Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatCvt 0 0.00% 64.73% # Class of executed instruction 47111201Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatMult 0 0.00% 64.73% # Class of executed instruction 47211687Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatMultAcc 0 0.00% 64.73% # Class of executed instruction 47311201Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatDiv 1409 0.01% 64.74% # Class of executed instruction 47411687Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatMisc 0 0.00% 64.74% # Class of executed instruction 47511201Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatSqrt 0 0.00% 64.74% # Class of executed instruction 47611201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAdd 0 0.00% 64.74% # Class of executed instruction 47711201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAddAcc 0 0.00% 64.74% # Class of executed instruction 47811201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAlu 0 0.00% 64.74% # Class of executed instruction 47911201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdCmp 0 0.00% 64.74% # Class of executed instruction 48011201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdCvt 0 0.00% 64.74% # Class of executed instruction 48111201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMisc 0 0.00% 64.74% # Class of executed instruction 48211201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMult 0 0.00% 64.74% # Class of executed instruction 48311201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMultAcc 0 0.00% 64.74% # Class of executed instruction 48411201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdShift 0 0.00% 64.74% # Class of executed instruction 48511201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdShiftAcc 0 0.00% 64.74% # Class of executed instruction 48611201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdSqrt 0 0.00% 64.74% # Class of executed instruction 48711201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatAdd 0 0.00% 64.74% # Class of executed instruction 48811201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatAlu 0 0.00% 64.74% # Class of executed instruction 48911201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatCmp 0 0.00% 64.74% # Class of executed instruction 49011201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatCvt 0 0.00% 64.74% # Class of executed instruction 49111201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatDiv 0 0.00% 64.74% # Class of executed instruction 49211201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMisc 0 0.00% 64.74% # Class of executed instruction 49311201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMult 0 0.00% 64.74% # Class of executed instruction 49411201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.74% # Class of executed instruction 49511201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.74% # Class of executed instruction 49611687Sandreas.hansson@arm.comsystem.cpu1.op_class::MemRead 2842559 18.31% 83.05% # Class of executed instruction 49711687Sandreas.hansson@arm.comsystem.cpu1.op_class::MemWrite 2023248 13.03% 96.08% # Class of executed instruction 49811687Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatMemRead 94457 0.61% 96.69% # Class of executed instruction 49911687Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatMemWrite 90649 0.58% 97.27% # Class of executed instruction 50011201Sandreas.hansson@arm.comsystem.cpu1.op_class::IprAccess 423253 2.73% 100.00% # Class of executed instruction 50111201Sandreas.hansson@arm.comsystem.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 50211336Sandreas.hansson@arm.comsystem.cpu1.op_class::total 15525875 # Class of executed instruction 50311754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states 50411336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.replacements 201757 # number of replacements 50511754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tagsinuse 497.601957 # Cycle average of tags in use 50611336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.total_refs 4718401 # Total number of references to valid blocks. 50711336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.sampled_refs 202065 # Sample count of references to valid blocks. 50811336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.avg_refs 23.350907 # Average number of references to valid blocks. 50910409Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.warmup_cycle 15869420000 # Cycle when the warmup percentage was hit. 51011754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.data 497.601957 # Average occupied blocks per requestor 51111336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.971879 # Average percentage of cache occupancy 51211336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::total 0.971879 # Average percentage of cache occupancy 51310409Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_task_id_blocks::1024 308 # Occupied blocks per task id 51410409Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::2 306 # Occupied blocks per task id 51510409Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 51610409Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_task_id_percent::1024 0.601562 # Percentage of cache occupancy per task id 51711336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tag_accesses 20020608 # Number of tag accesses 51811336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.data_accesses 20020608 # Number of data accesses 51911754Sandreas.hansson@arm.comsystem.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states 52011336Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 2632688 # number of ReadReq hits 52111336Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::total 2632688 # number of ReadReq hits 52211606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 1954647 # number of WriteReq hits 52311606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_hits::total 1954647 # number of WriteReq hits 52411336Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 61098 # number of LoadLockedReq hits 52511336Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::total 61098 # number of LoadLockedReq hits 52611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 64211 # number of StoreCondReq hits 52711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_hits::total 64211 # number of StoreCondReq hits 52811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 4587335 # number of demand (read+write) hits 52911606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_hits::total 4587335 # number of demand (read+write) hits 53011606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 4587335 # number of overall hits 53111606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_hits::total 4587335 # number of overall hits 53211336Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 140885 # number of ReadReq misses 53311336Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::total 140885 # number of ReadReq misses 53411606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 78313 # number of WriteReq misses 53511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_misses::total 78313 # number of WriteReq misses 53611336Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11000 # number of LoadLockedReq misses 53711336Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::total 11000 # number of LoadLockedReq misses 53811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 7304 # number of StoreCondReq misses 53911606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_misses::total 7304 # number of StoreCondReq misses 54011606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 219198 # number of demand (read+write) misses 54111606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_misses::total 219198 # number of demand (read+write) misses 54211606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 219198 # number of overall misses 54311606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_misses::total 219198 # number of overall misses 54411336Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 2773573 # number of ReadReq accesses(hits+misses) 54511336Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::total 2773573 # number of ReadReq accesses(hits+misses) 54610409Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 2032960 # number of WriteReq accesses(hits+misses) 54710409Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::total 2032960 # number of WriteReq accesses(hits+misses) 54810409Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 72098 # number of LoadLockedReq accesses(hits+misses) 54910409Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 72098 # number of LoadLockedReq accesses(hits+misses) 55010409Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 71515 # number of StoreCondReq accesses(hits+misses) 55110409Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::total 71515 # number of StoreCondReq accesses(hits+misses) 55211336Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::cpu1.data 4806533 # number of demand (read+write) accesses 55311336Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::total 4806533 # number of demand (read+write) accesses 55411336Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::cpu1.data 4806533 # number of overall (read+write) accesses 55511336Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::total 4806533 # number of overall (read+write) accesses 55610409Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.050795 # miss rate for ReadReq accesses 55710409Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.050795 # miss rate for ReadReq accesses 55811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.038522 # miss rate for WriteReq accesses 55911606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.038522 # miss rate for WriteReq accesses 56011336Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.152570 # miss rate for LoadLockedReq accesses 56111336Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.152570 # miss rate for LoadLockedReq accesses 56211606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.102132 # miss rate for StoreCondReq accesses 56311606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.102132 # miss rate for StoreCondReq accesses 56411606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.045604 # miss rate for demand accesses 56511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.045604 # miss rate for demand accesses 56611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.045604 # miss rate for overall accesses 56711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.045604 # miss rate for overall accesses 5688721SN/Asystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 5698721SN/Asystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 5708721SN/Asystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 5718721SN/Asystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 5728983Snate@binkert.orgsystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 5738983Snate@binkert.orgsystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 57411606Sandreas.sandberg@arm.comsystem.cpu1.dcache.writebacks::writebacks 144832 # number of writebacks 57511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.writebacks::total 144832 # number of writebacks 57611754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states 57711336Sandreas.hansson@arm.comsystem.cpu1.icache.tags.replacements 380647 # number of replacements 57811754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tagsinuse 453.133721 # Cycle average of tags in use 57911336Sandreas.hansson@arm.comsystem.cpu1.icache.tags.total_refs 15144687 # Total number of references to valid blocks. 58011336Sandreas.hansson@arm.comsystem.cpu1.icache.tags.sampled_refs 381159 # Sample count of references to valid blocks. 58111336Sandreas.hansson@arm.comsystem.cpu1.icache.tags.avg_refs 39.733253 # Average number of references to valid blocks. 58211754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.warmup_cycle 1859777228500 # Cycle when the warmup percentage was hit. 58311754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 453.133721 # Average occupied blocks per requestor 58410585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.885027 # Average percentage of cache occupancy 58510585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::total 0.885027 # Average percentage of cache occupancy 58610585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 58710585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::2 509 # Occupied blocks per task id 58810585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id 58910585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 59011336Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tag_accesses 15907063 # Number of tag accesses 59111336Sandreas.hansson@arm.comsystem.cpu1.icache.tags.data_accesses 15907063 # Number of data accesses 59211754Sandreas.hansson@arm.comsystem.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states 59311336Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 15144687 # number of ReadReq hits 59411336Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::total 15144687 # number of ReadReq hits 59511336Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::cpu1.inst 15144687 # number of demand (read+write) hits 59611336Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::total 15144687 # number of demand (read+write) hits 59711336Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::cpu1.inst 15144687 # number of overall hits 59811336Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::total 15144687 # number of overall hits 59911336Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 381188 # number of ReadReq misses 60011336Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::total 381188 # number of ReadReq misses 60111336Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::cpu1.inst 381188 # number of demand (read+write) misses 60211336Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::total 381188 # number of demand (read+write) misses 60311336Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::cpu1.inst 381188 # number of overall misses 60411336Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::total 381188 # number of overall misses 60511336Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 15525875 # number of ReadReq accesses(hits+misses) 60611336Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::total 15525875 # number of ReadReq accesses(hits+misses) 60711336Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::cpu1.inst 15525875 # number of demand (read+write) accesses 60811336Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::total 15525875 # number of demand (read+write) accesses 60911336Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::cpu1.inst 15525875 # number of overall (read+write) accesses 61011336Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::total 15525875 # number of overall (read+write) accesses 61111336Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024552 # miss rate for ReadReq accesses 61211336Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.024552 # miss rate for ReadReq accesses 61311336Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.024552 # miss rate for demand accesses 61411336Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::total 0.024552 # miss rate for demand accesses 61511336Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.024552 # miss rate for overall accesses 61611336Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::total 0.024552 # miss rate for overall accesses 61710585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 61810585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 61910585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 62010585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 62110585Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 62210585Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 62311336Sandreas.hansson@arm.comsystem.cpu1.icache.writebacks::writebacks 380647 # number of writebacks 62411336Sandreas.hansson@arm.comsystem.cpu1.icache.writebacks::total 380647 # number of writebacks 62510585Sandreas.hansson@arm.comsystem.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 62610585Sandreas.hansson@arm.comsystem.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 62710585Sandreas.hansson@arm.comsystem.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 62810585Sandreas.hansson@arm.comsystem.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 62910585Sandreas.hansson@arm.comsystem.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 63010585Sandreas.hansson@arm.comsystem.disk0.dma_write_txs 395 # Number of DMA write transactions. 63110585Sandreas.hansson@arm.comsystem.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 63210585Sandreas.hansson@arm.comsystem.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 63310585Sandreas.hansson@arm.comsystem.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 63410585Sandreas.hansson@arm.comsystem.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 63510585Sandreas.hansson@arm.comsystem.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 63610585Sandreas.hansson@arm.comsystem.disk2.dma_write_txs 1 # Number of DMA write transactions. 63711754Sandreas.hansson@arm.comsystem.iobus.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states 63810585Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq 7628 # Transaction distribution 63910585Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp 7628 # Transaction distribution 64010585Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 56140 # Transaction distribution 64110892Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 56140 # Transaction distribution 64210585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14686 # Packet count per connected master and slave (bytes) 64311245Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1014 # Packet count per connected master and slave (bytes) 64410585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 64510585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 64610585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 1076 # Packet count per connected master and slave (bytes) 64710585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18036 # Packet count per connected master and slave (bytes) 64810585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) 64910585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 65010585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 65110585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 44074 # Packet count per connected master and slave (bytes) 65210585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83462 # Packet count per connected master and slave (bytes) 65310585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.tsunami.ide.dma::total 83462 # Packet count per connected master and slave (bytes) 65410585Sandreas.hansson@arm.comsystem.iobus.pkt_count::total 127536 # Packet count per connected master and slave (bytes) 65510585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 58744 # Cumulative packet size per connected master and slave (bytes) 65611245Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2749 # Cumulative packet size per connected master and slave (bytes) 65710585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 65810585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 65910585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 1392 # Cumulative packet size per connected master and slave (bytes) 66010585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9018 # Cumulative packet size per connected master and slave (bytes) 66110585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) 66210585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 66310585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 66410585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::total 86162 # Cumulative packet size per connected master and slave (bytes) 66510585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661656 # Cumulative packet size per connected master and slave (bytes) 66610585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.tsunami.ide.dma::total 2661656 # Cumulative packet size per connected master and slave (bytes) 66710585Sandreas.hansson@arm.comsystem.iobus.pkt_size::total 2747818 # Cumulative packet size per connected master and slave (bytes) 66811754Sandreas.hansson@arm.comsystem.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states 66910585Sandreas.hansson@arm.comsystem.iocache.tags.replacements 41699 # number of replacements 67011336Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 0.434096 # Cycle average of tags in use 67110585Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 0 # Total number of references to valid blocks. 67210585Sandreas.hansson@arm.comsystem.iocache.tags.sampled_refs 41715 # Sample count of references to valid blocks. 67310585Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 67411502SCurtis.Dunham@arm.comsystem.iocache.tags.warmup_cycle 1685787164517 # Cycle when the warmup percentage was hit. 67511336Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::tsunami.ide 0.434096 # Average occupied blocks per requestor 67610585Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::tsunami.ide 0.027131 # Average percentage of cache occupancy 67710585Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.027131 # Average percentage of cache occupancy 67810585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 67910585Sandreas.hansson@arm.comsystem.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 68010585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 68110585Sandreas.hansson@arm.comsystem.iocache.tags.tag_accesses 375579 # Number of tag accesses 68210585Sandreas.hansson@arm.comsystem.iocache.tags.data_accesses 375579 # Number of data accesses 68311754Sandreas.hansson@arm.comsystem.iocache.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states 68410585Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::tsunami.ide 179 # number of ReadReq misses 68510585Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::total 179 # number of ReadReq misses 68610892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 68710892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses 68811456Sandreas.hansson@arm.comsystem.iocache.demand_misses::tsunami.ide 41731 # number of demand (read+write) misses 68911456Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 41731 # number of demand (read+write) misses 69011456Sandreas.hansson@arm.comsystem.iocache.overall_misses::tsunami.ide 41731 # number of overall misses 69111456Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 41731 # number of overall misses 69210585Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::tsunami.ide 179 # number of ReadReq accesses(hits+misses) 69310585Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::total 179 # number of ReadReq accesses(hits+misses) 69410892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) 69510892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) 69611456Sandreas.hansson@arm.comsystem.iocache.demand_accesses::tsunami.ide 41731 # number of demand (read+write) accesses 69711456Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 41731 # number of demand (read+write) accesses 69811456Sandreas.hansson@arm.comsystem.iocache.overall_accesses::tsunami.ide 41731 # number of overall (read+write) accesses 69911456Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 41731 # number of overall (read+write) accesses 70010585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 70110585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 70210892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses 70310892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 70410585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 70510585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 70610585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 70710585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 70810585Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 70910585Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 71010585Sandreas.hansson@arm.comsystem.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 71110585Sandreas.hansson@arm.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 71210585Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 71310585Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 71410585Sandreas.hansson@arm.comsystem.iocache.writebacks::writebacks 41520 # number of writebacks 71510585Sandreas.hansson@arm.comsystem.iocache.writebacks::total 41520 # number of writebacks 71611754Sandreas.hansson@arm.comsystem.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states 71711606Sandreas.sandberg@arm.comsystem.l2c.tags.replacements 999962 # number of replacements 71811754Sandreas.hansson@arm.comsystem.l2c.tags.tagsinuse 65520.418445 # Cycle average of tags in use 71911754Sandreas.hansson@arm.comsystem.l2c.tags.total_refs 4560627 # Total number of references to valid blocks. 72011606Sandreas.sandberg@arm.comsystem.l2c.tags.sampled_refs 1065470 # Sample count of references to valid blocks. 72111754Sandreas.hansson@arm.comsystem.l2c.tags.avg_refs 4.280390 # Average number of references to valid blocks. 72211606Sandreas.sandberg@arm.comsystem.l2c.tags.warmup_cycle 618103500 # Cycle when the warmup percentage was hit. 72311754Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::writebacks 304.654012 # Average occupied blocks per requestor 72411754Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 4865.757484 # Average occupied blocks per requestor 72511754Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.data 58473.870624 # Average occupied blocks per requestor 72611754Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 175.171542 # Average occupied blocks per requestor 72711754Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.data 1700.964784 # Average occupied blocks per requestor 72811606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::writebacks 0.004649 # Average percentage of cache occupancy 72911606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::cpu0.inst 0.074246 # Average percentage of cache occupancy 73011606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::cpu0.data 0.892240 # Average percentage of cache occupancy 73111201Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.inst 0.002673 # Average percentage of cache occupancy 73211606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::cpu1.data 0.025955 # Average percentage of cache occupancy 73311606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::total 0.999762 # Average percentage of cache occupancy 73411606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_task_id_blocks::1024 65508 # Occupied blocks per task id 73511606Sandreas.sandberg@arm.comsystem.l2c.tags.age_task_id_blocks_1024::0 674 # Occupied blocks per task id 73611606Sandreas.sandberg@arm.comsystem.l2c.tags.age_task_id_blocks_1024::1 2411 # Occupied blocks per task id 73711606Sandreas.sandberg@arm.comsystem.l2c.tags.age_task_id_blocks_1024::2 2462 # Occupied blocks per task id 73811606Sandreas.sandberg@arm.comsystem.l2c.tags.age_task_id_blocks_1024::3 9328 # Occupied blocks per task id 73911606Sandreas.sandberg@arm.comsystem.l2c.tags.age_task_id_blocks_1024::4 50633 # Occupied blocks per task id 74011606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_task_id_percent::1024 0.999573 # Percentage of cache occupancy per task id 74111754Sandreas.hansson@arm.comsystem.l2c.tags.tag_accesses 46077150 # Number of tag accesses 74211754Sandreas.hansson@arm.comsystem.l2c.tags.data_accesses 46077150 # Number of data accesses 74311754Sandreas.hansson@arm.comsystem.l2c.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states 74411606Sandreas.sandberg@arm.comsystem.l2c.WritebackDirty_hits::writebacks 778757 # number of WritebackDirty hits 74511606Sandreas.sandberg@arm.comsystem.l2c.WritebackDirty_hits::total 778757 # number of WritebackDirty hits 74611754Sandreas.hansson@arm.comsystem.l2c.WritebackClean_hits::writebacks 721479 # number of WritebackClean hits 74711754Sandreas.hansson@arm.comsystem.l2c.WritebackClean_hits::total 721479 # number of WritebackClean hits 74811606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data 3102 # number of UpgradeReq hits 74911606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_hits::cpu1.data 2744 # number of UpgradeReq hits 75011606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_hits::total 5846 # number of UpgradeReq hits 75111606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_hits::cpu0.data 1187 # number of SCUpgradeReq hits 75211606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_hits::cpu1.data 1121 # number of SCUpgradeReq hits 75311606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_hits::total 2308 # number of SCUpgradeReq hits 75411606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_hits::cpu0.data 111978 # number of ReadExReq hits 75511606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_hits::cpu1.data 56627 # number of ReadExReq hits 75611606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_hits::total 168605 # number of ReadExReq hits 75711336Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_hits::cpu0.inst 607070 # number of ReadCleanReq hits 75811336Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_hits::cpu1.inst 379530 # number of ReadCleanReq hits 75911336Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_hits::total 986600 # number of ReadCleanReq hits 76011606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.data 626251 # number of ReadSharedReq hits 76111606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.data 128790 # number of ReadSharedReq hits 76211606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_hits::total 755041 # number of ReadSharedReq hits 76311336Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.inst 607070 # number of demand (read+write) hits 76411606Sandreas.sandberg@arm.comsystem.l2c.demand_hits::cpu0.data 738229 # number of demand (read+write) hits 76511336Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.inst 379530 # number of demand (read+write) hits 76611606Sandreas.sandberg@arm.comsystem.l2c.demand_hits::cpu1.data 185417 # number of demand (read+write) hits 76711606Sandreas.sandberg@arm.comsystem.l2c.demand_hits::total 1910246 # number of demand (read+write) hits 76811336Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.inst 607070 # number of overall hits 76911606Sandreas.sandberg@arm.comsystem.l2c.overall_hits::cpu0.data 738229 # number of overall hits 77011336Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.inst 379530 # number of overall hits 77111606Sandreas.sandberg@arm.comsystem.l2c.overall_hits::cpu1.data 185417 # number of overall hits 77211606Sandreas.sandberg@arm.comsystem.l2c.overall_hits::total 1910246 # number of overall hits 77311606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_misses::cpu0.data 4 # number of UpgradeReq misses 77411606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_misses::cpu1.data 2 # number of UpgradeReq misses 77511606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_misses::total 6 # number of UpgradeReq misses 77611606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_misses::cpu1.data 1 # number of SCUpgradeReq misses 77711606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses 77811606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_misses::cpu0.data 113307 # number of ReadExReq misses 77911606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_misses::cpu1.data 11044 # number of ReadExReq misses 78011606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_misses::total 124351 # number of ReadExReq misses 78111201Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_misses::cpu0.inst 11848 # number of ReadCleanReq misses 78211336Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_misses::cpu1.inst 1658 # number of ReadCleanReq misses 78311336Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_misses::total 13506 # number of ReadCleanReq misses 78411606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.data 926616 # number of ReadSharedReq misses 78511606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.data 1036 # number of ReadSharedReq misses 78611606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_misses::total 927652 # number of ReadSharedReq misses 78711201Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.inst 11848 # number of demand (read+write) misses 78811606Sandreas.sandberg@arm.comsystem.l2c.demand_misses::cpu0.data 1039923 # number of demand (read+write) misses 78911336Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.inst 1658 # number of demand (read+write) misses 79011606Sandreas.sandberg@arm.comsystem.l2c.demand_misses::cpu1.data 12080 # number of demand (read+write) misses 79111606Sandreas.sandberg@arm.comsystem.l2c.demand_misses::total 1065509 # number of demand (read+write) misses 79211201Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.inst 11848 # number of overall misses 79311606Sandreas.sandberg@arm.comsystem.l2c.overall_misses::cpu0.data 1039923 # number of overall misses 79411336Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.inst 1658 # number of overall misses 79511606Sandreas.sandberg@arm.comsystem.l2c.overall_misses::cpu1.data 12080 # number of overall misses 79611606Sandreas.sandberg@arm.comsystem.l2c.overall_misses::total 1065509 # number of overall misses 79711606Sandreas.sandberg@arm.comsystem.l2c.WritebackDirty_accesses::writebacks 778757 # number of WritebackDirty accesses(hits+misses) 79811606Sandreas.sandberg@arm.comsystem.l2c.WritebackDirty_accesses::total 778757 # number of WritebackDirty accesses(hits+misses) 79911754Sandreas.hansson@arm.comsystem.l2c.WritebackClean_accesses::writebacks 721479 # number of WritebackClean accesses(hits+misses) 80011754Sandreas.hansson@arm.comsystem.l2c.WritebackClean_accesses::total 721479 # number of WritebackClean accesses(hits+misses) 80111606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.data 3106 # number of UpgradeReq accesses(hits+misses) 80211606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.data 2746 # number of UpgradeReq accesses(hits+misses) 80311606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_accesses::total 5852 # number of UpgradeReq accesses(hits+misses) 80411606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data 1187 # number of SCUpgradeReq accesses(hits+misses) 80511606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data 1122 # number of SCUpgradeReq accesses(hits+misses) 80611606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_accesses::total 2309 # number of SCUpgradeReq accesses(hits+misses) 80711606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data 225285 # number of ReadExReq accesses(hits+misses) 80811336Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data 67671 # number of ReadExReq accesses(hits+misses) 80911606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_accesses::total 292956 # number of ReadExReq accesses(hits+misses) 81011336Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_accesses::cpu0.inst 618918 # number of ReadCleanReq accesses(hits+misses) 81111336Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_accesses::cpu1.inst 381188 # number of ReadCleanReq accesses(hits+misses) 81211336Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_accesses::total 1000106 # number of ReadCleanReq accesses(hits+misses) 81311606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.data 1552867 # number of ReadSharedReq accesses(hits+misses) 81411606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.data 129826 # number of ReadSharedReq accesses(hits+misses) 81511606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_accesses::total 1682693 # number of ReadSharedReq accesses(hits+misses) 81611336Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.inst 618918 # number of demand (read+write) accesses 81711606Sandreas.sandberg@arm.comsystem.l2c.demand_accesses::cpu0.data 1778152 # number of demand (read+write) accesses 81811336Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.inst 381188 # number of demand (read+write) accesses 81911606Sandreas.sandberg@arm.comsystem.l2c.demand_accesses::cpu1.data 197497 # number of demand (read+write) accesses 82011606Sandreas.sandberg@arm.comsystem.l2c.demand_accesses::total 2975755 # number of demand (read+write) accesses 82111336Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.inst 618918 # number of overall (read+write) accesses 82211606Sandreas.sandberg@arm.comsystem.l2c.overall_accesses::cpu0.data 1778152 # number of overall (read+write) accesses 82311336Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.inst 381188 # number of overall (read+write) accesses 82411606Sandreas.sandberg@arm.comsystem.l2c.overall_accesses::cpu1.data 197497 # number of overall (read+write) accesses 82511606Sandreas.sandberg@arm.comsystem.l2c.overall_accesses::total 2975755 # number of overall (read+write) accesses 82611606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.001288 # miss rate for UpgradeReq accesses 82711606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.000728 # miss rate for UpgradeReq accesses 82811606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_miss_rate::total 0.001025 # miss rate for UpgradeReq accesses 82911606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.000891 # miss rate for SCUpgradeReq accesses 83011606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.000433 # miss rate for SCUpgradeReq accesses 83111606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.502950 # miss rate for ReadExReq accesses 83211606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 0.163201 # miss rate for ReadExReq accesses 83311606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_miss_rate::total 0.424470 # miss rate for ReadExReq accesses 83411201Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.019143 # miss rate for ReadCleanReq accesses 83511336Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.004350 # miss rate for ReadCleanReq accesses 83611336Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_miss_rate::total 0.013505 # miss rate for ReadCleanReq accesses 83711606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.data 0.596713 # miss rate for ReadSharedReq accesses 83811606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.data 0.007980 # miss rate for ReadSharedReq accesses 83911606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_rate::total 0.551290 # miss rate for ReadSharedReq accesses 84011201Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.inst 0.019143 # miss rate for demand accesses 84111606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_rate::cpu0.data 0.584834 # miss rate for demand accesses 84211336Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.inst 0.004350 # miss rate for demand accesses 84311606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_rate::cpu1.data 0.061165 # miss rate for demand accesses 84411606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_rate::total 0.358063 # miss rate for demand accesses 84511201Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.inst 0.019143 # miss rate for overall accesses 84611606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_rate::cpu0.data 0.584834 # miss rate for overall accesses 84711336Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.inst 0.004350 # miss rate for overall accesses 84811606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_rate::cpu1.data 0.061165 # miss rate for overall accesses 84911606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_rate::total 0.358063 # miss rate for overall accesses 85010585Sandreas.hansson@arm.comsystem.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 85110585Sandreas.hansson@arm.comsystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 85210585Sandreas.hansson@arm.comsystem.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 85310585Sandreas.hansson@arm.comsystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 85410585Sandreas.hansson@arm.comsystem.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 85510585Sandreas.hansson@arm.comsystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 85611606Sandreas.sandberg@arm.comsystem.l2c.writebacks::writebacks 80947 # number of writebacks 85711606Sandreas.sandberg@arm.comsystem.l2c.writebacks::total 80947 # number of writebacks 85811606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.tot_requests 2174394 # Total number of requests made to the snoop filter. 85911754Sandreas.hansson@arm.comsystem.membus.snoop_filter.hit_single_requests 1068314 # Number of requests hitting in the snoop filter with a single holder of the requested data. 86011754Sandreas.hansson@arm.comsystem.membus.snoop_filter.hit_multi_requests 544 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 86111502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 86211502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 86311502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 86411754Sandreas.hansson@arm.comsystem.membus.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states 86510892Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 7449 # Transaction distribution 86611606Sandreas.sandberg@arm.comsystem.membus.trans_dist::ReadResp 948786 # Transaction distribution 86710585Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 14588 # Transaction distribution 86810585Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 14588 # Transaction distribution 86911606Sandreas.sandberg@arm.comsystem.membus.trans_dist::WritebackDirty 122467 # Transaction distribution 87011606Sandreas.sandberg@arm.comsystem.membus.trans_dist::CleanEvict 918018 # Transaction distribution 87111606Sandreas.sandberg@arm.comsystem.membus.trans_dist::UpgradeReq 13880 # Transaction distribution 87211606Sandreas.sandberg@arm.comsystem.membus.trans_dist::SCUpgradeReq 11895 # Transaction distribution 87311606Sandreas.sandberg@arm.comsystem.membus.trans_dist::UpgradeResp 135 # Transaction distribution 87411606Sandreas.sandberg@arm.comsystem.membus.trans_dist::ReadExReq 125245 # Transaction distribution 87511606Sandreas.sandberg@arm.comsystem.membus.trans_dist::ReadExResp 124223 # Transaction distribution 87611606Sandreas.sandberg@arm.comsystem.membus.trans_dist::ReadSharedReq 941337 # Transaction distribution 87710892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateReq 41552 # Transaction distribution 87810892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateResp 41552 # Transaction distribution 87910585Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 44074 # Packet count per connected master and slave (bytes) 88011606Sandreas.sandberg@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3156480 # Packet count per connected master and slave (bytes) 88111606Sandreas.sandberg@arm.comsystem.membus.pkt_count_system.l2c.mem_side::total 3200554 # Packet count per connected master and slave (bytes) 88211336Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 125161 # Packet count per connected master and slave (bytes) 88311336Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 125161 # Packet count per connected master and slave (bytes) 88411606Sandreas.sandberg@arm.comsystem.membus.pkt_count::total 3325715 # Packet count per connected master and slave (bytes) 88510585Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 86162 # Cumulative packet size per connected master and slave (bytes) 88611606Sandreas.sandberg@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.physmem.port 73364992 # Cumulative packet size per connected master and slave (bytes) 88711606Sandreas.sandberg@arm.comsystem.membus.pkt_size_system.l2c.mem_side::total 73451154 # Cumulative packet size per connected master and slave (bytes) 88810892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2668736 # Cumulative packet size per connected master and slave (bytes) 88910892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 2668736 # Cumulative packet size per connected master and slave (bytes) 89011606Sandreas.sandberg@arm.comsystem.membus.pkt_size::total 76119890 # Cumulative packet size per connected master and slave (bytes) 89110585Sandreas.hansson@arm.comsystem.membus.snoops 0 # Total snoops (count) 89211570SCurtis.Dunham@arm.comsystem.membus.snoopTraffic 0 # Total snoop traffic (bytes) 89311606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::samples 2196431 # Request fanout histogram 89411754Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 0.000560 # Request fanout histogram 89511754Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0.023658 # Request fanout histogram 89610585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 89711754Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 2195201 99.94% 99.94% # Request fanout histogram 89811754Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 1230 0.06% 100.00% # Request fanout histogram 89910585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 90010585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 90111502SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 90210585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 90311606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::total 2196431 # Request fanout histogram 90411754Sandreas.hansson@arm.comsystem.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states 90511606Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_filter.tot_requests 6035809 # Total number of requests made to the snoop filter. 90611754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_single_requests 3010644 # Number of requests hitting in the snoop filter with a single holder of the requested data. 90711754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_multi_requests 386637 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 90811754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.tot_snoops 1627 # Total number of snoops made to the snoop filter. 90911754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_single_snoops 1537 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 91011138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_multi_snoops 90 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 91111754Sandreas.hansson@arm.comsystem.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states 91210892Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadReq 7449 # Transaction distribution 91311502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadResp 2732152 # Transaction distribution 91410585Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteReq 14588 # Transaction distribution 91510585Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteResp 14588 # Transaction distribution 91611606Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::WritebackDirty 778757 # Transaction distribution 91711336Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WritebackClean 998939 # Transaction distribution 91811606Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::CleanEvict 1204367 # Transaction distribution 91911606Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::UpgradeReq 19598 # Transaction distribution 92011606Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::SCUpgradeReq 14203 # Transaction distribution 92111606Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::UpgradeResp 33801 # Transaction distribution 92211336Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExReq 295242 # Transaction distribution 92311336Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExResp 295242 # Transaction distribution 92411336Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadCleanReq 1000127 # Transaction distribution 92511502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadSharedReq 1724576 # Transaction distribution 92611336Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1856170 # Packet count per connected master and slave (bytes) 92711606Sandreas.sandberg@arm.comsystem.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5450061 # Packet count per connected master and slave (bytes) 92811336Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1143023 # Packet count per connected master and slave (bytes) 92911606Sandreas.sandberg@arm.comsystem.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 684375 # Packet count per connected master and slave (bytes) 93011606Sandreas.sandberg@arm.comsystem.toL2Bus.pkt_count::total 9133629 # Packet count per connected master and slave (bytes) 93111336Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 79182784 # Cumulative packet size per connected master and slave (bytes) 93211606Sandreas.sandberg@arm.comsystem.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 155817595 # Cumulative packet size per connected master and slave (bytes) 93311336Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 48757440 # Cumulative packet size per connected master and slave (bytes) 93411606Sandreas.sandberg@arm.comsystem.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 23377367 # Cumulative packet size per connected master and slave (bytes) 93511606Sandreas.sandberg@arm.comsystem.toL2Bus.pkt_size::total 307135186 # Cumulative packet size per connected master and slave (bytes) 93611754Sandreas.hansson@arm.comsystem.toL2Bus.snoops 1001076 # Total snoops (count) 93711754Sandreas.hansson@arm.comsystem.toL2Bus.snoopTraffic 5203008 # Total snoop traffic (bytes) 93811754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::samples 7058756 # Request fanout histogram 93911754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::mean 0.107956 # Request fanout histogram 94011754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::stdev 0.310579 # Request fanout histogram 94110585Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 94211754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::0 6297275 89.21% 89.21% # Request fanout histogram 94311754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::1 760929 10.78% 99.99% # Request fanout histogram 94411754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::2 550 0.01% 100.00% # Request fanout histogram 94511138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::3 2 0.00% 100.00% # Request fanout histogram 94611138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram 94710585Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 94811138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 94911138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram 95011754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::total 7058756 # Request fanout histogram 95111754Sandreas.hansson@arm.comsystem.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states 95211754Sandreas.hansson@arm.comsystem.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states 95311754Sandreas.hansson@arm.comsystem.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states 95411754Sandreas.hansson@arm.comsystem.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states 95510585Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 95610585Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 95710585Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 95810585Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 95910585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 96010585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 96110585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 96210585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 96310585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 96410585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 96510585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 96610585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 96710585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 96810585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 96910585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 97010585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 97110585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 97210585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 97310585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 97410585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 97510585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 97610585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 97710585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 97810585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 97910585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 98010585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 98110585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 98210585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 98310585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 98410585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 98510585Sandreas.hansson@arm.comsystem.tsunami.ethernet.droppedPackets 0 # number of packets dropped 98611754Sandreas.hansson@arm.comsystem.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states 98711754Sandreas.hansson@arm.comsystem.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states 98811754Sandreas.hansson@arm.comsystem.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states 98911754Sandreas.hansson@arm.comsystem.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states 99011754Sandreas.hansson@arm.comsystem.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states 99111754Sandreas.hansson@arm.comsystem.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states 99211754Sandreas.hansson@arm.comsystem.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states 99311754Sandreas.hansson@arm.comsystem.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states 99411754Sandreas.hansson@arm.comsystem.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states 99511754Sandreas.hansson@arm.comsystem.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states 99611754Sandreas.hansson@arm.comsystem.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states 99711754Sandreas.hansson@arm.comsystem.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states 99811754Sandreas.hansson@arm.comsystem.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states 99911754Sandreas.hansson@arm.comsystem.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states 100011754Sandreas.hansson@arm.comsystem.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states 100111754Sandreas.hansson@arm.comsystem.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states 100211754Sandreas.hansson@arm.comsystem.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states 100311754Sandreas.hansson@arm.comsystem.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states 100411754Sandreas.hansson@arm.comsystem.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states 100511754Sandreas.hansson@arm.comsystem.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states 100611754Sandreas.hansson@arm.comsystem.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states 100711754Sandreas.hansson@arm.comsystem.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states 100811754Sandreas.hansson@arm.comsystem.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states 10092968SN/A 10102968SN/A---------- End Simulation Statistics ---------- 1011