stats.txt revision 10352
12968SN/A 22968SN/A---------- Begin Simulation Statistics ---------- 310352Sandreas.hansson@arm.comsim_seconds 1.870335 # Number of seconds simulated 410352Sandreas.hansson@arm.comsim_ticks 1870335131500 # Number of ticks simulated 510352Sandreas.hansson@arm.comfinal_tick 1870335131500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68721SN/Asim_freq 1000000000000 # Frequency of simulated ticks 710352Sandreas.hansson@arm.comhost_inst_rate 1824221 # Simulator instruction rate (inst/s) 810352Sandreas.hansson@arm.comhost_op_rate 1824220 # Simulator op (including micro ops) rate (op/s) 910352Sandreas.hansson@arm.comhost_tick_rate 54024573563 # Simulator tick rate (ticks/s) 1010352Sandreas.hansson@arm.comhost_mem_usage 318368 # Number of bytes of host memory used 1110352Sandreas.hansson@arm.comhost_seconds 34.62 # Real time elapsed on the host 1210352Sandreas.hansson@arm.comsim_insts 63154606 # Number of instructions simulated 1310352Sandreas.hansson@arm.comsim_ops 63154606 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1610352Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.inst 761088 # Number of bytes read from this memory 1710352Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.data 66705472 # Number of bytes read from this memory 1810352Sandreas.hansson@arm.comsystem.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 199797Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.inst 110976 # Number of bytes read from this memory 2010352Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.data 674112 # Number of bytes read from this memory 2110352Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 68252608 # Number of bytes read from this memory 2210352Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 761088 # Number of instructions bytes read from this memory 239797Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 110976 # Number of instructions bytes read from this memory 2410352Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 872064 # Number of instructions bytes read from this memory 2510352Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 5204096 # Number of bytes written to this memory 2610352Sandreas.hansson@arm.comsystem.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory 2710352Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 7863424 # Number of bytes written to this memory 2810352Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.inst 11892 # Number of read requests responded to by this memory 2910352Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.data 1042273 # Number of read requests responded to by this memory 3010352Sandreas.hansson@arm.comsystem.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory 319797Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.inst 1734 # Number of read requests responded to by this memory 3210352Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.data 10533 # Number of read requests responded to by this memory 3310352Sandreas.hansson@arm.comsystem.physmem.num_reads::total 1066447 # Number of read requests responded to by this memory 3410352Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 81314 # Number of write requests responded to by this memory 3510352Sandreas.hansson@arm.comsystem.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory 3610352Sandreas.hansson@arm.comsystem.physmem.num_writes::total 122866 # Number of write requests responded to by this memory 3710352Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.inst 406926 # Total read bandwidth from this memory (bytes/s) 3810352Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.data 35664984 # Total read bandwidth from this memory (bytes/s) 3910352Sandreas.hansson@arm.comsystem.physmem.bw_read::tsunami.ide 513 # Total read bandwidth from this memory (bytes/s) 409797Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.inst 59335 # Total read bandwidth from this memory (bytes/s) 4110352Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.data 360423 # Total read bandwidth from this memory (bytes/s) 4210352Sandreas.hansson@arm.comsystem.physmem.bw_read::total 36492181 # Total read bandwidth from this memory (bytes/s) 4310352Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu0.inst 406926 # Instruction read bandwidth from this memory (bytes/s) 449797Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu1.inst 59335 # Instruction read bandwidth from this memory (bytes/s) 4510352Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 466261 # Instruction read bandwidth from this memory (bytes/s) 4610352Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 2782440 # Write bandwidth from this memory (bytes/s) 4710352Sandreas.hansson@arm.comsystem.physmem.bw_write::tsunami.ide 1421846 # Write bandwidth from this memory (bytes/s) 4810352Sandreas.hansson@arm.comsystem.physmem.bw_write::total 4204286 # Write bandwidth from this memory (bytes/s) 4910352Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 2782440 # Total bandwidth to/from this memory (bytes/s) 5010352Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.inst 406926 # Total bandwidth to/from this memory (bytes/s) 5110352Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.data 35664984 # Total bandwidth to/from this memory (bytes/s) 5210352Sandreas.hansson@arm.comsystem.physmem.bw_total::tsunami.ide 1422359 # Total bandwidth to/from this memory (bytes/s) 539797Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.inst 59335 # Total bandwidth to/from this memory (bytes/s) 5410352Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.data 360423 # Total bandwidth to/from this memory (bytes/s) 5510352Sandreas.hansson@arm.comsystem.physmem.bw_total::total 40696467 # Total bandwidth to/from this memory (bytes/s) 5610352Sandreas.hansson@arm.comsystem.membus.throughput 40739369 # Throughput (bytes/s) 5710352Sandreas.hansson@arm.comsystem.membus.data_through_bus 76196274 # Total data (bytes) 589729Sandreas.hansson@arm.comsystem.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 5910036SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 6010352Sandreas.hansson@arm.comsystem.l2c.tags.replacements 1000624 # number of replacements 6110352Sandreas.hansson@arm.comsystem.l2c.tags.tagsinuse 65381.923240 # Cycle average of tags in use 6210352Sandreas.hansson@arm.comsystem.l2c.tags.total_refs 2464778 # Total number of references to valid blocks. 6310352Sandreas.hansson@arm.comsystem.l2c.tags.sampled_refs 1065766 # Sample count of references to valid blocks. 6410352Sandreas.hansson@arm.comsystem.l2c.tags.avg_refs 2.312682 # Average number of references to valid blocks. 659885Sstever@gmail.comsystem.l2c.tags.warmup_cycle 838081000 # Cycle when the warmup percentage was hit. 6610352Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::writebacks 56158.686870 # Average occupied blocks per requestor 6710352Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 4894.230886 # Average occupied blocks per requestor 6810352Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.data 4134.623273 # Average occupied blocks per requestor 6910352Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 174.423683 # Average occupied blocks per requestor 7010352Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.data 19.958527 # Average occupied blocks per requestor 719885Sstever@gmail.comsystem.l2c.tags.occ_percent::writebacks 0.856914 # Average percentage of cache occupancy 729885Sstever@gmail.comsystem.l2c.tags.occ_percent::cpu0.inst 0.074680 # Average percentage of cache occupancy 739885Sstever@gmail.comsystem.l2c.tags.occ_percent::cpu0.data 0.063089 # Average percentage of cache occupancy 749885Sstever@gmail.comsystem.l2c.tags.occ_percent::cpu1.inst 0.002661 # Average percentage of cache occupancy 759885Sstever@gmail.comsystem.l2c.tags.occ_percent::cpu1.data 0.000305 # Average percentage of cache occupancy 769885Sstever@gmail.comsystem.l2c.tags.occ_percent::total 0.997649 # Average percentage of cache occupancy 7710036SAli.Saidi@ARM.comsystem.l2c.tags.occ_task_id_blocks::1024 65142 # Occupied blocks per task id 7810036SAli.Saidi@ARM.comsystem.l2c.tags.age_task_id_blocks_1024::0 769 # Occupied blocks per task id 7910036SAli.Saidi@ARM.comsystem.l2c.tags.age_task_id_blocks_1024::1 3264 # Occupied blocks per task id 8010036SAli.Saidi@ARM.comsystem.l2c.tags.age_task_id_blocks_1024::2 6912 # Occupied blocks per task id 8110352Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::3 6213 # Occupied blocks per task id 8210352Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::4 47984 # Occupied blocks per task id 8310036SAli.Saidi@ARM.comsystem.l2c.tags.occ_task_id_percent::1024 0.993988 # Percentage of cache occupancy per task id 8410352Sandreas.hansson@arm.comsystem.l2c.tags.tag_accesses 32109770 # Number of tag accesses 8510352Sandreas.hansson@arm.comsystem.l2c.tags.data_accesses 32109770 # Number of data accesses 8610352Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu0.inst 873092 # number of ReadReq hits 8710352Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu0.data 763091 # number of ReadReq hits 8810352Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu1.inst 101902 # number of ReadReq hits 8910352Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu1.data 36740 # number of ReadReq hits 9010352Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::total 1774825 # number of ReadReq hits 9110352Sandreas.hansson@arm.comsystem.l2c.Writeback_hits::writebacks 816663 # number of Writeback hits 9210352Sandreas.hansson@arm.comsystem.l2c.Writeback_hits::total 816663 # number of Writeback hits 939797Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data 135 # number of UpgradeReq hits 949134Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_hits::cpu1.data 37 # number of UpgradeReq hits 959797Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::total 172 # number of UpgradeReq hits 969079SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_hits::cpu0.data 14 # number of SCUpgradeReq hits 978835SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_hits::cpu1.data 9 # number of SCUpgradeReq hits 989079SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_hits::total 23 # number of SCUpgradeReq hits 9910352Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu0.data 166232 # number of ReadExReq hits 10010352Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu1.data 14288 # number of ReadExReq hits 10110352Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::total 180520 # number of ReadExReq hits 10210352Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.inst 873092 # number of demand (read+write) hits 10310352Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.data 929323 # number of demand (read+write) hits 10410352Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.inst 101902 # number of demand (read+write) hits 10510352Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.data 51028 # number of demand (read+write) hits 10610352Sandreas.hansson@arm.comsystem.l2c.demand_hits::total 1955345 # number of demand (read+write) hits 10710352Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.inst 873092 # number of overall hits 10810352Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.data 929323 # number of overall hits 10910352Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.inst 101902 # number of overall hits 11010352Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.data 51028 # number of overall hits 11110352Sandreas.hansson@arm.comsystem.l2c.overall_hits::total 1955345 # number of overall hits 11210352Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu0.inst 11892 # number of ReadReq misses 1139797Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu0.data 926761 # number of ReadReq misses 1149797Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu1.inst 1734 # number of ReadReq misses 1159797Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu1.data 908 # number of ReadReq misses 11610352Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::total 941295 # number of ReadReq misses 1179797Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu0.data 2442 # number of UpgradeReq misses 1189797Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu1.data 570 # number of UpgradeReq misses 1199797Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::total 3012 # number of UpgradeReq misses 1209797Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu0.data 65 # number of SCUpgradeReq misses 1219797Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu1.data 100 # number of SCUpgradeReq misses 1229797Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::total 165 # number of SCUpgradeReq misses 1239797Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu0.data 115706 # number of ReadExReq misses 1249797Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu1.data 9662 # number of ReadExReq misses 1259797Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::total 125368 # number of ReadExReq misses 12610352Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.inst 11892 # number of demand (read+write) misses 1279797Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.data 1042467 # number of demand (read+write) misses 1289797Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.inst 1734 # number of demand (read+write) misses 1299797Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.data 10570 # number of demand (read+write) misses 13010352Sandreas.hansson@arm.comsystem.l2c.demand_misses::total 1066663 # number of demand (read+write) misses 13110352Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.inst 11892 # number of overall misses 1329797Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.data 1042467 # number of overall misses 1339797Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.inst 1734 # number of overall misses 1349797Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.data 10570 # number of overall misses 13510352Sandreas.hansson@arm.comsystem.l2c.overall_misses::total 1066663 # number of overall misses 13610352Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu0.inst 884984 # number of ReadReq accesses(hits+misses) 13710352Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu0.data 1689852 # number of ReadReq accesses(hits+misses) 13810352Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu1.inst 103636 # number of ReadReq accesses(hits+misses) 13910352Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu1.data 37648 # number of ReadReq accesses(hits+misses) 14010352Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::total 2716120 # number of ReadReq accesses(hits+misses) 14110352Sandreas.hansson@arm.comsystem.l2c.Writeback_accesses::writebacks 816663 # number of Writeback accesses(hits+misses) 14210352Sandreas.hansson@arm.comsystem.l2c.Writeback_accesses::total 816663 # number of Writeback accesses(hits+misses) 1439797Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.data 2577 # number of UpgradeReq accesses(hits+misses) 1449797Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.data 607 # number of UpgradeReq accesses(hits+misses) 1459797Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::total 3184 # number of UpgradeReq accesses(hits+misses) 1469797Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data 79 # number of SCUpgradeReq accesses(hits+misses) 1479797Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data 109 # number of SCUpgradeReq accesses(hits+misses) 1489797Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::total 188 # number of SCUpgradeReq accesses(hits+misses) 14910352Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data 281938 # number of ReadExReq accesses(hits+misses) 15010352Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data 23950 # number of ReadExReq accesses(hits+misses) 15110352Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::total 305888 # number of ReadExReq accesses(hits+misses) 15210352Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.inst 884984 # number of demand (read+write) accesses 15310352Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.data 1971790 # number of demand (read+write) accesses 15410352Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.inst 103636 # number of demand (read+write) accesses 15510352Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.data 61598 # number of demand (read+write) accesses 15610352Sandreas.hansson@arm.comsystem.l2c.demand_accesses::total 3022008 # number of demand (read+write) accesses 15710352Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.inst 884984 # number of overall (read+write) accesses 15810352Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.data 1971790 # number of overall (read+write) accesses 15910352Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.inst 103636 # number of overall (read+write) accesses 16010352Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.data 61598 # number of overall (read+write) accesses 16110352Sandreas.hansson@arm.comsystem.l2c.overall_accesses::total 3022008 # number of overall (read+write) accesses 16210352Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu0.inst 0.013438 # miss rate for ReadReq accesses 16310352Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu0.data 0.548427 # miss rate for ReadReq accesses 16410352Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu1.inst 0.016732 # miss rate for ReadReq accesses 16510352Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu1.data 0.024118 # miss rate for ReadReq accesses 16610352Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::total 0.346559 # miss rate for ReadReq accesses 1679797Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.947614 # miss rate for UpgradeReq accesses 1689797Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.939044 # miss rate for UpgradeReq accesses 1699797Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::total 0.945980 # miss rate for UpgradeReq accesses 1709797Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.822785 # miss rate for SCUpgradeReq accesses 1719797Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.917431 # miss rate for SCUpgradeReq accesses 1729797Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.877660 # miss rate for SCUpgradeReq accesses 17310352Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.410395 # miss rate for ReadExReq accesses 17410352Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 0.403424 # miss rate for ReadExReq accesses 17510352Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::total 0.409849 # miss rate for ReadExReq accesses 17610352Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.inst 0.013438 # miss rate for demand accesses 17710352Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.data 0.528691 # miss rate for demand accesses 17810352Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.inst 0.016732 # miss rate for demand accesses 17910352Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.data 0.171596 # miss rate for demand accesses 18010352Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::total 0.352965 # miss rate for demand accesses 18110352Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.inst 0.013438 # miss rate for overall accesses 18210352Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.data 0.528691 # miss rate for overall accesses 18310352Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.inst 0.016732 # miss rate for overall accesses 18410352Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.data 0.171596 # miss rate for overall accesses 18510352Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::total 0.352965 # miss rate for overall accesses 1868721SN/Asystem.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1878721SN/Asystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 1888721SN/Asystem.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 1898721SN/Asystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 1908983Snate@binkert.orgsystem.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1918983Snate@binkert.orgsystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1928721SN/Asystem.l2c.fast_writes 0 # number of fast writes performed 1938721SN/Asystem.l2c.cache_copies 0 # number of cache copies performed 19410352Sandreas.hansson@arm.comsystem.l2c.writebacks::writebacks 81314 # number of writebacks 19510352Sandreas.hansson@arm.comsystem.l2c.writebacks::total 81314 # number of writebacks 1968721SN/Asystem.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 1979885Sstever@gmail.comsystem.iocache.tags.replacements 41695 # number of replacements 19810352Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 0.435433 # Cycle average of tags in use 1999885Sstever@gmail.comsystem.iocache.tags.total_refs 0 # Total number of references to valid blocks. 2009885Sstever@gmail.comsystem.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks. 2019885Sstever@gmail.comsystem.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 2029885Sstever@gmail.comsystem.iocache.tags.warmup_cycle 1685787165017 # Cycle when the warmup percentage was hit. 20310352Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::tsunami.ide 0.435433 # Average occupied blocks per requestor 2049885Sstever@gmail.comsystem.iocache.tags.occ_percent::tsunami.ide 0.027215 # Average percentage of cache occupancy 2059885Sstever@gmail.comsystem.iocache.tags.occ_percent::total 0.027215 # Average percentage of cache occupancy 20610036SAli.Saidi@ARM.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 20710036SAli.Saidi@ARM.comsystem.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 20810036SAli.Saidi@ARM.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 20910036SAli.Saidi@ARM.comsystem.iocache.tags.tag_accesses 375543 # Number of tag accesses 21010036SAli.Saidi@ARM.comsystem.iocache.tags.data_accesses 375543 # Number of data accesses 21110352Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits 21210352Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits 2139797Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses 2149797Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::total 175 # number of ReadReq misses 21510352Sandreas.hansson@arm.comsystem.iocache.demand_misses::tsunami.ide 175 # number of demand (read+write) misses 21610352Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 175 # number of demand (read+write) misses 21710352Sandreas.hansson@arm.comsystem.iocache.overall_misses::tsunami.ide 175 # number of overall misses 21810352Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 175 # number of overall misses 2199797Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) 2209797Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) 22110352Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) 22210352Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) 22310352Sandreas.hansson@arm.comsystem.iocache.demand_accesses::tsunami.ide 175 # number of demand (read+write) accesses 22410352Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 175 # number of demand (read+write) accesses 22510352Sandreas.hansson@arm.comsystem.iocache.overall_accesses::tsunami.ide 175 # number of overall (read+write) accesses 22610352Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 175 # number of overall (read+write) accesses 2278835SAli.Saidi@ARM.comsystem.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 2289055Ssaidi@eecs.umich.edusystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2298835SAli.Saidi@ARM.comsystem.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 2309055Ssaidi@eecs.umich.edusystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2318835SAli.Saidi@ARM.comsystem.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 2329055Ssaidi@eecs.umich.edusystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2338721SN/Asystem.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2348721SN/Asystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2358721SN/Asystem.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 2368721SN/Asystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 2378983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2388983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 23910352Sandreas.hansson@arm.comsystem.iocache.fast_writes 41552 # number of fast writes performed 2408721SN/Asystem.iocache.cache_copies 0 # number of cache copies performed 2418721SN/Asystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2428721SN/Asystem.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 2438721SN/Asystem.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 2448721SN/Asystem.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 2458721SN/Asystem.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 2468721SN/Asystem.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 2478721SN/Asystem.disk0.dma_write_txs 395 # Number of DMA write transactions. 2488721SN/Asystem.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 2498721SN/Asystem.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 2508721SN/Asystem.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 2518721SN/Asystem.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 2528721SN/Asystem.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 2538721SN/Asystem.disk2.dma_write_txs 1 # Number of DMA write transactions. 2548721SN/Asystem.cpu0.dtb.fetch_hits 0 # ITB hits 2558721SN/Asystem.cpu0.dtb.fetch_misses 0 # ITB misses 2568721SN/Asystem.cpu0.dtb.fetch_acv 0 # ITB acv 2578721SN/Asystem.cpu0.dtb.fetch_accesses 0 # ITB accesses 25810352Sandreas.hansson@arm.comsystem.cpu0.dtb.read_hits 9154569 # DTB read hits 2598721SN/Asystem.cpu0.dtb.read_misses 7079 # DTB read misses 2608721SN/Asystem.cpu0.dtb.read_acv 152 # DTB read access violations 2618721SN/Asystem.cpu0.dtb.read_accesses 508987 # DTB read accesses 26210352Sandreas.hansson@arm.comsystem.cpu0.dtb.write_hits 5936918 # DTB write hits 2638721SN/Asystem.cpu0.dtb.write_misses 726 # DTB write misses 2648721SN/Asystem.cpu0.dtb.write_acv 99 # DTB write access violations 2658721SN/Asystem.cpu0.dtb.write_accesses 189050 # DTB write accesses 26610352Sandreas.hansson@arm.comsystem.cpu0.dtb.data_hits 15091487 # DTB hits 2676024SN/Asystem.cpu0.dtb.data_misses 7805 # DTB misses 2688721SN/Asystem.cpu0.dtb.data_acv 251 # DTB access violations 2698721SN/Asystem.cpu0.dtb.data_accesses 698037 # DTB accesses 27010352Sandreas.hansson@arm.comsystem.cpu0.itb.fetch_hits 3855534 # ITB hits 2718721SN/Asystem.cpu0.itb.fetch_misses 3485 # ITB misses 2728721SN/Asystem.cpu0.itb.fetch_acv 127 # ITB acv 27310352Sandreas.hansson@arm.comsystem.cpu0.itb.fetch_accesses 3859019 # ITB accesses 2748721SN/Asystem.cpu0.itb.read_hits 0 # DTB read hits 2758721SN/Asystem.cpu0.itb.read_misses 0 # DTB read misses 2768721SN/Asystem.cpu0.itb.read_acv 0 # DTB read access violations 2778721SN/Asystem.cpu0.itb.read_accesses 0 # DTB read accesses 2788721SN/Asystem.cpu0.itb.write_hits 0 # DTB write hits 2798721SN/Asystem.cpu0.itb.write_misses 0 # DTB write misses 2808721SN/Asystem.cpu0.itb.write_acv 0 # DTB write access violations 2818721SN/Asystem.cpu0.itb.write_accesses 0 # DTB write accesses 2826024SN/Asystem.cpu0.itb.data_hits 0 # DTB hits 2836024SN/Asystem.cpu0.itb.data_misses 0 # DTB misses 2848721SN/Asystem.cpu0.itb.data_acv 0 # DTB access violations 2858721SN/Asystem.cpu0.itb.data_accesses 0 # DTB accesses 28610352Sandreas.hansson@arm.comsystem.cpu0.numCycles 3740670264 # number of cpu cycles simulated 2878721SN/Asystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 2888721SN/Asystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 28910352Sandreas.hansson@arm.comsystem.cpu0.committedInsts 57222643 # Number of instructions committed 29010352Sandreas.hansson@arm.comsystem.cpu0.committedOps 57222643 # Number of ops (including micro ops) committed 29110352Sandreas.hansson@arm.comsystem.cpu0.num_int_alu_accesses 53250480 # Number of integer alu accesses 2929797Sandreas.hansson@arm.comsystem.cpu0.num_fp_alu_accesses 299810 # Number of float alu accesses 29310352Sandreas.hansson@arm.comsystem.cpu0.num_func_calls 1399593 # number of times a function call or return occured 29410352Sandreas.hansson@arm.comsystem.cpu0.num_conditional_control_insts 6808341 # number of instructions that are conditional controls 29510352Sandreas.hansson@arm.comsystem.cpu0.num_int_insts 53250480 # number of integer instructions 2969797Sandreas.hansson@arm.comsystem.cpu0.num_fp_insts 299810 # number of float instructions 29710352Sandreas.hansson@arm.comsystem.cpu0.num_int_register_reads 73319539 # number of times the integer registers were read 29810352Sandreas.hansson@arm.comsystem.cpu0.num_int_register_writes 39827957 # number of times the integer registers were written 2999797Sandreas.hansson@arm.comsystem.cpu0.num_fp_register_reads 147724 # number of times the floating registers were read 3009797Sandreas.hansson@arm.comsystem.cpu0.num_fp_register_writes 150835 # number of times the floating registers were written 30110352Sandreas.hansson@arm.comsystem.cpu0.num_mem_refs 15135573 # number of memory refs 30210352Sandreas.hansson@arm.comsystem.cpu0.num_load_insts 9184516 # Number of load instructions 30310352Sandreas.hansson@arm.comsystem.cpu0.num_store_insts 5951057 # Number of store instructions 30410352Sandreas.hansson@arm.comsystem.cpu0.num_idle_cycles 3683435851.584730 # Number of idle cycles 30510352Sandreas.hansson@arm.comsystem.cpu0.num_busy_cycles 57234412.415270 # Number of busy cycles 30610352Sandreas.hansson@arm.comsystem.cpu0.not_idle_fraction 0.015301 # Percentage of non-idle cycles 30710352Sandreas.hansson@arm.comsystem.cpu0.idle_fraction 0.984699 # Percentage of idle cycles 30810352Sandreas.hansson@arm.comsystem.cpu0.Branches 8650822 # Number of branches fetched 30910352Sandreas.hansson@arm.comsystem.cpu0.op_class::No_OpClass 3102524 5.42% 5.42% # Class of executed instruction 31010352Sandreas.hansson@arm.comsystem.cpu0.op_class::IntAlu 37811313 66.07% 71.49% # Class of executed instruction 31110352Sandreas.hansson@arm.comsystem.cpu0.op_class::IntMult 59497 0.10% 71.59% # Class of executed instruction 31210352Sandreas.hansson@arm.comsystem.cpu0.op_class::IntDiv 0 0.00% 71.59% # Class of executed instruction 31310352Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatAdd 30844 0.05% 71.65% # Class of executed instruction 31410220Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCmp 0 0.00% 71.65% # Class of executed instruction 31510220Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCvt 0 0.00% 71.65% # Class of executed instruction 31610220Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMult 0 0.00% 71.65% # Class of executed instruction 31710220Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatDiv 2221 0.00% 71.65% # Class of executed instruction 31810220Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatSqrt 0 0.00% 71.65% # Class of executed instruction 31910220Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAdd 0 0.00% 71.65% # Class of executed instruction 32010220Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAddAcc 0 0.00% 71.65% # Class of executed instruction 32110220Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAlu 0 0.00% 71.65% # Class of executed instruction 32210220Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCmp 0 0.00% 71.65% # Class of executed instruction 32310220Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCvt 0 0.00% 71.65% # Class of executed instruction 32410220Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMisc 0 0.00% 71.65% # Class of executed instruction 32510220Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMult 0 0.00% 71.65% # Class of executed instruction 32610220Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMultAcc 0 0.00% 71.65% # Class of executed instruction 32710220Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdShift 0 0.00% 71.65% # Class of executed instruction 32810220Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdShiftAcc 0 0.00% 71.65% # Class of executed instruction 32910220Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdSqrt 0 0.00% 71.65% # Class of executed instruction 33010220Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAdd 0 0.00% 71.65% # Class of executed instruction 33110220Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAlu 0 0.00% 71.65% # Class of executed instruction 33210220Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCmp 0 0.00% 71.65% # Class of executed instruction 33310220Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCvt 0 0.00% 71.65% # Class of executed instruction 33410220Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatDiv 0 0.00% 71.65% # Class of executed instruction 33510220Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMisc 0 0.00% 71.65% # Class of executed instruction 33610220Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMult 0 0.00% 71.65% # Class of executed instruction 33710220Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.65% # Class of executed instruction 33810220Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.65% # Class of executed instruction 33910352Sandreas.hansson@arm.comsystem.cpu0.op_class::MemRead 9401091 16.43% 88.08% # Class of executed instruction 34010352Sandreas.hansson@arm.comsystem.cpu0.op_class::MemWrite 5957003 10.41% 98.49% # Class of executed instruction 34110352Sandreas.hansson@arm.comsystem.cpu0.op_class::IprAccess 866206 1.51% 100.00% # Class of executed instruction 34210220Sandreas.hansson@arm.comsystem.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 34310352Sandreas.hansson@arm.comsystem.cpu0.op_class::total 57230699 # Class of executed instruction 3442968SN/Asystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 3459797Sandreas.hansson@arm.comsystem.cpu0.kern.inst.quiesce 6283 # number of quiesce instructions executed 34610352Sandreas.hansson@arm.comsystem.cpu0.kern.inst.hwrei 197118 # number of hwrei instructions executed 3479797Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::0 71004 40.60% 40.60% # number of times we switched to this ipl 3486291SN/Asystem.cpu0.kern.ipl_count::21 243 0.14% 40.74% # number of times we switched to this ipl 3496291SN/Asystem.cpu0.kern.ipl_count::22 1908 1.09% 41.83% # number of times we switched to this ipl 3506291SN/Asystem.cpu0.kern.ipl_count::30 8 0.00% 41.84% # number of times we switched to this ipl 35110352Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::31 101703 58.16% 100.00% # number of times we switched to this ipl 35210352Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::total 174866 # number of times we switched to this ipl 3539797Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::0 69637 49.24% 49.24% # number of times we switched to this ipl from a different ipl 3546291SN/Asystem.cpu0.kern.ipl_good::21 243 0.17% 49.41% # number of times we switched to this ipl from a different ipl 3556291SN/Asystem.cpu0.kern.ipl_good::22 1908 1.35% 50.76% # number of times we switched to this ipl from a different ipl 3566291SN/Asystem.cpu0.kern.ipl_good::30 8 0.01% 50.77% # number of times we switched to this ipl from a different ipl 3579797Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::31 69629 49.23% 100.00% # number of times we switched to this ipl from a different ipl 3589797Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::total 141425 # number of times we switched to this ipl from a different ipl 35910352Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::0 1852989089000 99.07% 99.07% # number of cycles we spent at this ipl 3606291SN/Asystem.cpu0.kern.ipl_ticks::21 20110000 0.00% 99.07% # number of cycles we spent at this ipl 3616291SN/Asystem.cpu0.kern.ipl_ticks::22 82044000 0.00% 99.08% # number of cycles we spent at this ipl 3626291SN/Asystem.cpu0.kern.ipl_ticks::30 949500 0.00% 99.08% # number of cycles we spent at this ipl 36310352Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::31 17242731500 0.92% 100.00% # number of cycles we spent at this ipl 36410352Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::total 1870334924000 # number of cycles we spent at this ipl 3659797Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_used::0 0.980748 # fraction of swpipl calls that actually changed the ipl 3666127SN/Asystem.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 3676127SN/Asystem.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 3686127SN/Asystem.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 36910352Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_used::31 0.684631 # fraction of swpipl calls that actually changed the ipl 37010352Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_used::total 0.808762 # fraction of swpipl calls that actually changed the ipl 3716291SN/Asystem.cpu0.kern.syscall::2 6 2.65% 2.65% # number of syscalls executed 3726291SN/Asystem.cpu0.kern.syscall::3 19 8.41% 11.06% # number of syscalls executed 3736291SN/Asystem.cpu0.kern.syscall::4 2 0.88% 11.95% # number of syscalls executed 3746291SN/Asystem.cpu0.kern.syscall::6 32 14.16% 26.11% # number of syscalls executed 3756291SN/Asystem.cpu0.kern.syscall::12 1 0.44% 26.55% # number of syscalls executed 3766291SN/Asystem.cpu0.kern.syscall::15 1 0.44% 26.99% # number of syscalls executed 3776291SN/Asystem.cpu0.kern.syscall::17 9 3.98% 30.97% # number of syscalls executed 3786291SN/Asystem.cpu0.kern.syscall::19 8 3.54% 34.51% # number of syscalls executed 3796291SN/Asystem.cpu0.kern.syscall::20 6 2.65% 37.17% # number of syscalls executed 3806291SN/Asystem.cpu0.kern.syscall::23 2 0.88% 38.05% # number of syscalls executed 3816291SN/Asystem.cpu0.kern.syscall::24 4 1.77% 39.82% # number of syscalls executed 3826291SN/Asystem.cpu0.kern.syscall::33 7 3.10% 42.92% # number of syscalls executed 3836291SN/Asystem.cpu0.kern.syscall::41 2 0.88% 43.81% # number of syscalls executed 3846291SN/Asystem.cpu0.kern.syscall::45 37 16.37% 60.18% # number of syscalls executed 3856291SN/Asystem.cpu0.kern.syscall::47 4 1.77% 61.95% # number of syscalls executed 3866291SN/Asystem.cpu0.kern.syscall::48 8 3.54% 65.49% # number of syscalls executed 3876291SN/Asystem.cpu0.kern.syscall::54 10 4.42% 69.91% # number of syscalls executed 3886291SN/Asystem.cpu0.kern.syscall::58 1 0.44% 70.35% # number of syscalls executed 3896291SN/Asystem.cpu0.kern.syscall::59 4 1.77% 72.12% # number of syscalls executed 3906291SN/Asystem.cpu0.kern.syscall::71 30 13.27% 85.40% # number of syscalls executed 3916291SN/Asystem.cpu0.kern.syscall::73 3 1.33% 86.73% # number of syscalls executed 3926291SN/Asystem.cpu0.kern.syscall::74 8 3.54% 90.27% # number of syscalls executed 3936291SN/Asystem.cpu0.kern.syscall::87 1 0.44% 90.71% # number of syscalls executed 3946291SN/Asystem.cpu0.kern.syscall::90 2 0.88% 91.59% # number of syscalls executed 3956291SN/Asystem.cpu0.kern.syscall::92 9 3.98% 95.58% # number of syscalls executed 3966291SN/Asystem.cpu0.kern.syscall::97 2 0.88% 96.46% # number of syscalls executed 3976291SN/Asystem.cpu0.kern.syscall::98 2 0.88% 97.35% # number of syscalls executed 3986291SN/Asystem.cpu0.kern.syscall::132 2 0.88% 98.23% # number of syscalls executed 3996291SN/Asystem.cpu0.kern.syscall::144 2 0.88% 99.12% # number of syscalls executed 4006291SN/Asystem.cpu0.kern.syscall::147 2 0.88% 100.00% # number of syscalls executed 4016127SN/Asystem.cpu0.kern.syscall::total 226 # number of syscalls executed 4028721SN/Asystem.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 4039797Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wripir 110 0.06% 0.06% # number of callpals executed 4048721SN/Asystem.cpu0.kern.callpal::wrmces 1 0.00% 0.06% # number of callpals executed 4058721SN/Asystem.cpu0.kern.callpal::wrfen 1 0.00% 0.06% # number of callpals executed 4068721SN/Asystem.cpu0.kern.callpal::wrvptptr 1 0.00% 0.06% # number of callpals executed 4079797Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::swpctx 3762 2.05% 2.11% # number of callpals executed 4088721SN/Asystem.cpu0.kern.callpal::tbi 38 0.02% 2.14% # number of callpals executed 4098721SN/Asystem.cpu0.kern.callpal::wrent 7 0.00% 2.14% # number of callpals executed 41010352Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::swpipl 168033 91.68% 93.82% # number of callpals executed 4119797Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::rdps 6150 3.36% 97.17% # number of callpals executed 4128721SN/Asystem.cpu0.kern.callpal::wrkgp 1 0.00% 97.17% # number of callpals executed 4138721SN/Asystem.cpu0.kern.callpal::wrusp 3 0.00% 97.17% # number of callpals executed 4149797Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::rdusp 7 0.00% 97.18% # number of callpals executed 4158721SN/Asystem.cpu0.kern.callpal::whami 2 0.00% 97.18% # number of callpals executed 4168721SN/Asystem.cpu0.kern.callpal::rti 4673 2.55% 99.73% # number of callpals executed 4178721SN/Asystem.cpu0.kern.callpal::callsys 357 0.19% 99.92% # number of callpals executed 4188721SN/Asystem.cpu0.kern.callpal::imb 142 0.08% 100.00% # number of callpals executed 41910352Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::total 183289 # number of callpals executed 4209797Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch::kernel 7091 # number of protection mode switches 42110352Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch::user 1156 # number of protection mode switches 4228721SN/Asystem.cpu0.kern.mode_switch::idle 0 # number of protection mode switches 42310352Sandreas.hansson@arm.comsystem.cpu0.kern.mode_good::kernel 1155 42410352Sandreas.hansson@arm.comsystem.cpu0.kern.mode_good::user 1156 4258721SN/Asystem.cpu0.kern.mode_good::idle 0 42610352Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch_good::kernel 0.162883 # fraction of useful protection mode switches 4278721SN/Asystem.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 4288983Snate@binkert.orgsystem.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches 42910352Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch_good::total 0.280223 # fraction of useful protection mode switches 43010352Sandreas.hansson@arm.comsystem.cpu0.kern.mode_ticks::kernel 1869377924000 99.95% 99.95% # number of ticks spent at the given mode 43110352Sandreas.hansson@arm.comsystem.cpu0.kern.mode_ticks::user 956999000 0.05% 100.00% # number of ticks spent at the given mode 4328721SN/Asystem.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode 4339797Sandreas.hansson@arm.comsystem.cpu0.kern.swap_context 3763 # number of times the context was actually changed 4348721SN/Asystem.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 4358721SN/Asystem.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 4368721SN/Asystem.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 4378721SN/Asystem.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 4388721SN/Asystem.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 4398983Snate@binkert.orgsystem.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 4408721SN/Asystem.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 4418721SN/Asystem.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 4428983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 4438721SN/Asystem.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 4448721SN/Asystem.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 4458983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 4468721SN/Asystem.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 4478721SN/Asystem.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 4488983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 4498721SN/Asystem.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 4508721SN/Asystem.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 4518983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 4528721SN/Asystem.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 4538721SN/Asystem.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 4548983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 4558721SN/Asystem.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 4568721SN/Asystem.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 4578983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 4588721SN/Asystem.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 4598721SN/Asystem.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 4608983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 4618721SN/Asystem.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 4628983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 4638721SN/Asystem.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 4648721SN/Asystem.tsunami.ethernet.droppedPackets 0 # number of packets dropped 46510352Sandreas.hansson@arm.comsystem.toL2Bus.throughput 133353257 # Throughput (bytes/s) 46610352Sandreas.hansson@arm.comsystem.toL2Bus.data_through_bus 246745714 # Total data (bytes) 46710352Sandreas.hansson@arm.comsystem.toL2Bus.snoop_data_through_bus 2669568 # Total snoop data (bytes) 4689962Sandreas.hansson@arm.comsystem.iobus.throughput 1460501 # Throughput (bytes/s) 4699797Sandreas.hansson@arm.comsystem.iobus.data_through_bus 2731626 # Total data (bytes) 47010352Sandreas.hansson@arm.comsystem.cpu0.icache.tags.replacements 884408 # number of replacements 47110352Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tagsinuse 511.244752 # Cycle average of tags in use 47210352Sandreas.hansson@arm.comsystem.cpu0.icache.tags.total_refs 56345695 # Total number of references to valid blocks. 47310352Sandreas.hansson@arm.comsystem.cpu0.icache.tags.sampled_refs 884920 # Sample count of references to valid blocks. 47410352Sandreas.hansson@arm.comsystem.cpu0.icache.tags.avg_refs 63.673208 # Average number of references to valid blocks. 4759885Sstever@gmail.comsystem.cpu0.icache.tags.warmup_cycle 9786576500 # Cycle when the warmup percentage was hit. 47610352Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 511.244752 # Average occupied blocks per requestor 4779797Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.998525 # Average percentage of cache occupancy 4789885Sstever@gmail.comsystem.cpu0.icache.tags.occ_percent::total 0.998525 # Average percentage of cache occupancy 47910036SAli.Saidi@ARM.comsystem.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 48010036SAli.Saidi@ARM.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id 48110036SAli.Saidi@ARM.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id 48210036SAli.Saidi@ARM.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 345 # Occupied blocks per task id 48310036SAli.Saidi@ARM.comsystem.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 48410352Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tag_accesses 58115703 # Number of tag accesses 48510352Sandreas.hansson@arm.comsystem.cpu0.icache.tags.data_accesses 58115703 # Number of data accesses 48610352Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 56345695 # number of ReadReq hits 48710352Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::total 56345695 # number of ReadReq hits 48810352Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 56345695 # number of demand (read+write) hits 48910352Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::total 56345695 # number of demand (read+write) hits 49010352Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 56345695 # number of overall hits 49110352Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::total 56345695 # number of overall hits 49210352Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 885004 # number of ReadReq misses 49310352Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::total 885004 # number of ReadReq misses 49410352Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 885004 # number of demand (read+write) misses 49510352Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::total 885004 # number of demand (read+write) misses 49610352Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 885004 # number of overall misses 49710352Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::total 885004 # number of overall misses 49810352Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 57230699 # number of ReadReq accesses(hits+misses) 49910352Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::total 57230699 # number of ReadReq accesses(hits+misses) 50010352Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 57230699 # number of demand (read+write) accesses 50110352Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::total 57230699 # number of demand (read+write) accesses 50210352Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 57230699 # number of overall (read+write) accesses 50310352Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::total 57230699 # number of overall (read+write) accesses 5049797Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015464 # miss rate for ReadReq accesses 5059797Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.015464 # miss rate for ReadReq accesses 5069797Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.015464 # miss rate for demand accesses 5079797Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.015464 # miss rate for demand accesses 5089797Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.015464 # miss rate for overall accesses 5099797Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.015464 # miss rate for overall accesses 5108721SN/Asystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 5118721SN/Asystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 5128721SN/Asystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 5138721SN/Asystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 5148983Snate@binkert.orgsystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 5158983Snate@binkert.orgsystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 5168721SN/Asystem.cpu0.icache.fast_writes 0 # number of fast writes performed 5178721SN/Asystem.cpu0.icache.cache_copies 0 # number of cache copies performed 5188721SN/Asystem.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 51910352Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.replacements 1978697 # number of replacements 52010352Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tagsinuse 507.129647 # Cycle average of tags in use 52110352Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.total_refs 13123800 # Total number of references to valid blocks. 52210352Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.sampled_refs 1979209 # Sample count of references to valid blocks. 52310352Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.avg_refs 6.630831 # Average number of references to valid blocks. 5249885Sstever@gmail.comsystem.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. 52510352Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.data 507.129647 # Average occupied blocks per requestor 5269797Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.990488 # Average percentage of cache occupancy 5279885Sstever@gmail.comsystem.cpu0.dcache.tags.occ_percent::total 0.990488 # Average percentage of cache occupancy 52810036SAli.Saidi@ARM.comsystem.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 52910036SAli.Saidi@ARM.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::0 443 # Occupied blocks per task id 53010036SAli.Saidi@ARM.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::1 65 # Occupied blocks per task id 53110036SAli.Saidi@ARM.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id 53210036SAli.Saidi@ARM.comsystem.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 53310352Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tag_accesses 62404315 # Number of tag accesses 53410352Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.data_accesses 62404315 # Number of data accesses 53510352Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 7298365 # number of ReadReq hits 53610352Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::total 7298365 # number of ReadReq hits 53710352Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 5462282 # number of WriteReq hits 53810352Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::total 5462282 # number of WriteReq hits 5399797Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 172144 # number of LoadLockedReq hits 5409797Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::total 172144 # number of LoadLockedReq hits 5419962Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 186624 # number of StoreCondReq hits 5429962Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::total 186624 # number of StoreCondReq hits 54310352Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 12760647 # number of demand (read+write) hits 54410352Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::total 12760647 # number of demand (read+write) hits 54510352Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 12760647 # number of overall hits 54610352Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::total 12760647 # number of overall hits 54710352Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 1683343 # number of ReadReq misses 54810352Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::total 1683343 # number of ReadReq misses 5499962Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 285998 # number of WriteReq misses 5509962Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::total 285998 # number of WriteReq misses 5519797Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16153 # number of LoadLockedReq misses 5529797Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::total 16153 # number of LoadLockedReq misses 5539962Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 714 # number of StoreCondReq misses 5549962Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::total 714 # number of StoreCondReq misses 55510352Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 1969341 # number of demand (read+write) misses 55610352Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::total 1969341 # number of demand (read+write) misses 55710352Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 1969341 # number of overall misses 55810352Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::total 1969341 # number of overall misses 55910352Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 8981708 # number of ReadReq accesses(hits+misses) 56010352Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 8981708 # number of ReadReq accesses(hits+misses) 56110352Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 5748280 # number of WriteReq accesses(hits+misses) 56210352Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 5748280 # number of WriteReq accesses(hits+misses) 5639797Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 188297 # number of LoadLockedReq accesses(hits+misses) 5649797Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 188297 # number of LoadLockedReq accesses(hits+misses) 5659797Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 187338 # number of StoreCondReq accesses(hits+misses) 5669797Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::total 187338 # number of StoreCondReq accesses(hits+misses) 56710352Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 14729988 # number of demand (read+write) accesses 56810352Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::total 14729988 # number of demand (read+write) accesses 56910352Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 14729988 # number of overall (read+write) accesses 57010352Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::total 14729988 # number of overall (read+write) accesses 5719962Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.187419 # miss rate for ReadReq accesses 5729962Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.187419 # miss rate for ReadReq accesses 5739797Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049754 # miss rate for WriteReq accesses 5749797Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.049754 # miss rate for WriteReq accesses 5759797Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085785 # miss rate for LoadLockedReq accesses 5769797Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085785 # miss rate for LoadLockedReq accesses 5779962Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003811 # miss rate for StoreCondReq accesses 5789962Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.003811 # miss rate for StoreCondReq accesses 5799797Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.133696 # miss rate for demand accesses 5809797Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.133696 # miss rate for demand accesses 5819797Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.133696 # miss rate for overall accesses 5829797Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.133696 # miss rate for overall accesses 5838721SN/Asystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 5848721SN/Asystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 5858721SN/Asystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 5868721SN/Asystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 5878983Snate@binkert.orgsystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 5888983Snate@binkert.orgsystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 5898721SN/Asystem.cpu0.dcache.fast_writes 0 # number of fast writes performed 5908721SN/Asystem.cpu0.dcache.cache_copies 0 # number of cache copies performed 59110352Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::writebacks 775643 # number of writebacks 59210352Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::total 775643 # number of writebacks 5938721SN/Asystem.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 5948721SN/Asystem.cpu1.dtb.fetch_hits 0 # ITB hits 5958721SN/Asystem.cpu1.dtb.fetch_misses 0 # ITB misses 5968721SN/Asystem.cpu1.dtb.fetch_acv 0 # ITB acv 5978721SN/Asystem.cpu1.dtb.fetch_accesses 0 # ITB accesses 5989797Sandreas.hansson@arm.comsystem.cpu1.dtb.read_hits 1163439 # DTB read hits 5998721SN/Asystem.cpu1.dtb.read_misses 3277 # DTB read misses 6008721SN/Asystem.cpu1.dtb.read_acv 58 # DTB read access violations 6018721SN/Asystem.cpu1.dtb.read_accesses 220342 # DTB read accesses 6029797Sandreas.hansson@arm.comsystem.cpu1.dtb.write_hits 751446 # DTB write hits 6038721SN/Asystem.cpu1.dtb.write_misses 415 # DTB write misses 6048721SN/Asystem.cpu1.dtb.write_acv 58 # DTB write access violations 6058721SN/Asystem.cpu1.dtb.write_accesses 103280 # DTB write accesses 6069797Sandreas.hansson@arm.comsystem.cpu1.dtb.data_hits 1914885 # DTB hits 6076024SN/Asystem.cpu1.dtb.data_misses 3692 # DTB misses 6088721SN/Asystem.cpu1.dtb.data_acv 116 # DTB access violations 6098721SN/Asystem.cpu1.dtb.data_accesses 323622 # DTB accesses 6109797Sandreas.hansson@arm.comsystem.cpu1.itb.fetch_hits 1468399 # ITB hits 6118721SN/Asystem.cpu1.itb.fetch_misses 1539 # ITB misses 6128721SN/Asystem.cpu1.itb.fetch_acv 57 # ITB acv 6139797Sandreas.hansson@arm.comsystem.cpu1.itb.fetch_accesses 1469938 # ITB accesses 6148721SN/Asystem.cpu1.itb.read_hits 0 # DTB read hits 6158721SN/Asystem.cpu1.itb.read_misses 0 # DTB read misses 6168721SN/Asystem.cpu1.itb.read_acv 0 # DTB read access violations 6178721SN/Asystem.cpu1.itb.read_accesses 0 # DTB read accesses 6188721SN/Asystem.cpu1.itb.write_hits 0 # DTB write hits 6198721SN/Asystem.cpu1.itb.write_misses 0 # DTB write misses 6208721SN/Asystem.cpu1.itb.write_acv 0 # DTB write access violations 6218721SN/Asystem.cpu1.itb.write_accesses 0 # DTB write accesses 6226024SN/Asystem.cpu1.itb.data_hits 0 # DTB hits 6236024SN/Asystem.cpu1.itb.data_misses 0 # DTB misses 6248721SN/Asystem.cpu1.itb.data_acv 0 # DTB access violations 6258721SN/Asystem.cpu1.itb.data_accesses 0 # DTB accesses 62610352Sandreas.hansson@arm.comsystem.cpu1.numCycles 3740248099 # number of cpu cycles simulated 6278721SN/Asystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 6288721SN/Asystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 62910352Sandreas.hansson@arm.comsystem.cpu1.committedInsts 5931963 # Number of instructions committed 63010352Sandreas.hansson@arm.comsystem.cpu1.committedOps 5931963 # Number of ops (including micro ops) committed 63110352Sandreas.hansson@arm.comsystem.cpu1.num_int_alu_accesses 5550581 # Number of integer alu accesses 6329797Sandreas.hansson@arm.comsystem.cpu1.num_fp_alu_accesses 28590 # Number of float alu accesses 6339797Sandreas.hansson@arm.comsystem.cpu1.num_func_calls 182742 # number of times a function call or return occured 63410352Sandreas.hansson@arm.comsystem.cpu1.num_conditional_control_insts 577192 # number of instructions that are conditional controls 63510352Sandreas.hansson@arm.comsystem.cpu1.num_int_insts 5550581 # number of integer instructions 6369797Sandreas.hansson@arm.comsystem.cpu1.num_fp_insts 28590 # number of float instructions 63710352Sandreas.hansson@arm.comsystem.cpu1.num_int_register_reads 7657293 # number of times the integer registers were read 63810352Sandreas.hansson@arm.comsystem.cpu1.num_int_register_writes 4163277 # number of times the integer registers were written 6399797Sandreas.hansson@arm.comsystem.cpu1.num_fp_register_reads 17889 # number of times the floating registers were read 6409797Sandreas.hansson@arm.comsystem.cpu1.num_fp_register_writes 17683 # number of times the floating registers were written 6419797Sandreas.hansson@arm.comsystem.cpu1.num_mem_refs 1926244 # number of memory refs 6429797Sandreas.hansson@arm.comsystem.cpu1.num_load_insts 1170888 # Number of load instructions 6439797Sandreas.hansson@arm.comsystem.cpu1.num_store_insts 755356 # Number of store instructions 64410352Sandreas.hansson@arm.comsystem.cpu1.num_idle_cycles 3734311403.078359 # Number of idle cycles 64510352Sandreas.hansson@arm.comsystem.cpu1.num_busy_cycles 5936695.921641 # Number of busy cycles 6469797Sandreas.hansson@arm.comsystem.cpu1.not_idle_fraction 0.001587 # Percentage of non-idle cycles 6479797Sandreas.hansson@arm.comsystem.cpu1.idle_fraction 0.998413 # Percentage of idle cycles 64810352Sandreas.hansson@arm.comsystem.cpu1.Branches 836749 # Number of branches fetched 64910220Sandreas.hansson@arm.comsystem.cpu1.op_class::No_OpClass 239814 4.04% 4.04% # Class of executed instruction 65010352Sandreas.hansson@arm.comsystem.cpu1.op_class::IntAlu 3533248 59.52% 63.56% # Class of executed instruction 65110220Sandreas.hansson@arm.comsystem.cpu1.op_class::IntMult 9651 0.16% 63.73% # Class of executed instruction 65210220Sandreas.hansson@arm.comsystem.cpu1.op_class::IntDiv 0 0.00% 63.73% # Class of executed instruction 65310352Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatAdd 7388 0.12% 63.85% # Class of executed instruction 65410220Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatCmp 0 0.00% 63.85% # Class of executed instruction 65510220Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatCvt 0 0.00% 63.85% # Class of executed instruction 65610220Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatMult 0 0.00% 63.85% # Class of executed instruction 65710220Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatDiv 1421 0.02% 63.88% # Class of executed instruction 65810220Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatSqrt 0 0.00% 63.88% # Class of executed instruction 65910220Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAdd 0 0.00% 63.88% # Class of executed instruction 66010220Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAddAcc 0 0.00% 63.88% # Class of executed instruction 66110220Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAlu 0 0.00% 63.88% # Class of executed instruction 66210220Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdCmp 0 0.00% 63.88% # Class of executed instruction 66310220Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdCvt 0 0.00% 63.88% # Class of executed instruction 66410220Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMisc 0 0.00% 63.88% # Class of executed instruction 66510220Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMult 0 0.00% 63.88% # Class of executed instruction 66610220Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMultAcc 0 0.00% 63.88% # Class of executed instruction 66710220Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdShift 0 0.00% 63.88% # Class of executed instruction 66810220Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdShiftAcc 0 0.00% 63.88% # Class of executed instruction 66910220Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdSqrt 0 0.00% 63.88% # Class of executed instruction 67010220Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatAdd 0 0.00% 63.88% # Class of executed instruction 67110220Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatAlu 0 0.00% 63.88% # Class of executed instruction 67210220Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatCmp 0 0.00% 63.88% # Class of executed instruction 67310220Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatCvt 0 0.00% 63.88% # Class of executed instruction 67410220Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatDiv 0 0.00% 63.88% # Class of executed instruction 67510220Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMisc 0 0.00% 63.88% # Class of executed instruction 67610220Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMult 0 0.00% 63.88% # Class of executed instruction 67710220Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMultAcc 0 0.00% 63.88% # Class of executed instruction 67810220Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatSqrt 0 0.00% 63.88% # Class of executed instruction 67910220Sandreas.hansson@arm.comsystem.cpu1.op_class::MemRead 1191429 20.07% 83.95% # Class of executed instruction 68010220Sandreas.hansson@arm.comsystem.cpu1.op_class::MemWrite 755540 12.73% 96.68% # Class of executed instruction 68110220Sandreas.hansson@arm.comsystem.cpu1.op_class::IprAccess 197280 3.32% 100.00% # Class of executed instruction 68210220Sandreas.hansson@arm.comsystem.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 68310352Sandreas.hansson@arm.comsystem.cpu1.op_class::total 5935771 # Class of executed instruction 6842968SN/Asystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 68510352Sandreas.hansson@arm.comsystem.cpu1.kern.inst.quiesce 2205 # number of quiesce instructions executed 6869797Sandreas.hansson@arm.comsystem.cpu1.kern.inst.hwrei 39554 # number of hwrei instructions executed 6879797Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::0 10328 33.46% 33.46% # number of times we switched to this ipl 6889797Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::22 1907 6.18% 39.64% # number of times we switched to this ipl 6899797Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::30 110 0.36% 40.00% # number of times we switched to this ipl 6909797Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::31 18518 60.00% 100.00% # number of times we switched to this ipl 6919797Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::total 30863 # number of times we switched to this ipl 6929797Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::0 10318 45.77% 45.77% # number of times we switched to this ipl from a different ipl 6939797Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::22 1907 8.46% 54.23% # number of times we switched to this ipl from a different ipl 6949797Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::30 110 0.49% 54.72% # number of times we switched to this ipl from a different ipl 6959797Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::31 10208 45.28% 100.00% # number of times we switched to this ipl from a different ipl 6969797Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::total 22543 # number of times we switched to this ipl from a different ipl 69710352Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::0 1859122617500 99.41% 99.41% # number of cycles we spent at this ipl 6986291SN/Asystem.cpu1.kern.ipl_ticks::22 82001000 0.00% 99.42% # number of cycles we spent at this ipl 6999797Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::30 14064500 0.00% 99.42% # number of cycles we spent at this ipl 7009797Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::31 10905353000 0.58% 100.00% # number of cycles we spent at this ipl 70110352Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::total 1870124036000 # number of cycles we spent at this ipl 7029797Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_used::0 0.999032 # fraction of swpipl calls that actually changed the ipl 7036127SN/Asystem.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 7046127SN/Asystem.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 7059797Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_used::31 0.551247 # fraction of swpipl calls that actually changed the ipl 7069797Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_used::total 0.730422 # fraction of swpipl calls that actually changed the ipl 7076291SN/Asystem.cpu1.kern.syscall::2 2 2.00% 2.00% # number of syscalls executed 7086291SN/Asystem.cpu1.kern.syscall::3 11 11.00% 13.00% # number of syscalls executed 7096291SN/Asystem.cpu1.kern.syscall::4 2 2.00% 15.00% # number of syscalls executed 7106291SN/Asystem.cpu1.kern.syscall::6 10 10.00% 25.00% # number of syscalls executed 7116291SN/Asystem.cpu1.kern.syscall::17 6 6.00% 31.00% # number of syscalls executed 7126291SN/Asystem.cpu1.kern.syscall::19 2 2.00% 33.00% # number of syscalls executed 7136291SN/Asystem.cpu1.kern.syscall::23 2 2.00% 35.00% # number of syscalls executed 7146291SN/Asystem.cpu1.kern.syscall::24 2 2.00% 37.00% # number of syscalls executed 7156291SN/Asystem.cpu1.kern.syscall::33 4 4.00% 41.00% # number of syscalls executed 7166291SN/Asystem.cpu1.kern.syscall::45 17 17.00% 58.00% # number of syscalls executed 7176291SN/Asystem.cpu1.kern.syscall::47 2 2.00% 60.00% # number of syscalls executed 7186291SN/Asystem.cpu1.kern.syscall::48 2 2.00% 62.00% # number of syscalls executed 7196291SN/Asystem.cpu1.kern.syscall::59 3 3.00% 65.00% # number of syscalls executed 7206291SN/Asystem.cpu1.kern.syscall::71 24 24.00% 89.00% # number of syscalls executed 7216291SN/Asystem.cpu1.kern.syscall::74 8 8.00% 97.00% # number of syscalls executed 7226291SN/Asystem.cpu1.kern.syscall::90 1 1.00% 98.00% # number of syscalls executed 7236291SN/Asystem.cpu1.kern.syscall::132 2 2.00% 100.00% # number of syscalls executed 7246127SN/Asystem.cpu1.kern.syscall::total 100 # number of syscalls executed 7258721SN/Asystem.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 7268721SN/Asystem.cpu1.kern.callpal::wripir 8 0.02% 0.03% # number of callpals executed 7278721SN/Asystem.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed 7288721SN/Asystem.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed 7299797Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::swpctx 470 1.46% 1.50% # number of callpals executed 7308721SN/Asystem.cpu1.kern.callpal::tbi 15 0.05% 1.54% # number of callpals executed 7318721SN/Asystem.cpu1.kern.callpal::wrent 7 0.02% 1.57% # number of callpals executed 7329797Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::swpipl 26238 81.66% 83.22% # number of callpals executed 7339797Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::rdps 2576 8.02% 91.24% # number of callpals executed 7349797Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wrkgp 1 0.00% 91.25% # number of callpals executed 7359797Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wrusp 4 0.01% 91.26% # number of callpals executed 7369797Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::rdusp 2 0.01% 91.26% # number of callpals executed 7379797Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::whami 3 0.01% 91.27% # number of callpals executed 7389797Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::rti 2607 8.11% 99.39% # number of callpals executed 7398721SN/Asystem.cpu1.kern.callpal::callsys 158 0.49% 99.88% # number of callpals executed 7408721SN/Asystem.cpu1.kern.callpal::imb 38 0.12% 100.00% # number of callpals executed 7418721SN/Asystem.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed 7429797Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::total 32131 # number of callpals executed 7439797Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch::kernel 1033 # number of protection mode switches 7448721SN/Asystem.cpu1.kern.mode_switch::user 580 # number of protection mode switches 7459797Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch::idle 2046 # number of protection mode switches 7469797Sandreas.hansson@arm.comsystem.cpu1.kern.mode_good::kernel 612 7478721SN/Asystem.cpu1.kern.mode_good::user 580 7489797Sandreas.hansson@arm.comsystem.cpu1.kern.mode_good::idle 32 7499797Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch_good::kernel 0.592449 # fraction of useful protection mode switches 7508721SN/Asystem.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 7519797Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch_good::idle 0.015640 # fraction of useful protection mode switches 7529797Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch_good::total 0.334518 # fraction of useful protection mode switches 75310352Sandreas.hansson@arm.comsystem.cpu1.kern.mode_ticks::kernel 1373909000 0.07% 0.07% # number of ticks spent at the given mode 7548721SN/Asystem.cpu1.kern.mode_ticks::user 508289000 0.03% 0.10% # number of ticks spent at the given mode 75510352Sandreas.hansson@arm.comsystem.cpu1.kern.mode_ticks::idle 1868002186500 99.90% 100.00% # number of ticks spent at the given mode 7569797Sandreas.hansson@arm.comsystem.cpu1.kern.swap_context 471 # number of times the context was actually changed 75710352Sandreas.hansson@arm.comsystem.cpu1.icache.tags.replacements 103097 # number of replacements 75810352Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tagsinuse 427.126315 # Cycle average of tags in use 75910352Sandreas.hansson@arm.comsystem.cpu1.icache.tags.total_refs 5832135 # Total number of references to valid blocks. 76010352Sandreas.hansson@arm.comsystem.cpu1.icache.tags.sampled_refs 103609 # Sample count of references to valid blocks. 76110352Sandreas.hansson@arm.comsystem.cpu1.icache.tags.avg_refs 56.289849 # Average number of references to valid blocks. 76210352Sandreas.hansson@arm.comsystem.cpu1.icache.tags.warmup_cycle 1868932699000 # Cycle when the warmup percentage was hit. 76310352Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 427.126315 # Average occupied blocks per requestor 7649797Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.834231 # Average percentage of cache occupancy 7659885Sstever@gmail.comsystem.cpu1.icache.tags.occ_percent::total 0.834231 # Average percentage of cache occupancy 76610036SAli.Saidi@ARM.comsystem.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 76710036SAli.Saidi@ARM.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id 76810036SAli.Saidi@ARM.comsystem.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 76910352Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tag_accesses 6039407 # Number of tag accesses 77010352Sandreas.hansson@arm.comsystem.cpu1.icache.tags.data_accesses 6039407 # Number of data accesses 77110352Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 5832135 # number of ReadReq hits 77210352Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::total 5832135 # number of ReadReq hits 77310352Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::cpu1.inst 5832135 # number of demand (read+write) hits 77410352Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::total 5832135 # number of demand (read+write) hits 77510352Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::cpu1.inst 5832135 # number of overall hits 77610352Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::total 5832135 # number of overall hits 77710352Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 103636 # number of ReadReq misses 77810352Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::total 103636 # number of ReadReq misses 77910352Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::cpu1.inst 103636 # number of demand (read+write) misses 78010352Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::total 103636 # number of demand (read+write) misses 78110352Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::cpu1.inst 103636 # number of overall misses 78210352Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::total 103636 # number of overall misses 78310352Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 5935771 # number of ReadReq accesses(hits+misses) 78410352Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::total 5935771 # number of ReadReq accesses(hits+misses) 78510352Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::cpu1.inst 5935771 # number of demand (read+write) accesses 78610352Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::total 5935771 # number of demand (read+write) accesses 78710352Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::cpu1.inst 5935771 # number of overall (read+write) accesses 78810352Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::total 5935771 # number of overall (read+write) accesses 78910352Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.017460 # miss rate for ReadReq accesses 79010352Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.017460 # miss rate for ReadReq accesses 79110352Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.017460 # miss rate for demand accesses 79210352Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::total 0.017460 # miss rate for demand accesses 79310352Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.017460 # miss rate for overall accesses 79410352Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::total 0.017460 # miss rate for overall accesses 7958721SN/Asystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 7968721SN/Asystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 7978721SN/Asystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 7988721SN/Asystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 7998983Snate@binkert.orgsystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 8008983Snate@binkert.orgsystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 8018721SN/Asystem.cpu1.icache.fast_writes 0 # number of fast writes performed 8028721SN/Asystem.cpu1.icache.cache_copies 0 # number of cache copies performed 8038721SN/Asystem.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 80410352Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.replacements 62047 # number of replacements 80510352Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tagsinuse 421.558473 # Cycle average of tags in use 80610352Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.total_refs 1836050 # Total number of references to valid blocks. 80710352Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.sampled_refs 62385 # Sample count of references to valid blocks. 80810352Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.avg_refs 29.430953 # Average number of references to valid blocks. 80910352Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.warmup_cycle 1851115162500 # Cycle when the warmup percentage was hit. 81010352Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.data 421.558473 # Average occupied blocks per requestor 81110352Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.823356 # Average percentage of cache occupancy 81210352Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::total 0.823356 # Average percentage of cache occupancy 81310036SAli.Saidi@ARM.comsystem.cpu1.dcache.tags.occ_task_id_blocks::1024 338 # Occupied blocks per task id 81410036SAli.Saidi@ARM.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::2 337 # Occupied blocks per task id 81510036SAli.Saidi@ARM.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 81610036SAli.Saidi@ARM.comsystem.cpu1.dcache.tags.occ_task_id_percent::1024 0.660156 # Percentage of cache occupancy per task id 81710352Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tag_accesses 7735314 # Number of tag accesses 81810352Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.data_accesses 7735314 # Number of data accesses 81910352Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 1109520 # number of ReadReq hits 82010352Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::total 1109520 # number of ReadReq hits 82110352Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 707454 # number of WriteReq hits 82210352Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::total 707454 # number of WriteReq hits 8239797Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 15133 # number of LoadLockedReq hits 8249797Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::total 15133 # number of LoadLockedReq hits 8259797Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 15610 # number of StoreCondReq hits 8269797Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::total 15610 # number of StoreCondReq hits 82710352Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 1816974 # number of demand (read+write) hits 82810352Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::total 1816974 # number of demand (read+write) hits 82910352Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 1816974 # number of overall hits 83010352Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::total 1816974 # number of overall hits 83110352Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 41445 # number of ReadReq misses 83210352Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::total 41445 # number of ReadReq misses 83310352Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 25851 # number of WriteReq misses 83410352Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::total 25851 # number of WriteReq misses 8359797Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1285 # number of LoadLockedReq misses 8369797Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::total 1285 # number of LoadLockedReq misses 8379797Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 735 # number of StoreCondReq misses 8389797Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::total 735 # number of StoreCondReq misses 83910352Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 67296 # number of demand (read+write) misses 84010352Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::total 67296 # number of demand (read+write) misses 84110352Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 67296 # number of overall misses 84210352Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::total 67296 # number of overall misses 8439797Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 1150965 # number of ReadReq accesses(hits+misses) 8449797Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::total 1150965 # number of ReadReq accesses(hits+misses) 8459797Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 733305 # number of WriteReq accesses(hits+misses) 8469797Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::total 733305 # number of WriteReq accesses(hits+misses) 8479797Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 16418 # number of LoadLockedReq accesses(hits+misses) 8489797Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 16418 # number of LoadLockedReq accesses(hits+misses) 8499797Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 16345 # number of StoreCondReq accesses(hits+misses) 8509797Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::total 16345 # number of StoreCondReq accesses(hits+misses) 8519797Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::cpu1.data 1884270 # number of demand (read+write) accesses 8529797Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::total 1884270 # number of demand (read+write) accesses 8539797Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::cpu1.data 1884270 # number of overall (read+write) accesses 8549797Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::total 1884270 # number of overall (read+write) accesses 85510352Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036009 # miss rate for ReadReq accesses 85610352Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.036009 # miss rate for ReadReq accesses 85710352Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.035253 # miss rate for WriteReq accesses 85810352Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.035253 # miss rate for WriteReq accesses 8599797Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.078268 # miss rate for LoadLockedReq accesses 8609797Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.078268 # miss rate for LoadLockedReq accesses 8619797Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.044968 # miss rate for StoreCondReq accesses 8629797Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.044968 # miss rate for StoreCondReq accesses 86310352Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.035715 # miss rate for demand accesses 86410352Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.035715 # miss rate for demand accesses 86510352Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.035715 # miss rate for overall accesses 86610352Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.035715 # miss rate for overall accesses 8678721SN/Asystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 8688721SN/Asystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 8698721SN/Asystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 8708721SN/Asystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 8718983Snate@binkert.orgsystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 8728983Snate@binkert.orgsystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 8738721SN/Asystem.cpu1.dcache.fast_writes 0 # number of fast writes performed 8748721SN/Asystem.cpu1.dcache.cache_copies 0 # number of cache copies performed 87510352Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::writebacks 41020 # number of writebacks 87610352Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::total 41020 # number of writebacks 8778721SN/Asystem.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 8782968SN/A 8792968SN/A---------- End Simulation Statistics ---------- 880