stats.txt revision 9924:31ef410b6843
12SN/A 21762SN/A---------- Begin Simulation Statistics ---------- 32SN/Asim_seconds 0.144337 # Number of seconds simulated 42SN/Asim_ticks 144337151000 # Number of ticks simulated 52SN/Afinal_tick 144337151000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 62SN/Asim_freq 1000000000000 # Frequency of simulated ticks 72SN/Ahost_inst_rate 71990 # Simulator instruction rate (inst/s) 82SN/Ahost_op_rate 120663 # Simulator op (including micro ops) rate (op/s) 92SN/Ahost_tick_rate 78676444 # Simulator tick rate (ticks/s) 102SN/Ahost_mem_usage 280564 # Number of bytes of host memory used 112SN/Ahost_seconds 1834.57 # Real time elapsed on the host 122SN/Asim_insts 132071192 # Number of instructions simulated 132SN/Asim_ops 221363384 # Number of ops (including micro ops) simulated 142SN/Asystem.physmem.bytes_read::cpu.inst 217984 # Number of bytes read from this memory 152SN/Asystem.physmem.bytes_read::cpu.data 125184 # Number of bytes read from this memory 162SN/Asystem.physmem.bytes_read::total 343168 # Number of bytes read from this memory 172SN/Asystem.physmem.bytes_inst_read::cpu.inst 217984 # Number of instructions bytes read from this memory 182SN/Asystem.physmem.bytes_inst_read::total 217984 # Number of instructions bytes read from this memory 192SN/Asystem.physmem.num_reads::cpu.inst 3406 # Number of read requests responded to by this memory 202SN/Asystem.physmem.num_reads::cpu.data 1956 # Number of read requests responded to by this memory 212SN/Asystem.physmem.num_reads::total 5362 # Number of read requests responded to by this memory 222SN/Asystem.physmem.bw_read::cpu.inst 1510242 # Total read bandwidth from this memory (bytes/s) 232SN/Asystem.physmem.bw_read::cpu.data 867303 # Total read bandwidth from this memory (bytes/s) 242SN/Asystem.physmem.bw_read::total 2377545 # Total read bandwidth from this memory (bytes/s) 252SN/Asystem.physmem.bw_inst_read::cpu.inst 1510242 # Instruction read bandwidth from this memory (bytes/s) 262SN/Asystem.physmem.bw_inst_read::total 1510242 # Instruction read bandwidth from this memory (bytes/s) 272665Ssaidi@eecs.umich.edusystem.physmem.bw_total::cpu.inst 1510242 # Total bandwidth to/from this memory (bytes/s) 282665Ssaidi@eecs.umich.edusystem.physmem.bw_total::cpu.data 867303 # Total bandwidth to/from this memory (bytes/s) 292SN/Asystem.physmem.bw_total::total 2377545 # Total bandwidth to/from this memory (bytes/s) 302SN/Asystem.physmem.readReqs 5363 # Total number of read requests accepted by DRAM controller 312439SN/Asystem.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller 32146SN/Asystem.physmem.readBursts 5363 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts 33146SN/Asystem.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts 34146SN/Asystem.physmem.bytesRead 343168 # Total number of bytes read from memory 35146SN/Asystem.physmem.bytesWritten 0 # Total number of bytes written to memory 36146SN/Asystem.physmem.bytesConsumedRd 343168 # bytesRead derated as per pkt->getSize() 37146SN/Asystem.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 381717SN/Asystem.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q 39146SN/Asystem.physmem.neitherReadNorWrite 155 # Reqs where no action is needed 401717SN/Asystem.physmem.perBankRdReqs::0 287 # Track reads on a per bank basis 41146SN/Asystem.physmem.perBankRdReqs::1 360 # Track reads on a per bank basis 421977SN/Asystem.physmem.perBankRdReqs::2 449 # Track reads on a per bank basis 432623SN/Asystem.physmem.perBankRdReqs::3 361 # Track reads on a per bank basis 442683Sktlim@umich.edusystem.physmem.perBankRdReqs::4 329 # Track reads on a per bank basis 451717SN/Asystem.physmem.perBankRdReqs::5 326 # Track reads on a per bank basis 46146SN/Asystem.physmem.perBankRdReqs::6 396 # Track reads on a per bank basis 472683Sktlim@umich.edusystem.physmem.perBankRdReqs::7 379 # Track reads on a per bank basis 481917SN/Asystem.physmem.perBankRdReqs::8 340 # Track reads on a per bank basis 492592SN/Asystem.physmem.perBankRdReqs::9 277 # Track reads on a per bank basis 502683Sktlim@umich.edusystem.physmem.perBankRdReqs::10 230 # Track reads on a per bank basis 512036SN/Asystem.physmem.perBankRdReqs::11 279 # Track reads on a per bank basis 52146SN/Asystem.physmem.perBankRdReqs::12 206 # Track reads on a per bank basis 5356SN/Asystem.physmem.perBankRdReqs::13 469 # Track reads on a per bank basis 5456SN/Asystem.physmem.perBankRdReqs::14 390 # Track reads on a per bank basis 5556SN/Asystem.physmem.perBankRdReqs::15 285 # Track reads on a per bank basis 56695SN/Asystem.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 572901Ssaidi@eecs.umich.edusystem.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 582SN/Asystem.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 591858SN/Asystem.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 6056SN/Asystem.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 612171SN/Asystem.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 622170SN/Asystem.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 632170SN/Asystem.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 64146SN/Asystem.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 652462SN/Asystem.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 66146SN/Asystem.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 672SN/Asystem.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 682SN/Asystem.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 692449SN/Asystem.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 701355SN/Asystem.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 712623SN/Asystem.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 722683Sktlim@umich.edusystem.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 73224SN/Asystem.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 741858SN/Asystem.physmem.totGap 144337117000 # Total gap between requests 752683Sktlim@umich.edusystem.physmem.readPktSize::0 0 # Categorize read packet sizes 762420SN/Asystem.physmem.readPktSize::1 0 # Categorize read packet sizes 772683Sktlim@umich.edusystem.physmem.readPktSize::2 0 # Categorize read packet sizes 782520SN/Asystem.physmem.readPktSize::3 0 # Categorize read packet sizes 792420SN/Asystem.physmem.readPktSize::4 0 # Categorize read packet sizes 802SN/Asystem.physmem.readPktSize::5 0 # Categorize read packet sizes 812683Sktlim@umich.edusystem.physmem.readPktSize::6 5363 # Categorize read packet sizes 822672Sktlim@umich.edusystem.physmem.writePktSize::0 0 # Categorize write packet sizes 832683Sktlim@umich.edusystem.physmem.writePktSize::1 0 # Categorize write packet sizes 842SN/Asystem.physmem.writePktSize::2 0 # Categorize write packet sizes 852SN/Asystem.physmem.writePktSize::3 0 # Categorize write packet sizes 86334SN/Asystem.physmem.writePktSize::4 0 # Categorize write packet sizes 87140SN/Asystem.physmem.writePktSize::5 0 # Categorize write packet sizes 88334SN/Asystem.physmem.writePktSize::6 0 # Categorize write packet sizes 892SN/Asystem.physmem.rdQLenPdf::0 4337 # What read queue length does an incoming req see 902SN/Asystem.physmem.rdQLenPdf::1 861 # What read queue length does an incoming req see 912SN/Asystem.physmem.rdQLenPdf::2 143 # What read queue length does an incoming req see 922680Sktlim@umich.edusystem.physmem.rdQLenPdf::3 21 # What read queue length does an incoming req see 932SN/Asystem.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 942SN/Asystem.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 952623SN/Asystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 962SN/Asystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 972SN/Asystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 982SN/Asystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 99180SN/Asystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 1002623SN/Asystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 101393SN/Asystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 102393SN/Asystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 103393SN/Asystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 104393SN/Asystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 105384SN/Asystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 106384SN/Asystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 107393SN/Asystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 1082623SN/Asystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 109393SN/Asystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 110393SN/Asystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 111393SN/Asystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 112393SN/Asystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 113384SN/Asystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 114189SN/Asystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 115189SN/Asystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1162623SN/Asystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1172SN/Asystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 118729SN/Asystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 119334SN/Asystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1202SN/Asystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 1212SN/Asystem.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 1222SN/Asystem.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 1232SN/Asystem.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 1242SN/Asystem.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 1252SN/Asystem.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 1262SN/Asystem.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 1272SN/Asystem.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 1282SN/Asystem.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 1292SN/Asystem.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 1302SN/Asystem.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 1312SN/Asystem.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 1321001SN/Asystem.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 1331001SN/Asystem.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 1341001SN/Asystem.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 1351001SN/Asystem.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 1361001SN/Asystem.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 1372SN/Asystem.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 1382SN/Asystem.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 1392SN/Asystem.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 1402SN/Asystem.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 1412SN/Asystem.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 1422SN/Asystem.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 1432SN/Asystem.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 1442SN/Asystem.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 1452SN/Asystem.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 1462SN/Asystem.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 1472SN/Asystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 1482SN/Asystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 1492SN/Asystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 1502SN/Asystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 1512SN/Asystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 1522SN/Asystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 1532SN/Asystem.physmem.bytesPerActivate::samples 502 # Bytes accessed per row activation 1542390SN/Asystem.physmem.bytesPerActivate::mean 668.557769 # Bytes accessed per row activation 1552390SN/Asystem.physmem.bytesPerActivate::gmean 237.238454 # Bytes accessed per row activation 1562390SN/Asystem.physmem.bytesPerActivate::stdev 1295.396575 # Bytes accessed per row activation 1572390SN/Asystem.physmem.bytesPerActivate::64-65 170 33.86% 33.86% # Bytes accessed per row activation 1582390SN/Asystem.physmem.bytesPerActivate::128-129 76 15.14% 49.00% # Bytes accessed per row activation 1592390SN/Asystem.physmem.bytesPerActivate::192-193 42 8.37% 57.37% # Bytes accessed per row activation 1602390SN/Asystem.physmem.bytesPerActivate::256-257 23 4.58% 61.95% # Bytes accessed per row activation 1612390SN/Asystem.physmem.bytesPerActivate::320-321 26 5.18% 67.13% # Bytes accessed per row activation 1622390SN/Asystem.physmem.bytesPerActivate::384-385 11 2.19% 69.32% # Bytes accessed per row activation 1632390SN/Asystem.physmem.bytesPerActivate::448-449 16 3.19% 72.51% # Bytes accessed per row activation 1642390SN/Asystem.physmem.bytesPerActivate::512-513 9 1.79% 74.30% # Bytes accessed per row activation 1652390SN/Asystem.physmem.bytesPerActivate::576-577 9 1.79% 76.10% # Bytes accessed per row activation 166385SN/Asystem.physmem.bytesPerActivate::640-641 7 1.39% 77.49% # Bytes accessed per row activation 1672SN/Asystem.physmem.bytesPerActivate::704-705 3 0.60% 78.09% # Bytes accessed per row activation 1682SN/Asystem.physmem.bytesPerActivate::768-769 8 1.59% 79.68% # Bytes accessed per row activation 1692SN/Asystem.physmem.bytesPerActivate::832-833 5 1.00% 80.68% # Bytes accessed per row activation 1702623SN/Asystem.physmem.bytesPerActivate::896-897 3 0.60% 81.27% # Bytes accessed per row activation 171334SN/Asystem.physmem.bytesPerActivate::960-961 4 0.80% 82.07% # Bytes accessed per row activation 172334SN/Asystem.physmem.bytesPerActivate::1024-1025 5 1.00% 83.07% # Bytes accessed per row activation 1732623SN/Asystem.physmem.bytesPerActivate::1088-1089 4 0.80% 83.86% # Bytes accessed per row activation 174334SN/Asystem.physmem.bytesPerActivate::1152-1153 5 1.00% 84.86% # Bytes accessed per row activation 175334SN/Asystem.physmem.bytesPerActivate::1216-1217 2 0.40% 85.26% # Bytes accessed per row activation 176334SN/Asystem.physmem.bytesPerActivate::1280-1281 2 0.40% 85.66% # Bytes accessed per row activation 1772623SN/Asystem.physmem.bytesPerActivate::1344-1345 3 0.60% 86.25% # Bytes accessed per row activation 1782SN/Asystem.physmem.bytesPerActivate::1408-1409 5 1.00% 87.25% # Bytes accessed per row activation 179921SN/Asystem.physmem.bytesPerActivate::1472-1473 3 0.60% 87.85% # Bytes accessed per row activation 1802915Sktlim@umich.edusystem.physmem.bytesPerActivate::1536-1537 1 0.20% 88.05% # Bytes accessed per row activation 1812915Sktlim@umich.edusystem.physmem.bytesPerActivate::1600-1601 2 0.40% 88.45% # Bytes accessed per row activation 1822683Sktlim@umich.edusystem.physmem.bytesPerActivate::1664-1665 1 0.20% 88.65% # Bytes accessed per row activation 1832SN/Asystem.physmem.bytesPerActivate::1728-1729 1 0.20% 88.84% # Bytes accessed per row activation 1842SN/Asystem.physmem.bytesPerActivate::1792-1793 2 0.40% 89.24% # Bytes accessed per row activation 1852SN/Asystem.physmem.bytesPerActivate::1856-1857 4 0.80% 90.04% # Bytes accessed per row activation 1862623SN/Asystem.physmem.bytesPerActivate::1920-1921 4 0.80% 90.84% # Bytes accessed per row activation 1872SN/Asystem.physmem.bytesPerActivate::1984-1985 1 0.20% 91.04% # Bytes accessed per row activation 188921SN/Asystem.physmem.bytesPerActivate::2048-2049 2 0.40% 91.43% # Bytes accessed per row activation 1892915Sktlim@umich.edusystem.physmem.bytesPerActivate::2176-2177 1 0.20% 91.63% # Bytes accessed per row activation 1902915Sktlim@umich.edusystem.physmem.bytesPerActivate::2240-2241 4 0.80% 92.43% # Bytes accessed per row activation 1912SN/Asystem.physmem.bytesPerActivate::2304-2305 1 0.20% 92.63% # Bytes accessed per row activation 1922SN/Asystem.physmem.bytesPerActivate::2432-2433 2 0.40% 93.03% # Bytes accessed per row activation 1932SN/Asystem.physmem.bytesPerActivate::2496-2497 2 0.40% 93.43% # Bytes accessed per row activation 1942SN/Asystem.physmem.bytesPerActivate::2624-2625 1 0.20% 93.63% # Bytes accessed per row activation 1952SN/Asystem.physmem.bytesPerActivate::2688-2689 1 0.20% 93.82% # Bytes accessed per row activation 1962SN/Asystem.physmem.bytesPerActivate::2816-2817 5 1.00% 94.82% # Bytes accessed per row activation 1972SN/Asystem.physmem.bytesPerActivate::2880-2881 1 0.20% 95.02% # Bytes accessed per row activation 198595SN/Asystem.physmem.bytesPerActivate::2944-2945 1 0.20% 95.22% # Bytes accessed per row activation 1992623SN/Asystem.physmem.bytesPerActivate::3264-3265 1 0.20% 95.42% # Bytes accessed per row activation 200595SN/Asystem.physmem.bytesPerActivate::3328-3329 1 0.20% 95.62% # Bytes accessed per row activation 2012390SN/Asystem.physmem.bytesPerActivate::3392-3393 1 0.20% 95.82% # Bytes accessed per row activation 2021080SN/Asystem.physmem.bytesPerActivate::3520-3521 2 0.40% 96.22% # Bytes accessed per row activation 2031080SN/Asystem.physmem.bytesPerActivate::3584-3585 1 0.20% 96.41% # Bytes accessed per row activation 2041080SN/Asystem.physmem.bytesPerActivate::3648-3649 1 0.20% 96.61% # Bytes accessed per row activation 2051080SN/Asystem.physmem.bytesPerActivate::4224-4225 1 0.20% 96.81% # Bytes accessed per row activation 2061080SN/Asystem.physmem.bytesPerActivate::4352-4353 2 0.40% 97.21% # Bytes accessed per row activation 2071080SN/Asystem.physmem.bytesPerActivate::4480-4481 1 0.20% 97.41% # Bytes accessed per row activation 2081080SN/Asystem.physmem.bytesPerActivate::4544-4545 1 0.20% 97.61% # Bytes accessed per row activation 2091121SN/Asystem.physmem.bytesPerActivate::4672-4673 1 0.20% 97.81% # Bytes accessed per row activation 2102107SN/Asystem.physmem.bytesPerActivate::5312-5313 1 0.20% 98.01% # Bytes accessed per row activation 2111089SN/Asystem.physmem.bytesPerActivate::5888-5889 1 0.20% 98.21% # Bytes accessed per row activation 2121089SN/Asystem.physmem.bytesPerActivate::6336-6337 1 0.20% 98.41% # Bytes accessed per row activation 2131080SN/Asystem.physmem.bytesPerActivate::6592-6593 1 0.20% 98.61% # Bytes accessed per row activation 2141080SN/Asystem.physmem.bytesPerActivate::6912-6913 1 0.20% 98.80% # Bytes accessed per row activation 2151080SN/Asystem.physmem.bytesPerActivate::8128-8129 1 0.20% 99.00% # Bytes accessed per row activation 2161080SN/Asystem.physmem.bytesPerActivate::8192-8193 5 1.00% 100.00% # Bytes accessed per row activation 217595SN/Asystem.physmem.bytesPerActivate::total 502 # Bytes accessed per row activation 2182623SN/Asystem.physmem.totQLat 12694000 # Total cycles spent in queuing delays 2192683Sktlim@umich.edusystem.physmem.totMemAccLat 119204000 # Sum of mem lat for all requests 220595SN/Asystem.physmem.totBusLat 26815000 # Total cycles spent in databus access 2212090SN/Asystem.physmem.totBankLat 79695000 # Total cycles spent in bank access 2222683Sktlim@umich.edusystem.physmem.avgQLat 2366.96 # Average queueing delay per request 2232683Sktlim@umich.edusystem.physmem.avgBankLat 14860.15 # Average bank access latency per request 224595SN/Asystem.physmem.avgBusLat 5000.00 # Average bus latency per request 2252205SN/Asystem.physmem.avgMemAccLat 22227.11 # Average memory access latency 2262205SN/Asystem.physmem.avgRdBW 2.38 # Average achieved read bandwidth in MB/s 2272683Sktlim@umich.edusystem.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s 2282683Sktlim@umich.edusystem.physmem.avgConsumedRdBW 2.38 # Average consumed read bandwidth in MB/s 229595SN/Asystem.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 230595SN/Asystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 2312390SN/Asystem.physmem.busUtil 0.02 # Data bus utilization in percentage 2322423SN/Asystem.physmem.avgRdQLen 0.00 # Average read queue length over time 2332390SN/Asystem.physmem.avgWrQLen 0.00 # Average write queue length over time 234595SN/Asystem.physmem.readRowHits 4861 # Number of row buffer hits during reads 235595SN/Asystem.physmem.writeRowHits 0 # Number of row buffer hits during writes 236595SN/Asystem.physmem.readRowHitRate 90.64 # Row buffer hit rate for reads 2372623SN/Asystem.physmem.writeRowHitRate nan # Row buffer hit rate for writes 238595SN/Asystem.physmem.avgGap 26913503.08 # Average gap between requests 2392390SN/Asystem.membus.throughput 2376658 # Throughput (bytes/s) 2401080SN/Asystem.membus.trans_dist::ReadReq 3834 # Transaction distribution 241595SN/Asystem.membus.trans_dist::ReadResp 3831 # Transaction distribution 2421080SN/Asystem.membus.trans_dist::UpgradeReq 155 # Transaction distribution 2431080SN/Asystem.membus.trans_dist::UpgradeResp 155 # Transaction distribution 244595SN/Asystem.membus.trans_dist::ReadExReq 1529 # Transaction distribution 2452683Sktlim@umich.edusystem.membus.trans_dist::ReadExResp 1529 # Transaction distribution 2461080SN/Asystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11033 # Packet count per connected master and slave (bytes) 2471080SN/Asystem.membus.pkt_count_system.cpu.l2cache.mem_side::total 11033 # Packet count per connected master and slave (bytes) 2481080SN/Asystem.membus.pkt_count::total 11033 # Packet count per connected master and slave (bytes) 2491121SN/Asystem.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 343040 # Cumulative packet size per connected master and slave (bytes) 2502107SN/Asystem.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 343040 # Cumulative packet size per connected master and slave (bytes) 2511089SN/Asystem.membus.tot_pkt_size::total 343040 # Cumulative packet size per connected master and slave (bytes) 2521080SN/Asystem.membus.data_through_bus 343040 # Total data (bytes) 2531089SN/Asystem.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 2541080SN/Asystem.membus.reqLayer0.occupancy 6990500 # Layer occupancy (ticks) 2551080SN/Asystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 2561080SN/Asystem.membus.respLayer1.occupancy 50919845 # Layer occupancy (ticks) 257595SN/Asystem.membus.respLayer1.utilization 0.0 # Layer utilization (%) 2582683Sktlim@umich.edusystem.cpu.branchPred.lookups 18643050 # Number of BP lookups 2591080SN/Asystem.cpu.branchPred.condPredicted 18643050 # Number of conditional branches predicted 2602090SN/Asystem.cpu.branchPred.condIncorrect 1490032 # Number of conditional branches incorrect 2611080SN/Asystem.cpu.branchPred.BTBLookups 11410312 # Number of BTB lookups 262595SN/Asystem.cpu.branchPred.BTBHits 10785938 # Number of BTB hits 2632683Sktlim@umich.edusystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 2642683Sktlim@umich.edusystem.cpu.branchPred.BTBHitPct 94.527985 # BTB Hit Percentage 265595SN/Asystem.cpu.branchPred.usedRAS 1319504 # Number of times the RAS was used to get a target. 2662683Sktlim@umich.edusystem.cpu.branchPred.RASInCorrect 23183 # Number of incorrect RAS predictions. 2671098SN/Asystem.cpu.workload.num_syscalls 400 # Number of system calls 2681098SN/Asystem.cpu.numCycles 288958646 # number of cpu cycles simulated 2691098SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 2702683Sktlim@umich.edusystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 2711098SN/Asystem.cpu.fetch.icacheStallCycles 23449793 # Number of cycles fetch is stalled on an Icache miss 2721098SN/Asystem.cpu.fetch.Insts 206693394 # Number of instructions fetch has processed 2731098SN/Asystem.cpu.fetch.Branches 18643050 # Number of branches that fetch encountered 2742012SN/Asystem.cpu.fetch.predictedBranches 12105442 # Number of branches that fetch has predicted taken 2751098SN/Asystem.cpu.fetch.Cycles 54202287 # Number of cycles fetch has run and was not squashing or blocked 2761098SN/Asystem.cpu.fetch.SquashCycles 15520872 # Number of cycles fetch has spent squashing 277595SN/Asystem.cpu.fetch.BlockedCycles 177854529 # Number of cycles fetch has spent blocked 2782205SN/Asystem.cpu.fetch.MiscStallCycles 1763 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 2792205SN/Asystem.cpu.fetch.PendingTrapStallCycles 10399 # Number of stall cycles due to pending traps 2802205SN/Asystem.cpu.fetch.IcacheWaitRetryStallCycles 75 # Number of stall cycles due to full MSHR 281595SN/Asystem.cpu.fetch.CacheLines 22344441 # Number of cache lines fetched 2822390SN/Asystem.cpu.fetch.IcacheSquashes 223502 # Number of outstanding Icache misses that were squashed 2832420SN/Asystem.cpu.fetch.rateDist::samples 269290652 # Number of instructions fetched each cycle (Total) 2842423SN/Asystem.cpu.fetch.rateDist::mean 1.269559 # Number of instructions fetched each cycle (Total) 2852390SN/Asystem.cpu.fetch.rateDist::stdev 2.757534 # Number of instructions fetched each cycle (Total) 286595SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 287595SN/Asystem.cpu.fetch.rateDist::0 216527015 80.41% 80.41% # Number of instructions fetched each cycle (Total) 2881858SN/Asystem.cpu.fetch.rateDist::1 2848467 1.06% 81.46% # Number of instructions fetched each cycle (Total) 2892SN/Asystem.cpu.fetch.rateDist::2 2311919 0.86% 82.32% # Number of instructions fetched each cycle (Total) 2902623SN/Asystem.cpu.fetch.rateDist::3 2635920 0.98% 83.30% # Number of instructions fetched each cycle (Total) 2912SN/Asystem.cpu.fetch.rateDist::4 3216253 1.19% 84.50% # Number of instructions fetched each cycle (Total) 2922680Sktlim@umich.edusystem.cpu.fetch.rateDist::5 3385278 1.26% 85.75% # Number of instructions fetched each cycle (Total) 2932SN/Asystem.cpu.fetch.rateDist::6 3830479 1.42% 87.18% # Number of instructions fetched each cycle (Total) 2942SN/Asystem.cpu.fetch.rateDist::7 2556488 0.95% 88.12% # Number of instructions fetched each cycle (Total) 2952SN/Asystem.cpu.fetch.rateDist::8 31978833 11.88% 100.00% # Number of instructions fetched each cycle (Total) 2961858SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 2972SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 2982623SN/Asystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 2992SN/Asystem.cpu.fetch.rateDist::total 269290652 # Number of instructions fetched each cycle (Total) 3002SN/Asystem.cpu.fetch.branchRate 0.064518 # Number of branch fetches per cycle 3012SN/Asystem.cpu.fetch.rate 0.715304 # Number of inst fetches per cycle 3022683Sktlim@umich.edusystem.cpu.decode.IdleCycles 36876732 # Number of cycles decode is idle 3032SN/Asystem.cpu.decode.BlockedCycles 166835033 # Number of cycles decode is blocked 3042683Sktlim@umich.edusystem.cpu.decode.RunCycles 41579230 # Number of cycles decode is running 3052SN/Asystem.cpu.decode.UnblockCycles 10227851 # Number of cycles decode is unblocking 3062SN/Asystem.cpu.decode.SquashCycles 13771806 # Number of cycles decode is squashing 3072SN/Asystem.cpu.decode.DecodedInsts 335978387 # Number of instructions handled by decode 3082SN/Asystem.cpu.rename.SquashCycles 13771806 # Number of cycles rename is squashing 3092SN/Asystem.cpu.rename.IdleCycles 44930878 # Number of cycles rename is idle 3102623SN/Asystem.cpu.rename.BlockCycles 116570981 # Number of cycles rename is blocking 3112SN/Asystem.cpu.rename.serializeStallCycles 32723 # count of cycles rename stalled for serializing inst 3121858SN/Asystem.cpu.rename.RunCycles 42705730 # Number of cycles rename is running 3132683Sktlim@umich.edusystem.cpu.rename.UnblockCycles 51278534 # Number of cycles rename is unblocking 3142SN/Asystem.cpu.rename.RenamedInsts 329616672 # Number of instructions processed by rename 3152SN/Asystem.cpu.rename.ROBFullEvents 10920 # Number of times rename has blocked due to ROB full 3161133SN/Asystem.cpu.rename.IQFullEvents 26000838 # Number of times rename has blocked due to IQ full 3172SN/Asystem.cpu.rename.LSQFullEvents 22678371 # Number of times rename has blocked due to LSQ full 3182683Sktlim@umich.edusystem.cpu.rename.RenamedOperands 382329896 # Number of destination operands rename has renamed 3192107SN/Asystem.cpu.rename.RenameLookups 917574751 # Number of register rename lookups that rename has made 3202107SN/Asystem.cpu.rename.int_rename_lookups 605864950 # Number of integer rename lookups 3212683Sktlim@umich.edusystem.cpu.rename.fp_rename_lookups 4114395 # Number of floating rename lookups 3222SN/Asystem.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed 3232107SN/Asystem.cpu.rename.UndoneMaps 122900446 # Number of HB maps that are undone due to squashing 3242SN/Asystem.cpu.rename.serializingInsts 2069 # count of serializing insts renamed 3252SN/Asystem.cpu.rename.tempSerializingInsts 2059 # count of temporary serializing insts renamed 3262SN/Asystem.cpu.rename.skidInsts 104883314 # count of insts added to the skid buffer 3272SN/Asystem.cpu.memDep0.insertedLoads 84491871 # Number of loads inserted to the mem dependence unit. 3282SN/Asystem.cpu.memDep0.insertedStores 30099442 # Number of stores inserted to the mem dependence unit. 3292683Sktlim@umich.edusystem.cpu.memDep0.conflictingLoads 58238426 # Number of conflicting loads. 3302107SN/Asystem.cpu.memDep0.conflictingStores 18921052 # Number of conflicting stores. 3312107SN/Asystem.cpu.iq.iqInstsAdded 322680314 # Number of instructions added to the IQ (excludes non-spec) 3322SN/Asystem.cpu.iq.iqNonSpecInstsAdded 4268 # Number of non-speculative instructions added to the IQ 3332SN/Asystem.cpu.iq.iqInstsIssued 260554870 # Number of instructions issued 3342SN/Asystem.cpu.iq.iqSquashedInstsIssued 118520 # Number of squashed instructions issued 3352SN/Asystem.cpu.iq.iqSquashedInstsExamined 100937084 # Number of squashed instructions iterated over during squash; mainly for profiling 3362SN/Asystem.cpu.iq.iqSquashedOperandsExamined 209936848 # Number of squashed operands that are examined and possibly removed from graph 3372SN/Asystem.cpu.iq.iqSquashedNonSpecRemoved 3023 # Number of squashed non-spec instructions that were removed 3382SN/Asystem.cpu.iq.issued_per_cycle::samples 269290652 # Number of insts issued each cycle 3392683Sktlim@umich.edusystem.cpu.iq.issued_per_cycle::mean 0.967560 # Number of insts issued each cycle 3402SN/Asystem.cpu.iq.issued_per_cycle::stdev 1.344979 # Number of insts issued each cycle 3412SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 3422683Sktlim@umich.edusystem.cpu.iq.issued_per_cycle::0 143216818 53.18% 53.18% # Number of insts issued each cycle 3432683Sktlim@umich.edusystem.cpu.iq.issued_per_cycle::1 55391998 20.57% 73.75% # Number of insts issued each cycle 3442683Sktlim@umich.edusystem.cpu.iq.issued_per_cycle::2 34136198 12.68% 86.43% # Number of insts issued each cycle 3452234SN/Asystem.cpu.iq.issued_per_cycle::3 19056794 7.08% 93.51% # Number of insts issued each cycle 3462680Sktlim@umich.edusystem.cpu.iq.issued_per_cycle::4 10890991 4.04% 97.55% # Number of insts issued each cycle 3472SN/Asystem.cpu.iq.issued_per_cycle::5 4174838 1.55% 99.10% # Number of insts issued each cycle 3482SN/Asystem.cpu.iq.issued_per_cycle::6 1812713 0.67% 99.77% # Number of insts issued each cycle 3492683Sktlim@umich.edusystem.cpu.iq.issued_per_cycle::7 476754 0.18% 99.95% # Number of insts issued each cycle 3502SN/Asystem.cpu.iq.issued_per_cycle::8 133548 0.05% 100.00% # Number of insts issued each cycle 3512SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 3522SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 3532623SN/Asystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 3542SN/Asystem.cpu.iq.issued_per_cycle::total 269290652 # Number of insts issued each cycle 3552623SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 3562623SN/Asystem.cpu.iq.fu_full::IntAlu 129591 4.77% 4.77% # attempts to use FU when none available 3572662Sstever@eecs.umich.edusystem.cpu.iq.fu_full::IntMult 0 0.00% 4.77% # attempts to use FU when none available 3582623SN/Asystem.cpu.iq.fu_full::IntDiv 0 0.00% 4.77% # attempts to use FU when none available 3592623SN/Asystem.cpu.iq.fu_full::FloatAdd 0 0.00% 4.77% # attempts to use FU when none available 3602741Sksewell@umich.edusystem.cpu.iq.fu_full::FloatCmp 0 0.00% 4.77% # attempts to use FU when none available 3612741Sksewell@umich.edusystem.cpu.iq.fu_full::FloatCvt 0 0.00% 4.77% # attempts to use FU when none available 3622741Sksewell@umich.edusystem.cpu.iq.fu_full::FloatMult 0 0.00% 4.77% # attempts to use FU when none available 3632741Sksewell@umich.edusystem.cpu.iq.fu_full::FloatDiv 0 0.00% 4.77% # attempts to use FU when none available 3642683Sktlim@umich.edusystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.77% # attempts to use FU when none available 3652683Sktlim@umich.edusystem.cpu.iq.fu_full::SimdAdd 0 0.00% 4.77% # attempts to use FU when none available 3662741Sksewell@umich.edusystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.77% # attempts to use FU when none available 3672623SN/Asystem.cpu.iq.fu_full::SimdAlu 0 0.00% 4.77% # attempts to use FU when none available 3682683Sktlim@umich.edusystem.cpu.iq.fu_full::SimdCmp 0 0.00% 4.77% # attempts to use FU when none available 3692683Sktlim@umich.edusystem.cpu.iq.fu_full::SimdCvt 0 0.00% 4.77% # attempts to use FU when none available 3702683Sktlim@umich.edusystem.cpu.iq.fu_full::SimdMisc 0 0.00% 4.77% # attempts to use FU when none available 3712623SN/Asystem.cpu.iq.fu_full::SimdMult 0 0.00% 4.77% # attempts to use FU when none available 3722683Sktlim@umich.edusystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.77% # attempts to use FU when none available 3732623SN/Asystem.cpu.iq.fu_full::SimdShift 0 0.00% 4.77% # attempts to use FU when none available 3742623SN/Asystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.77% # attempts to use FU when none available 3752623SN/Asystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.77% # attempts to use FU when none available 3762623SN/Asystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.77% # attempts to use FU when none available 3772623SN/Asystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.77% # attempts to use FU when none available 3782623SN/Asystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.77% # attempts to use FU when none available 3792623SN/Asystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.77% # attempts to use FU when none available 3802623SN/Asystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.77% # attempts to use FU when none available 3812SN/Asystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.77% # attempts to use FU when none available 3822683Sktlim@umich.edusystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.77% # attempts to use FU when none available 3832427SN/Asystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.77% # attempts to use FU when none available 3842683Sktlim@umich.edusystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.77% # attempts to use FU when none available 3852427SN/Asystem.cpu.iq.fu_full::MemRead 2286947 84.14% 88.91% # attempts to use FU when none available 3862SN/Asystem.cpu.iq.fu_full::MemWrite 301448 11.09% 100.00% # attempts to use FU when none available 3872623SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 3882623SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 3892623SN/Asystem.cpu.iq.FU_type_0::No_OpClass 1210947 0.46% 0.46% # Type of FU issued 3902SN/Asystem.cpu.iq.FU_type_0::IntAlu 162062878 62.20% 62.66% # Type of FU issued 3912683Sktlim@umich.edusystem.cpu.iq.FU_type_0::IntMult 788601 0.30% 62.97% # Type of FU issued 3922SN/Asystem.cpu.iq.FU_type_0::IntDiv 7035610 2.70% 65.67% # Type of FU issued 3932623SN/Asystem.cpu.iq.FU_type_0::FloatAdd 1446949 0.56% 66.22% # Type of FU issued 3942623SN/Asystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.22% # Type of FU issued 3952SN/Asystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.22% # Type of FU issued 3962623SN/Asystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.22% # Type of FU issued 3972623SN/Asystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.22% # Type of FU issued 3982683Sktlim@umich.edusystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.22% # Type of FU issued 3992470SN/Asystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.22% # Type of FU issued 4002680Sktlim@umich.edusystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.22% # Type of FU issued 4012683Sktlim@umich.edusystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.22% # Type of FU issued 4022623SN/Asystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.22% # Type of FU issued 4032623SN/Asystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.22% # Type of FU issued 4042623SN/Asystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.22% # Type of FU issued 4052623SN/Asystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.22% # Type of FU issued 4062623SN/Asystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.22% # Type of FU issued 4072623SN/Asystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.22% # Type of FU issued 4082683Sktlim@umich.edusystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.22% # Type of FU issued 4092623SN/Asystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.22% # Type of FU issued 4102623SN/Asystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.22% # Type of FU issued 4112623SN/Asystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.22% # Type of FU issued 4122623SN/Asystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.22% # Type of FU issued 4132623SN/Asystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.22% # Type of FU issued 4142623SN/Asystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.22% # Type of FU issued 4152623SN/Asystem.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.22% # Type of FU issued 4162683Sktlim@umich.edusystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.22% # Type of FU issued 4172623SN/Asystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.22% # Type of FU issued 4182683Sktlim@umich.edusystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.22% # Type of FU issued 4192683Sktlim@umich.edusystem.cpu.iq.FU_type_0::MemRead 65458486 25.12% 91.34% # Type of FU issued 4202683Sktlim@umich.edusystem.cpu.iq.FU_type_0::MemWrite 22551399 8.66% 100.00% # Type of FU issued 4212623SN/Asystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 4222683Sktlim@umich.edusystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 4232623SN/Asystem.cpu.iq.FU_type_0::total 260554870 # Type of FU issued 4242420SN/Asystem.cpu.iq.rate 0.901703 # Inst issue rate 4252SN/Asystem.cpu.iq.fu_busy_cnt 2717986 # FU busy when requested 4262623SN/Asystem.cpu.iq.fu_busy_rate 0.010432 # FU busy rate (busy events/executed inst) 4272623SN/Asystem.cpu.iq.int_inst_queue_reads 788349666 # Number of integer instruction queue reads 4282SN/Asystem.cpu.iq.int_inst_queue_writes 420314195 # Number of integer instruction queue writes 4292SN/Asystem.cpu.iq.int_inst_queue_wakeup_accesses 255192215 # Number of integer instruction queue wakeup accesses 4302623SN/Asystem.cpu.iq.fp_inst_queue_reads 4887232 # Number of floating instruction queue reads 4312623SN/Asystem.cpu.iq.fp_inst_queue_writes 3589351 # Number of floating instruction queue writes 4322623SN/Asystem.cpu.iq.fp_inst_queue_wakeup_accesses 2349681 # Number of floating instruction queue wakeup accesses 4332623SN/Asystem.cpu.iq.int_alu_accesses 259602195 # Number of integer alu accesses 4342SN/Asystem.cpu.iq.fp_alu_accesses 2459714 # Number of floating point alu accesses 4352683Sktlim@umich.edusystem.cpu.iew.lsq.thread0.forwLoads 18922795 # Number of loads that had data forwarded from stores 4362644Sstever@eecs.umich.edusystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 4372644Sstever@eecs.umich.edusystem.cpu.iew.lsq.thread0.squashedLoads 27842284 # Number of loads squashed 4382644Sstever@eecs.umich.edusystem.cpu.iew.lsq.thread0.ignoredResponses 26598 # Number of memory responses ignored because the instruction is squashed 4392644Sstever@eecs.umich.edusystem.cpu.iew.lsq.thread0.memOrderViolation 287421 # Number of memory ordering violations 4402623SN/Asystem.cpu.iew.lsq.thread0.squashedStores 9583725 # Number of stores squashed 4412SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 4422SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 4432623SN/Asystem.cpu.iew.lsq.thread0.rescheduledLoads 49875 # Number of loads that were rescheduled 4442623SN/Asystem.cpu.iew.lsq.thread0.cacheBlocked 33 # Number of times an access to memory failed due to the cache being blocked 4452623SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 4462090SN/Asystem.cpu.iew.iewSquashCycles 13771806 # Number of cycles IEW is squashing 4472680Sktlim@umich.edusystem.cpu.iew.iewBlockCycles 85094278 # Number of cycles IEW is blocking 4482SN/Asystem.cpu.iew.iewUnblockCycles 5458618 # Number of cycles IEW is unblocking 4492SN/Asystem.cpu.iew.iewDispatchedInsts 322684582 # Number of instructions dispatched to IQ 4502SN/Asystem.cpu.iew.iewDispSquashedInsts 133416 # Number of squashed instructions skipped by dispatch 4512683Sktlim@umich.edusystem.cpu.iew.iewDispLoadInsts 84491871 # Number of dispatched load instructions 4522623SN/Asystem.cpu.iew.iewDispStoreInsts 30099442 # Number of dispatched store instructions 4532683Sktlim@umich.edusystem.cpu.iew.iewDispNonSpecInsts 2045 # Number of dispatched non-speculative instructions 4542251SN/Asystem.cpu.iew.iewIQFullEvents 2689502 # Number of times the IQ has become full, causing a stall 4552683Sktlim@umich.edusystem.cpu.iew.iewLSQFullEvents 13828 # Number of times the LSQ has become full, causing a stall 4562683Sktlim@umich.edusystem.cpu.iew.memOrderViolationEvents 287421 # Number of memory order violations 4572935Sksewell@umich.edusystem.cpu.iew.predictedTakenIncorrect 641114 # Number of branches that were predicted taken incorrectly 4582251SN/Asystem.cpu.iew.predictedNotTakenIncorrect 899581 # Number of branches that were predicted not taken incorrectly 4592251SN/Asystem.cpu.iew.branchMispredicts 1540695 # Number of branch mispredicts detected at execute 4602SN/Asystem.cpu.iew.iewExecutedInsts 258780631 # Number of executed instructions 4612SN/Asystem.cpu.iew.iewExecLoadInsts 64687698 # Number of load instructions executed 4621858SN/Asystem.cpu.iew.iewExecSquashedInsts 1774239 # Number of squashed instructions skipped in execute 4632SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 4642SN/Asystem.cpu.iew.exec_nop 0 # number of nop insts executed 4652683Sktlim@umich.edusystem.cpu.iew.exec_refs 87035316 # number of memory reference insts executed 4662680Sktlim@umich.edusystem.cpu.iew.exec_branches 14266808 # Number of branches executed 4672683Sktlim@umich.edusystem.cpu.iew.exec_stores 22347618 # Number of stores executed 4682SN/Asystem.cpu.iew.exec_rate 0.895563 # Inst execution rate 4692SN/Asystem.cpu.iew.wb_sent 258140972 # cumulative count of insts sent to commit 4702SN/Asystem.cpu.iew.wb_count 257541896 # cumulative count of insts written-back 471system.cpu.iew.wb_producers 206006775 # num instructions producing a value 472system.cpu.iew.wb_consumers 369206880 # num instructions consuming a value 473system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 474system.cpu.iew.wb_rate 0.891276 # insts written-back per cycle 475system.cpu.iew.wb_fanout 0.557971 # average fanout of values written-back 476system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 477system.cpu.commit.commitSquashedInsts 101393363 # The number of squashed insts skipped by commit 478system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards 479system.cpu.commit.branchMispredicts 1491544 # The number of times a branch was mispredicted 480system.cpu.commit.committed_per_cycle::samples 255518846 # Number of insts commited each cycle 481system.cpu.commit.committed_per_cycle::mean 0.866329 # Number of insts commited each cycle 482system.cpu.commit.committed_per_cycle::stdev 1.656611 # Number of insts commited each cycle 483system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 484system.cpu.commit.committed_per_cycle::0 156315405 61.18% 61.18% # Number of insts commited each cycle 485system.cpu.commit.committed_per_cycle::1 57071451 22.34% 83.51% # Number of insts commited each cycle 486system.cpu.commit.committed_per_cycle::2 14008929 5.48% 88.99% # Number of insts commited each cycle 487system.cpu.commit.committed_per_cycle::3 12048531 4.72% 93.71% # Number of insts commited each cycle 488system.cpu.commit.committed_per_cycle::4 4172668 1.63% 95.34% # Number of insts commited each cycle 489system.cpu.commit.committed_per_cycle::5 2970306 1.16% 96.50% # Number of insts commited each cycle 490system.cpu.commit.committed_per_cycle::6 908783 0.36% 96.86% # Number of insts commited each cycle 491system.cpu.commit.committed_per_cycle::7 1048602 0.41% 97.27% # Number of insts commited each cycle 492system.cpu.commit.committed_per_cycle::8 6974171 2.73% 100.00% # Number of insts commited each cycle 493system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 494system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 495system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 496system.cpu.commit.committed_per_cycle::total 255518846 # Number of insts commited each cycle 497system.cpu.commit.committedInsts 132071192 # Number of instructions committed 498system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed 499system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 500system.cpu.commit.refs 77165304 # Number of memory references committed 501system.cpu.commit.loads 56649587 # Number of loads committed 502system.cpu.commit.membars 0 # Number of memory barriers committed 503system.cpu.commit.branches 12326938 # Number of branches committed 504system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. 505system.cpu.commit.int_insts 219019985 # Number of committed integer instructions. 506system.cpu.commit.function_calls 797818 # Number of function calls committed. 507system.cpu.commit.bw_lim_events 6974171 # number cycles where commit BW limit reached 508system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 509system.cpu.rob.rob_reads 571301422 # The number of ROB reads 510system.cpu.rob.rob_writes 659310799 # The number of ROB writes 511system.cpu.timesIdled 5931788 # Number of times that the entire CPU went into an idle state and unscheduled itself 512system.cpu.idleCycles 19667994 # Total number of cycles that the CPU has spent unscheduled due to idling 513system.cpu.committedInsts 132071192 # Number of Instructions Simulated 514system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated 515system.cpu.committedInsts_total 132071192 # Number of Instructions Simulated 516system.cpu.cpi 2.187901 # CPI: Cycles Per Instruction 517system.cpu.cpi_total 2.187901 # CPI: Total CPI of All Threads 518system.cpu.ipc 0.457059 # IPC: Instructions Per Cycle 519system.cpu.ipc_total 0.457059 # IPC: Total IPC of All Threads 520system.cpu.int_regfile_reads 451358394 # number of integer regfile reads 521system.cpu.int_regfile_writes 233998694 # number of integer regfile writes 522system.cpu.fp_regfile_reads 3217923 # number of floating regfile reads 523system.cpu.fp_regfile_writes 2009376 # number of floating regfile writes 524system.cpu.cc_regfile_reads 102822009 # number of cc regfile reads 525system.cpu.cc_regfile_writes 59823089 # number of cc regfile writes 526system.cpu.misc_regfile_reads 133360573 # number of misc regfile reads 527system.cpu.misc_regfile_writes 1689 # number of misc regfile writes 528system.cpu.toL2Bus.throughput 3892220 # Throughput (bytes/s) 529system.cpu.toL2Bus.trans_dist::ReadReq 7233 # Transaction distribution 530system.cpu.toL2Bus.trans_dist::ReadResp 7229 # Transaction distribution 531system.cpu.toL2Bus.trans_dist::Writeback 13 # Transaction distribution 532system.cpu.toL2Bus.trans_dist::UpgradeReq 156 # Transaction distribution 533system.cpu.toL2Bus.trans_dist::UpgradeResp 156 # Transaction distribution 534system.cpu.toL2Bus.trans_dist::ReadExReq 1536 # Transaction distribution 535system.cpu.toL2Bus.trans_dist::ReadExResp 1536 # Transaction distribution 536system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13381 # Packet count per connected master and slave (bytes) 537system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4322 # Packet count per connected master and slave (bytes) 538system.cpu.toL2Bus.pkt_count::total 17703 # Packet count per connected master and slave (bytes) 539system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 423168 # Cumulative packet size per connected master and slave (bytes) 540system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 128640 # Cumulative packet size per connected master and slave (bytes) 541system.cpu.toL2Bus.tot_pkt_size::total 551808 # Cumulative packet size per connected master and slave (bytes) 542system.cpu.toL2Bus.data_through_bus 551808 # Total data (bytes) 543system.cpu.toL2Bus.snoop_data_through_bus 9984 # Total snoop data (bytes) 544system.cpu.toL2Bus.reqLayer0.occupancy 4482000 # Layer occupancy (ticks) 545system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 546system.cpu.toL2Bus.respLayer0.occupancy 10834750 # Layer occupancy (ticks) 547system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 548system.cpu.toL2Bus.respLayer1.occupancy 3517155 # Layer occupancy (ticks) 549system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 550system.cpu.icache.tags.replacements 4647 # number of replacements 551system.cpu.icache.tags.tagsinuse 1626.526476 # Cycle average of tags in use 552system.cpu.icache.tags.total_refs 22335618 # Total number of references to valid blocks. 553system.cpu.icache.tags.sampled_refs 6612 # Sample count of references to valid blocks. 554system.cpu.icache.tags.avg_refs 3378.042650 # Average number of references to valid blocks. 555system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 556system.cpu.icache.tags.occ_blocks::cpu.inst 1626.526476 # Average occupied blocks per requestor 557system.cpu.icache.tags.occ_percent::cpu.inst 0.794202 # Average percentage of cache occupancy 558system.cpu.icache.tags.occ_percent::total 0.794202 # Average percentage of cache occupancy 559system.cpu.icache.ReadReq_hits::cpu.inst 22335618 # number of ReadReq hits 560system.cpu.icache.ReadReq_hits::total 22335618 # number of ReadReq hits 561system.cpu.icache.demand_hits::cpu.inst 22335618 # number of demand (read+write) hits 562system.cpu.icache.demand_hits::total 22335618 # number of demand (read+write) hits 563system.cpu.icache.overall_hits::cpu.inst 22335618 # number of overall hits 564system.cpu.icache.overall_hits::total 22335618 # number of overall hits 565system.cpu.icache.ReadReq_misses::cpu.inst 8823 # number of ReadReq misses 566system.cpu.icache.ReadReq_misses::total 8823 # number of ReadReq misses 567system.cpu.icache.demand_misses::cpu.inst 8823 # number of demand (read+write) misses 568system.cpu.icache.demand_misses::total 8823 # number of demand (read+write) misses 569system.cpu.icache.overall_misses::cpu.inst 8823 # number of overall misses 570system.cpu.icache.overall_misses::total 8823 # number of overall misses 571system.cpu.icache.ReadReq_miss_latency::cpu.inst 352032500 # number of ReadReq miss cycles 572system.cpu.icache.ReadReq_miss_latency::total 352032500 # number of ReadReq miss cycles 573system.cpu.icache.demand_miss_latency::cpu.inst 352032500 # number of demand (read+write) miss cycles 574system.cpu.icache.demand_miss_latency::total 352032500 # number of demand (read+write) miss cycles 575system.cpu.icache.overall_miss_latency::cpu.inst 352032500 # number of overall miss cycles 576system.cpu.icache.overall_miss_latency::total 352032500 # number of overall miss cycles 577system.cpu.icache.ReadReq_accesses::cpu.inst 22344441 # number of ReadReq accesses(hits+misses) 578system.cpu.icache.ReadReq_accesses::total 22344441 # number of ReadReq accesses(hits+misses) 579system.cpu.icache.demand_accesses::cpu.inst 22344441 # number of demand (read+write) accesses 580system.cpu.icache.demand_accesses::total 22344441 # number of demand (read+write) accesses 581system.cpu.icache.overall_accesses::cpu.inst 22344441 # number of overall (read+write) accesses 582system.cpu.icache.overall_accesses::total 22344441 # number of overall (read+write) accesses 583system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000395 # miss rate for ReadReq accesses 584system.cpu.icache.ReadReq_miss_rate::total 0.000395 # miss rate for ReadReq accesses 585system.cpu.icache.demand_miss_rate::cpu.inst 0.000395 # miss rate for demand accesses 586system.cpu.icache.demand_miss_rate::total 0.000395 # miss rate for demand accesses 587system.cpu.icache.overall_miss_rate::cpu.inst 0.000395 # miss rate for overall accesses 588system.cpu.icache.overall_miss_rate::total 0.000395 # miss rate for overall accesses 589system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39899.410631 # average ReadReq miss latency 590system.cpu.icache.ReadReq_avg_miss_latency::total 39899.410631 # average ReadReq miss latency 591system.cpu.icache.demand_avg_miss_latency::cpu.inst 39899.410631 # average overall miss latency 592system.cpu.icache.demand_avg_miss_latency::total 39899.410631 # average overall miss latency 593system.cpu.icache.overall_avg_miss_latency::cpu.inst 39899.410631 # average overall miss latency 594system.cpu.icache.overall_avg_miss_latency::total 39899.410631 # average overall miss latency 595system.cpu.icache.blocked_cycles::no_mshrs 978 # number of cycles access was blocked 596system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 597system.cpu.icache.blocked::no_mshrs 17 # number of cycles access was blocked 598system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 599system.cpu.icache.avg_blocked_cycles::no_mshrs 57.529412 # average number of cycles each access was blocked 600system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 601system.cpu.icache.fast_writes 0 # number of fast writes performed 602system.cpu.icache.cache_copies 0 # number of cache copies performed 603system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2054 # number of ReadReq MSHR hits 604system.cpu.icache.ReadReq_mshr_hits::total 2054 # number of ReadReq MSHR hits 605system.cpu.icache.demand_mshr_hits::cpu.inst 2054 # number of demand (read+write) MSHR hits 606system.cpu.icache.demand_mshr_hits::total 2054 # number of demand (read+write) MSHR hits 607system.cpu.icache.overall_mshr_hits::cpu.inst 2054 # number of overall MSHR hits 608system.cpu.icache.overall_mshr_hits::total 2054 # number of overall MSHR hits 609system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6769 # number of ReadReq MSHR misses 610system.cpu.icache.ReadReq_mshr_misses::total 6769 # number of ReadReq MSHR misses 611system.cpu.icache.demand_mshr_misses::cpu.inst 6769 # number of demand (read+write) MSHR misses 612system.cpu.icache.demand_mshr_misses::total 6769 # number of demand (read+write) MSHR misses 613system.cpu.icache.overall_mshr_misses::cpu.inst 6769 # number of overall MSHR misses 614system.cpu.icache.overall_mshr_misses::total 6769 # number of overall MSHR misses 615system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 262819250 # number of ReadReq MSHR miss cycles 616system.cpu.icache.ReadReq_mshr_miss_latency::total 262819250 # number of ReadReq MSHR miss cycles 617system.cpu.icache.demand_mshr_miss_latency::cpu.inst 262819250 # number of demand (read+write) MSHR miss cycles 618system.cpu.icache.demand_mshr_miss_latency::total 262819250 # number of demand (read+write) MSHR miss cycles 619system.cpu.icache.overall_mshr_miss_latency::cpu.inst 262819250 # number of overall MSHR miss cycles 620system.cpu.icache.overall_mshr_miss_latency::total 262819250 # number of overall MSHR miss cycles 621system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for ReadReq accesses 622system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000303 # mshr miss rate for ReadReq accesses 623system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for demand accesses 624system.cpu.icache.demand_mshr_miss_rate::total 0.000303 # mshr miss rate for demand accesses 625system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for overall accesses 626system.cpu.icache.overall_mshr_miss_rate::total 0.000303 # mshr miss rate for overall accesses 627system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 38826.894667 # average ReadReq mshr miss latency 628system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 38826.894667 # average ReadReq mshr miss latency 629system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 38826.894667 # average overall mshr miss latency 630system.cpu.icache.demand_avg_mshr_miss_latency::total 38826.894667 # average overall mshr miss latency 631system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 38826.894667 # average overall mshr miss latency 632system.cpu.icache.overall_avg_mshr_miss_latency::total 38826.894667 # average overall mshr miss latency 633system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 634system.cpu.l2cache.tags.replacements 0 # number of replacements 635system.cpu.l2cache.tags.tagsinuse 2554.251018 # Cycle average of tags in use 636system.cpu.l2cache.tags.total_refs 3246 # Total number of references to valid blocks. 637system.cpu.l2cache.tags.sampled_refs 3834 # Sample count of references to valid blocks. 638system.cpu.l2cache.tags.avg_refs 0.846635 # Average number of references to valid blocks. 639system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 640system.cpu.l2cache.tags.occ_blocks::writebacks 1.761986 # Average occupied blocks per requestor 641system.cpu.l2cache.tags.occ_blocks::cpu.inst 2240.158882 # Average occupied blocks per requestor 642system.cpu.l2cache.tags.occ_blocks::cpu.data 312.330149 # Average occupied blocks per requestor 643system.cpu.l2cache.tags.occ_percent::writebacks 0.000054 # Average percentage of cache occupancy 644system.cpu.l2cache.tags.occ_percent::cpu.inst 0.068364 # Average percentage of cache occupancy 645system.cpu.l2cache.tags.occ_percent::cpu.data 0.009532 # Average percentage of cache occupancy 646system.cpu.l2cache.tags.occ_percent::total 0.077950 # Average percentage of cache occupancy 647system.cpu.l2cache.ReadReq_hits::cpu.inst 3206 # number of ReadReq hits 648system.cpu.l2cache.ReadReq_hits::cpu.data 36 # number of ReadReq hits 649system.cpu.l2cache.ReadReq_hits::total 3242 # number of ReadReq hits 650system.cpu.l2cache.Writeback_hits::writebacks 13 # number of Writeback hits 651system.cpu.l2cache.Writeback_hits::total 13 # number of Writeback hits 652system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits 653system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits 654system.cpu.l2cache.ReadExReq_hits::cpu.data 7 # number of ReadExReq hits 655system.cpu.l2cache.ReadExReq_hits::total 7 # number of ReadExReq hits 656system.cpu.l2cache.demand_hits::cpu.inst 3206 # number of demand (read+write) hits 657system.cpu.l2cache.demand_hits::cpu.data 43 # number of demand (read+write) hits 658system.cpu.l2cache.demand_hits::total 3249 # number of demand (read+write) hits 659system.cpu.l2cache.overall_hits::cpu.inst 3206 # number of overall hits 660system.cpu.l2cache.overall_hits::cpu.data 43 # number of overall hits 661system.cpu.l2cache.overall_hits::total 3249 # number of overall hits 662system.cpu.l2cache.ReadReq_misses::cpu.inst 3407 # number of ReadReq misses 663system.cpu.l2cache.ReadReq_misses::cpu.data 428 # number of ReadReq misses 664system.cpu.l2cache.ReadReq_misses::total 3835 # number of ReadReq misses 665system.cpu.l2cache.UpgradeReq_misses::cpu.data 155 # number of UpgradeReq misses 666system.cpu.l2cache.UpgradeReq_misses::total 155 # number of UpgradeReq misses 667system.cpu.l2cache.ReadExReq_misses::cpu.data 1529 # number of ReadExReq misses 668system.cpu.l2cache.ReadExReq_misses::total 1529 # number of ReadExReq misses 669system.cpu.l2cache.demand_misses::cpu.inst 3407 # number of demand (read+write) misses 670system.cpu.l2cache.demand_misses::cpu.data 1957 # number of demand (read+write) misses 671system.cpu.l2cache.demand_misses::total 5364 # number of demand (read+write) misses 672system.cpu.l2cache.overall_misses::cpu.inst 3407 # number of overall misses 673system.cpu.l2cache.overall_misses::cpu.data 1957 # number of overall misses 674system.cpu.l2cache.overall_misses::total 5364 # number of overall misses 675system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 223827000 # number of ReadReq miss cycles 676system.cpu.l2cache.ReadReq_miss_latency::cpu.data 31029500 # number of ReadReq miss cycles 677system.cpu.l2cache.ReadReq_miss_latency::total 254856500 # number of ReadReq miss cycles 678system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 96683500 # number of ReadExReq miss cycles 679system.cpu.l2cache.ReadExReq_miss_latency::total 96683500 # number of ReadExReq miss cycles 680system.cpu.l2cache.demand_miss_latency::cpu.inst 223827000 # number of demand (read+write) miss cycles 681system.cpu.l2cache.demand_miss_latency::cpu.data 127713000 # number of demand (read+write) miss cycles 682system.cpu.l2cache.demand_miss_latency::total 351540000 # number of demand (read+write) miss cycles 683system.cpu.l2cache.overall_miss_latency::cpu.inst 223827000 # number of overall miss cycles 684system.cpu.l2cache.overall_miss_latency::cpu.data 127713000 # number of overall miss cycles 685system.cpu.l2cache.overall_miss_latency::total 351540000 # number of overall miss cycles 686system.cpu.l2cache.ReadReq_accesses::cpu.inst 6613 # number of ReadReq accesses(hits+misses) 687system.cpu.l2cache.ReadReq_accesses::cpu.data 464 # number of ReadReq accesses(hits+misses) 688system.cpu.l2cache.ReadReq_accesses::total 7077 # number of ReadReq accesses(hits+misses) 689system.cpu.l2cache.Writeback_accesses::writebacks 13 # number of Writeback accesses(hits+misses) 690system.cpu.l2cache.Writeback_accesses::total 13 # number of Writeback accesses(hits+misses) 691system.cpu.l2cache.UpgradeReq_accesses::cpu.data 156 # number of UpgradeReq accesses(hits+misses) 692system.cpu.l2cache.UpgradeReq_accesses::total 156 # number of UpgradeReq accesses(hits+misses) 693system.cpu.l2cache.ReadExReq_accesses::cpu.data 1536 # number of ReadExReq accesses(hits+misses) 694system.cpu.l2cache.ReadExReq_accesses::total 1536 # number of ReadExReq accesses(hits+misses) 695system.cpu.l2cache.demand_accesses::cpu.inst 6613 # number of demand (read+write) accesses 696system.cpu.l2cache.demand_accesses::cpu.data 2000 # number of demand (read+write) accesses 697system.cpu.l2cache.demand_accesses::total 8613 # number of demand (read+write) accesses 698system.cpu.l2cache.overall_accesses::cpu.inst 6613 # number of overall (read+write) accesses 699system.cpu.l2cache.overall_accesses::cpu.data 2000 # number of overall (read+write) accesses 700system.cpu.l2cache.overall_accesses::total 8613 # number of overall (read+write) accesses 701system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.515197 # miss rate for ReadReq accesses 702system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.922414 # miss rate for ReadReq accesses 703system.cpu.l2cache.ReadReq_miss_rate::total 0.541896 # miss rate for ReadReq accesses 704system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.993590 # miss rate for UpgradeReq accesses 705system.cpu.l2cache.UpgradeReq_miss_rate::total 0.993590 # miss rate for UpgradeReq accesses 706system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.995443 # miss rate for ReadExReq accesses 707system.cpu.l2cache.ReadExReq_miss_rate::total 0.995443 # miss rate for ReadExReq accesses 708system.cpu.l2cache.demand_miss_rate::cpu.inst 0.515197 # miss rate for demand accesses 709system.cpu.l2cache.demand_miss_rate::cpu.data 0.978500 # miss rate for demand accesses 710system.cpu.l2cache.demand_miss_rate::total 0.622780 # miss rate for demand accesses 711system.cpu.l2cache.overall_miss_rate::cpu.inst 0.515197 # miss rate for overall accesses 712system.cpu.l2cache.overall_miss_rate::cpu.data 0.978500 # miss rate for overall accesses 713system.cpu.l2cache.overall_miss_rate::total 0.622780 # miss rate for overall accesses 714system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65696.213678 # average ReadReq miss latency 715system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72498.831776 # average ReadReq miss latency 716system.cpu.l2cache.ReadReq_avg_miss_latency::total 66455.410691 # average ReadReq miss latency 717system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 63233.158927 # average ReadExReq miss latency 718system.cpu.l2cache.ReadExReq_avg_miss_latency::total 63233.158927 # average ReadExReq miss latency 719system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65696.213678 # average overall miss latency 720system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65259.580991 # average overall miss latency 721system.cpu.l2cache.demand_avg_miss_latency::total 65536.912752 # average overall miss latency 722system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65696.213678 # average overall miss latency 723system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65259.580991 # average overall miss latency 724system.cpu.l2cache.overall_avg_miss_latency::total 65536.912752 # average overall miss latency 725system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 726system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 727system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 728system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 729system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 730system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 731system.cpu.l2cache.fast_writes 0 # number of fast writes performed 732system.cpu.l2cache.cache_copies 0 # number of cache copies performed 733system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3407 # number of ReadReq MSHR misses 734system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 428 # number of ReadReq MSHR misses 735system.cpu.l2cache.ReadReq_mshr_misses::total 3835 # number of ReadReq MSHR misses 736system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 155 # number of UpgradeReq MSHR misses 737system.cpu.l2cache.UpgradeReq_mshr_misses::total 155 # number of UpgradeReq MSHR misses 738system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1529 # number of ReadExReq MSHR misses 739system.cpu.l2cache.ReadExReq_mshr_misses::total 1529 # number of ReadExReq MSHR misses 740system.cpu.l2cache.demand_mshr_misses::cpu.inst 3407 # number of demand (read+write) MSHR misses 741system.cpu.l2cache.demand_mshr_misses::cpu.data 1957 # number of demand (read+write) MSHR misses 742system.cpu.l2cache.demand_mshr_misses::total 5364 # number of demand (read+write) MSHR misses 743system.cpu.l2cache.overall_mshr_misses::cpu.inst 3407 # number of overall MSHR misses 744system.cpu.l2cache.overall_mshr_misses::cpu.data 1957 # number of overall MSHR misses 745system.cpu.l2cache.overall_mshr_misses::total 5364 # number of overall MSHR misses 746system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 180933000 # number of ReadReq MSHR miss cycles 747system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25685000 # number of ReadReq MSHR miss cycles 748system.cpu.l2cache.ReadReq_mshr_miss_latency::total 206618000 # number of ReadReq MSHR miss cycles 749system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1550155 # number of UpgradeReq MSHR miss cycles 750system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1550155 # number of UpgradeReq MSHR miss cycles 751system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 77075500 # number of ReadExReq MSHR miss cycles 752system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 77075500 # number of ReadExReq MSHR miss cycles 753system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 180933000 # number of demand (read+write) MSHR miss cycles 754system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 102760500 # number of demand (read+write) MSHR miss cycles 755system.cpu.l2cache.demand_mshr_miss_latency::total 283693500 # number of demand (read+write) MSHR miss cycles 756system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 180933000 # number of overall MSHR miss cycles 757system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 102760500 # number of overall MSHR miss cycles 758system.cpu.l2cache.overall_mshr_miss_latency::total 283693500 # number of overall MSHR miss cycles 759system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.515197 # mshr miss rate for ReadReq accesses 760system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.922414 # mshr miss rate for ReadReq accesses 761system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.541896 # mshr miss rate for ReadReq accesses 762system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.993590 # mshr miss rate for UpgradeReq accesses 763system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.993590 # mshr miss rate for UpgradeReq accesses 764system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.995443 # mshr miss rate for ReadExReq accesses 765system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.995443 # mshr miss rate for ReadExReq accesses 766system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.515197 # mshr miss rate for demand accesses 767system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.978500 # mshr miss rate for demand accesses 768system.cpu.l2cache.demand_mshr_miss_rate::total 0.622780 # mshr miss rate for demand accesses 769system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.515197 # mshr miss rate for overall accesses 770system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.978500 # mshr miss rate for overall accesses 771system.cpu.l2cache.overall_mshr_miss_rate::total 0.622780 # mshr miss rate for overall accesses 772system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53106.251834 # average ReadReq mshr miss latency 773system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60011.682243 # average ReadReq mshr miss latency 774system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53876.923077 # average ReadReq mshr miss latency 775system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 776system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency 777system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50409.090909 # average ReadExReq mshr miss latency 778system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50409.090909 # average ReadExReq mshr miss latency 779system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53106.251834 # average overall mshr miss latency 780system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52509.197752 # average overall mshr miss latency 781system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52888.422819 # average overall mshr miss latency 782system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53106.251834 # average overall mshr miss latency 783system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52509.197752 # average overall mshr miss latency 784system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52888.422819 # average overall mshr miss latency 785system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 786system.cpu.dcache.tags.replacements 54 # number of replacements 787system.cpu.dcache.tags.tagsinuse 1431.071380 # Cycle average of tags in use 788system.cpu.dcache.tags.total_refs 66125331 # Total number of references to valid blocks. 789system.cpu.dcache.tags.sampled_refs 1997 # Sample count of references to valid blocks. 790system.cpu.dcache.tags.avg_refs 33112.334001 # Average number of references to valid blocks. 791system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 792system.cpu.dcache.tags.occ_blocks::cpu.data 1431.071380 # Average occupied blocks per requestor 793system.cpu.dcache.tags.occ_percent::cpu.data 0.349383 # Average percentage of cache occupancy 794system.cpu.dcache.tags.occ_percent::total 0.349383 # Average percentage of cache occupancy 795system.cpu.dcache.ReadReq_hits::cpu.data 45611085 # number of ReadReq hits 796system.cpu.dcache.ReadReq_hits::total 45611085 # number of ReadReq hits 797system.cpu.dcache.WriteReq_hits::cpu.data 20514038 # number of WriteReq hits 798system.cpu.dcache.WriteReq_hits::total 20514038 # number of WriteReq hits 799system.cpu.dcache.demand_hits::cpu.data 66125123 # number of demand (read+write) hits 800system.cpu.dcache.demand_hits::total 66125123 # number of demand (read+write) hits 801system.cpu.dcache.overall_hits::cpu.data 66125123 # number of overall hits 802system.cpu.dcache.overall_hits::total 66125123 # number of overall hits 803system.cpu.dcache.ReadReq_misses::cpu.data 915 # number of ReadReq misses 804system.cpu.dcache.ReadReq_misses::total 915 # number of ReadReq misses 805system.cpu.dcache.WriteReq_misses::cpu.data 1693 # number of WriteReq misses 806system.cpu.dcache.WriteReq_misses::total 1693 # number of WriteReq misses 807system.cpu.dcache.demand_misses::cpu.data 2608 # number of demand (read+write) misses 808system.cpu.dcache.demand_misses::total 2608 # number of demand (read+write) misses 809system.cpu.dcache.overall_misses::cpu.data 2608 # number of overall misses 810system.cpu.dcache.overall_misses::total 2608 # number of overall misses 811system.cpu.dcache.ReadReq_miss_latency::cpu.data 55175302 # number of ReadReq miss cycles 812system.cpu.dcache.ReadReq_miss_latency::total 55175302 # number of ReadReq miss cycles 813system.cpu.dcache.WriteReq_miss_latency::cpu.data 106081155 # number of WriteReq miss cycles 814system.cpu.dcache.WriteReq_miss_latency::total 106081155 # number of WriteReq miss cycles 815system.cpu.dcache.demand_miss_latency::cpu.data 161256457 # number of demand (read+write) miss cycles 816system.cpu.dcache.demand_miss_latency::total 161256457 # number of demand (read+write) miss cycles 817system.cpu.dcache.overall_miss_latency::cpu.data 161256457 # number of overall miss cycles 818system.cpu.dcache.overall_miss_latency::total 161256457 # number of overall miss cycles 819system.cpu.dcache.ReadReq_accesses::cpu.data 45612000 # number of ReadReq accesses(hits+misses) 820system.cpu.dcache.ReadReq_accesses::total 45612000 # number of ReadReq accesses(hits+misses) 821system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) 822system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) 823system.cpu.dcache.demand_accesses::cpu.data 66127731 # number of demand (read+write) accesses 824system.cpu.dcache.demand_accesses::total 66127731 # number of demand (read+write) accesses 825system.cpu.dcache.overall_accesses::cpu.data 66127731 # number of overall (read+write) accesses 826system.cpu.dcache.overall_accesses::total 66127731 # number of overall (read+write) accesses 827system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses 828system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses 829system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000083 # miss rate for WriteReq accesses 830system.cpu.dcache.WriteReq_miss_rate::total 0.000083 # miss rate for WriteReq accesses 831system.cpu.dcache.demand_miss_rate::cpu.data 0.000039 # miss rate for demand accesses 832system.cpu.dcache.demand_miss_rate::total 0.000039 # miss rate for demand accesses 833system.cpu.dcache.overall_miss_rate::cpu.data 0.000039 # miss rate for overall accesses 834system.cpu.dcache.overall_miss_rate::total 0.000039 # miss rate for overall accesses 835system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60300.876503 # average ReadReq miss latency 836system.cpu.dcache.ReadReq_avg_miss_latency::total 60300.876503 # average ReadReq miss latency 837system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62658.685765 # average WriteReq miss latency 838system.cpu.dcache.WriteReq_avg_miss_latency::total 62658.685765 # average WriteReq miss latency 839system.cpu.dcache.demand_avg_miss_latency::cpu.data 61831.463574 # average overall miss latency 840system.cpu.dcache.demand_avg_miss_latency::total 61831.463574 # average overall miss latency 841system.cpu.dcache.overall_avg_miss_latency::cpu.data 61831.463574 # average overall miss latency 842system.cpu.dcache.overall_avg_miss_latency::total 61831.463574 # average overall miss latency 843system.cpu.dcache.blocked_cycles::no_mshrs 351 # number of cycles access was blocked 844system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 845system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked 846system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 847system.cpu.dcache.avg_blocked_cycles::no_mshrs 87.750000 # average number of cycles each access was blocked 848system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 849system.cpu.dcache.fast_writes 0 # number of fast writes performed 850system.cpu.dcache.cache_copies 0 # number of cache copies performed 851system.cpu.dcache.writebacks::writebacks 13 # number of writebacks 852system.cpu.dcache.writebacks::total 13 # number of writebacks 853system.cpu.dcache.ReadReq_mshr_hits::cpu.data 450 # number of ReadReq MSHR hits 854system.cpu.dcache.ReadReq_mshr_hits::total 450 # number of ReadReq MSHR hits 855system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits 856system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits 857system.cpu.dcache.demand_mshr_hits::cpu.data 452 # number of demand (read+write) MSHR hits 858system.cpu.dcache.demand_mshr_hits::total 452 # number of demand (read+write) MSHR hits 859system.cpu.dcache.overall_mshr_hits::cpu.data 452 # number of overall MSHR hits 860system.cpu.dcache.overall_mshr_hits::total 452 # number of overall MSHR hits 861system.cpu.dcache.ReadReq_mshr_misses::cpu.data 465 # number of ReadReq MSHR misses 862system.cpu.dcache.ReadReq_mshr_misses::total 465 # number of ReadReq MSHR misses 863system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1691 # number of WriteReq MSHR misses 864system.cpu.dcache.WriteReq_mshr_misses::total 1691 # number of WriteReq MSHR misses 865system.cpu.dcache.demand_mshr_misses::cpu.data 2156 # number of demand (read+write) MSHR misses 866system.cpu.dcache.demand_mshr_misses::total 2156 # number of demand (read+write) MSHR misses 867system.cpu.dcache.overall_mshr_misses::cpu.data 2156 # number of overall MSHR misses 868system.cpu.dcache.overall_mshr_misses::total 2156 # number of overall MSHR misses 869system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 31924750 # number of ReadReq MSHR miss cycles 870system.cpu.dcache.ReadReq_mshr_miss_latency::total 31924750 # number of ReadReq MSHR miss cycles 871system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 101851095 # number of WriteReq MSHR miss cycles 872system.cpu.dcache.WriteReq_mshr_miss_latency::total 101851095 # number of WriteReq MSHR miss cycles 873system.cpu.dcache.demand_mshr_miss_latency::cpu.data 133775845 # number of demand (read+write) MSHR miss cycles 874system.cpu.dcache.demand_mshr_miss_latency::total 133775845 # number of demand (read+write) MSHR miss cycles 875system.cpu.dcache.overall_mshr_miss_latency::cpu.data 133775845 # number of overall MSHR miss cycles 876system.cpu.dcache.overall_mshr_miss_latency::total 133775845 # number of overall MSHR miss cycles 877system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses 878system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses 879system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000082 # mshr miss rate for WriteReq accesses 880system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000082 # mshr miss rate for WriteReq accesses 881system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000033 # mshr miss rate for demand accesses 882system.cpu.dcache.demand_mshr_miss_rate::total 0.000033 # mshr miss rate for demand accesses 883system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000033 # mshr miss rate for overall accesses 884system.cpu.dcache.overall_mshr_miss_rate::total 0.000033 # mshr miss rate for overall accesses 885system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68655.376344 # average ReadReq mshr miss latency 886system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68655.376344 # average ReadReq mshr miss latency 887system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60231.280308 # average WriteReq mshr miss latency 888system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60231.280308 # average WriteReq mshr miss latency 889system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62048.165584 # average overall mshr miss latency 890system.cpu.dcache.demand_avg_mshr_miss_latency::total 62048.165584 # average overall mshr miss latency 891system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62048.165584 # average overall mshr miss latency 892system.cpu.dcache.overall_avg_mshr_miss_latency::total 62048.165584 # average overall mshr miss latency 893system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 894 895---------- End Simulation Statistics ---------- 896