stats.txt revision 9449:56610ab73040
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.082648 # Number of seconds simulated 4sim_ticks 82648140000 # Number of ticks simulated 5final_tick 82648140000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 31465 # Simulator instruction rate (inst/s) 8host_op_rate 52738 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 19690094 # Simulator tick rate (ticks/s) 10host_mem_usage 268216 # Number of bytes of host memory used 11host_seconds 4197.45 # Real time elapsed on the host 12sim_insts 132071192 # Number of instructions simulated 13sim_ops 221362961 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 217728 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 124416 # Number of bytes read from this memory 16system.physmem.bytes_read::total 342144 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 217728 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 217728 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 3402 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 1944 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 5346 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 2634397 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 1505370 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 4139766 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 2634397 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 2634397 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 2634397 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 1505370 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 4139766 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.readReqs 5348 # Total number of read requests seen 31system.physmem.writeReqs 0 # Total number of write requests seen 32system.physmem.cpureqs 5502 # Reqs generatd by CPU via cache - shady 33system.physmem.bytesRead 342144 # Total number of bytes read from memory 34system.physmem.bytesWritten 0 # Total number of bytes written to memory 35system.physmem.bytesConsumedRd 342144 # bytesRead derated as per pkt->getSize() 36system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 37system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q 38system.physmem.neitherReadNorWrite 154 # Reqs where no action is needed 39system.physmem.perBankRdReqs::0 306 # Track reads on a per bank basis 40system.physmem.perBankRdReqs::1 318 # Track reads on a per bank basis 41system.physmem.perBankRdReqs::2 313 # Track reads on a per bank basis 42system.physmem.perBankRdReqs::3 318 # Track reads on a per bank basis 43system.physmem.perBankRdReqs::4 308 # Track reads on a per bank basis 44system.physmem.perBankRdReqs::5 368 # Track reads on a per bank basis 45system.physmem.perBankRdReqs::6 328 # Track reads on a per bank basis 46system.physmem.perBankRdReqs::7 306 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::8 260 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::9 277 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::10 361 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::11 434 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::12 435 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::13 352 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::14 369 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::15 295 # Track reads on a per bank basis 55system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 56system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 57system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 58system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 59system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 60system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 61system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 62system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 73system.physmem.totGap 82648109000 # Total gap between requests 74system.physmem.readPktSize::0 0 # Categorize read packet sizes 75system.physmem.readPktSize::1 0 # Categorize read packet sizes 76system.physmem.readPktSize::2 0 # Categorize read packet sizes 77system.physmem.readPktSize::3 0 # Categorize read packet sizes 78system.physmem.readPktSize::4 0 # Categorize read packet sizes 79system.physmem.readPktSize::5 0 # Categorize read packet sizes 80system.physmem.readPktSize::6 5348 # Categorize read packet sizes 81system.physmem.readPktSize::7 0 # Categorize read packet sizes 82system.physmem.readPktSize::8 0 # Categorize read packet sizes 83system.physmem.writePktSize::0 0 # categorize write packet sizes 84system.physmem.writePktSize::1 0 # categorize write packet sizes 85system.physmem.writePktSize::2 0 # categorize write packet sizes 86system.physmem.writePktSize::3 0 # categorize write packet sizes 87system.physmem.writePktSize::4 0 # categorize write packet sizes 88system.physmem.writePktSize::5 0 # categorize write packet sizes 89system.physmem.writePktSize::6 0 # categorize write packet sizes 90system.physmem.writePktSize::7 0 # categorize write packet sizes 91system.physmem.writePktSize::8 0 # categorize write packet sizes 92system.physmem.neitherpktsize::0 0 # categorize neither packet sizes 93system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 94system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 95system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 96system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 97system.physmem.neitherpktsize::5 0 # categorize neither packet sizes 98system.physmem.neitherpktsize::6 154 # categorize neither packet sizes 99system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 100system.physmem.neitherpktsize::8 0 # categorize neither packet sizes 101system.physmem.rdQLenPdf::0 4185 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::1 926 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::2 200 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::3 33 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see 134system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 167system.physmem.totQLat 16873822 # Total cycles spent in queuing delays 168system.physmem.totMemAccLat 122447822 # Sum of mem lat for all requests 169system.physmem.totBusLat 21392000 # Total cycles spent in databus access 170system.physmem.totBankLat 84182000 # Total cycles spent in bank access 171system.physmem.avgQLat 3155.16 # Average queueing delay per request 172system.physmem.avgBankLat 15740.84 # Average bank access latency per request 173system.physmem.avgBusLat 4000.00 # Average bus latency per request 174system.physmem.avgMemAccLat 22896.00 # Average memory access latency 175system.physmem.avgRdBW 4.14 # Average achieved read bandwidth in MB/s 176system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s 177system.physmem.avgConsumedRdBW 4.14 # Average consumed read bandwidth in MB/s 178system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 179system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 180system.physmem.busUtil 0.03 # Data bus utilization in percentage 181system.physmem.avgRdQLen 0.00 # Average read queue length over time 182system.physmem.avgWrQLen 0.00 # Average write queue length over time 183system.physmem.readRowHits 4742 # Number of row buffer hits during reads 184system.physmem.writeRowHits 0 # Number of row buffer hits during writes 185system.physmem.readRowHitRate 88.67 # Row buffer hit rate for reads 186system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 187system.physmem.avgGap 15454021.88 # Average gap between requests 188system.cpu.workload.num_syscalls 400 # Number of system calls 189system.cpu.numCycles 165296281 # number of cpu cycles simulated 190system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 191system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 192system.cpu.BPredUnit.lookups 19953215 # Number of BP lookups 193system.cpu.BPredUnit.condPredicted 19953215 # Number of conditional branches predicted 194system.cpu.BPredUnit.condIncorrect 2011335 # Number of conditional branches incorrect 195system.cpu.BPredUnit.BTBLookups 13840594 # Number of BTB lookups 196system.cpu.BPredUnit.BTBHits 13098591 # Number of BTB hits 197system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 198system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. 199system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. 200system.cpu.fetch.icacheStallCycles 25831000 # Number of cycles fetch is stalled on an Icache miss 201system.cpu.fetch.Insts 218891152 # Number of instructions fetch has processed 202system.cpu.fetch.Branches 19953215 # Number of branches that fetch encountered 203system.cpu.fetch.predictedBranches 13098591 # Number of branches that fetch has predicted taken 204system.cpu.fetch.Cycles 57573712 # Number of cycles fetch has run and was not squashing or blocked 205system.cpu.fetch.SquashCycles 17632764 # Number of cycles fetch has spent squashing 206system.cpu.fetch.BlockedCycles 66415443 # Number of cycles fetch has spent blocked 207system.cpu.fetch.MiscStallCycles 240 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 208system.cpu.fetch.PendingTrapStallCycles 1579 # Number of stall cycles due to pending traps 209system.cpu.fetch.IcacheWaitRetryStallCycles 75 # Number of stall cycles due to full MSHR 210system.cpu.fetch.CacheLines 24446053 # Number of cache lines fetched 211system.cpu.fetch.IcacheSquashes 431779 # Number of outstanding Icache misses that were squashed 212system.cpu.fetch.rateDist::samples 165175969 # Number of instructions fetched each cycle (Total) 213system.cpu.fetch.rateDist::mean 2.190116 # Number of instructions fetched each cycle (Total) 214system.cpu.fetch.rateDist::stdev 3.327383 # Number of instructions fetched each cycle (Total) 215system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 216system.cpu.fetch.rateDist::0 109199449 66.11% 66.11% # Number of instructions fetched each cycle (Total) 217system.cpu.fetch.rateDist::1 3061509 1.85% 67.96% # Number of instructions fetched each cycle (Total) 218system.cpu.fetch.rateDist::2 2383315 1.44% 69.41% # Number of instructions fetched each cycle (Total) 219system.cpu.fetch.rateDist::3 2892599 1.75% 71.16% # Number of instructions fetched each cycle (Total) 220system.cpu.fetch.rateDist::4 3450171 2.09% 73.25% # Number of instructions fetched each cycle (Total) 221system.cpu.fetch.rateDist::5 3573015 2.16% 75.41% # Number of instructions fetched each cycle (Total) 222system.cpu.fetch.rateDist::6 4309284 2.61% 78.02% # Number of instructions fetched each cycle (Total) 223system.cpu.fetch.rateDist::7 2725915 1.65% 79.67% # Number of instructions fetched each cycle (Total) 224system.cpu.fetch.rateDist::8 33580712 20.33% 100.00% # Number of instructions fetched each cycle (Total) 225system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 226system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 227system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 228system.cpu.fetch.rateDist::total 165175969 # Number of instructions fetched each cycle (Total) 229system.cpu.fetch.branchRate 0.120712 # Number of branch fetches per cycle 230system.cpu.fetch.rate 1.324235 # Number of inst fetches per cycle 231system.cpu.decode.IdleCycles 38701150 # Number of cycles decode is idle 232system.cpu.decode.BlockedCycles 56465114 # Number of cycles decode is blocked 233system.cpu.decode.RunCycles 44698220 # Number of cycles decode is running 234system.cpu.decode.UnblockCycles 9957565 # Number of cycles decode is unblocking 235system.cpu.decode.SquashCycles 15353920 # Number of cycles decode is squashing 236system.cpu.decode.DecodedInsts 353610105 # Number of instructions handled by decode 237system.cpu.rename.SquashCycles 15353920 # Number of cycles rename is squashing 238system.cpu.rename.IdleCycles 46165738 # Number of cycles rename is idle 239system.cpu.rename.BlockCycles 14909579 # Number of cycles rename is blocking 240system.cpu.rename.serializeStallCycles 23078 # count of cycles rename stalled for serializing inst 241system.cpu.rename.RunCycles 46524421 # Number of cycles rename is running 242system.cpu.rename.UnblockCycles 42199233 # Number of cycles rename is unblocking 243system.cpu.rename.RenamedInsts 345243747 # Number of instructions processed by rename 244system.cpu.rename.ROBFullEvents 88 # Number of times rename has blocked due to ROB full 245system.cpu.rename.IQFullEvents 17893684 # Number of times rename has blocked due to IQ full 246system.cpu.rename.LSQFullEvents 22177130 # Number of times rename has blocked due to LSQ full 247system.cpu.rename.FullRegisterEvents 107 # Number of times there has been no free registers 248system.cpu.rename.RenamedOperands 398936501 # Number of destination operands rename has renamed 249system.cpu.rename.RenameLookups 960723880 # Number of register rename lookups that rename has made 250system.cpu.rename.int_rename_lookups 950976963 # Number of integer rename lookups 251system.cpu.rename.fp_rename_lookups 9746917 # Number of floating rename lookups 252system.cpu.rename.CommittedMaps 259428604 # Number of HB maps that are committed 253system.cpu.rename.UndoneMaps 139507897 # Number of HB maps that are undone due to squashing 254system.cpu.rename.serializingInsts 1674 # count of serializing insts renamed 255system.cpu.rename.tempSerializingInsts 1664 # count of temporary serializing insts renamed 256system.cpu.rename.skidInsts 90390787 # count of insts added to the skid buffer 257system.cpu.memDep0.insertedLoads 86672801 # Number of loads inserted to the mem dependence unit. 258system.cpu.memDep0.insertedStores 31756377 # Number of stores inserted to the mem dependence unit. 259system.cpu.memDep0.conflictingLoads 57758664 # Number of conflicting loads. 260system.cpu.memDep0.conflictingStores 18775058 # Number of conflicting stores. 261system.cpu.iq.iqInstsAdded 333623093 # Number of instructions added to the IQ (excludes non-spec) 262system.cpu.iq.iqNonSpecInstsAdded 3362 # Number of non-speculative instructions added to the IQ 263system.cpu.iq.iqInstsIssued 267451276 # Number of instructions issued 264system.cpu.iq.iqSquashedInstsIssued 258403 # Number of squashed instructions issued 265system.cpu.iq.iqSquashedInstsExamined 111810012 # Number of squashed instructions iterated over during squash; mainly for profiling 266system.cpu.iq.iqSquashedOperandsExamined 230098900 # Number of squashed operands that are examined and possibly removed from graph 267system.cpu.iq.iqSquashedNonSpecRemoved 2117 # Number of squashed non-spec instructions that were removed 268system.cpu.iq.issued_per_cycle::samples 165175969 # Number of insts issued each cycle 269system.cpu.iq.issued_per_cycle::mean 1.619190 # Number of insts issued each cycle 270system.cpu.iq.issued_per_cycle::stdev 1.505359 # Number of insts issued each cycle 271system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 272system.cpu.iq.issued_per_cycle::0 44964626 27.22% 27.22% # Number of insts issued each cycle 273system.cpu.iq.issued_per_cycle::1 46539597 28.18% 55.40% # Number of insts issued each cycle 274system.cpu.iq.issued_per_cycle::2 32801785 19.86% 75.26% # Number of insts issued each cycle 275system.cpu.iq.issued_per_cycle::3 19824720 12.00% 87.26% # Number of insts issued each cycle 276system.cpu.iq.issued_per_cycle::4 13230335 8.01% 95.27% # Number of insts issued each cycle 277system.cpu.iq.issued_per_cycle::5 4791341 2.90% 98.17% # Number of insts issued each cycle 278system.cpu.iq.issued_per_cycle::6 2351721 1.42% 99.59% # Number of insts issued each cycle 279system.cpu.iq.issued_per_cycle::7 529174 0.32% 99.91% # Number of insts issued each cycle 280system.cpu.iq.issued_per_cycle::8 142670 0.09% 100.00% # Number of insts issued each cycle 281system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 282system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 283system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 284system.cpu.iq.issued_per_cycle::total 165175969 # Number of insts issued each cycle 285system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 286system.cpu.iq.fu_full::IntAlu 137826 5.20% 5.20% # attempts to use FU when none available 287system.cpu.iq.fu_full::IntMult 0 0.00% 5.20% # attempts to use FU when none available 288system.cpu.iq.fu_full::IntDiv 0 0.00% 5.20% # attempts to use FU when none available 289system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.20% # attempts to use FU when none available 290system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.20% # attempts to use FU when none available 291system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.20% # attempts to use FU when none available 292system.cpu.iq.fu_full::FloatMult 0 0.00% 5.20% # attempts to use FU when none available 293system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.20% # attempts to use FU when none available 294system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.20% # attempts to use FU when none available 295system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.20% # attempts to use FU when none available 296system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.20% # attempts to use FU when none available 297system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.20% # attempts to use FU when none available 298system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.20% # attempts to use FU when none available 299system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.20% # attempts to use FU when none available 300system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.20% # attempts to use FU when none available 301system.cpu.iq.fu_full::SimdMult 0 0.00% 5.20% # attempts to use FU when none available 302system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.20% # attempts to use FU when none available 303system.cpu.iq.fu_full::SimdShift 0 0.00% 5.20% # attempts to use FU when none available 304system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.20% # attempts to use FU when none available 305system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.20% # attempts to use FU when none available 306system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.20% # attempts to use FU when none available 307system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.20% # attempts to use FU when none available 308system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.20% # attempts to use FU when none available 309system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.20% # attempts to use FU when none available 310system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.20% # attempts to use FU when none available 311system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.20% # attempts to use FU when none available 312system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.20% # attempts to use FU when none available 313system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.20% # attempts to use FU when none available 314system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.20% # attempts to use FU when none available 315system.cpu.iq.fu_full::MemRead 2250902 84.86% 90.05% # attempts to use FU when none available 316system.cpu.iq.fu_full::MemWrite 263908 9.95% 100.00% # attempts to use FU when none available 317system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 318system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 319system.cpu.iq.FU_type_0::No_OpClass 1212134 0.45% 0.45% # Type of FU issued 320system.cpu.iq.FU_type_0::IntAlu 174151286 65.12% 65.57% # Type of FU issued 321system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.57% # Type of FU issued 322system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.57% # Type of FU issued 323system.cpu.iq.FU_type_0::FloatAdd 1593879 0.60% 66.16% # Type of FU issued 324system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.16% # Type of FU issued 325system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.16% # Type of FU issued 326system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.16% # Type of FU issued 327system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.16% # Type of FU issued 328system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.16% # Type of FU issued 329system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.16% # Type of FU issued 330system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.16% # Type of FU issued 331system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.16% # Type of FU issued 332system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.16% # Type of FU issued 333system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.16% # Type of FU issued 334system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.16% # Type of FU issued 335system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.16% # Type of FU issued 336system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.16% # Type of FU issued 337system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.16% # Type of FU issued 338system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.16% # Type of FU issued 339system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.16% # Type of FU issued 340system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.16% # Type of FU issued 341system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.16% # Type of FU issued 342system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.16% # Type of FU issued 343system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.16% # Type of FU issued 344system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.16% # Type of FU issued 345system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.16% # Type of FU issued 346system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.16% # Type of FU issued 347system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.16% # Type of FU issued 348system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.16% # Type of FU issued 349system.cpu.iq.FU_type_0::MemRead 67229168 25.14% 91.30% # Type of FU issued 350system.cpu.iq.FU_type_0::MemWrite 23264809 8.70% 100.00% # Type of FU issued 351system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 352system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 353system.cpu.iq.FU_type_0::total 267451276 # Type of FU issued 354system.cpu.iq.rate 1.618011 # Inst issue rate 355system.cpu.iq.fu_busy_cnt 2652636 # FU busy when requested 356system.cpu.iq.fu_busy_rate 0.009918 # FU busy rate (busy events/executed inst) 357system.cpu.iq.int_inst_queue_reads 697648502 # Number of integer instruction queue reads 358system.cpu.iq.int_inst_queue_writes 441157156 # Number of integer instruction queue writes 359system.cpu.iq.int_inst_queue_wakeup_accesses 260237459 # Number of integer instruction queue wakeup accesses 360system.cpu.iq.fp_inst_queue_reads 5341058 # Number of floating instruction queue reads 361system.cpu.iq.fp_inst_queue_writes 4570848 # Number of floating instruction queue writes 362system.cpu.iq.fp_inst_queue_wakeup_accesses 2570585 # Number of floating instruction queue wakeup accesses 363system.cpu.iq.int_alu_accesses 266205797 # Number of integer alu accesses 364system.cpu.iq.fp_alu_accesses 2685981 # Number of floating point alu accesses 365system.cpu.iew.lsq.thread0.forwLoads 19039823 # Number of loads that had data forwarded from stores 366system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 367system.cpu.iew.lsq.thread0.squashedLoads 30023215 # Number of loads squashed 368system.cpu.iew.lsq.thread0.ignoredResponses 29490 # Number of memory responses ignored because the instruction is squashed 369system.cpu.iew.lsq.thread0.memOrderViolation 296813 # Number of memory ordering violations 370system.cpu.iew.lsq.thread0.squashedStores 11240660 # Number of stores squashed 371system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 372system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 373system.cpu.iew.lsq.thread0.rescheduledLoads 49425 # Number of loads that were rescheduled 374system.cpu.iew.lsq.thread0.cacheBlocked 13 # Number of times an access to memory failed due to the cache being blocked 375system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 376system.cpu.iew.iewSquashCycles 15353920 # Number of cycles IEW is squashing 377system.cpu.iew.iewBlockCycles 582358 # Number of cycles IEW is blocking 378system.cpu.iew.iewUnblockCycles 260686 # Number of cycles IEW is unblocking 379system.cpu.iew.iewDispatchedInsts 333626455 # Number of instructions dispatched to IQ 380system.cpu.iew.iewDispSquashedInsts 190123 # Number of squashed instructions skipped by dispatch 381system.cpu.iew.iewDispLoadInsts 86672801 # Number of dispatched load instructions 382system.cpu.iew.iewDispStoreInsts 31756377 # Number of dispatched store instructions 383system.cpu.iew.iewDispNonSpecInsts 1654 # Number of dispatched non-speculative instructions 384system.cpu.iew.iewIQFullEvents 146774 # Number of times the IQ has become full, causing a stall 385system.cpu.iew.iewLSQFullEvents 31153 # Number of times the LSQ has become full, causing a stall 386system.cpu.iew.memOrderViolationEvents 296813 # Number of memory order violations 387system.cpu.iew.predictedTakenIncorrect 1177159 # Number of branches that were predicted taken incorrectly 388system.cpu.iew.predictedNotTakenIncorrect 916050 # Number of branches that were predicted not taken incorrectly 389system.cpu.iew.branchMispredicts 2093209 # Number of branch mispredicts detected at execute 390system.cpu.iew.iewExecutedInsts 264577691 # Number of executed instructions 391system.cpu.iew.iewExecLoadInsts 66245889 # Number of load instructions executed 392system.cpu.iew.iewExecSquashedInsts 2873585 # Number of squashed instructions skipped in execute 393system.cpu.iew.exec_swp 0 # number of swp insts executed 394system.cpu.iew.exec_nop 0 # number of nop insts executed 395system.cpu.iew.exec_refs 89117815 # number of memory reference insts executed 396system.cpu.iew.exec_branches 14597039 # Number of branches executed 397system.cpu.iew.exec_stores 22871926 # Number of stores executed 398system.cpu.iew.exec_rate 1.600627 # Inst execution rate 399system.cpu.iew.wb_sent 263630467 # cumulative count of insts sent to commit 400system.cpu.iew.wb_count 262808044 # cumulative count of insts written-back 401system.cpu.iew.wb_producers 212084858 # num instructions producing a value 402system.cpu.iew.wb_consumers 375096623 # num instructions consuming a value 403system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 404system.cpu.iew.wb_rate 1.589921 # insts written-back per cycle 405system.cpu.iew.wb_fanout 0.565414 # average fanout of values written-back 406system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 407system.cpu.commit.commitSquashedInsts 112301239 # The number of squashed insts skipped by commit 408system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards 409system.cpu.commit.branchMispredicts 2011502 # The number of times a branch was mispredicted 410system.cpu.commit.committed_per_cycle::samples 149822049 # Number of insts commited each cycle 411system.cpu.commit.committed_per_cycle::mean 1.477506 # Number of insts commited each cycle 412system.cpu.commit.committed_per_cycle::stdev 1.946000 # Number of insts commited each cycle 413system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 414system.cpu.commit.committed_per_cycle::0 50722618 33.86% 33.86% # Number of insts commited each cycle 415system.cpu.commit.committed_per_cycle::1 57116806 38.12% 71.98% # Number of insts commited each cycle 416system.cpu.commit.committed_per_cycle::2 13820755 9.22% 81.20% # Number of insts commited each cycle 417system.cpu.commit.committed_per_cycle::3 12019830 8.02% 89.23% # Number of insts commited each cycle 418system.cpu.commit.committed_per_cycle::4 4145175 2.77% 91.99% # Number of insts commited each cycle 419system.cpu.commit.committed_per_cycle::5 2956577 1.97% 93.97% # Number of insts commited each cycle 420system.cpu.commit.committed_per_cycle::6 1072909 0.72% 94.68% # Number of insts commited each cycle 421system.cpu.commit.committed_per_cycle::7 994916 0.66% 95.35% # Number of insts commited each cycle 422system.cpu.commit.committed_per_cycle::8 6972463 4.65% 100.00% # Number of insts commited each cycle 423system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 424system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 425system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 426system.cpu.commit.committed_per_cycle::total 149822049 # Number of insts commited each cycle 427system.cpu.commit.committedInsts 132071192 # Number of instructions committed 428system.cpu.commit.committedOps 221362961 # Number of ops (including micro ops) committed 429system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 430system.cpu.commit.refs 77165303 # Number of memory references committed 431system.cpu.commit.loads 56649586 # Number of loads committed 432system.cpu.commit.membars 0 # Number of memory barriers committed 433system.cpu.commit.branches 12326938 # Number of branches committed 434system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. 435system.cpu.commit.int_insts 220339551 # Number of committed integer instructions. 436system.cpu.commit.function_calls 0 # Number of function calls committed. 437system.cpu.commit.bw_lim_events 6972463 # number cycles where commit BW limit reached 438system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 439system.cpu.rob.rob_reads 476513786 # The number of ROB reads 440system.cpu.rob.rob_writes 682717187 # The number of ROB writes 441system.cpu.timesIdled 2881 # Number of times that the entire CPU went into an idle state and unscheduled itself 442system.cpu.idleCycles 120312 # Total number of cycles that the CPU has spent unscheduled due to idling 443system.cpu.committedInsts 132071192 # Number of Instructions Simulated 444system.cpu.committedOps 221362961 # Number of Ops (including micro ops) Simulated 445system.cpu.committedInsts_total 132071192 # Number of Instructions Simulated 446system.cpu.cpi 1.251570 # CPI: Cycles Per Instruction 447system.cpu.cpi_total 1.251570 # CPI: Total CPI of All Threads 448system.cpu.ipc 0.798997 # IPC: Instructions Per Cycle 449system.cpu.ipc_total 0.798997 # IPC: Total IPC of All Threads 450system.cpu.int_regfile_reads 562635091 # number of integer regfile reads 451system.cpu.int_regfile_writes 298739906 # number of integer regfile writes 452system.cpu.fp_regfile_reads 3520410 # number of floating regfile reads 453system.cpu.fp_regfile_writes 2230055 # number of floating regfile writes 454system.cpu.misc_regfile_reads 137014018 # number of misc regfile reads 455system.cpu.misc_regfile_writes 844 # number of misc regfile writes 456system.cpu.icache.replacements 4732 # number of replacements 457system.cpu.icache.tagsinuse 1624.168426 # Cycle average of tags in use 458system.cpu.icache.total_refs 24437101 # Total number of references to valid blocks. 459system.cpu.icache.sampled_refs 6701 # Sample count of references to valid blocks. 460system.cpu.icache.avg_refs 3646.784211 # Average number of references to valid blocks. 461system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 462system.cpu.icache.occ_blocks::cpu.inst 1624.168426 # Average occupied blocks per requestor 463system.cpu.icache.occ_percent::cpu.inst 0.793051 # Average percentage of cache occupancy 464system.cpu.icache.occ_percent::total 0.793051 # Average percentage of cache occupancy 465system.cpu.icache.ReadReq_hits::cpu.inst 24437101 # number of ReadReq hits 466system.cpu.icache.ReadReq_hits::total 24437101 # number of ReadReq hits 467system.cpu.icache.demand_hits::cpu.inst 24437101 # number of demand (read+write) hits 468system.cpu.icache.demand_hits::total 24437101 # number of demand (read+write) hits 469system.cpu.icache.overall_hits::cpu.inst 24437101 # number of overall hits 470system.cpu.icache.overall_hits::total 24437101 # number of overall hits 471system.cpu.icache.ReadReq_misses::cpu.inst 8952 # number of ReadReq misses 472system.cpu.icache.ReadReq_misses::total 8952 # number of ReadReq misses 473system.cpu.icache.demand_misses::cpu.inst 8952 # number of demand (read+write) misses 474system.cpu.icache.demand_misses::total 8952 # number of demand (read+write) misses 475system.cpu.icache.overall_misses::cpu.inst 8952 # number of overall misses 476system.cpu.icache.overall_misses::total 8952 # number of overall misses 477system.cpu.icache.ReadReq_miss_latency::cpu.inst 259465998 # number of ReadReq miss cycles 478system.cpu.icache.ReadReq_miss_latency::total 259465998 # number of ReadReq miss cycles 479system.cpu.icache.demand_miss_latency::cpu.inst 259465998 # number of demand (read+write) miss cycles 480system.cpu.icache.demand_miss_latency::total 259465998 # number of demand (read+write) miss cycles 481system.cpu.icache.overall_miss_latency::cpu.inst 259465998 # number of overall miss cycles 482system.cpu.icache.overall_miss_latency::total 259465998 # number of overall miss cycles 483system.cpu.icache.ReadReq_accesses::cpu.inst 24446053 # number of ReadReq accesses(hits+misses) 484system.cpu.icache.ReadReq_accesses::total 24446053 # number of ReadReq accesses(hits+misses) 485system.cpu.icache.demand_accesses::cpu.inst 24446053 # number of demand (read+write) accesses 486system.cpu.icache.demand_accesses::total 24446053 # number of demand (read+write) accesses 487system.cpu.icache.overall_accesses::cpu.inst 24446053 # number of overall (read+write) accesses 488system.cpu.icache.overall_accesses::total 24446053 # number of overall (read+write) accesses 489system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000366 # miss rate for ReadReq accesses 490system.cpu.icache.ReadReq_miss_rate::total 0.000366 # miss rate for ReadReq accesses 491system.cpu.icache.demand_miss_rate::cpu.inst 0.000366 # miss rate for demand accesses 492system.cpu.icache.demand_miss_rate::total 0.000366 # miss rate for demand accesses 493system.cpu.icache.overall_miss_rate::cpu.inst 0.000366 # miss rate for overall accesses 494system.cpu.icache.overall_miss_rate::total 0.000366 # miss rate for overall accesses 495system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28984.137399 # average ReadReq miss latency 496system.cpu.icache.ReadReq_avg_miss_latency::total 28984.137399 # average ReadReq miss latency 497system.cpu.icache.demand_avg_miss_latency::cpu.inst 28984.137399 # average overall miss latency 498system.cpu.icache.demand_avg_miss_latency::total 28984.137399 # average overall miss latency 499system.cpu.icache.overall_avg_miss_latency::cpu.inst 28984.137399 # average overall miss latency 500system.cpu.icache.overall_avg_miss_latency::total 28984.137399 # average overall miss latency 501system.cpu.icache.blocked_cycles::no_mshrs 676 # number of cycles access was blocked 502system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 503system.cpu.icache.blocked::no_mshrs 21 # number of cycles access was blocked 504system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 505system.cpu.icache.avg_blocked_cycles::no_mshrs 32.190476 # average number of cycles each access was blocked 506system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 507system.cpu.icache.fast_writes 0 # number of fast writes performed 508system.cpu.icache.cache_copies 0 # number of cache copies performed 509system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2097 # number of ReadReq MSHR hits 510system.cpu.icache.ReadReq_mshr_hits::total 2097 # number of ReadReq MSHR hits 511system.cpu.icache.demand_mshr_hits::cpu.inst 2097 # number of demand (read+write) MSHR hits 512system.cpu.icache.demand_mshr_hits::total 2097 # number of demand (read+write) MSHR hits 513system.cpu.icache.overall_mshr_hits::cpu.inst 2097 # number of overall MSHR hits 514system.cpu.icache.overall_mshr_hits::total 2097 # number of overall MSHR hits 515system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6855 # number of ReadReq MSHR misses 516system.cpu.icache.ReadReq_mshr_misses::total 6855 # number of ReadReq MSHR misses 517system.cpu.icache.demand_mshr_misses::cpu.inst 6855 # number of demand (read+write) MSHR misses 518system.cpu.icache.demand_mshr_misses::total 6855 # number of demand (read+write) MSHR misses 519system.cpu.icache.overall_mshr_misses::cpu.inst 6855 # number of overall MSHR misses 520system.cpu.icache.overall_mshr_misses::total 6855 # number of overall MSHR misses 521system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 198302998 # number of ReadReq MSHR miss cycles 522system.cpu.icache.ReadReq_mshr_miss_latency::total 198302998 # number of ReadReq MSHR miss cycles 523system.cpu.icache.demand_mshr_miss_latency::cpu.inst 198302998 # number of demand (read+write) MSHR miss cycles 524system.cpu.icache.demand_mshr_miss_latency::total 198302998 # number of demand (read+write) MSHR miss cycles 525system.cpu.icache.overall_mshr_miss_latency::cpu.inst 198302998 # number of overall MSHR miss cycles 526system.cpu.icache.overall_mshr_miss_latency::total 198302998 # number of overall MSHR miss cycles 527system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000280 # mshr miss rate for ReadReq accesses 528system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000280 # mshr miss rate for ReadReq accesses 529system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000280 # mshr miss rate for demand accesses 530system.cpu.icache.demand_mshr_miss_rate::total 0.000280 # mshr miss rate for demand accesses 531system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000280 # mshr miss rate for overall accesses 532system.cpu.icache.overall_mshr_miss_rate::total 0.000280 # mshr miss rate for overall accesses 533system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28928.227279 # average ReadReq mshr miss latency 534system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28928.227279 # average ReadReq mshr miss latency 535system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28928.227279 # average overall mshr miss latency 536system.cpu.icache.demand_avg_mshr_miss_latency::total 28928.227279 # average overall mshr miss latency 537system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28928.227279 # average overall mshr miss latency 538system.cpu.icache.overall_avg_mshr_miss_latency::total 28928.227279 # average overall mshr miss latency 539system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 540system.cpu.l2cache.replacements 0 # number of replacements 541system.cpu.l2cache.tagsinuse 2509.913640 # Cycle average of tags in use 542system.cpu.l2cache.total_refs 3332 # Total number of references to valid blocks. 543system.cpu.l2cache.sampled_refs 3792 # Sample count of references to valid blocks. 544system.cpu.l2cache.avg_refs 0.878692 # Average number of references to valid blocks. 545system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 546system.cpu.l2cache.occ_blocks::writebacks 0.902701 # Average occupied blocks per requestor 547system.cpu.l2cache.occ_blocks::cpu.inst 2234.774413 # Average occupied blocks per requestor 548system.cpu.l2cache.occ_blocks::cpu.data 274.236526 # Average occupied blocks per requestor 549system.cpu.l2cache.occ_percent::writebacks 0.000028 # Average percentage of cache occupancy 550system.cpu.l2cache.occ_percent::cpu.inst 0.068200 # Average percentage of cache occupancy 551system.cpu.l2cache.occ_percent::cpu.data 0.008369 # Average percentage of cache occupancy 552system.cpu.l2cache.occ_percent::total 0.076596 # Average percentage of cache occupancy 553system.cpu.l2cache.ReadReq_hits::cpu.inst 3299 # number of ReadReq hits 554system.cpu.l2cache.ReadReq_hits::cpu.data 30 # number of ReadReq hits 555system.cpu.l2cache.ReadReq_hits::total 3329 # number of ReadReq hits 556system.cpu.l2cache.Writeback_hits::writebacks 14 # number of Writeback hits 557system.cpu.l2cache.Writeback_hits::total 14 # number of Writeback hits 558system.cpu.l2cache.ReadExReq_hits::cpu.data 7 # number of ReadExReq hits 559system.cpu.l2cache.ReadExReq_hits::total 7 # number of ReadExReq hits 560system.cpu.l2cache.demand_hits::cpu.inst 3299 # number of demand (read+write) hits 561system.cpu.l2cache.demand_hits::cpu.data 37 # number of demand (read+write) hits 562system.cpu.l2cache.demand_hits::total 3336 # number of demand (read+write) hits 563system.cpu.l2cache.overall_hits::cpu.inst 3299 # number of overall hits 564system.cpu.l2cache.overall_hits::cpu.data 37 # number of overall hits 565system.cpu.l2cache.overall_hits::total 3336 # number of overall hits 566system.cpu.l2cache.ReadReq_misses::cpu.inst 3402 # number of ReadReq misses 567system.cpu.l2cache.ReadReq_misses::cpu.data 386 # number of ReadReq misses 568system.cpu.l2cache.ReadReq_misses::total 3788 # number of ReadReq misses 569system.cpu.l2cache.UpgradeReq_misses::cpu.data 154 # number of UpgradeReq misses 570system.cpu.l2cache.UpgradeReq_misses::total 154 # number of UpgradeReq misses 571system.cpu.l2cache.ReadExReq_misses::cpu.data 1560 # number of ReadExReq misses 572system.cpu.l2cache.ReadExReq_misses::total 1560 # number of ReadExReq misses 573system.cpu.l2cache.demand_misses::cpu.inst 3402 # number of demand (read+write) misses 574system.cpu.l2cache.demand_misses::cpu.data 1946 # number of demand (read+write) misses 575system.cpu.l2cache.demand_misses::total 5348 # number of demand (read+write) misses 576system.cpu.l2cache.overall_misses::cpu.inst 3402 # number of overall misses 577system.cpu.l2cache.overall_misses::cpu.data 1946 # number of overall misses 578system.cpu.l2cache.overall_misses::total 5348 # number of overall misses 579system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 158304000 # number of ReadReq miss cycles 580system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21677000 # number of ReadReq miss cycles 581system.cpu.l2cache.ReadReq_miss_latency::total 179981000 # number of ReadReq miss cycles 582system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 68234000 # number of ReadExReq miss cycles 583system.cpu.l2cache.ReadExReq_miss_latency::total 68234000 # number of ReadExReq miss cycles 584system.cpu.l2cache.demand_miss_latency::cpu.inst 158304000 # number of demand (read+write) miss cycles 585system.cpu.l2cache.demand_miss_latency::cpu.data 89911000 # number of demand (read+write) miss cycles 586system.cpu.l2cache.demand_miss_latency::total 248215000 # number of demand (read+write) miss cycles 587system.cpu.l2cache.overall_miss_latency::cpu.inst 158304000 # number of overall miss cycles 588system.cpu.l2cache.overall_miss_latency::cpu.data 89911000 # number of overall miss cycles 589system.cpu.l2cache.overall_miss_latency::total 248215000 # number of overall miss cycles 590system.cpu.l2cache.ReadReq_accesses::cpu.inst 6701 # number of ReadReq accesses(hits+misses) 591system.cpu.l2cache.ReadReq_accesses::cpu.data 416 # number of ReadReq accesses(hits+misses) 592system.cpu.l2cache.ReadReq_accesses::total 7117 # number of ReadReq accesses(hits+misses) 593system.cpu.l2cache.Writeback_accesses::writebacks 14 # number of Writeback accesses(hits+misses) 594system.cpu.l2cache.Writeback_accesses::total 14 # number of Writeback accesses(hits+misses) 595system.cpu.l2cache.UpgradeReq_accesses::cpu.data 154 # number of UpgradeReq accesses(hits+misses) 596system.cpu.l2cache.UpgradeReq_accesses::total 154 # number of UpgradeReq accesses(hits+misses) 597system.cpu.l2cache.ReadExReq_accesses::cpu.data 1567 # number of ReadExReq accesses(hits+misses) 598system.cpu.l2cache.ReadExReq_accesses::total 1567 # number of ReadExReq accesses(hits+misses) 599system.cpu.l2cache.demand_accesses::cpu.inst 6701 # number of demand (read+write) accesses 600system.cpu.l2cache.demand_accesses::cpu.data 1983 # number of demand (read+write) accesses 601system.cpu.l2cache.demand_accesses::total 8684 # number of demand (read+write) accesses 602system.cpu.l2cache.overall_accesses::cpu.inst 6701 # number of overall (read+write) accesses 603system.cpu.l2cache.overall_accesses::cpu.data 1983 # number of overall (read+write) accesses 604system.cpu.l2cache.overall_accesses::total 8684 # number of overall (read+write) accesses 605system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.507685 # miss rate for ReadReq accesses 606system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.927885 # miss rate for ReadReq accesses 607system.cpu.l2cache.ReadReq_miss_rate::total 0.532247 # miss rate for ReadReq accesses 608system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 609system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 610system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.995533 # miss rate for ReadExReq accesses 611system.cpu.l2cache.ReadExReq_miss_rate::total 0.995533 # miss rate for ReadExReq accesses 612system.cpu.l2cache.demand_miss_rate::cpu.inst 0.507685 # miss rate for demand accesses 613system.cpu.l2cache.demand_miss_rate::cpu.data 0.981341 # miss rate for demand accesses 614system.cpu.l2cache.demand_miss_rate::total 0.615845 # miss rate for demand accesses 615system.cpu.l2cache.overall_miss_rate::cpu.inst 0.507685 # miss rate for overall accesses 616system.cpu.l2cache.overall_miss_rate::cpu.data 0.981341 # miss rate for overall accesses 617system.cpu.l2cache.overall_miss_rate::total 0.615845 # miss rate for overall accesses 618system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 46532.627866 # average ReadReq miss latency 619system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56158.031088 # average ReadReq miss latency 620system.cpu.l2cache.ReadReq_avg_miss_latency::total 47513.463569 # average ReadReq miss latency 621system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 43739.743590 # average ReadExReq miss latency 622system.cpu.l2cache.ReadExReq_avg_miss_latency::total 43739.743590 # average ReadExReq miss latency 623system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 46532.627866 # average overall miss latency 624system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46202.980473 # average overall miss latency 625system.cpu.l2cache.demand_avg_miss_latency::total 46412.677636 # average overall miss latency 626system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 46532.627866 # average overall miss latency 627system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46202.980473 # average overall miss latency 628system.cpu.l2cache.overall_avg_miss_latency::total 46412.677636 # average overall miss latency 629system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 630system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 631system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 632system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 633system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 634system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 635system.cpu.l2cache.fast_writes 0 # number of fast writes performed 636system.cpu.l2cache.cache_copies 0 # number of cache copies performed 637system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3402 # number of ReadReq MSHR misses 638system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 386 # number of ReadReq MSHR misses 639system.cpu.l2cache.ReadReq_mshr_misses::total 3788 # number of ReadReq MSHR misses 640system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 154 # number of UpgradeReq MSHR misses 641system.cpu.l2cache.UpgradeReq_mshr_misses::total 154 # number of UpgradeReq MSHR misses 642system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1560 # number of ReadExReq MSHR misses 643system.cpu.l2cache.ReadExReq_mshr_misses::total 1560 # number of ReadExReq MSHR misses 644system.cpu.l2cache.demand_mshr_misses::cpu.inst 3402 # number of demand (read+write) MSHR misses 645system.cpu.l2cache.demand_mshr_misses::cpu.data 1946 # number of demand (read+write) MSHR misses 646system.cpu.l2cache.demand_mshr_misses::total 5348 # number of demand (read+write) MSHR misses 647system.cpu.l2cache.overall_mshr_misses::cpu.inst 3402 # number of overall MSHR misses 648system.cpu.l2cache.overall_mshr_misses::cpu.data 1946 # number of overall MSHR misses 649system.cpu.l2cache.overall_mshr_misses::total 5348 # number of overall MSHR misses 650system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 115394983 # number of ReadReq MSHR miss cycles 651system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16844098 # number of ReadReq MSHR miss cycles 652system.cpu.l2cache.ReadReq_mshr_miss_latency::total 132239081 # number of ReadReq MSHR miss cycles 653system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1540154 # number of UpgradeReq MSHR miss cycles 654system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1540154 # number of UpgradeReq MSHR miss cycles 655system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48432493 # number of ReadExReq MSHR miss cycles 656system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48432493 # number of ReadExReq MSHR miss cycles 657system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 115394983 # number of demand (read+write) MSHR miss cycles 658system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 65276591 # number of demand (read+write) MSHR miss cycles 659system.cpu.l2cache.demand_mshr_miss_latency::total 180671574 # number of demand (read+write) MSHR miss cycles 660system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 115394983 # number of overall MSHR miss cycles 661system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 65276591 # number of overall MSHR miss cycles 662system.cpu.l2cache.overall_mshr_miss_latency::total 180671574 # number of overall MSHR miss cycles 663system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.507685 # mshr miss rate for ReadReq accesses 664system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.927885 # mshr miss rate for ReadReq accesses 665system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.532247 # mshr miss rate for ReadReq accesses 666system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 667system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 668system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.995533 # mshr miss rate for ReadExReq accesses 669system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.995533 # mshr miss rate for ReadExReq accesses 670system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.507685 # mshr miss rate for demand accesses 671system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.981341 # mshr miss rate for demand accesses 672system.cpu.l2cache.demand_mshr_miss_rate::total 0.615845 # mshr miss rate for demand accesses 673system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.507685 # mshr miss rate for overall accesses 674system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.981341 # mshr miss rate for overall accesses 675system.cpu.l2cache.overall_mshr_miss_rate::total 0.615845 # mshr miss rate for overall accesses 676system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33919.748089 # average ReadReq mshr miss latency 677system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43637.559585 # average ReadReq mshr miss latency 678system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 34910.000264 # average ReadReq mshr miss latency 679system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 680system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency 681system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31046.469872 # average ReadExReq mshr miss latency 682system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31046.469872 # average ReadExReq mshr miss latency 683system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33919.748089 # average overall mshr miss latency 684system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33543.983042 # average overall mshr miss latency 685system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33783.016829 # average overall mshr miss latency 686system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33919.748089 # average overall mshr miss latency 687system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33543.983042 # average overall mshr miss latency 688system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33783.016829 # average overall mshr miss latency 689system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 690system.cpu.dcache.replacements 55 # number of replacements 691system.cpu.dcache.tagsinuse 1411.367257 # Cycle average of tags in use 692system.cpu.dcache.total_refs 67560996 # Total number of references to valid blocks. 693system.cpu.dcache.sampled_refs 1981 # Sample count of references to valid blocks. 694system.cpu.dcache.avg_refs 34104.490661 # Average number of references to valid blocks. 695system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 696system.cpu.dcache.occ_blocks::cpu.data 1411.367257 # Average occupied blocks per requestor 697system.cpu.dcache.occ_percent::cpu.data 0.344572 # Average percentage of cache occupancy 698system.cpu.dcache.occ_percent::total 0.344572 # Average percentage of cache occupancy 699system.cpu.dcache.ReadReq_hits::cpu.data 47046789 # number of ReadReq hits 700system.cpu.dcache.ReadReq_hits::total 47046789 # number of ReadReq hits 701system.cpu.dcache.WriteReq_hits::cpu.data 20514009 # number of WriteReq hits 702system.cpu.dcache.WriteReq_hits::total 20514009 # number of WriteReq hits 703system.cpu.dcache.demand_hits::cpu.data 67560798 # number of demand (read+write) hits 704system.cpu.dcache.demand_hits::total 67560798 # number of demand (read+write) hits 705system.cpu.dcache.overall_hits::cpu.data 67560798 # number of overall hits 706system.cpu.dcache.overall_hits::total 67560798 # number of overall hits 707system.cpu.dcache.ReadReq_misses::cpu.data 791 # number of ReadReq misses 708system.cpu.dcache.ReadReq_misses::total 791 # number of ReadReq misses 709system.cpu.dcache.WriteReq_misses::cpu.data 1722 # number of WriteReq misses 710system.cpu.dcache.WriteReq_misses::total 1722 # number of WriteReq misses 711system.cpu.dcache.demand_misses::cpu.data 2513 # number of demand (read+write) misses 712system.cpu.dcache.demand_misses::total 2513 # number of demand (read+write) misses 713system.cpu.dcache.overall_misses::cpu.data 2513 # number of overall misses 714system.cpu.dcache.overall_misses::total 2513 # number of overall misses 715system.cpu.dcache.ReadReq_miss_latency::cpu.data 37144000 # number of ReadReq miss cycles 716system.cpu.dcache.ReadReq_miss_latency::total 37144000 # number of ReadReq miss cycles 717system.cpu.dcache.WriteReq_miss_latency::cpu.data 76853000 # number of WriteReq miss cycles 718system.cpu.dcache.WriteReq_miss_latency::total 76853000 # number of WriteReq miss cycles 719system.cpu.dcache.demand_miss_latency::cpu.data 113997000 # number of demand (read+write) miss cycles 720system.cpu.dcache.demand_miss_latency::total 113997000 # number of demand (read+write) miss cycles 721system.cpu.dcache.overall_miss_latency::cpu.data 113997000 # number of overall miss cycles 722system.cpu.dcache.overall_miss_latency::total 113997000 # number of overall miss cycles 723system.cpu.dcache.ReadReq_accesses::cpu.data 47047580 # number of ReadReq accesses(hits+misses) 724system.cpu.dcache.ReadReq_accesses::total 47047580 # number of ReadReq accesses(hits+misses) 725system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) 726system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) 727system.cpu.dcache.demand_accesses::cpu.data 67563311 # number of demand (read+write) accesses 728system.cpu.dcache.demand_accesses::total 67563311 # number of demand (read+write) accesses 729system.cpu.dcache.overall_accesses::cpu.data 67563311 # number of overall (read+write) accesses 730system.cpu.dcache.overall_accesses::total 67563311 # number of overall (read+write) accesses 731system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000017 # miss rate for ReadReq accesses 732system.cpu.dcache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses 733system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000084 # miss rate for WriteReq accesses 734system.cpu.dcache.WriteReq_miss_rate::total 0.000084 # miss rate for WriteReq accesses 735system.cpu.dcache.demand_miss_rate::cpu.data 0.000037 # miss rate for demand accesses 736system.cpu.dcache.demand_miss_rate::total 0.000037 # miss rate for demand accesses 737system.cpu.dcache.overall_miss_rate::cpu.data 0.000037 # miss rate for overall accesses 738system.cpu.dcache.overall_miss_rate::total 0.000037 # miss rate for overall accesses 739system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 46958.280657 # average ReadReq miss latency 740system.cpu.dcache.ReadReq_avg_miss_latency::total 46958.280657 # average ReadReq miss latency 741system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44630.081301 # average WriteReq miss latency 742system.cpu.dcache.WriteReq_avg_miss_latency::total 44630.081301 # average WriteReq miss latency 743system.cpu.dcache.demand_avg_miss_latency::cpu.data 45362.912853 # average overall miss latency 744system.cpu.dcache.demand_avg_miss_latency::total 45362.912853 # average overall miss latency 745system.cpu.dcache.overall_avg_miss_latency::cpu.data 45362.912853 # average overall miss latency 746system.cpu.dcache.overall_avg_miss_latency::total 45362.912853 # average overall miss latency 747system.cpu.dcache.blocked_cycles::no_mshrs 86 # number of cycles access was blocked 748system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 749system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked 750system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 751system.cpu.dcache.avg_blocked_cycles::no_mshrs 43 # average number of cycles each access was blocked 752system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 753system.cpu.dcache.fast_writes 0 # number of fast writes performed 754system.cpu.dcache.cache_copies 0 # number of cache copies performed 755system.cpu.dcache.writebacks::writebacks 14 # number of writebacks 756system.cpu.dcache.writebacks::total 14 # number of writebacks 757system.cpu.dcache.ReadReq_mshr_hits::cpu.data 374 # number of ReadReq MSHR hits 758system.cpu.dcache.ReadReq_mshr_hits::total 374 # number of ReadReq MSHR hits 759system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits 760system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits 761system.cpu.dcache.demand_mshr_hits::cpu.data 376 # number of demand (read+write) MSHR hits 762system.cpu.dcache.demand_mshr_hits::total 376 # number of demand (read+write) MSHR hits 763system.cpu.dcache.overall_mshr_hits::cpu.data 376 # number of overall MSHR hits 764system.cpu.dcache.overall_mshr_hits::total 376 # number of overall MSHR hits 765system.cpu.dcache.ReadReq_mshr_misses::cpu.data 417 # number of ReadReq MSHR misses 766system.cpu.dcache.ReadReq_mshr_misses::total 417 # number of ReadReq MSHR misses 767system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1720 # number of WriteReq MSHR misses 768system.cpu.dcache.WriteReq_mshr_misses::total 1720 # number of WriteReq MSHR misses 769system.cpu.dcache.demand_mshr_misses::cpu.data 2137 # number of demand (read+write) MSHR misses 770system.cpu.dcache.demand_mshr_misses::total 2137 # number of demand (read+write) MSHR misses 771system.cpu.dcache.overall_mshr_misses::cpu.data 2137 # number of overall MSHR misses 772system.cpu.dcache.overall_mshr_misses::total 2137 # number of overall MSHR misses 773system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22474000 # number of ReadReq MSHR miss cycles 774system.cpu.dcache.ReadReq_mshr_miss_latency::total 22474000 # number of ReadReq MSHR miss cycles 775system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73299500 # number of WriteReq MSHR miss cycles 776system.cpu.dcache.WriteReq_mshr_miss_latency::total 73299500 # number of WriteReq MSHR miss cycles 777system.cpu.dcache.demand_mshr_miss_latency::cpu.data 95773500 # number of demand (read+write) MSHR miss cycles 778system.cpu.dcache.demand_mshr_miss_latency::total 95773500 # number of demand (read+write) MSHR miss cycles 779system.cpu.dcache.overall_mshr_miss_latency::cpu.data 95773500 # number of overall MSHR miss cycles 780system.cpu.dcache.overall_mshr_miss_latency::total 95773500 # number of overall MSHR miss cycles 781system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses 782system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses 783system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for WriteReq accesses 784system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000084 # mshr miss rate for WriteReq accesses 785system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for demand accesses 786system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses 787system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses 788system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses 789system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53894.484412 # average ReadReq mshr miss latency 790system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53894.484412 # average ReadReq mshr miss latency 791system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42615.988372 # average WriteReq mshr miss latency 792system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42615.988372 # average WriteReq mshr miss latency 793system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44816.799251 # average overall mshr miss latency 794system.cpu.dcache.demand_avg_mshr_miss_latency::total 44816.799251 # average overall mshr miss latency 795system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44816.799251 # average overall mshr miss latency 796system.cpu.dcache.overall_avg_mshr_miss_latency::total 44816.799251 # average overall mshr miss latency 797system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 798 799---------- End Simulation Statistics ---------- 800