stats.txt revision 9223:be1c1059438b
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.084417 # Number of seconds simulated 4sim_ticks 84416735500 # Number of ticks simulated 5final_tick 84416735500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 63787 # Simulator instruction rate (inst/s) 8host_op_rate 106913 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 40771301 # Simulator tick rate (ticks/s) 10host_mem_usage 285396 # Number of bytes of host memory used 11host_seconds 2070.49 # Real time elapsed on the host 12sim_insts 132071192 # Number of instructions simulated 13sim_ops 221362960 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 219392 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 124672 # Number of bytes read from this memory 16system.physmem.bytes_read::total 344064 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 219392 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 219392 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 3428 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 1948 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 5376 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 2598916 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 1476864 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 4075779 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 2598916 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 2598916 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 2598916 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 1476864 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 4075779 # Total bandwidth to/from this memory (bytes/s) 30system.cpu.workload.num_syscalls 400 # Number of system calls 31system.cpu.numCycles 168833472 # number of cpu cycles simulated 32system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 33system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 34system.cpu.BPredUnit.lookups 20699953 # Number of BP lookups 35system.cpu.BPredUnit.condPredicted 20699953 # Number of conditional branches predicted 36system.cpu.BPredUnit.condIncorrect 2254791 # Number of conditional branches incorrect 37system.cpu.BPredUnit.BTBLookups 15116204 # Number of BTB lookups 38system.cpu.BPredUnit.BTBHits 13734495 # Number of BTB hits 39system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 40system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. 41system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. 42system.cpu.fetch.icacheStallCycles 27236198 # Number of cycles fetch is stalled on an Icache miss 43system.cpu.fetch.Insts 227395589 # Number of instructions fetch has processed 44system.cpu.fetch.Branches 20699953 # Number of branches that fetch encountered 45system.cpu.fetch.predictedBranches 13734495 # Number of branches that fetch has predicted taken 46system.cpu.fetch.Cycles 59717541 # Number of cycles fetch has run and was not squashing or blocked 47system.cpu.fetch.SquashCycles 19334489 # Number of cycles fetch has spent squashing 48system.cpu.fetch.BlockedCycles 64998537 # Number of cycles fetch has spent blocked 49system.cpu.fetch.MiscStallCycles 379 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 50system.cpu.fetch.PendingTrapStallCycles 2980 # Number of stall cycles due to pending traps 51system.cpu.fetch.CacheLines 25696290 # Number of cache lines fetched 52system.cpu.fetch.IcacheSquashes 472102 # Number of outstanding Icache misses that were squashed 53system.cpu.fetch.rateDist::samples 168753880 # Number of instructions fetched each cycle (Total) 54system.cpu.fetch.rateDist::mean 2.217952 # Number of instructions fetched each cycle (Total) 55system.cpu.fetch.rateDist::stdev 3.336457 # Number of instructions fetched each cycle (Total) 56system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 57system.cpu.fetch.rateDist::0 110699150 65.60% 65.60% # Number of instructions fetched each cycle (Total) 58system.cpu.fetch.rateDist::1 3224321 1.91% 67.51% # Number of instructions fetched each cycle (Total) 59system.cpu.fetch.rateDist::2 2475319 1.47% 68.98% # Number of instructions fetched each cycle (Total) 60system.cpu.fetch.rateDist::3 3099058 1.84% 70.81% # Number of instructions fetched each cycle (Total) 61system.cpu.fetch.rateDist::4 3522120 2.09% 72.90% # Number of instructions fetched each cycle (Total) 62system.cpu.fetch.rateDist::5 3727832 2.21% 75.11% # Number of instructions fetched each cycle (Total) 63system.cpu.fetch.rateDist::6 4580737 2.71% 77.82% # Number of instructions fetched each cycle (Total) 64system.cpu.fetch.rateDist::7 2798912 1.66% 79.48% # Number of instructions fetched each cycle (Total) 65system.cpu.fetch.rateDist::8 34626431 20.52% 100.00% # Number of instructions fetched each cycle (Total) 66system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 67system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 68system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 69system.cpu.fetch.rateDist::total 168753880 # Number of instructions fetched each cycle (Total) 70system.cpu.fetch.branchRate 0.122606 # Number of branch fetches per cycle 71system.cpu.fetch.rate 1.346863 # Number of inst fetches per cycle 72system.cpu.decode.IdleCycles 40114666 # Number of cycles decode is idle 73system.cpu.decode.BlockedCycles 55275027 # Number of cycles decode is blocked 74system.cpu.decode.RunCycles 46754888 # Number of cycles decode is running 75system.cpu.decode.UnblockCycles 9811054 # Number of cycles decode is unblocking 76system.cpu.decode.SquashCycles 16798245 # Number of cycles decode is squashing 77system.cpu.decode.DecodedInsts 365144878 # Number of instructions handled by decode 78system.cpu.rename.SquashCycles 16798245 # Number of cycles rename is squashing 79system.cpu.rename.IdleCycles 47659212 # Number of cycles rename is idle 80system.cpu.rename.BlockCycles 14495562 # Number of cycles rename is blocking 81system.cpu.rename.serializeStallCycles 23044 # count of cycles rename stalled for serializing inst 82system.cpu.rename.RunCycles 48366883 # Number of cycles rename is running 83system.cpu.rename.UnblockCycles 41410934 # Number of cycles rename is unblocking 84system.cpu.rename.RenamedInsts 355937871 # Number of instructions processed by rename 85system.cpu.rename.ROBFullEvents 38 # Number of times rename has blocked due to ROB full 86system.cpu.rename.IQFullEvents 17144692 # Number of times rename has blocked due to IQ full 87system.cpu.rename.LSQFullEvents 22141197 # Number of times rename has blocked due to LSQ full 88system.cpu.rename.RenamedOperands 410198872 # Number of destination operands rename has renamed 89system.cpu.rename.RenameLookups 987348929 # Number of register rename lookups that rename has made 90system.cpu.rename.int_rename_lookups 977397781 # Number of integer rename lookups 91system.cpu.rename.fp_rename_lookups 9951148 # Number of floating rename lookups 92system.cpu.rename.CommittedMaps 259428603 # Number of HB maps that are committed 93system.cpu.rename.UndoneMaps 150770269 # Number of HB maps that are undone due to squashing 94system.cpu.rename.serializingInsts 1731 # count of serializing insts renamed 95system.cpu.rename.tempSerializingInsts 1722 # count of temporary serializing insts renamed 96system.cpu.rename.skidInsts 89681152 # count of insts added to the skid buffer 97system.cpu.memDep0.insertedLoads 89661303 # Number of loads inserted to the mem dependence unit. 98system.cpu.memDep0.insertedStores 32849139 # Number of stores inserted to the mem dependence unit. 99system.cpu.memDep0.conflictingLoads 58579836 # Number of conflicting loads. 100system.cpu.memDep0.conflictingStores 19046101 # Number of conflicting stores. 101system.cpu.iq.iqInstsAdded 343008159 # Number of instructions added to the IQ (excludes non-spec) 102system.cpu.iq.iqNonSpecInstsAdded 4651 # Number of non-speculative instructions added to the IQ 103system.cpu.iq.iqInstsIssued 272074168 # Number of instructions issued 104system.cpu.iq.iqSquashedInstsIssued 315487 # Number of squashed instructions issued 105system.cpu.iq.iqSquashedInstsExamined 121115880 # Number of squashed instructions iterated over during squash; mainly for profiling 106system.cpu.iq.iqSquashedOperandsExamined 246174480 # Number of squashed operands that are examined and possibly removed from graph 107system.cpu.iq.iqSquashedNonSpecRemoved 3405 # Number of squashed non-spec instructions that were removed 108system.cpu.iq.issued_per_cycle::samples 168753880 # Number of insts issued each cycle 109system.cpu.iq.issued_per_cycle::mean 1.612254 # Number of insts issued each cycle 110system.cpu.iq.issued_per_cycle::stdev 1.516605 # Number of insts issued each cycle 111system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 112system.cpu.iq.issued_per_cycle::0 47246333 28.00% 28.00% # Number of insts issued each cycle 113system.cpu.iq.issued_per_cycle::1 46593223 27.61% 55.61% # Number of insts issued each cycle 114system.cpu.iq.issued_per_cycle::2 33100078 19.61% 75.22% # Number of insts issued each cycle 115system.cpu.iq.issued_per_cycle::3 20197900 11.97% 87.19% # Number of insts issued each cycle 116system.cpu.iq.issued_per_cycle::4 13442909 7.97% 95.16% # Number of insts issued each cycle 117system.cpu.iq.issued_per_cycle::5 5008835 2.97% 98.12% # Number of insts issued each cycle 118system.cpu.iq.issued_per_cycle::6 2434360 1.44% 99.57% # Number of insts issued each cycle 119system.cpu.iq.issued_per_cycle::7 576818 0.34% 99.91% # Number of insts issued each cycle 120system.cpu.iq.issued_per_cycle::8 153424 0.09% 100.00% # Number of insts issued each cycle 121system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 122system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 123system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 124system.cpu.iq.issued_per_cycle::total 168753880 # Number of insts issued each cycle 125system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 126system.cpu.iq.fu_full::IntAlu 133668 5.05% 5.05% # attempts to use FU when none available 127system.cpu.iq.fu_full::IntMult 0 0.00% 5.05% # attempts to use FU when none available 128system.cpu.iq.fu_full::IntDiv 0 0.00% 5.05% # attempts to use FU when none available 129system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.05% # attempts to use FU when none available 130system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.05% # attempts to use FU when none available 131system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.05% # attempts to use FU when none available 132system.cpu.iq.fu_full::FloatMult 0 0.00% 5.05% # attempts to use FU when none available 133system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.05% # attempts to use FU when none available 134system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.05% # attempts to use FU when none available 135system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.05% # attempts to use FU when none available 136system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.05% # attempts to use FU when none available 137system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.05% # attempts to use FU when none available 138system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.05% # attempts to use FU when none available 139system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.05% # attempts to use FU when none available 140system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.05% # attempts to use FU when none available 141system.cpu.iq.fu_full::SimdMult 0 0.00% 5.05% # attempts to use FU when none available 142system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.05% # attempts to use FU when none available 143system.cpu.iq.fu_full::SimdShift 0 0.00% 5.05% # attempts to use FU when none available 144system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.05% # attempts to use FU when none available 145system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.05% # attempts to use FU when none available 146system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.05% # attempts to use FU when none available 147system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.05% # attempts to use FU when none available 148system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.05% # attempts to use FU when none available 149system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.05% # attempts to use FU when none available 150system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.05% # attempts to use FU when none available 151system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.05% # attempts to use FU when none available 152system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.05% # attempts to use FU when none available 153system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.05% # attempts to use FU when none available 154system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.05% # attempts to use FU when none available 155system.cpu.iq.fu_full::MemRead 2245630 84.89% 89.95% # attempts to use FU when none available 156system.cpu.iq.fu_full::MemWrite 265941 10.05% 100.00% # attempts to use FU when none available 157system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 158system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 159system.cpu.iq.FU_type_0::No_OpClass 1212775 0.45% 0.45% # Type of FU issued 160system.cpu.iq.FU_type_0::IntAlu 177115116 65.10% 65.54% # Type of FU issued 161system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.54% # Type of FU issued 162system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.54% # Type of FU issued 163system.cpu.iq.FU_type_0::FloatAdd 1587982 0.58% 66.13% # Type of FU issued 164system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.13% # Type of FU issued 165system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.13% # Type of FU issued 166system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.13% # Type of FU issued 167system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.13% # Type of FU issued 168system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.13% # Type of FU issued 169system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.13% # Type of FU issued 170system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.13% # Type of FU issued 171system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.13% # Type of FU issued 172system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.13% # Type of FU issued 173system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.13% # Type of FU issued 174system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.13% # Type of FU issued 175system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.13% # Type of FU issued 176system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.13% # Type of FU issued 177system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.13% # Type of FU issued 178system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.13% # Type of FU issued 179system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.13% # Type of FU issued 180system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.13% # Type of FU issued 181system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.13% # Type of FU issued 182system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.13% # Type of FU issued 183system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.13% # Type of FU issued 184system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.13% # Type of FU issued 185system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.13% # Type of FU issued 186system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.13% # Type of FU issued 187system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.13% # Type of FU issued 188system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.13% # Type of FU issued 189system.cpu.iq.FU_type_0::MemRead 68640688 25.23% 91.36% # Type of FU issued 190system.cpu.iq.FU_type_0::MemWrite 23517607 8.64% 100.00% # Type of FU issued 191system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 192system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 193system.cpu.iq.FU_type_0::total 272074168 # Type of FU issued 194system.cpu.iq.rate 1.611494 # Inst issue rate 195system.cpu.iq.fu_busy_cnt 2645239 # FU busy when requested 196system.cpu.iq.fu_busy_rate 0.009722 # FU busy rate (busy events/executed inst) 197system.cpu.iq.int_inst_queue_reads 710552167 # Number of integer instruction queue reads 198system.cpu.iq.int_inst_queue_writes 459825601 # Number of integer instruction queue writes 199system.cpu.iq.int_inst_queue_wakeup_accesses 264280356 # Number of integer instruction queue wakeup accesses 200system.cpu.iq.fp_inst_queue_reads 5310775 # Number of floating instruction queue reads 201system.cpu.iq.fp_inst_queue_writes 4610743 # Number of floating instruction queue writes 202system.cpu.iq.fp_inst_queue_wakeup_accesses 2547999 # Number of floating instruction queue wakeup accesses 203system.cpu.iq.int_alu_accesses 270845077 # Number of integer alu accesses 204system.cpu.iq.fp_alu_accesses 2661555 # Number of floating point alu accesses 205system.cpu.iew.lsq.thread0.forwLoads 19085225 # Number of loads that had data forwarded from stores 206system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 207system.cpu.iew.lsq.thread0.squashedLoads 33011717 # Number of loads squashed 208system.cpu.iew.lsq.thread0.ignoredResponses 33669 # Number of memory responses ignored because the instruction is squashed 209system.cpu.iew.lsq.thread0.memOrderViolation 313308 # Number of memory ordering violations 210system.cpu.iew.lsq.thread0.squashedStores 12333423 # Number of stores squashed 211system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 212system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 213system.cpu.iew.lsq.thread0.rescheduledLoads 49764 # Number of loads that were rescheduled 214system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 215system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 216system.cpu.iew.iewSquashCycles 16798245 # Number of cycles IEW is squashing 217system.cpu.iew.iewBlockCycles 578433 # Number of cycles IEW is blocking 218system.cpu.iew.iewUnblockCycles 255971 # Number of cycles IEW is unblocking 219system.cpu.iew.iewDispatchedInsts 343012810 # Number of instructions dispatched to IQ 220system.cpu.iew.iewDispSquashedInsts 262853 # Number of squashed instructions skipped by dispatch 221system.cpu.iew.iewDispLoadInsts 89661303 # Number of dispatched load instructions 222system.cpu.iew.iewDispStoreInsts 32849139 # Number of dispatched store instructions 223system.cpu.iew.iewDispNonSpecInsts 1696 # Number of dispatched non-speculative instructions 224system.cpu.iew.iewIQFullEvents 171518 # Number of times the IQ has become full, causing a stall 225system.cpu.iew.iewLSQFullEvents 28262 # Number of times the LSQ has become full, causing a stall 226system.cpu.iew.memOrderViolationEvents 313308 # Number of memory order violations 227system.cpu.iew.predictedTakenIncorrect 1334034 # Number of branches that were predicted taken incorrectly 228system.cpu.iew.predictedNotTakenIncorrect 1025575 # Number of branches that were predicted not taken incorrectly 229system.cpu.iew.branchMispredicts 2359609 # Number of branch mispredicts detected at execute 230system.cpu.iew.iewExecutedInsts 268880206 # Number of executed instructions 231system.cpu.iew.iewExecLoadInsts 67501088 # Number of load instructions executed 232system.cpu.iew.iewExecSquashedInsts 3193962 # Number of squashed instructions skipped in execute 233system.cpu.iew.exec_swp 0 # number of swp insts executed 234system.cpu.iew.exec_nop 0 # number of nop insts executed 235system.cpu.iew.exec_refs 90609613 # number of memory reference insts executed 236system.cpu.iew.exec_branches 14778913 # Number of branches executed 237system.cpu.iew.exec_stores 23108525 # Number of stores executed 238system.cpu.iew.exec_rate 1.592576 # Inst execution rate 239system.cpu.iew.wb_sent 267790153 # cumulative count of insts sent to commit 240system.cpu.iew.wb_count 266828355 # cumulative count of insts written-back 241system.cpu.iew.wb_producers 215466239 # num instructions producing a value 242system.cpu.iew.wb_consumers 378707057 # num instructions consuming a value 243system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 244system.cpu.iew.wb_rate 1.580423 # insts written-back per cycle 245system.cpu.iew.wb_fanout 0.568952 # average fanout of values written-back 246system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 247system.cpu.commit.commitSquashedInsts 121732782 # The number of squashed insts skipped by commit 248system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards 249system.cpu.commit.branchMispredicts 2255092 # The number of times a branch was mispredicted 250system.cpu.commit.committed_per_cycle::samples 151955635 # Number of insts commited each cycle 251system.cpu.commit.committed_per_cycle::mean 1.456760 # Number of insts commited each cycle 252system.cpu.commit.committed_per_cycle::stdev 1.933041 # Number of insts commited each cycle 253system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 254system.cpu.commit.committed_per_cycle::0 52584491 34.61% 34.61% # Number of insts commited each cycle 255system.cpu.commit.committed_per_cycle::1 57288776 37.70% 72.31% # Number of insts commited each cycle 256system.cpu.commit.committed_per_cycle::2 13942421 9.18% 81.48% # Number of insts commited each cycle 257system.cpu.commit.committed_per_cycle::3 11933178 7.85% 89.33% # Number of insts commited each cycle 258system.cpu.commit.committed_per_cycle::4 4288993 2.82% 92.16% # Number of insts commited each cycle 259system.cpu.commit.committed_per_cycle::5 2988620 1.97% 94.12% # Number of insts commited each cycle 260system.cpu.commit.committed_per_cycle::6 1076250 0.71% 94.83% # Number of insts commited each cycle 261system.cpu.commit.committed_per_cycle::7 990012 0.65% 95.48% # Number of insts commited each cycle 262system.cpu.commit.committed_per_cycle::8 6862894 4.52% 100.00% # Number of insts commited each cycle 263system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 264system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 265system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 266system.cpu.commit.committed_per_cycle::total 151955635 # Number of insts commited each cycle 267system.cpu.commit.committedInsts 132071192 # Number of instructions committed 268system.cpu.commit.committedOps 221362960 # Number of ops (including micro ops) committed 269system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 270system.cpu.commit.refs 77165302 # Number of memory references committed 271system.cpu.commit.loads 56649586 # Number of loads committed 272system.cpu.commit.membars 0 # Number of memory barriers committed 273system.cpu.commit.branches 12326938 # Number of branches committed 274system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. 275system.cpu.commit.int_insts 220339549 # Number of committed integer instructions. 276system.cpu.commit.function_calls 0 # Number of function calls committed. 277system.cpu.commit.bw_lim_events 6862894 # number cycles where commit BW limit reached 278system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 279system.cpu.rob.rob_reads 488188483 # The number of ROB reads 280system.cpu.rob.rob_writes 703031879 # The number of ROB writes 281system.cpu.timesIdled 1775 # Number of times that the entire CPU went into an idle state and unscheduled itself 282system.cpu.idleCycles 79592 # Total number of cycles that the CPU has spent unscheduled due to idling 283system.cpu.committedInsts 132071192 # Number of Instructions Simulated 284system.cpu.committedOps 221362960 # Number of Ops (including micro ops) Simulated 285system.cpu.committedInsts_total 132071192 # Number of Instructions Simulated 286system.cpu.cpi 1.278352 # CPI: Cycles Per Instruction 287system.cpu.cpi_total 1.278352 # CPI: Total CPI of All Threads 288system.cpu.ipc 0.782257 # IPC: Instructions Per Cycle 289system.cpu.ipc_total 0.782257 # IPC: Total IPC of All Threads 290system.cpu.int_regfile_reads 568126600 # number of integer regfile reads 291system.cpu.int_regfile_writes 302940757 # number of integer regfile writes 292system.cpu.fp_regfile_reads 3504532 # number of floating regfile reads 293system.cpu.fp_regfile_writes 2218521 # number of floating regfile writes 294system.cpu.misc_regfile_reads 139578385 # number of misc regfile reads 295system.cpu.misc_regfile_writes 844 # number of misc regfile writes 296system.cpu.icache.replacements 5271 # number of replacements 297system.cpu.icache.tagsinuse 1637.773069 # Cycle average of tags in use 298system.cpu.icache.total_refs 25687510 # Total number of references to valid blocks. 299system.cpu.icache.sampled_refs 7238 # Sample count of references to valid blocks. 300system.cpu.icache.avg_refs 3548.979000 # Average number of references to valid blocks. 301system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 302system.cpu.icache.occ_blocks::cpu.inst 1637.773069 # Average occupied blocks per requestor 303system.cpu.icache.occ_percent::cpu.inst 0.799694 # Average percentage of cache occupancy 304system.cpu.icache.occ_percent::total 0.799694 # Average percentage of cache occupancy 305system.cpu.icache.ReadReq_hits::cpu.inst 25687510 # number of ReadReq hits 306system.cpu.icache.ReadReq_hits::total 25687510 # number of ReadReq hits 307system.cpu.icache.demand_hits::cpu.inst 25687510 # number of demand (read+write) hits 308system.cpu.icache.demand_hits::total 25687510 # number of demand (read+write) hits 309system.cpu.icache.overall_hits::cpu.inst 25687510 # number of overall hits 310system.cpu.icache.overall_hits::total 25687510 # number of overall hits 311system.cpu.icache.ReadReq_misses::cpu.inst 8780 # number of ReadReq misses 312system.cpu.icache.ReadReq_misses::total 8780 # number of ReadReq misses 313system.cpu.icache.demand_misses::cpu.inst 8780 # number of demand (read+write) misses 314system.cpu.icache.demand_misses::total 8780 # number of demand (read+write) misses 315system.cpu.icache.overall_misses::cpu.inst 8780 # number of overall misses 316system.cpu.icache.overall_misses::total 8780 # number of overall misses 317system.cpu.icache.ReadReq_miss_latency::cpu.inst 192794500 # number of ReadReq miss cycles 318system.cpu.icache.ReadReq_miss_latency::total 192794500 # number of ReadReq miss cycles 319system.cpu.icache.demand_miss_latency::cpu.inst 192794500 # number of demand (read+write) miss cycles 320system.cpu.icache.demand_miss_latency::total 192794500 # number of demand (read+write) miss cycles 321system.cpu.icache.overall_miss_latency::cpu.inst 192794500 # number of overall miss cycles 322system.cpu.icache.overall_miss_latency::total 192794500 # number of overall miss cycles 323system.cpu.icache.ReadReq_accesses::cpu.inst 25696290 # number of ReadReq accesses(hits+misses) 324system.cpu.icache.ReadReq_accesses::total 25696290 # number of ReadReq accesses(hits+misses) 325system.cpu.icache.demand_accesses::cpu.inst 25696290 # number of demand (read+write) accesses 326system.cpu.icache.demand_accesses::total 25696290 # number of demand (read+write) accesses 327system.cpu.icache.overall_accesses::cpu.inst 25696290 # number of overall (read+write) accesses 328system.cpu.icache.overall_accesses::total 25696290 # number of overall (read+write) accesses 329system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000342 # miss rate for ReadReq accesses 330system.cpu.icache.ReadReq_miss_rate::total 0.000342 # miss rate for ReadReq accesses 331system.cpu.icache.demand_miss_rate::cpu.inst 0.000342 # miss rate for demand accesses 332system.cpu.icache.demand_miss_rate::total 0.000342 # miss rate for demand accesses 333system.cpu.icache.overall_miss_rate::cpu.inst 0.000342 # miss rate for overall accesses 334system.cpu.icache.overall_miss_rate::total 0.000342 # miss rate for overall accesses 335system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21958.371298 # average ReadReq miss latency 336system.cpu.icache.ReadReq_avg_miss_latency::total 21958.371298 # average ReadReq miss latency 337system.cpu.icache.demand_avg_miss_latency::cpu.inst 21958.371298 # average overall miss latency 338system.cpu.icache.demand_avg_miss_latency::total 21958.371298 # average overall miss latency 339system.cpu.icache.overall_avg_miss_latency::cpu.inst 21958.371298 # average overall miss latency 340system.cpu.icache.overall_avg_miss_latency::total 21958.371298 # average overall miss latency 341system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 342system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 343system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 344system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 345system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 346system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 347system.cpu.icache.fast_writes 0 # number of fast writes performed 348system.cpu.icache.cache_copies 0 # number of cache copies performed 349system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1357 # number of ReadReq MSHR hits 350system.cpu.icache.ReadReq_mshr_hits::total 1357 # number of ReadReq MSHR hits 351system.cpu.icache.demand_mshr_hits::cpu.inst 1357 # number of demand (read+write) MSHR hits 352system.cpu.icache.demand_mshr_hits::total 1357 # number of demand (read+write) MSHR hits 353system.cpu.icache.overall_mshr_hits::cpu.inst 1357 # number of overall MSHR hits 354system.cpu.icache.overall_mshr_hits::total 1357 # number of overall MSHR hits 355system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7423 # number of ReadReq MSHR misses 356system.cpu.icache.ReadReq_mshr_misses::total 7423 # number of ReadReq MSHR misses 357system.cpu.icache.demand_mshr_misses::cpu.inst 7423 # number of demand (read+write) MSHR misses 358system.cpu.icache.demand_mshr_misses::total 7423 # number of demand (read+write) MSHR misses 359system.cpu.icache.overall_mshr_misses::cpu.inst 7423 # number of overall MSHR misses 360system.cpu.icache.overall_mshr_misses::total 7423 # number of overall MSHR misses 361system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 135764500 # number of ReadReq MSHR miss cycles 362system.cpu.icache.ReadReq_mshr_miss_latency::total 135764500 # number of ReadReq MSHR miss cycles 363system.cpu.icache.demand_mshr_miss_latency::cpu.inst 135764500 # number of demand (read+write) MSHR miss cycles 364system.cpu.icache.demand_mshr_miss_latency::total 135764500 # number of demand (read+write) MSHR miss cycles 365system.cpu.icache.overall_mshr_miss_latency::cpu.inst 135764500 # number of overall MSHR miss cycles 366system.cpu.icache.overall_mshr_miss_latency::total 135764500 # number of overall MSHR miss cycles 367system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000289 # mshr miss rate for ReadReq accesses 368system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000289 # mshr miss rate for ReadReq accesses 369system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000289 # mshr miss rate for demand accesses 370system.cpu.icache.demand_mshr_miss_rate::total 0.000289 # mshr miss rate for demand accesses 371system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000289 # mshr miss rate for overall accesses 372system.cpu.icache.overall_mshr_miss_rate::total 0.000289 # mshr miss rate for overall accesses 373system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18289.707665 # average ReadReq mshr miss latency 374system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18289.707665 # average ReadReq mshr miss latency 375system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18289.707665 # average overall mshr miss latency 376system.cpu.icache.demand_avg_mshr_miss_latency::total 18289.707665 # average overall mshr miss latency 377system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18289.707665 # average overall mshr miss latency 378system.cpu.icache.overall_avg_mshr_miss_latency::total 18289.707665 # average overall mshr miss latency 379system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 380system.cpu.dcache.replacements 57 # number of replacements 381system.cpu.dcache.tagsinuse 1420.532831 # Cycle average of tags in use 382system.cpu.dcache.total_refs 68760800 # Total number of references to valid blocks. 383system.cpu.dcache.sampled_refs 1983 # Sample count of references to valid blocks. 384system.cpu.dcache.avg_refs 34675.138679 # Average number of references to valid blocks. 385system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 386system.cpu.dcache.occ_blocks::cpu.data 1420.532831 # Average occupied blocks per requestor 387system.cpu.dcache.occ_percent::cpu.data 0.346810 # Average percentage of cache occupancy 388system.cpu.dcache.occ_percent::total 0.346810 # Average percentage of cache occupancy 389system.cpu.dcache.ReadReq_hits::cpu.data 48246578 # number of ReadReq hits 390system.cpu.dcache.ReadReq_hits::total 48246578 # number of ReadReq hits 391system.cpu.dcache.WriteReq_hits::cpu.data 20513979 # number of WriteReq hits 392system.cpu.dcache.WriteReq_hits::total 20513979 # number of WriteReq hits 393system.cpu.dcache.demand_hits::cpu.data 68760557 # number of demand (read+write) hits 394system.cpu.dcache.demand_hits::total 68760557 # number of demand (read+write) hits 395system.cpu.dcache.overall_hits::cpu.data 68760557 # number of overall hits 396system.cpu.dcache.overall_hits::total 68760557 # number of overall hits 397system.cpu.dcache.ReadReq_misses::cpu.data 811 # number of ReadReq misses 398system.cpu.dcache.ReadReq_misses::total 811 # number of ReadReq misses 399system.cpu.dcache.WriteReq_misses::cpu.data 1751 # number of WriteReq misses 400system.cpu.dcache.WriteReq_misses::total 1751 # number of WriteReq misses 401system.cpu.dcache.demand_misses::cpu.data 2562 # number of demand (read+write) misses 402system.cpu.dcache.demand_misses::total 2562 # number of demand (read+write) misses 403system.cpu.dcache.overall_misses::cpu.data 2562 # number of overall misses 404system.cpu.dcache.overall_misses::total 2562 # number of overall misses 405system.cpu.dcache.ReadReq_miss_latency::cpu.data 28099500 # number of ReadReq miss cycles 406system.cpu.dcache.ReadReq_miss_latency::total 28099500 # number of ReadReq miss cycles 407system.cpu.dcache.WriteReq_miss_latency::cpu.data 66966000 # number of WriteReq miss cycles 408system.cpu.dcache.WriteReq_miss_latency::total 66966000 # number of WriteReq miss cycles 409system.cpu.dcache.demand_miss_latency::cpu.data 95065500 # number of demand (read+write) miss cycles 410system.cpu.dcache.demand_miss_latency::total 95065500 # number of demand (read+write) miss cycles 411system.cpu.dcache.overall_miss_latency::cpu.data 95065500 # number of overall miss cycles 412system.cpu.dcache.overall_miss_latency::total 95065500 # number of overall miss cycles 413system.cpu.dcache.ReadReq_accesses::cpu.data 48247389 # number of ReadReq accesses(hits+misses) 414system.cpu.dcache.ReadReq_accesses::total 48247389 # number of ReadReq accesses(hits+misses) 415system.cpu.dcache.WriteReq_accesses::cpu.data 20515730 # number of WriteReq accesses(hits+misses) 416system.cpu.dcache.WriteReq_accesses::total 20515730 # number of WriteReq accesses(hits+misses) 417system.cpu.dcache.demand_accesses::cpu.data 68763119 # number of demand (read+write) accesses 418system.cpu.dcache.demand_accesses::total 68763119 # number of demand (read+write) accesses 419system.cpu.dcache.overall_accesses::cpu.data 68763119 # number of overall (read+write) accesses 420system.cpu.dcache.overall_accesses::total 68763119 # number of overall (read+write) accesses 421system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000017 # miss rate for ReadReq accesses 422system.cpu.dcache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses 423system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000085 # miss rate for WriteReq accesses 424system.cpu.dcache.WriteReq_miss_rate::total 0.000085 # miss rate for WriteReq accesses 425system.cpu.dcache.demand_miss_rate::cpu.data 0.000037 # miss rate for demand accesses 426system.cpu.dcache.demand_miss_rate::total 0.000037 # miss rate for demand accesses 427system.cpu.dcache.overall_miss_rate::cpu.data 0.000037 # miss rate for overall accesses 428system.cpu.dcache.overall_miss_rate::total 0.000037 # miss rate for overall accesses 429system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34647.965475 # average ReadReq miss latency 430system.cpu.dcache.ReadReq_avg_miss_latency::total 34647.965475 # average ReadReq miss latency 431system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38244.431753 # average WriteReq miss latency 432system.cpu.dcache.WriteReq_avg_miss_latency::total 38244.431753 # average WriteReq miss latency 433system.cpu.dcache.demand_avg_miss_latency::cpu.data 37105.971897 # average overall miss latency 434system.cpu.dcache.demand_avg_miss_latency::total 37105.971897 # average overall miss latency 435system.cpu.dcache.overall_avg_miss_latency::cpu.data 37105.971897 # average overall miss latency 436system.cpu.dcache.overall_avg_miss_latency::total 37105.971897 # average overall miss latency 437system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 438system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 439system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 440system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 441system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 442system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 443system.cpu.dcache.fast_writes 0 # number of fast writes performed 444system.cpu.dcache.cache_copies 0 # number of cache copies performed 445system.cpu.dcache.writebacks::writebacks 14 # number of writebacks 446system.cpu.dcache.writebacks::total 14 # number of writebacks 447system.cpu.dcache.ReadReq_mshr_hits::cpu.data 389 # number of ReadReq MSHR hits 448system.cpu.dcache.ReadReq_mshr_hits::total 389 # number of ReadReq MSHR hits 449system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3 # number of WriteReq MSHR hits 450system.cpu.dcache.WriteReq_mshr_hits::total 3 # number of WriteReq MSHR hits 451system.cpu.dcache.demand_mshr_hits::cpu.data 392 # number of demand (read+write) MSHR hits 452system.cpu.dcache.demand_mshr_hits::total 392 # number of demand (read+write) MSHR hits 453system.cpu.dcache.overall_mshr_hits::cpu.data 392 # number of overall MSHR hits 454system.cpu.dcache.overall_mshr_hits::total 392 # number of overall MSHR hits 455system.cpu.dcache.ReadReq_mshr_misses::cpu.data 422 # number of ReadReq MSHR misses 456system.cpu.dcache.ReadReq_mshr_misses::total 422 # number of ReadReq MSHR misses 457system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses 458system.cpu.dcache.WriteReq_mshr_misses::total 1748 # number of WriteReq MSHR misses 459system.cpu.dcache.demand_mshr_misses::cpu.data 2170 # number of demand (read+write) MSHR misses 460system.cpu.dcache.demand_mshr_misses::total 2170 # number of demand (read+write) MSHR misses 461system.cpu.dcache.overall_mshr_misses::cpu.data 2170 # number of overall MSHR misses 462system.cpu.dcache.overall_mshr_misses::total 2170 # number of overall MSHR misses 463system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14825500 # number of ReadReq MSHR miss cycles 464system.cpu.dcache.ReadReq_mshr_miss_latency::total 14825500 # number of ReadReq MSHR miss cycles 465system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 61621000 # number of WriteReq MSHR miss cycles 466system.cpu.dcache.WriteReq_mshr_miss_latency::total 61621000 # number of WriteReq MSHR miss cycles 467system.cpu.dcache.demand_mshr_miss_latency::cpu.data 76446500 # number of demand (read+write) MSHR miss cycles 468system.cpu.dcache.demand_mshr_miss_latency::total 76446500 # number of demand (read+write) MSHR miss cycles 469system.cpu.dcache.overall_mshr_miss_latency::cpu.data 76446500 # number of overall MSHR miss cycles 470system.cpu.dcache.overall_mshr_miss_latency::total 76446500 # number of overall MSHR miss cycles 471system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses 472system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses 473system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000085 # mshr miss rate for WriteReq accesses 474system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000085 # mshr miss rate for WriteReq accesses 475system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for demand accesses 476system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses 477system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses 478system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses 479system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35131.516588 # average ReadReq mshr miss latency 480system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35131.516588 # average ReadReq mshr miss latency 481system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35252.288330 # average WriteReq mshr miss latency 482system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35252.288330 # average WriteReq mshr miss latency 483system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35228.801843 # average overall mshr miss latency 484system.cpu.dcache.demand_avg_mshr_miss_latency::total 35228.801843 # average overall mshr miss latency 485system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35228.801843 # average overall mshr miss latency 486system.cpu.dcache.overall_avg_mshr_miss_latency::total 35228.801843 # average overall mshr miss latency 487system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 488system.cpu.l2cache.replacements 0 # number of replacements 489system.cpu.l2cache.tagsinuse 2557.455601 # Cycle average of tags in use 490system.cpu.l2cache.total_refs 3843 # Total number of references to valid blocks. 491system.cpu.l2cache.sampled_refs 3822 # Sample count of references to valid blocks. 492system.cpu.l2cache.avg_refs 1.005495 # Average number of references to valid blocks. 493system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 494system.cpu.l2cache.occ_blocks::writebacks 1.544201 # Average occupied blocks per requestor 495system.cpu.l2cache.occ_blocks::cpu.inst 2269.052334 # Average occupied blocks per requestor 496system.cpu.l2cache.occ_blocks::cpu.data 286.859067 # Average occupied blocks per requestor 497system.cpu.l2cache.occ_percent::writebacks 0.000047 # Average percentage of cache occupancy 498system.cpu.l2cache.occ_percent::cpu.inst 0.069246 # Average percentage of cache occupancy 499system.cpu.l2cache.occ_percent::cpu.data 0.008754 # Average percentage of cache occupancy 500system.cpu.l2cache.occ_percent::total 0.078047 # Average percentage of cache occupancy 501system.cpu.l2cache.ReadReq_hits::cpu.inst 3810 # number of ReadReq hits 502system.cpu.l2cache.ReadReq_hits::cpu.data 30 # number of ReadReq hits 503system.cpu.l2cache.ReadReq_hits::total 3840 # number of ReadReq hits 504system.cpu.l2cache.Writeback_hits::writebacks 14 # number of Writeback hits 505system.cpu.l2cache.Writeback_hits::total 14 # number of Writeback hits 506system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits 507system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits 508system.cpu.l2cache.ReadExReq_hits::cpu.data 7 # number of ReadExReq hits 509system.cpu.l2cache.ReadExReq_hits::total 7 # number of ReadExReq hits 510system.cpu.l2cache.demand_hits::cpu.inst 3810 # number of demand (read+write) hits 511system.cpu.l2cache.demand_hits::cpu.data 37 # number of demand (read+write) hits 512system.cpu.l2cache.demand_hits::total 3847 # number of demand (read+write) hits 513system.cpu.l2cache.overall_hits::cpu.inst 3810 # number of overall hits 514system.cpu.l2cache.overall_hits::cpu.data 37 # number of overall hits 515system.cpu.l2cache.overall_hits::total 3847 # number of overall hits 516system.cpu.l2cache.ReadReq_misses::cpu.inst 3428 # number of ReadReq misses 517system.cpu.l2cache.ReadReq_misses::cpu.data 391 # number of ReadReq misses 518system.cpu.l2cache.ReadReq_misses::total 3819 # number of ReadReq misses 519system.cpu.l2cache.UpgradeReq_misses::cpu.data 184 # number of UpgradeReq misses 520system.cpu.l2cache.UpgradeReq_misses::total 184 # number of UpgradeReq misses 521system.cpu.l2cache.ReadExReq_misses::cpu.data 1557 # number of ReadExReq misses 522system.cpu.l2cache.ReadExReq_misses::total 1557 # number of ReadExReq misses 523system.cpu.l2cache.demand_misses::cpu.inst 3428 # number of demand (read+write) misses 524system.cpu.l2cache.demand_misses::cpu.data 1948 # number of demand (read+write) misses 525system.cpu.l2cache.demand_misses::total 5376 # number of demand (read+write) misses 526system.cpu.l2cache.overall_misses::cpu.inst 3428 # number of overall misses 527system.cpu.l2cache.overall_misses::cpu.data 1948 # number of overall misses 528system.cpu.l2cache.overall_misses::total 5376 # number of overall misses 529system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 120468000 # number of ReadReq miss cycles 530system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14185500 # number of ReadReq miss cycles 531system.cpu.l2cache.ReadReq_miss_latency::total 134653500 # number of ReadReq miss cycles 532system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 53721000 # number of ReadExReq miss cycles 533system.cpu.l2cache.ReadExReq_miss_latency::total 53721000 # number of ReadExReq miss cycles 534system.cpu.l2cache.demand_miss_latency::cpu.inst 120468000 # number of demand (read+write) miss cycles 535system.cpu.l2cache.demand_miss_latency::cpu.data 67906500 # number of demand (read+write) miss cycles 536system.cpu.l2cache.demand_miss_latency::total 188374500 # number of demand (read+write) miss cycles 537system.cpu.l2cache.overall_miss_latency::cpu.inst 120468000 # number of overall miss cycles 538system.cpu.l2cache.overall_miss_latency::cpu.data 67906500 # number of overall miss cycles 539system.cpu.l2cache.overall_miss_latency::total 188374500 # number of overall miss cycles 540system.cpu.l2cache.ReadReq_accesses::cpu.inst 7238 # number of ReadReq accesses(hits+misses) 541system.cpu.l2cache.ReadReq_accesses::cpu.data 421 # number of ReadReq accesses(hits+misses) 542system.cpu.l2cache.ReadReq_accesses::total 7659 # number of ReadReq accesses(hits+misses) 543system.cpu.l2cache.Writeback_accesses::writebacks 14 # number of Writeback accesses(hits+misses) 544system.cpu.l2cache.Writeback_accesses::total 14 # number of Writeback accesses(hits+misses) 545system.cpu.l2cache.UpgradeReq_accesses::cpu.data 185 # number of UpgradeReq accesses(hits+misses) 546system.cpu.l2cache.UpgradeReq_accesses::total 185 # number of UpgradeReq accesses(hits+misses) 547system.cpu.l2cache.ReadExReq_accesses::cpu.data 1564 # number of ReadExReq accesses(hits+misses) 548system.cpu.l2cache.ReadExReq_accesses::total 1564 # number of ReadExReq accesses(hits+misses) 549system.cpu.l2cache.demand_accesses::cpu.inst 7238 # number of demand (read+write) accesses 550system.cpu.l2cache.demand_accesses::cpu.data 1985 # number of demand (read+write) accesses 551system.cpu.l2cache.demand_accesses::total 9223 # number of demand (read+write) accesses 552system.cpu.l2cache.overall_accesses::cpu.inst 7238 # number of overall (read+write) accesses 553system.cpu.l2cache.overall_accesses::cpu.data 1985 # number of overall (read+write) accesses 554system.cpu.l2cache.overall_accesses::total 9223 # number of overall (read+write) accesses 555system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.473611 # miss rate for ReadReq accesses 556system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.928741 # miss rate for ReadReq accesses 557system.cpu.l2cache.ReadReq_miss_rate::total 0.498629 # miss rate for ReadReq accesses 558system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.994595 # miss rate for UpgradeReq accesses 559system.cpu.l2cache.UpgradeReq_miss_rate::total 0.994595 # miss rate for UpgradeReq accesses 560system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.995524 # miss rate for ReadExReq accesses 561system.cpu.l2cache.ReadExReq_miss_rate::total 0.995524 # miss rate for ReadExReq accesses 562system.cpu.l2cache.demand_miss_rate::cpu.inst 0.473611 # miss rate for demand accesses 563system.cpu.l2cache.demand_miss_rate::cpu.data 0.981360 # miss rate for demand accesses 564system.cpu.l2cache.demand_miss_rate::total 0.582891 # miss rate for demand accesses 565system.cpu.l2cache.overall_miss_rate::cpu.inst 0.473611 # miss rate for overall accesses 566system.cpu.l2cache.overall_miss_rate::cpu.data 0.981360 # miss rate for overall accesses 567system.cpu.l2cache.overall_miss_rate::total 0.582891 # miss rate for overall accesses 568system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35142.357060 # average ReadReq miss latency 569system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 36280.051151 # average ReadReq miss latency 570system.cpu.l2cache.ReadReq_avg_miss_latency::total 35258.837392 # average ReadReq miss latency 571system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34502.890173 # average ReadExReq miss latency 572system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34502.890173 # average ReadExReq miss latency 573system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35142.357060 # average overall miss latency 574system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34859.599589 # average overall miss latency 575system.cpu.l2cache.demand_avg_miss_latency::total 35039.899554 # average overall miss latency 576system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35142.357060 # average overall miss latency 577system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34859.599589 # average overall miss latency 578system.cpu.l2cache.overall_avg_miss_latency::total 35039.899554 # average overall miss latency 579system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 580system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 581system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 582system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 583system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 584system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 585system.cpu.l2cache.fast_writes 0 # number of fast writes performed 586system.cpu.l2cache.cache_copies 0 # number of cache copies performed 587system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3428 # number of ReadReq MSHR misses 588system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 391 # number of ReadReq MSHR misses 589system.cpu.l2cache.ReadReq_mshr_misses::total 3819 # number of ReadReq MSHR misses 590system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 184 # number of UpgradeReq MSHR misses 591system.cpu.l2cache.UpgradeReq_mshr_misses::total 184 # number of UpgradeReq MSHR misses 592system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1557 # number of ReadExReq MSHR misses 593system.cpu.l2cache.ReadExReq_mshr_misses::total 1557 # number of ReadExReq MSHR misses 594system.cpu.l2cache.demand_mshr_misses::cpu.inst 3428 # number of demand (read+write) MSHR misses 595system.cpu.l2cache.demand_mshr_misses::cpu.data 1948 # number of demand (read+write) MSHR misses 596system.cpu.l2cache.demand_mshr_misses::total 5376 # number of demand (read+write) MSHR misses 597system.cpu.l2cache.overall_mshr_misses::cpu.inst 3428 # number of overall MSHR misses 598system.cpu.l2cache.overall_mshr_misses::cpu.data 1948 # number of overall MSHR misses 599system.cpu.l2cache.overall_mshr_misses::total 5376 # number of overall MSHR misses 600system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 109517000 # number of ReadReq MSHR miss cycles 601system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12953500 # number of ReadReq MSHR miss cycles 602system.cpu.l2cache.ReadReq_mshr_miss_latency::total 122470500 # number of ReadReq MSHR miss cycles 603system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 5704000 # number of UpgradeReq MSHR miss cycles 604system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 5704000 # number of UpgradeReq MSHR miss cycles 605system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48730500 # number of ReadExReq MSHR miss cycles 606system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48730500 # number of ReadExReq MSHR miss cycles 607system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 109517000 # number of demand (read+write) MSHR miss cycles 608system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 61684000 # number of demand (read+write) MSHR miss cycles 609system.cpu.l2cache.demand_mshr_miss_latency::total 171201000 # number of demand (read+write) MSHR miss cycles 610system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 109517000 # number of overall MSHR miss cycles 611system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 61684000 # number of overall MSHR miss cycles 612system.cpu.l2cache.overall_mshr_miss_latency::total 171201000 # number of overall MSHR miss cycles 613system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.473611 # mshr miss rate for ReadReq accesses 614system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.928741 # mshr miss rate for ReadReq accesses 615system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.498629 # mshr miss rate for ReadReq accesses 616system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.994595 # mshr miss rate for UpgradeReq accesses 617system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.994595 # mshr miss rate for UpgradeReq accesses 618system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.995524 # mshr miss rate for ReadExReq accesses 619system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.995524 # mshr miss rate for ReadExReq accesses 620system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.473611 # mshr miss rate for demand accesses 621system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.981360 # mshr miss rate for demand accesses 622system.cpu.l2cache.demand_mshr_miss_rate::total 0.582891 # mshr miss rate for demand accesses 623system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.473611 # mshr miss rate for overall accesses 624system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.981360 # mshr miss rate for overall accesses 625system.cpu.l2cache.overall_mshr_miss_rate::total 0.582891 # mshr miss rate for overall accesses 626system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31947.782964 # average ReadReq mshr miss latency 627system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33129.156010 # average ReadReq mshr miss latency 628system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32068.735271 # average ReadReq mshr miss latency 629system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency 630system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency 631system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31297.687861 # average ReadExReq mshr miss latency 632system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31297.687861 # average ReadExReq mshr miss latency 633system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31947.782964 # average overall mshr miss latency 634system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31665.297741 # average overall mshr miss latency 635system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31845.424107 # average overall mshr miss latency 636system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31947.782964 # average overall mshr miss latency 637system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31665.297741 # average overall mshr miss latency 638system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31845.424107 # average overall mshr miss latency 639system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 640 641---------- End Simulation Statistics ---------- 642