stats.txt revision 9039:9a22621c741c
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.087752 # Number of seconds simulated 4sim_ticks 87751730000 # Number of ticks simulated 5final_tick 87751730000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 56809 # Simulator instruction rate (inst/s) 8host_op_rate 95217 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 37745520 # Simulator tick rate (ticks/s) 10host_mem_usage 259224 # Number of bytes of host memory used 11host_seconds 2324.83 # Real time elapsed on the host 12sim_insts 132071227 # Number of instructions simulated 13sim_ops 221363017 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 345024 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 219584 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 0 # Number of bytes written to this memory 17system.physmem.num_reads 5391 # Number of read requests responded to by this memory 18system.physmem.num_writes 0 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory 20system.physmem.bw_read 3931820 # Total read bandwidth from this memory (bytes/s) 21system.physmem.bw_inst_read 2502332 # Instruction read bandwidth from this memory (bytes/s) 22system.physmem.bw_total 3931820 # Total bandwidth to/from this memory (bytes/s) 23system.cpu.workload.num_syscalls 400 # Number of system calls 24system.cpu.numCycles 175503461 # number of cpu cycles simulated 25system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 26system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 27system.cpu.BPredUnit.lookups 20929970 # Number of BP lookups 28system.cpu.BPredUnit.condPredicted 20929970 # Number of conditional branches predicted 29system.cpu.BPredUnit.condIncorrect 2208761 # Number of conditional branches incorrect 30system.cpu.BPredUnit.BTBLookups 15515509 # Number of BTB lookups 31system.cpu.BPredUnit.BTBHits 13857635 # Number of BTB hits 32system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 33system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. 34system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. 35system.cpu.fetch.icacheStallCycles 27320294 # Number of cycles fetch is stalled on an Icache miss 36system.cpu.fetch.Insts 226942709 # Number of instructions fetch has processed 37system.cpu.fetch.Branches 20929970 # Number of branches that fetch encountered 38system.cpu.fetch.predictedBranches 13857635 # Number of branches that fetch has predicted taken 39system.cpu.fetch.Cycles 59854483 # Number of cycles fetch has run and was not squashing or blocked 40system.cpu.fetch.SquashCycles 19459786 # Number of cycles fetch has spent squashing 41system.cpu.fetch.BlockedCycles 71271521 # Number of cycles fetch has spent blocked 42system.cpu.fetch.MiscStallCycles 647 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 43system.cpu.fetch.PendingTrapStallCycles 5211 # Number of stall cycles due to pending traps 44system.cpu.fetch.CacheLines 25822554 # Number of cache lines fetched 45system.cpu.fetch.IcacheSquashes 471165 # Number of outstanding Icache misses that were squashed 46system.cpu.fetch.rateDist::samples 175426420 # Number of instructions fetched each cycle (Total) 47system.cpu.fetch.rateDist::mean 2.136612 # Number of instructions fetched each cycle (Total) 48system.cpu.fetch.rateDist::stdev 3.300359 # Number of instructions fetched each cycle (Total) 49system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 50system.cpu.fetch.rateDist::0 117249103 66.84% 66.84% # Number of instructions fetched each cycle (Total) 51system.cpu.fetch.rateDist::1 3234615 1.84% 68.68% # Number of instructions fetched each cycle (Total) 52system.cpu.fetch.rateDist::2 2477718 1.41% 70.09% # Number of instructions fetched each cycle (Total) 53system.cpu.fetch.rateDist::3 3147881 1.79% 71.89% # Number of instructions fetched each cycle (Total) 54system.cpu.fetch.rateDist::4 3542128 2.02% 73.91% # Number of instructions fetched each cycle (Total) 55system.cpu.fetch.rateDist::5 3766355 2.15% 76.05% # Number of instructions fetched each cycle (Total) 56system.cpu.fetch.rateDist::6 4530628 2.58% 78.64% # Number of instructions fetched each cycle (Total) 57system.cpu.fetch.rateDist::7 2823565 1.61% 80.25% # Number of instructions fetched each cycle (Total) 58system.cpu.fetch.rateDist::8 34654427 19.75% 100.00% # Number of instructions fetched each cycle (Total) 59system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 60system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 61system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 62system.cpu.fetch.rateDist::total 175426420 # Number of instructions fetched each cycle (Total) 63system.cpu.fetch.branchRate 0.119257 # Number of branch fetches per cycle 64system.cpu.fetch.rate 1.293095 # Number of inst fetches per cycle 65system.cpu.decode.IdleCycles 40654970 # Number of cycles decode is idle 66system.cpu.decode.BlockedCycles 61059749 # Number of cycles decode is blocked 67system.cpu.decode.RunCycles 46547974 # Number of cycles decode is running 68system.cpu.decode.UnblockCycles 10189463 # Number of cycles decode is unblocking 69system.cpu.decode.SquashCycles 16974264 # Number of cycles decode is squashing 70system.cpu.decode.DecodedInsts 365977737 # Number of instructions handled by decode 71system.cpu.rename.SquashCycles 16974264 # Number of cycles rename is squashing 72system.cpu.rename.IdleCycles 48548849 # Number of cycles rename is idle 73system.cpu.rename.BlockCycles 16319097 # Number of cycles rename is blocking 74system.cpu.rename.serializeStallCycles 23046 # count of cycles rename stalled for serializing inst 75system.cpu.rename.RunCycles 48140036 # Number of cycles rename is running 76system.cpu.rename.UnblockCycles 45421128 # Number of cycles rename is unblocking 77system.cpu.rename.RenamedInsts 356799059 # Number of instructions processed by rename 78system.cpu.rename.ROBFullEvents 33 # Number of times rename has blocked due to ROB full 79system.cpu.rename.IQFullEvents 20636040 # Number of times rename has blocked due to IQ full 80system.cpu.rename.LSQFullEvents 22537767 # Number of times rename has blocked due to LSQ full 81system.cpu.rename.FullRegisterEvents 2198 # Number of times there has been no free registers 82system.cpu.rename.RenamedOperands 506554560 # Number of destination operands rename has renamed 83system.cpu.rename.RenameLookups 1130537584 # Number of register rename lookups that rename has made 84system.cpu.rename.int_rename_lookups 1120266837 # Number of integer rename lookups 85system.cpu.rename.fp_rename_lookups 10270747 # Number of floating rename lookups 86system.cpu.rename.CommittedMaps 320143989 # Number of HB maps that are committed 87system.cpu.rename.UndoneMaps 186410571 # Number of HB maps that are undone due to squashing 88system.cpu.rename.serializingInsts 1911 # count of serializing insts renamed 89system.cpu.rename.tempSerializingInsts 1906 # count of temporary serializing insts renamed 90system.cpu.rename.skidInsts 95097015 # count of insts added to the skid buffer 91system.cpu.memDep0.insertedLoads 89808446 # Number of loads inserted to the mem dependence unit. 92system.cpu.memDep0.insertedStores 33130186 # Number of stores inserted to the mem dependence unit. 93system.cpu.memDep0.conflictingLoads 59201466 # Number of conflicting loads. 94system.cpu.memDep0.conflictingStores 19519303 # Number of conflicting stores. 95system.cpu.iq.iqInstsAdded 344515408 # Number of instructions added to the IQ (excludes non-spec) 96system.cpu.iq.iqNonSpecInstsAdded 7842 # Number of non-speculative instructions added to the IQ 97system.cpu.iq.iqInstsIssued 270869041 # Number of instructions issued 98system.cpu.iq.iqSquashedInstsIssued 254270 # Number of squashed instructions issued 99system.cpu.iq.iqSquashedInstsExamined 122674827 # Number of squashed instructions iterated over during squash; mainly for profiling 100system.cpu.iq.iqSquashedOperandsExamined 297005948 # Number of squashed operands that are examined and possibly removed from graph 101system.cpu.iq.iqSquashedNonSpecRemoved 6596 # Number of squashed non-spec instructions that were removed 102system.cpu.iq.issued_per_cycle::samples 175426420 # Number of insts issued each cycle 103system.cpu.iq.issued_per_cycle::mean 1.544061 # Number of insts issued each cycle 104system.cpu.iq.issued_per_cycle::stdev 1.467197 # Number of insts issued each cycle 105system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 106system.cpu.iq.issued_per_cycle::0 49131919 28.01% 28.01% # Number of insts issued each cycle 107system.cpu.iq.issued_per_cycle::1 52597597 29.98% 57.99% # Number of insts issued each cycle 108system.cpu.iq.issued_per_cycle::2 34344440 19.58% 77.57% # Number of insts issued each cycle 109system.cpu.iq.issued_per_cycle::3 18981960 10.82% 88.39% # Number of insts issued each cycle 110system.cpu.iq.issued_per_cycle::4 12711399 7.25% 95.63% # Number of insts issued each cycle 111system.cpu.iq.issued_per_cycle::5 4926918 2.81% 98.44% # Number of insts issued each cycle 112system.cpu.iq.issued_per_cycle::6 2079867 1.19% 99.63% # Number of insts issued each cycle 113system.cpu.iq.issued_per_cycle::7 541264 0.31% 99.94% # Number of insts issued each cycle 114system.cpu.iq.issued_per_cycle::8 111056 0.06% 100.00% # Number of insts issued each cycle 115system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 116system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 117system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 118system.cpu.iq.issued_per_cycle::total 175426420 # Number of insts issued each cycle 119system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 120system.cpu.iq.fu_full::IntAlu 91065 3.49% 3.49% # attempts to use FU when none available 121system.cpu.iq.fu_full::IntMult 0 0.00% 3.49% # attempts to use FU when none available 122system.cpu.iq.fu_full::IntDiv 0 0.00% 3.49% # attempts to use FU when none available 123system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.49% # attempts to use FU when none available 124system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.49% # attempts to use FU when none available 125system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.49% # attempts to use FU when none available 126system.cpu.iq.fu_full::FloatMult 0 0.00% 3.49% # attempts to use FU when none available 127system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.49% # attempts to use FU when none available 128system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.49% # attempts to use FU when none available 129system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.49% # attempts to use FU when none available 130system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.49% # attempts to use FU when none available 131system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.49% # attempts to use FU when none available 132system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.49% # attempts to use FU when none available 133system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.49% # attempts to use FU when none available 134system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.49% # attempts to use FU when none available 135system.cpu.iq.fu_full::SimdMult 0 0.00% 3.49% # attempts to use FU when none available 136system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.49% # attempts to use FU when none available 137system.cpu.iq.fu_full::SimdShift 0 0.00% 3.49% # attempts to use FU when none available 138system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.49% # attempts to use FU when none available 139system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.49% # attempts to use FU when none available 140system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.49% # attempts to use FU when none available 141system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.49% # attempts to use FU when none available 142system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.49% # attempts to use FU when none available 143system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.49% # attempts to use FU when none available 144system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.49% # attempts to use FU when none available 145system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.49% # attempts to use FU when none available 146system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.49% # attempts to use FU when none available 147system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.49% # attempts to use FU when none available 148system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.49% # attempts to use FU when none available 149system.cpu.iq.fu_full::MemRead 2241508 85.86% 89.35% # attempts to use FU when none available 150system.cpu.iq.fu_full::MemWrite 277930 10.65% 100.00% # attempts to use FU when none available 151system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 152system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 153system.cpu.iq.FU_type_0::No_OpClass 1212815 0.45% 0.45% # Type of FU issued 154system.cpu.iq.FU_type_0::IntAlu 176257528 65.07% 65.52% # Type of FU issued 155system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.52% # Type of FU issued 156system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.52% # Type of FU issued 157system.cpu.iq.FU_type_0::FloatAdd 1592327 0.59% 66.11% # Type of FU issued 158system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.11% # Type of FU issued 159system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.11% # Type of FU issued 160system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.11% # Type of FU issued 161system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.11% # Type of FU issued 162system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.11% # Type of FU issued 163system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.11% # Type of FU issued 164system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.11% # Type of FU issued 165system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.11% # Type of FU issued 166system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.11% # Type of FU issued 167system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.11% # Type of FU issued 168system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.11% # Type of FU issued 169system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.11% # Type of FU issued 170system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.11% # Type of FU issued 171system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.11% # Type of FU issued 172system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.11% # Type of FU issued 173system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.11% # Type of FU issued 174system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.11% # Type of FU issued 175system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.11% # Type of FU issued 176system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.11% # Type of FU issued 177system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.11% # Type of FU issued 178system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.11% # Type of FU issued 179system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.11% # Type of FU issued 180system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.11% # Type of FU issued 181system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.11% # Type of FU issued 182system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.11% # Type of FU issued 183system.cpu.iq.FU_type_0::MemRead 68300084 25.22% 91.32% # Type of FU issued 184system.cpu.iq.FU_type_0::MemWrite 23506287 8.68% 100.00% # Type of FU issued 185system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 186system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 187system.cpu.iq.FU_type_0::total 270869041 # Type of FU issued 188system.cpu.iq.rate 1.543383 # Inst issue rate 189system.cpu.iq.fu_busy_cnt 2610503 # FU busy when requested 190system.cpu.iq.fu_busy_rate 0.009638 # FU busy rate (busy events/executed inst) 191system.cpu.iq.int_inst_queue_reads 714724682 # Number of integer instruction queue reads 192system.cpu.iq.int_inst_queue_writes 462639790 # Number of integer instruction queue writes 193system.cpu.iq.int_inst_queue_wakeup_accesses 263265519 # Number of integer instruction queue wakeup accesses 194system.cpu.iq.fp_inst_queue_reads 5304593 # Number of floating instruction queue reads 195system.cpu.iq.fp_inst_queue_writes 4857798 # Number of floating instruction queue writes 196system.cpu.iq.fp_inst_queue_wakeup_accesses 2549095 # Number of floating instruction queue wakeup accesses 197system.cpu.iq.int_alu_accesses 269608691 # Number of integer alu accesses 198system.cpu.iq.fp_alu_accesses 2658038 # Number of floating point alu accesses 199system.cpu.iew.lsq.thread0.forwLoads 18925158 # Number of loads that had data forwarded from stores 200system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 201system.cpu.iew.lsq.thread0.squashedLoads 33158856 # Number of loads squashed 202system.cpu.iew.lsq.thread0.ignoredResponses 30567 # Number of memory responses ignored because the instruction is squashed 203system.cpu.iew.lsq.thread0.memOrderViolation 304625 # Number of memory ordering violations 204system.cpu.iew.lsq.thread0.squashedStores 12614470 # Number of stores squashed 205system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 206system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 207system.cpu.iew.lsq.thread0.rescheduledLoads 47486 # Number of loads that were rescheduled 208system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 209system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 210system.cpu.iew.iewSquashCycles 16974264 # Number of cycles IEW is squashing 211system.cpu.iew.iewBlockCycles 523635 # Number of cycles IEW is blocking 212system.cpu.iew.iewUnblockCycles 253200 # Number of cycles IEW is unblocking 213system.cpu.iew.iewDispatchedInsts 344523250 # Number of instructions dispatched to IQ 214system.cpu.iew.iewDispSquashedInsts 297274 # Number of squashed instructions skipped by dispatch 215system.cpu.iew.iewDispLoadInsts 89808446 # Number of dispatched load instructions 216system.cpu.iew.iewDispStoreInsts 33130186 # Number of dispatched store instructions 217system.cpu.iew.iewDispNonSpecInsts 1859 # Number of dispatched non-speculative instructions 218system.cpu.iew.iewIQFullEvents 168556 # Number of times the IQ has become full, causing a stall 219system.cpu.iew.iewLSQFullEvents 31575 # Number of times the LSQ has become full, causing a stall 220system.cpu.iew.memOrderViolationEvents 304625 # Number of memory order violations 221system.cpu.iew.predictedTakenIncorrect 1298513 # Number of branches that were predicted taken incorrectly 222system.cpu.iew.predictedNotTakenIncorrect 1028751 # Number of branches that were predicted not taken incorrectly 223system.cpu.iew.branchMispredicts 2327264 # Number of branch mispredicts detected at execute 224system.cpu.iew.iewExecutedInsts 267763849 # Number of executed instructions 225system.cpu.iew.iewExecLoadInsts 67223329 # Number of load instructions executed 226system.cpu.iew.iewExecSquashedInsts 3105192 # Number of squashed instructions skipped in execute 227system.cpu.iew.exec_swp 0 # number of swp insts executed 228system.cpu.iew.exec_nop 0 # number of nop insts executed 229system.cpu.iew.exec_refs 90337843 # number of memory reference insts executed 230system.cpu.iew.exec_branches 14773998 # Number of branches executed 231system.cpu.iew.exec_stores 23114514 # Number of stores executed 232system.cpu.iew.exec_rate 1.525690 # Inst execution rate 233system.cpu.iew.wb_sent 266689649 # cumulative count of insts sent to commit 234system.cpu.iew.wb_count 265814614 # cumulative count of insts written-back 235system.cpu.iew.wb_producers 214459238 # num instructions producing a value 236system.cpu.iew.wb_consumers 504388652 # num instructions consuming a value 237system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 238system.cpu.iew.wb_rate 1.514583 # insts written-back per cycle 239system.cpu.iew.wb_fanout 0.425186 # average fanout of values written-back 240system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 241system.cpu.commit.commitCommittedInsts 132071227 # The number of committed instructions 242system.cpu.commit.commitCommittedOps 221363017 # The number of committed instructions 243system.cpu.commit.commitSquashedInsts 123271968 # The number of squashed insts skipped by commit 244system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards 245system.cpu.commit.branchMispredicts 2209353 # The number of times a branch was mispredicted 246system.cpu.commit.committed_per_cycle::samples 158452156 # Number of insts commited each cycle 247system.cpu.commit.committed_per_cycle::mean 1.397034 # Number of insts commited each cycle 248system.cpu.commit.committed_per_cycle::stdev 1.794480 # Number of insts commited each cycle 249system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 250system.cpu.commit.committed_per_cycle::0 54225216 34.22% 34.22% # Number of insts commited each cycle 251system.cpu.commit.committed_per_cycle::1 60443910 38.15% 72.37% # Number of insts commited each cycle 252system.cpu.commit.committed_per_cycle::2 15544008 9.81% 82.18% # Number of insts commited each cycle 253system.cpu.commit.committed_per_cycle::3 12710691 8.02% 90.20% # Number of insts commited each cycle 254system.cpu.commit.committed_per_cycle::4 4546278 2.87% 93.07% # Number of insts commited each cycle 255system.cpu.commit.committed_per_cycle::5 2974927 1.88% 94.95% # Number of insts commited each cycle 256system.cpu.commit.committed_per_cycle::6 2086566 1.32% 96.26% # Number of insts commited each cycle 257system.cpu.commit.committed_per_cycle::7 1244605 0.79% 97.05% # Number of insts commited each cycle 258system.cpu.commit.committed_per_cycle::8 4675955 2.95% 100.00% # Number of insts commited each cycle 259system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 260system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 261system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 262system.cpu.commit.committed_per_cycle::total 158452156 # Number of insts commited each cycle 263system.cpu.commit.committedInsts 132071227 # Number of instructions committed 264system.cpu.commit.committedOps 221363017 # Number of ops (including micro ops) committed 265system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 266system.cpu.commit.refs 77165306 # Number of memory references committed 267system.cpu.commit.loads 56649590 # Number of loads committed 268system.cpu.commit.membars 0 # Number of memory barriers committed 269system.cpu.commit.branches 12326943 # Number of branches committed 270system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. 271system.cpu.commit.int_insts 220339606 # Number of committed integer instructions. 272system.cpu.commit.function_calls 0 # Number of function calls committed. 273system.cpu.commit.bw_lim_events 4675955 # number cycles where commit BW limit reached 274system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 275system.cpu.rob.rob_reads 498411186 # The number of ROB reads 276system.cpu.rob.rob_writes 706281673 # The number of ROB writes 277system.cpu.timesIdled 1684 # Number of times that the entire CPU went into an idle state and unscheduled itself 278system.cpu.idleCycles 77041 # Total number of cycles that the CPU has spent unscheduled due to idling 279system.cpu.committedInsts 132071227 # Number of Instructions Simulated 280system.cpu.committedOps 221363017 # Number of Ops (including micro ops) Simulated 281system.cpu.committedInsts_total 132071227 # Number of Instructions Simulated 282system.cpu.cpi 1.328855 # CPI: Cycles Per Instruction 283system.cpu.cpi_total 1.328855 # CPI: Total CPI of All Threads 284system.cpu.ipc 0.752528 # IPC: Instructions Per Cycle 285system.cpu.ipc_total 0.752528 # IPC: Total IPC of All Threads 286system.cpu.int_regfile_reads 657510098 # number of integer regfile reads 287system.cpu.int_regfile_writes 365370199 # number of integer regfile writes 288system.cpu.fp_regfile_reads 3509073 # number of floating regfile reads 289system.cpu.fp_regfile_writes 2221147 # number of floating regfile writes 290system.cpu.misc_regfile_reads 139423581 # number of misc regfile reads 291system.cpu.misc_regfile_writes 844 # number of misc regfile writes 292system.cpu.icache.replacements 5601 # number of replacements 293system.cpu.icache.tagsinuse 1627.936468 # Cycle average of tags in use 294system.cpu.icache.total_refs 25813461 # Total number of references to valid blocks. 295system.cpu.icache.sampled_refs 7571 # Sample count of references to valid blocks. 296system.cpu.icache.avg_refs 3409.518029 # Average number of references to valid blocks. 297system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 298system.cpu.icache.occ_blocks::cpu.inst 1627.936468 # Average occupied blocks per requestor 299system.cpu.icache.occ_percent::cpu.inst 0.794891 # Average percentage of cache occupancy 300system.cpu.icache.occ_percent::total 0.794891 # Average percentage of cache occupancy 301system.cpu.icache.ReadReq_hits::cpu.inst 25813461 # number of ReadReq hits 302system.cpu.icache.ReadReq_hits::total 25813461 # number of ReadReq hits 303system.cpu.icache.demand_hits::cpu.inst 25813461 # number of demand (read+write) hits 304system.cpu.icache.demand_hits::total 25813461 # number of demand (read+write) hits 305system.cpu.icache.overall_hits::cpu.inst 25813461 # number of overall hits 306system.cpu.icache.overall_hits::total 25813461 # number of overall hits 307system.cpu.icache.ReadReq_misses::cpu.inst 9093 # number of ReadReq misses 308system.cpu.icache.ReadReq_misses::total 9093 # number of ReadReq misses 309system.cpu.icache.demand_misses::cpu.inst 9093 # number of demand (read+write) misses 310system.cpu.icache.demand_misses::total 9093 # number of demand (read+write) misses 311system.cpu.icache.overall_misses::cpu.inst 9093 # number of overall misses 312system.cpu.icache.overall_misses::total 9093 # number of overall misses 313system.cpu.icache.ReadReq_miss_latency::cpu.inst 187306000 # number of ReadReq miss cycles 314system.cpu.icache.ReadReq_miss_latency::total 187306000 # number of ReadReq miss cycles 315system.cpu.icache.demand_miss_latency::cpu.inst 187306000 # number of demand (read+write) miss cycles 316system.cpu.icache.demand_miss_latency::total 187306000 # number of demand (read+write) miss cycles 317system.cpu.icache.overall_miss_latency::cpu.inst 187306000 # number of overall miss cycles 318system.cpu.icache.overall_miss_latency::total 187306000 # number of overall miss cycles 319system.cpu.icache.ReadReq_accesses::cpu.inst 25822554 # number of ReadReq accesses(hits+misses) 320system.cpu.icache.ReadReq_accesses::total 25822554 # number of ReadReq accesses(hits+misses) 321system.cpu.icache.demand_accesses::cpu.inst 25822554 # number of demand (read+write) accesses 322system.cpu.icache.demand_accesses::total 25822554 # number of demand (read+write) accesses 323system.cpu.icache.overall_accesses::cpu.inst 25822554 # number of overall (read+write) accesses 324system.cpu.icache.overall_accesses::total 25822554 # number of overall (read+write) accesses 325system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000352 # miss rate for ReadReq accesses 326system.cpu.icache.demand_miss_rate::cpu.inst 0.000352 # miss rate for demand accesses 327system.cpu.icache.overall_miss_rate::cpu.inst 0.000352 # miss rate for overall accesses 328system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20598.922248 # average ReadReq miss latency 329system.cpu.icache.demand_avg_miss_latency::cpu.inst 20598.922248 # average overall miss latency 330system.cpu.icache.overall_avg_miss_latency::cpu.inst 20598.922248 # average overall miss latency 331system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 332system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 333system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 334system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 335system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 336system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 337system.cpu.icache.fast_writes 0 # number of fast writes performed 338system.cpu.icache.cache_copies 0 # number of cache copies performed 339system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1367 # number of ReadReq MSHR hits 340system.cpu.icache.ReadReq_mshr_hits::total 1367 # number of ReadReq MSHR hits 341system.cpu.icache.demand_mshr_hits::cpu.inst 1367 # number of demand (read+write) MSHR hits 342system.cpu.icache.demand_mshr_hits::total 1367 # number of demand (read+write) MSHR hits 343system.cpu.icache.overall_mshr_hits::cpu.inst 1367 # number of overall MSHR hits 344system.cpu.icache.overall_mshr_hits::total 1367 # number of overall MSHR hits 345system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7726 # number of ReadReq MSHR misses 346system.cpu.icache.ReadReq_mshr_misses::total 7726 # number of ReadReq MSHR misses 347system.cpu.icache.demand_mshr_misses::cpu.inst 7726 # number of demand (read+write) MSHR misses 348system.cpu.icache.demand_mshr_misses::total 7726 # number of demand (read+write) MSHR misses 349system.cpu.icache.overall_mshr_misses::cpu.inst 7726 # number of overall MSHR misses 350system.cpu.icache.overall_mshr_misses::total 7726 # number of overall MSHR misses 351system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 130634500 # number of ReadReq MSHR miss cycles 352system.cpu.icache.ReadReq_mshr_miss_latency::total 130634500 # number of ReadReq MSHR miss cycles 353system.cpu.icache.demand_mshr_miss_latency::cpu.inst 130634500 # number of demand (read+write) MSHR miss cycles 354system.cpu.icache.demand_mshr_miss_latency::total 130634500 # number of demand (read+write) MSHR miss cycles 355system.cpu.icache.overall_mshr_miss_latency::cpu.inst 130634500 # number of overall MSHR miss cycles 356system.cpu.icache.overall_mshr_miss_latency::total 130634500 # number of overall MSHR miss cycles 357system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for ReadReq accesses 358system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for demand accesses 359system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for overall accesses 360system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16908.426094 # average ReadReq mshr miss latency 361system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16908.426094 # average overall mshr miss latency 362system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16908.426094 # average overall mshr miss latency 363system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 364system.cpu.dcache.replacements 56 # number of replacements 365system.cpu.dcache.tagsinuse 1426.584624 # Cycle average of tags in use 366system.cpu.dcache.total_refs 68642098 # Total number of references to valid blocks. 367system.cpu.dcache.sampled_refs 1997 # Sample count of references to valid blocks. 368system.cpu.dcache.avg_refs 34372.607912 # Average number of references to valid blocks. 369system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 370system.cpu.dcache.occ_blocks::cpu.data 1426.584624 # Average occupied blocks per requestor 371system.cpu.dcache.occ_percent::cpu.data 0.348287 # Average percentage of cache occupancy 372system.cpu.dcache.occ_percent::total 0.348287 # Average percentage of cache occupancy 373system.cpu.dcache.ReadReq_hits::cpu.data 48127880 # number of ReadReq hits 374system.cpu.dcache.ReadReq_hits::total 48127880 # number of ReadReq hits 375system.cpu.dcache.WriteReq_hits::cpu.data 20514014 # number of WriteReq hits 376system.cpu.dcache.WriteReq_hits::total 20514014 # number of WriteReq hits 377system.cpu.dcache.demand_hits::cpu.data 68641894 # number of demand (read+write) hits 378system.cpu.dcache.demand_hits::total 68641894 # number of demand (read+write) hits 379system.cpu.dcache.overall_hits::cpu.data 68641894 # number of overall hits 380system.cpu.dcache.overall_hits::total 68641894 # number of overall hits 381system.cpu.dcache.ReadReq_misses::cpu.data 772 # number of ReadReq misses 382system.cpu.dcache.ReadReq_misses::total 772 # number of ReadReq misses 383system.cpu.dcache.WriteReq_misses::cpu.data 1716 # number of WriteReq misses 384system.cpu.dcache.WriteReq_misses::total 1716 # number of WriteReq misses 385system.cpu.dcache.demand_misses::cpu.data 2488 # number of demand (read+write) misses 386system.cpu.dcache.demand_misses::total 2488 # number of demand (read+write) misses 387system.cpu.dcache.overall_misses::cpu.data 2488 # number of overall misses 388system.cpu.dcache.overall_misses::total 2488 # number of overall misses 389system.cpu.dcache.ReadReq_miss_latency::cpu.data 24823500 # number of ReadReq miss cycles 390system.cpu.dcache.ReadReq_miss_latency::total 24823500 # number of ReadReq miss cycles 391system.cpu.dcache.WriteReq_miss_latency::cpu.data 65115000 # number of WriteReq miss cycles 392system.cpu.dcache.WriteReq_miss_latency::total 65115000 # number of WriteReq miss cycles 393system.cpu.dcache.demand_miss_latency::cpu.data 89938500 # number of demand (read+write) miss cycles 394system.cpu.dcache.demand_miss_latency::total 89938500 # number of demand (read+write) miss cycles 395system.cpu.dcache.overall_miss_latency::cpu.data 89938500 # number of overall miss cycles 396system.cpu.dcache.overall_miss_latency::total 89938500 # number of overall miss cycles 397system.cpu.dcache.ReadReq_accesses::cpu.data 48128652 # number of ReadReq accesses(hits+misses) 398system.cpu.dcache.ReadReq_accesses::total 48128652 # number of ReadReq accesses(hits+misses) 399system.cpu.dcache.WriteReq_accesses::cpu.data 20515730 # number of WriteReq accesses(hits+misses) 400system.cpu.dcache.WriteReq_accesses::total 20515730 # number of WriteReq accesses(hits+misses) 401system.cpu.dcache.demand_accesses::cpu.data 68644382 # number of demand (read+write) accesses 402system.cpu.dcache.demand_accesses::total 68644382 # number of demand (read+write) accesses 403system.cpu.dcache.overall_accesses::cpu.data 68644382 # number of overall (read+write) accesses 404system.cpu.dcache.overall_accesses::total 68644382 # number of overall (read+write) accesses 405system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000016 # miss rate for ReadReq accesses 406system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000084 # miss rate for WriteReq accesses 407system.cpu.dcache.demand_miss_rate::cpu.data 0.000036 # miss rate for demand accesses 408system.cpu.dcache.overall_miss_rate::cpu.data 0.000036 # miss rate for overall accesses 409system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32154.792746 # average ReadReq miss latency 410system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37945.804196 # average WriteReq miss latency 411system.cpu.dcache.demand_avg_miss_latency::cpu.data 36148.914791 # average overall miss latency 412system.cpu.dcache.overall_avg_miss_latency::cpu.data 36148.914791 # average overall miss latency 413system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 414system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 415system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 416system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 417system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 418system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 419system.cpu.dcache.fast_writes 0 # number of fast writes performed 420system.cpu.dcache.cache_copies 0 # number of cache copies performed 421system.cpu.dcache.writebacks::writebacks 13 # number of writebacks 422system.cpu.dcache.writebacks::total 13 # number of writebacks 423system.cpu.dcache.ReadReq_mshr_hits::cpu.data 331 # number of ReadReq MSHR hits 424system.cpu.dcache.ReadReq_mshr_hits::total 331 # number of ReadReq MSHR hits 425system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3 # number of WriteReq MSHR hits 426system.cpu.dcache.WriteReq_mshr_hits::total 3 # number of WriteReq MSHR hits 427system.cpu.dcache.demand_mshr_hits::cpu.data 334 # number of demand (read+write) MSHR hits 428system.cpu.dcache.demand_mshr_hits::total 334 # number of demand (read+write) MSHR hits 429system.cpu.dcache.overall_mshr_hits::cpu.data 334 # number of overall MSHR hits 430system.cpu.dcache.overall_mshr_hits::total 334 # number of overall MSHR hits 431system.cpu.dcache.ReadReq_mshr_misses::cpu.data 441 # number of ReadReq MSHR misses 432system.cpu.dcache.ReadReq_mshr_misses::total 441 # number of ReadReq MSHR misses 433system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1713 # number of WriteReq MSHR misses 434system.cpu.dcache.WriteReq_mshr_misses::total 1713 # number of WriteReq MSHR misses 435system.cpu.dcache.demand_mshr_misses::cpu.data 2154 # number of demand (read+write) MSHR misses 436system.cpu.dcache.demand_mshr_misses::total 2154 # number of demand (read+write) MSHR misses 437system.cpu.dcache.overall_mshr_misses::cpu.data 2154 # number of overall MSHR misses 438system.cpu.dcache.overall_mshr_misses::total 2154 # number of overall MSHR misses 439system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14546500 # number of ReadReq MSHR miss cycles 440system.cpu.dcache.ReadReq_mshr_miss_latency::total 14546500 # number of ReadReq MSHR miss cycles 441system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 59868000 # number of WriteReq MSHR miss cycles 442system.cpu.dcache.WriteReq_mshr_miss_latency::total 59868000 # number of WriteReq MSHR miss cycles 443system.cpu.dcache.demand_mshr_miss_latency::cpu.data 74414500 # number of demand (read+write) MSHR miss cycles 444system.cpu.dcache.demand_mshr_miss_latency::total 74414500 # number of demand (read+write) MSHR miss cycles 445system.cpu.dcache.overall_mshr_miss_latency::cpu.data 74414500 # number of overall MSHR miss cycles 446system.cpu.dcache.overall_mshr_miss_latency::total 74414500 # number of overall MSHR miss cycles 447system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses 448system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000083 # mshr miss rate for WriteReq accesses 449system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000031 # mshr miss rate for demand accesses 450system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000031 # mshr miss rate for overall accesses 451system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32985.260771 # average ReadReq mshr miss latency 452system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34949.211909 # average WriteReq mshr miss latency 453system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34547.121634 # average overall mshr miss latency 454system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34547.121634 # average overall mshr miss latency 455system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 456system.cpu.l2cache.replacements 0 # number of replacements 457system.cpu.l2cache.tagsinuse 2579.336511 # Cycle average of tags in use 458system.cpu.l2cache.total_refs 4173 # Total number of references to valid blocks. 459system.cpu.l2cache.sampled_refs 3841 # Sample count of references to valid blocks. 460system.cpu.l2cache.avg_refs 1.086436 # Average number of references to valid blocks. 461system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 462system.cpu.l2cache.occ_blocks::writebacks 1.713269 # Average occupied blocks per requestor 463system.cpu.l2cache.occ_blocks::cpu.inst 2279.819240 # Average occupied blocks per requestor 464system.cpu.l2cache.occ_blocks::cpu.data 297.804001 # Average occupied blocks per requestor 465system.cpu.l2cache.occ_percent::writebacks 0.000052 # Average percentage of cache occupancy 466system.cpu.l2cache.occ_percent::cpu.inst 0.069575 # Average percentage of cache occupancy 467system.cpu.l2cache.occ_percent::cpu.data 0.009088 # Average percentage of cache occupancy 468system.cpu.l2cache.occ_percent::total 0.078715 # Average percentage of cache occupancy 469system.cpu.l2cache.ReadReq_hits::cpu.inst 4140 # number of ReadReq hits 470system.cpu.l2cache.ReadReq_hits::cpu.data 31 # number of ReadReq hits 471system.cpu.l2cache.ReadReq_hits::total 4171 # number of ReadReq hits 472system.cpu.l2cache.Writeback_hits::writebacks 13 # number of Writeback hits 473system.cpu.l2cache.Writeback_hits::total 13 # number of Writeback hits 474system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits 475system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits 476system.cpu.l2cache.demand_hits::cpu.inst 4140 # number of demand (read+write) hits 477system.cpu.l2cache.demand_hits::cpu.data 39 # number of demand (read+write) hits 478system.cpu.l2cache.demand_hits::total 4179 # number of demand (read+write) hits 479system.cpu.l2cache.overall_hits::cpu.inst 4140 # number of overall hits 480system.cpu.l2cache.overall_hits::cpu.data 39 # number of overall hits 481system.cpu.l2cache.overall_hits::total 4179 # number of overall hits 482system.cpu.l2cache.ReadReq_misses::cpu.inst 3431 # number of ReadReq misses 483system.cpu.l2cache.ReadReq_misses::cpu.data 409 # number of ReadReq misses 484system.cpu.l2cache.ReadReq_misses::total 3840 # number of ReadReq misses 485system.cpu.l2cache.UpgradeReq_misses::cpu.data 155 # number of UpgradeReq misses 486system.cpu.l2cache.UpgradeReq_misses::total 155 # number of UpgradeReq misses 487system.cpu.l2cache.ReadExReq_misses::cpu.data 1551 # number of ReadExReq misses 488system.cpu.l2cache.ReadExReq_misses::total 1551 # number of ReadExReq misses 489system.cpu.l2cache.demand_misses::cpu.inst 3431 # number of demand (read+write) misses 490system.cpu.l2cache.demand_misses::cpu.data 1960 # number of demand (read+write) misses 491system.cpu.l2cache.demand_misses::total 5391 # number of demand (read+write) misses 492system.cpu.l2cache.overall_misses::cpu.inst 3431 # number of overall misses 493system.cpu.l2cache.overall_misses::cpu.data 1960 # number of overall misses 494system.cpu.l2cache.overall_misses::total 5391 # number of overall misses 495system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 117518500 # number of ReadReq miss cycles 496system.cpu.l2cache.ReadReq_miss_latency::cpu.data 13976500 # number of ReadReq miss cycles 497system.cpu.l2cache.ReadReq_miss_latency::total 131495000 # number of ReadReq miss cycles 498system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 52996000 # number of ReadExReq miss cycles 499system.cpu.l2cache.ReadExReq_miss_latency::total 52996000 # number of ReadExReq miss cycles 500system.cpu.l2cache.demand_miss_latency::cpu.inst 117518500 # number of demand (read+write) miss cycles 501system.cpu.l2cache.demand_miss_latency::cpu.data 66972500 # number of demand (read+write) miss cycles 502system.cpu.l2cache.demand_miss_latency::total 184491000 # number of demand (read+write) miss cycles 503system.cpu.l2cache.overall_miss_latency::cpu.inst 117518500 # number of overall miss cycles 504system.cpu.l2cache.overall_miss_latency::cpu.data 66972500 # number of overall miss cycles 505system.cpu.l2cache.overall_miss_latency::total 184491000 # number of overall miss cycles 506system.cpu.l2cache.ReadReq_accesses::cpu.inst 7571 # number of ReadReq accesses(hits+misses) 507system.cpu.l2cache.ReadReq_accesses::cpu.data 440 # number of ReadReq accesses(hits+misses) 508system.cpu.l2cache.ReadReq_accesses::total 8011 # number of ReadReq accesses(hits+misses) 509system.cpu.l2cache.Writeback_accesses::writebacks 13 # number of Writeback accesses(hits+misses) 510system.cpu.l2cache.Writeback_accesses::total 13 # number of Writeback accesses(hits+misses) 511system.cpu.l2cache.UpgradeReq_accesses::cpu.data 155 # number of UpgradeReq accesses(hits+misses) 512system.cpu.l2cache.UpgradeReq_accesses::total 155 # number of UpgradeReq accesses(hits+misses) 513system.cpu.l2cache.ReadExReq_accesses::cpu.data 1559 # number of ReadExReq accesses(hits+misses) 514system.cpu.l2cache.ReadExReq_accesses::total 1559 # number of ReadExReq accesses(hits+misses) 515system.cpu.l2cache.demand_accesses::cpu.inst 7571 # number of demand (read+write) accesses 516system.cpu.l2cache.demand_accesses::cpu.data 1999 # number of demand (read+write) accesses 517system.cpu.l2cache.demand_accesses::total 9570 # number of demand (read+write) accesses 518system.cpu.l2cache.overall_accesses::cpu.inst 7571 # number of overall (read+write) accesses 519system.cpu.l2cache.overall_accesses::cpu.data 1999 # number of overall (read+write) accesses 520system.cpu.l2cache.overall_accesses::total 9570 # number of overall (read+write) accesses 521system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.453177 # miss rate for ReadReq accesses 522system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.929545 # miss rate for ReadReq accesses 523system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 524system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994869 # miss rate for ReadExReq accesses 525system.cpu.l2cache.demand_miss_rate::cpu.inst 0.453177 # miss rate for demand accesses 526system.cpu.l2cache.demand_miss_rate::cpu.data 0.980490 # miss rate for demand accesses 527system.cpu.l2cache.overall_miss_rate::cpu.inst 0.453177 # miss rate for overall accesses 528system.cpu.l2cache.overall_miss_rate::cpu.data 0.980490 # miss rate for overall accesses 529system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34251.967356 # average ReadReq miss latency 530system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34172.371638 # average ReadReq miss latency 531system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34168.923275 # average ReadExReq miss latency 532system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34251.967356 # average overall miss latency 533system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34169.642857 # average overall miss latency 534system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34251.967356 # average overall miss latency 535system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34169.642857 # average overall miss latency 536system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 537system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 538system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 539system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 540system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 541system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 542system.cpu.l2cache.fast_writes 0 # number of fast writes performed 543system.cpu.l2cache.cache_copies 0 # number of cache copies performed 544system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3431 # number of ReadReq MSHR misses 545system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 409 # number of ReadReq MSHR misses 546system.cpu.l2cache.ReadReq_mshr_misses::total 3840 # number of ReadReq MSHR misses 547system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 155 # number of UpgradeReq MSHR misses 548system.cpu.l2cache.UpgradeReq_mshr_misses::total 155 # number of UpgradeReq MSHR misses 549system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1551 # number of ReadExReq MSHR misses 550system.cpu.l2cache.ReadExReq_mshr_misses::total 1551 # number of ReadExReq MSHR misses 551system.cpu.l2cache.demand_mshr_misses::cpu.inst 3431 # number of demand (read+write) MSHR misses 552system.cpu.l2cache.demand_mshr_misses::cpu.data 1960 # number of demand (read+write) MSHR misses 553system.cpu.l2cache.demand_mshr_misses::total 5391 # number of demand (read+write) MSHR misses 554system.cpu.l2cache.overall_mshr_misses::cpu.inst 3431 # number of overall MSHR misses 555system.cpu.l2cache.overall_mshr_misses::cpu.data 1960 # number of overall MSHR misses 556system.cpu.l2cache.overall_mshr_misses::total 5391 # number of overall MSHR misses 557system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 106440500 # number of ReadReq MSHR miss cycles 558system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12676500 # number of ReadReq MSHR miss cycles 559system.cpu.l2cache.ReadReq_mshr_miss_latency::total 119117000 # number of ReadReq MSHR miss cycles 560system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 4805000 # number of UpgradeReq MSHR miss cycles 561system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 4805000 # number of UpgradeReq MSHR miss cycles 562system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48110500 # number of ReadExReq MSHR miss cycles 563system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48110500 # number of ReadExReq MSHR miss cycles 564system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 106440500 # number of demand (read+write) MSHR miss cycles 565system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 60787000 # number of demand (read+write) MSHR miss cycles 566system.cpu.l2cache.demand_mshr_miss_latency::total 167227500 # number of demand (read+write) MSHR miss cycles 567system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 106440500 # number of overall MSHR miss cycles 568system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 60787000 # number of overall MSHR miss cycles 569system.cpu.l2cache.overall_mshr_miss_latency::total 167227500 # number of overall MSHR miss cycles 570system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.453177 # mshr miss rate for ReadReq accesses 571system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.929545 # mshr miss rate for ReadReq accesses 572system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 573system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994869 # mshr miss rate for ReadExReq accesses 574system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.453177 # mshr miss rate for demand accesses 575system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980490 # mshr miss rate for demand accesses 576system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.453177 # mshr miss rate for overall accesses 577system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980490 # mshr miss rate for overall accesses 578system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31023.171087 # average ReadReq mshr miss latency 579system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30993.887531 # average ReadReq mshr miss latency 580system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency 581system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31019.019987 # average ReadExReq mshr miss latency 582system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31023.171087 # average overall mshr miss latency 583system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31013.775510 # average overall mshr miss latency 584system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31023.171087 # average overall mshr miss latency 585system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31013.775510 # average overall mshr miss latency 586system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 587 588---------- End Simulation Statistics ---------- 589