linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.096690                       # Number of seconds simulated
sim_ticks                                 96689893000                       # Number of ticks simulated
final_tick                                96689893000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 118200                       # Simulator instruction rate (inst/s)
host_tick_rate                               51629155                       # Simulator tick rate (ticks/s)
host_mem_usage                                 224032                       # Number of bytes of host memory used
host_seconds                                  1872.78                       # Real time elapsed on the host
sim_insts                                   221363017                       # Number of instructions simulated
system.physmem.bytes_read                      340224                       # Number of bytes read from this memory
system.physmem.bytes_inst_read                 215424                       # Number of instructions bytes read from this memory
system.physmem.bytes_written                        0                       # Number of bytes written to this memory
system.physmem.num_reads                         5316                       # Number of read requests responded to by this memory
system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
system.physmem.num_other                            0                       # Number of other requests responded to by this memory
system.physmem.bw_read                        3518713                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read                   2227989                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total                       3518713                       # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls                  400                       # Number of system calls
system.cpu.numCycles                        193379787                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.BPredUnit.lookups                 25818202                       # Number of BP lookups
system.cpu.BPredUnit.condPredicted           25818202                       # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect            2898724                       # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups              23602930                       # Number of BTB lookups
system.cpu.BPredUnit.BTBHits                 20841363                       # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles           30995459                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      261573615                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    25818202                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           20841363                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                      70808397                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                26924712                       # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles               67767699                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                  120                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles          1017                       # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines                  28859729                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                549788                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples          193293197                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.259018                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.335260                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                124336745     64.33%     64.33% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  4112034      2.13%     66.45% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  3238737      1.68%     68.13% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                  4462671      2.31%     70.44% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  4295145      2.22%     72.66% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  4476640      2.32%     74.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                  5418723      2.80%     77.78% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  3020771      1.56%     79.34% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 39931731     20.66%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            193293197                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.133510                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.352642                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 44764810                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              57827624                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  57161965                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               9818293                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles               23720505                       # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts              424367292                       # Number of instructions handled by decode
system.cpu.rename.SquashCycles               23720505                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 53388300                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                14632169                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles          21921                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  57615812                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              43914490                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              411765049                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                    18                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents               19034939                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents              22478875                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands           438156432                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            1066580371                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       1055689317                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups          10891054                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             234363409                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                203793023                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts               1794                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts           1788                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  94980657                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            104262380                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            37289638                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads          67232013                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores         21668119                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  396788007                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded                2705                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 287703359                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            254770                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined       174855842                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined    350938331                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved           1459                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     193293197                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.488430                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.480803                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            60724695     31.42%     31.42% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            54019027     27.95%     59.36% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2            35712551     18.48%     77.84% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3            21012235     10.87%     88.71% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            13686479      7.08%     95.79% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             5222239      2.70%     98.49% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6             2184583      1.13%     99.62% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7              593188      0.31%     99.93% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              138200      0.07%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       193293197                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                  110269      4.01%      4.01% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%      4.01% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      4.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      4.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      4.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      4.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      4.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      4.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      4.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      4.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      4.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      4.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      4.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      4.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      4.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      4.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      4.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      4.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      4.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      4.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      4.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      4.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      4.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      4.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      4.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      4.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      4.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      4.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      4.01% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                2317531     84.31%     88.32% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                321034     11.68%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass           1208234      0.42%      0.42% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             187072997     65.02%     65.44% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                    0      0.00%     65.44% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     65.44% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd             1650386      0.57%     66.02% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.02% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     66.02% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     66.02% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     66.02% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     66.02% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     66.02% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     66.02% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     66.02% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     66.02% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     66.02% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     66.02% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     66.02% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     66.02% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     66.02% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     66.02% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     66.02% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     66.02% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     66.02% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     66.02% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     66.02% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     66.02% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.02% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.02% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.02% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.02% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             73223880     25.45%     91.47% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            24547862      8.53%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              287703359                       # Type of FU issued
system.cpu.iq.rate                           1.487763                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     2748834                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.009554                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          766190945                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         566572341                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    278374724                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads             5512574                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes            5407408                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses      2648186                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              286471551                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                 2772408                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads         18351013                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads     47612790                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        32223                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation       339608                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores     16773922                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads        46155                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles               23720505                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                  359624                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                213865                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           396790712                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            135718                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             104262380                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             37289638                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts               1786                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                 119790                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                 15845                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents         339608                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect        2505263                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       598160                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              3103423                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             283855997                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              71689961                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           3847362                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                             0                       # number of nop insts executed
system.cpu.iew.exec_refs                     95739480                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 15662592                       # Number of branches executed
system.cpu.iew.exec_stores                   24049519                       # Number of stores executed
system.cpu.iew.exec_rate                     1.467868                       # Inst execution rate
system.cpu.iew.wb_sent                      282319460                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     281022910                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 227917239                       # num instructions producing a value
system.cpu.iew.wb_consumers                 378870882                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.453218                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.601570                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts      221363017                       # The number of committed instructions
system.cpu.commit.commitSquashedInsts       175435625                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls            1246                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts           2898838                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    169572692                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.305417                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.741291                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     63662174     37.54%     37.54% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     62350604     36.77%     74.31% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     15592003      9.19%     83.51% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     11999288      7.08%     90.58% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      5440588      3.21%     93.79% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      2982193      1.76%     95.55% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      2011991      1.19%     96.74% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7      1185528      0.70%     97.44% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      4348323      2.56%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    169572692                       # Number of insts commited each cycle
system.cpu.commit.count                     221363017                       # Number of instructions committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       77165306                       # Number of memory references committed
system.cpu.commit.loads                      56649590                       # Number of loads committed
system.cpu.commit.membars                           0                       # Number of memory barriers committed
system.cpu.commit.branches                   12326943                       # Number of branches committed
system.cpu.commit.fp_insts                    2162459                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 220339606                       # Number of committed integer instructions.
system.cpu.commit.function_calls                    0                       # Number of function calls committed.
system.cpu.commit.bw_lim_events               4348323                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                    562023011                       # The number of ROB reads
system.cpu.rob.rob_writes                   817360743                       # The number of ROB writes
system.cpu.timesIdled                            1880                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                           86590                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                   221363017                       # Number of Instructions Simulated
system.cpu.committedInsts_total             221363017                       # Number of Instructions Simulated
system.cpu.cpi                               0.873587                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.873587                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.144706                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.144706                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                530675330                       # number of integer regfile reads
system.cpu.int_regfile_writes               288962100                       # number of integer regfile writes
system.cpu.fp_regfile_reads                   3614411                       # number of floating regfile reads
system.cpu.fp_regfile_writes                  2302807                       # number of floating regfile writes
system.cpu.misc_regfile_reads               149913222                       # number of misc regfile reads
system.cpu.misc_regfile_writes                    844                       # number of misc regfile writes
system.cpu.icache.replacements                   4227                       # number of replacements
system.cpu.icache.tagsinuse               1595.324923                       # Cycle average of tags in use
system.cpu.icache.total_refs                 28852140                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                   6194                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                4658.078786                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0           1595.324923                       # Average occupied blocks per context
system.cpu.icache.occ_percent::0             0.778967                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits               28852140                       # number of ReadReq hits
system.cpu.icache.demand_hits                28852140                       # number of demand (read+write) hits
system.cpu.icache.overall_hits               28852140                       # number of overall hits
system.cpu.icache.ReadReq_misses                 7589                       # number of ReadReq misses
system.cpu.icache.demand_misses                  7589                       # number of demand (read+write) misses
system.cpu.icache.overall_misses                 7589                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency      174464500                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency       174464500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency      174464500                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses           28859729                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses            28859729                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses           28859729                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate          0.000263                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate           0.000263                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate          0.000263                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 22989.129003                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 22989.129003                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 22989.129003                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.writebacks                        0                       # number of writebacks
system.cpu.icache.ReadReq_mshr_hits              1125                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits               1125                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits              1125                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses            6464                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses             6464                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses            6464                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency    125677000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency    125677000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency    125677000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate     0.000224                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate      0.000224                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate     0.000224                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 19442.605198                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 19442.605198                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 19442.605198                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                     59                       # number of replacements
system.cpu.dcache.tagsinuse               1416.877097                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 73598603                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                   1986                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs               37058.712487                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0           1416.877097                       # Average occupied blocks per context
system.cpu.dcache.occ_percent::0             0.345917                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits               53090649                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits              20507453                       # number of WriteReq hits
system.cpu.dcache.demand_hits                73598102                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits               73598102                       # number of overall hits
system.cpu.dcache.ReadReq_misses                  848                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses                8277                       # number of WriteReq misses
system.cpu.dcache.demand_misses                  9125                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses                 9125                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency       26447500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency     228348000                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency       254795500                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency      254795500                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses           53091497                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses          20515730                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses            73607227                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses           73607227                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate          0.000016                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate         0.000403                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate           0.000124                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate          0.000124                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 31188.089623                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 27588.256615                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency 27922.794521                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 27922.794521                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks                       14                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits               424                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits             6443                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits               6867                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits              6867                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses             424                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses           1834                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses             2258                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses            2258                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency     13981500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency     64146500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency     78128000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency     78128000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate     0.000008                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate     0.000089                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate      0.000031                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate     0.000031                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32975.235849                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34976.281352                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 34600.531444                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 34600.531444                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements                     0                       # number of replacements
system.cpu.l2cache.tagsinuse              2499.166941                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                    2858                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs                  3763                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                  0.759500                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0          2497.181729                       # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1             1.985212                       # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0            0.076208                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1            0.000061                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits                  2857                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits                  14                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits                   8                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits                   2865                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits                  2865                       # number of overall hits
system.cpu.l2cache.ReadReq_misses                3759                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses              270                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses              1557                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses                 5316                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses                5316                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency     128731000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency     53240500                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency      181971500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency     181971500                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses              6616                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses              14                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses            270                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses            1565                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses               8181                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses              8181                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate         0.568168                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate       0.994888                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate          0.649798                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate         0.649798                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34246.076084                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34194.283879                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34230.906697                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34230.906697                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks                       0                       # number of writebacks
system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses           3759                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses          270                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses         1557                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses            5316                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses           5316                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency    116600500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency      8370000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency     48374500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency    164975000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency    164975000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate     0.568168                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.994888                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate     0.649798                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate     0.649798                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31019.021016                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        31000                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31069.043031                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31033.671934                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31033.671934                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------