stats.txt revision 9620:89aa34e10625
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.074157 # Number of seconds simulated 4sim_ticks 74157495500 # Number of ticks simulated 5final_tick 74157495500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 51189 # Simulator instruction rate (inst/s) 8host_op_rate 56047 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 22031117 # Simulator tick rate (ticks/s) 10host_mem_usage 291420 # Number of bytes of host memory used 11host_seconds 3366.03 # Real time elapsed on the host 12sim_insts 172303021 # Number of instructions simulated 13sim_ops 188656503 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 131776 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 111936 # Number of bytes read from this memory 16system.physmem.bytes_read::total 243712 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 131776 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 131776 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 2059 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 1749 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 3808 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 1776975 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 1509436 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 3286411 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 1776975 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 1776975 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 1776975 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 1509436 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 3286411 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.readReqs 3809 # Total number of read requests seen 31system.physmem.writeReqs 0 # Total number of write requests seen 32system.physmem.cpureqs 3811 # Reqs generatd by CPU via cache - shady 33system.physmem.bytesRead 243712 # Total number of bytes read from memory 34system.physmem.bytesWritten 0 # Total number of bytes written to memory 35system.physmem.bytesConsumedRd 243712 # bytesRead derated as per pkt->getSize() 36system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 37system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q 38system.physmem.neitherReadNorWrite 2 # Reqs where no action is needed 39system.physmem.perBankRdReqs::0 323 # Track reads on a per bank basis 40system.physmem.perBankRdReqs::1 239 # Track reads on a per bank basis 41system.physmem.perBankRdReqs::2 208 # Track reads on a per bank basis 42system.physmem.perBankRdReqs::3 272 # Track reads on a per bank basis 43system.physmem.perBankRdReqs::4 244 # Track reads on a per bank basis 44system.physmem.perBankRdReqs::5 197 # Track reads on a per bank basis 45system.physmem.perBankRdReqs::6 247 # Track reads on a per bank basis 46system.physmem.perBankRdReqs::7 252 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::8 233 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::9 244 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::10 235 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::11 193 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::12 201 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::13 199 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::14 248 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::15 274 # Track reads on a per bank basis 55system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 56system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 57system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 58system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 59system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 60system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 61system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 62system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 73system.physmem.totGap 74157477000 # Total gap between requests 74system.physmem.readPktSize::0 0 # Categorize read packet sizes 75system.physmem.readPktSize::1 0 # Categorize read packet sizes 76system.physmem.readPktSize::2 0 # Categorize read packet sizes 77system.physmem.readPktSize::3 0 # Categorize read packet sizes 78system.physmem.readPktSize::4 0 # Categorize read packet sizes 79system.physmem.readPktSize::5 0 # Categorize read packet sizes 80system.physmem.readPktSize::6 3809 # Categorize read packet sizes 81system.physmem.writePktSize::0 0 # Categorize write packet sizes 82system.physmem.writePktSize::1 0 # Categorize write packet sizes 83system.physmem.writePktSize::2 0 # Categorize write packet sizes 84system.physmem.writePktSize::3 0 # Categorize write packet sizes 85system.physmem.writePktSize::4 0 # Categorize write packet sizes 86system.physmem.writePktSize::5 0 # Categorize write packet sizes 87system.physmem.writePktSize::6 0 # Categorize write packet sizes 88system.physmem.rdQLenPdf::0 2784 # What read queue length does an incoming req see 89system.physmem.rdQLenPdf::1 808 # What read queue length does an incoming req see 90system.physmem.rdQLenPdf::2 160 # What read queue length does an incoming req see 91system.physmem.rdQLenPdf::3 48 # What read queue length does an incoming req see 92system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see 93system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 120system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 121system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 122system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 123system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 124system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 125system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 152system.physmem.totQLat 17510750 # Total cycles spent in queuing delays 153system.physmem.totMemAccLat 103435750 # Sum of mem lat for all requests 154system.physmem.totBusLat 19045000 # Total cycles spent in databus access 155system.physmem.totBankLat 66880000 # Total cycles spent in bank access 156system.physmem.avgQLat 4597.20 # Average queueing delay per request 157system.physmem.avgBankLat 17558.41 # Average bank access latency per request 158system.physmem.avgBusLat 5000.00 # Average bus latency per request 159system.physmem.avgMemAccLat 27155.62 # Average memory access latency 160system.physmem.avgRdBW 3.29 # Average achieved read bandwidth in MB/s 161system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s 162system.physmem.avgConsumedRdBW 3.29 # Average consumed read bandwidth in MB/s 163system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 164system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 165system.physmem.busUtil 0.03 # Data bus utilization in percentage 166system.physmem.avgRdQLen 0.00 # Average read queue length over time 167system.physmem.avgWrQLen 0.00 # Average write queue length over time 168system.physmem.readRowHits 3021 # Number of row buffer hits during reads 169system.physmem.writeRowHits 0 # Number of row buffer hits during writes 170system.physmem.readRowHitRate 79.31 # Row buffer hit rate for reads 171system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 172system.physmem.avgGap 19469014.70 # Average gap between requests 173system.cpu.branchPred.lookups 94703867 # Number of BP lookups 174system.cpu.branchPred.condPredicted 74722053 # Number of conditional branches predicted 175system.cpu.branchPred.condIncorrect 6280216 # Number of conditional branches incorrect 176system.cpu.branchPred.BTBLookups 44664544 # Number of BTB lookups 177system.cpu.branchPred.BTBHits 43035053 # Number of BTB hits 178system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 179system.cpu.branchPred.BTBHitPct 96.351712 # BTB Hit Percentage 180system.cpu.branchPred.usedRAS 4359745 # Number of times the RAS was used to get a target. 181system.cpu.branchPred.RASInCorrect 88611 # Number of incorrect RAS predictions. 182system.cpu.dtb.inst_hits 0 # ITB inst hits 183system.cpu.dtb.inst_misses 0 # ITB inst misses 184system.cpu.dtb.read_hits 0 # DTB read hits 185system.cpu.dtb.read_misses 0 # DTB read misses 186system.cpu.dtb.write_hits 0 # DTB write hits 187system.cpu.dtb.write_misses 0 # DTB write misses 188system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 189system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 190system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 191system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 192system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 193system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 194system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 195system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 196system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 197system.cpu.dtb.read_accesses 0 # DTB read accesses 198system.cpu.dtb.write_accesses 0 # DTB write accesses 199system.cpu.dtb.inst_accesses 0 # ITB inst accesses 200system.cpu.dtb.hits 0 # DTB hits 201system.cpu.dtb.misses 0 # DTB misses 202system.cpu.dtb.accesses 0 # DTB accesses 203system.cpu.itb.inst_hits 0 # ITB inst hits 204system.cpu.itb.inst_misses 0 # ITB inst misses 205system.cpu.itb.read_hits 0 # DTB read hits 206system.cpu.itb.read_misses 0 # DTB read misses 207system.cpu.itb.write_hits 0 # DTB write hits 208system.cpu.itb.write_misses 0 # DTB write misses 209system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 210system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 211system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 212system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 213system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 214system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 215system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 216system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 217system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 218system.cpu.itb.read_accesses 0 # DTB read accesses 219system.cpu.itb.write_accesses 0 # DTB write accesses 220system.cpu.itb.inst_accesses 0 # ITB inst accesses 221system.cpu.itb.hits 0 # DTB hits 222system.cpu.itb.misses 0 # DTB misses 223system.cpu.itb.accesses 0 # DTB accesses 224system.cpu.workload.num_syscalls 400 # Number of system calls 225system.cpu.numCycles 148314992 # number of cpu cycles simulated 226system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 227system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 228system.cpu.fetch.icacheStallCycles 39662414 # Number of cycles fetch is stalled on an Icache miss 229system.cpu.fetch.Insts 380030694 # Number of instructions fetch has processed 230system.cpu.fetch.Branches 94703867 # Number of branches that fetch encountered 231system.cpu.fetch.predictedBranches 47394798 # Number of branches that fetch has predicted taken 232system.cpu.fetch.Cycles 80357293 # Number of cycles fetch has run and was not squashing or blocked 233system.cpu.fetch.SquashCycles 27270600 # Number of cycles fetch has spent squashing 234system.cpu.fetch.BlockedCycles 7200009 # Number of cycles fetch has spent blocked 235system.cpu.fetch.MiscStallCycles 7 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 236system.cpu.fetch.PendingTrapStallCycles 5243 # Number of stall cycles due to pending traps 237system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions 238system.cpu.fetch.IcacheWaitRetryStallCycles 23 # Number of stall cycles due to full MSHR 239system.cpu.fetch.CacheLines 36857358 # Number of cache lines fetched 240system.cpu.fetch.IcacheSquashes 1832427 # Number of outstanding Icache misses that were squashed 241system.cpu.fetch.rateDist::samples 148199476 # Number of instructions fetched each cycle (Total) 242system.cpu.fetch.rateDist::mean 2.801422 # Number of instructions fetched each cycle (Total) 243system.cpu.fetch.rateDist::stdev 3.152732 # Number of instructions fetched each cycle (Total) 244system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 245system.cpu.fetch.rateDist::0 68011684 45.89% 45.89% # Number of instructions fetched each cycle (Total) 246system.cpu.fetch.rateDist::1 5276203 3.56% 49.45% # Number of instructions fetched each cycle (Total) 247system.cpu.fetch.rateDist::2 10540688 7.11% 56.56% # Number of instructions fetched each cycle (Total) 248system.cpu.fetch.rateDist::3 10280783 6.94% 63.50% # Number of instructions fetched each cycle (Total) 249system.cpu.fetch.rateDist::4 8654302 5.84% 69.34% # Number of instructions fetched each cycle (Total) 250system.cpu.fetch.rateDist::5 6554085 4.42% 73.76% # Number of instructions fetched each cycle (Total) 251system.cpu.fetch.rateDist::6 6244651 4.21% 77.98% # Number of instructions fetched each cycle (Total) 252system.cpu.fetch.rateDist::7 7982798 5.39% 83.36% # Number of instructions fetched each cycle (Total) 253system.cpu.fetch.rateDist::8 24654282 16.64% 100.00% # Number of instructions fetched each cycle (Total) 254system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 255system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 256system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 257system.cpu.fetch.rateDist::total 148199476 # Number of instructions fetched each cycle (Total) 258system.cpu.fetch.branchRate 0.638532 # Number of branch fetches per cycle 259system.cpu.fetch.rate 2.562322 # Number of inst fetches per cycle 260system.cpu.decode.IdleCycles 45512613 # Number of cycles decode is idle 261system.cpu.decode.BlockedCycles 5867522 # Number of cycles decode is blocked 262system.cpu.decode.RunCycles 74797201 # Number of cycles decode is running 263system.cpu.decode.UnblockCycles 1201275 # Number of cycles decode is unblocking 264system.cpu.decode.SquashCycles 20820865 # Number of cycles decode is squashing 265system.cpu.decode.BranchResolved 14305085 # Number of times decode resolved a branch 266system.cpu.decode.BranchMispred 164111 # Number of times decode detected a branch misprediction 267system.cpu.decode.DecodedInsts 392663870 # Number of instructions handled by decode 268system.cpu.decode.SquashedInsts 738369 # Number of squashed instructions handled by decode 269system.cpu.rename.SquashCycles 20820865 # Number of cycles rename is squashing 270system.cpu.rename.IdleCycles 50901215 # Number of cycles rename is idle 271system.cpu.rename.BlockCycles 722150 # Number of cycles rename is blocking 272system.cpu.rename.serializeStallCycles 593982 # count of cycles rename stalled for serializing inst 273system.cpu.rename.RunCycles 70547488 # Number of cycles rename is running 274system.cpu.rename.UnblockCycles 4613776 # Number of cycles rename is unblocking 275system.cpu.rename.RenamedInsts 371203156 # Number of instructions processed by rename 276system.cpu.rename.ROBFullEvents 33 # Number of times rename has blocked due to ROB full 277system.cpu.rename.IQFullEvents 343152 # Number of times rename has blocked due to IQ full 278system.cpu.rename.LSQFullEvents 3655877 # Number of times rename has blocked due to LSQ full 279system.cpu.rename.FullRegisterEvents 29 # Number of times there has been no free registers 280system.cpu.rename.RenamedOperands 631482556 # Number of destination operands rename has renamed 281system.cpu.rename.RenameLookups 1581281661 # Number of register rename lookups that rename has made 282system.cpu.rename.int_rename_lookups 1563963855 # Number of integer rename lookups 283system.cpu.rename.fp_rename_lookups 17317806 # Number of floating rename lookups 284system.cpu.rename.CommittedMaps 298044139 # Number of HB maps that are committed 285system.cpu.rename.UndoneMaps 333438417 # Number of HB maps that are undone due to squashing 286system.cpu.rename.serializingInsts 25133 # count of serializing insts renamed 287system.cpu.rename.tempSerializingInsts 25129 # count of temporary serializing insts renamed 288system.cpu.rename.skidInsts 13026907 # count of insts added to the skid buffer 289system.cpu.memDep0.insertedLoads 42996111 # Number of loads inserted to the mem dependence unit. 290system.cpu.memDep0.insertedStores 16422667 # Number of stores inserted to the mem dependence unit. 291system.cpu.memDep0.conflictingLoads 5676383 # Number of conflicting loads. 292system.cpu.memDep0.conflictingStores 3667621 # Number of conflicting stores. 293system.cpu.iq.iqInstsAdded 329112708 # Number of instructions added to the IQ (excludes non-spec) 294system.cpu.iq.iqNonSpecInstsAdded 47143 # Number of non-speculative instructions added to the IQ 295system.cpu.iq.iqInstsIssued 249432965 # Number of instructions issued 296system.cpu.iq.iqSquashedInstsIssued 790911 # Number of squashed instructions issued 297system.cpu.iq.iqSquashedInstsExamined 139431014 # Number of squashed instructions iterated over during squash; mainly for profiling 298system.cpu.iq.iqSquashedOperandsExamined 361763997 # Number of squashed operands that are examined and possibly removed from graph 299system.cpu.iq.iqSquashedNonSpecRemoved 1927 # Number of squashed non-spec instructions that were removed 300system.cpu.iq.issued_per_cycle::samples 148199476 # Number of insts issued each cycle 301system.cpu.iq.issued_per_cycle::mean 1.683089 # Number of insts issued each cycle 302system.cpu.iq.issued_per_cycle::stdev 1.761808 # Number of insts issued each cycle 303system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 304system.cpu.iq.issued_per_cycle::0 56042939 37.82% 37.82% # Number of insts issued each cycle 305system.cpu.iq.issued_per_cycle::1 22629719 15.27% 53.09% # Number of insts issued each cycle 306system.cpu.iq.issued_per_cycle::2 24820832 16.75% 69.83% # Number of insts issued each cycle 307system.cpu.iq.issued_per_cycle::3 20320046 13.71% 83.55% # Number of insts issued each cycle 308system.cpu.iq.issued_per_cycle::4 12535804 8.46% 92.00% # Number of insts issued each cycle 309system.cpu.iq.issued_per_cycle::5 6521757 4.40% 96.40% # Number of insts issued each cycle 310system.cpu.iq.issued_per_cycle::6 4030887 2.72% 99.12% # Number of insts issued each cycle 311system.cpu.iq.issued_per_cycle::7 1115815 0.75% 99.88% # Number of insts issued each cycle 312system.cpu.iq.issued_per_cycle::8 181677 0.12% 100.00% # Number of insts issued each cycle 313system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 314system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 315system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 316system.cpu.iq.issued_per_cycle::total 148199476 # Number of insts issued each cycle 317system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 318system.cpu.iq.fu_full::IntAlu 963057 38.38% 38.38% # attempts to use FU when none available 319system.cpu.iq.fu_full::IntMult 5596 0.22% 38.60% # attempts to use FU when none available 320system.cpu.iq.fu_full::IntDiv 0 0.00% 38.60% # attempts to use FU when none available 321system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.60% # attempts to use FU when none available 322system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.60% # attempts to use FU when none available 323system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.60% # attempts to use FU when none available 324system.cpu.iq.fu_full::FloatMult 0 0.00% 38.60% # attempts to use FU when none available 325system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.60% # attempts to use FU when none available 326system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.60% # attempts to use FU when none available 327system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.60% # attempts to use FU when none available 328system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.60% # attempts to use FU when none available 329system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.60% # attempts to use FU when none available 330system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.60% # attempts to use FU when none available 331system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.60% # attempts to use FU when none available 332system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.60% # attempts to use FU when none available 333system.cpu.iq.fu_full::SimdMult 0 0.00% 38.60% # attempts to use FU when none available 334system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.60% # attempts to use FU when none available 335system.cpu.iq.fu_full::SimdShift 0 0.00% 38.60% # attempts to use FU when none available 336system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.60% # attempts to use FU when none available 337system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.60% # attempts to use FU when none available 338system.cpu.iq.fu_full::SimdFloatAdd 101 0.00% 38.60% # attempts to use FU when none available 339system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.60% # attempts to use FU when none available 340system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.60% # attempts to use FU when none available 341system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.60% # attempts to use FU when none available 342system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.60% # attempts to use FU when none available 343system.cpu.iq.fu_full::SimdFloatMisc 51 0.00% 38.61% # attempts to use FU when none available 344system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.61% # attempts to use FU when none available 345system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.61% # attempts to use FU when none available 346system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.61% # attempts to use FU when none available 347system.cpu.iq.fu_full::MemRead 1167699 46.53% 85.14% # attempts to use FU when none available 348system.cpu.iq.fu_full::MemWrite 372909 14.86% 100.00% # attempts to use FU when none available 349system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 350system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 351system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 352system.cpu.iq.FU_type_0::IntAlu 194880762 78.13% 78.13% # Type of FU issued 353system.cpu.iq.FU_type_0::IntMult 980286 0.39% 78.52% # Type of FU issued 354system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.52% # Type of FU issued 355system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.52% # Type of FU issued 356system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.52% # Type of FU issued 357system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.52% # Type of FU issued 358system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.52% # Type of FU issued 359system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.52% # Type of FU issued 360system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.52% # Type of FU issued 361system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.52% # Type of FU issued 362system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.52% # Type of FU issued 363system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.52% # Type of FU issued 364system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.52% # Type of FU issued 365system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.52% # Type of FU issued 366system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.52% # Type of FU issued 367system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.52% # Type of FU issued 368system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.52% # Type of FU issued 369system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.52% # Type of FU issued 370system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.52% # Type of FU issued 371system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.52% # Type of FU issued 372system.cpu.iq.FU_type_0::SimdFloatAdd 33071 0.01% 78.54% # Type of FU issued 373system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.54% # Type of FU issued 374system.cpu.iq.FU_type_0::SimdFloatCmp 164429 0.07% 78.60% # Type of FU issued 375system.cpu.iq.FU_type_0::SimdFloatCvt 254305 0.10% 78.70% # Type of FU issued 376system.cpu.iq.FU_type_0::SimdFloatDiv 76429 0.03% 78.73% # Type of FU issued 377system.cpu.iq.FU_type_0::SimdFloatMisc 465674 0.19% 78.92% # Type of FU issued 378system.cpu.iq.FU_type_0::SimdFloatMult 206396 0.08% 79.00% # Type of FU issued 379system.cpu.iq.FU_type_0::SimdFloatMultAcc 71854 0.03% 79.03% # Type of FU issued 380system.cpu.iq.FU_type_0::SimdFloatSqrt 321 0.00% 79.03% # Type of FU issued 381system.cpu.iq.FU_type_0::MemRead 38348799 15.37% 94.41% # Type of FU issued 382system.cpu.iq.FU_type_0::MemWrite 13950639 5.59% 100.00% # Type of FU issued 383system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 384system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 385system.cpu.iq.FU_type_0::total 249432965 # Type of FU issued 386system.cpu.iq.rate 1.681779 # Inst issue rate 387system.cpu.iq.fu_busy_cnt 2509413 # FU busy when requested 388system.cpu.iq.fu_busy_rate 0.010060 # FU busy rate (busy events/executed inst) 389system.cpu.iq.int_inst_queue_reads 646629225 # Number of integer instruction queue reads 390system.cpu.iq.int_inst_queue_writes 466421271 # Number of integer instruction queue writes 391system.cpu.iq.int_inst_queue_wakeup_accesses 237868779 # Number of integer instruction queue wakeup accesses 392system.cpu.iq.fp_inst_queue_reads 3736505 # Number of floating instruction queue reads 393system.cpu.iq.fp_inst_queue_writes 2188097 # Number of floating instruction queue writes 394system.cpu.iq.fp_inst_queue_wakeup_accesses 1840763 # Number of floating instruction queue wakeup accesses 395system.cpu.iq.int_alu_accesses 250067463 # Number of integer alu accesses 396system.cpu.iq.fp_alu_accesses 1874915 # Number of floating point alu accesses 397system.cpu.iew.lsq.thread0.forwLoads 2006857 # Number of loads that had data forwarded from stores 398system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 399system.cpu.iew.lsq.thread0.squashedLoads 13146627 # Number of loads squashed 400system.cpu.iew.lsq.thread0.ignoredResponses 11917 # Number of memory responses ignored because the instruction is squashed 401system.cpu.iew.lsq.thread0.memOrderViolation 18980 # Number of memory ordering violations 402system.cpu.iew.lsq.thread0.squashedStores 3778033 # Number of stores squashed 403system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 404system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 405system.cpu.iew.lsq.thread0.rescheduledLoads 10 # Number of loads that were rescheduled 406system.cpu.iew.lsq.thread0.cacheBlocked 104 # Number of times an access to memory failed due to the cache being blocked 407system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 408system.cpu.iew.iewSquashCycles 20820865 # Number of cycles IEW is squashing 409system.cpu.iew.iewBlockCycles 17088 # Number of cycles IEW is blocking 410system.cpu.iew.iewUnblockCycles 846 # Number of cycles IEW is unblocking 411system.cpu.iew.iewDispatchedInsts 329176829 # Number of instructions dispatched to IQ 412system.cpu.iew.iewDispSquashedInsts 784787 # Number of squashed instructions skipped by dispatch 413system.cpu.iew.iewDispLoadInsts 42996111 # Number of dispatched load instructions 414system.cpu.iew.iewDispStoreInsts 16422667 # Number of dispatched store instructions 415system.cpu.iew.iewDispNonSpecInsts 24735 # Number of dispatched non-speculative instructions 416system.cpu.iew.iewIQFullEvents 188 # Number of times the IQ has become full, causing a stall 417system.cpu.iew.iewLSQFullEvents 265 # Number of times the LSQ has become full, causing a stall 418system.cpu.iew.memOrderViolationEvents 18980 # Number of memory order violations 419system.cpu.iew.predictedTakenIncorrect 3891833 # Number of branches that were predicted taken incorrectly 420system.cpu.iew.predictedNotTakenIncorrect 3757719 # Number of branches that were predicted not taken incorrectly 421system.cpu.iew.branchMispredicts 7649552 # Number of branch mispredicts detected at execute 422system.cpu.iew.iewExecutedInsts 242934999 # Number of executed instructions 423system.cpu.iew.iewExecLoadInsts 36843669 # Number of load instructions executed 424system.cpu.iew.iewExecSquashedInsts 6497966 # Number of squashed instructions skipped in execute 425system.cpu.iew.exec_swp 0 # number of swp insts executed 426system.cpu.iew.exec_nop 16978 # number of nop insts executed 427system.cpu.iew.exec_refs 50492106 # number of memory reference insts executed 428system.cpu.iew.exec_branches 53412943 # Number of branches executed 429system.cpu.iew.exec_stores 13648437 # Number of stores executed 430system.cpu.iew.exec_rate 1.637967 # Inst execution rate 431system.cpu.iew.wb_sent 240767037 # cumulative count of insts sent to commit 432system.cpu.iew.wb_count 239709542 # cumulative count of insts written-back 433system.cpu.iew.wb_producers 148457899 # num instructions producing a value 434system.cpu.iew.wb_consumers 267241195 # num instructions consuming a value 435system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 436system.cpu.iew.wb_rate 1.616219 # insts written-back per cycle 437system.cpu.iew.wb_fanout 0.555520 # average fanout of values written-back 438system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 439system.cpu.commit.commitSquashedInsts 140505920 # The number of squashed insts skipped by commit 440system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards 441system.cpu.commit.branchMispredicts 6126595 # The number of times a branch was mispredicted 442system.cpu.commit.committed_per_cycle::samples 127378611 # Number of insts commited each cycle 443system.cpu.commit.committed_per_cycle::mean 1.481182 # Number of insts commited each cycle 444system.cpu.commit.committed_per_cycle::stdev 2.186353 # Number of insts commited each cycle 445system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 446system.cpu.commit.committed_per_cycle::0 57698651 45.30% 45.30% # Number of insts commited each cycle 447system.cpu.commit.committed_per_cycle::1 31675595 24.87% 70.16% # Number of insts commited each cycle 448system.cpu.commit.committed_per_cycle::2 13783953 10.82% 80.99% # Number of insts commited each cycle 449system.cpu.commit.committed_per_cycle::3 7631475 5.99% 86.98% # Number of insts commited each cycle 450system.cpu.commit.committed_per_cycle::4 4374952 3.43% 90.41% # Number of insts commited each cycle 451system.cpu.commit.committed_per_cycle::5 1321227 1.04% 91.45% # Number of insts commited each cycle 452system.cpu.commit.committed_per_cycle::6 1703973 1.34% 92.79% # Number of insts commited each cycle 453system.cpu.commit.committed_per_cycle::7 1307096 1.03% 93.81% # Number of insts commited each cycle 454system.cpu.commit.committed_per_cycle::8 7881689 6.19% 100.00% # Number of insts commited each cycle 455system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 456system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 457system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 458system.cpu.commit.committed_per_cycle::total 127378611 # Number of insts commited each cycle 459system.cpu.commit.committedInsts 172317409 # Number of instructions committed 460system.cpu.commit.committedOps 188670891 # Number of ops (including micro ops) committed 461system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 462system.cpu.commit.refs 42494118 # Number of memory references committed 463system.cpu.commit.loads 29849484 # Number of loads committed 464system.cpu.commit.membars 22408 # Number of memory barriers committed 465system.cpu.commit.branches 40300311 # Number of branches committed 466system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. 467system.cpu.commit.int_insts 150106217 # Number of committed integer instructions. 468system.cpu.commit.function_calls 1848934 # Number of function calls committed. 469system.cpu.commit.bw_lim_events 7881689 # number cycles where commit BW limit reached 470system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 471system.cpu.rob.rob_reads 448668532 # The number of ROB reads 472system.cpu.rob.rob_writes 679284219 # The number of ROB writes 473system.cpu.timesIdled 2567 # Number of times that the entire CPU went into an idle state and unscheduled itself 474system.cpu.idleCycles 115516 # Total number of cycles that the CPU has spent unscheduled due to idling 475system.cpu.committedInsts 172303021 # Number of Instructions Simulated 476system.cpu.committedOps 188656503 # Number of Ops (including micro ops) Simulated 477system.cpu.committedInsts_total 172303021 # Number of Instructions Simulated 478system.cpu.cpi 0.860780 # CPI: Cycles Per Instruction 479system.cpu.cpi_total 0.860780 # CPI: Total CPI of All Threads 480system.cpu.ipc 1.161737 # IPC: Instructions Per Cycle 481system.cpu.ipc_total 1.161737 # IPC: Total IPC of All Threads 482system.cpu.int_regfile_reads 1079304778 # number of integer regfile reads 483system.cpu.int_regfile_writes 384845307 # number of integer regfile writes 484system.cpu.fp_regfile_reads 2912671 # number of floating regfile reads 485system.cpu.fp_regfile_writes 2496150 # number of floating regfile writes 486system.cpu.misc_regfile_reads 54492663 # number of misc regfile reads 487system.cpu.misc_regfile_writes 820036 # number of misc regfile writes 488system.cpu.icache.replacements 2376 # number of replacements 489system.cpu.icache.tagsinuse 1350.566241 # Cycle average of tags in use 490system.cpu.icache.total_refs 36852122 # Total number of references to valid blocks. 491system.cpu.icache.sampled_refs 4106 # Sample count of references to valid blocks. 492system.cpu.icache.avg_refs 8975.188018 # Average number of references to valid blocks. 493system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 494system.cpu.icache.occ_blocks::cpu.inst 1350.566241 # Average occupied blocks per requestor 495system.cpu.icache.occ_percent::cpu.inst 0.659456 # Average percentage of cache occupancy 496system.cpu.icache.occ_percent::total 0.659456 # Average percentage of cache occupancy 497system.cpu.icache.ReadReq_hits::cpu.inst 36852123 # number of ReadReq hits 498system.cpu.icache.ReadReq_hits::total 36852123 # number of ReadReq hits 499system.cpu.icache.demand_hits::cpu.inst 36852123 # number of demand (read+write) hits 500system.cpu.icache.demand_hits::total 36852123 # number of demand (read+write) hits 501system.cpu.icache.overall_hits::cpu.inst 36852123 # number of overall hits 502system.cpu.icache.overall_hits::total 36852123 # number of overall hits 503system.cpu.icache.ReadReq_misses::cpu.inst 5235 # number of ReadReq misses 504system.cpu.icache.ReadReq_misses::total 5235 # number of ReadReq misses 505system.cpu.icache.demand_misses::cpu.inst 5235 # number of demand (read+write) misses 506system.cpu.icache.demand_misses::total 5235 # number of demand (read+write) misses 507system.cpu.icache.overall_misses::cpu.inst 5235 # number of overall misses 508system.cpu.icache.overall_misses::total 5235 # number of overall misses 509system.cpu.icache.ReadReq_miss_latency::cpu.inst 167149000 # number of ReadReq miss cycles 510system.cpu.icache.ReadReq_miss_latency::total 167149000 # number of ReadReq miss cycles 511system.cpu.icache.demand_miss_latency::cpu.inst 167149000 # number of demand (read+write) miss cycles 512system.cpu.icache.demand_miss_latency::total 167149000 # number of demand (read+write) miss cycles 513system.cpu.icache.overall_miss_latency::cpu.inst 167149000 # number of overall miss cycles 514system.cpu.icache.overall_miss_latency::total 167149000 # number of overall miss cycles 515system.cpu.icache.ReadReq_accesses::cpu.inst 36857358 # number of ReadReq accesses(hits+misses) 516system.cpu.icache.ReadReq_accesses::total 36857358 # number of ReadReq accesses(hits+misses) 517system.cpu.icache.demand_accesses::cpu.inst 36857358 # number of demand (read+write) accesses 518system.cpu.icache.demand_accesses::total 36857358 # number of demand (read+write) accesses 519system.cpu.icache.overall_accesses::cpu.inst 36857358 # number of overall (read+write) accesses 520system.cpu.icache.overall_accesses::total 36857358 # number of overall (read+write) accesses 521system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000142 # miss rate for ReadReq accesses 522system.cpu.icache.ReadReq_miss_rate::total 0.000142 # miss rate for ReadReq accesses 523system.cpu.icache.demand_miss_rate::cpu.inst 0.000142 # miss rate for demand accesses 524system.cpu.icache.demand_miss_rate::total 0.000142 # miss rate for demand accesses 525system.cpu.icache.overall_miss_rate::cpu.inst 0.000142 # miss rate for overall accesses 526system.cpu.icache.overall_miss_rate::total 0.000142 # miss rate for overall accesses 527system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31929.130850 # average ReadReq miss latency 528system.cpu.icache.ReadReq_avg_miss_latency::total 31929.130850 # average ReadReq miss latency 529system.cpu.icache.demand_avg_miss_latency::cpu.inst 31929.130850 # average overall miss latency 530system.cpu.icache.demand_avg_miss_latency::total 31929.130850 # average overall miss latency 531system.cpu.icache.overall_avg_miss_latency::cpu.inst 31929.130850 # average overall miss latency 532system.cpu.icache.overall_avg_miss_latency::total 31929.130850 # average overall miss latency 533system.cpu.icache.blocked_cycles::no_mshrs 608 # number of cycles access was blocked 534system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 535system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked 536system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 537system.cpu.icache.avg_blocked_cycles::no_mshrs 38 # average number of cycles each access was blocked 538system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 539system.cpu.icache.fast_writes 0 # number of fast writes performed 540system.cpu.icache.cache_copies 0 # number of cache copies performed 541system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1123 # number of ReadReq MSHR hits 542system.cpu.icache.ReadReq_mshr_hits::total 1123 # number of ReadReq MSHR hits 543system.cpu.icache.demand_mshr_hits::cpu.inst 1123 # number of demand (read+write) MSHR hits 544system.cpu.icache.demand_mshr_hits::total 1123 # number of demand (read+write) MSHR hits 545system.cpu.icache.overall_mshr_hits::cpu.inst 1123 # number of overall MSHR hits 546system.cpu.icache.overall_mshr_hits::total 1123 # number of overall MSHR hits 547system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4112 # number of ReadReq MSHR misses 548system.cpu.icache.ReadReq_mshr_misses::total 4112 # number of ReadReq MSHR misses 549system.cpu.icache.demand_mshr_misses::cpu.inst 4112 # number of demand (read+write) MSHR misses 550system.cpu.icache.demand_mshr_misses::total 4112 # number of demand (read+write) MSHR misses 551system.cpu.icache.overall_mshr_misses::cpu.inst 4112 # number of overall MSHR misses 552system.cpu.icache.overall_mshr_misses::total 4112 # number of overall MSHR misses 553system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 128908500 # number of ReadReq MSHR miss cycles 554system.cpu.icache.ReadReq_mshr_miss_latency::total 128908500 # number of ReadReq MSHR miss cycles 555system.cpu.icache.demand_mshr_miss_latency::cpu.inst 128908500 # number of demand (read+write) MSHR miss cycles 556system.cpu.icache.demand_mshr_miss_latency::total 128908500 # number of demand (read+write) MSHR miss cycles 557system.cpu.icache.overall_mshr_miss_latency::cpu.inst 128908500 # number of overall MSHR miss cycles 558system.cpu.icache.overall_mshr_miss_latency::total 128908500 # number of overall MSHR miss cycles 559system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for ReadReq accesses 560system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000112 # mshr miss rate for ReadReq accesses 561system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for demand accesses 562system.cpu.icache.demand_mshr_miss_rate::total 0.000112 # mshr miss rate for demand accesses 563system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for overall accesses 564system.cpu.icache.overall_mshr_miss_rate::total 0.000112 # mshr miss rate for overall accesses 565system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 31349.343385 # average ReadReq mshr miss latency 566system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 31349.343385 # average ReadReq mshr miss latency 567system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 31349.343385 # average overall mshr miss latency 568system.cpu.icache.demand_avg_mshr_miss_latency::total 31349.343385 # average overall mshr miss latency 569system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 31349.343385 # average overall mshr miss latency 570system.cpu.icache.overall_avg_mshr_miss_latency::total 31349.343385 # average overall mshr miss latency 571system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 572system.cpu.l2cache.replacements 0 # number of replacements 573system.cpu.l2cache.tagsinuse 1970.529288 # Cycle average of tags in use 574system.cpu.l2cache.total_refs 2136 # Total number of references to valid blocks. 575system.cpu.l2cache.sampled_refs 2737 # Sample count of references to valid blocks. 576system.cpu.l2cache.avg_refs 0.780417 # Average number of references to valid blocks. 577system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 578system.cpu.l2cache.occ_blocks::writebacks 4.024044 # Average occupied blocks per requestor 579system.cpu.l2cache.occ_blocks::cpu.inst 1429.621147 # Average occupied blocks per requestor 580system.cpu.l2cache.occ_blocks::cpu.data 536.884097 # Average occupied blocks per requestor 581system.cpu.l2cache.occ_percent::writebacks 0.000123 # Average percentage of cache occupancy 582system.cpu.l2cache.occ_percent::cpu.inst 0.043629 # Average percentage of cache occupancy 583system.cpu.l2cache.occ_percent::cpu.data 0.016384 # Average percentage of cache occupancy 584system.cpu.l2cache.occ_percent::total 0.060136 # Average percentage of cache occupancy 585system.cpu.l2cache.ReadReq_hits::cpu.inst 2045 # number of ReadReq hits 586system.cpu.l2cache.ReadReq_hits::cpu.data 90 # number of ReadReq hits 587system.cpu.l2cache.ReadReq_hits::total 2135 # number of ReadReq hits 588system.cpu.l2cache.Writeback_hits::writebacks 19 # number of Writeback hits 589system.cpu.l2cache.Writeback_hits::total 19 # number of Writeback hits 590system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits 591system.cpu.l2cache.UpgradeReq_hits::total 3 # number of UpgradeReq hits 592system.cpu.l2cache.ReadExReq_hits::cpu.data 10 # number of ReadExReq hits 593system.cpu.l2cache.ReadExReq_hits::total 10 # number of ReadExReq hits 594system.cpu.l2cache.demand_hits::cpu.inst 2045 # number of demand (read+write) hits 595system.cpu.l2cache.demand_hits::cpu.data 100 # number of demand (read+write) hits 596system.cpu.l2cache.demand_hits::total 2145 # number of demand (read+write) hits 597system.cpu.l2cache.overall_hits::cpu.inst 2045 # number of overall hits 598system.cpu.l2cache.overall_hits::cpu.data 100 # number of overall hits 599system.cpu.l2cache.overall_hits::total 2145 # number of overall hits 600system.cpu.l2cache.ReadReq_misses::cpu.inst 2064 # number of ReadReq misses 601system.cpu.l2cache.ReadReq_misses::cpu.data 683 # number of ReadReq misses 602system.cpu.l2cache.ReadReq_misses::total 2747 # number of ReadReq misses 603system.cpu.l2cache.UpgradeReq_misses::cpu.data 2 # number of UpgradeReq misses 604system.cpu.l2cache.UpgradeReq_misses::total 2 # number of UpgradeReq misses 605system.cpu.l2cache.ReadExReq_misses::cpu.data 1077 # number of ReadExReq misses 606system.cpu.l2cache.ReadExReq_misses::total 1077 # number of ReadExReq misses 607system.cpu.l2cache.demand_misses::cpu.inst 2064 # number of demand (read+write) misses 608system.cpu.l2cache.demand_misses::cpu.data 1760 # number of demand (read+write) misses 609system.cpu.l2cache.demand_misses::total 3824 # number of demand (read+write) misses 610system.cpu.l2cache.overall_misses::cpu.inst 2064 # number of overall misses 611system.cpu.l2cache.overall_misses::cpu.data 1760 # number of overall misses 612system.cpu.l2cache.overall_misses::total 3824 # number of overall misses 613system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 104326000 # number of ReadReq miss cycles 614system.cpu.l2cache.ReadReq_miss_latency::cpu.data 39339000 # number of ReadReq miss cycles 615system.cpu.l2cache.ReadReq_miss_latency::total 143665000 # number of ReadReq miss cycles 616system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 49436000 # number of ReadExReq miss cycles 617system.cpu.l2cache.ReadExReq_miss_latency::total 49436000 # number of ReadExReq miss cycles 618system.cpu.l2cache.demand_miss_latency::cpu.inst 104326000 # number of demand (read+write) miss cycles 619system.cpu.l2cache.demand_miss_latency::cpu.data 88775000 # number of demand (read+write) miss cycles 620system.cpu.l2cache.demand_miss_latency::total 193101000 # number of demand (read+write) miss cycles 621system.cpu.l2cache.overall_miss_latency::cpu.inst 104326000 # number of overall miss cycles 622system.cpu.l2cache.overall_miss_latency::cpu.data 88775000 # number of overall miss cycles 623system.cpu.l2cache.overall_miss_latency::total 193101000 # number of overall miss cycles 624system.cpu.l2cache.ReadReq_accesses::cpu.inst 4109 # number of ReadReq accesses(hits+misses) 625system.cpu.l2cache.ReadReq_accesses::cpu.data 773 # number of ReadReq accesses(hits+misses) 626system.cpu.l2cache.ReadReq_accesses::total 4882 # number of ReadReq accesses(hits+misses) 627system.cpu.l2cache.Writeback_accesses::writebacks 19 # number of Writeback accesses(hits+misses) 628system.cpu.l2cache.Writeback_accesses::total 19 # number of Writeback accesses(hits+misses) 629system.cpu.l2cache.UpgradeReq_accesses::cpu.data 5 # number of UpgradeReq accesses(hits+misses) 630system.cpu.l2cache.UpgradeReq_accesses::total 5 # number of UpgradeReq accesses(hits+misses) 631system.cpu.l2cache.ReadExReq_accesses::cpu.data 1087 # number of ReadExReq accesses(hits+misses) 632system.cpu.l2cache.ReadExReq_accesses::total 1087 # number of ReadExReq accesses(hits+misses) 633system.cpu.l2cache.demand_accesses::cpu.inst 4109 # number of demand (read+write) accesses 634system.cpu.l2cache.demand_accesses::cpu.data 1860 # number of demand (read+write) accesses 635system.cpu.l2cache.demand_accesses::total 5969 # number of demand (read+write) accesses 636system.cpu.l2cache.overall_accesses::cpu.inst 4109 # number of overall (read+write) accesses 637system.cpu.l2cache.overall_accesses::cpu.data 1860 # number of overall (read+write) accesses 638system.cpu.l2cache.overall_accesses::total 5969 # number of overall (read+write) accesses 639system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.502312 # miss rate for ReadReq accesses 640system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.883571 # miss rate for ReadReq accesses 641system.cpu.l2cache.ReadReq_miss_rate::total 0.562679 # miss rate for ReadReq accesses 642system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.400000 # miss rate for UpgradeReq accesses 643system.cpu.l2cache.UpgradeReq_miss_rate::total 0.400000 # miss rate for UpgradeReq accesses 644system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.990800 # miss rate for ReadExReq accesses 645system.cpu.l2cache.ReadExReq_miss_rate::total 0.990800 # miss rate for ReadExReq accesses 646system.cpu.l2cache.demand_miss_rate::cpu.inst 0.502312 # miss rate for demand accesses 647system.cpu.l2cache.demand_miss_rate::cpu.data 0.946237 # miss rate for demand accesses 648system.cpu.l2cache.demand_miss_rate::total 0.640643 # miss rate for demand accesses 649system.cpu.l2cache.overall_miss_rate::cpu.inst 0.502312 # miss rate for overall accesses 650system.cpu.l2cache.overall_miss_rate::cpu.data 0.946237 # miss rate for overall accesses 651system.cpu.l2cache.overall_miss_rate::total 0.640643 # miss rate for overall accesses 652system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50545.542636 # average ReadReq miss latency 653system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57597.364568 # average ReadReq miss latency 654system.cpu.l2cache.ReadReq_avg_miss_latency::total 52298.871496 # average ReadReq miss latency 655system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 45901.578459 # average ReadExReq miss latency 656system.cpu.l2cache.ReadExReq_avg_miss_latency::total 45901.578459 # average ReadExReq miss latency 657system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50545.542636 # average overall miss latency 658system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50440.340909 # average overall miss latency 659system.cpu.l2cache.demand_avg_miss_latency::total 50497.123431 # average overall miss latency 660system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50545.542636 # average overall miss latency 661system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50440.340909 # average overall miss latency 662system.cpu.l2cache.overall_avg_miss_latency::total 50497.123431 # average overall miss latency 663system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 664system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 665system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 666system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 667system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 668system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 669system.cpu.l2cache.fast_writes 0 # number of fast writes performed 670system.cpu.l2cache.cache_copies 0 # number of cache copies performed 671system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits 672system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 11 # number of ReadReq MSHR hits 673system.cpu.l2cache.ReadReq_mshr_hits::total 15 # number of ReadReq MSHR hits 674system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits 675system.cpu.l2cache.demand_mshr_hits::cpu.data 11 # number of demand (read+write) MSHR hits 676system.cpu.l2cache.demand_mshr_hits::total 15 # number of demand (read+write) MSHR hits 677system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits 678system.cpu.l2cache.overall_mshr_hits::cpu.data 11 # number of overall MSHR hits 679system.cpu.l2cache.overall_mshr_hits::total 15 # number of overall MSHR hits 680system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2060 # number of ReadReq MSHR misses 681system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 672 # number of ReadReq MSHR misses 682system.cpu.l2cache.ReadReq_mshr_misses::total 2732 # number of ReadReq MSHR misses 683system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2 # number of UpgradeReq MSHR misses 684system.cpu.l2cache.UpgradeReq_mshr_misses::total 2 # number of UpgradeReq MSHR misses 685system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1077 # number of ReadExReq MSHR misses 686system.cpu.l2cache.ReadExReq_mshr_misses::total 1077 # number of ReadExReq MSHR misses 687system.cpu.l2cache.demand_mshr_misses::cpu.inst 2060 # number of demand (read+write) MSHR misses 688system.cpu.l2cache.demand_mshr_misses::cpu.data 1749 # number of demand (read+write) MSHR misses 689system.cpu.l2cache.demand_mshr_misses::total 3809 # number of demand (read+write) MSHR misses 690system.cpu.l2cache.overall_mshr_misses::cpu.inst 2060 # number of overall MSHR misses 691system.cpu.l2cache.overall_mshr_misses::cpu.data 1749 # number of overall MSHR misses 692system.cpu.l2cache.overall_mshr_misses::total 3809 # number of overall MSHR misses 693system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 78499737 # number of ReadReq MSHR miss cycles 694system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 30515256 # number of ReadReq MSHR miss cycles 695system.cpu.l2cache.ReadReq_mshr_miss_latency::total 109014993 # number of ReadReq MSHR miss cycles 696system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 20002 # number of UpgradeReq MSHR miss cycles 697system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 20002 # number of UpgradeReq MSHR miss cycles 698system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 36053347 # number of ReadExReq MSHR miss cycles 699system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 36053347 # number of ReadExReq MSHR miss cycles 700system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 78499737 # number of demand (read+write) MSHR miss cycles 701system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 66568603 # number of demand (read+write) MSHR miss cycles 702system.cpu.l2cache.demand_mshr_miss_latency::total 145068340 # number of demand (read+write) MSHR miss cycles 703system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 78499737 # number of overall MSHR miss cycles 704system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 66568603 # number of overall MSHR miss cycles 705system.cpu.l2cache.overall_mshr_miss_latency::total 145068340 # number of overall MSHR miss cycles 706system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.501339 # mshr miss rate for ReadReq accesses 707system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.869340 # mshr miss rate for ReadReq accesses 708system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.559607 # mshr miss rate for ReadReq accesses 709system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.400000 # mshr miss rate for UpgradeReq accesses 710system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.400000 # mshr miss rate for UpgradeReq accesses 711system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.990800 # mshr miss rate for ReadExReq accesses 712system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.990800 # mshr miss rate for ReadExReq accesses 713system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.501339 # mshr miss rate for demand accesses 714system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.940323 # mshr miss rate for demand accesses 715system.cpu.l2cache.demand_mshr_miss_rate::total 0.638130 # mshr miss rate for demand accesses 716system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.501339 # mshr miss rate for overall accesses 717system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.940323 # mshr miss rate for overall accesses 718system.cpu.l2cache.overall_mshr_miss_rate::total 0.638130 # mshr miss rate for overall accesses 719system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38106.668447 # average ReadReq mshr miss latency 720system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45409.607143 # average ReadReq mshr miss latency 721system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39902.998902 # average ReadReq mshr miss latency 722system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 723system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency 724system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33475.716806 # average ReadExReq mshr miss latency 725system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33475.716806 # average ReadExReq mshr miss latency 726system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38106.668447 # average overall mshr miss latency 727system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38060.950829 # average overall mshr miss latency 728system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38085.676030 # average overall mshr miss latency 729system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38106.668447 # average overall mshr miss latency 730system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38060.950829 # average overall mshr miss latency 731system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38085.676030 # average overall mshr miss latency 732system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 733system.cpu.dcache.replacements 61 # number of replacements 734system.cpu.dcache.tagsinuse 1409.645291 # Cycle average of tags in use 735system.cpu.dcache.total_refs 46783527 # Total number of references to valid blocks. 736system.cpu.dcache.sampled_refs 1860 # Sample count of references to valid blocks. 737system.cpu.dcache.avg_refs 25152.433871 # Average number of references to valid blocks. 738system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 739system.cpu.dcache.occ_blocks::cpu.data 1409.645291 # Average occupied blocks per requestor 740system.cpu.dcache.occ_percent::cpu.data 0.344152 # Average percentage of cache occupancy 741system.cpu.dcache.occ_percent::total 0.344152 # Average percentage of cache occupancy 742system.cpu.dcache.ReadReq_hits::cpu.data 34382093 # number of ReadReq hits 743system.cpu.dcache.ReadReq_hits::total 34382093 # number of ReadReq hits 744system.cpu.dcache.WriteReq_hits::cpu.data 12356549 # number of WriteReq hits 745system.cpu.dcache.WriteReq_hits::total 12356549 # number of WriteReq hits 746system.cpu.dcache.LoadLockedReq_hits::cpu.data 22473 # number of LoadLockedReq hits 747system.cpu.dcache.LoadLockedReq_hits::total 22473 # number of LoadLockedReq hits 748system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits 749system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits 750system.cpu.dcache.demand_hits::cpu.data 46738642 # number of demand (read+write) hits 751system.cpu.dcache.demand_hits::total 46738642 # number of demand (read+write) hits 752system.cpu.dcache.overall_hits::cpu.data 46738642 # number of overall hits 753system.cpu.dcache.overall_hits::total 46738642 # number of overall hits 754system.cpu.dcache.ReadReq_misses::cpu.data 1903 # number of ReadReq misses 755system.cpu.dcache.ReadReq_misses::total 1903 # number of ReadReq misses 756system.cpu.dcache.WriteReq_misses::cpu.data 7738 # number of WriteReq misses 757system.cpu.dcache.WriteReq_misses::total 7738 # number of WriteReq misses 758system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 759system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 760system.cpu.dcache.demand_misses::cpu.data 9641 # number of demand (read+write) misses 761system.cpu.dcache.demand_misses::total 9641 # number of demand (read+write) misses 762system.cpu.dcache.overall_misses::cpu.data 9641 # number of overall misses 763system.cpu.dcache.overall_misses::total 9641 # number of overall misses 764system.cpu.dcache.ReadReq_miss_latency::cpu.data 93214000 # number of ReadReq miss cycles 765system.cpu.dcache.ReadReq_miss_latency::total 93214000 # number of ReadReq miss cycles 766system.cpu.dcache.WriteReq_miss_latency::cpu.data 305598496 # number of WriteReq miss cycles 767system.cpu.dcache.WriteReq_miss_latency::total 305598496 # number of WriteReq miss cycles 768system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 102000 # number of LoadLockedReq miss cycles 769system.cpu.dcache.LoadLockedReq_miss_latency::total 102000 # number of LoadLockedReq miss cycles 770system.cpu.dcache.demand_miss_latency::cpu.data 398812496 # number of demand (read+write) miss cycles 771system.cpu.dcache.demand_miss_latency::total 398812496 # number of demand (read+write) miss cycles 772system.cpu.dcache.overall_miss_latency::cpu.data 398812496 # number of overall miss cycles 773system.cpu.dcache.overall_miss_latency::total 398812496 # number of overall miss cycles 774system.cpu.dcache.ReadReq_accesses::cpu.data 34383996 # number of ReadReq accesses(hits+misses) 775system.cpu.dcache.ReadReq_accesses::total 34383996 # number of ReadReq accesses(hits+misses) 776system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) 777system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) 778system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22475 # number of LoadLockedReq accesses(hits+misses) 779system.cpu.dcache.LoadLockedReq_accesses::total 22475 # number of LoadLockedReq accesses(hits+misses) 780system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) 781system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) 782system.cpu.dcache.demand_accesses::cpu.data 46748283 # number of demand (read+write) accesses 783system.cpu.dcache.demand_accesses::total 46748283 # number of demand (read+write) accesses 784system.cpu.dcache.overall_accesses::cpu.data 46748283 # number of overall (read+write) accesses 785system.cpu.dcache.overall_accesses::total 46748283 # number of overall (read+write) accesses 786system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000055 # miss rate for ReadReq accesses 787system.cpu.dcache.ReadReq_miss_rate::total 0.000055 # miss rate for ReadReq accesses 788system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000626 # miss rate for WriteReq accesses 789system.cpu.dcache.WriteReq_miss_rate::total 0.000626 # miss rate for WriteReq accesses 790system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000089 # miss rate for LoadLockedReq accesses 791system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000089 # miss rate for LoadLockedReq accesses 792system.cpu.dcache.demand_miss_rate::cpu.data 0.000206 # miss rate for demand accesses 793system.cpu.dcache.demand_miss_rate::total 0.000206 # miss rate for demand accesses 794system.cpu.dcache.overall_miss_rate::cpu.data 0.000206 # miss rate for overall accesses 795system.cpu.dcache.overall_miss_rate::total 0.000206 # miss rate for overall accesses 796system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48982.658960 # average ReadReq miss latency 797system.cpu.dcache.ReadReq_avg_miss_latency::total 48982.658960 # average ReadReq miss latency 798system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39493.214784 # average WriteReq miss latency 799system.cpu.dcache.WriteReq_avg_miss_latency::total 39493.214784 # average WriteReq miss latency 800system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 51000 # average LoadLockedReq miss latency 801system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 51000 # average LoadLockedReq miss latency 802system.cpu.dcache.demand_avg_miss_latency::cpu.data 41366.299761 # average overall miss latency 803system.cpu.dcache.demand_avg_miss_latency::total 41366.299761 # average overall miss latency 804system.cpu.dcache.overall_avg_miss_latency::cpu.data 41366.299761 # average overall miss latency 805system.cpu.dcache.overall_avg_miss_latency::total 41366.299761 # average overall miss latency 806system.cpu.dcache.blocked_cycles::no_mshrs 527 # number of cycles access was blocked 807system.cpu.dcache.blocked_cycles::no_targets 67 # number of cycles access was blocked 808system.cpu.dcache.blocked::no_mshrs 13 # number of cycles access was blocked 809system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked 810system.cpu.dcache.avg_blocked_cycles::no_mshrs 40.538462 # average number of cycles each access was blocked 811system.cpu.dcache.avg_blocked_cycles::no_targets 33.500000 # average number of cycles each access was blocked 812system.cpu.dcache.fast_writes 0 # number of fast writes performed 813system.cpu.dcache.cache_copies 0 # number of cache copies performed 814system.cpu.dcache.writebacks::writebacks 19 # number of writebacks 815system.cpu.dcache.writebacks::total 19 # number of writebacks 816system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1128 # number of ReadReq MSHR hits 817system.cpu.dcache.ReadReq_mshr_hits::total 1128 # number of ReadReq MSHR hits 818system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6648 # number of WriteReq MSHR hits 819system.cpu.dcache.WriteReq_mshr_hits::total 6648 # number of WriteReq MSHR hits 820system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 821system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits 822system.cpu.dcache.demand_mshr_hits::cpu.data 7776 # number of demand (read+write) MSHR hits 823system.cpu.dcache.demand_mshr_hits::total 7776 # number of demand (read+write) MSHR hits 824system.cpu.dcache.overall_mshr_hits::cpu.data 7776 # number of overall MSHR hits 825system.cpu.dcache.overall_mshr_hits::total 7776 # number of overall MSHR hits 826system.cpu.dcache.ReadReq_mshr_misses::cpu.data 775 # number of ReadReq MSHR misses 827system.cpu.dcache.ReadReq_mshr_misses::total 775 # number of ReadReq MSHR misses 828system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1090 # number of WriteReq MSHR misses 829system.cpu.dcache.WriteReq_mshr_misses::total 1090 # number of WriteReq MSHR misses 830system.cpu.dcache.demand_mshr_misses::cpu.data 1865 # number of demand (read+write) MSHR misses 831system.cpu.dcache.demand_mshr_misses::total 1865 # number of demand (read+write) MSHR misses 832system.cpu.dcache.overall_mshr_misses::cpu.data 1865 # number of overall MSHR misses 833system.cpu.dcache.overall_mshr_misses::total 1865 # number of overall MSHR misses 834system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 41130000 # number of ReadReq MSHR miss cycles 835system.cpu.dcache.ReadReq_mshr_miss_latency::total 41130000 # number of ReadReq MSHR miss cycles 836system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 50620998 # number of WriteReq MSHR miss cycles 837system.cpu.dcache.WriteReq_mshr_miss_latency::total 50620998 # number of WriteReq MSHR miss cycles 838system.cpu.dcache.demand_mshr_miss_latency::cpu.data 91750998 # number of demand (read+write) MSHR miss cycles 839system.cpu.dcache.demand_mshr_miss_latency::total 91750998 # number of demand (read+write) MSHR miss cycles 840system.cpu.dcache.overall_mshr_miss_latency::cpu.data 91750998 # number of overall MSHR miss cycles 841system.cpu.dcache.overall_mshr_miss_latency::total 91750998 # number of overall MSHR miss cycles 842system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses 843system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses 844system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses 845system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000088 # mshr miss rate for WriteReq accesses 846system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses 847system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses 848system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses 849system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses 850system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53070.967742 # average ReadReq mshr miss latency 851system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53070.967742 # average ReadReq mshr miss latency 852system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46441.282569 # average WriteReq mshr miss latency 853system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46441.282569 # average WriteReq mshr miss latency 854system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49196.245576 # average overall mshr miss latency 855system.cpu.dcache.demand_avg_mshr_miss_latency::total 49196.245576 # average overall mshr miss latency 856system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49196.245576 # average overall mshr miss latency 857system.cpu.dcache.overall_avg_mshr_miss_latency::total 49196.245576 # average overall mshr miss latency 858system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 859 860---------- End Simulation Statistics ---------- 861