stats.txt revision 8825:23b349d77ac1
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.105851 # Number of seconds simulated 4sim_ticks 105850842000 # Number of ticks simulated 5final_tick 105850842000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 46914 # Simulator instruction rate (inst/s) 8host_tick_rate 26320721 # Simulator tick rate (ticks/s) 9host_mem_usage 259812 # Number of bytes of host memory used 10host_seconds 4021.58 # Real time elapsed on the host 11sim_insts 188667627 # Number of instructions simulated 12system.physmem.bytes_read 239936 # Number of bytes read from this memory 13system.physmem.bytes_inst_read 128320 # Number of instructions bytes read from this memory 14system.physmem.bytes_written 0 # Number of bytes written to this memory 15system.physmem.num_reads 3749 # Number of read requests responded to by this memory 16system.physmem.num_writes 0 # Number of write requests responded to by this memory 17system.physmem.num_other 0 # Number of other requests responded to by this memory 18system.physmem.bw_read 2266737 # Total read bandwidth from this memory (bytes/s) 19system.physmem.bw_inst_read 1212272 # Instruction read bandwidth from this memory (bytes/s) 20system.physmem.bw_total 2266737 # Total bandwidth to/from this memory (bytes/s) 21system.cpu.dtb.inst_hits 0 # ITB inst hits 22system.cpu.dtb.inst_misses 0 # ITB inst misses 23system.cpu.dtb.read_hits 0 # DTB read hits 24system.cpu.dtb.read_misses 0 # DTB read misses 25system.cpu.dtb.write_hits 0 # DTB write hits 26system.cpu.dtb.write_misses 0 # DTB write misses 27system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 28system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 29system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 30system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 31system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 32system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 33system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 34system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 35system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 36system.cpu.dtb.read_accesses 0 # DTB read accesses 37system.cpu.dtb.write_accesses 0 # DTB write accesses 38system.cpu.dtb.inst_accesses 0 # ITB inst accesses 39system.cpu.dtb.hits 0 # DTB hits 40system.cpu.dtb.misses 0 # DTB misses 41system.cpu.dtb.accesses 0 # DTB accesses 42system.cpu.itb.inst_hits 0 # ITB inst hits 43system.cpu.itb.inst_misses 0 # ITB inst misses 44system.cpu.itb.read_hits 0 # DTB read hits 45system.cpu.itb.read_misses 0 # DTB read misses 46system.cpu.itb.write_hits 0 # DTB write hits 47system.cpu.itb.write_misses 0 # DTB write misses 48system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 49system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 50system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 51system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 52system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 53system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 54system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 55system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 56system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 57system.cpu.itb.read_accesses 0 # DTB read accesses 58system.cpu.itb.write_accesses 0 # DTB write accesses 59system.cpu.itb.inst_accesses 0 # ITB inst accesses 60system.cpu.itb.hits 0 # DTB hits 61system.cpu.itb.misses 0 # DTB misses 62system.cpu.itb.accesses 0 # DTB accesses 63system.cpu.workload.num_syscalls 400 # Number of system calls 64system.cpu.numCycles 211701685 # number of cpu cycles simulated 65system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 66system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 67system.cpu.BPredUnit.lookups 102100879 # Number of BP lookups 68system.cpu.BPredUnit.condPredicted 80677195 # Number of conditional branches predicted 69system.cpu.BPredUnit.condIncorrect 9930193 # Number of conditional branches incorrect 70system.cpu.BPredUnit.BTBLookups 84233443 # Number of BTB lookups 71system.cpu.BPredUnit.BTBHits 79245701 # Number of BTB hits 72system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 73system.cpu.BPredUnit.usedRAS 4698090 # Number of times the RAS was used to get a target. 74system.cpu.BPredUnit.RASInCorrect 111402 # Number of incorrect RAS predictions. 75system.cpu.fetch.icacheStallCycles 44542965 # Number of cycles fetch is stalled on an Icache miss 76system.cpu.fetch.Insts 416708415 # Number of instructions fetch has processed 77system.cpu.fetch.Branches 102100879 # Number of branches that fetch encountered 78system.cpu.fetch.predictedBranches 83943791 # Number of branches that fetch has predicted taken 79system.cpu.fetch.Cycles 108793327 # Number of cycles fetch has run and was not squashing or blocked 80system.cpu.fetch.SquashCycles 33207424 # Number of cycles fetch has spent squashing 81system.cpu.fetch.BlockedCycles 35058719 # Number of cycles fetch has spent blocked 82system.cpu.fetch.MiscStallCycles 11 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 83system.cpu.fetch.PendingTrapStallCycles 259 # Number of stall cycles due to pending traps 84system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions 85system.cpu.fetch.CacheLines 40619675 # Number of cache lines fetched 86system.cpu.fetch.IcacheSquashes 2204435 # Number of outstanding Icache misses that were squashed 87system.cpu.fetch.rateDist::samples 211643202 # Number of instructions fetched each cycle (Total) 88system.cpu.fetch.rateDist::mean 2.135620 # Number of instructions fetched each cycle (Total) 89system.cpu.fetch.rateDist::stdev 2.646860 # Number of instructions fetched each cycle (Total) 90system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 91system.cpu.fetch.rateDist::0 103052143 48.69% 48.69% # Number of instructions fetched each cycle (Total) 92system.cpu.fetch.rateDist::1 4614041 2.18% 50.87% # Number of instructions fetched each cycle (Total) 93system.cpu.fetch.rateDist::2 32953123 15.57% 66.44% # Number of instructions fetched each cycle (Total) 94system.cpu.fetch.rateDist::3 18235328 8.62% 75.06% # Number of instructions fetched each cycle (Total) 95system.cpu.fetch.rateDist::4 9171108 4.33% 79.39% # Number of instructions fetched each cycle (Total) 96system.cpu.fetch.rateDist::5 12530200 5.92% 85.31% # Number of instructions fetched each cycle (Total) 97system.cpu.fetch.rateDist::6 8476968 4.01% 89.32% # Number of instructions fetched each cycle (Total) 98system.cpu.fetch.rateDist::7 4316297 2.04% 91.36% # Number of instructions fetched each cycle (Total) 99system.cpu.fetch.rateDist::8 18293994 8.64% 100.00% # Number of instructions fetched each cycle (Total) 100system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 101system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 102system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 103system.cpu.fetch.rateDist::total 211643202 # Number of instructions fetched each cycle (Total) 104system.cpu.fetch.branchRate 0.482287 # Number of branch fetches per cycle 105system.cpu.fetch.rate 1.968376 # Number of inst fetches per cycle 106system.cpu.decode.IdleCycles 53231519 # Number of cycles decode is idle 107system.cpu.decode.BlockedCycles 33609414 # Number of cycles decode is blocked 108system.cpu.decode.RunCycles 100494512 # Number of cycles decode is running 109system.cpu.decode.UnblockCycles 1217161 # Number of cycles decode is unblocking 110system.cpu.decode.SquashCycles 23090596 # Number of cycles decode is squashing 111system.cpu.decode.BranchResolved 14181130 # Number of times decode resolved a branch 112system.cpu.decode.BranchMispred 166488 # Number of times decode detected a branch misprediction 113system.cpu.decode.DecodedInsts 422617374 # Number of instructions handled by decode 114system.cpu.decode.SquashedInsts 695976 # Number of squashed instructions handled by decode 115system.cpu.rename.SquashCycles 23090596 # Number of cycles rename is squashing 116system.cpu.rename.IdleCycles 62189594 # Number of cycles rename is idle 117system.cpu.rename.BlockCycles 455687 # Number of cycles rename is blocking 118system.cpu.rename.serializeStallCycles 28663702 # count of cycles rename stalled for serializing inst 119system.cpu.rename.RunCycles 92677243 # Number of cycles rename is running 120system.cpu.rename.UnblockCycles 4566380 # Number of cycles rename is unblocking 121system.cpu.rename.RenamedInsts 388527700 # Number of instructions processed by rename 122system.cpu.rename.IQFullEvents 20997 # Number of times rename has blocked due to IQ full 123system.cpu.rename.LSQFullEvents 2241803 # Number of times rename has blocked due to LSQ full 124system.cpu.rename.RenamedOperands 666137382 # Number of destination operands rename has renamed 125system.cpu.rename.RenameLookups 1656361753 # Number of register rename lookups that rename has made 126system.cpu.rename.int_rename_lookups 1638646831 # Number of integer rename lookups 127system.cpu.rename.fp_rename_lookups 17714922 # Number of floating rename lookups 128system.cpu.rename.CommittedMaps 298061936 # Number of HB maps that are committed 129system.cpu.rename.UndoneMaps 368075446 # Number of HB maps that are undone due to squashing 130system.cpu.rename.serializingInsts 2723266 # count of serializing insts renamed 131system.cpu.rename.tempSerializingInsts 2675408 # count of temporary serializing insts renamed 132system.cpu.rename.skidInsts 23504222 # count of insts added to the skid buffer 133system.cpu.memDep0.insertedLoads 46900559 # Number of loads inserted to the mem dependence unit. 134system.cpu.memDep0.insertedStores 16903337 # Number of stores inserted to the mem dependence unit. 135system.cpu.memDep0.conflictingLoads 3858030 # Number of conflicting loads. 136system.cpu.memDep0.conflictingStores 2525525 # Number of conflicting stores. 137system.cpu.iq.iqInstsAdded 332647611 # Number of instructions added to the IQ (excludes non-spec) 138system.cpu.iq.iqNonSpecInstsAdded 2225423 # Number of non-speculative instructions added to the IQ 139system.cpu.iq.iqInstsIssued 261830951 # Number of instructions issued 140system.cpu.iq.iqSquashedInstsIssued 960204 # Number of squashed instructions issued 141system.cpu.iq.iqSquashedInstsExamined 143464205 # Number of squashed instructions iterated over during squash; mainly for profiling 142system.cpu.iq.iqSquashedOperandsExamined 342029155 # Number of squashed operands that are examined and possibly removed from graph 143system.cpu.iq.iqSquashedNonSpecRemoved 589405 # Number of squashed non-spec instructions that were removed 144system.cpu.iq.issued_per_cycle::samples 211643202 # Number of insts issued each cycle 145system.cpu.iq.issued_per_cycle::mean 1.237134 # Number of insts issued each cycle 146system.cpu.iq.issued_per_cycle::stdev 1.489338 # Number of insts issued each cycle 147system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 148system.cpu.iq.issued_per_cycle::0 97826086 46.22% 46.22% # Number of insts issued each cycle 149system.cpu.iq.issued_per_cycle::1 37864076 17.89% 64.11% # Number of insts issued each cycle 150system.cpu.iq.issued_per_cycle::2 34104807 16.11% 80.23% # Number of insts issued each cycle 151system.cpu.iq.issued_per_cycle::3 22781361 10.76% 90.99% # Number of insts issued each cycle 152system.cpu.iq.issued_per_cycle::4 11447248 5.41% 96.40% # Number of insts issued each cycle 153system.cpu.iq.issued_per_cycle::5 4765675 2.25% 98.65% # Number of insts issued each cycle 154system.cpu.iq.issued_per_cycle::6 2321089 1.10% 99.75% # Number of insts issued each cycle 155system.cpu.iq.issued_per_cycle::7 393603 0.19% 99.93% # Number of insts issued each cycle 156system.cpu.iq.issued_per_cycle::8 139257 0.07% 100.00% # Number of insts issued each cycle 157system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 158system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 159system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 160system.cpu.iq.issued_per_cycle::total 211643202 # Number of insts issued each cycle 161system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 162system.cpu.iq.fu_full::IntAlu 397917 18.24% 18.24% # attempts to use FU when none available 163system.cpu.iq.fu_full::IntMult 5522 0.25% 18.50% # attempts to use FU when none available 164system.cpu.iq.fu_full::IntDiv 0 0.00% 18.50% # attempts to use FU when none available 165system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.50% # attempts to use FU when none available 166system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.50% # attempts to use FU when none available 167system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.50% # attempts to use FU when none available 168system.cpu.iq.fu_full::FloatMult 0 0.00% 18.50% # attempts to use FU when none available 169system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.50% # attempts to use FU when none available 170system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.50% # attempts to use FU when none available 171system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.50% # attempts to use FU when none available 172system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.50% # attempts to use FU when none available 173system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.50% # attempts to use FU when none available 174system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.50% # attempts to use FU when none available 175system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.50% # attempts to use FU when none available 176system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.50% # attempts to use FU when none available 177system.cpu.iq.fu_full::SimdMult 0 0.00% 18.50% # attempts to use FU when none available 178system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.50% # attempts to use FU when none available 179system.cpu.iq.fu_full::SimdShift 0 0.00% 18.50% # attempts to use FU when none available 180system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.50% # attempts to use FU when none available 181system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.50% # attempts to use FU when none available 182system.cpu.iq.fu_full::SimdFloatAdd 50 0.00% 18.50% # attempts to use FU when none available 183system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.50% # attempts to use FU when none available 184system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.50% # attempts to use FU when none available 185system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.50% # attempts to use FU when none available 186system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.50% # attempts to use FU when none available 187system.cpu.iq.fu_full::SimdFloatMisc 46 0.00% 18.50% # attempts to use FU when none available 188system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.50% # attempts to use FU when none available 189system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.50% # attempts to use FU when none available 190system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.50% # attempts to use FU when none available 191system.cpu.iq.fu_full::MemRead 1324685 60.73% 79.23% # attempts to use FU when none available 192system.cpu.iq.fu_full::MemWrite 453082 20.77% 100.00% # attempts to use FU when none available 193system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 194system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 195system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 196system.cpu.iq.FU_type_0::IntAlu 204918446 78.26% 78.26% # Type of FU issued 197system.cpu.iq.FU_type_0::IntMult 928788 0.35% 78.62% # Type of FU issued 198system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.62% # Type of FU issued 199system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.62% # Type of FU issued 200system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.62% # Type of FU issued 201system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.62% # Type of FU issued 202system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.62% # Type of FU issued 203system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.62% # Type of FU issued 204system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.62% # Type of FU issued 205system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.62% # Type of FU issued 206system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.62% # Type of FU issued 207system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.62% # Type of FU issued 208system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.62% # Type of FU issued 209system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.62% # Type of FU issued 210system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.62% # Type of FU issued 211system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.62% # Type of FU issued 212system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.62% # Type of FU issued 213system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.62% # Type of FU issued 214system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.62% # Type of FU issued 215system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.62% # Type of FU issued 216system.cpu.iq.FU_type_0::SimdFloatAdd 33078 0.01% 78.63% # Type of FU issued 217system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.63% # Type of FU issued 218system.cpu.iq.FU_type_0::SimdFloatCmp 166576 0.06% 78.69% # Type of FU issued 219system.cpu.iq.FU_type_0::SimdFloatCvt 257183 0.10% 78.79% # Type of FU issued 220system.cpu.iq.FU_type_0::SimdFloatDiv 76398 0.03% 78.82% # Type of FU issued 221system.cpu.iq.FU_type_0::SimdFloatMisc 467924 0.18% 79.00% # Type of FU issued 222system.cpu.iq.FU_type_0::SimdFloatMult 207596 0.08% 79.08% # Type of FU issued 223system.cpu.iq.FU_type_0::SimdFloatMultAcc 71825 0.03% 79.11% # Type of FU issued 224system.cpu.iq.FU_type_0::SimdFloatSqrt 325 0.00% 79.11% # Type of FU issued 225system.cpu.iq.FU_type_0::MemRead 40744644 15.56% 94.67% # Type of FU issued 226system.cpu.iq.FU_type_0::MemWrite 13958168 5.33% 100.00% # Type of FU issued 227system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 228system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 229system.cpu.iq.FU_type_0::total 261830951 # Type of FU issued 230system.cpu.iq.rate 1.236792 # Inst issue rate 231system.cpu.iq.fu_busy_cnt 2181302 # FU busy when requested 232system.cpu.iq.fu_busy_rate 0.008331 # FU busy rate (busy events/executed inst) 233system.cpu.iq.int_inst_queue_reads 734699293 # Number of integer instruction queue reads 234system.cpu.iq.int_inst_queue_writes 476117347 # Number of integer instruction queue writes 235system.cpu.iq.int_inst_queue_wakeup_accesses 242859396 # Number of integer instruction queue wakeup accesses 236system.cpu.iq.fp_inst_queue_reads 3747317 # Number of floating instruction queue reads 237system.cpu.iq.fp_inst_queue_writes 2232204 # Number of floating instruction queue writes 238system.cpu.iq.fp_inst_queue_wakeup_accesses 1844998 # Number of floating instruction queue wakeup accesses 239system.cpu.iq.int_alu_accesses 262127165 # Number of integer alu accesses 240system.cpu.iq.fp_alu_accesses 1885088 # Number of floating point alu accesses 241system.cpu.iew.lsq.thread0.forwLoads 1590290 # Number of loads that had data forwarded from stores 242system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 243system.cpu.iew.lsq.thread0.squashedLoads 17048851 # Number of loads squashed 244system.cpu.iew.lsq.thread0.ignoredResponses 31549 # Number of memory responses ignored because the instruction is squashed 245system.cpu.iew.lsq.thread0.memOrderViolation 12762 # Number of memory ordering violations 246system.cpu.iew.lsq.thread0.squashedStores 4256480 # Number of stores squashed 247system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 248system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 249system.cpu.iew.lsq.thread0.rescheduledLoads 20 # Number of loads that were rescheduled 250system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked 251system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 252system.cpu.iew.iewSquashCycles 23090596 # Number of cycles IEW is squashing 253system.cpu.iew.iewBlockCycles 13781 # Number of cycles IEW is blocking 254system.cpu.iew.iewUnblockCycles 840 # Number of cycles IEW is unblocking 255system.cpu.iew.iewDispatchedInsts 334926486 # Number of instructions dispatched to IQ 256system.cpu.iew.iewDispSquashedInsts 3752435 # Number of squashed instructions skipped by dispatch 257system.cpu.iew.iewDispLoadInsts 46900559 # Number of dispatched load instructions 258system.cpu.iew.iewDispStoreInsts 16903337 # Number of dispatched store instructions 259system.cpu.iew.iewDispNonSpecInsts 2201532 # Number of dispatched non-speculative instructions 260system.cpu.iew.iewIQFullEvents 340 # Number of times the IQ has become full, causing a stall 261system.cpu.iew.iewLSQFullEvents 255 # Number of times the LSQ has become full, causing a stall 262system.cpu.iew.memOrderViolationEvents 12762 # Number of memory order violations 263system.cpu.iew.predictedTakenIncorrect 9994816 # Number of branches that were predicted taken incorrectly 264system.cpu.iew.predictedNotTakenIncorrect 1695108 # Number of branches that were predicted not taken incorrectly 265system.cpu.iew.branchMispredicts 11689924 # Number of branch mispredicts detected at execute 266system.cpu.iew.iewExecutedInsts 249206258 # Number of executed instructions 267system.cpu.iew.iewExecLoadInsts 38606621 # Number of load instructions executed 268system.cpu.iew.iewExecSquashedInsts 12624693 # Number of squashed instructions skipped in execute 269system.cpu.iew.exec_swp 0 # number of swp insts executed 270system.cpu.iew.exec_nop 53452 # number of nop insts executed 271system.cpu.iew.exec_refs 52203623 # number of memory reference insts executed 272system.cpu.iew.exec_branches 52584405 # Number of branches executed 273system.cpu.iew.exec_stores 13597002 # Number of stores executed 274system.cpu.iew.exec_rate 1.177158 # Inst execution rate 275system.cpu.iew.wb_sent 246234772 # cumulative count of insts sent to commit 276system.cpu.iew.wb_count 244704394 # cumulative count of insts written-back 277system.cpu.iew.wb_producers 148512928 # num instructions producing a value 278system.cpu.iew.wb_consumers 247801271 # num instructions consuming a value 279system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 280system.cpu.iew.wb_rate 1.155893 # insts written-back per cycle 281system.cpu.iew.wb_fanout 0.599323 # average fanout of values written-back 282system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 283system.cpu.commit.commitCommittedInsts 188682015 # The number of committed instructions 284system.cpu.commit.commitSquashedInsts 146244510 # The number of squashed insts skipped by commit 285system.cpu.commit.commitNonSpecStalls 1636018 # The number of times commit has been forced to stall to communicate backwards 286system.cpu.commit.branchMispredicts 9791900 # The number of times a branch was mispredicted 287system.cpu.commit.committed_per_cycle::samples 188552607 # Number of insts commited each cycle 288system.cpu.commit.committed_per_cycle::mean 1.000686 # Number of insts commited each cycle 289system.cpu.commit.committed_per_cycle::stdev 1.681539 # Number of insts commited each cycle 290system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 291system.cpu.commit.committed_per_cycle::0 105375521 55.89% 55.89% # Number of insts commited each cycle 292system.cpu.commit.committed_per_cycle::1 40844225 21.66% 77.55% # Number of insts commited each cycle 293system.cpu.commit.committed_per_cycle::2 19484606 10.33% 87.88% # Number of insts commited each cycle 294system.cpu.commit.committed_per_cycle::3 8759294 4.65% 92.53% # Number of insts commited each cycle 295system.cpu.commit.committed_per_cycle::4 4914501 2.61% 95.13% # Number of insts commited each cycle 296system.cpu.commit.committed_per_cycle::5 2011973 1.07% 96.20% # Number of insts commited each cycle 297system.cpu.commit.committed_per_cycle::6 1708688 0.91% 97.11% # Number of insts commited each cycle 298system.cpu.commit.committed_per_cycle::7 1009693 0.54% 97.64% # Number of insts commited each cycle 299system.cpu.commit.committed_per_cycle::8 4444106 2.36% 100.00% # Number of insts commited each cycle 300system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 301system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 302system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 303system.cpu.commit.committed_per_cycle::total 188552607 # Number of insts commited each cycle 304system.cpu.commit.count 188682015 # Number of instructions committed 305system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 306system.cpu.commit.refs 42498565 # Number of memory references committed 307system.cpu.commit.loads 29851708 # Number of loads committed 308system.cpu.commit.membars 22408 # Number of memory barriers committed 309system.cpu.commit.branches 40283906 # Number of branches committed 310system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. 311system.cpu.commit.int_insts 150115117 # Number of committed integer instructions. 312system.cpu.commit.function_calls 1848934 # Number of function calls committed. 313system.cpu.commit.bw_lim_events 4444106 # number cycles where commit BW limit reached 314system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 315system.cpu.rob.rob_reads 519029825 # The number of ROB reads 316system.cpu.rob.rob_writes 693007050 # The number of ROB writes 317system.cpu.timesIdled 1719 # Number of times that the entire CPU went into an idle state and unscheduled itself 318system.cpu.idleCycles 58483 # Total number of cycles that the CPU has spent unscheduled due to idling 319system.cpu.committedInsts 188667627 # Number of Instructions Simulated 320system.cpu.committedInsts_total 188667627 # Number of Instructions Simulated 321system.cpu.cpi 1.122088 # CPI: Cycles Per Instruction 322system.cpu.cpi_total 1.122088 # CPI: Total CPI of All Threads 323system.cpu.ipc 0.891196 # IPC: Instructions Per Cycle 324system.cpu.ipc_total 0.891196 # IPC: Total IPC of All Threads 325system.cpu.int_regfile_reads 1111988877 # number of integer regfile reads 326system.cpu.int_regfile_writes 407368356 # number of integer regfile writes 327system.cpu.fp_regfile_reads 2928539 # number of floating regfile reads 328system.cpu.fp_regfile_writes 2498508 # number of floating regfile writes 329system.cpu.misc_regfile_reads 502946356 # number of misc regfile reads 330system.cpu.misc_regfile_writes 824482 # number of misc regfile writes 331system.cpu.icache.replacements 1934 # number of replacements 332system.cpu.icache.tagsinuse 1329.301324 # Cycle average of tags in use 333system.cpu.icache.total_refs 40615441 # Total number of references to valid blocks. 334system.cpu.icache.sampled_refs 3640 # Sample count of references to valid blocks. 335system.cpu.icache.avg_refs 11158.088187 # Average number of references to valid blocks. 336system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 337system.cpu.icache.occ_blocks::0 1329.301324 # Average occupied blocks per context 338system.cpu.icache.occ_percent::0 0.649073 # Average percentage of cache occupancy 339system.cpu.icache.ReadReq_hits 40615441 # number of ReadReq hits 340system.cpu.icache.demand_hits 40615441 # number of demand (read+write) hits 341system.cpu.icache.overall_hits 40615441 # number of overall hits 342system.cpu.icache.ReadReq_misses 4234 # number of ReadReq misses 343system.cpu.icache.demand_misses 4234 # number of demand (read+write) misses 344system.cpu.icache.overall_misses 4234 # number of overall misses 345system.cpu.icache.ReadReq_miss_latency 101275500 # number of ReadReq miss cycles 346system.cpu.icache.demand_miss_latency 101275500 # number of demand (read+write) miss cycles 347system.cpu.icache.overall_miss_latency 101275500 # number of overall miss cycles 348system.cpu.icache.ReadReq_accesses 40619675 # number of ReadReq accesses(hits+misses) 349system.cpu.icache.demand_accesses 40619675 # number of demand (read+write) accesses 350system.cpu.icache.overall_accesses 40619675 # number of overall (read+write) accesses 351system.cpu.icache.ReadReq_miss_rate 0.000104 # miss rate for ReadReq accesses 352system.cpu.icache.demand_miss_rate 0.000104 # miss rate for demand accesses 353system.cpu.icache.overall_miss_rate 0.000104 # miss rate for overall accesses 354system.cpu.icache.ReadReq_avg_miss_latency 23919.579594 # average ReadReq miss latency 355system.cpu.icache.demand_avg_miss_latency 23919.579594 # average overall miss latency 356system.cpu.icache.overall_avg_miss_latency 23919.579594 # average overall miss latency 357system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 358system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 359system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 360system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 361system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 362system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 363system.cpu.icache.fast_writes 0 # number of fast writes performed 364system.cpu.icache.cache_copies 0 # number of cache copies performed 365system.cpu.icache.writebacks 0 # number of writebacks 366system.cpu.icache.ReadReq_mshr_hits 594 # number of ReadReq MSHR hits 367system.cpu.icache.demand_mshr_hits 594 # number of demand (read+write) MSHR hits 368system.cpu.icache.overall_mshr_hits 594 # number of overall MSHR hits 369system.cpu.icache.ReadReq_mshr_misses 3640 # number of ReadReq MSHR misses 370system.cpu.icache.demand_mshr_misses 3640 # number of demand (read+write) MSHR misses 371system.cpu.icache.overall_mshr_misses 3640 # number of overall MSHR misses 372system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 373system.cpu.icache.ReadReq_mshr_miss_latency 74572500 # number of ReadReq MSHR miss cycles 374system.cpu.icache.demand_mshr_miss_latency 74572500 # number of demand (read+write) MSHR miss cycles 375system.cpu.icache.overall_mshr_miss_latency 74572500 # number of overall MSHR miss cycles 376system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 377system.cpu.icache.ReadReq_mshr_miss_rate 0.000090 # mshr miss rate for ReadReq accesses 378system.cpu.icache.demand_mshr_miss_rate 0.000090 # mshr miss rate for demand accesses 379system.cpu.icache.overall_mshr_miss_rate 0.000090 # mshr miss rate for overall accesses 380system.cpu.icache.ReadReq_avg_mshr_miss_latency 20486.950549 # average ReadReq mshr miss latency 381system.cpu.icache.demand_avg_mshr_miss_latency 20486.950549 # average overall mshr miss latency 382system.cpu.icache.overall_avg_mshr_miss_latency 20486.950549 # average overall mshr miss latency 383system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 384system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated 385system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 386system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 387system.cpu.dcache.replacements 53 # number of replacements 388system.cpu.dcache.tagsinuse 1403.723956 # Cycle average of tags in use 389system.cpu.dcache.total_refs 48643693 # Total number of references to valid blocks. 390system.cpu.dcache.sampled_refs 1846 # Sample count of references to valid blocks. 391system.cpu.dcache.avg_refs 26350.862947 # Average number of references to valid blocks. 392system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 393system.cpu.dcache.occ_blocks::0 1403.723956 # Average occupied blocks per context 394system.cpu.dcache.occ_percent::0 0.342706 # Average percentage of cache occupancy 395system.cpu.dcache.ReadReq_hits 36234545 # number of ReadReq hits 396system.cpu.dcache.WriteReq_hits 12356727 # number of WriteReq hits 397system.cpu.dcache.LoadLockedReq_hits 27791 # number of LoadLockedReq hits 398system.cpu.dcache.StoreCondReq_hits 24630 # number of StoreCondReq hits 399system.cpu.dcache.demand_hits 48591272 # number of demand (read+write) hits 400system.cpu.dcache.overall_hits 48591272 # number of overall hits 401system.cpu.dcache.ReadReq_misses 1808 # number of ReadReq misses 402system.cpu.dcache.WriteReq_misses 7560 # number of WriteReq misses 403system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses 404system.cpu.dcache.demand_misses 9368 # number of demand (read+write) misses 405system.cpu.dcache.overall_misses 9368 # number of overall misses 406system.cpu.dcache.ReadReq_miss_latency 59529000 # number of ReadReq miss cycles 407system.cpu.dcache.WriteReq_miss_latency 237156500 # number of WriteReq miss cycles 408system.cpu.dcache.LoadLockedReq_miss_latency 63500 # number of LoadLockedReq miss cycles 409system.cpu.dcache.demand_miss_latency 296685500 # number of demand (read+write) miss cycles 410system.cpu.dcache.overall_miss_latency 296685500 # number of overall miss cycles 411system.cpu.dcache.ReadReq_accesses 36236353 # number of ReadReq accesses(hits+misses) 412system.cpu.dcache.WriteReq_accesses 12364287 # number of WriteReq accesses(hits+misses) 413system.cpu.dcache.LoadLockedReq_accesses 27793 # number of LoadLockedReq accesses(hits+misses) 414system.cpu.dcache.StoreCondReq_accesses 24630 # number of StoreCondReq accesses(hits+misses) 415system.cpu.dcache.demand_accesses 48600640 # number of demand (read+write) accesses 416system.cpu.dcache.overall_accesses 48600640 # number of overall (read+write) accesses 417system.cpu.dcache.ReadReq_miss_rate 0.000050 # miss rate for ReadReq accesses 418system.cpu.dcache.WriteReq_miss_rate 0.000611 # miss rate for WriteReq accesses 419system.cpu.dcache.LoadLockedReq_miss_rate 0.000072 # miss rate for LoadLockedReq accesses 420system.cpu.dcache.demand_miss_rate 0.000193 # miss rate for demand accesses 421system.cpu.dcache.overall_miss_rate 0.000193 # miss rate for overall accesses 422system.cpu.dcache.ReadReq_avg_miss_latency 32925.331858 # average ReadReq miss latency 423system.cpu.dcache.WriteReq_avg_miss_latency 31369.907407 # average WriteReq miss latency 424system.cpu.dcache.LoadLockedReq_avg_miss_latency 31750 # average LoadLockedReq miss latency 425system.cpu.dcache.demand_avg_miss_latency 31670.100342 # average overall miss latency 426system.cpu.dcache.overall_avg_miss_latency 31670.100342 # average overall miss latency 427system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 428system.cpu.dcache.blocked_cycles::no_targets 20000 # number of cycles access was blocked 429system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 430system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked 431system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 432system.cpu.dcache.avg_blocked_cycles::no_targets 20000 # average number of cycles each access was blocked 433system.cpu.dcache.fast_writes 0 # number of fast writes performed 434system.cpu.dcache.cache_copies 0 # number of cache copies performed 435system.cpu.dcache.writebacks 18 # number of writebacks 436system.cpu.dcache.ReadReq_mshr_hits 1053 # number of ReadReq MSHR hits 437system.cpu.dcache.WriteReq_mshr_hits 6469 # number of WriteReq MSHR hits 438system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits 439system.cpu.dcache.demand_mshr_hits 7522 # number of demand (read+write) MSHR hits 440system.cpu.dcache.overall_mshr_hits 7522 # number of overall MSHR hits 441system.cpu.dcache.ReadReq_mshr_misses 755 # number of ReadReq MSHR misses 442system.cpu.dcache.WriteReq_mshr_misses 1091 # number of WriteReq MSHR misses 443system.cpu.dcache.demand_mshr_misses 1846 # number of demand (read+write) MSHR misses 444system.cpu.dcache.overall_mshr_misses 1846 # number of overall MSHR misses 445system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 446system.cpu.dcache.ReadReq_mshr_miss_latency 24116500 # number of ReadReq MSHR miss cycles 447system.cpu.dcache.WriteReq_mshr_miss_latency 38344000 # number of WriteReq MSHR miss cycles 448system.cpu.dcache.demand_mshr_miss_latency 62460500 # number of demand (read+write) MSHR miss cycles 449system.cpu.dcache.overall_mshr_miss_latency 62460500 # number of overall MSHR miss cycles 450system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 451system.cpu.dcache.ReadReq_mshr_miss_rate 0.000021 # mshr miss rate for ReadReq accesses 452system.cpu.dcache.WriteReq_mshr_miss_rate 0.000088 # mshr miss rate for WriteReq accesses 453system.cpu.dcache.demand_mshr_miss_rate 0.000038 # mshr miss rate for demand accesses 454system.cpu.dcache.overall_mshr_miss_rate 0.000038 # mshr miss rate for overall accesses 455system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31942.384106 # average ReadReq mshr miss latency 456system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35145.737855 # average WriteReq mshr miss latency 457system.cpu.dcache.demand_avg_mshr_miss_latency 33835.590466 # average overall mshr miss latency 458system.cpu.dcache.overall_avg_mshr_miss_latency 33835.590466 # average overall mshr miss latency 459system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 460system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 461system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 462system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 463system.cpu.l2cache.replacements 0 # number of replacements 464system.cpu.l2cache.tagsinuse 1923.480613 # Cycle average of tags in use 465system.cpu.l2cache.total_refs 1714 # Total number of references to valid blocks. 466system.cpu.l2cache.sampled_refs 2676 # Sample count of references to valid blocks. 467system.cpu.l2cache.avg_refs 0.640508 # Average number of references to valid blocks. 468system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 469system.cpu.l2cache.occ_blocks::0 1919.476269 # Average occupied blocks per context 470system.cpu.l2cache.occ_blocks::1 4.004344 # Average occupied blocks per context 471system.cpu.l2cache.occ_percent::0 0.058578 # Average percentage of cache occupancy 472system.cpu.l2cache.occ_percent::1 0.000122 # Average percentage of cache occupancy 473system.cpu.l2cache.ReadReq_hits 1714 # number of ReadReq hits 474system.cpu.l2cache.Writeback_hits 18 # number of Writeback hits 475system.cpu.l2cache.ReadExReq_hits 9 # number of ReadExReq hits 476system.cpu.l2cache.demand_hits 1723 # number of demand (read+write) hits 477system.cpu.l2cache.overall_hits 1723 # number of overall hits 478system.cpu.l2cache.ReadReq_misses 2681 # number of ReadReq misses 479system.cpu.l2cache.ReadExReq_misses 1082 # number of ReadExReq misses 480system.cpu.l2cache.demand_misses 3763 # number of demand (read+write) misses 481system.cpu.l2cache.overall_misses 3763 # number of overall misses 482system.cpu.l2cache.ReadReq_miss_latency 91922000 # number of ReadReq miss cycles 483system.cpu.l2cache.ReadExReq_miss_latency 37184000 # number of ReadExReq miss cycles 484system.cpu.l2cache.demand_miss_latency 129106000 # number of demand (read+write) miss cycles 485system.cpu.l2cache.overall_miss_latency 129106000 # number of overall miss cycles 486system.cpu.l2cache.ReadReq_accesses 4395 # number of ReadReq accesses(hits+misses) 487system.cpu.l2cache.Writeback_accesses 18 # number of Writeback accesses(hits+misses) 488system.cpu.l2cache.ReadExReq_accesses 1091 # number of ReadExReq accesses(hits+misses) 489system.cpu.l2cache.demand_accesses 5486 # number of demand (read+write) accesses 490system.cpu.l2cache.overall_accesses 5486 # number of overall (read+write) accesses 491system.cpu.l2cache.ReadReq_miss_rate 0.610011 # miss rate for ReadReq accesses 492system.cpu.l2cache.ReadExReq_miss_rate 0.991751 # miss rate for ReadExReq accesses 493system.cpu.l2cache.demand_miss_rate 0.685928 # miss rate for demand accesses 494system.cpu.l2cache.overall_miss_rate 0.685928 # miss rate for overall accesses 495system.cpu.l2cache.ReadReq_avg_miss_latency 34286.460276 # average ReadReq miss latency 496system.cpu.l2cache.ReadExReq_avg_miss_latency 34365.988909 # average ReadExReq miss latency 497system.cpu.l2cache.demand_avg_miss_latency 34309.327664 # average overall miss latency 498system.cpu.l2cache.overall_avg_miss_latency 34309.327664 # average overall miss latency 499system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 500system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 501system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 502system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 503system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 504system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 505system.cpu.l2cache.fast_writes 0 # number of fast writes performed 506system.cpu.l2cache.cache_copies 0 # number of cache copies performed 507system.cpu.l2cache.writebacks 0 # number of writebacks 508system.cpu.l2cache.ReadReq_mshr_hits 14 # number of ReadReq MSHR hits 509system.cpu.l2cache.demand_mshr_hits 14 # number of demand (read+write) MSHR hits 510system.cpu.l2cache.overall_mshr_hits 14 # number of overall MSHR hits 511system.cpu.l2cache.ReadReq_mshr_misses 2667 # number of ReadReq MSHR misses 512system.cpu.l2cache.ReadExReq_mshr_misses 1082 # number of ReadExReq MSHR misses 513system.cpu.l2cache.demand_mshr_misses 3749 # number of demand (read+write) MSHR misses 514system.cpu.l2cache.overall_mshr_misses 3749 # number of overall MSHR misses 515system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 516system.cpu.l2cache.ReadReq_mshr_miss_latency 82895000 # number of ReadReq MSHR miss cycles 517system.cpu.l2cache.ReadExReq_mshr_miss_latency 33590000 # number of ReadExReq MSHR miss cycles 518system.cpu.l2cache.demand_mshr_miss_latency 116485000 # number of demand (read+write) MSHR miss cycles 519system.cpu.l2cache.overall_mshr_miss_latency 116485000 # number of overall MSHR miss cycles 520system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 521system.cpu.l2cache.ReadReq_mshr_miss_rate 0.606826 # mshr miss rate for ReadReq accesses 522system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.991751 # mshr miss rate for ReadExReq accesses 523system.cpu.l2cache.demand_mshr_miss_rate 0.683376 # mshr miss rate for demand accesses 524system.cpu.l2cache.overall_mshr_miss_rate 0.683376 # mshr miss rate for overall accesses 525system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31081.739783 # average ReadReq mshr miss latency 526system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31044.362292 # average ReadExReq mshr miss latency 527system.cpu.l2cache.demand_avg_mshr_miss_latency 31070.952254 # average overall mshr miss latency 528system.cpu.l2cache.overall_avg_mshr_miss_latency 31070.952254 # average overall mshr miss latency 529system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 530system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated 531system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 532system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 533 534---------- End Simulation Statistics ---------- 535