stats.txt revision 10038:7eccd14e2610
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.074220 # Number of seconds simulated 4sim_ticks 74219931000 # Number of ticks simulated 5final_tick 74219931000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 128899 # Simulator instruction rate (inst/s) 8host_op_rate 141133 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 55523526 # Simulator tick rate (ticks/s) 10host_mem_usage 273064 # Number of bytes of host memory used 11host_seconds 1336.73 # Real time elapsed on the host 12sim_insts 172303021 # Number of instructions simulated 13sim_ops 188656503 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 131072 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 111680 # Number of bytes read from this memory 18system.physmem.bytes_read::total 242752 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 131072 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 131072 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 2048 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 1745 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 3793 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 1765995 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 1504717 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 3270712 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 1765995 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 1765995 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 1765995 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 1504717 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 3270712 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 3794 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 3794 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 242816 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 242816 # Total read bytes from the system interface side 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 43system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 44system.physmem.perBankRdBursts::0 306 # Per bank write bursts 45system.physmem.perBankRdBursts::1 215 # Per bank write bursts 46system.physmem.perBankRdBursts::2 133 # Per bank write bursts 47system.physmem.perBankRdBursts::3 308 # Per bank write bursts 48system.physmem.perBankRdBursts::4 298 # Per bank write bursts 49system.physmem.perBankRdBursts::5 299 # Per bank write bursts 50system.physmem.perBankRdBursts::6 264 # Per bank write bursts 51system.physmem.perBankRdBursts::7 216 # Per bank write bursts 52system.physmem.perBankRdBursts::8 246 # Per bank write bursts 53system.physmem.perBankRdBursts::9 215 # Per bank write bursts 54system.physmem.perBankRdBursts::10 289 # Per bank write bursts 55system.physmem.perBankRdBursts::11 193 # Per bank write bursts 56system.physmem.perBankRdBursts::12 189 # Per bank write bursts 57system.physmem.perBankRdBursts::13 206 # Per bank write bursts 58system.physmem.perBankRdBursts::14 217 # Per bank write bursts 59system.physmem.perBankRdBursts::15 200 # Per bank write bursts 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts 63system.physmem.perBankWrBursts::3 0 # Per bank write bursts 64system.physmem.perBankWrBursts::4 0 # Per bank write bursts 65system.physmem.perBankWrBursts::5 0 # Per bank write bursts 66system.physmem.perBankWrBursts::6 0 # Per bank write bursts 67system.physmem.perBankWrBursts::7 0 # Per bank write bursts 68system.physmem.perBankWrBursts::8 0 # Per bank write bursts 69system.physmem.perBankWrBursts::9 0 # Per bank write bursts 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 78system.physmem.totGap 74219912500 # Total gap between requests 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 3794 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) 93system.physmem.rdQLenPdf::0 2825 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 784 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 142 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 36 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 125system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 157system.physmem.bytesPerActivate::samples 717 # Bytes accessed per row activation 158system.physmem.bytesPerActivate::mean 334.192469 # Bytes accessed per row activation 159system.physmem.bytesPerActivate::gmean 180.652659 # Bytes accessed per row activation 160system.physmem.bytesPerActivate::stdev 576.534776 # Bytes accessed per row activation 161system.physmem.bytesPerActivate::64-65 257 35.84% 35.84% # Bytes accessed per row activation 162system.physmem.bytesPerActivate::128-129 120 16.74% 52.58% # Bytes accessed per row activation 163system.physmem.bytesPerActivate::192-193 71 9.90% 62.48% # Bytes accessed per row activation 164system.physmem.bytesPerActivate::256-257 49 6.83% 69.32% # Bytes accessed per row activation 165system.physmem.bytesPerActivate::320-321 19 2.65% 71.97% # Bytes accessed per row activation 166system.physmem.bytesPerActivate::384-385 26 3.63% 75.59% # Bytes accessed per row activation 167system.physmem.bytesPerActivate::448-449 20 2.79% 78.38% # Bytes accessed per row activation 168system.physmem.bytesPerActivate::512-513 17 2.37% 80.75% # Bytes accessed per row activation 169system.physmem.bytesPerActivate::576-577 17 2.37% 83.12% # Bytes accessed per row activation 170system.physmem.bytesPerActivate::640-641 40 5.58% 88.70% # Bytes accessed per row activation 171system.physmem.bytesPerActivate::704-705 17 2.37% 91.07% # Bytes accessed per row activation 172system.physmem.bytesPerActivate::768-769 6 0.84% 91.91% # Bytes accessed per row activation 173system.physmem.bytesPerActivate::832-833 6 0.84% 92.75% # Bytes accessed per row activation 174system.physmem.bytesPerActivate::896-897 8 1.12% 93.86% # Bytes accessed per row activation 175system.physmem.bytesPerActivate::960-961 6 0.84% 94.70% # Bytes accessed per row activation 176system.physmem.bytesPerActivate::1024-1025 5 0.70% 95.40% # Bytes accessed per row activation 177system.physmem.bytesPerActivate::1088-1089 4 0.56% 95.96% # Bytes accessed per row activation 178system.physmem.bytesPerActivate::1152-1153 1 0.14% 96.09% # Bytes accessed per row activation 179system.physmem.bytesPerActivate::1216-1217 2 0.28% 96.37% # Bytes accessed per row activation 180system.physmem.bytesPerActivate::1280-1281 2 0.28% 96.65% # Bytes accessed per row activation 181system.physmem.bytesPerActivate::1344-1345 2 0.28% 96.93% # Bytes accessed per row activation 182system.physmem.bytesPerActivate::1408-1409 2 0.28% 97.21% # Bytes accessed per row activation 183system.physmem.bytesPerActivate::1472-1473 1 0.14% 97.35% # Bytes accessed per row activation 184system.physmem.bytesPerActivate::1536-1537 1 0.14% 97.49% # Bytes accessed per row activation 185system.physmem.bytesPerActivate::1600-1601 1 0.14% 97.63% # Bytes accessed per row activation 186system.physmem.bytesPerActivate::1664-1665 1 0.14% 97.77% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::1728-1729 1 0.14% 97.91% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::1792-1793 2 0.28% 98.19% # Bytes accessed per row activation 189system.physmem.bytesPerActivate::1856-1857 1 0.14% 98.33% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::1984-1985 2 0.28% 98.61% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::2176-2177 1 0.14% 98.74% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::2688-2689 1 0.14% 98.88% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::2816-2817 1 0.14% 99.02% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::3008-3009 1 0.14% 99.16% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::3200-3201 1 0.14% 99.30% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::3392-3393 1 0.14% 99.44% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::3648-3649 1 0.14% 99.58% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::3712-3713 1 0.14% 99.72% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::6656-6657 1 0.14% 99.86% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::8192-8193 1 0.14% 100.00% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::total 717 # Bytes accessed per row activation 202system.physmem.totQLat 25208000 # Total ticks spent queuing 203system.physmem.totMemAccLat 100718000 # Total ticks spent from burst creation until serviced by the DRAM 204system.physmem.totBusLat 18970000 # Total ticks spent in databus transfers 205system.physmem.totBankLat 56540000 # Total ticks spent accessing banks 206system.physmem.avgQLat 6644.18 # Average queueing delay per DRAM burst 207system.physmem.avgBankLat 14902.48 # Average bank access latency per DRAM burst 208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 209system.physmem.avgMemAccLat 26546.65 # Average memory access latency per DRAM burst 210system.physmem.avgRdBW 3.27 # Average DRAM read bandwidth in MiByte/s 211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 212system.physmem.avgRdBWSys 3.27 # Average system read bandwidth in MiByte/s 213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 215system.physmem.busUtil 0.03 # Data bus utilization in percentage 216system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 218system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing 219system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 220system.physmem.readRowHits 3077 # Number of row buffer hits during reads 221system.physmem.writeRowHits 0 # Number of row buffer hits during writes 222system.physmem.readRowHitRate 81.10 # Row buffer hit rate for reads 223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 224system.physmem.avgGap 19562443.99 # Average gap between requests 225system.physmem.pageHitRate 81.10 # Row buffer hit rate, read and write combined 226system.physmem.prechargeAllPercent 0.24 # Percentage of time for which DRAM has all the banks in precharge state 227system.membus.throughput 3270712 # Throughput (bytes/s) 228system.membus.trans_dist::ReadReq 2723 # Transaction distribution 229system.membus.trans_dist::ReadResp 2722 # Transaction distribution 230system.membus.trans_dist::ReadExReq 1071 # Transaction distribution 231system.membus.trans_dist::ReadExResp 1071 # Transaction distribution 232system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7587 # Packet count per connected master and slave (bytes) 233system.membus.pkt_count::total 7587 # Packet count per connected master and slave (bytes) 234system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 242752 # Cumulative packet size per connected master and slave (bytes) 235system.membus.tot_pkt_size::total 242752 # Cumulative packet size per connected master and slave (bytes) 236system.membus.data_through_bus 242752 # Total data (bytes) 237system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 238system.membus.reqLayer0.occupancy 4681000 # Layer occupancy (ticks) 239system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 240system.membus.respLayer1.occupancy 35532250 # Layer occupancy (ticks) 241system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 242system.cpu_clk_domain.clock 500 # Clock period in ticks 243system.cpu.branchPred.lookups 94784239 # Number of BP lookups 244system.cpu.branchPred.condPredicted 74783977 # Number of conditional branches predicted 245system.cpu.branchPred.condIncorrect 6281559 # Number of conditional branches incorrect 246system.cpu.branchPred.BTBLookups 44678373 # Number of BTB lookups 247system.cpu.branchPred.BTBHits 43049971 # Number of BTB hits 248system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 249system.cpu.branchPred.BTBHitPct 96.355279 # BTB Hit Percentage 250system.cpu.branchPred.usedRAS 4356641 # Number of times the RAS was used to get a target. 251system.cpu.branchPred.RASInCorrect 88400 # Number of incorrect RAS predictions. 252system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 253system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 254system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 255system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 256system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 257system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 258system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 259system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 260system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 261system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 262system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 263system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 264system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 265system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 266system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 267system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 268system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 269system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 270system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 271system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 272system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 273system.cpu.dtb.inst_hits 0 # ITB inst hits 274system.cpu.dtb.inst_misses 0 # ITB inst misses 275system.cpu.dtb.read_hits 0 # DTB read hits 276system.cpu.dtb.read_misses 0 # DTB read misses 277system.cpu.dtb.write_hits 0 # DTB write hits 278system.cpu.dtb.write_misses 0 # DTB write misses 279system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 280system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 281system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 282system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 283system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 284system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 285system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 286system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 287system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 288system.cpu.dtb.read_accesses 0 # DTB read accesses 289system.cpu.dtb.write_accesses 0 # DTB write accesses 290system.cpu.dtb.inst_accesses 0 # ITB inst accesses 291system.cpu.dtb.hits 0 # DTB hits 292system.cpu.dtb.misses 0 # DTB misses 293system.cpu.dtb.accesses 0 # DTB accesses 294system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 295system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 296system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 297system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 298system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 299system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 300system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 301system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 302system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 303system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 304system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 305system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 306system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 307system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 308system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 309system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 310system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 311system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 312system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 313system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 314system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 315system.cpu.itb.inst_hits 0 # ITB inst hits 316system.cpu.itb.inst_misses 0 # ITB inst misses 317system.cpu.itb.read_hits 0 # DTB read hits 318system.cpu.itb.read_misses 0 # DTB read misses 319system.cpu.itb.write_hits 0 # DTB write hits 320system.cpu.itb.write_misses 0 # DTB write misses 321system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 322system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 323system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 324system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 325system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 326system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 327system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 328system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 329system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 330system.cpu.itb.read_accesses 0 # DTB read accesses 331system.cpu.itb.write_accesses 0 # DTB write accesses 332system.cpu.itb.inst_accesses 0 # ITB inst accesses 333system.cpu.itb.hits 0 # DTB hits 334system.cpu.itb.misses 0 # DTB misses 335system.cpu.itb.accesses 0 # DTB accesses 336system.cpu.workload.num_syscalls 400 # Number of system calls 337system.cpu.numCycles 148439863 # number of cpu cycles simulated 338system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 339system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 340system.cpu.fetch.icacheStallCycles 39656875 # Number of cycles fetch is stalled on an Icache miss 341system.cpu.fetch.Insts 380179667 # Number of instructions fetch has processed 342system.cpu.fetch.Branches 94784239 # Number of branches that fetch encountered 343system.cpu.fetch.predictedBranches 47406612 # Number of branches that fetch has predicted taken 344system.cpu.fetch.Cycles 80370607 # Number of cycles fetch has run and was not squashing or blocked 345system.cpu.fetch.SquashCycles 27283097 # Number of cycles fetch has spent squashing 346system.cpu.fetch.BlockedCycles 7220794 # Number of cycles fetch has spent blocked 347system.cpu.fetch.MiscStallCycles 45 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 348system.cpu.fetch.PendingTrapStallCycles 6206 # Number of stall cycles due to pending traps 349system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions 350system.cpu.fetch.IcacheWaitRetryStallCycles 50 # Number of stall cycles due to full MSHR 351system.cpu.fetch.CacheLines 36850851 # Number of cache lines fetched 352system.cpu.fetch.IcacheSquashes 1831977 # Number of outstanding Icache misses that were squashed 353system.cpu.fetch.rateDist::samples 148240291 # Number of instructions fetched each cycle (Total) 354system.cpu.fetch.rateDist::mean 2.801605 # Number of instructions fetched each cycle (Total) 355system.cpu.fetch.rateDist::stdev 3.152871 # Number of instructions fetched each cycle (Total) 356system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 357system.cpu.fetch.rateDist::0 68038529 45.90% 45.90% # Number of instructions fetched each cycle (Total) 358system.cpu.fetch.rateDist::1 5265458 3.55% 49.45% # Number of instructions fetched each cycle (Total) 359system.cpu.fetch.rateDist::2 10540663 7.11% 56.56% # Number of instructions fetched each cycle (Total) 360system.cpu.fetch.rateDist::3 10285699 6.94% 63.50% # Number of instructions fetched each cycle (Total) 361system.cpu.fetch.rateDist::4 8660453 5.84% 69.34% # Number of instructions fetched each cycle (Total) 362system.cpu.fetch.rateDist::5 6545120 4.42% 73.76% # Number of instructions fetched each cycle (Total) 363system.cpu.fetch.rateDist::6 6246377 4.21% 77.97% # Number of instructions fetched each cycle (Total) 364system.cpu.fetch.rateDist::7 8002820 5.40% 83.37% # Number of instructions fetched each cycle (Total) 365system.cpu.fetch.rateDist::8 24655172 16.63% 100.00% # Number of instructions fetched each cycle (Total) 366system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 367system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 368system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 369system.cpu.fetch.rateDist::total 148240291 # Number of instructions fetched each cycle (Total) 370system.cpu.fetch.branchRate 0.638536 # Number of branch fetches per cycle 371system.cpu.fetch.rate 2.561170 # Number of inst fetches per cycle 372system.cpu.decode.IdleCycles 45513767 # Number of cycles decode is idle 373system.cpu.decode.BlockedCycles 5886575 # Number of cycles decode is blocked 374system.cpu.decode.RunCycles 74804066 # Number of cycles decode is running 375system.cpu.decode.UnblockCycles 1203498 # Number of cycles decode is unblocking 376system.cpu.decode.SquashCycles 20832385 # Number of cycles decode is squashing 377system.cpu.decode.BranchResolved 14327909 # Number of times decode resolved a branch 378system.cpu.decode.BranchMispred 164350 # Number of times decode detected a branch misprediction 379system.cpu.decode.DecodedInsts 392779624 # Number of instructions handled by decode 380system.cpu.decode.SquashedInsts 733803 # Number of squashed instructions handled by decode 381system.cpu.rename.SquashCycles 20832385 # Number of cycles rename is squashing 382system.cpu.rename.IdleCycles 50900716 # Number of cycles rename is idle 383system.cpu.rename.BlockCycles 730751 # Number of cycles rename is blocking 384system.cpu.rename.serializeStallCycles 603183 # count of cycles rename stalled for serializing inst 385system.cpu.rename.RunCycles 70558259 # Number of cycles rename is running 386system.cpu.rename.UnblockCycles 4614997 # Number of cycles rename is unblocking 387system.cpu.rename.RenamedInsts 371307860 # Number of instructions processed by rename 388system.cpu.rename.ROBFullEvents 42 # Number of times rename has blocked due to ROB full 389system.cpu.rename.IQFullEvents 339068 # Number of times rename has blocked due to IQ full 390system.cpu.rename.LSQFullEvents 3661204 # Number of times rename has blocked due to LSQ full 391system.cpu.rename.FullRegisterEvents 25 # Number of times there has been no free registers 392system.cpu.rename.RenamedOperands 631703204 # Number of destination operands rename has renamed 393system.cpu.rename.RenameLookups 1588513521 # Number of register rename lookups that rename has made 394system.cpu.rename.int_rename_lookups 1506815662 # Number of integer rename lookups 395system.cpu.rename.fp_rename_lookups 3203425 # Number of floating rename lookups 396system.cpu.rename.CommittedMaps 298044139 # Number of HB maps that are committed 397system.cpu.rename.UndoneMaps 333659065 # Number of HB maps that are undone due to squashing 398system.cpu.rename.serializingInsts 25072 # count of serializing insts renamed 399system.cpu.rename.tempSerializingInsts 25068 # count of temporary serializing insts renamed 400system.cpu.rename.skidInsts 13010227 # count of insts added to the skid buffer 401system.cpu.memDep0.insertedLoads 43012674 # Number of loads inserted to the mem dependence unit. 402system.cpu.memDep0.insertedStores 16416368 # Number of stores inserted to the mem dependence unit. 403system.cpu.memDep0.conflictingLoads 5733538 # Number of conflicting loads. 404system.cpu.memDep0.conflictingStores 3666489 # Number of conflicting stores. 405system.cpu.iq.iqInstsAdded 329189946 # Number of instructions added to the IQ (excludes non-spec) 406system.cpu.iq.iqNonSpecInstsAdded 47154 # Number of non-speculative instructions added to the IQ 407system.cpu.iq.iqInstsIssued 249456447 # Number of instructions issued 408system.cpu.iq.iqSquashedInstsIssued 789359 # Number of squashed instructions issued 409system.cpu.iq.iqSquashedInstsExamined 139503196 # Number of squashed instructions iterated over during squash; mainly for profiling 410system.cpu.iq.iqSquashedOperandsExamined 362394637 # Number of squashed operands that are examined and possibly removed from graph 411system.cpu.iq.iqSquashedNonSpecRemoved 1938 # Number of squashed non-spec instructions that were removed 412system.cpu.iq.issued_per_cycle::samples 148240291 # Number of insts issued each cycle 413system.cpu.iq.issued_per_cycle::mean 1.682784 # Number of insts issued each cycle 414system.cpu.iq.issued_per_cycle::stdev 1.761427 # Number of insts issued each cycle 415system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 416system.cpu.iq.issued_per_cycle::0 56059626 37.82% 37.82% # Number of insts issued each cycle 417system.cpu.iq.issued_per_cycle::1 22638758 15.27% 53.09% # Number of insts issued each cycle 418system.cpu.iq.issued_per_cycle::2 24824129 16.75% 69.83% # Number of insts issued each cycle 419system.cpu.iq.issued_per_cycle::3 20343397 13.72% 83.56% # Number of insts issued each cycle 420system.cpu.iq.issued_per_cycle::4 12534810 8.46% 92.01% # Number of insts issued each cycle 421system.cpu.iq.issued_per_cycle::5 6516110 4.40% 96.41% # Number of insts issued each cycle 422system.cpu.iq.issued_per_cycle::6 4026087 2.72% 99.12% # Number of insts issued each cycle 423system.cpu.iq.issued_per_cycle::7 1116064 0.75% 99.88% # Number of insts issued each cycle 424system.cpu.iq.issued_per_cycle::8 181310 0.12% 100.00% # Number of insts issued each cycle 425system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 426system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 427system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 428system.cpu.iq.issued_per_cycle::total 148240291 # Number of insts issued each cycle 429system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 430system.cpu.iq.fu_full::IntAlu 965209 38.57% 38.57% # attempts to use FU when none available 431system.cpu.iq.fu_full::IntMult 5593 0.22% 38.79% # attempts to use FU when none available 432system.cpu.iq.fu_full::IntDiv 0 0.00% 38.79% # attempts to use FU when none available 433system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.79% # attempts to use FU when none available 434system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.79% # attempts to use FU when none available 435system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.79% # attempts to use FU when none available 436system.cpu.iq.fu_full::FloatMult 0 0.00% 38.79% # attempts to use FU when none available 437system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.79% # attempts to use FU when none available 438system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.79% # attempts to use FU when none available 439system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.79% # attempts to use FU when none available 440system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.79% # attempts to use FU when none available 441system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.79% # attempts to use FU when none available 442system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.79% # attempts to use FU when none available 443system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.79% # attempts to use FU when none available 444system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.79% # attempts to use FU when none available 445system.cpu.iq.fu_full::SimdMult 0 0.00% 38.79% # attempts to use FU when none available 446system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.79% # attempts to use FU when none available 447system.cpu.iq.fu_full::SimdShift 0 0.00% 38.79% # attempts to use FU when none available 448system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.79% # attempts to use FU when none available 449system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.79% # attempts to use FU when none available 450system.cpu.iq.fu_full::SimdFloatAdd 101 0.00% 38.79% # attempts to use FU when none available 451system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.79% # attempts to use FU when none available 452system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.79% # attempts to use FU when none available 453system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.79% # attempts to use FU when none available 454system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.79% # attempts to use FU when none available 455system.cpu.iq.fu_full::SimdFloatMisc 48 0.00% 38.80% # attempts to use FU when none available 456system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.80% # attempts to use FU when none available 457system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.80% # attempts to use FU when none available 458system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.80% # attempts to use FU when none available 459system.cpu.iq.fu_full::MemRead 1158969 46.31% 85.11% # attempts to use FU when none available 460system.cpu.iq.fu_full::MemWrite 372730 14.89% 100.00% # attempts to use FU when none available 461system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 462system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 463system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 464system.cpu.iq.FU_type_0::IntAlu 194899827 78.13% 78.13% # Type of FU issued 465system.cpu.iq.FU_type_0::IntMult 979613 0.39% 78.52% # Type of FU issued 466system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.52% # Type of FU issued 467system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.52% # Type of FU issued 468system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.52% # Type of FU issued 469system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.52% # Type of FU issued 470system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.52% # Type of FU issued 471system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.52% # Type of FU issued 472system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.52% # Type of FU issued 473system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.52% # Type of FU issued 474system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.52% # Type of FU issued 475system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.52% # Type of FU issued 476system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.52% # Type of FU issued 477system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.52% # Type of FU issued 478system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.52% # Type of FU issued 479system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.52% # Type of FU issued 480system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.52% # Type of FU issued 481system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.52% # Type of FU issued 482system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.52% # Type of FU issued 483system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.52% # Type of FU issued 484system.cpu.iq.FU_type_0::SimdFloatAdd 33082 0.01% 78.54% # Type of FU issued 485system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.54% # Type of FU issued 486system.cpu.iq.FU_type_0::SimdFloatCmp 164367 0.07% 78.60% # Type of FU issued 487system.cpu.iq.FU_type_0::SimdFloatCvt 255141 0.10% 78.70% # Type of FU issued 488system.cpu.iq.FU_type_0::SimdFloatDiv 76420 0.03% 78.73% # Type of FU issued 489system.cpu.iq.FU_type_0::SimdFloatMisc 466123 0.19% 78.92% # Type of FU issued 490system.cpu.iq.FU_type_0::SimdFloatMult 206380 0.08% 79.00% # Type of FU issued 491system.cpu.iq.FU_type_0::SimdFloatMultAcc 71866 0.03% 79.03% # Type of FU issued 492system.cpu.iq.FU_type_0::SimdFloatSqrt 321 0.00% 79.03% # Type of FU issued 493system.cpu.iq.FU_type_0::MemRead 38355265 15.38% 94.41% # Type of FU issued 494system.cpu.iq.FU_type_0::MemWrite 13948042 5.59% 100.00% # Type of FU issued 495system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 496system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 497system.cpu.iq.FU_type_0::total 249456447 # Type of FU issued 498system.cpu.iq.rate 1.680522 # Inst issue rate 499system.cpu.iq.fu_busy_cnt 2502650 # FU busy when requested 500system.cpu.iq.fu_busy_rate 0.010032 # FU busy rate (busy events/executed inst) 501system.cpu.iq.int_inst_queue_reads 646705187 # Number of integer instruction queue reads 502system.cpu.iq.int_inst_queue_writes 466563017 # Number of integer instruction queue writes 503system.cpu.iq.int_inst_queue_wakeup_accesses 237885267 # Number of integer instruction queue wakeup accesses 504system.cpu.iq.fp_inst_queue_reads 3740007 # Number of floating instruction queue reads 505system.cpu.iq.fp_inst_queue_writes 2195697 # Number of floating instruction queue writes 506system.cpu.iq.fp_inst_queue_wakeup_accesses 1842613 # Number of floating instruction queue wakeup accesses 507system.cpu.iq.int_alu_accesses 250082678 # Number of integer alu accesses 508system.cpu.iq.fp_alu_accesses 1876419 # Number of floating point alu accesses 509system.cpu.iew.lsq.thread0.forwLoads 2013206 # Number of loads that had data forwarded from stores 510system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 511system.cpu.iew.lsq.thread0.squashedLoads 13163190 # Number of loads squashed 512system.cpu.iew.lsq.thread0.ignoredResponses 11604 # Number of memory responses ignored because the instruction is squashed 513system.cpu.iew.lsq.thread0.memOrderViolation 18881 # Number of memory ordering violations 514system.cpu.iew.lsq.thread0.squashedStores 3771734 # Number of stores squashed 515system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 516system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 517system.cpu.iew.lsq.thread0.rescheduledLoads 18 # Number of loads that were rescheduled 518system.cpu.iew.lsq.thread0.cacheBlocked 107 # Number of times an access to memory failed due to the cache being blocked 519system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 520system.cpu.iew.iewSquashCycles 20832385 # Number of cycles IEW is squashing 521system.cpu.iew.iewBlockCycles 18544 # Number of cycles IEW is blocking 522system.cpu.iew.iewUnblockCycles 886 # Number of cycles IEW is unblocking 523system.cpu.iew.iewDispatchedInsts 329254297 # Number of instructions dispatched to IQ 524system.cpu.iew.iewDispSquashedInsts 785292 # Number of squashed instructions skipped by dispatch 525system.cpu.iew.iewDispLoadInsts 43012674 # Number of dispatched load instructions 526system.cpu.iew.iewDispStoreInsts 16416368 # Number of dispatched store instructions 527system.cpu.iew.iewDispNonSpecInsts 24746 # Number of dispatched non-speculative instructions 528system.cpu.iew.iewIQFullEvents 181 # Number of times the IQ has become full, causing a stall 529system.cpu.iew.iewLSQFullEvents 276 # Number of times the LSQ has become full, causing a stall 530system.cpu.iew.memOrderViolationEvents 18881 # Number of memory order violations 531system.cpu.iew.predictedTakenIncorrect 3889950 # Number of branches that were predicted taken incorrectly 532system.cpu.iew.predictedNotTakenIncorrect 3760088 # Number of branches that were predicted not taken incorrectly 533system.cpu.iew.branchMispredicts 7650038 # Number of branch mispredicts detected at execute 534system.cpu.iew.iewExecutedInsts 242960344 # Number of executed instructions 535system.cpu.iew.iewExecLoadInsts 36851914 # Number of load instructions executed 536system.cpu.iew.iewExecSquashedInsts 6496103 # Number of squashed instructions skipped in execute 537system.cpu.iew.exec_swp 0 # number of swp insts executed 538system.cpu.iew.exec_nop 17197 # number of nop insts executed 539system.cpu.iew.exec_refs 50500351 # number of memory reference insts executed 540system.cpu.iew.exec_branches 53426054 # Number of branches executed 541system.cpu.iew.exec_stores 13648437 # Number of stores executed 542system.cpu.iew.exec_rate 1.636759 # Inst execution rate 543system.cpu.iew.wb_sent 240785488 # cumulative count of insts sent to commit 544system.cpu.iew.wb_count 239727880 # cumulative count of insts written-back 545system.cpu.iew.wb_producers 148473973 # num instructions producing a value 546system.cpu.iew.wb_consumers 267261246 # num instructions consuming a value 547system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 548system.cpu.iew.wb_rate 1.614983 # insts written-back per cycle 549system.cpu.iew.wb_fanout 0.555539 # average fanout of values written-back 550system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 551system.cpu.commit.commitSquashedInsts 140583409 # The number of squashed insts skipped by commit 552system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards 553system.cpu.commit.branchMispredicts 6128231 # The number of times a branch was mispredicted 554system.cpu.commit.committed_per_cycle::samples 127407906 # Number of insts commited each cycle 555system.cpu.commit.committed_per_cycle::mean 1.480841 # Number of insts commited each cycle 556system.cpu.commit.committed_per_cycle::stdev 2.185453 # Number of insts commited each cycle 557system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 558system.cpu.commit.committed_per_cycle::0 57701601 45.29% 45.29% # Number of insts commited each cycle 559system.cpu.commit.committed_per_cycle::1 31696921 24.88% 70.17% # Number of insts commited each cycle 560system.cpu.commit.committed_per_cycle::2 13777775 10.81% 80.98% # Number of insts commited each cycle 561system.cpu.commit.committed_per_cycle::3 7640604 6.00% 86.98% # Number of insts commited each cycle 562system.cpu.commit.committed_per_cycle::4 4387783 3.44% 90.42% # Number of insts commited each cycle 563system.cpu.commit.committed_per_cycle::5 1321955 1.04% 91.46% # Number of insts commited each cycle 564system.cpu.commit.committed_per_cycle::6 1703214 1.34% 92.80% # Number of insts commited each cycle 565system.cpu.commit.committed_per_cycle::7 1308007 1.03% 93.82% # Number of insts commited each cycle 566system.cpu.commit.committed_per_cycle::8 7870046 6.18% 100.00% # Number of insts commited each cycle 567system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 568system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 569system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 570system.cpu.commit.committed_per_cycle::total 127407906 # Number of insts commited each cycle 571system.cpu.commit.committedInsts 172317409 # Number of instructions committed 572system.cpu.commit.committedOps 188670891 # Number of ops (including micro ops) committed 573system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 574system.cpu.commit.refs 42494118 # Number of memory references committed 575system.cpu.commit.loads 29849484 # Number of loads committed 576system.cpu.commit.membars 22408 # Number of memory barriers committed 577system.cpu.commit.branches 40300311 # Number of branches committed 578system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. 579system.cpu.commit.int_insts 150106217 # Number of committed integer instructions. 580system.cpu.commit.function_calls 1848934 # Number of function calls committed. 581system.cpu.commit.bw_lim_events 7870046 # number cycles where commit BW limit reached 582system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 583system.cpu.rob.rob_reads 448786959 # The number of ROB reads 584system.cpu.rob.rob_writes 679450685 # The number of ROB writes 585system.cpu.timesIdled 2806 # Number of times that the entire CPU went into an idle state and unscheduled itself 586system.cpu.idleCycles 199572 # Total number of cycles that the CPU has spent unscheduled due to idling 587system.cpu.committedInsts 172303021 # Number of Instructions Simulated 588system.cpu.committedOps 188656503 # Number of Ops (including micro ops) Simulated 589system.cpu.committedInsts_total 172303021 # Number of Instructions Simulated 590system.cpu.cpi 0.861505 # CPI: Cycles Per Instruction 591system.cpu.cpi_total 0.861505 # CPI: Total CPI of All Threads 592system.cpu.ipc 1.160760 # IPC: Instructions Per Cycle 593system.cpu.ipc_total 1.160760 # IPC: Total IPC of All Threads 594system.cpu.int_regfile_reads 1079416198 # number of integer regfile reads 595system.cpu.int_regfile_writes 384871537 # number of integer regfile writes 596system.cpu.fp_regfile_reads 2913086 # number of floating regfile reads 597system.cpu.fp_regfile_writes 2499105 # number of floating regfile writes 598system.cpu.misc_regfile_reads 64870078 # number of misc regfile reads 599system.cpu.misc_regfile_writes 820036 # number of misc regfile writes 600system.cpu.toL2Bus.throughput 5170363 # Throughput (bytes/s) 601system.cpu.toL2Bus.trans_dist::ReadReq 4900 # Transaction distribution 602system.cpu.toL2Bus.trans_dist::ReadResp 4899 # Transaction distribution 603system.cpu.toL2Bus.trans_dist::Writeback 18 # Transaction distribution 604system.cpu.toL2Bus.trans_dist::ReadExReq 1079 # Transaction distribution 605system.cpu.toL2Bus.trans_dist::ReadExResp 1079 # Transaction distribution 606system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8253 # Packet count per connected master and slave (bytes) 607system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3722 # Packet count per connected master and slave (bytes) 608system.cpu.toL2Bus.pkt_count::total 11975 # Packet count per connected master and slave (bytes) 609system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 264064 # Cumulative packet size per connected master and slave (bytes) 610system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119680 # Cumulative packet size per connected master and slave (bytes) 611system.cpu.toL2Bus.tot_pkt_size::total 383744 # Cumulative packet size per connected master and slave (bytes) 612system.cpu.toL2Bus.data_through_bus 383744 # Total data (bytes) 613system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 614system.cpu.toL2Bus.reqLayer0.occupancy 3016500 # Layer occupancy (ticks) 615system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 616system.cpu.toL2Bus.respLayer0.occupancy 6553746 # Layer occupancy (ticks) 617system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 618system.cpu.toL2Bus.respLayer1.occupancy 3047989 # Layer occupancy (ticks) 619system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 620system.cpu.icache.tags.replacements 2395 # number of replacements 621system.cpu.icache.tags.tagsinuse 1347.740461 # Cycle average of tags in use 622system.cpu.icache.tags.total_refs 36845513 # Total number of references to valid blocks. 623system.cpu.icache.tags.sampled_refs 4126 # Sample count of references to valid blocks. 624system.cpu.icache.tags.avg_refs 8930.080708 # Average number of references to valid blocks. 625system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 626system.cpu.icache.tags.occ_blocks::cpu.inst 1347.740461 # Average occupied blocks per requestor 627system.cpu.icache.tags.occ_percent::cpu.inst 0.658076 # Average percentage of cache occupancy 628system.cpu.icache.tags.occ_percent::total 0.658076 # Average percentage of cache occupancy 629system.cpu.icache.tags.occ_task_id_blocks::1024 1731 # Occupied blocks per task id 630system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id 631system.cpu.icache.tags.age_task_id_blocks_1024::1 82 # Occupied blocks per task id 632system.cpu.icache.tags.age_task_id_blocks_1024::2 544 # Occupied blocks per task id 633system.cpu.icache.tags.age_task_id_blocks_1024::3 27 # Occupied blocks per task id 634system.cpu.icache.tags.age_task_id_blocks_1024::4 1037 # Occupied blocks per task id 635system.cpu.icache.tags.occ_task_id_percent::1024 0.845215 # Percentage of cache occupancy per task id 636system.cpu.icache.tags.tag_accesses 73705828 # Number of tag accesses 637system.cpu.icache.tags.data_accesses 73705828 # Number of data accesses 638system.cpu.icache.ReadReq_hits::cpu.inst 36845513 # number of ReadReq hits 639system.cpu.icache.ReadReq_hits::total 36845513 # number of ReadReq hits 640system.cpu.icache.demand_hits::cpu.inst 36845513 # number of demand (read+write) hits 641system.cpu.icache.demand_hits::total 36845513 # number of demand (read+write) hits 642system.cpu.icache.overall_hits::cpu.inst 36845513 # number of overall hits 643system.cpu.icache.overall_hits::total 36845513 # number of overall hits 644system.cpu.icache.ReadReq_misses::cpu.inst 5338 # number of ReadReq misses 645system.cpu.icache.ReadReq_misses::total 5338 # number of ReadReq misses 646system.cpu.icache.demand_misses::cpu.inst 5338 # number of demand (read+write) misses 647system.cpu.icache.demand_misses::total 5338 # number of demand (read+write) misses 648system.cpu.icache.overall_misses::cpu.inst 5338 # number of overall misses 649system.cpu.icache.overall_misses::total 5338 # number of overall misses 650system.cpu.icache.ReadReq_miss_latency::cpu.inst 225943745 # number of ReadReq miss cycles 651system.cpu.icache.ReadReq_miss_latency::total 225943745 # number of ReadReq miss cycles 652system.cpu.icache.demand_miss_latency::cpu.inst 225943745 # number of demand (read+write) miss cycles 653system.cpu.icache.demand_miss_latency::total 225943745 # number of demand (read+write) miss cycles 654system.cpu.icache.overall_miss_latency::cpu.inst 225943745 # number of overall miss cycles 655system.cpu.icache.overall_miss_latency::total 225943745 # number of overall miss cycles 656system.cpu.icache.ReadReq_accesses::cpu.inst 36850851 # number of ReadReq accesses(hits+misses) 657system.cpu.icache.ReadReq_accesses::total 36850851 # number of ReadReq accesses(hits+misses) 658system.cpu.icache.demand_accesses::cpu.inst 36850851 # number of demand (read+write) accesses 659system.cpu.icache.demand_accesses::total 36850851 # number of demand (read+write) accesses 660system.cpu.icache.overall_accesses::cpu.inst 36850851 # number of overall (read+write) accesses 661system.cpu.icache.overall_accesses::total 36850851 # number of overall (read+write) accesses 662system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000145 # miss rate for ReadReq accesses 663system.cpu.icache.ReadReq_miss_rate::total 0.000145 # miss rate for ReadReq accesses 664system.cpu.icache.demand_miss_rate::cpu.inst 0.000145 # miss rate for demand accesses 665system.cpu.icache.demand_miss_rate::total 0.000145 # miss rate for demand accesses 666system.cpu.icache.overall_miss_rate::cpu.inst 0.000145 # miss rate for overall accesses 667system.cpu.icache.overall_miss_rate::total 0.000145 # miss rate for overall accesses 668system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42327.415699 # average ReadReq miss latency 669system.cpu.icache.ReadReq_avg_miss_latency::total 42327.415699 # average ReadReq miss latency 670system.cpu.icache.demand_avg_miss_latency::cpu.inst 42327.415699 # average overall miss latency 671system.cpu.icache.demand_avg_miss_latency::total 42327.415699 # average overall miss latency 672system.cpu.icache.overall_avg_miss_latency::cpu.inst 42327.415699 # average overall miss latency 673system.cpu.icache.overall_avg_miss_latency::total 42327.415699 # average overall miss latency 674system.cpu.icache.blocked_cycles::no_mshrs 1128 # number of cycles access was blocked 675system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 676system.cpu.icache.blocked::no_mshrs 19 # number of cycles access was blocked 677system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 678system.cpu.icache.avg_blocked_cycles::no_mshrs 59.368421 # average number of cycles each access was blocked 679system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 680system.cpu.icache.fast_writes 0 # number of fast writes performed 681system.cpu.icache.cache_copies 0 # number of cache copies performed 682system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1211 # number of ReadReq MSHR hits 683system.cpu.icache.ReadReq_mshr_hits::total 1211 # number of ReadReq MSHR hits 684system.cpu.icache.demand_mshr_hits::cpu.inst 1211 # number of demand (read+write) MSHR hits 685system.cpu.icache.demand_mshr_hits::total 1211 # number of demand (read+write) MSHR hits 686system.cpu.icache.overall_mshr_hits::cpu.inst 1211 # number of overall MSHR hits 687system.cpu.icache.overall_mshr_hits::total 1211 # number of overall MSHR hits 688system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4127 # number of ReadReq MSHR misses 689system.cpu.icache.ReadReq_mshr_misses::total 4127 # number of ReadReq MSHR misses 690system.cpu.icache.demand_mshr_misses::cpu.inst 4127 # number of demand (read+write) MSHR misses 691system.cpu.icache.demand_mshr_misses::total 4127 # number of demand (read+write) MSHR misses 692system.cpu.icache.overall_mshr_misses::cpu.inst 4127 # number of overall MSHR misses 693system.cpu.icache.overall_mshr_misses::total 4127 # number of overall MSHR misses 694system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 168102254 # number of ReadReq MSHR miss cycles 695system.cpu.icache.ReadReq_mshr_miss_latency::total 168102254 # number of ReadReq MSHR miss cycles 696system.cpu.icache.demand_mshr_miss_latency::cpu.inst 168102254 # number of demand (read+write) MSHR miss cycles 697system.cpu.icache.demand_mshr_miss_latency::total 168102254 # number of demand (read+write) MSHR miss cycles 698system.cpu.icache.overall_mshr_miss_latency::cpu.inst 168102254 # number of overall MSHR miss cycles 699system.cpu.icache.overall_mshr_miss_latency::total 168102254 # number of overall MSHR miss cycles 700system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for ReadReq accesses 701system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000112 # mshr miss rate for ReadReq accesses 702system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for demand accesses 703system.cpu.icache.demand_mshr_miss_rate::total 0.000112 # mshr miss rate for demand accesses 704system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for overall accesses 705system.cpu.icache.overall_mshr_miss_rate::total 0.000112 # mshr miss rate for overall accesses 706system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40732.312576 # average ReadReq mshr miss latency 707system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40732.312576 # average ReadReq mshr miss latency 708system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40732.312576 # average overall mshr miss latency 709system.cpu.icache.demand_avg_mshr_miss_latency::total 40732.312576 # average overall mshr miss latency 710system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40732.312576 # average overall mshr miss latency 711system.cpu.icache.overall_avg_mshr_miss_latency::total 40732.312576 # average overall mshr miss latency 712system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 713system.cpu.l2cache.tags.replacements 0 # number of replacements 714system.cpu.l2cache.tags.tagsinuse 1967.449595 # Cycle average of tags in use 715system.cpu.l2cache.tags.total_refs 2163 # Total number of references to valid blocks. 716system.cpu.l2cache.tags.sampled_refs 2732 # Sample count of references to valid blocks. 717system.cpu.l2cache.tags.avg_refs 0.791728 # Average number of references to valid blocks. 718system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 719system.cpu.l2cache.tags.occ_blocks::writebacks 4.994097 # Average occupied blocks per requestor 720system.cpu.l2cache.tags.occ_blocks::cpu.inst 1425.569547 # Average occupied blocks per requestor 721system.cpu.l2cache.tags.occ_blocks::cpu.data 536.885951 # Average occupied blocks per requestor 722system.cpu.l2cache.tags.occ_percent::writebacks 0.000152 # Average percentage of cache occupancy 723system.cpu.l2cache.tags.occ_percent::cpu.inst 0.043505 # Average percentage of cache occupancy 724system.cpu.l2cache.tags.occ_percent::cpu.data 0.016384 # Average percentage of cache occupancy 725system.cpu.l2cache.tags.occ_percent::total 0.060042 # Average percentage of cache occupancy 726system.cpu.l2cache.tags.occ_task_id_blocks::1024 2732 # Occupied blocks per task id 727system.cpu.l2cache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id 728system.cpu.l2cache.tags.age_task_id_blocks_1024::1 91 # Occupied blocks per task id 729system.cpu.l2cache.tags.age_task_id_blocks_1024::2 604 # Occupied blocks per task id 730system.cpu.l2cache.tags.age_task_id_blocks_1024::3 28 # Occupied blocks per task id 731system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1970 # Occupied blocks per task id 732system.cpu.l2cache.tags.occ_task_id_percent::1024 0.083374 # Percentage of cache occupancy per task id 733system.cpu.l2cache.tags.tag_accesses 51787 # Number of tag accesses 734system.cpu.l2cache.tags.data_accesses 51787 # Number of data accesses 735system.cpu.l2cache.ReadReq_hits::cpu.inst 2074 # number of ReadReq hits 736system.cpu.l2cache.ReadReq_hits::cpu.data 88 # number of ReadReq hits 737system.cpu.l2cache.ReadReq_hits::total 2162 # number of ReadReq hits 738system.cpu.l2cache.Writeback_hits::writebacks 18 # number of Writeback hits 739system.cpu.l2cache.Writeback_hits::total 18 # number of Writeback hits 740system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits 741system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits 742system.cpu.l2cache.demand_hits::cpu.inst 2074 # number of demand (read+write) hits 743system.cpu.l2cache.demand_hits::cpu.data 96 # number of demand (read+write) hits 744system.cpu.l2cache.demand_hits::total 2170 # number of demand (read+write) hits 745system.cpu.l2cache.overall_hits::cpu.inst 2074 # number of overall hits 746system.cpu.l2cache.overall_hits::cpu.data 96 # number of overall hits 747system.cpu.l2cache.overall_hits::total 2170 # number of overall hits 748system.cpu.l2cache.ReadReq_misses::cpu.inst 2053 # number of ReadReq misses 749system.cpu.l2cache.ReadReq_misses::cpu.data 685 # number of ReadReq misses 750system.cpu.l2cache.ReadReq_misses::total 2738 # number of ReadReq misses 751system.cpu.l2cache.ReadExReq_misses::cpu.data 1071 # number of ReadExReq misses 752system.cpu.l2cache.ReadExReq_misses::total 1071 # number of ReadExReq misses 753system.cpu.l2cache.demand_misses::cpu.inst 2053 # number of demand (read+write) misses 754system.cpu.l2cache.demand_misses::cpu.data 1756 # number of demand (read+write) misses 755system.cpu.l2cache.demand_misses::total 3809 # number of demand (read+write) misses 756system.cpu.l2cache.overall_misses::cpu.inst 2053 # number of overall misses 757system.cpu.l2cache.overall_misses::cpu.data 1756 # number of overall misses 758system.cpu.l2cache.overall_misses::total 3809 # number of overall misses 759system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 143228250 # number of ReadReq miss cycles 760system.cpu.l2cache.ReadReq_miss_latency::cpu.data 51387250 # number of ReadReq miss cycles 761system.cpu.l2cache.ReadReq_miss_latency::total 194615500 # number of ReadReq miss cycles 762system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 72292250 # number of ReadExReq miss cycles 763system.cpu.l2cache.ReadExReq_miss_latency::total 72292250 # number of ReadExReq miss cycles 764system.cpu.l2cache.demand_miss_latency::cpu.inst 143228250 # number of demand (read+write) miss cycles 765system.cpu.l2cache.demand_miss_latency::cpu.data 123679500 # number of demand (read+write) miss cycles 766system.cpu.l2cache.demand_miss_latency::total 266907750 # number of demand (read+write) miss cycles 767system.cpu.l2cache.overall_miss_latency::cpu.inst 143228250 # number of overall miss cycles 768system.cpu.l2cache.overall_miss_latency::cpu.data 123679500 # number of overall miss cycles 769system.cpu.l2cache.overall_miss_latency::total 266907750 # number of overall miss cycles 770system.cpu.l2cache.ReadReq_accesses::cpu.inst 4127 # number of ReadReq accesses(hits+misses) 771system.cpu.l2cache.ReadReq_accesses::cpu.data 773 # number of ReadReq accesses(hits+misses) 772system.cpu.l2cache.ReadReq_accesses::total 4900 # number of ReadReq accesses(hits+misses) 773system.cpu.l2cache.Writeback_accesses::writebacks 18 # number of Writeback accesses(hits+misses) 774system.cpu.l2cache.Writeback_accesses::total 18 # number of Writeback accesses(hits+misses) 775system.cpu.l2cache.ReadExReq_accesses::cpu.data 1079 # number of ReadExReq accesses(hits+misses) 776system.cpu.l2cache.ReadExReq_accesses::total 1079 # number of ReadExReq accesses(hits+misses) 777system.cpu.l2cache.demand_accesses::cpu.inst 4127 # number of demand (read+write) accesses 778system.cpu.l2cache.demand_accesses::cpu.data 1852 # number of demand (read+write) accesses 779system.cpu.l2cache.demand_accesses::total 5979 # number of demand (read+write) accesses 780system.cpu.l2cache.overall_accesses::cpu.inst 4127 # number of overall (read+write) accesses 781system.cpu.l2cache.overall_accesses::cpu.data 1852 # number of overall (read+write) accesses 782system.cpu.l2cache.overall_accesses::total 5979 # number of overall (read+write) accesses 783system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.497456 # miss rate for ReadReq accesses 784system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.886158 # miss rate for ReadReq accesses 785system.cpu.l2cache.ReadReq_miss_rate::total 0.558776 # miss rate for ReadReq accesses 786system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992586 # miss rate for ReadExReq accesses 787system.cpu.l2cache.ReadExReq_miss_rate::total 0.992586 # miss rate for ReadExReq accesses 788system.cpu.l2cache.demand_miss_rate::cpu.inst 0.497456 # miss rate for demand accesses 789system.cpu.l2cache.demand_miss_rate::cpu.data 0.948164 # miss rate for demand accesses 790system.cpu.l2cache.demand_miss_rate::total 0.637063 # miss rate for demand accesses 791system.cpu.l2cache.overall_miss_rate::cpu.inst 0.497456 # miss rate for overall accesses 792system.cpu.l2cache.overall_miss_rate::cpu.data 0.948164 # miss rate for overall accesses 793system.cpu.l2cache.overall_miss_rate::total 0.637063 # miss rate for overall accesses 794system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69765.343400 # average ReadReq miss latency 795system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75017.883212 # average ReadReq miss latency 796system.cpu.l2cache.ReadReq_avg_miss_latency::total 71079.437546 # average ReadReq miss latency 797system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67499.766573 # average ReadExReq miss latency 798system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67499.766573 # average ReadExReq miss latency 799system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69765.343400 # average overall miss latency 800system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70432.517084 # average overall miss latency 801system.cpu.l2cache.demand_avg_miss_latency::total 70072.919401 # average overall miss latency 802system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69765.343400 # average overall miss latency 803system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70432.517084 # average overall miss latency 804system.cpu.l2cache.overall_avg_miss_latency::total 70072.919401 # average overall miss latency 805system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 806system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 807system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 808system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 809system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 810system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 811system.cpu.l2cache.fast_writes 0 # number of fast writes performed 812system.cpu.l2cache.cache_copies 0 # number of cache copies performed 813system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits 814system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 11 # number of ReadReq MSHR hits 815system.cpu.l2cache.ReadReq_mshr_hits::total 15 # number of ReadReq MSHR hits 816system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits 817system.cpu.l2cache.demand_mshr_hits::cpu.data 11 # number of demand (read+write) MSHR hits 818system.cpu.l2cache.demand_mshr_hits::total 15 # number of demand (read+write) MSHR hits 819system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits 820system.cpu.l2cache.overall_mshr_hits::cpu.data 11 # number of overall MSHR hits 821system.cpu.l2cache.overall_mshr_hits::total 15 # number of overall MSHR hits 822system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2049 # number of ReadReq MSHR misses 823system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 674 # number of ReadReq MSHR misses 824system.cpu.l2cache.ReadReq_mshr_misses::total 2723 # number of ReadReq MSHR misses 825system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1071 # number of ReadExReq MSHR misses 826system.cpu.l2cache.ReadExReq_mshr_misses::total 1071 # number of ReadExReq MSHR misses 827system.cpu.l2cache.demand_mshr_misses::cpu.inst 2049 # number of demand (read+write) MSHR misses 828system.cpu.l2cache.demand_mshr_misses::cpu.data 1745 # number of demand (read+write) MSHR misses 829system.cpu.l2cache.demand_mshr_misses::total 3794 # number of demand (read+write) MSHR misses 830system.cpu.l2cache.overall_mshr_misses::cpu.inst 2049 # number of overall MSHR misses 831system.cpu.l2cache.overall_mshr_misses::cpu.data 1745 # number of overall MSHR misses 832system.cpu.l2cache.overall_mshr_misses::total 3794 # number of overall MSHR misses 833system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 117257250 # number of ReadReq MSHR miss cycles 834system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 42300250 # number of ReadReq MSHR miss cycles 835system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159557500 # number of ReadReq MSHR miss cycles 836system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 58841750 # number of ReadExReq MSHR miss cycles 837system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 58841750 # number of ReadExReq MSHR miss cycles 838system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 117257250 # number of demand (read+write) MSHR miss cycles 839system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 101142000 # number of demand (read+write) MSHR miss cycles 840system.cpu.l2cache.demand_mshr_miss_latency::total 218399250 # number of demand (read+write) MSHR miss cycles 841system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 117257250 # number of overall MSHR miss cycles 842system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 101142000 # number of overall MSHR miss cycles 843system.cpu.l2cache.overall_mshr_miss_latency::total 218399250 # number of overall MSHR miss cycles 844system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.496487 # mshr miss rate for ReadReq accesses 845system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.871928 # mshr miss rate for ReadReq accesses 846system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.555714 # mshr miss rate for ReadReq accesses 847system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992586 # mshr miss rate for ReadExReq accesses 848system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992586 # mshr miss rate for ReadExReq accesses 849system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.496487 # mshr miss rate for demand accesses 850system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.942225 # mshr miss rate for demand accesses 851system.cpu.l2cache.demand_mshr_miss_rate::total 0.634554 # mshr miss rate for demand accesses 852system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.496487 # mshr miss rate for overall accesses 853system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.942225 # mshr miss rate for overall accesses 854system.cpu.l2cache.overall_mshr_miss_rate::total 0.634554 # mshr miss rate for overall accesses 855system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57226.573939 # average ReadReq mshr miss latency 856system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62760.014837 # average ReadReq mshr miss latency 857system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58596.217407 # average ReadReq mshr miss latency 858system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54940.943044 # average ReadExReq mshr miss latency 859system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54940.943044 # average ReadExReq mshr miss latency 860system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57226.573939 # average overall mshr miss latency 861system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57961.031519 # average overall mshr miss latency 862system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57564.377965 # average overall mshr miss latency 863system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57226.573939 # average overall mshr miss latency 864system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57961.031519 # average overall mshr miss latency 865system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57564.377965 # average overall mshr miss latency 866system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 867system.cpu.dcache.tags.replacements 57 # number of replacements 868system.cpu.dcache.tags.tagsinuse 1406.103051 # Cycle average of tags in use 869system.cpu.dcache.tags.total_refs 46786126 # Total number of references to valid blocks. 870system.cpu.dcache.tags.sampled_refs 1852 # Sample count of references to valid blocks. 871system.cpu.dcache.tags.avg_refs 25262.487041 # Average number of references to valid blocks. 872system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 873system.cpu.dcache.tags.occ_blocks::cpu.data 1406.103051 # Average occupied blocks per requestor 874system.cpu.dcache.tags.occ_percent::cpu.data 0.343287 # Average percentage of cache occupancy 875system.cpu.dcache.tags.occ_percent::total 0.343287 # Average percentage of cache occupancy 876system.cpu.dcache.tags.occ_task_id_blocks::1024 1795 # Occupied blocks per task id 877system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id 878system.cpu.dcache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id 879system.cpu.dcache.tags.age_task_id_blocks_1024::2 353 # Occupied blocks per task id 880system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 881system.cpu.dcache.tags.age_task_id_blocks_1024::4 1378 # Occupied blocks per task id 882system.cpu.dcache.tags.occ_task_id_percent::1024 0.438232 # Percentage of cache occupancy per task id 883system.cpu.dcache.tags.tag_accesses 93593354 # Number of tag accesses 884system.cpu.dcache.tags.data_accesses 93593354 # Number of data accesses 885system.cpu.dcache.ReadReq_hits::cpu.data 34384681 # number of ReadReq hits 886system.cpu.dcache.ReadReq_hits::total 34384681 # number of ReadReq hits 887system.cpu.dcache.WriteReq_hits::cpu.data 12356564 # number of WriteReq hits 888system.cpu.dcache.WriteReq_hits::total 12356564 # number of WriteReq hits 889system.cpu.dcache.LoadLockedReq_hits::cpu.data 22474 # number of LoadLockedReq hits 890system.cpu.dcache.LoadLockedReq_hits::total 22474 # number of LoadLockedReq hits 891system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits 892system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits 893system.cpu.dcache.demand_hits::cpu.data 46741245 # number of demand (read+write) hits 894system.cpu.dcache.demand_hits::total 46741245 # number of demand (read+write) hits 895system.cpu.dcache.overall_hits::cpu.data 46741245 # number of overall hits 896system.cpu.dcache.overall_hits::total 46741245 # number of overall hits 897system.cpu.dcache.ReadReq_misses::cpu.data 1900 # number of ReadReq misses 898system.cpu.dcache.ReadReq_misses::total 1900 # number of ReadReq misses 899system.cpu.dcache.WriteReq_misses::cpu.data 7723 # number of WriteReq misses 900system.cpu.dcache.WriteReq_misses::total 7723 # number of WriteReq misses 901system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 902system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 903system.cpu.dcache.demand_misses::cpu.data 9623 # number of demand (read+write) misses 904system.cpu.dcache.demand_misses::total 9623 # number of demand (read+write) misses 905system.cpu.dcache.overall_misses::cpu.data 9623 # number of overall misses 906system.cpu.dcache.overall_misses::total 9623 # number of overall misses 907system.cpu.dcache.ReadReq_miss_latency::cpu.data 121712227 # number of ReadReq miss cycles 908system.cpu.dcache.ReadReq_miss_latency::total 121712227 # number of ReadReq miss cycles 909system.cpu.dcache.WriteReq_miss_latency::cpu.data 465623746 # number of WriteReq miss cycles 910system.cpu.dcache.WriteReq_miss_latency::total 465623746 # number of WriteReq miss cycles 911system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 142500 # number of LoadLockedReq miss cycles 912system.cpu.dcache.LoadLockedReq_miss_latency::total 142500 # number of LoadLockedReq miss cycles 913system.cpu.dcache.demand_miss_latency::cpu.data 587335973 # number of demand (read+write) miss cycles 914system.cpu.dcache.demand_miss_latency::total 587335973 # number of demand (read+write) miss cycles 915system.cpu.dcache.overall_miss_latency::cpu.data 587335973 # number of overall miss cycles 916system.cpu.dcache.overall_miss_latency::total 587335973 # number of overall miss cycles 917system.cpu.dcache.ReadReq_accesses::cpu.data 34386581 # number of ReadReq accesses(hits+misses) 918system.cpu.dcache.ReadReq_accesses::total 34386581 # number of ReadReq accesses(hits+misses) 919system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) 920system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) 921system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22476 # number of LoadLockedReq accesses(hits+misses) 922system.cpu.dcache.LoadLockedReq_accesses::total 22476 # number of LoadLockedReq accesses(hits+misses) 923system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) 924system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) 925system.cpu.dcache.demand_accesses::cpu.data 46750868 # number of demand (read+write) accesses 926system.cpu.dcache.demand_accesses::total 46750868 # number of demand (read+write) accesses 927system.cpu.dcache.overall_accesses::cpu.data 46750868 # number of overall (read+write) accesses 928system.cpu.dcache.overall_accesses::total 46750868 # number of overall (read+write) accesses 929system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000055 # miss rate for ReadReq accesses 930system.cpu.dcache.ReadReq_miss_rate::total 0.000055 # miss rate for ReadReq accesses 931system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000625 # miss rate for WriteReq accesses 932system.cpu.dcache.WriteReq_miss_rate::total 0.000625 # miss rate for WriteReq accesses 933system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000089 # miss rate for LoadLockedReq accesses 934system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000089 # miss rate for LoadLockedReq accesses 935system.cpu.dcache.demand_miss_rate::cpu.data 0.000206 # miss rate for demand accesses 936system.cpu.dcache.demand_miss_rate::total 0.000206 # miss rate for demand accesses 937system.cpu.dcache.overall_miss_rate::cpu.data 0.000206 # miss rate for overall accesses 938system.cpu.dcache.overall_miss_rate::total 0.000206 # miss rate for overall accesses 939system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64059.066842 # average ReadReq miss latency 940system.cpu.dcache.ReadReq_avg_miss_latency::total 64059.066842 # average ReadReq miss latency 941system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60290.527774 # average WriteReq miss latency 942system.cpu.dcache.WriteReq_avg_miss_latency::total 60290.527774 # average WriteReq miss latency 943system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71250 # average LoadLockedReq miss latency 944system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71250 # average LoadLockedReq miss latency 945system.cpu.dcache.demand_avg_miss_latency::cpu.data 61034.601787 # average overall miss latency 946system.cpu.dcache.demand_avg_miss_latency::total 61034.601787 # average overall miss latency 947system.cpu.dcache.overall_avg_miss_latency::cpu.data 61034.601787 # average overall miss latency 948system.cpu.dcache.overall_avg_miss_latency::total 61034.601787 # average overall miss latency 949system.cpu.dcache.blocked_cycles::no_mshrs 592 # number of cycles access was blocked 950system.cpu.dcache.blocked_cycles::no_targets 314 # number of cycles access was blocked 951system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked 952system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked 953system.cpu.dcache.avg_blocked_cycles::no_mshrs 53.818182 # average number of cycles each access was blocked 954system.cpu.dcache.avg_blocked_cycles::no_targets 78.500000 # average number of cycles each access was blocked 955system.cpu.dcache.fast_writes 0 # number of fast writes performed 956system.cpu.dcache.cache_copies 0 # number of cache copies performed 957system.cpu.dcache.writebacks::writebacks 18 # number of writebacks 958system.cpu.dcache.writebacks::total 18 # number of writebacks 959system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1126 # number of ReadReq MSHR hits 960system.cpu.dcache.ReadReq_mshr_hits::total 1126 # number of ReadReq MSHR hits 961system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6645 # number of WriteReq MSHR hits 962system.cpu.dcache.WriteReq_mshr_hits::total 6645 # number of WriteReq MSHR hits 963system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 964system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits 965system.cpu.dcache.demand_mshr_hits::cpu.data 7771 # number of demand (read+write) MSHR hits 966system.cpu.dcache.demand_mshr_hits::total 7771 # number of demand (read+write) MSHR hits 967system.cpu.dcache.overall_mshr_hits::cpu.data 7771 # number of overall MSHR hits 968system.cpu.dcache.overall_mshr_hits::total 7771 # number of overall MSHR hits 969system.cpu.dcache.ReadReq_mshr_misses::cpu.data 774 # number of ReadReq MSHR misses 970system.cpu.dcache.ReadReq_mshr_misses::total 774 # number of ReadReq MSHR misses 971system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1078 # number of WriteReq MSHR misses 972system.cpu.dcache.WriteReq_mshr_misses::total 1078 # number of WriteReq MSHR misses 973system.cpu.dcache.demand_mshr_misses::cpu.data 1852 # number of demand (read+write) MSHR misses 974system.cpu.dcache.demand_mshr_misses::total 1852 # number of demand (read+write) MSHR misses 975system.cpu.dcache.overall_mshr_misses::cpu.data 1852 # number of overall MSHR misses 976system.cpu.dcache.overall_mshr_misses::total 1852 # number of overall MSHR misses 977system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 53118011 # number of ReadReq MSHR miss cycles 978system.cpu.dcache.ReadReq_mshr_miss_latency::total 53118011 # number of ReadReq MSHR miss cycles 979system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73393498 # number of WriteReq MSHR miss cycles 980system.cpu.dcache.WriteReq_mshr_miss_latency::total 73393498 # number of WriteReq MSHR miss cycles 981system.cpu.dcache.demand_mshr_miss_latency::cpu.data 126511509 # number of demand (read+write) MSHR miss cycles 982system.cpu.dcache.demand_mshr_miss_latency::total 126511509 # number of demand (read+write) MSHR miss cycles 983system.cpu.dcache.overall_mshr_miss_latency::cpu.data 126511509 # number of overall MSHR miss cycles 984system.cpu.dcache.overall_mshr_miss_latency::total 126511509 # number of overall MSHR miss cycles 985system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses 986system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses 987system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000087 # mshr miss rate for WriteReq accesses 988system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000087 # mshr miss rate for WriteReq accesses 989system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses 990system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses 991system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses 992system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses 993system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68627.921189 # average ReadReq mshr miss latency 994system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68627.921189 # average ReadReq mshr miss latency 995system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68083.022263 # average WriteReq mshr miss latency 996system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68083.022263 # average WriteReq mshr miss latency 997system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68310.750000 # average overall mshr miss latency 998system.cpu.dcache.demand_avg_mshr_miss_latency::total 68310.750000 # average overall mshr miss latency 999system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68310.750000 # average overall mshr miss latency 1000system.cpu.dcache.overall_avg_mshr_miss_latency::total 68310.750000 # average overall mshr miss latency 1001system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1002 1003---------- End Simulation Statistics ---------- 1004