stats.txt revision 10036:80e84beef3bb
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.074220 # Number of seconds simulated 4sim_ticks 74219948500 # Number of ticks simulated 5final_tick 74219948500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 133200 # Simulator instruction rate (inst/s) 8host_op_rate 145842 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 57376166 # Simulator tick rate (ticks/s) 10host_mem_usage 253176 # Number of bytes of host memory used 11host_seconds 1293.57 # Real time elapsed on the host 12sim_insts 172303021 # Number of instructions simulated 13sim_ops 188656503 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 131072 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 111680 # Number of bytes read from this memory 18system.physmem.bytes_read::total 242752 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 131072 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 131072 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 2048 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 1745 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 3793 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 1765994 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 1504717 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 3270711 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 1765994 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 1765994 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 1765994 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 1504717 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 3270711 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 3794 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 3794 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 242816 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 242816 # Total read bytes from the system interface side 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 43system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 44system.physmem.perBankRdBursts::0 306 # Per bank write bursts 45system.physmem.perBankRdBursts::1 215 # Per bank write bursts 46system.physmem.perBankRdBursts::2 133 # Per bank write bursts 47system.physmem.perBankRdBursts::3 308 # Per bank write bursts 48system.physmem.perBankRdBursts::4 298 # Per bank write bursts 49system.physmem.perBankRdBursts::5 299 # Per bank write bursts 50system.physmem.perBankRdBursts::6 264 # Per bank write bursts 51system.physmem.perBankRdBursts::7 216 # Per bank write bursts 52system.physmem.perBankRdBursts::8 246 # Per bank write bursts 53system.physmem.perBankRdBursts::9 215 # Per bank write bursts 54system.physmem.perBankRdBursts::10 289 # Per bank write bursts 55system.physmem.perBankRdBursts::11 193 # Per bank write bursts 56system.physmem.perBankRdBursts::12 189 # Per bank write bursts 57system.physmem.perBankRdBursts::13 206 # Per bank write bursts 58system.physmem.perBankRdBursts::14 217 # Per bank write bursts 59system.physmem.perBankRdBursts::15 200 # Per bank write bursts 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts 63system.physmem.perBankWrBursts::3 0 # Per bank write bursts 64system.physmem.perBankWrBursts::4 0 # Per bank write bursts 65system.physmem.perBankWrBursts::5 0 # Per bank write bursts 66system.physmem.perBankWrBursts::6 0 # Per bank write bursts 67system.physmem.perBankWrBursts::7 0 # Per bank write bursts 68system.physmem.perBankWrBursts::8 0 # Per bank write bursts 69system.physmem.perBankWrBursts::9 0 # Per bank write bursts 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 78system.physmem.totGap 74219930000 # Total gap between requests 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 3794 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) 93system.physmem.rdQLenPdf::0 2825 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 784 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 142 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 36 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 125system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 157system.physmem.bytesPerActivate::samples 717 # Bytes accessed per row activation 158system.physmem.bytesPerActivate::mean 334.192469 # Bytes accessed per row activation 159system.physmem.bytesPerActivate::gmean 180.652659 # Bytes accessed per row activation 160system.physmem.bytesPerActivate::stdev 576.534776 # Bytes accessed per row activation 161system.physmem.bytesPerActivate::64-65 257 35.84% 35.84% # Bytes accessed per row activation 162system.physmem.bytesPerActivate::128-129 120 16.74% 52.58% # Bytes accessed per row activation 163system.physmem.bytesPerActivate::192-193 71 9.90% 62.48% # Bytes accessed per row activation 164system.physmem.bytesPerActivate::256-257 49 6.83% 69.32% # Bytes accessed per row activation 165system.physmem.bytesPerActivate::320-321 19 2.65% 71.97% # Bytes accessed per row activation 166system.physmem.bytesPerActivate::384-385 26 3.63% 75.59% # Bytes accessed per row activation 167system.physmem.bytesPerActivate::448-449 20 2.79% 78.38% # Bytes accessed per row activation 168system.physmem.bytesPerActivate::512-513 17 2.37% 80.75% # Bytes accessed per row activation 169system.physmem.bytesPerActivate::576-577 17 2.37% 83.12% # Bytes accessed per row activation 170system.physmem.bytesPerActivate::640-641 40 5.58% 88.70% # Bytes accessed per row activation 171system.physmem.bytesPerActivate::704-705 17 2.37% 91.07% # Bytes accessed per row activation 172system.physmem.bytesPerActivate::768-769 6 0.84% 91.91% # Bytes accessed per row activation 173system.physmem.bytesPerActivate::832-833 6 0.84% 92.75% # Bytes accessed per row activation 174system.physmem.bytesPerActivate::896-897 8 1.12% 93.86% # Bytes accessed per row activation 175system.physmem.bytesPerActivate::960-961 6 0.84% 94.70% # Bytes accessed per row activation 176system.physmem.bytesPerActivate::1024-1025 5 0.70% 95.40% # Bytes accessed per row activation 177system.physmem.bytesPerActivate::1088-1089 4 0.56% 95.96% # Bytes accessed per row activation 178system.physmem.bytesPerActivate::1152-1153 1 0.14% 96.09% # Bytes accessed per row activation 179system.physmem.bytesPerActivate::1216-1217 2 0.28% 96.37% # Bytes accessed per row activation 180system.physmem.bytesPerActivate::1280-1281 2 0.28% 96.65% # Bytes accessed per row activation 181system.physmem.bytesPerActivate::1344-1345 2 0.28% 96.93% # Bytes accessed per row activation 182system.physmem.bytesPerActivate::1408-1409 2 0.28% 97.21% # Bytes accessed per row activation 183system.physmem.bytesPerActivate::1472-1473 1 0.14% 97.35% # Bytes accessed per row activation 184system.physmem.bytesPerActivate::1536-1537 1 0.14% 97.49% # Bytes accessed per row activation 185system.physmem.bytesPerActivate::1600-1601 1 0.14% 97.63% # Bytes accessed per row activation 186system.physmem.bytesPerActivate::1664-1665 1 0.14% 97.77% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::1728-1729 1 0.14% 97.91% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::1792-1793 2 0.28% 98.19% # Bytes accessed per row activation 189system.physmem.bytesPerActivate::1856-1857 1 0.14% 98.33% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::1984-1985 2 0.28% 98.61% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::2176-2177 1 0.14% 98.74% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::2688-2689 1 0.14% 98.88% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::2816-2817 1 0.14% 99.02% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::3008-3009 1 0.14% 99.16% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::3200-3201 1 0.14% 99.30% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::3392-3393 1 0.14% 99.44% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::3648-3649 1 0.14% 99.58% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::3712-3713 1 0.14% 99.72% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::6656-6657 1 0.14% 99.86% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::8192-8193 1 0.14% 100.00% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::total 717 # Bytes accessed per row activation 202system.physmem.totQLat 25203500 # Total ticks spent queuing 203system.physmem.totMemAccLat 100713500 # Total ticks spent from burst creation until serviced by the DRAM 204system.physmem.totBusLat 18970000 # Total ticks spent in databus transfers 205system.physmem.totBankLat 56540000 # Total ticks spent accessing banks 206system.physmem.avgQLat 6642.99 # Average queueing delay per DRAM burst 207system.physmem.avgBankLat 14902.48 # Average bank access latency per DRAM burst 208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 209system.physmem.avgMemAccLat 26545.47 # Average memory access latency per DRAM burst 210system.physmem.avgRdBW 3.27 # Average DRAM read bandwidth in MiByte/s 211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 212system.physmem.avgRdBWSys 3.27 # Average system read bandwidth in MiByte/s 213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 215system.physmem.busUtil 0.03 # Data bus utilization in percentage 216system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 218system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing 219system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 220system.physmem.readRowHits 3077 # Number of row buffer hits during reads 221system.physmem.writeRowHits 0 # Number of row buffer hits during writes 222system.physmem.readRowHitRate 81.10 # Row buffer hit rate for reads 223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 224system.physmem.avgGap 19562448.60 # Average gap between requests 225system.physmem.pageHitRate 81.10 # Row buffer hit rate, read and write combined 226system.physmem.prechargeAllPercent 0.24 # Percentage of time for which DRAM has all the banks in precharge state 227system.membus.throughput 3270711 # Throughput (bytes/s) 228system.membus.trans_dist::ReadReq 2723 # Transaction distribution 229system.membus.trans_dist::ReadResp 2722 # Transaction distribution 230system.membus.trans_dist::ReadExReq 1071 # Transaction distribution 231system.membus.trans_dist::ReadExResp 1071 # Transaction distribution 232system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7587 # Packet count per connected master and slave (bytes) 233system.membus.pkt_count::total 7587 # Packet count per connected master and slave (bytes) 234system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 242752 # Cumulative packet size per connected master and slave (bytes) 235system.membus.tot_pkt_size::total 242752 # Cumulative packet size per connected master and slave (bytes) 236system.membus.data_through_bus 242752 # Total data (bytes) 237system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 238system.membus.reqLayer0.occupancy 4682500 # Layer occupancy (ticks) 239system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 240system.membus.respLayer1.occupancy 35532750 # Layer occupancy (ticks) 241system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 242system.cpu_clk_domain.clock 500 # Clock period in ticks 243system.cpu.branchPred.lookups 94784274 # Number of BP lookups 244system.cpu.branchPred.condPredicted 74784006 # Number of conditional branches predicted 245system.cpu.branchPred.condIncorrect 6281562 # Number of conditional branches incorrect 246system.cpu.branchPred.BTBLookups 44678423 # Number of BTB lookups 247system.cpu.branchPred.BTBHits 43050018 # Number of BTB hits 248system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 249system.cpu.branchPred.BTBHitPct 96.355276 # BTB Hit Percentage 250system.cpu.branchPred.usedRAS 4356639 # Number of times the RAS was used to get a target. 251system.cpu.branchPred.RASInCorrect 88400 # Number of incorrect RAS predictions. 252system.cpu.dtb.inst_hits 0 # ITB inst hits 253system.cpu.dtb.inst_misses 0 # ITB inst misses 254system.cpu.dtb.read_hits 0 # DTB read hits 255system.cpu.dtb.read_misses 0 # DTB read misses 256system.cpu.dtb.write_hits 0 # DTB write hits 257system.cpu.dtb.write_misses 0 # DTB write misses 258system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 259system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 260system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 261system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 262system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 263system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 264system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 265system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 266system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 267system.cpu.dtb.read_accesses 0 # DTB read accesses 268system.cpu.dtb.write_accesses 0 # DTB write accesses 269system.cpu.dtb.inst_accesses 0 # ITB inst accesses 270system.cpu.dtb.hits 0 # DTB hits 271system.cpu.dtb.misses 0 # DTB misses 272system.cpu.dtb.accesses 0 # DTB accesses 273system.cpu.itb.inst_hits 0 # ITB inst hits 274system.cpu.itb.inst_misses 0 # ITB inst misses 275system.cpu.itb.read_hits 0 # DTB read hits 276system.cpu.itb.read_misses 0 # DTB read misses 277system.cpu.itb.write_hits 0 # DTB write hits 278system.cpu.itb.write_misses 0 # DTB write misses 279system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 280system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 281system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 282system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 283system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 284system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 285system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 286system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 287system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 288system.cpu.itb.read_accesses 0 # DTB read accesses 289system.cpu.itb.write_accesses 0 # DTB write accesses 290system.cpu.itb.inst_accesses 0 # ITB inst accesses 291system.cpu.itb.hits 0 # DTB hits 292system.cpu.itb.misses 0 # DTB misses 293system.cpu.itb.accesses 0 # DTB accesses 294system.cpu.workload.num_syscalls 400 # Number of system calls 295system.cpu.numCycles 148439898 # number of cpu cycles simulated 296system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 297system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 298system.cpu.fetch.icacheStallCycles 39656921 # Number of cycles fetch is stalled on an Icache miss 299system.cpu.fetch.Insts 380179930 # Number of instructions fetch has processed 300system.cpu.fetch.Branches 94784274 # Number of branches that fetch encountered 301system.cpu.fetch.predictedBranches 47406657 # Number of branches that fetch has predicted taken 302system.cpu.fetch.Cycles 80370665 # Number of cycles fetch has run and was not squashing or blocked 303system.cpu.fetch.SquashCycles 27283127 # Number of cycles fetch has spent squashing 304system.cpu.fetch.BlockedCycles 7220968 # Number of cycles fetch has spent blocked 305system.cpu.fetch.MiscStallCycles 44 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 306system.cpu.fetch.PendingTrapStallCycles 6188 # Number of stall cycles due to pending traps 307system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions 308system.cpu.fetch.IcacheWaitRetryStallCycles 50 # Number of stall cycles due to full MSHR 309system.cpu.fetch.CacheLines 36850894 # Number of cache lines fetched 310system.cpu.fetch.IcacheSquashes 1831983 # Number of outstanding Icache misses that were squashed 311system.cpu.fetch.rateDist::samples 148240577 # Number of instructions fetched each cycle (Total) 312system.cpu.fetch.rateDist::mean 2.801601 # Number of instructions fetched each cycle (Total) 313system.cpu.fetch.rateDist::stdev 3.152871 # Number of instructions fetched each cycle (Total) 314system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 315system.cpu.fetch.rateDist::0 68038757 45.90% 45.90% # Number of instructions fetched each cycle (Total) 316system.cpu.fetch.rateDist::1 5265463 3.55% 49.45% # Number of instructions fetched each cycle (Total) 317system.cpu.fetch.rateDist::2 10540668 7.11% 56.56% # Number of instructions fetched each cycle (Total) 318system.cpu.fetch.rateDist::3 10285704 6.94% 63.50% # Number of instructions fetched each cycle (Total) 319system.cpu.fetch.rateDist::4 8660470 5.84% 69.34% # Number of instructions fetched each cycle (Total) 320system.cpu.fetch.rateDist::5 6545129 4.42% 73.76% # Number of instructions fetched each cycle (Total) 321system.cpu.fetch.rateDist::6 6246382 4.21% 77.97% # Number of instructions fetched each cycle (Total) 322system.cpu.fetch.rateDist::7 8002830 5.40% 83.37% # Number of instructions fetched each cycle (Total) 323system.cpu.fetch.rateDist::8 24655174 16.63% 100.00% # Number of instructions fetched each cycle (Total) 324system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 325system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 326system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 327system.cpu.fetch.rateDist::total 148240577 # Number of instructions fetched each cycle (Total) 328system.cpu.fetch.branchRate 0.638536 # Number of branch fetches per cycle 329system.cpu.fetch.rate 2.561171 # Number of inst fetches per cycle 330system.cpu.decode.IdleCycles 45513795 # Number of cycles decode is idle 331system.cpu.decode.BlockedCycles 5886752 # Number of cycles decode is blocked 332system.cpu.decode.RunCycles 74804124 # Number of cycles decode is running 333system.cpu.decode.UnblockCycles 1203493 # Number of cycles decode is unblocking 334system.cpu.decode.SquashCycles 20832413 # Number of cycles decode is squashing 335system.cpu.decode.BranchResolved 14327914 # Number of times decode resolved a branch 336system.cpu.decode.BranchMispred 164349 # Number of times decode detected a branch misprediction 337system.cpu.decode.DecodedInsts 392779880 # Number of instructions handled by decode 338system.cpu.decode.SquashedInsts 733794 # Number of squashed instructions handled by decode 339system.cpu.rename.SquashCycles 20832413 # Number of cycles rename is squashing 340system.cpu.rename.IdleCycles 50900748 # Number of cycles rename is idle 341system.cpu.rename.BlockCycles 730699 # Number of cycles rename is blocking 342system.cpu.rename.serializeStallCycles 603191 # count of cycles rename stalled for serializing inst 343system.cpu.rename.RunCycles 70558309 # Number of cycles rename is running 344system.cpu.rename.UnblockCycles 4615217 # Number of cycles rename is unblocking 345system.cpu.rename.RenamedInsts 371308082 # Number of instructions processed by rename 346system.cpu.rename.ROBFullEvents 19 # Number of times rename has blocked due to ROB full 347system.cpu.rename.IQFullEvents 339275 # Number of times rename has blocked due to IQ full 348system.cpu.rename.LSQFullEvents 3661219 # Number of times rename has blocked due to LSQ full 349system.cpu.rename.FullRegisterEvents 231 # Number of times there has been no free registers 350system.cpu.rename.RenamedOperands 631703471 # Number of destination operands rename has renamed 351system.cpu.rename.RenameLookups 1581699910 # Number of register rename lookups that rename has made 352system.cpu.rename.int_rename_lookups 1506871257 # Number of integer rename lookups 353system.cpu.rename.fp_rename_lookups 3203425 # Number of floating rename lookups 354system.cpu.rename.CommittedMaps 298044139 # Number of HB maps that are committed 355system.cpu.rename.UndoneMaps 333659332 # Number of HB maps that are undone due to squashing 356system.cpu.rename.serializingInsts 25072 # count of serializing insts renamed 357system.cpu.rename.tempSerializingInsts 25068 # count of temporary serializing insts renamed 358system.cpu.rename.skidInsts 13010245 # count of insts added to the skid buffer 359system.cpu.memDep0.insertedLoads 43012682 # Number of loads inserted to the mem dependence unit. 360system.cpu.memDep0.insertedStores 16416405 # Number of stores inserted to the mem dependence unit. 361system.cpu.memDep0.conflictingLoads 5733542 # Number of conflicting loads. 362system.cpu.memDep0.conflictingStores 3666500 # Number of conflicting stores. 363system.cpu.iq.iqInstsAdded 329190147 # Number of instructions added to the IQ (excludes non-spec) 364system.cpu.iq.iqNonSpecInstsAdded 47154 # Number of non-speculative instructions added to the IQ 365system.cpu.iq.iqInstsIssued 249456617 # Number of instructions issued 366system.cpu.iq.iqSquashedInstsIssued 789368 # Number of squashed instructions issued 367system.cpu.iq.iqSquashedInstsExamined 139503392 # Number of squashed instructions iterated over during squash; mainly for profiling 368system.cpu.iq.iqSquashedOperandsExamined 362002773 # Number of squashed operands that are examined and possibly removed from graph 369system.cpu.iq.iqSquashedNonSpecRemoved 1938 # Number of squashed non-spec instructions that were removed 370system.cpu.iq.issued_per_cycle::samples 148240577 # Number of insts issued each cycle 371system.cpu.iq.issued_per_cycle::mean 1.682782 # Number of insts issued each cycle 372system.cpu.iq.issued_per_cycle::stdev 1.761427 # Number of insts issued each cycle 373system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 374system.cpu.iq.issued_per_cycle::0 56059832 37.82% 37.82% # Number of insts issued each cycle 375system.cpu.iq.issued_per_cycle::1 22638796 15.27% 53.09% # Number of insts issued each cycle 376system.cpu.iq.issued_per_cycle::2 24824164 16.75% 69.83% # Number of insts issued each cycle 377system.cpu.iq.issued_per_cycle::3 20343400 13.72% 83.56% # Number of insts issued each cycle 378system.cpu.iq.issued_per_cycle::4 12534797 8.46% 92.01% # Number of insts issued each cycle 379system.cpu.iq.issued_per_cycle::5 6516114 4.40% 96.41% # Number of insts issued each cycle 380system.cpu.iq.issued_per_cycle::6 4026095 2.72% 99.12% # Number of insts issued each cycle 381system.cpu.iq.issued_per_cycle::7 1116067 0.75% 99.88% # Number of insts issued each cycle 382system.cpu.iq.issued_per_cycle::8 181312 0.12% 100.00% # Number of insts issued each cycle 383system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 384system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 385system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 386system.cpu.iq.issued_per_cycle::total 148240577 # Number of insts issued each cycle 387system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 388system.cpu.iq.fu_full::IntAlu 965215 38.57% 38.57% # attempts to use FU when none available 389system.cpu.iq.fu_full::IntMult 5593 0.22% 38.79% # attempts to use FU when none available 390system.cpu.iq.fu_full::IntDiv 0 0.00% 38.79% # attempts to use FU when none available 391system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.79% # attempts to use FU when none available 392system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.79% # attempts to use FU when none available 393system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.79% # attempts to use FU when none available 394system.cpu.iq.fu_full::FloatMult 0 0.00% 38.79% # attempts to use FU when none available 395system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.79% # attempts to use FU when none available 396system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.79% # attempts to use FU when none available 397system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.79% # attempts to use FU when none available 398system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.79% # attempts to use FU when none available 399system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.79% # attempts to use FU when none available 400system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.79% # attempts to use FU when none available 401system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.79% # attempts to use FU when none available 402system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.79% # attempts to use FU when none available 403system.cpu.iq.fu_full::SimdMult 0 0.00% 38.79% # attempts to use FU when none available 404system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.79% # attempts to use FU when none available 405system.cpu.iq.fu_full::SimdShift 0 0.00% 38.79% # attempts to use FU when none available 406system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.79% # attempts to use FU when none available 407system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.79% # attempts to use FU when none available 408system.cpu.iq.fu_full::SimdFloatAdd 101 0.00% 38.80% # attempts to use FU when none available 409system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.80% # attempts to use FU when none available 410system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.80% # attempts to use FU when none available 411system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.80% # attempts to use FU when none available 412system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.80% # attempts to use FU when none available 413system.cpu.iq.fu_full::SimdFloatMisc 48 0.00% 38.80% # attempts to use FU when none available 414system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.80% # attempts to use FU when none available 415system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.80% # attempts to use FU when none available 416system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.80% # attempts to use FU when none available 417system.cpu.iq.fu_full::MemRead 1158967 46.31% 85.11% # attempts to use FU when none available 418system.cpu.iq.fu_full::MemWrite 372730 14.89% 100.00% # attempts to use FU when none available 419system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 420system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 421system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 422system.cpu.iq.FU_type_0::IntAlu 194899963 78.13% 78.13% # Type of FU issued 423system.cpu.iq.FU_type_0::IntMult 979613 0.39% 78.52% # Type of FU issued 424system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.52% # Type of FU issued 425system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.52% # Type of FU issued 426system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.52% # Type of FU issued 427system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.52% # Type of FU issued 428system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.52% # Type of FU issued 429system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.52% # Type of FU issued 430system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.52% # Type of FU issued 431system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.52% # Type of FU issued 432system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.52% # Type of FU issued 433system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.52% # Type of FU issued 434system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.52% # Type of FU issued 435system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.52% # Type of FU issued 436system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.52% # Type of FU issued 437system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.52% # Type of FU issued 438system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.52% # Type of FU issued 439system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.52% # Type of FU issued 440system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.52% # Type of FU issued 441system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.52% # Type of FU issued 442system.cpu.iq.FU_type_0::SimdFloatAdd 33082 0.01% 78.54% # Type of FU issued 443system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.54% # Type of FU issued 444system.cpu.iq.FU_type_0::SimdFloatCmp 164367 0.07% 78.60% # Type of FU issued 445system.cpu.iq.FU_type_0::SimdFloatCvt 255141 0.10% 78.70% # Type of FU issued 446system.cpu.iq.FU_type_0::SimdFloatDiv 76420 0.03% 78.73% # Type of FU issued 447system.cpu.iq.FU_type_0::SimdFloatMisc 466123 0.19% 78.92% # Type of FU issued 448system.cpu.iq.FU_type_0::SimdFloatMult 206380 0.08% 79.00% # Type of FU issued 449system.cpu.iq.FU_type_0::SimdFloatMultAcc 71866 0.03% 79.03% # Type of FU issued 450system.cpu.iq.FU_type_0::SimdFloatSqrt 321 0.00% 79.03% # Type of FU issued 451system.cpu.iq.FU_type_0::MemRead 38355278 15.38% 94.41% # Type of FU issued 452system.cpu.iq.FU_type_0::MemWrite 13948063 5.59% 100.00% # Type of FU issued 453system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 454system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 455system.cpu.iq.FU_type_0::total 249456617 # Type of FU issued 456system.cpu.iq.rate 1.680523 # Inst issue rate 457system.cpu.iq.fu_busy_cnt 2502654 # FU busy when requested 458system.cpu.iq.fu_busy_rate 0.010032 # FU busy rate (busy events/executed inst) 459system.cpu.iq.int_inst_queue_reads 646705826 # Number of integer instruction queue reads 460system.cpu.iq.int_inst_queue_writes 466563414 # Number of integer instruction queue writes 461system.cpu.iq.int_inst_queue_wakeup_accesses 237885445 # Number of integer instruction queue wakeup accesses 462system.cpu.iq.fp_inst_queue_reads 3740007 # Number of floating instruction queue reads 463system.cpu.iq.fp_inst_queue_writes 2195697 # Number of floating instruction queue writes 464system.cpu.iq.fp_inst_queue_wakeup_accesses 1842613 # Number of floating instruction queue wakeup accesses 465system.cpu.iq.int_alu_accesses 250082852 # Number of integer alu accesses 466system.cpu.iq.fp_alu_accesses 1876419 # Number of floating point alu accesses 467system.cpu.iew.lsq.thread0.forwLoads 2013198 # Number of loads that had data forwarded from stores 468system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 469system.cpu.iew.lsq.thread0.squashedLoads 13163198 # Number of loads squashed 470system.cpu.iew.lsq.thread0.ignoredResponses 11604 # Number of memory responses ignored because the instruction is squashed 471system.cpu.iew.lsq.thread0.memOrderViolation 18881 # Number of memory ordering violations 472system.cpu.iew.lsq.thread0.squashedStores 3771771 # Number of stores squashed 473system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 474system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 475system.cpu.iew.lsq.thread0.rescheduledLoads 18 # Number of loads that were rescheduled 476system.cpu.iew.lsq.thread0.cacheBlocked 107 # Number of times an access to memory failed due to the cache being blocked 477system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 478system.cpu.iew.iewSquashCycles 20832413 # Number of cycles IEW is squashing 479system.cpu.iew.iewBlockCycles 18550 # Number of cycles IEW is blocking 480system.cpu.iew.iewUnblockCycles 893 # Number of cycles IEW is unblocking 481system.cpu.iew.iewDispatchedInsts 329254497 # Number of instructions dispatched to IQ 482system.cpu.iew.iewDispSquashedInsts 785294 # Number of squashed instructions skipped by dispatch 483system.cpu.iew.iewDispLoadInsts 43012682 # Number of dispatched load instructions 484system.cpu.iew.iewDispStoreInsts 16416405 # Number of dispatched store instructions 485system.cpu.iew.iewDispNonSpecInsts 24746 # Number of dispatched non-speculative instructions 486system.cpu.iew.iewIQFullEvents 188 # Number of times the IQ has become full, causing a stall 487system.cpu.iew.iewLSQFullEvents 276 # Number of times the LSQ has become full, causing a stall 488system.cpu.iew.memOrderViolationEvents 18881 # Number of memory order violations 489system.cpu.iew.predictedTakenIncorrect 3889958 # Number of branches that were predicted taken incorrectly 490system.cpu.iew.predictedNotTakenIncorrect 3760086 # Number of branches that were predicted not taken incorrectly 491system.cpu.iew.branchMispredicts 7650044 # Number of branch mispredicts detected at execute 492system.cpu.iew.iewExecutedInsts 242960519 # Number of executed instructions 493system.cpu.iew.iewExecLoadInsts 36851938 # Number of load instructions executed 494system.cpu.iew.iewExecSquashedInsts 6496098 # Number of squashed instructions skipped in execute 495system.cpu.iew.exec_swp 0 # number of swp insts executed 496system.cpu.iew.exec_nop 17196 # number of nop insts executed 497system.cpu.iew.exec_refs 50500394 # number of memory reference insts executed 498system.cpu.iew.exec_branches 53426072 # Number of branches executed 499system.cpu.iew.exec_stores 13648456 # Number of stores executed 500system.cpu.iew.exec_rate 1.636760 # Inst execution rate 501system.cpu.iew.wb_sent 240785663 # cumulative count of insts sent to commit 502system.cpu.iew.wb_count 239728058 # cumulative count of insts written-back 503system.cpu.iew.wb_producers 148474078 # num instructions producing a value 504system.cpu.iew.wb_consumers 267261470 # num instructions consuming a value 505system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 506system.cpu.iew.wb_rate 1.614984 # insts written-back per cycle 507system.cpu.iew.wb_fanout 0.555539 # average fanout of values written-back 508system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 509system.cpu.commit.commitSquashedInsts 140583609 # The number of squashed insts skipped by commit 510system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards 511system.cpu.commit.branchMispredicts 6128235 # The number of times a branch was mispredicted 512system.cpu.commit.committed_per_cycle::samples 127408164 # Number of insts commited each cycle 513system.cpu.commit.committed_per_cycle::mean 1.480838 # Number of insts commited each cycle 514system.cpu.commit.committed_per_cycle::stdev 2.185451 # Number of insts commited each cycle 515system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 516system.cpu.commit.committed_per_cycle::0 57701829 45.29% 45.29% # Number of insts commited each cycle 517system.cpu.commit.committed_per_cycle::1 31696937 24.88% 70.17% # Number of insts commited each cycle 518system.cpu.commit.committed_per_cycle::2 13777780 10.81% 80.98% # Number of insts commited each cycle 519system.cpu.commit.committed_per_cycle::3 7640618 6.00% 86.98% # Number of insts commited each cycle 520system.cpu.commit.committed_per_cycle::4 4387787 3.44% 90.42% # Number of insts commited each cycle 521system.cpu.commit.committed_per_cycle::5 1321958 1.04% 91.46% # Number of insts commited each cycle 522system.cpu.commit.committed_per_cycle::6 1703212 1.34% 92.80% # Number of insts commited each cycle 523system.cpu.commit.committed_per_cycle::7 1308014 1.03% 93.82% # Number of insts commited each cycle 524system.cpu.commit.committed_per_cycle::8 7870029 6.18% 100.00% # Number of insts commited each cycle 525system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 526system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 527system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 528system.cpu.commit.committed_per_cycle::total 127408164 # Number of insts commited each cycle 529system.cpu.commit.committedInsts 172317409 # Number of instructions committed 530system.cpu.commit.committedOps 188670891 # Number of ops (including micro ops) committed 531system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 532system.cpu.commit.refs 42494118 # Number of memory references committed 533system.cpu.commit.loads 29849484 # Number of loads committed 534system.cpu.commit.membars 22408 # Number of memory barriers committed 535system.cpu.commit.branches 40300311 # Number of branches committed 536system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. 537system.cpu.commit.int_insts 150106217 # Number of committed integer instructions. 538system.cpu.commit.function_calls 1848934 # Number of function calls committed. 539system.cpu.commit.bw_lim_events 7870029 # number cycles where commit BW limit reached 540system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 541system.cpu.rob.rob_reads 448787434 # The number of ROB reads 542system.cpu.rob.rob_writes 679451113 # The number of ROB writes 543system.cpu.timesIdled 2805 # Number of times that the entire CPU went into an idle state and unscheduled itself 544system.cpu.idleCycles 199321 # Total number of cycles that the CPU has spent unscheduled due to idling 545system.cpu.committedInsts 172303021 # Number of Instructions Simulated 546system.cpu.committedOps 188656503 # Number of Ops (including micro ops) Simulated 547system.cpu.committedInsts_total 172303021 # Number of Instructions Simulated 548system.cpu.cpi 0.861505 # CPI: Cycles Per Instruction 549system.cpu.cpi_total 0.861505 # CPI: Total CPI of All Threads 550system.cpu.ipc 1.160759 # IPC: Instructions Per Cycle 551system.cpu.ipc_total 1.160759 # IPC: Total IPC of All Threads 552system.cpu.int_regfile_reads 1079417004 # number of integer regfile reads 553system.cpu.int_regfile_writes 384871783 # number of integer regfile writes 554system.cpu.fp_regfile_reads 2913086 # number of floating regfile reads 555system.cpu.fp_regfile_writes 2499105 # number of floating regfile writes 556system.cpu.misc_regfile_reads 54501288 # number of misc regfile reads 557system.cpu.misc_regfile_writes 820036 # number of misc regfile writes 558system.cpu.toL2Bus.throughput 5169500 # Throughput (bytes/s) 559system.cpu.toL2Bus.trans_dist::ReadReq 4899 # Transaction distribution 560system.cpu.toL2Bus.trans_dist::ReadResp 4898 # Transaction distribution 561system.cpu.toL2Bus.trans_dist::Writeback 18 # Transaction distribution 562system.cpu.toL2Bus.trans_dist::ReadExReq 1079 # Transaction distribution 563system.cpu.toL2Bus.trans_dist::ReadExResp 1079 # Transaction distribution 564system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8251 # Packet count per connected master and slave (bytes) 565system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3722 # Packet count per connected master and slave (bytes) 566system.cpu.toL2Bus.pkt_count::total 11973 # Packet count per connected master and slave (bytes) 567system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 264000 # Cumulative packet size per connected master and slave (bytes) 568system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119680 # Cumulative packet size per connected master and slave (bytes) 569system.cpu.toL2Bus.tot_pkt_size::total 383680 # Cumulative packet size per connected master and slave (bytes) 570system.cpu.toL2Bus.data_through_bus 383680 # Total data (bytes) 571system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 572system.cpu.toL2Bus.reqLayer0.occupancy 3016000 # Layer occupancy (ticks) 573system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 574system.cpu.toL2Bus.respLayer0.occupancy 6552496 # Layer occupancy (ticks) 575system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 576system.cpu.toL2Bus.respLayer1.occupancy 3047739 # Layer occupancy (ticks) 577system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 578system.cpu.icache.tags.replacements 2394 # number of replacements 579system.cpu.icache.tags.tagsinuse 1347.740549 # Cycle average of tags in use 580system.cpu.icache.tags.total_refs 36845557 # Total number of references to valid blocks. 581system.cpu.icache.tags.sampled_refs 4125 # Sample count of references to valid blocks. 582system.cpu.icache.tags.avg_refs 8932.256242 # Average number of references to valid blocks. 583system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 584system.cpu.icache.tags.occ_blocks::cpu.inst 1347.740549 # Average occupied blocks per requestor 585system.cpu.icache.tags.occ_percent::cpu.inst 0.658076 # Average percentage of cache occupancy 586system.cpu.icache.tags.occ_percent::total 0.658076 # Average percentage of cache occupancy 587system.cpu.icache.tags.occ_task_id_blocks::1024 1731 # Occupied blocks per task id 588system.cpu.icache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id 589system.cpu.icache.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id 590system.cpu.icache.tags.age_task_id_blocks_1024::2 544 # Occupied blocks per task id 591system.cpu.icache.tags.age_task_id_blocks_1024::3 27 # Occupied blocks per task id 592system.cpu.icache.tags.age_task_id_blocks_1024::4 1037 # Occupied blocks per task id 593system.cpu.icache.tags.occ_task_id_percent::1024 0.845215 # Percentage of cache occupancy per task id 594system.cpu.icache.tags.tag_accesses 73705913 # Number of tag accesses 595system.cpu.icache.tags.data_accesses 73705913 # Number of data accesses 596system.cpu.icache.ReadReq_hits::cpu.inst 36845557 # number of ReadReq hits 597system.cpu.icache.ReadReq_hits::total 36845557 # number of ReadReq hits 598system.cpu.icache.demand_hits::cpu.inst 36845557 # number of demand (read+write) hits 599system.cpu.icache.demand_hits::total 36845557 # number of demand (read+write) hits 600system.cpu.icache.overall_hits::cpu.inst 36845557 # number of overall hits 601system.cpu.icache.overall_hits::total 36845557 # number of overall hits 602system.cpu.icache.ReadReq_misses::cpu.inst 5337 # number of ReadReq misses 603system.cpu.icache.ReadReq_misses::total 5337 # number of ReadReq misses 604system.cpu.icache.demand_misses::cpu.inst 5337 # number of demand (read+write) misses 605system.cpu.icache.demand_misses::total 5337 # number of demand (read+write) misses 606system.cpu.icache.overall_misses::cpu.inst 5337 # number of overall misses 607system.cpu.icache.overall_misses::total 5337 # number of overall misses 608system.cpu.icache.ReadReq_miss_latency::cpu.inst 225938245 # number of ReadReq miss cycles 609system.cpu.icache.ReadReq_miss_latency::total 225938245 # number of ReadReq miss cycles 610system.cpu.icache.demand_miss_latency::cpu.inst 225938245 # number of demand (read+write) miss cycles 611system.cpu.icache.demand_miss_latency::total 225938245 # number of demand (read+write) miss cycles 612system.cpu.icache.overall_miss_latency::cpu.inst 225938245 # number of overall miss cycles 613system.cpu.icache.overall_miss_latency::total 225938245 # number of overall miss cycles 614system.cpu.icache.ReadReq_accesses::cpu.inst 36850894 # number of ReadReq accesses(hits+misses) 615system.cpu.icache.ReadReq_accesses::total 36850894 # number of ReadReq accesses(hits+misses) 616system.cpu.icache.demand_accesses::cpu.inst 36850894 # number of demand (read+write) accesses 617system.cpu.icache.demand_accesses::total 36850894 # number of demand (read+write) accesses 618system.cpu.icache.overall_accesses::cpu.inst 36850894 # number of overall (read+write) accesses 619system.cpu.icache.overall_accesses::total 36850894 # number of overall (read+write) accesses 620system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000145 # miss rate for ReadReq accesses 621system.cpu.icache.ReadReq_miss_rate::total 0.000145 # miss rate for ReadReq accesses 622system.cpu.icache.demand_miss_rate::cpu.inst 0.000145 # miss rate for demand accesses 623system.cpu.icache.demand_miss_rate::total 0.000145 # miss rate for demand accesses 624system.cpu.icache.overall_miss_rate::cpu.inst 0.000145 # miss rate for overall accesses 625system.cpu.icache.overall_miss_rate::total 0.000145 # miss rate for overall accesses 626system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42334.316095 # average ReadReq miss latency 627system.cpu.icache.ReadReq_avg_miss_latency::total 42334.316095 # average ReadReq miss latency 628system.cpu.icache.demand_avg_miss_latency::cpu.inst 42334.316095 # average overall miss latency 629system.cpu.icache.demand_avg_miss_latency::total 42334.316095 # average overall miss latency 630system.cpu.icache.overall_avg_miss_latency::cpu.inst 42334.316095 # average overall miss latency 631system.cpu.icache.overall_avg_miss_latency::total 42334.316095 # average overall miss latency 632system.cpu.icache.blocked_cycles::no_mshrs 1128 # number of cycles access was blocked 633system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 634system.cpu.icache.blocked::no_mshrs 19 # number of cycles access was blocked 635system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 636system.cpu.icache.avg_blocked_cycles::no_mshrs 59.368421 # average number of cycles each access was blocked 637system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 638system.cpu.icache.fast_writes 0 # number of fast writes performed 639system.cpu.icache.cache_copies 0 # number of cache copies performed 640system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1211 # number of ReadReq MSHR hits 641system.cpu.icache.ReadReq_mshr_hits::total 1211 # number of ReadReq MSHR hits 642system.cpu.icache.demand_mshr_hits::cpu.inst 1211 # number of demand (read+write) MSHR hits 643system.cpu.icache.demand_mshr_hits::total 1211 # number of demand (read+write) MSHR hits 644system.cpu.icache.overall_mshr_hits::cpu.inst 1211 # number of overall MSHR hits 645system.cpu.icache.overall_mshr_hits::total 1211 # number of overall MSHR hits 646system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4126 # number of ReadReq MSHR misses 647system.cpu.icache.ReadReq_mshr_misses::total 4126 # number of ReadReq MSHR misses 648system.cpu.icache.demand_mshr_misses::cpu.inst 4126 # number of demand (read+write) MSHR misses 649system.cpu.icache.demand_mshr_misses::total 4126 # number of demand (read+write) MSHR misses 650system.cpu.icache.overall_mshr_misses::cpu.inst 4126 # number of overall MSHR misses 651system.cpu.icache.overall_mshr_misses::total 4126 # number of overall MSHR misses 652system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 168088504 # number of ReadReq MSHR miss cycles 653system.cpu.icache.ReadReq_mshr_miss_latency::total 168088504 # number of ReadReq MSHR miss cycles 654system.cpu.icache.demand_mshr_miss_latency::cpu.inst 168088504 # number of demand (read+write) MSHR miss cycles 655system.cpu.icache.demand_mshr_miss_latency::total 168088504 # number of demand (read+write) MSHR miss cycles 656system.cpu.icache.overall_mshr_miss_latency::cpu.inst 168088504 # number of overall MSHR miss cycles 657system.cpu.icache.overall_mshr_miss_latency::total 168088504 # number of overall MSHR miss cycles 658system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for ReadReq accesses 659system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000112 # mshr miss rate for ReadReq accesses 660system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for demand accesses 661system.cpu.icache.demand_mshr_miss_rate::total 0.000112 # mshr miss rate for demand accesses 662system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for overall accesses 663system.cpu.icache.overall_mshr_miss_rate::total 0.000112 # mshr miss rate for overall accesses 664system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40738.852157 # average ReadReq mshr miss latency 665system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40738.852157 # average ReadReq mshr miss latency 666system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40738.852157 # average overall mshr miss latency 667system.cpu.icache.demand_avg_mshr_miss_latency::total 40738.852157 # average overall mshr miss latency 668system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40738.852157 # average overall mshr miss latency 669system.cpu.icache.overall_avg_mshr_miss_latency::total 40738.852157 # average overall mshr miss latency 670system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 671system.cpu.l2cache.tags.replacements 0 # number of replacements 672system.cpu.l2cache.tags.tagsinuse 1967.449764 # Cycle average of tags in use 673system.cpu.l2cache.tags.total_refs 2162 # Total number of references to valid blocks. 674system.cpu.l2cache.tags.sampled_refs 2732 # Sample count of references to valid blocks. 675system.cpu.l2cache.tags.avg_refs 0.791362 # Average number of references to valid blocks. 676system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 677system.cpu.l2cache.tags.occ_blocks::writebacks 4.994098 # Average occupied blocks per requestor 678system.cpu.l2cache.tags.occ_blocks::cpu.inst 1425.569687 # Average occupied blocks per requestor 679system.cpu.l2cache.tags.occ_blocks::cpu.data 536.885979 # Average occupied blocks per requestor 680system.cpu.l2cache.tags.occ_percent::writebacks 0.000152 # Average percentage of cache occupancy 681system.cpu.l2cache.tags.occ_percent::cpu.inst 0.043505 # Average percentage of cache occupancy 682system.cpu.l2cache.tags.occ_percent::cpu.data 0.016384 # Average percentage of cache occupancy 683system.cpu.l2cache.tags.occ_percent::total 0.060042 # Average percentage of cache occupancy 684system.cpu.l2cache.tags.occ_task_id_blocks::1024 2732 # Occupied blocks per task id 685system.cpu.l2cache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id 686system.cpu.l2cache.tags.age_task_id_blocks_1024::1 91 # Occupied blocks per task id 687system.cpu.l2cache.tags.age_task_id_blocks_1024::2 604 # Occupied blocks per task id 688system.cpu.l2cache.tags.age_task_id_blocks_1024::3 28 # Occupied blocks per task id 689system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1970 # Occupied blocks per task id 690system.cpu.l2cache.tags.occ_task_id_percent::1024 0.083374 # Percentage of cache occupancy per task id 691system.cpu.l2cache.tags.tag_accesses 51779 # Number of tag accesses 692system.cpu.l2cache.tags.data_accesses 51779 # Number of data accesses 693system.cpu.l2cache.ReadReq_hits::cpu.inst 2073 # number of ReadReq hits 694system.cpu.l2cache.ReadReq_hits::cpu.data 88 # number of ReadReq hits 695system.cpu.l2cache.ReadReq_hits::total 2161 # number of ReadReq hits 696system.cpu.l2cache.Writeback_hits::writebacks 18 # number of Writeback hits 697system.cpu.l2cache.Writeback_hits::total 18 # number of Writeback hits 698system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits 699system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits 700system.cpu.l2cache.demand_hits::cpu.inst 2073 # number of demand (read+write) hits 701system.cpu.l2cache.demand_hits::cpu.data 96 # number of demand (read+write) hits 702system.cpu.l2cache.demand_hits::total 2169 # number of demand (read+write) hits 703system.cpu.l2cache.overall_hits::cpu.inst 2073 # number of overall hits 704system.cpu.l2cache.overall_hits::cpu.data 96 # number of overall hits 705system.cpu.l2cache.overall_hits::total 2169 # number of overall hits 706system.cpu.l2cache.ReadReq_misses::cpu.inst 2053 # number of ReadReq misses 707system.cpu.l2cache.ReadReq_misses::cpu.data 685 # number of ReadReq misses 708system.cpu.l2cache.ReadReq_misses::total 2738 # number of ReadReq misses 709system.cpu.l2cache.ReadExReq_misses::cpu.data 1071 # number of ReadExReq misses 710system.cpu.l2cache.ReadExReq_misses::total 1071 # number of ReadExReq misses 711system.cpu.l2cache.demand_misses::cpu.inst 2053 # number of demand (read+write) misses 712system.cpu.l2cache.demand_misses::cpu.data 1756 # number of demand (read+write) misses 713system.cpu.l2cache.demand_misses::total 3809 # number of demand (read+write) misses 714system.cpu.l2cache.overall_misses::cpu.inst 2053 # number of overall misses 715system.cpu.l2cache.overall_misses::cpu.data 1756 # number of overall misses 716system.cpu.l2cache.overall_misses::total 3809 # number of overall misses 717system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 143225500 # number of ReadReq miss cycles 718system.cpu.l2cache.ReadReq_miss_latency::cpu.data 51383000 # number of ReadReq miss cycles 719system.cpu.l2cache.ReadReq_miss_latency::total 194608500 # number of ReadReq miss cycles 720system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 72292250 # number of ReadExReq miss cycles 721system.cpu.l2cache.ReadExReq_miss_latency::total 72292250 # number of ReadExReq miss cycles 722system.cpu.l2cache.demand_miss_latency::cpu.inst 143225500 # number of demand (read+write) miss cycles 723system.cpu.l2cache.demand_miss_latency::cpu.data 123675250 # number of demand (read+write) miss cycles 724system.cpu.l2cache.demand_miss_latency::total 266900750 # number of demand (read+write) miss cycles 725system.cpu.l2cache.overall_miss_latency::cpu.inst 143225500 # number of overall miss cycles 726system.cpu.l2cache.overall_miss_latency::cpu.data 123675250 # number of overall miss cycles 727system.cpu.l2cache.overall_miss_latency::total 266900750 # number of overall miss cycles 728system.cpu.l2cache.ReadReq_accesses::cpu.inst 4126 # number of ReadReq accesses(hits+misses) 729system.cpu.l2cache.ReadReq_accesses::cpu.data 773 # number of ReadReq accesses(hits+misses) 730system.cpu.l2cache.ReadReq_accesses::total 4899 # number of ReadReq accesses(hits+misses) 731system.cpu.l2cache.Writeback_accesses::writebacks 18 # number of Writeback accesses(hits+misses) 732system.cpu.l2cache.Writeback_accesses::total 18 # number of Writeback accesses(hits+misses) 733system.cpu.l2cache.ReadExReq_accesses::cpu.data 1079 # number of ReadExReq accesses(hits+misses) 734system.cpu.l2cache.ReadExReq_accesses::total 1079 # number of ReadExReq accesses(hits+misses) 735system.cpu.l2cache.demand_accesses::cpu.inst 4126 # number of demand (read+write) accesses 736system.cpu.l2cache.demand_accesses::cpu.data 1852 # number of demand (read+write) accesses 737system.cpu.l2cache.demand_accesses::total 5978 # number of demand (read+write) accesses 738system.cpu.l2cache.overall_accesses::cpu.inst 4126 # number of overall (read+write) accesses 739system.cpu.l2cache.overall_accesses::cpu.data 1852 # number of overall (read+write) accesses 740system.cpu.l2cache.overall_accesses::total 5978 # number of overall (read+write) accesses 741system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.497576 # miss rate for ReadReq accesses 742system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.886158 # miss rate for ReadReq accesses 743system.cpu.l2cache.ReadReq_miss_rate::total 0.558890 # miss rate for ReadReq accesses 744system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992586 # miss rate for ReadExReq accesses 745system.cpu.l2cache.ReadExReq_miss_rate::total 0.992586 # miss rate for ReadExReq accesses 746system.cpu.l2cache.demand_miss_rate::cpu.inst 0.497576 # miss rate for demand accesses 747system.cpu.l2cache.demand_miss_rate::cpu.data 0.948164 # miss rate for demand accesses 748system.cpu.l2cache.demand_miss_rate::total 0.637170 # miss rate for demand accesses 749system.cpu.l2cache.overall_miss_rate::cpu.inst 0.497576 # miss rate for overall accesses 750system.cpu.l2cache.overall_miss_rate::cpu.data 0.948164 # miss rate for overall accesses 751system.cpu.l2cache.overall_miss_rate::total 0.637170 # miss rate for overall accesses 752system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69764.003897 # average ReadReq miss latency 753system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75011.678832 # average ReadReq miss latency 754system.cpu.l2cache.ReadReq_avg_miss_latency::total 71076.880935 # average ReadReq miss latency 755system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67499.766573 # average ReadExReq miss latency 756system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67499.766573 # average ReadExReq miss latency 757system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69764.003897 # average overall miss latency 758system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70430.096811 # average overall miss latency 759system.cpu.l2cache.demand_avg_miss_latency::total 70071.081649 # average overall miss latency 760system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69764.003897 # average overall miss latency 761system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70430.096811 # average overall miss latency 762system.cpu.l2cache.overall_avg_miss_latency::total 70071.081649 # average overall miss latency 763system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 764system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 765system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 766system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 767system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 768system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 769system.cpu.l2cache.fast_writes 0 # number of fast writes performed 770system.cpu.l2cache.cache_copies 0 # number of cache copies performed 771system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits 772system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 11 # number of ReadReq MSHR hits 773system.cpu.l2cache.ReadReq_mshr_hits::total 15 # number of ReadReq MSHR hits 774system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits 775system.cpu.l2cache.demand_mshr_hits::cpu.data 11 # number of demand (read+write) MSHR hits 776system.cpu.l2cache.demand_mshr_hits::total 15 # number of demand (read+write) MSHR hits 777system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits 778system.cpu.l2cache.overall_mshr_hits::cpu.data 11 # number of overall MSHR hits 779system.cpu.l2cache.overall_mshr_hits::total 15 # number of overall MSHR hits 780system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2049 # number of ReadReq MSHR misses 781system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 674 # number of ReadReq MSHR misses 782system.cpu.l2cache.ReadReq_mshr_misses::total 2723 # number of ReadReq MSHR misses 783system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1071 # number of ReadExReq MSHR misses 784system.cpu.l2cache.ReadExReq_mshr_misses::total 1071 # number of ReadExReq MSHR misses 785system.cpu.l2cache.demand_mshr_misses::cpu.inst 2049 # number of demand (read+write) MSHR misses 786system.cpu.l2cache.demand_mshr_misses::cpu.data 1745 # number of demand (read+write) MSHR misses 787system.cpu.l2cache.demand_mshr_misses::total 3794 # number of demand (read+write) MSHR misses 788system.cpu.l2cache.overall_mshr_misses::cpu.inst 2049 # number of overall MSHR misses 789system.cpu.l2cache.overall_mshr_misses::cpu.data 1745 # number of overall MSHR misses 790system.cpu.l2cache.overall_mshr_misses::total 3794 # number of overall MSHR misses 791system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 117253000 # number of ReadReq MSHR miss cycles 792system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 42297000 # number of ReadReq MSHR miss cycles 793system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159550000 # number of ReadReq MSHR miss cycles 794system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 58841750 # number of ReadExReq MSHR miss cycles 795system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 58841750 # number of ReadExReq MSHR miss cycles 796system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 117253000 # number of demand (read+write) MSHR miss cycles 797system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 101138750 # number of demand (read+write) MSHR miss cycles 798system.cpu.l2cache.demand_mshr_miss_latency::total 218391750 # number of demand (read+write) MSHR miss cycles 799system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 117253000 # number of overall MSHR miss cycles 800system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 101138750 # number of overall MSHR miss cycles 801system.cpu.l2cache.overall_mshr_miss_latency::total 218391750 # number of overall MSHR miss cycles 802system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.496607 # mshr miss rate for ReadReq accesses 803system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.871928 # mshr miss rate for ReadReq accesses 804system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.555828 # mshr miss rate for ReadReq accesses 805system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992586 # mshr miss rate for ReadExReq accesses 806system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992586 # mshr miss rate for ReadExReq accesses 807system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.496607 # mshr miss rate for demand accesses 808system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.942225 # mshr miss rate for demand accesses 809system.cpu.l2cache.demand_mshr_miss_rate::total 0.634660 # mshr miss rate for demand accesses 810system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.496607 # mshr miss rate for overall accesses 811system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.942225 # mshr miss rate for overall accesses 812system.cpu.l2cache.overall_mshr_miss_rate::total 0.634660 # mshr miss rate for overall accesses 813system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57224.499756 # average ReadReq mshr miss latency 814system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62755.192878 # average ReadReq mshr miss latency 815system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58593.463092 # average ReadReq mshr miss latency 816system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54940.943044 # average ReadExReq mshr miss latency 817system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54940.943044 # average ReadExReq mshr miss latency 818system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57224.499756 # average overall mshr miss latency 819system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57959.169054 # average overall mshr miss latency 820system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57562.401160 # average overall mshr miss latency 821system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57224.499756 # average overall mshr miss latency 822system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57959.169054 # average overall mshr miss latency 823system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57562.401160 # average overall mshr miss latency 824system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 825system.cpu.dcache.tags.replacements 57 # number of replacements 826system.cpu.dcache.tags.tagsinuse 1406.103135 # Cycle average of tags in use 827system.cpu.dcache.tags.total_refs 46786156 # Total number of references to valid blocks. 828system.cpu.dcache.tags.sampled_refs 1852 # Sample count of references to valid blocks. 829system.cpu.dcache.tags.avg_refs 25262.503240 # Average number of references to valid blocks. 830system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 831system.cpu.dcache.tags.occ_blocks::cpu.data 1406.103135 # Average occupied blocks per requestor 832system.cpu.dcache.tags.occ_percent::cpu.data 0.343287 # Average percentage of cache occupancy 833system.cpu.dcache.tags.occ_percent::total 0.343287 # Average percentage of cache occupancy 834system.cpu.dcache.tags.occ_task_id_blocks::1024 1795 # Occupied blocks per task id 835system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id 836system.cpu.dcache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id 837system.cpu.dcache.tags.age_task_id_blocks_1024::2 353 # Occupied blocks per task id 838system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 839system.cpu.dcache.tags.age_task_id_blocks_1024::4 1378 # Occupied blocks per task id 840system.cpu.dcache.tags.occ_task_id_percent::1024 0.438232 # Percentage of cache occupancy per task id 841system.cpu.dcache.tags.tag_accesses 93593418 # Number of tag accesses 842system.cpu.dcache.tags.data_accesses 93593418 # Number of data accesses 843system.cpu.dcache.ReadReq_hits::cpu.data 34384711 # number of ReadReq hits 844system.cpu.dcache.ReadReq_hits::total 34384711 # number of ReadReq hits 845system.cpu.dcache.WriteReq_hits::cpu.data 12356564 # number of WriteReq hits 846system.cpu.dcache.WriteReq_hits::total 12356564 # number of WriteReq hits 847system.cpu.dcache.LoadLockedReq_hits::cpu.data 22474 # number of LoadLockedReq hits 848system.cpu.dcache.LoadLockedReq_hits::total 22474 # number of LoadLockedReq hits 849system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits 850system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits 851system.cpu.dcache.demand_hits::cpu.data 46741275 # number of demand (read+write) hits 852system.cpu.dcache.demand_hits::total 46741275 # number of demand (read+write) hits 853system.cpu.dcache.overall_hits::cpu.data 46741275 # number of overall hits 854system.cpu.dcache.overall_hits::total 46741275 # number of overall hits 855system.cpu.dcache.ReadReq_misses::cpu.data 1902 # number of ReadReq misses 856system.cpu.dcache.ReadReq_misses::total 1902 # number of ReadReq misses 857system.cpu.dcache.WriteReq_misses::cpu.data 7723 # number of WriteReq misses 858system.cpu.dcache.WriteReq_misses::total 7723 # number of WriteReq misses 859system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 860system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 861system.cpu.dcache.demand_misses::cpu.data 9625 # number of demand (read+write) misses 862system.cpu.dcache.demand_misses::total 9625 # number of demand (read+write) misses 863system.cpu.dcache.overall_misses::cpu.data 9625 # number of overall misses 864system.cpu.dcache.overall_misses::total 9625 # number of overall misses 865system.cpu.dcache.ReadReq_miss_latency::cpu.data 121862727 # number of ReadReq miss cycles 866system.cpu.dcache.ReadReq_miss_latency::total 121862727 # number of ReadReq miss cycles 867system.cpu.dcache.WriteReq_miss_latency::cpu.data 465623746 # number of WriteReq miss cycles 868system.cpu.dcache.WriteReq_miss_latency::total 465623746 # number of WriteReq miss cycles 869system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 142500 # number of LoadLockedReq miss cycles 870system.cpu.dcache.LoadLockedReq_miss_latency::total 142500 # number of LoadLockedReq miss cycles 871system.cpu.dcache.demand_miss_latency::cpu.data 587486473 # number of demand (read+write) miss cycles 872system.cpu.dcache.demand_miss_latency::total 587486473 # number of demand (read+write) miss cycles 873system.cpu.dcache.overall_miss_latency::cpu.data 587486473 # number of overall miss cycles 874system.cpu.dcache.overall_miss_latency::total 587486473 # number of overall miss cycles 875system.cpu.dcache.ReadReq_accesses::cpu.data 34386613 # number of ReadReq accesses(hits+misses) 876system.cpu.dcache.ReadReq_accesses::total 34386613 # number of ReadReq accesses(hits+misses) 877system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) 878system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) 879system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22476 # number of LoadLockedReq accesses(hits+misses) 880system.cpu.dcache.LoadLockedReq_accesses::total 22476 # number of LoadLockedReq accesses(hits+misses) 881system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) 882system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) 883system.cpu.dcache.demand_accesses::cpu.data 46750900 # number of demand (read+write) accesses 884system.cpu.dcache.demand_accesses::total 46750900 # number of demand (read+write) accesses 885system.cpu.dcache.overall_accesses::cpu.data 46750900 # number of overall (read+write) accesses 886system.cpu.dcache.overall_accesses::total 46750900 # number of overall (read+write) accesses 887system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000055 # miss rate for ReadReq accesses 888system.cpu.dcache.ReadReq_miss_rate::total 0.000055 # miss rate for ReadReq accesses 889system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000625 # miss rate for WriteReq accesses 890system.cpu.dcache.WriteReq_miss_rate::total 0.000625 # miss rate for WriteReq accesses 891system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000089 # miss rate for LoadLockedReq accesses 892system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000089 # miss rate for LoadLockedReq accesses 893system.cpu.dcache.demand_miss_rate::cpu.data 0.000206 # miss rate for demand accesses 894system.cpu.dcache.demand_miss_rate::total 0.000206 # miss rate for demand accesses 895system.cpu.dcache.overall_miss_rate::cpu.data 0.000206 # miss rate for overall accesses 896system.cpu.dcache.overall_miss_rate::total 0.000206 # miss rate for overall accesses 897system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64070.834385 # average ReadReq miss latency 898system.cpu.dcache.ReadReq_avg_miss_latency::total 64070.834385 # average ReadReq miss latency 899system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60290.527774 # average WriteReq miss latency 900system.cpu.dcache.WriteReq_avg_miss_latency::total 60290.527774 # average WriteReq miss latency 901system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71250 # average LoadLockedReq miss latency 902system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71250 # average LoadLockedReq miss latency 903system.cpu.dcache.demand_avg_miss_latency::cpu.data 61037.555636 # average overall miss latency 904system.cpu.dcache.demand_avg_miss_latency::total 61037.555636 # average overall miss latency 905system.cpu.dcache.overall_avg_miss_latency::cpu.data 61037.555636 # average overall miss latency 906system.cpu.dcache.overall_avg_miss_latency::total 61037.555636 # average overall miss latency 907system.cpu.dcache.blocked_cycles::no_mshrs 592 # number of cycles access was blocked 908system.cpu.dcache.blocked_cycles::no_targets 314 # number of cycles access was blocked 909system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked 910system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked 911system.cpu.dcache.avg_blocked_cycles::no_mshrs 53.818182 # average number of cycles each access was blocked 912system.cpu.dcache.avg_blocked_cycles::no_targets 78.500000 # average number of cycles each access was blocked 913system.cpu.dcache.fast_writes 0 # number of fast writes performed 914system.cpu.dcache.cache_copies 0 # number of cache copies performed 915system.cpu.dcache.writebacks::writebacks 18 # number of writebacks 916system.cpu.dcache.writebacks::total 18 # number of writebacks 917system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1128 # number of ReadReq MSHR hits 918system.cpu.dcache.ReadReq_mshr_hits::total 1128 # number of ReadReq MSHR hits 919system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6645 # number of WriteReq MSHR hits 920system.cpu.dcache.WriteReq_mshr_hits::total 6645 # number of WriteReq MSHR hits 921system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 922system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits 923system.cpu.dcache.demand_mshr_hits::cpu.data 7773 # number of demand (read+write) MSHR hits 924system.cpu.dcache.demand_mshr_hits::total 7773 # number of demand (read+write) MSHR hits 925system.cpu.dcache.overall_mshr_hits::cpu.data 7773 # number of overall MSHR hits 926system.cpu.dcache.overall_mshr_hits::total 7773 # number of overall MSHR hits 927system.cpu.dcache.ReadReq_mshr_misses::cpu.data 774 # number of ReadReq MSHR misses 928system.cpu.dcache.ReadReq_mshr_misses::total 774 # number of ReadReq MSHR misses 929system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1078 # number of WriteReq MSHR misses 930system.cpu.dcache.WriteReq_mshr_misses::total 1078 # number of WriteReq MSHR misses 931system.cpu.dcache.demand_mshr_misses::cpu.data 1852 # number of demand (read+write) MSHR misses 932system.cpu.dcache.demand_mshr_misses::total 1852 # number of demand (read+write) MSHR misses 933system.cpu.dcache.overall_mshr_misses::cpu.data 1852 # number of overall MSHR misses 934system.cpu.dcache.overall_mshr_misses::total 1852 # number of overall MSHR misses 935system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 53113761 # number of ReadReq MSHR miss cycles 936system.cpu.dcache.ReadReq_mshr_miss_latency::total 53113761 # number of ReadReq MSHR miss cycles 937system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73393498 # number of WriteReq MSHR miss cycles 938system.cpu.dcache.WriteReq_mshr_miss_latency::total 73393498 # number of WriteReq MSHR miss cycles 939system.cpu.dcache.demand_mshr_miss_latency::cpu.data 126507259 # number of demand (read+write) MSHR miss cycles 940system.cpu.dcache.demand_mshr_miss_latency::total 126507259 # number of demand (read+write) MSHR miss cycles 941system.cpu.dcache.overall_mshr_miss_latency::cpu.data 126507259 # number of overall MSHR miss cycles 942system.cpu.dcache.overall_mshr_miss_latency::total 126507259 # number of overall MSHR miss cycles 943system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses 944system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses 945system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000087 # mshr miss rate for WriteReq accesses 946system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000087 # mshr miss rate for WriteReq accesses 947system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses 948system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses 949system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses 950system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses 951system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68622.430233 # average ReadReq mshr miss latency 952system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68622.430233 # average ReadReq mshr miss latency 953system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68083.022263 # average WriteReq mshr miss latency 954system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68083.022263 # average WriteReq mshr miss latency 955system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68308.455184 # average overall mshr miss latency 956system.cpu.dcache.demand_avg_mshr_miss_latency::total 68308.455184 # average overall mshr miss latency 957system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68308.455184 # average overall mshr miss latency 958system.cpu.dcache.overall_avg_mshr_miss_latency::total 68308.455184 # average overall mshr miss latency 959system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 960 961---------- End Simulation Statistics ---------- 962