config.ini revision 8150
1[root] 2type=Root 3children=system 4time_sync_enable=false 5time_sync_period=100000000000 6time_sync_spin_threshold=100000000 7 8[system] 9type=System 10children=cpu membus physmem 11mem_mode=atomic 12physmem=system.physmem 13work_begin_ckpt_count=0 14work_begin_cpu_id_exit=-1 15work_begin_exit_count=0 16work_cpus_ckpt_count=0 17work_end_ckpt_count=0 18work_end_exit_count=0 19work_item_id=-1 20 21[system.cpu] 22type=DerivO3CPU 23children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload 24BTBEntries=4096 25BTBTagSize=16 26LFSTSize=1024 27LQEntries=32 28RASSize=16 29SQEntries=32 30SSITSize=1024 31activity=0 32backComSize=5 33cachePorts=200 34checker=Null 35choiceCtrBits=2 36choicePredictorSize=8192 37clock=500 38commitToDecodeDelay=1 39commitToFetchDelay=1 40commitToIEWDelay=1 41commitToRenameDelay=1 42commitWidth=8 43cpu_id=0 44decodeToFetchDelay=1 45decodeToRenameDelay=1 46decodeWidth=8 47defer_registration=false 48dispatchWidth=8 49do_checkpoint_insts=true 50do_statistics_insts=true 51dtb=system.cpu.dtb 52fetchToDecodeDelay=1 53fetchTrapLatency=1 54fetchWidth=8 55forwardComSize=5 56fuPool=system.cpu.fuPool 57function_trace=false 58function_trace_start=0 59globalCtrBits=2 60globalHistoryBits=13 61globalPredictorSize=8192 62iewToCommitDelay=1 63iewToDecodeDelay=1 64iewToFetchDelay=1 65iewToRenameDelay=1 66instShiftAmt=2 67issueToExecuteDelay=1 68issueWidth=8 69itb=system.cpu.itb 70localCtrBits=2 71localHistoryBits=11 72localHistoryTableSize=2048 73localPredictorSize=2048 74max_insts_all_threads=0 75max_insts_any_thread=0 76max_loads_all_threads=0 77max_loads_any_thread=0 78numIQEntries=64 79numPhysFloatRegs=256 80numPhysIntRegs=256 81numROBEntries=192 82numRobs=1 83numThreads=1 84phase=0 85predType=tournament 86progress_interval=0 87renameToDecodeDelay=1 88renameToFetchDelay=1 89renameToIEWDelay=2 90renameToROBDelay=1 91renameWidth=8 92smtCommitPolicy=RoundRobin 93smtFetchPolicy=SingleThread 94smtIQPolicy=Partitioned 95smtIQThreshold=100 96smtLSQPolicy=Partitioned 97smtLSQThreshold=100 98smtNumFetchingThreads=1 99smtROBPolicy=Partitioned 100smtROBThreshold=100 101squashWidth=8 102system=system 103tracer=system.cpu.tracer 104trapLatency=13 105wbDepth=1 106wbWidth=8 107workload=system.cpu.workload 108dcache_port=system.cpu.dcache.cpu_side 109icache_port=system.cpu.icache.cpu_side 110 111[system.cpu.dcache] 112type=BaseCache 113addr_range=0:18446744073709551615 114assoc=2 115block_size=64 116forward_snoops=true 117hash_delay=1 118is_top_level=true 119latency=1000 120max_miss_count=0 121mshrs=10 122num_cpus=1 123prefetch_data_accesses_only=false 124prefetch_degree=1 125prefetch_latency=10000 126prefetch_on_access=false 127prefetch_past_page=false 128prefetch_policy=none 129prefetch_serial_squash=false 130prefetch_use_cpu_id=true 131prefetcher_size=100 132prioritizeRequests=false 133repl=Null 134size=262144 135subblock_size=0 136tgts_per_mshr=20 137trace_addr=0 138two_queue=false 139write_buffers=8 140cpu_side=system.cpu.dcache_port 141mem_side=system.cpu.toL2Bus.port[1] 142 143[system.cpu.dtb] 144type=ArmTLB 145size=64 146 147[system.cpu.fuPool] 148type=FUPool 149children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 150FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 151 152[system.cpu.fuPool.FUList0] 153type=FUDesc 154children=opList 155count=6 156opList=system.cpu.fuPool.FUList0.opList 157 158[system.cpu.fuPool.FUList0.opList] 159type=OpDesc 160issueLat=1 161opClass=IntAlu 162opLat=1 163 164[system.cpu.fuPool.FUList1] 165type=FUDesc 166children=opList0 opList1 167count=2 168opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 169 170[system.cpu.fuPool.FUList1.opList0] 171type=OpDesc 172issueLat=1 173opClass=IntMult 174opLat=3 175 176[system.cpu.fuPool.FUList1.opList1] 177type=OpDesc 178issueLat=19 179opClass=IntDiv 180opLat=20 181 182[system.cpu.fuPool.FUList2] 183type=FUDesc 184children=opList0 opList1 opList2 185count=4 186opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 187 188[system.cpu.fuPool.FUList2.opList0] 189type=OpDesc 190issueLat=1 191opClass=FloatAdd 192opLat=2 193 194[system.cpu.fuPool.FUList2.opList1] 195type=OpDesc 196issueLat=1 197opClass=FloatCmp 198opLat=2 199 200[system.cpu.fuPool.FUList2.opList2] 201type=OpDesc 202issueLat=1 203opClass=FloatCvt 204opLat=2 205 206[system.cpu.fuPool.FUList3] 207type=FUDesc 208children=opList0 opList1 opList2 209count=2 210opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 211 212[system.cpu.fuPool.FUList3.opList0] 213type=OpDesc 214issueLat=1 215opClass=FloatMult 216opLat=4 217 218[system.cpu.fuPool.FUList3.opList1] 219type=OpDesc 220issueLat=12 221opClass=FloatDiv 222opLat=12 223 224[system.cpu.fuPool.FUList3.opList2] 225type=OpDesc 226issueLat=24 227opClass=FloatSqrt 228opLat=24 229 230[system.cpu.fuPool.FUList4] 231type=FUDesc 232children=opList 233count=0 234opList=system.cpu.fuPool.FUList4.opList 235 236[system.cpu.fuPool.FUList4.opList] 237type=OpDesc 238issueLat=1 239opClass=MemRead 240opLat=1 241 242[system.cpu.fuPool.FUList5] 243type=FUDesc 244children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 245count=4 246opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 247 248[system.cpu.fuPool.FUList5.opList00] 249type=OpDesc 250issueLat=1 251opClass=SimdAdd 252opLat=1 253 254[system.cpu.fuPool.FUList5.opList01] 255type=OpDesc 256issueLat=1 257opClass=SimdAddAcc 258opLat=1 259 260[system.cpu.fuPool.FUList5.opList02] 261type=OpDesc 262issueLat=1 263opClass=SimdAlu 264opLat=1 265 266[system.cpu.fuPool.FUList5.opList03] 267type=OpDesc 268issueLat=1 269opClass=SimdCmp 270opLat=1 271 272[system.cpu.fuPool.FUList5.opList04] 273type=OpDesc 274issueLat=1 275opClass=SimdCvt 276opLat=1 277 278[system.cpu.fuPool.FUList5.opList05] 279type=OpDesc 280issueLat=1 281opClass=SimdMisc 282opLat=1 283 284[system.cpu.fuPool.FUList5.opList06] 285type=OpDesc 286issueLat=1 287opClass=SimdMult 288opLat=1 289 290[system.cpu.fuPool.FUList5.opList07] 291type=OpDesc 292issueLat=1 293opClass=SimdMultAcc 294opLat=1 295 296[system.cpu.fuPool.FUList5.opList08] 297type=OpDesc 298issueLat=1 299opClass=SimdShift 300opLat=1 301 302[system.cpu.fuPool.FUList5.opList09] 303type=OpDesc 304issueLat=1 305opClass=SimdShiftAcc 306opLat=1 307 308[system.cpu.fuPool.FUList5.opList10] 309type=OpDesc 310issueLat=1 311opClass=SimdSqrt 312opLat=1 313 314[system.cpu.fuPool.FUList5.opList11] 315type=OpDesc 316issueLat=1 317opClass=SimdFloatAdd 318opLat=1 319 320[system.cpu.fuPool.FUList5.opList12] 321type=OpDesc 322issueLat=1 323opClass=SimdFloatAlu 324opLat=1 325 326[system.cpu.fuPool.FUList5.opList13] 327type=OpDesc 328issueLat=1 329opClass=SimdFloatCmp 330opLat=1 331 332[system.cpu.fuPool.FUList5.opList14] 333type=OpDesc 334issueLat=1 335opClass=SimdFloatCvt 336opLat=1 337 338[system.cpu.fuPool.FUList5.opList15] 339type=OpDesc 340issueLat=1 341opClass=SimdFloatDiv 342opLat=1 343 344[system.cpu.fuPool.FUList5.opList16] 345type=OpDesc 346issueLat=1 347opClass=SimdFloatMisc 348opLat=1 349 350[system.cpu.fuPool.FUList5.opList17] 351type=OpDesc 352issueLat=1 353opClass=SimdFloatMult 354opLat=1 355 356[system.cpu.fuPool.FUList5.opList18] 357type=OpDesc 358issueLat=1 359opClass=SimdFloatMultAcc 360opLat=1 361 362[system.cpu.fuPool.FUList5.opList19] 363type=OpDesc 364issueLat=1 365opClass=SimdFloatSqrt 366opLat=1 367 368[system.cpu.fuPool.FUList6] 369type=FUDesc 370children=opList 371count=0 372opList=system.cpu.fuPool.FUList6.opList 373 374[system.cpu.fuPool.FUList6.opList] 375type=OpDesc 376issueLat=1 377opClass=MemWrite 378opLat=1 379 380[system.cpu.fuPool.FUList7] 381type=FUDesc 382children=opList0 opList1 383count=4 384opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 385 386[system.cpu.fuPool.FUList7.opList0] 387type=OpDesc 388issueLat=1 389opClass=MemRead 390opLat=1 391 392[system.cpu.fuPool.FUList7.opList1] 393type=OpDesc 394issueLat=1 395opClass=MemWrite 396opLat=1 397 398[system.cpu.fuPool.FUList8] 399type=FUDesc 400children=opList 401count=1 402opList=system.cpu.fuPool.FUList8.opList 403 404[system.cpu.fuPool.FUList8.opList] 405type=OpDesc 406issueLat=3 407opClass=IprAccess 408opLat=3 409 410[system.cpu.icache] 411type=BaseCache 412addr_range=0:18446744073709551615 413assoc=2 414block_size=64 415forward_snoops=true 416hash_delay=1 417is_top_level=true 418latency=1000 419max_miss_count=0 420mshrs=10 421num_cpus=1 422prefetch_data_accesses_only=false 423prefetch_degree=1 424prefetch_latency=10000 425prefetch_on_access=false 426prefetch_past_page=false 427prefetch_policy=none 428prefetch_serial_squash=false 429prefetch_use_cpu_id=true 430prefetcher_size=100 431prioritizeRequests=false 432repl=Null 433size=131072 434subblock_size=0 435tgts_per_mshr=20 436trace_addr=0 437two_queue=false 438write_buffers=8 439cpu_side=system.cpu.icache_port 440mem_side=system.cpu.toL2Bus.port[0] 441 442[system.cpu.itb] 443type=ArmTLB 444size=64 445 446[system.cpu.l2cache] 447type=BaseCache 448addr_range=0:18446744073709551615 449assoc=2 450block_size=64 451forward_snoops=true 452hash_delay=1 453is_top_level=false 454latency=1000 455max_miss_count=0 456mshrs=10 457num_cpus=1 458prefetch_data_accesses_only=false 459prefetch_degree=1 460prefetch_latency=10000 461prefetch_on_access=false 462prefetch_past_page=false 463prefetch_policy=none 464prefetch_serial_squash=false 465prefetch_use_cpu_id=true 466prefetcher_size=100 467prioritizeRequests=false 468repl=Null 469size=2097152 470subblock_size=0 471tgts_per_mshr=5 472trace_addr=0 473two_queue=false 474write_buffers=8 475cpu_side=system.cpu.toL2Bus.port[2] 476mem_side=system.membus.port[1] 477 478[system.cpu.toL2Bus] 479type=Bus 480block_size=64 481bus_id=0 482clock=1000 483header_cycles=1 484use_default_range=false 485width=64 486port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side 487 488[system.cpu.tracer] 489type=ExeTracer 490 491[system.cpu.workload] 492type=LiveProcess 493cmd=twolf smred 494cwd=build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing 495egid=100 496env= 497errout=cerr 498euid=100 499executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/twolf 500gid=100 501input=cin 502max_stack_size=67108864 503output=cout 504pid=100 505ppid=99 506simpoint=0 507system=system 508uid=100 509 510[system.membus] 511type=Bus 512block_size=64 513bus_id=0 514clock=1000 515header_cycles=1 516use_default_range=false 517width=64 518port=system.physmem.port[0] system.cpu.l2cache.mem_side 519 520[system.physmem] 521type=PhysicalMemory 522file= 523latency=30000 524latency_var=0 525null=false 526range=0:134217727 527zero=false 528port=system.membus.port[0] 529 530